2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org>
3 * Copyright (c) 2000, Michael Smith <msmith@freebsd.org>
4 * Copyright (c) 2000, BSDi
5 * Copyright (c) 2003, Thomas Moestl <tmm@FreeBSD.org>
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice unmodified, this list of conditions, and the following
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD$");
33 #include "opt_ofw_pci.h"
35 #include <sys/param.h>
37 #include <sys/kernel.h>
38 #include <sys/libkern.h>
39 #include <sys/module.h>
40 #include <sys/pciio.h>
42 #include <dev/ofw/ofw_bus.h>
43 #include <dev/ofw/ofw_pci.h>
44 #include <dev/ofw/openfirm.h>
46 #include <machine/bus.h>
48 #include <machine/bus_common.h>
49 #include <machine/iommureg.h>
51 #include <machine/resource.h>
53 #include <dev/pci/pcireg.h>
54 #include <dev/pci/pcivar.h>
55 #include <dev/pci/pci_private.h>
57 #include <sparc64/pci/ofw_pci.h>
62 /* Helper functions */
63 static void ofw_pcibus_setup_device(device_t bridge, uint32_t clock,
64 u_int busno, u_int slot, u_int func);
67 static device_probe_t ofw_pcibus_probe;
68 static device_attach_t ofw_pcibus_attach;
69 static pci_assign_interrupt_t ofw_pcibus_assign_interrupt;
70 static ofw_bus_get_devinfo_t ofw_pcibus_get_devinfo;
71 static bus_child_pnpinfo_str_t ofw_pcibus_pnpinfo_str;
73 static device_method_t ofw_pcibus_methods[] = {
74 /* Device interface */
75 DEVMETHOD(device_probe, ofw_pcibus_probe),
76 DEVMETHOD(device_attach, ofw_pcibus_attach),
79 DEVMETHOD(bus_child_pnpinfo_str, ofw_pcibus_pnpinfo_str),
82 DEVMETHOD(pci_assign_interrupt, ofw_pcibus_assign_interrupt),
84 /* ofw_bus interface */
85 DEVMETHOD(ofw_bus_get_devinfo, ofw_pcibus_get_devinfo),
86 DEVMETHOD(ofw_bus_get_compat, ofw_bus_gen_get_compat),
87 DEVMETHOD(ofw_bus_get_model, ofw_bus_gen_get_model),
88 DEVMETHOD(ofw_bus_get_name, ofw_bus_gen_get_name),
89 DEVMETHOD(ofw_bus_get_node, ofw_bus_gen_get_node),
90 DEVMETHOD(ofw_bus_get_type, ofw_bus_gen_get_type),
95 struct ofw_pcibus_devinfo {
96 struct pci_devinfo opd_dinfo;
97 struct ofw_bus_devinfo opd_obdinfo;
100 static devclass_t pci_devclass;
102 DEFINE_CLASS_1(pci, ofw_pcibus_driver, ofw_pcibus_methods, 1 /* no softc */,
104 DRIVER_MODULE(ofw_pcibus, pcib, ofw_pcibus_driver, pci_devclass, 0, 0);
105 MODULE_VERSION(ofw_pcibus, 1);
106 MODULE_DEPEND(ofw_pcibus, pci, 1, 1, 1);
109 ofw_pcibus_probe(device_t dev)
112 if (ofw_bus_get_node(dev) == 0)
114 device_set_desc(dev, "OFW PCI bus");
120 * Perform miscellaneous setups the firmware usually does not do for us.
123 ofw_pcibus_setup_device(device_t bridge, uint32_t clock, u_int busno,
124 u_int slot, u_int func)
130 * Initialize the latency timer register for busmaster devices to
131 * work properly. This is another task which the firmware doesn't
132 * always perform. The Min_Gnt register can be used to compute its
133 * recommended value: it contains the desired latency in units of
134 * 1/4 us assuming a clock rate of 33MHz. To calculate the correct
135 * latency timer value, the clock frequency of the bus (defaulting
136 * to 33MHz) should be used and no wait states assumed.
137 * For bridges, we additionally set up the bridge control and the
138 * secondary latency registers.
140 if ((PCIB_READ_CONFIG(bridge, busno, slot, func, PCIR_HDRTYPE, 1) &
141 PCIM_HDRTYPE) == PCIM_HDRTYPE_BRIDGE) {
142 reg = PCIB_READ_CONFIG(bridge, busno, slot, func,
143 PCIR_BRIDGECTL_1, 1);
144 reg |= PCIB_BCR_MASTER_ABORT_MODE | PCIB_BCR_SERR_ENABLE |
145 PCIB_BCR_PERR_ENABLE;
147 device_printf(bridge,
148 "bridge %d/%d/%d: control 0x%x -> 0x%x\n",
149 busno, slot, func, PCIB_READ_CONFIG(bridge, busno, slot,
150 func, PCIR_BRIDGECTL_1, 1), reg);
151 #endif /* OFW_PCI_DEBUG */
152 PCIB_WRITE_CONFIG(bridge, busno, slot, func, PCIR_BRIDGECTL_1,
155 reg = OFW_PCI_LATENCY;
157 device_printf(bridge,
158 "bridge %d/%d/%d: latency timer %d -> %d\n",
159 busno, slot, func, PCIB_READ_CONFIG(bridge, busno, slot,
160 func, PCIR_SECLAT_1, 1), reg);
161 #endif /* OFW_PCI_DEBUG */
162 PCIB_WRITE_CONFIG(bridge, busno, slot, func, PCIR_SECLAT_1,
165 reg = PCIB_READ_CONFIG(bridge, busno, slot, func,
178 reg = OFW_PCI_LATENCY;
181 device_printf(bridge, "device %d/%d/%d: latency timer %d -> %d\n",
182 busno, slot, func, PCIB_READ_CONFIG(bridge, busno, slot, func,
183 PCIR_LATTIMER, 1), reg);
184 #endif /* OFW_PCI_DEBUG */
185 PCIB_WRITE_CONFIG(bridge, busno, slot, func, PCIR_LATTIMER, reg, 1);
188 * Compute a value to write into the cache line size register.
189 * The role of the streaming cache is unclear in write invalidate
190 * transfers, so it is made sure that it's line size is always
191 * reached. Generally, the cache line size is fixed at 64 bytes
192 * by Fireplane/Safari, JBus and UPA.
194 PCIB_WRITE_CONFIG(bridge, busno, slot, func, PCIR_CACHELNSZ,
195 STRBUF_LINESZ / sizeof(uint32_t), 1);
199 * The preset in the intline register is usually wrong. Reset
200 * it to 255, so that the PCI code will reroute the interrupt if
203 PCIB_WRITE_CONFIG(bridge, busno, slot, func, PCIR_INTLINE,
208 ofw_pcibus_attach(device_t dev)
211 struct ofw_pci_register pcir;
212 struct ofw_pcibus_devinfo *dinfo;
213 phandle_t node, child;
215 u_int busno, domain, func, slot;
217 pcib = device_get_parent(dev);
218 domain = pcib_get_domain(dev);
219 busno = pcib_get_bus(dev);
221 device_printf(dev, "domain=%d, physical bus=%d\n",
223 node = ofw_bus_get_node(dev);
226 /* Add the PCI side of the HOST-PCI bridge itself to the bus. */
227 if (strcmp(device_get_name(device_get_parent(pcib)), "nexus") == 0 &&
228 (dinfo = (struct ofw_pcibus_devinfo *)pci_read_device(pcib,
229 domain, busno, 0, 0, sizeof(*dinfo))) != NULL) {
230 if (ofw_bus_gen_setup_devinfo(&dinfo->opd_obdinfo, node) != 0)
231 pci_freecfg((struct pci_devinfo *)dinfo);
233 pci_add_child(dev, (struct pci_devinfo *)dinfo);
237 if (OF_getprop(ofw_bus_get_node(pcib), "clock-frequency", &clock,
238 sizeof(clock)) == -1)
240 for (child = OF_child(node); child != 0; child = OF_peer(child)) {
241 if (OF_getprop(child, "reg", &pcir, sizeof(pcir)) == -1)
243 slot = OFW_PCI_PHYS_HI_DEVICE(pcir.phys_hi);
244 func = OFW_PCI_PHYS_HI_FUNCTION(pcir.phys_hi);
245 /* Some OFW device trees contain dupes. */
246 if (pci_find_dbsf(domain, busno, slot, func) != NULL)
248 ofw_pcibus_setup_device(pcib, clock, busno, slot, func);
249 dinfo = (struct ofw_pcibus_devinfo *)pci_read_device(pcib,
250 domain, busno, slot, func, sizeof(*dinfo));
253 if (ofw_bus_gen_setup_devinfo(&dinfo->opd_obdinfo, child) !=
255 pci_freecfg((struct pci_devinfo *)dinfo);
258 pci_add_child(dev, (struct pci_devinfo *)dinfo);
261 return (bus_generic_attach(dev));
265 ofw_pcibus_assign_interrupt(device_t dev, device_t child)
270 isz = OF_getprop(ofw_bus_get_node(child), "interrupts", &intr,
272 if (isz != sizeof(intr)) {
273 /* No property; our best guess is the intpin. */
274 intr = pci_get_intpin(child);
276 } else if (intr >= 255) {
278 * A fully specified interrupt (including IGN), as present on
279 * SPARCengine Ultra AX and E450. Extract the INO and return
282 return (INTINO(intr));
286 * If we got intr from a property, it may or may not be an intpin.
287 * For on-board devices, it frequently is not, and is completely out
288 * of the valid intpin range. For PCI slots, it hopefully is,
289 * otherwise we will have trouble interfacing with non-OFW buses
291 * Since we cannot tell which it is without violating layering, we
292 * will always use the route_interrupt method, and treat exceptions
293 * on the level they become apparent.
295 return (PCIB_ROUTE_INTERRUPT(device_get_parent(dev), child, intr));
298 static const struct ofw_bus_devinfo *
299 ofw_pcibus_get_devinfo(device_t bus, device_t dev)
301 struct ofw_pcibus_devinfo *dinfo;
303 dinfo = device_get_ivars(dev);
304 return (&dinfo->opd_obdinfo);
308 ofw_pcibus_pnpinfo_str(device_t dev, device_t child, char *buf,
312 pci_child_pnpinfo_str_method(dev, child, buf, buflen);
313 if (ofw_bus_get_node(child) != -1) {
314 strlcat(buf, " ", buflen); /* Separate info. */
315 ofw_bus_gen_child_pnpinfo_str(dev, child, buf, buflen);