lib/libpmc/libpmc.c

   1 /*-
   2  * Copyright (c) 2003-2008 Joseph Koshy
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  * 1. Redistributions of source code must retain the above copyright
   9  *    notice, this list of conditions and the following disclaimer.
  10  * 2. Redistributions in binary form must reproduce the above copyright
  11  *    notice, this list of conditions and the following disclaimer in the
  12  *    documentation and/or other materials provided with the distribution.
  13  *
  14  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  15  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  16  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  17  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  18  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  19  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  20  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  21  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  22  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  23  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  24  * SUCH DAMAGE.
  25  */
  26
  27 #include <sys/cdefs.h>
  28 __FBSDID("$FreeBSD$");
  29
  30 #include <sys/types.h>
  31 #include <sys/module.h>
  32 #include <sys/pmc.h>
  33 #include <sys/syscall.h>
  34
  35 #include <ctype.h>
  36 #include <errno.h>
  37 #include <fcntl.h>
  38 #include <pmc.h>
  39 #include <stdio.h>
  40 #include <stdlib.h>
  41 #include <string.h>
  42 #include <strings.h>
  43 #include <unistd.h>
  44
  45 #include "libpmcinternal.h"
  46
  47 /* Function prototypes */
  48 #if defined(__i386__)
  49 static int k7_allocate_pmc(enum pmc_event _pe, char *_ctrspec,
  50     struct pmc_op_pmcallocate *_pmc_config);
  51 #endif
  52 #if defined(__amd64__) || defined(__i386__)
  53 static int iaf_allocate_pmc(enum pmc_event _pe, char *_ctrspec,
  54     struct pmc_op_pmcallocate *_pmc_config);
  55 static int iap_allocate_pmc(enum pmc_event _pe, char *_ctrspec,
  56     struct pmc_op_pmcallocate *_pmc_config);
  57 static int ucf_allocate_pmc(enum pmc_event _pe, char *_ctrspec,
  58     struct pmc_op_pmcallocate *_pmc_config);
  59 static int ucp_allocate_pmc(enum pmc_event _pe, char *_ctrspec,
  60     struct pmc_op_pmcallocate *_pmc_config);
  61 static int k8_allocate_pmc(enum pmc_event _pe, char *_ctrspec,
  62     struct pmc_op_pmcallocate *_pmc_config);
  63 static int p4_allocate_pmc(enum pmc_event _pe, char *_ctrspec,
  64     struct pmc_op_pmcallocate *_pmc_config);
  65 #endif
  66 #if defined(__i386__)
  67 static int p5_allocate_pmc(enum pmc_event _pe, char *_ctrspec,
  68     struct pmc_op_pmcallocate *_pmc_config);
  69 static int p6_allocate_pmc(enum pmc_event _pe, char *_ctrspec,
  70     struct pmc_op_pmcallocate *_pmc_config);
  71 #endif
  72 #if defined(__amd64__) || defined(__i386__)
  73 static int tsc_allocate_pmc(enum pmc_event _pe, char *_ctrspec,
  74     struct pmc_op_pmcallocate *_pmc_config);
  75 #endif
  76
  77 #define PMC_CALL(cmd, params)                           \
  78         syscall(pmc_syscall, PMC_OP_##cmd, (params))
  79
  80 /*
  81  * Event aliases provide a way for the user to ask for generic events
  82  * like "cache-misses", or "instructions-retired".  These aliases are
  83  * mapped to the appropriate canonical event descriptions using a
  84  * lookup table.
  85  */
  86 struct pmc_event_alias {
  87         const char      *pm_alias;
  88         const char      *pm_spec;
  89 };
  90
  91 static const struct pmc_event_alias *pmc_mdep_event_aliases;
  92
  93 /*
  94  * The pmc_event_descr structure maps symbolic names known to the user
  95  * to integer codes used by the PMC KLD.
  96  */
  97 struct pmc_event_descr {
  98         const char      *pm_ev_name;
  99         enum pmc_event  pm_ev_code;
 100 };
 101
 102 /*
 103  * The pmc_class_descr structure maps class name prefixes for
 104  * event names to event tables and other PMC class data.
 105  */
 106 struct pmc_class_descr {
 107         const char      *pm_evc_name;
 108         size_t          pm_evc_name_size;
 109         enum pmc_class  pm_evc_class;
 110         const struct pmc_event_descr *pm_evc_event_table;
 111         size_t          pm_evc_event_table_size;
 112         int             (*pm_evc_allocate_pmc)(enum pmc_event _pe,
 113                             char *_ctrspec, struct pmc_op_pmcallocate *_pa);
 114 };
 115
 116 #define PMC_TABLE_SIZE(N)       (sizeof(N)/sizeof(N[0]))
 117 #define PMC_EVENT_TABLE_SIZE(N) PMC_TABLE_SIZE(N##_event_table)
 118
 119 #undef  __PMC_EV
 120 #define __PMC_EV(C,N) { #N, PMC_EV_ ## C ## _ ## N },
 121
 122 /*
 123  * PMC_CLASSDEP_TABLE(NAME, CLASS)
 124  *
 125  * Define a table mapping event names and aliases to HWPMC event IDs.
 126  */
 127 #define PMC_CLASSDEP_TABLE(N, C)                                \
 128         static const struct pmc_event_descr N##_event_table[] = \
 129         {                                                       \
 130                 __PMC_EV_##C()                                  \
 131         }
 132
 133 PMC_CLASSDEP_TABLE(iaf, IAF);
 134 PMC_CLASSDEP_TABLE(k7, K7);
 135 PMC_CLASSDEP_TABLE(k8, K8);
 136 PMC_CLASSDEP_TABLE(p4, P4);
 137 PMC_CLASSDEP_TABLE(p5, P5);
 138 PMC_CLASSDEP_TABLE(p6, P6);
 139 PMC_CLASSDEP_TABLE(ucf, UCF);
 140
 141 #undef  __PMC_EV_ALIAS
 142 #define __PMC_EV_ALIAS(N,CODE)  { N, PMC_EV_##CODE },
 143
 144 static const struct pmc_event_descr atom_event_table[] =
 145 {
 146         __PMC_EV_ALIAS_ATOM()
 147 };
 148
 149 static const struct pmc_event_descr core_event_table[] =
 150 {
 151         __PMC_EV_ALIAS_CORE()
 152 };
 153
 154
 155 static const struct pmc_event_descr core2_event_table[] =
 156 {
 157         __PMC_EV_ALIAS_CORE2()
 158 };
 159
 160 static const struct pmc_event_descr corei7_event_table[] =
 161 {
 162         __PMC_EV_ALIAS_COREI7()
 163 };
 164
 165 static const struct pmc_event_descr westmere_event_table[] =
 166 {
 167         __PMC_EV_ALIAS_WESTMERE()
 168 };
 169
 170 static const struct pmc_event_descr corei7uc_event_table[] =
 171 {
 172         __PMC_EV_ALIAS_COREI7UC()
 173 };
 174
 175 static const struct pmc_event_descr westmereuc_event_table[] =
 176 {
 177         __PMC_EV_ALIAS_WESTMEREUC()
 178 };
 179
 180 /*
 181  * PMC_MDEP_TABLE(NAME, PRIMARYCLASS, ADDITIONAL_CLASSES...)
 182  *
 183  * Map a CPU to the PMC classes it supports.
 184  */
 185 #define PMC_MDEP_TABLE(N,C,...)                         \
 186         static const enum pmc_class N##_pmc_classes[] = {       \
 187                 PMC_CLASS_##C, __VA_ARGS__                      \
 188         }
 189
 190 PMC_MDEP_TABLE(atom, IAP, PMC_CLASS_IAF, PMC_CLASS_TSC);
 191 PMC_MDEP_TABLE(core, IAP, PMC_CLASS_TSC);
 192 PMC_MDEP_TABLE(core2, IAP, PMC_CLASS_IAF, PMC_CLASS_TSC);
 193 PMC_MDEP_TABLE(corei7, IAP, PMC_CLASS_IAF, PMC_CLASS_TSC, PMC_CLASS_UCF, PMC_CLASS_UCP);
 194 PMC_MDEP_TABLE(westmere, IAP, PMC_CLASS_IAF, PMC_CLASS_TSC, PMC_CLASS_UCF, PMC_CLASS_UCP);
 195 PMC_MDEP_TABLE(k7, K7, PMC_CLASS_TSC);
 196 PMC_MDEP_TABLE(k8, K8, PMC_CLASS_TSC);
 197 PMC_MDEP_TABLE(p4, P4, PMC_CLASS_TSC);
 198 PMC_MDEP_TABLE(p5, P5, PMC_CLASS_TSC);
 199 PMC_MDEP_TABLE(p6, P6, PMC_CLASS_TSC);
 200
 201 static const struct pmc_event_descr tsc_event_table[] =
 202 {
 203         __PMC_EV_TSC()
 204 };
 205
 206 #undef  PMC_CLASS_TABLE_DESC
 207 #define PMC_CLASS_TABLE_DESC(NAME, CLASS, EVENTS, ALLOCATOR)    \
 208 static const struct pmc_class_descr NAME##_class_table_descr =  \
 209         {                                                       \
 210                 .pm_evc_name  = #CLASS "-",                     \
 211                 .pm_evc_name_size = sizeof(#CLASS "-") - 1,     \
 212                 .pm_evc_class = PMC_CLASS_##CLASS ,             \
 213                 .pm_evc_event_table = EVENTS##_event_table ,    \
 214                 .pm_evc_event_table_size =                      \
 215                         PMC_EVENT_TABLE_SIZE(EVENTS),           \
 216                 .pm_evc_allocate_pmc = ALLOCATOR##_allocate_pmc \
 217         }
 218
 219 #if     defined(__i386__) || defined(__amd64__)
 220 PMC_CLASS_TABLE_DESC(iaf, IAF, iaf, iaf);
 221 PMC_CLASS_TABLE_DESC(atom, IAP, atom, iap);
 222 PMC_CLASS_TABLE_DESC(core, IAP, core, iap);
 223 PMC_CLASS_TABLE_DESC(core2, IAP, core2, iap);
 224 PMC_CLASS_TABLE_DESC(corei7, IAP, corei7, iap);
 225 PMC_CLASS_TABLE_DESC(westmere, IAP, westmere, iap);
 226 PMC_CLASS_TABLE_DESC(ucf, UCF, ucf, ucf);
 227 PMC_CLASS_TABLE_DESC(corei7uc, UCP, corei7uc, ucp);
 228 PMC_CLASS_TABLE_DESC(westmereuc, UCP, westmereuc, ucp);
 229 #endif
 230 #if     defined(__i386__)
 231 PMC_CLASS_TABLE_DESC(k7, K7, k7, k7);
 232 #endif
 233 #if     defined(__i386__) || defined(__amd64__)
 234 PMC_CLASS_TABLE_DESC(k8, K8, k8, k8);
 235 PMC_CLASS_TABLE_DESC(p4, P4, p4, p4);
 236 #endif
 237 #if     defined(__i386__)
 238 PMC_CLASS_TABLE_DESC(p5, P5, p5, p5);
 239 PMC_CLASS_TABLE_DESC(p6, P6, p6, p6);
 240 #endif
 241 #if     defined(__i386__) || defined(__amd64__)
 242 PMC_CLASS_TABLE_DESC(tsc, TSC, tsc, tsc);
 243 #endif
 244
 245 #undef  PMC_CLASS_TABLE_DESC
 246
 247 static const struct pmc_class_descr **pmc_class_table;
 248 #define PMC_CLASS_TABLE_SIZE    cpu_info.pm_nclass
 249
 250 static const enum pmc_class *pmc_mdep_class_list;
 251 static size_t pmc_mdep_class_list_size;
 252
 253 /*
 254  * Mapping tables, mapping enumeration values to human readable
 255  * strings.
 256  */
 257
 258 static const char * pmc_capability_names[] = {
 259 #undef  __PMC_CAP
 260 #define __PMC_CAP(N,V,D)        #N ,
 261         __PMC_CAPS()
 262 };
 263
 264 static const char * pmc_class_names[] = {
 265 #undef  __PMC_CLASS
 266 #define __PMC_CLASS(C)  #C ,
 267         __PMC_CLASSES()
 268 };
 269
 270 struct pmc_cputype_map {
 271         enum pmc_class  pm_cputype;
 272         const char      *pm_name;
 273 };
 274
 275 static const struct pmc_cputype_map pmc_cputype_names[] = {
 276 #undef  __PMC_CPU
 277 #define __PMC_CPU(S, V, D) { .pm_cputype = PMC_CPU_##S, .pm_name = #S } ,
 278         __PMC_CPUS()
 279 };
 280
 281 static const char * pmc_disposition_names[] = {
 282 #undef  __PMC_DISP
 283 #define __PMC_DISP(D)   #D ,
 284         __PMC_DISPOSITIONS()
 285 };
 286
 287 static const char * pmc_mode_names[] = {
 288 #undef  __PMC_MODE
 289 #define __PMC_MODE(M,N) #M ,
 290         __PMC_MODES()
 291 };
 292
 293 static const char * pmc_state_names[] = {
 294 #undef  __PMC_STATE
 295 #define __PMC_STATE(S) #S ,
 296         __PMC_STATES()
 297 };
 298
 299 static int pmc_syscall = -1;            /* filled in by pmc_init() */
 300
 301 static struct pmc_cpuinfo cpu_info;     /* filled in by pmc_init() */
 302
 303 /* Event masks for events */
 304 struct pmc_masks {
 305         const char      *pm_name;
 306         const uint32_t  pm_value;
 307 };
 308 #define PMCMASK(N,V)    { .pm_name = #N, .pm_value = (V) }
 309 #define NULLMASK        { .pm_name = NULL }
 310
 311 #if defined(__amd64__) || defined(__i386__)
 312 static int
 313 pmc_parse_mask(const struct pmc_masks *pmask, char *p, uint32_t *evmask)
 314 {
 315         const struct pmc_masks *pm;
 316         char *q, *r;
 317         int c;
 318
 319         if (pmask == NULL)      /* no mask keywords */
 320                 return (-1);
 321         q = strchr(p, '=');     /* skip '=' */
 322         if (*++q == '\0')       /* no more data */
 323                 return (-1);
 324         c = 0;                  /* count of mask keywords seen */
 325         while ((r = strsep(&q, "+")) != NULL) {
 326                 for (pm = pmask; pm->pm_name && strcasecmp(r, pm->pm_name);
 327                     pm++)
 328                         ;
 329                 if (pm->pm_name == NULL) /* not found */
 330                         return (-1);
 331                 *evmask |= pm->pm_value;
 332                 c++;
 333         }
 334         return (c);
 335 }
 336 #endif
 337
 338 #define KWMATCH(p,kw)           (strcasecmp((p), (kw)) == 0)
 339 #define KWPREFIXMATCH(p,kw)     (strncasecmp((p), (kw), sizeof((kw)) - 1) == 0)
 340 #define EV_ALIAS(N,S)           { .pm_alias = N, .pm_spec = S }
 341
 342 #if defined(__i386__)
 343
 344 /*
 345  * AMD K7 (Athlon) CPUs.
 346  */
 347
 348 static struct pmc_event_alias k7_aliases[] = {
 349         EV_ALIAS("branches",            "k7-retired-branches"),
 350         EV_ALIAS("branch-mispredicts",  "k7-retired-branches-mispredicted"),
 351         EV_ALIAS("cycles",              "tsc"),
 352         EV_ALIAS("dc-misses",           "k7-dc-misses"),
 353         EV_ALIAS("ic-misses",           "k7-ic-misses"),
 354         EV_ALIAS("instructions",        "k7-retired-instructions"),
 355         EV_ALIAS("interrupts",          "k7-hardware-interrupts"),
 356         EV_ALIAS(NULL, NULL)
 357 };
 358
 359 #define K7_KW_COUNT     "count"
 360 #define K7_KW_EDGE      "edge"
 361 #define K7_KW_INV       "inv"
 362 #define K7_KW_OS        "os"
 363 #define K7_KW_UNITMASK  "unitmask"
 364 #define K7_KW_USR       "usr"
 365
 366 static int
 367 k7_allocate_pmc(enum pmc_event pe, char *ctrspec,
 368     struct pmc_op_pmcallocate *pmc_config)
 369 {
 370         char            *e, *p, *q;
 371         int             c, has_unitmask;
 372         uint32_t        count, unitmask;
 373
 374         pmc_config->pm_md.pm_amd.pm_amd_config = 0;
 375         pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE);
 376
 377         if (pe == PMC_EV_K7_DC_REFILLS_FROM_L2 ||
 378             pe == PMC_EV_K7_DC_REFILLS_FROM_SYSTEM ||
 379             pe == PMC_EV_K7_DC_WRITEBACKS) {
 380                 has_unitmask = 1;
 381                 unitmask = AMD_PMC_UNITMASK_MOESI;
 382         } else
 383                 unitmask = has_unitmask = 0;
 384
 385         while ((p = strsep(&ctrspec, ",")) != NULL) {
 386                 if (KWPREFIXMATCH(p, K7_KW_COUNT "=")) {
 387                         q = strchr(p, '=');
 388                         if (*++q == '\0') /* skip '=' */
 389                                 return (-1);
 390
 391                         count = strtol(q, &e, 0);
 392                         if (e == q || *e != '\0')
 393                                 return (-1);
 394
 395                         pmc_config->pm_caps |= PMC_CAP_THRESHOLD;
 396                         pmc_config->pm_md.pm_amd.pm_amd_config |=
 397                             AMD_PMC_TO_COUNTER(count);
 398
 399                 } else if (KWMATCH(p, K7_KW_EDGE)) {
 400                         pmc_config->pm_caps |= PMC_CAP_EDGE;
 401                 } else if (KWMATCH(p, K7_KW_INV)) {
 402                         pmc_config->pm_caps |= PMC_CAP_INVERT;
 403                 } else if (KWMATCH(p, K7_KW_OS)) {
 404                         pmc_config->pm_caps |= PMC_CAP_SYSTEM;
 405                 } else if (KWPREFIXMATCH(p, K7_KW_UNITMASK "=")) {
 406                         if (has_unitmask == 0)
 407                                 return (-1);
 408                         unitmask = 0;
 409                         q = strchr(p, '=');
 410                         if (*++q == '\0') /* skip '=' */
 411                                 return (-1);
 412
 413                         while ((c = tolower(*q++)) != 0)
 414                                 if (c == 'm')
 415                                         unitmask |= AMD_PMC_UNITMASK_M;
 416                                 else if (c == 'o')
 417                                         unitmask |= AMD_PMC_UNITMASK_O;
 418                                 else if (c == 'e')
 419                                         unitmask |= AMD_PMC_UNITMASK_E;
 420                                 else if (c == 's')
 421                                         unitmask |= AMD_PMC_UNITMASK_S;
 422                                 else if (c == 'i')
 423                                         unitmask |= AMD_PMC_UNITMASK_I;
 424                                 else if (c == '+')
 425                                         continue;
 426                                 else
 427                                         return (-1);
 428
 429                         if (unitmask == 0)
 430                                 return (-1);
 431
 432                 } else if (KWMATCH(p, K7_KW_USR)) {
 433                         pmc_config->pm_caps |= PMC_CAP_USER;
 434                 } else
 435                         return (-1);
 436         }
 437
 438         if (has_unitmask) {
 439                 pmc_config->pm_caps |= PMC_CAP_QUALIFIER;
 440                 pmc_config->pm_md.pm_amd.pm_amd_config |=
 441                     AMD_PMC_TO_UNITMASK(unitmask);
 442         }
 443
 444         return (0);
 445
 446 }
 447
 448 #endif
 449
 450 #if defined(__amd64__) || defined(__i386__)
 451
 452 /*
 453  * Intel Core (Family 6, Model E) PMCs.
 454  */
 455
 456 static struct pmc_event_alias core_aliases[] = {
 457         EV_ALIAS("branches",            "iap-br-instr-ret"),
 458         EV_ALIAS("branch-mispredicts",  "iap-br-mispred-ret"),
 459         EV_ALIAS("cycles",              "tsc-tsc"),
 460         EV_ALIAS("ic-misses",           "iap-icache-misses"),
 461         EV_ALIAS("instructions",        "iap-instr-ret"),
 462         EV_ALIAS("interrupts",          "iap-core-hw-int-rx"),
 463         EV_ALIAS("unhalted-cycles",     "iap-unhalted-core-cycles"),
 464         EV_ALIAS(NULL, NULL)
 465 };
 466
 467 /*
 468  * Intel Core2 (Family 6, Model F), Core2Extreme (Family 6, Model 17H)
 469  * and Atom (Family 6, model 1CH) PMCs.
 470  *
 471  * We map aliases to events on the fixed-function counters if these
 472  * are present.  Note that not all CPUs in this family contain fixed-function
 473  * counters.
 474  */
 475
 476 static struct pmc_event_alias core2_aliases[] = {
 477         EV_ALIAS("branches",            "iap-br-inst-retired.any"),
 478         EV_ALIAS("branch-mispredicts",  "iap-br-inst-retired.mispred"),
 479         EV_ALIAS("cycles",              "tsc-tsc"),
 480         EV_ALIAS("ic-misses",           "iap-l1i-misses"),
 481         EV_ALIAS("instructions",        "iaf-instr-retired.any"),
 482         EV_ALIAS("interrupts",          "iap-hw-int-rcv"),
 483         EV_ALIAS("unhalted-cycles",     "iaf-cpu-clk-unhalted.core"),
 484         EV_ALIAS(NULL, NULL)
 485 };
 486
 487 static struct pmc_event_alias core2_aliases_without_iaf[] = {
 488         EV_ALIAS("branches",            "iap-br-inst-retired.any"),
 489         EV_ALIAS("branch-mispredicts",  "iap-br-inst-retired.mispred"),
 490         EV_ALIAS("cycles",              "tsc-tsc"),
 491         EV_ALIAS("ic-misses",           "iap-l1i-misses"),
 492         EV_ALIAS("instructions",        "iap-inst-retired.any_p"),
 493         EV_ALIAS("interrupts",          "iap-hw-int-rcv"),
 494         EV_ALIAS("unhalted-cycles",     "iap-cpu-clk-unhalted.core_p"),
 495         EV_ALIAS(NULL, NULL)
 496 };
 497
 498 #define atom_aliases                    core2_aliases
 499 #define atom_aliases_without_iaf        core2_aliases_without_iaf
 500 #define corei7_aliases                  core2_aliases
 501 #define corei7_aliases_without_iaf      core2_aliases_without_iaf
 502 #define westmere_aliases                core2_aliases
 503 #define westmere_aliases_without_iaf    core2_aliases_without_iaf
 504
 505 #define IAF_KW_OS               "os"
 506 #define IAF_KW_USR              "usr"
 507 #define IAF_KW_ANYTHREAD        "anythread"
 508
 509 /*
 510  * Parse an event specifier for Intel fixed function counters.
 511  */
 512 static int
 513 iaf_allocate_pmc(enum pmc_event pe, char *ctrspec,
 514     struct pmc_op_pmcallocate *pmc_config)
 515 {
 516         char *p;
 517
 518         (void) pe;
 519
 520         pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE);
 521         pmc_config->pm_md.pm_iaf.pm_iaf_flags = 0;
 522
 523         while ((p = strsep(&ctrspec, ",")) != NULL) {
 524                 if (KWMATCH(p, IAF_KW_OS))
 525                         pmc_config->pm_caps |= PMC_CAP_SYSTEM;
 526                 else if (KWMATCH(p, IAF_KW_USR))
 527                         pmc_config->pm_caps |= PMC_CAP_USER;
 528                 else if (KWMATCH(p, IAF_KW_ANYTHREAD))
 529                         pmc_config->pm_md.pm_iaf.pm_iaf_flags |= IAF_ANY;
 530                 else
 531                         return (-1);
 532         }
 533
 534         return (0);
 535 }
 536
 537 /*
 538  * Core/Core2 support.
 539  */
 540
 541 #define IAP_KW_AGENT            "agent"
 542 #define IAP_KW_ANYTHREAD        "anythread"
 543 #define IAP_KW_CACHESTATE       "cachestate"
 544 #define IAP_KW_CMASK            "cmask"
 545 #define IAP_KW_CORE             "core"
 546 #define IAP_KW_EDGE             "edge"
 547 #define IAP_KW_INV              "inv"
 548 #define IAP_KW_OS               "os"
 549 #define IAP_KW_PREFETCH         "prefetch"
 550 #define IAP_KW_SNOOPRESPONSE    "snoopresponse"
 551 #define IAP_KW_SNOOPTYPE        "snooptype"
 552 #define IAP_KW_TRANSITION       "trans"
 553 #define IAP_KW_USR              "usr"
 554 #define IAP_KW_RSP              "rsp"
 555
 556 static struct pmc_masks iap_core_mask[] = {
 557         PMCMASK(all,    (0x3 << 14)),
 558         PMCMASK(this,   (0x1 << 14)),
 559         NULLMASK
 560 };
 561
 562 static struct pmc_masks iap_agent_mask[] = {
 563         PMCMASK(this,   0),
 564         PMCMASK(any,    (0x1 << 13)),
 565         NULLMASK
 566 };
 567
 568 static struct pmc_masks iap_prefetch_mask[] = {
 569         PMCMASK(both,           (0x3 << 12)),
 570         PMCMASK(only,           (0x1 << 12)),
 571         PMCMASK(exclude,        0),
 572         NULLMASK
 573 };
 574
 575 static struct pmc_masks iap_cachestate_mask[] = {
 576         PMCMASK(i,              (1 <<  8)),
 577         PMCMASK(s,              (1 <<  9)),
 578         PMCMASK(e,              (1 << 10)),
 579         PMCMASK(m,              (1 << 11)),
 580         NULLMASK
 581 };
 582
 583 static struct pmc_masks iap_snoopresponse_mask[] = {
 584         PMCMASK(clean,          (1 << 8)),
 585         PMCMASK(hit,            (1 << 9)),
 586         PMCMASK(hitm,           (1 << 11)),
 587         NULLMASK
 588 };
 589
 590 static struct pmc_masks iap_snooptype_mask[] = {
 591         PMCMASK(cmp2s,          (1 << 8)),
 592         PMCMASK(cmp2i,          (1 << 9)),
 593         NULLMASK
 594 };
 595
 596 static struct pmc_masks iap_transition_mask[] = {
 597         PMCMASK(any,            0x00),
 598         PMCMASK(frequency,      0x10),
 599         NULLMASK
 600 };
 601
 602 static struct pmc_masks iap_rsp_mask[] = {
 603         PMCMASK(DMND_DATA_RD,           (1 <<  0)),
 604         PMCMASK(DMND_RFO,               (1 <<  1)),
 605         PMCMASK(DMND_IFETCH,            (1 <<  2)),
 606         PMCMASK(WB,                     (1 <<  3)),
 607         PMCMASK(PF_DATA_RD,             (1 <<  4)),
 608         PMCMASK(PF_RFO,                 (1 <<  5)),
 609         PMCMASK(PF_IFETCH,              (1 <<  6)),
 610         PMCMASK(OTHER,                  (1 <<  7)),
 611         PMCMASK(UNCORE_HIT,             (1 <<  8)),
 612         PMCMASK(OTHER_CORE_HIT_SNP,     (1 <<  9)),
 613         PMCMASK(OTHER_CORE_HITM,        (1 << 10)),
 614         PMCMASK(REMOTE_CACHE_FWD,       (1 << 12)),
 615         PMCMASK(REMOTE_DRAM,            (1 << 13)),
 616         PMCMASK(LOCAL_DRAM,             (1 << 14)),
 617         PMCMASK(NON_DRAM,               (1 << 15)),
 618         NULLMASK
 619 };
 620
 621 static int
 622 iap_allocate_pmc(enum pmc_event pe, char *ctrspec,
 623     struct pmc_op_pmcallocate *pmc_config)
 624 {
 625         char *e, *p, *q;
 626         uint32_t cachestate, evmask, rsp;
 627         int count, n;
 628
 629         pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE |
 630             PMC_CAP_QUALIFIER);
 631         pmc_config->pm_md.pm_iap.pm_iap_config = 0;
 632
 633         cachestate = evmask = rsp = 0;
 634
 635         /* Parse additional modifiers if present */
 636         while ((p = strsep(&ctrspec, ",")) != NULL) {
 637
 638                 n = 0;
 639                 if (KWPREFIXMATCH(p, IAP_KW_CMASK "=")) {
 640                         q = strchr(p, '=');
 641                         if (*++q == '\0') /* skip '=' */
 642                                 return (-1);
 643                         count = strtol(q, &e, 0);
 644                         if (e == q || *e != '\0')
 645                                 return (-1);
 646                         pmc_config->pm_caps |= PMC_CAP_THRESHOLD;
 647                         pmc_config->pm_md.pm_iap.pm_iap_config |=
 648                             IAP_CMASK(count);
 649                 } else if (KWMATCH(p, IAP_KW_EDGE)) {
 650                         pmc_config->pm_caps |= PMC_CAP_EDGE;
 651                 } else if (KWMATCH(p, IAP_KW_INV)) {
 652                         pmc_config->pm_caps |= PMC_CAP_INVERT;
 653                 } else if (KWMATCH(p, IAP_KW_OS)) {
 654                         pmc_config->pm_caps |= PMC_CAP_SYSTEM;
 655                 } else if (KWMATCH(p, IAP_KW_USR)) {
 656                         pmc_config->pm_caps |= PMC_CAP_USER;
 657                 } else if (KWMATCH(p, IAP_KW_ANYTHREAD)) {
 658                         pmc_config->pm_md.pm_iap.pm_iap_config |= IAP_ANY;
 659                 } else if (KWPREFIXMATCH(p, IAP_KW_CORE "=")) {
 660                         n = pmc_parse_mask(iap_core_mask, p, &evmask);
 661                         if (n != 1)
 662                                 return (-1);
 663                 } else if (KWPREFIXMATCH(p, IAP_KW_AGENT "=")) {
 664                         n = pmc_parse_mask(iap_agent_mask, p, &evmask);
 665                         if (n != 1)
 666                                 return (-1);
 667                 } else if (KWPREFIXMATCH(p, IAP_KW_PREFETCH "=")) {
 668                         n = pmc_parse_mask(iap_prefetch_mask, p, &evmask);
 669                         if (n != 1)
 670                                 return (-1);
 671                 } else if (KWPREFIXMATCH(p, IAP_KW_CACHESTATE "=")) {
 672                         n = pmc_parse_mask(iap_cachestate_mask, p, &cachestate);
 673                 } else if (cpu_info.pm_cputype == PMC_CPU_INTEL_CORE &&
 674                     KWPREFIXMATCH(p, IAP_KW_TRANSITION "=")) {
 675                         n = pmc_parse_mask(iap_transition_mask, p, &evmask);
 676                         if (n != 1)
 677                                 return (-1);
 678                 } else if (cpu_info.pm_cputype == PMC_CPU_INTEL_ATOM ||
 679                     cpu_info.pm_cputype == PMC_CPU_INTEL_CORE2 ||
 680                     cpu_info.pm_cputype == PMC_CPU_INTEL_CORE2EXTREME) {
 681                         if (KWPREFIXMATCH(p, IAP_KW_SNOOPRESPONSE "=")) {
 682                                 n = pmc_parse_mask(iap_snoopresponse_mask, p,
 683                                     &evmask);
 684                         } else if (KWPREFIXMATCH(p, IAP_KW_SNOOPTYPE "=")) {
 685                                 n = pmc_parse_mask(iap_snooptype_mask, p,
 686                                     &evmask);
 687                         } else
 688                                 return (-1);
 689                 } else if (cpu_info.pm_cputype == PMC_CPU_INTEL_COREI7 ||
 690                     cpu_info.pm_cputype == PMC_CPU_INTEL_WESTMERE) {
 691                         if (KWPREFIXMATCH(p, IAP_KW_RSP "=")) {
 692                                 n = pmc_parse_mask(iap_rsp_mask, p, &rsp);
 693                         } else
 694                                 return (-1);
 695                 } else
 696                         return (-1);
 697
 698                 if (n < 0)      /* Parsing failed. */
 699                         return (-1);
 700         }
 701
 702         pmc_config->pm_md.pm_iap.pm_iap_config |= evmask;
 703
 704         /*
 705          * If the event requires a 'cachestate' qualifier but was not
 706          * specified by the user, use a sensible default.
 707          */
 708         switch (pe) {
 709         case PMC_EV_IAP_EVENT_28H: /* Core, Core2, Atom */
 710         case PMC_EV_IAP_EVENT_29H: /* Core, Core2, Atom */
 711         case PMC_EV_IAP_EVENT_2AH: /* Core, Core2, Atom */
 712         case PMC_EV_IAP_EVENT_2BH: /* Atom, Core2 */
 713         case PMC_EV_IAP_EVENT_2EH: /* Core, Core2, Atom */
 714         case PMC_EV_IAP_EVENT_30H: /* Core, Core2, Atom */
 715         case PMC_EV_IAP_EVENT_32H: /* Core */
 716         case PMC_EV_IAP_EVENT_40H: /* Core */
 717         case PMC_EV_IAP_EVENT_41H: /* Core */
 718         case PMC_EV_IAP_EVENT_42H: /* Core, Core2, Atom */
 719                 if (cachestate == 0)
 720                         cachestate = (0xF << 8);
 721                 break;
 722         case PMC_EV_IAP_EVENT_77H: /* Atom */
 723                 /* IAP_EVENT_77H only accepts a cachestate qualifier on the
 724                  * Atom processor
 725                  */
 726                 if(cpu_info.pm_cputype == PMC_CPU_INTEL_ATOM && cachestate == 0)
 727                         cachestate = (0xF << 8);
 728             break;
 729         default:
 730                 break;
 731         }
 732
 733         pmc_config->pm_md.pm_iap.pm_iap_config |= cachestate;
 734         pmc_config->pm_md.pm_iap.pm_iap_rsp = rsp;
 735
 736         return (0);
 737 }
 738
 739 /*
 740  * Intel Uncore.
 741  */
 742
 743 static int
 744 ucf_allocate_pmc(enum pmc_event pe, char *ctrspec,
 745     struct pmc_op_pmcallocate *pmc_config)
 746 {
 747         (void) pe;
 748         (void) ctrspec;
 749
 750         pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE);
 751         pmc_config->pm_md.pm_ucf.pm_ucf_flags = 0;
 752
 753         return (0);
 754 }
 755
 756 #define UCP_KW_CMASK            "cmask"
 757 #define UCP_KW_EDGE             "edge"
 758 #define UCP_KW_INV              "inv"
 759
 760 static int
 761 ucp_allocate_pmc(enum pmc_event pe, char *ctrspec,
 762     struct pmc_op_pmcallocate *pmc_config)
 763 {
 764         char *e, *p, *q;
 765         int count, n;
 766
 767         (void) pe;
 768
 769         pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE |
 770             PMC_CAP_QUALIFIER);
 771         pmc_config->pm_md.pm_ucp.pm_ucp_config = 0;
 772
 773         /* Parse additional modifiers if present */
 774         while ((p = strsep(&ctrspec, ",")) != NULL) {
 775
 776                 n = 0;
 777                 if (KWPREFIXMATCH(p, UCP_KW_CMASK "=")) {
 778                         q = strchr(p, '=');
 779                         if (*++q == '\0') /* skip '=' */
 780                                 return (-1);
 781                         count = strtol(q, &e, 0);
 782                         if (e == q || *e != '\0')
 783                                 return (-1);
 784                         pmc_config->pm_caps |= PMC_CAP_THRESHOLD;
 785                         pmc_config->pm_md.pm_ucp.pm_ucp_config |=
 786                             UCP_CMASK(count);
 787                 } else if (KWMATCH(p, UCP_KW_EDGE)) {
 788                         pmc_config->pm_caps |= PMC_CAP_EDGE;
 789                 } else if (KWMATCH(p, UCP_KW_INV)) {
 790                         pmc_config->pm_caps |= PMC_CAP_INVERT;
 791                 } else
 792                         return (-1);
 793
 794                 if (n < 0)      /* Parsing failed. */
 795                         return (-1);
 796         }
 797
 798         return (0);
 799 }
 800
 801 /*
 802  * AMD K8 PMCs.
 803  *
 804  * These are very similar to AMD K7 PMCs, but support more kinds of
 805  * events.
 806  */
 807
 808 static struct pmc_event_alias k8_aliases[] = {
 809         EV_ALIAS("branches",            "k8-fr-retired-taken-branches"),
 810         EV_ALIAS("branch-mispredicts",
 811             "k8-fr-retired-taken-branches-mispredicted"),
 812         EV_ALIAS("cycles",              "tsc"),
 813         EV_ALIAS("dc-misses",           "k8-dc-miss"),
 814         EV_ALIAS("ic-misses",           "k8-ic-miss"),
 815         EV_ALIAS("instructions",        "k8-fr-retired-x86-instructions"),
 816         EV_ALIAS("interrupts",          "k8-fr-taken-hardware-interrupts"),
 817         EV_ALIAS("unhalted-cycles",     "k8-bu-cpu-clk-unhalted"),
 818         EV_ALIAS(NULL, NULL)
 819 };
 820
 821 #define __K8MASK(N,V) PMCMASK(N,(1 << (V)))
 822
 823 /*
 824  * Parsing tables
 825  */
 826
 827 /* fp dispatched fpu ops */
 828 static const struct pmc_masks k8_mask_fdfo[] = {
 829         __K8MASK(add-pipe-excluding-junk-ops,   0),
 830         __K8MASK(multiply-pipe-excluding-junk-ops,      1),
 831         __K8MASK(store-pipe-excluding-junk-ops, 2),
 832         __K8MASK(add-pipe-junk-ops,             3),
 833         __K8MASK(multiply-pipe-junk-ops,        4),
 834         __K8MASK(store-pipe-junk-ops,           5),
 835         NULLMASK
 836 };
 837
 838 /* ls segment register loads */
 839 static const struct pmc_masks k8_mask_lsrl[] = {
 840         __K8MASK(es,    0),
 841         __K8MASK(cs,    1),
 842         __K8MASK(ss,    2),
 843         __K8MASK(ds,    3),
 844         __K8MASK(fs,    4),
 845         __K8MASK(gs,    5),
 846         __K8MASK(hs,    6),
 847         NULLMASK
 848 };
 849
 850 /* ls locked operation */
 851 static const struct pmc_masks k8_mask_llo[] = {
 852         __K8MASK(locked-instructions,   0),
 853         __K8MASK(cycles-in-request,     1),
 854         __K8MASK(cycles-to-complete,    2),
 855         NULLMASK
 856 };
 857
 858 /* dc refill from {l2,system} and dc copyback */
 859 static const struct pmc_masks k8_mask_dc[] = {
 860         __K8MASK(invalid,       0),
 861         __K8MASK(shared,        1),
 862         __K8MASK(exclusive,     2),
 863         __K8MASK(owner,         3),
 864         __K8MASK(modified,      4),
 865         NULLMASK
 866 };
 867
 868 /* dc one bit ecc error */
 869 static const struct pmc_masks k8_mask_dobee[] = {
 870         __K8MASK(scrubber,      0),
 871         __K8MASK(piggyback,     1),
 872         NULLMASK
 873 };
 874
 875 /* dc dispatched prefetch instructions */
 876 static const struct pmc_masks k8_mask_ddpi[] = {
 877         __K8MASK(load,  0),
 878         __K8MASK(store, 1),
 879         __K8MASK(nta,   2),
 880         NULLMASK
 881 };
 882
 883 /* dc dcache accesses by locks */
 884 static const struct pmc_masks k8_mask_dabl[] = {
 885         __K8MASK(accesses,      0),
 886         __K8MASK(misses,        1),
 887         NULLMASK
 888 };
 889
 890 /* bu internal l2 request */
 891 static const struct pmc_masks k8_mask_bilr[] = {
 892         __K8MASK(ic-fill,       0),
 893         __K8MASK(dc-fill,       1),
 894         __K8MASK(tlb-reload,    2),
 895         __K8MASK(tag-snoop,     3),
 896         __K8MASK(cancelled,     4),
 897         NULLMASK
 898 };
 899
 900 /* bu fill request l2 miss */
 901 static const struct pmc_masks k8_mask_bfrlm[] = {
 902         __K8MASK(ic-fill,       0),
 903         __K8MASK(dc-fill,       1),
 904         __K8MASK(tlb-reload,    2),
 905         NULLMASK
 906 };
 907
 908 /* bu fill into l2 */
 909 static const struct pmc_masks k8_mask_bfil[] = {
 910         __K8MASK(dirty-l2-victim,       0),
 911         __K8MASK(victim-from-l2,        1),
 912         NULLMASK
 913 };
 914
 915 /* fr retired fpu instructions */
 916 static const struct pmc_masks k8_mask_frfi[] = {
 917         __K8MASK(x87,                   0),
 918         __K8MASK(mmx-3dnow,             1),
 919         __K8MASK(packed-sse-sse2,       2),
 920         __K8MASK(scalar-sse-sse2,       3),
 921         NULLMASK
 922 };
 923
 924 /* fr retired fastpath double op instructions */
 925 static const struct pmc_masks k8_mask_frfdoi[] = {
 926         __K8MASK(low-op-pos-0,          0),
 927         __K8MASK(low-op-pos-1,          1),
 928         __K8MASK(low-op-pos-2,          2),
 929         NULLMASK
 930 };
 931
 932 /* fr fpu exceptions */
 933 static const struct pmc_masks k8_mask_ffe[] = {
 934         __K8MASK(x87-reclass-microfaults,       0),
 935         __K8MASK(sse-retype-microfaults,        1),
 936         __K8MASK(sse-reclass-microfaults,       2),
 937         __K8MASK(sse-and-x87-microtraps,        3),
 938         NULLMASK
 939 };
 940
 941 /* nb memory controller page access event */
 942 static const struct pmc_masks k8_mask_nmcpae[] = {
 943         __K8MASK(page-hit,      0),
 944         __K8MASK(page-miss,     1),
 945         __K8MASK(page-conflict, 2),
 946         NULLMASK
 947 };
 948
 949 /* nb memory controller turnaround */
 950 static const struct pmc_masks k8_mask_nmct[] = {
 951         __K8MASK(dimm-turnaround,               0),
 952         __K8MASK(read-to-write-turnaround,      1),
 953         __K8MASK(write-to-read-turnaround,      2),
 954         NULLMASK
 955 };
 956
 957 /* nb memory controller bypass saturation */
 958 static const struct pmc_masks k8_mask_nmcbs[] = {
 959         __K8MASK(memory-controller-hi-pri-bypass,       0),
 960         __K8MASK(memory-controller-lo-pri-bypass,       1),
 961         __K8MASK(dram-controller-interface-bypass,      2),
 962         __K8MASK(dram-controller-queue-bypass,          3),
 963         NULLMASK
 964 };
 965
 966 /* nb sized commands */
 967 static const struct pmc_masks k8_mask_nsc[] = {
 968         __K8MASK(nonpostwrszbyte,       0),
 969         __K8MASK(nonpostwrszdword,      1),
 970         __K8MASK(postwrszbyte,          2),
 971         __K8MASK(postwrszdword,         3),
 972         __K8MASK(rdszbyte,              4),
 973         __K8MASK(rdszdword,             5),
 974         __K8MASK(rdmodwr,               6),
 975         NULLMASK
 976 };
 977
 978 /* nb probe result */
 979 static const struct pmc_masks k8_mask_npr[] = {
 980         __K8MASK(probe-miss,            0),
 981         __K8MASK(probe-hit,             1),
 982         __K8MASK(probe-hit-dirty-no-memory-cancel, 2),
 983         __K8MASK(probe-hit-dirty-with-memory-cancel, 3),
 984         NULLMASK
 985 };
 986
 987 /* nb hypertransport bus bandwidth */
 988 static const struct pmc_masks k8_mask_nhbb[] = { /* HT bus bandwidth */
 989         __K8MASK(command,       0),
 990         __K8MASK(data,  1),
 991         __K8MASK(buffer-release, 2),
 992         __K8MASK(nop,   3),
 993         NULLMASK
 994 };
 995
 996 #undef  __K8MASK
 997
 998 #define K8_KW_COUNT     "count"
 999 #define K8_KW_EDGE      "edge"
1000 #define K8_KW_INV       "inv"
1001 #define K8_KW_MASK      "mask"
1002 #define K8_KW_OS        "os"
1003 #define K8_KW_USR       "usr"
1004
1005 static int
1006 k8_allocate_pmc(enum pmc_event pe, char *ctrspec,
1007     struct pmc_op_pmcallocate *pmc_config)
1008 {
1009         char            *e, *p, *q;
1010         int             n;
1011         uint32_t        count, evmask;
1012         const struct pmc_masks  *pm, *pmask;
1013
1014         pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE);
1015         pmc_config->pm_md.pm_amd.pm_amd_config = 0;
1016
1017         pmask = NULL;
1018         evmask = 0;
1019
1020 #define __K8SETMASK(M) pmask = k8_mask_##M
1021
1022         /* setup parsing tables */
1023         switch (pe) {
1024         case PMC_EV_K8_FP_DISPATCHED_FPU_OPS:
1025                 __K8SETMASK(fdfo);
1026                 break;
1027         case PMC_EV_K8_LS_SEGMENT_REGISTER_LOAD:
1028                 __K8SETMASK(lsrl);
1029                 break;
1030         case PMC_EV_K8_LS_LOCKED_OPERATION:
1031                 __K8SETMASK(llo);
1032                 break;
1033         case PMC_EV_K8_DC_REFILL_FROM_L2:
1034         case PMC_EV_K8_DC_REFILL_FROM_SYSTEM:
1035         case PMC_EV_K8_DC_COPYBACK:
1036                 __K8SETMASK(dc);
1037                 break;
1038         case PMC_EV_K8_DC_ONE_BIT_ECC_ERROR:
1039                 __K8SETMASK(dobee);
1040                 break;
1041         case PMC_EV_K8_DC_DISPATCHED_PREFETCH_INSTRUCTIONS:
1042                 __K8SETMASK(ddpi);
1043                 break;
1044         case PMC_EV_K8_DC_DCACHE_ACCESSES_BY_LOCKS:
1045                 __K8SETMASK(dabl);
1046                 break;
1047         case PMC_EV_K8_BU_INTERNAL_L2_REQUEST:
1048                 __K8SETMASK(bilr);
1049                 break;
1050         case PMC_EV_K8_BU_FILL_REQUEST_L2_MISS:
1051                 __K8SETMASK(bfrlm);
1052                 break;
1053         case PMC_EV_K8_BU_FILL_INTO_L2:
1054                 __K8SETMASK(bfil);
1055                 break;
1056         case PMC_EV_K8_FR_RETIRED_FPU_INSTRUCTIONS:
1057                 __K8SETMASK(frfi);
1058                 break;
1059         case PMC_EV_K8_FR_RETIRED_FASTPATH_DOUBLE_OP_INSTRUCTIONS:
1060                 __K8SETMASK(frfdoi);
1061                 break;
1062         case PMC_EV_K8_FR_FPU_EXCEPTIONS:
1063                 __K8SETMASK(ffe);
1064                 break;
1065         case PMC_EV_K8_NB_MEMORY_CONTROLLER_PAGE_ACCESS_EVENT:
1066                 __K8SETMASK(nmcpae);
1067                 break;
1068         case PMC_EV_K8_NB_MEMORY_CONTROLLER_TURNAROUND:
1069                 __K8SETMASK(nmct);
1070                 break;
1071         case PMC_EV_K8_NB_MEMORY_CONTROLLER_BYPASS_SATURATION:
1072                 __K8SETMASK(nmcbs);
1073                 break;
1074         case PMC_EV_K8_NB_SIZED_COMMANDS:
1075                 __K8SETMASK(nsc);
1076                 break;
1077         case PMC_EV_K8_NB_PROBE_RESULT:
1078                 __K8SETMASK(npr);
1079                 break;
1080         case PMC_EV_K8_NB_HT_BUS0_BANDWIDTH:
1081         case PMC_EV_K8_NB_HT_BUS1_BANDWIDTH:
1082         case PMC_EV_K8_NB_HT_BUS2_BANDWIDTH:
1083                 __K8SETMASK(nhbb);
1084                 break;
1085
1086         default:
1087                 break;          /* no options defined */
1088         }
1089
1090         while ((p = strsep(&ctrspec, ",")) != NULL) {
1091                 if (KWPREFIXMATCH(p, K8_KW_COUNT "=")) {
1092                         q = strchr(p, '=');
1093                         if (*++q == '\0') /* skip '=' */
1094                                 return (-1);
1095
1096                         count = strtol(q, &e, 0);
1097                         if (e == q || *e != '\0')
1098                                 return (-1);
1099
1100                         pmc_config->pm_caps |= PMC_CAP_THRESHOLD;
1101                         pmc_config->pm_md.pm_amd.pm_amd_config |=
1102                             AMD_PMC_TO_COUNTER(count);
1103
1104                 } else if (KWMATCH(p, K8_KW_EDGE)) {
1105                         pmc_config->pm_caps |= PMC_CAP_EDGE;
1106                 } else if (KWMATCH(p, K8_KW_INV)) {
1107                         pmc_config->pm_caps |= PMC_CAP_INVERT;
1108                 } else if (KWPREFIXMATCH(p, K8_KW_MASK "=")) {
1109                         if ((n = pmc_parse_mask(pmask, p, &evmask)) < 0)
1110                                 return (-1);
1111                         pmc_config->pm_caps |= PMC_CAP_QUALIFIER;
1112                 } else if (KWMATCH(p, K8_KW_OS)) {
1113                         pmc_config->pm_caps |= PMC_CAP_SYSTEM;
1114                 } else if (KWMATCH(p, K8_KW_USR)) {
1115                         pmc_config->pm_caps |= PMC_CAP_USER;
1116                 } else
1117                         return (-1);
1118         }
1119
1120         /* other post processing */
1121         switch (pe) {
1122         case PMC_EV_K8_FP_DISPATCHED_FPU_OPS:
1123         case PMC_EV_K8_FP_CYCLES_WITH_NO_FPU_OPS_RETIRED:
1124         case PMC_EV_K8_FP_DISPATCHED_FPU_FAST_FLAG_OPS:
1125         case PMC_EV_K8_FR_RETIRED_FASTPATH_DOUBLE_OP_INSTRUCTIONS:
1126         case PMC_EV_K8_FR_RETIRED_FPU_INSTRUCTIONS:
1127         case PMC_EV_K8_FR_FPU_EXCEPTIONS:
1128                 /* XXX only available in rev B and later */
1129                 break;
1130         case PMC_EV_K8_DC_DCACHE_ACCESSES_BY_LOCKS:
1131                 /* XXX only available in rev C and later */
1132                 break;
1133         case PMC_EV_K8_LS_LOCKED_OPERATION:
1134                 /* XXX CPU Rev A,B evmask is to be zero */
1135                 if (evmask & (evmask - 1)) /* > 1 bit set */
1136                         return (-1);
1137                 if (evmask == 0) {
1138                         evmask = 0x01; /* Rev C and later: #instrs */
1139                         pmc_config->pm_caps |= PMC_CAP_QUALIFIER;
1140                 }
1141                 break;
1142         default:
1143                 if (evmask == 0 && pmask != NULL) {
1144                         for (pm = pmask; pm->pm_name; pm++)
1145                                 evmask |= pm->pm_value;
1146                         pmc_config->pm_caps |= PMC_CAP_QUALIFIER;
1147                 }
1148         }
1149
1150         if (pmc_config->pm_caps & PMC_CAP_QUALIFIER)
1151                 pmc_config->pm_md.pm_amd.pm_amd_config =
1152                     AMD_PMC_TO_UNITMASK(evmask);
1153
1154         return (0);
1155 }
1156
1157 #endif
1158
1159 #if defined(__amd64__) || defined(__i386__)
1160
1161 /*
1162  * Intel P4 PMCs
1163  */
1164
1165 static struct pmc_event_alias p4_aliases[] = {
1166         EV_ALIAS("branches",            "p4-branch-retired,mask=mmtp+mmtm"),
1167         EV_ALIAS("branch-mispredicts",  "p4-mispred-branch-retired"),
1168         EV_ALIAS("cycles",              "tsc"),
1169         EV_ALIAS("instructions",
1170             "p4-instr-retired,mask=nbogusntag+nbogustag"),
1171         EV_ALIAS("unhalted-cycles",     "p4-global-power-events"),
1172         EV_ALIAS(NULL, NULL)
1173 };
1174
1175 #define P4_KW_ACTIVE    "active"
1176 #define P4_KW_ACTIVE_ANY "any"
1177 #define P4_KW_ACTIVE_BOTH "both"
1178 #define P4_KW_ACTIVE_NONE "none"
1179 #define P4_KW_ACTIVE_SINGLE "single"
1180 #define P4_KW_BUSREQTYPE "busreqtype"
1181 #define P4_KW_CASCADE   "cascade"
1182 #define P4_KW_EDGE      "edge"
1183 #define P4_KW_INV       "complement"
1184 #define P4_KW_OS        "os"
1185 #define P4_KW_MASK      "mask"
1186 #define P4_KW_PRECISE   "precise"
1187 #define P4_KW_TAG       "tag"
1188 #define P4_KW_THRESHOLD "threshold"
1189 #define P4_KW_USR       "usr"
1190
1191 #define __P4MASK(N,V) PMCMASK(N, (1 << (V)))
1192
1193 static const struct pmc_masks p4_mask_tcdm[] = { /* tc deliver mode */
1194         __P4MASK(dd, 0),
1195         __P4MASK(db, 1),
1196         __P4MASK(di, 2),
1197         __P4MASK(bd, 3),
1198         __P4MASK(bb, 4),
1199         __P4MASK(bi, 5),
1200         __P4MASK(id, 6),
1201         __P4MASK(ib, 7),
1202         NULLMASK
1203 };
1204
1205 static const struct pmc_masks p4_mask_bfr[] = { /* bpu fetch request */
1206         __P4MASK(tcmiss, 0),
1207         NULLMASK,
1208 };
1209
1210 static const struct pmc_masks p4_mask_ir[] = { /* itlb reference */
1211         __P4MASK(hit, 0),
1212         __P4MASK(miss, 1),
1213         __P4MASK(hit-uc, 2),
1214         NULLMASK
1215 };
1216
1217 static const struct pmc_masks p4_mask_memcan[] = { /* memory cancel */
1218         __P4MASK(st-rb-full, 2),
1219         __P4MASK(64k-conf, 3),
1220         NULLMASK
1221 };
1222
1223 static const struct pmc_masks p4_mask_memcomp[] = { /* memory complete */
1224         __P4MASK(lsc, 0),
1225         __P4MASK(ssc, 1),
1226         NULLMASK
1227 };
1228
1229 static const struct pmc_masks p4_mask_lpr[] = { /* load port replay */
1230         __P4MASK(split-ld, 1),
1231         NULLMASK
1232 };
1233
1234 static const struct pmc_masks p4_mask_spr[] = { /* store port replay */
1235         __P4MASK(split-st, 1),
1236         NULLMASK
1237 };
1238
1239 static const struct pmc_masks p4_mask_mlr[] = { /* mob load replay */
1240         __P4MASK(no-sta, 1),
1241         __P4MASK(no-std, 3),
1242         __P4MASK(partial-data, 4),
1243         __P4MASK(unalgn-addr, 5),
1244         NULLMASK
1245 };
1246
1247 static const struct pmc_masks p4_mask_pwt[] = { /* page walk type */
1248         __P4MASK(dtmiss, 0),
1249         __P4MASK(itmiss, 1),
1250         NULLMASK
1251 };
1252
1253 static const struct pmc_masks p4_mask_bcr[] = { /* bsq cache reference */
1254         __P4MASK(rd-2ndl-hits, 0),
1255         __P4MASK(rd-2ndl-hite, 1),
1256         __P4MASK(rd-2ndl-hitm, 2),
1257         __P4MASK(rd-3rdl-hits, 3),
1258         __P4MASK(rd-3rdl-hite, 4),
1259         __P4MASK(rd-3rdl-hitm, 5),
1260         __P4MASK(rd-2ndl-miss, 8),
1261         __P4MASK(rd-3rdl-miss, 9),
1262         __P4MASK(wr-2ndl-miss, 10),
1263         NULLMASK
1264 };
1265
1266 static const struct pmc_masks p4_mask_ia[] = { /* ioq allocation */
1267         __P4MASK(all-read, 5),
1268         __P4MASK(all-write, 6),
1269         __P4MASK(mem-uc, 7),
1270         __P4MASK(mem-wc, 8),
1271         __P4MASK(mem-wt, 9),
1272         __P4MASK(mem-wp, 10),
1273         __P4MASK(mem-wb, 11),
1274         __P4MASK(own, 13),
1275         __P4MASK(other, 14),
1276         __P4MASK(prefetch, 15),
1277         NULLMASK
1278 };
1279
1280 static const struct pmc_masks p4_mask_iae[] = { /* ioq active entries */
1281         __P4MASK(all-read, 5),
1282         __P4MASK(all-write, 6),
1283         __P4MASK(mem-uc, 7),
1284         __P4MASK(mem-wc, 8),
1285         __P4MASK(mem-wt, 9),
1286         __P4MASK(mem-wp, 10),
1287         __P4MASK(mem-wb, 11),
1288         __P4MASK(own, 13),
1289         __P4MASK(other, 14),
1290         __P4MASK(prefetch, 15),
1291         NULLMASK
1292 };
1293
1294 static const struct pmc_masks p4_mask_fda[] = { /* fsb data activity */
1295         __P4MASK(drdy-drv, 0),
1296         __P4MASK(drdy-own, 1),
1297         __P4MASK(drdy-other, 2),
1298         __P4MASK(dbsy-drv, 3),
1299         __P4MASK(dbsy-own, 4),
1300         __P4MASK(dbsy-other, 5),
1301         NULLMASK
1302 };
1303
1304 static const struct pmc_masks p4_mask_ba[] = { /* bsq allocation */
1305         __P4MASK(req-type0, 0),
1306         __P4MASK(req-type1, 1),
1307         __P4MASK(req-len0, 2),
1308         __P4MASK(req-len1, 3),
1309         __P4MASK(req-io-type, 5),
1310         __P4MASK(req-lock-type, 6),
1311         __P4MASK(req-cache-type, 7),
1312         __P4MASK(req-split-type, 8),
1313         __P4MASK(req-dem-type, 9),
1314         __P4MASK(req-ord-type, 10),
1315         __P4MASK(mem-type0, 11),
1316         __P4MASK(mem-type1, 12),
1317         __P4MASK(mem-type2, 13),
1318         NULLMASK
1319 };
1320
1321 static const struct pmc_masks p4_mask_sia[] = { /* sse input assist */
1322         __P4MASK(all, 15),
1323         NULLMASK
1324 };
1325
1326 static const struct pmc_masks p4_mask_psu[] = { /* packed sp uop */
1327         __P4MASK(all, 15),
1328         NULLMASK
1329 };
1330
1331 static const struct pmc_masks p4_mask_pdu[] = { /* packed dp uop */
1332         __P4MASK(all, 15),
1333         NULLMASK
1334 };
1335
1336 static const struct pmc_masks p4_mask_ssu[] = { /* scalar sp uop */
1337         __P4MASK(all, 15),
1338         NULLMASK
1339 };
1340
1341 static const struct pmc_masks p4_mask_sdu[] = { /* scalar dp uop */
1342         __P4MASK(all, 15),
1343         NULLMASK
1344 };
1345
1346 static const struct pmc_masks p4_mask_64bmu[] = { /* 64 bit mmx uop */
1347         __P4MASK(all, 15),
1348         NULLMASK
1349 };
1350
1351 static const struct pmc_masks p4_mask_128bmu[] = { /* 128 bit mmx uop */
1352         __P4MASK(all, 15),
1353         NULLMASK
1354 };
1355
1356 static const struct pmc_masks p4_mask_xfu[] = { /* X87 fp uop */
1357         __P4MASK(all, 15),
1358         NULLMASK
1359 };
1360
1361 static const struct pmc_masks p4_mask_xsmu[] = { /* x87 simd moves uop */
1362         __P4MASK(allp0, 3),
1363         __P4MASK(allp2, 4),
1364         NULLMASK
1365 };
1366
1367 static const struct pmc_masks p4_mask_gpe[] = { /* global power events */
1368         __P4MASK(running, 0),
1369         NULLMASK
1370 };
1371
1372 static const struct pmc_masks p4_mask_tmx[] = { /* TC ms xfer */
1373         __P4MASK(cisc, 0),
1374         NULLMASK
1375 };
1376
1377 static const struct pmc_masks p4_mask_uqw[] = { /* uop queue writes */
1378         __P4MASK(from-tc-build, 0),
1379         __P4MASK(from-tc-deliver, 1),
1380         __P4MASK(from-rom, 2),
1381         NULLMASK
1382 };
1383
1384 static const struct pmc_masks p4_mask_rmbt[] = {
1385         /* retired mispred branch type */
1386         __P4MASK(conditional, 1),
1387         __P4MASK(call, 2),
1388         __P4MASK(return, 3),
1389         __P4MASK(indirect, 4),
1390         NULLMASK
1391 };
1392
1393 static const struct pmc_masks p4_mask_rbt[] = { /* retired branch type */
1394         __P4MASK(conditional, 1),
1395         __P4MASK(call, 2),
1396         __P4MASK(retired, 3),
1397         __P4MASK(indirect, 4),
1398         NULLMASK
1399 };
1400
1401 static const struct pmc_masks p4_mask_rs[] = { /* resource stall */
1402         __P4MASK(sbfull, 5),
1403         NULLMASK
1404 };
1405
1406 static const struct pmc_masks p4_mask_wb[] = { /* WC buffer */
1407         __P4MASK(wcb-evicts, 0),
1408         __P4MASK(wcb-full-evict, 1),
1409         NULLMASK
1410 };
1411
1412 static const struct pmc_masks p4_mask_fee[] = { /* front end event */
1413         __P4MASK(nbogus, 0),
1414         __P4MASK(bogus, 1),
1415         NULLMASK
1416 };
1417
1418 static const struct pmc_masks p4_mask_ee[] = { /* execution event */
1419         __P4MASK(nbogus0, 0),
1420         __P4MASK(nbogus1, 1),
1421         __P4MASK(nbogus2, 2),
1422         __P4MASK(nbogus3, 3),
1423         __P4MASK(bogus0, 4),
1424         __P4MASK(bogus1, 5),
1425         __P4MASK(bogus2, 6),
1426         __P4MASK(bogus3, 7),
1427         NULLMASK
1428 };
1429
1430 static const struct pmc_masks p4_mask_re[] = { /* replay event */
1431         __P4MASK(nbogus, 0),
1432         __P4MASK(bogus, 1),
1433         NULLMASK
1434 };
1435
1436 static const struct pmc_masks p4_mask_insret[] = { /* instr retired */
1437         __P4MASK(nbogusntag, 0),
1438         __P4MASK(nbogustag, 1),
1439         __P4MASK(bogusntag, 2),
1440         __P4MASK(bogustag, 3),
1441         NULLMASK
1442 };
1443
1444 static const struct pmc_masks p4_mask_ur[] = { /* uops retired */
1445         __P4MASK(nbogus, 0),
1446         __P4MASK(bogus, 1),
1447         NULLMASK
1448 };
1449
1450 static const struct pmc_masks p4_mask_ut[] = { /* uop type */
1451         __P4MASK(tagloads, 1),
1452         __P4MASK(tagstores, 2),
1453         NULLMASK
1454 };
1455
1456 static const struct pmc_masks p4_mask_br[] = { /* branch retired */
1457         __P4MASK(mmnp, 0),
1458         __P4MASK(mmnm, 1),
1459         __P4MASK(mmtp, 2),
1460         __P4MASK(mmtm, 3),
1461         NULLMASK
1462 };
1463
1464 static const struct pmc_masks p4_mask_mbr[] = { /* mispred branch retired */
1465         __P4MASK(nbogus, 0),
1466         NULLMASK
1467 };
1468
1469 static const struct pmc_masks p4_mask_xa[] = { /* x87 assist */
1470         __P4MASK(fpsu, 0),
1471         __P4MASK(fpso, 1),
1472         __P4MASK(poao, 2),
1473         __P4MASK(poau, 3),
1474         __P4MASK(prea, 4),
1475         NULLMASK
1476 };
1477
1478 static const struct pmc_masks p4_mask_machclr[] = { /* machine clear */
1479         __P4MASK(clear, 0),
1480         __P4MASK(moclear, 2),
1481         __P4MASK(smclear, 3),
1482         NULLMASK
1483 };
1484
1485 /* P4 event parser */
1486 static int
1487 p4_allocate_pmc(enum pmc_event pe, char *ctrspec,
1488     struct pmc_op_pmcallocate *pmc_config)
1489 {
1490
1491         char    *e, *p, *q;
1492         int     count, has_tag, has_busreqtype, n;
1493         uint32_t evmask, cccractivemask;
1494         const struct pmc_masks *pm, *pmask;
1495
1496         pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE);
1497         pmc_config->pm_md.pm_p4.pm_p4_cccrconfig =
1498             pmc_config->pm_md.pm_p4.pm_p4_escrconfig = 0;
1499
1500         pmask   = NULL;
1501         evmask  = 0;
1502         cccractivemask = 0x3;
1503         has_tag = has_busreqtype = 0;
1504
1505 #define __P4SETMASK(M) do {                             \
1506         pmask = p4_mask_##M;                            \
1507 } while (0)
1508
1509         switch (pe) {
1510         case PMC_EV_P4_TC_DELIVER_MODE:
1511                 __P4SETMASK(tcdm);
1512                 break;
1513         case PMC_EV_P4_BPU_FETCH_REQUEST:
1514                 __P4SETMASK(bfr);
1515                 break;
1516         case PMC_EV_P4_ITLB_REFERENCE:
1517                 __P4SETMASK(ir);
1518                 break;
1519         case PMC_EV_P4_MEMORY_CANCEL:
1520                 __P4SETMASK(memcan);
1521                 break;
1522         case PMC_EV_P4_MEMORY_COMPLETE:
1523                 __P4SETMASK(memcomp);
1524                 break;
1525         case PMC_EV_P4_LOAD_PORT_REPLAY:
1526                 __P4SETMASK(lpr);
1527                 break;
1528         case PMC_EV_P4_STORE_PORT_REPLAY:
1529                 __P4SETMASK(spr);
1530                 break;
1531         case PMC_EV_P4_MOB_LOAD_REPLAY:
1532                 __P4SETMASK(mlr);
1533                 break;
1534         case PMC_EV_P4_PAGE_WALK_TYPE:
1535                 __P4SETMASK(pwt);
1536                 break;
1537         case PMC_EV_P4_BSQ_CACHE_REFERENCE:
1538                 __P4SETMASK(bcr);
1539                 break;
1540         case PMC_EV_P4_IOQ_ALLOCATION:
1541                 __P4SETMASK(ia);
1542                 has_busreqtype = 1;
1543                 break;
1544         case PMC_EV_P4_IOQ_ACTIVE_ENTRIES:
1545                 __P4SETMASK(iae);
1546                 has_busreqtype = 1;
1547                 break;
1548         case PMC_EV_P4_FSB_DATA_ACTIVITY:
1549                 __P4SETMASK(fda);
1550                 break;
1551         case PMC_EV_P4_BSQ_ALLOCATION:
1552                 __P4SETMASK(ba);
1553                 break;
1554         case PMC_EV_P4_SSE_INPUT_ASSIST:
1555                 __P4SETMASK(sia);
1556                 break;
1557         case PMC_EV_P4_PACKED_SP_UOP:
1558                 __P4SETMASK(psu);
1559                 break;
1560         case PMC_EV_P4_PACKED_DP_UOP:
1561                 __P4SETMASK(pdu);
1562                 break;
1563         case PMC_EV_P4_SCALAR_SP_UOP:
1564                 __P4SETMASK(ssu);
1565                 break;
1566         case PMC_EV_P4_SCALAR_DP_UOP:
1567                 __P4SETMASK(sdu);
1568                 break;
1569         case PMC_EV_P4_64BIT_MMX_UOP:
1570                 __P4SETMASK(64bmu);
1571                 break;
1572         case PMC_EV_P4_128BIT_MMX_UOP:
1573                 __P4SETMASK(128bmu);
1574                 break;
1575         case PMC_EV_P4_X87_FP_UOP:
1576                 __P4SETMASK(xfu);
1577                 break;
1578         case PMC_EV_P4_X87_SIMD_MOVES_UOP:
1579                 __P4SETMASK(xsmu);
1580                 break;
1581         case PMC_EV_P4_GLOBAL_POWER_EVENTS:
1582                 __P4SETMASK(gpe);
1583                 break;
1584         case PMC_EV_P4_TC_MS_XFER:
1585                 __P4SETMASK(tmx);
1586                 break;
1587         case PMC_EV_P4_UOP_QUEUE_WRITES:
1588                 __P4SETMASK(uqw);
1589                 break;
1590         case PMC_EV_P4_RETIRED_MISPRED_BRANCH_TYPE:
1591                 __P4SETMASK(rmbt);
1592                 break;
1593         case PMC_EV_P4_RETIRED_BRANCH_TYPE:
1594                 __P4SETMASK(rbt);
1595                 break;
1596         case PMC_EV_P4_RESOURCE_STALL:
1597                 __P4SETMASK(rs);
1598                 break;
1599         case PMC_EV_P4_WC_BUFFER:
1600                 __P4SETMASK(wb);
1601                 break;
1602         case PMC_EV_P4_BSQ_ACTIVE_ENTRIES:
1603         case PMC_EV_P4_B2B_CYCLES:
1604         case PMC_EV_P4_BNR:
1605         case PMC_EV_P4_SNOOP:
1606         case PMC_EV_P4_RESPONSE:
1607                 break;
1608         case PMC_EV_P4_FRONT_END_EVENT:
1609                 __P4SETMASK(fee);
1610                 break;
1611         case PMC_EV_P4_EXECUTION_EVENT:
1612                 __P4SETMASK(ee);
1613                 break;
1614         case PMC_EV_P4_REPLAY_EVENT:
1615                 __P4SETMASK(re);
1616                 break;
1617         case PMC_EV_P4_INSTR_RETIRED:
1618                 __P4SETMASK(insret);
1619                 break;
1620         case PMC_EV_P4_UOPS_RETIRED:
1621                 __P4SETMASK(ur);
1622                 break;
1623         case PMC_EV_P4_UOP_TYPE:
1624                 __P4SETMASK(ut);
1625                 break;
1626         case PMC_EV_P4_BRANCH_RETIRED:
1627                 __P4SETMASK(br);
1628                 break;
1629         case PMC_EV_P4_MISPRED_BRANCH_RETIRED:
1630                 __P4SETMASK(mbr);
1631                 break;
1632         case PMC_EV_P4_X87_ASSIST:
1633                 __P4SETMASK(xa);
1634                 break;
1635         case PMC_EV_P4_MACHINE_CLEAR:
1636                 __P4SETMASK(machclr);
1637                 break;
1638         default:
1639                 return (-1);
1640         }
1641
1642         /* process additional flags */
1643         while ((p = strsep(&ctrspec, ",")) != NULL) {
1644                 if (KWPREFIXMATCH(p, P4_KW_ACTIVE)) {
1645                         q = strchr(p, '=');
1646                         if (*++q == '\0') /* skip '=' */
1647                                 return (-1);
1648
1649                         if (strcasecmp(q, P4_KW_ACTIVE_NONE) == 0)
1650                                 cccractivemask = 0x0;
1651                         else if (strcasecmp(q, P4_KW_ACTIVE_SINGLE) == 0)
1652                                 cccractivemask = 0x1;
1653                         else if (strcasecmp(q, P4_KW_ACTIVE_BOTH) == 0)
1654                                 cccractivemask = 0x2;
1655                         else if (strcasecmp(q, P4_KW_ACTIVE_ANY) == 0)
1656                                 cccractivemask = 0x3;
1657                         else
1658                                 return (-1);
1659
1660                 } else if (KWPREFIXMATCH(p, P4_KW_BUSREQTYPE)) {
1661                         if (has_busreqtype == 0)
1662                                 return (-1);
1663
1664                         q = strchr(p, '=');
1665                         if (*++q == '\0') /* skip '=' */
1666                                 return (-1);
1667
1668                         count = strtol(q, &e, 0);
1669                         if (e == q || *e != '\0')
1670                                 return (-1);
1671                         evmask = (evmask & ~0x1F) | (count & 0x1F);
1672                 } else if (KWMATCH(p, P4_KW_CASCADE))
1673                         pmc_config->pm_caps |= PMC_CAP_CASCADE;
1674                 else if (KWMATCH(p, P4_KW_EDGE))
1675                         pmc_config->pm_caps |= PMC_CAP_EDGE;
1676                 else if (KWMATCH(p, P4_KW_INV))
1677                         pmc_config->pm_caps |= PMC_CAP_INVERT;
1678                 else if (KWPREFIXMATCH(p, P4_KW_MASK "=")) {
1679                         if ((n = pmc_parse_mask(pmask, p, &evmask)) < 0)
1680                                 return (-1);
1681                         pmc_config->pm_caps |= PMC_CAP_QUALIFIER;
1682                 } else if (KWMATCH(p, P4_KW_OS))
1683                         pmc_config->pm_caps |= PMC_CAP_SYSTEM;
1684                 else if (KWMATCH(p, P4_KW_PRECISE))
1685                         pmc_config->pm_caps |= PMC_CAP_PRECISE;
1686                 else if (KWPREFIXMATCH(p, P4_KW_TAG "=")) {
1687                         if (has_tag == 0)
1688                                 return (-1);
1689
1690                         q = strchr(p, '=');
1691                         if (*++q == '\0') /* skip '=' */
1692                                 return (-1);
1693
1694                         count = strtol(q, &e, 0);
1695                         if (e == q || *e != '\0')
1696                                 return (-1);
1697
1698                         pmc_config->pm_caps |= PMC_CAP_TAGGING;
1699                         pmc_config->pm_md.pm_p4.pm_p4_escrconfig |=
1700                             P4_ESCR_TO_TAG_VALUE(count);
1701                 } else if (KWPREFIXMATCH(p, P4_KW_THRESHOLD "=")) {
1702                         q = strchr(p, '=');
1703                         if (*++q == '\0') /* skip '=' */
1704                                 return (-1);
1705
1706                         count = strtol(q, &e, 0);
1707                         if (e == q || *e != '\0')
1708                                 return (-1);
1709
1710                         pmc_config->pm_caps |= PMC_CAP_THRESHOLD;
1711                         pmc_config->pm_md.pm_p4.pm_p4_cccrconfig &=
1712                             ~P4_CCCR_THRESHOLD_MASK;
1713                         pmc_config->pm_md.pm_p4.pm_p4_cccrconfig |=
1714                             P4_CCCR_TO_THRESHOLD(count);
1715                 } else if (KWMATCH(p, P4_KW_USR))
1716                         pmc_config->pm_caps |= PMC_CAP_USER;
1717                 else
1718                         return (-1);
1719         }
1720
1721         /* other post processing */
1722         if (pe == PMC_EV_P4_IOQ_ALLOCATION ||
1723             pe == PMC_EV_P4_FSB_DATA_ACTIVITY ||
1724             pe == PMC_EV_P4_BSQ_ALLOCATION)
1725                 pmc_config->pm_caps |= PMC_CAP_EDGE;
1726
1727         /* fill in thread activity mask */
1728         pmc_config->pm_md.pm_p4.pm_p4_cccrconfig |=
1729             P4_CCCR_TO_ACTIVE_THREAD(cccractivemask);
1730
1731         if (evmask)
1732                 pmc_config->pm_caps |= PMC_CAP_QUALIFIER;
1733
1734         switch (pe) {
1735         case PMC_EV_P4_FSB_DATA_ACTIVITY:
1736                 if ((evmask & 0x06) == 0x06 ||
1737                     (evmask & 0x18) == 0x18)
1738                         return (-1); /* can't have own+other bits together */
1739                 if (evmask == 0) /* default:drdy-{drv,own}+dbsy{drv,own} */
1740                         evmask = 0x1D;
1741                 break;
1742         case PMC_EV_P4_MACHINE_CLEAR:
1743                 /* only one bit is allowed to be set */
1744                 if ((evmask & (evmask - 1)) != 0)
1745                         return (-1);
1746                 if (evmask == 0) {
1747                         evmask = 0x1;   /* 'CLEAR' */
1748                         pmc_config->pm_caps |= PMC_CAP_QUALIFIER;
1749                 }
1750                 break;
1751         default:
1752                 if (evmask == 0 && pmask) {
1753                         for (pm = pmask; pm->pm_name; pm++)
1754                                 evmask |= pm->pm_value;
1755                         pmc_config->pm_caps |= PMC_CAP_QUALIFIER;
1756                 }
1757         }
1758
1759         pmc_config->pm_md.pm_p4.pm_p4_escrconfig =
1760             P4_ESCR_TO_EVENT_MASK(evmask);
1761
1762         return (0);
1763 }
1764
1765 #endif
1766
1767 #if defined(__i386__)
1768
1769 /*
1770  * Pentium style PMCs
1771  */
1772
1773 static struct pmc_event_alias p5_aliases[] = {
1774         EV_ALIAS("branches",            "p5-taken-branches"),
1775         EV_ALIAS("cycles",              "tsc"),
1776         EV_ALIAS("dc-misses",           "p5-data-read-miss-or-write-miss"),
1777         EV_ALIAS("ic-misses",           "p5-code-cache-miss"),
1778         EV_ALIAS("instructions",        "p5-instructions-executed"),
1779         EV_ALIAS("interrupts",          "p5-hardware-interrupts"),
1780         EV_ALIAS("unhalted-cycles",
1781             "p5-number-of-cycles-not-in-halt-state"),
1782         EV_ALIAS(NULL, NULL)
1783 };
1784
1785 static int
1786 p5_allocate_pmc(enum pmc_event pe, char *ctrspec,
1787     struct pmc_op_pmcallocate *pmc_config)
1788 {
1789         return (-1 || pe || ctrspec || pmc_config); /* shut up gcc */
1790 }
1791
1792 /*
1793  * Pentium Pro style PMCs.  These PMCs are found in Pentium II, Pentium III,
1794  * and Pentium M CPUs.
1795  */
1796
1797 static struct pmc_event_alias p6_aliases[] = {
1798         EV_ALIAS("branches",            "p6-br-inst-retired"),
1799         EV_ALIAS("branch-mispredicts",  "p6-br-miss-pred-retired"),
1800         EV_ALIAS("cycles",              "tsc"),
1801         EV_ALIAS("dc-misses",           "p6-dcu-lines-in"),
1802         EV_ALIAS("ic-misses",           "p6-ifu-fetch-miss"),
1803         EV_ALIAS("instructions",        "p6-inst-retired"),
1804         EV_ALIAS("interrupts",          "p6-hw-int-rx"),
1805         EV_ALIAS("unhalted-cycles",     "p6-cpu-clk-unhalted"),
1806         EV_ALIAS(NULL, NULL)
1807 };
1808
1809 #define P6_KW_CMASK     "cmask"
1810 #define P6_KW_EDGE      "edge"
1811 #define P6_KW_INV       "inv"
1812 #define P6_KW_OS        "os"
1813 #define P6_KW_UMASK     "umask"
1814 #define P6_KW_USR       "usr"
1815
1816 static struct pmc_masks p6_mask_mesi[] = {
1817         PMCMASK(m,      0x01),
1818         PMCMASK(e,      0x02),
1819         PMCMASK(s,      0x04),
1820         PMCMASK(i,      0x08),
1821         NULLMASK
1822 };
1823
1824 static struct pmc_masks p6_mask_mesihw[] = {
1825         PMCMASK(m,      0x01),
1826         PMCMASK(e,      0x02),
1827         PMCMASK(s,      0x04),
1828         PMCMASK(i,      0x08),
1829         PMCMASK(nonhw,  0x00),
1830         PMCMASK(hw,     0x10),
1831         PMCMASK(both,   0x30),
1832         NULLMASK
1833 };
1834
1835 static struct pmc_masks p6_mask_hw[] = {
1836         PMCMASK(nonhw,  0x00),
1837         PMCMASK(hw,     0x10),
1838         PMCMASK(both,   0x30),
1839         NULLMASK
1840 };
1841
1842 static struct pmc_masks p6_mask_any[] = {
1843         PMCMASK(self,   0x00),
1844         PMCMASK(any,    0x20),
1845         NULLMASK
1846 };
1847
1848 static struct pmc_masks p6_mask_ekp[] = {
1849         PMCMASK(nta,    0x00),
1850         PMCMASK(t1,     0x01),
1851         PMCMASK(t2,     0x02),
1852         PMCMASK(wos,    0x03),
1853         NULLMASK
1854 };
1855
1856 static struct pmc_masks p6_mask_pps[] = {
1857         PMCMASK(packed-and-scalar, 0x00),
1858         PMCMASK(scalar, 0x01),
1859         NULLMASK
1860 };
1861
1862 static struct pmc_masks p6_mask_mite[] = {
1863         PMCMASK(packed-multiply,         0x01),
1864         PMCMASK(packed-shift,           0x02),
1865         PMCMASK(pack,                   0x04),
1866         PMCMASK(unpack,                 0x08),
1867         PMCMASK(packed-logical,         0x10),
1868         PMCMASK(packed-arithmetic,      0x20),
1869         NULLMASK
1870 };
1871
1872 static struct pmc_masks p6_mask_fmt[] = {
1873         PMCMASK(mmxtofp,        0x00),
1874         PMCMASK(fptommx,        0x01),
1875         NULLMASK
1876 };
1877
1878 static struct pmc_masks p6_mask_sr[] = {
1879         PMCMASK(es,     0x01),
1880         PMCMASK(ds,     0x02),
1881         PMCMASK(fs,     0x04),
1882         PMCMASK(gs,     0x08),
1883         NULLMASK
1884 };
1885
1886 static struct pmc_masks p6_mask_eet[] = {
1887         PMCMASK(all,    0x00),
1888         PMCMASK(freq,   0x02),
1889         NULLMASK
1890 };
1891
1892 static struct pmc_masks p6_mask_efur[] = {
1893         PMCMASK(all,    0x00),
1894         PMCMASK(loadop, 0x01),
1895         PMCMASK(stdsta, 0x02),
1896         NULLMASK
1897 };
1898
1899 static struct pmc_masks p6_mask_essir[] = {
1900         PMCMASK(sse-packed-single,      0x00),
1901         PMCMASK(sse-packed-single-scalar-single, 0x01),
1902         PMCMASK(sse2-packed-double,     0x02),
1903         PMCMASK(sse2-scalar-double,     0x03),
1904         NULLMASK
1905 };
1906
1907 static struct pmc_masks p6_mask_esscir[] = {
1908         PMCMASK(sse-packed-single,      0x00),
1909         PMCMASK(sse-scalar-single,      0x01),
1910         PMCMASK(sse2-packed-double,     0x02),
1911         PMCMASK(sse2-scalar-double,     0x03),
1912         NULLMASK
1913 };
1914
1915 /* P6 event parser */
1916 static int
1917 p6_allocate_pmc(enum pmc_event pe, char *ctrspec,
1918     struct pmc_op_pmcallocate *pmc_config)
1919 {
1920         char *e, *p, *q;
1921         uint32_t evmask;
1922         int count, n;
1923         const struct pmc_masks *pm, *pmask;
1924
1925         pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE);
1926         pmc_config->pm_md.pm_ppro.pm_ppro_config = 0;
1927
1928         evmask = 0;
1929
1930 #define P6MASKSET(M)    pmask = p6_mask_ ## M
1931
1932         switch(pe) {
1933         case PMC_EV_P6_L2_IFETCH:       P6MASKSET(mesi); break;
1934         case PMC_EV_P6_L2_LD:           P6MASKSET(mesi); break;
1935         case PMC_EV_P6_L2_ST:           P6MASKSET(mesi); break;
1936         case PMC_EV_P6_L2_RQSTS:        P6MASKSET(mesi); break;
1937         case PMC_EV_P6_BUS_DRDY_CLOCKS:
1938         case PMC_EV_P6_BUS_LOCK_CLOCKS:
1939         case PMC_EV_P6_BUS_TRAN_BRD:
1940         case PMC_EV_P6_BUS_TRAN_RFO:
1941         case PMC_EV_P6_BUS_TRANS_WB:
1942         case PMC_EV_P6_BUS_TRAN_IFETCH:
1943         case PMC_EV_P6_BUS_TRAN_INVAL:
1944         case PMC_EV_P6_BUS_TRAN_PWR:
1945         case PMC_EV_P6_BUS_TRANS_P:
1946         case PMC_EV_P6_BUS_TRANS_IO:
1947         case PMC_EV_P6_BUS_TRAN_DEF:
1948         case PMC_EV_P6_BUS_TRAN_BURST:
1949         case PMC_EV_P6_BUS_TRAN_ANY:
1950         case PMC_EV_P6_BUS_TRAN_MEM:
1951                 P6MASKSET(any); break;
1952         case PMC_EV_P6_EMON_KNI_PREF_DISPATCHED:
1953         case PMC_EV_P6_EMON_KNI_PREF_MISS:
1954                 P6MASKSET(ekp); break;
1955         case PMC_EV_P6_EMON_KNI_INST_RETIRED:
1956         case PMC_EV_P6_EMON_KNI_COMP_INST_RET:
1957                 P6MASKSET(pps); break;
1958         case PMC_EV_P6_MMX_INSTR_TYPE_EXEC:
1959                 P6MASKSET(mite); break;
1960         case PMC_EV_P6_FP_MMX_TRANS:
1961                 P6MASKSET(fmt); break;
1962         case PMC_EV_P6_SEG_RENAME_STALLS:
1963         case PMC_EV_P6_SEG_REG_RENAMES:
1964                 P6MASKSET(sr);  break;
1965         case PMC_EV_P6_EMON_EST_TRANS:
1966                 P6MASKSET(eet); break;
1967         case PMC_EV_P6_EMON_FUSED_UOPS_RET:
1968                 P6MASKSET(efur); break;
1969         case PMC_EV_P6_EMON_SSE_SSE2_INST_RETIRED:
1970                 P6MASKSET(essir); break;
1971         case PMC_EV_P6_EMON_SSE_SSE2_COMP_INST_RETIRED:
1972                 P6MASKSET(esscir); break;
1973         default:
1974                 pmask = NULL;
1975                 break;
1976         }
1977
1978         /* Pentium M PMCs have a few events with different semantics */
1979         if (cpu_info.pm_cputype == PMC_CPU_INTEL_PM) {
1980                 if (pe == PMC_EV_P6_L2_LD ||
1981                     pe == PMC_EV_P6_L2_LINES_IN ||
1982                     pe == PMC_EV_P6_L2_LINES_OUT)
1983                         P6MASKSET(mesihw);
1984                 else if (pe == PMC_EV_P6_L2_M_LINES_OUTM)
1985                         P6MASKSET(hw);
1986         }
1987
1988         /* Parse additional modifiers if present */
1989         while ((p = strsep(&ctrspec, ",")) != NULL) {
1990                 if (KWPREFIXMATCH(p, P6_KW_CMASK "=")) {
1991                         q = strchr(p, '=');
1992                         if (*++q == '\0') /* skip '=' */
1993                                 return (-1);
1994                         count = strtol(q, &e, 0);
1995                         if (e == q || *e != '\0')
1996                                 return (-1);
1997                         pmc_config->pm_caps |= PMC_CAP_THRESHOLD;
1998                         pmc_config->pm_md.pm_ppro.pm_ppro_config |=
1999                             P6_EVSEL_TO_CMASK(count);
2000                 } else if (KWMATCH(p, P6_KW_EDGE)) {
2001                         pmc_config->pm_caps |= PMC_CAP_EDGE;
2002                 } else if (KWMATCH(p, P6_KW_INV)) {
2003                         pmc_config->pm_caps |= PMC_CAP_INVERT;
2004                 } else if (KWMATCH(p, P6_KW_OS)) {
2005                         pmc_config->pm_caps |= PMC_CAP_SYSTEM;
2006                 } else if (KWPREFIXMATCH(p, P6_KW_UMASK "=")) {
2007                         evmask = 0;
2008                         if ((n = pmc_parse_mask(pmask, p, &evmask)) < 0)
2009                                 return (-1);
2010                         if ((pe == PMC_EV_P6_BUS_DRDY_CLOCKS ||
2011                              pe == PMC_EV_P6_BUS_LOCK_CLOCKS ||
2012                              pe == PMC_EV_P6_BUS_TRAN_BRD ||
2013                              pe == PMC_EV_P6_BUS_TRAN_RFO ||
2014                              pe == PMC_EV_P6_BUS_TRAN_IFETCH ||
2015                              pe == PMC_EV_P6_BUS_TRAN_INVAL ||
2016                              pe == PMC_EV_P6_BUS_TRAN_PWR ||
2017                              pe == PMC_EV_P6_BUS_TRAN_DEF ||
2018                              pe == PMC_EV_P6_BUS_TRAN_BURST ||
2019                              pe == PMC_EV_P6_BUS_TRAN_ANY ||
2020                              pe == PMC_EV_P6_BUS_TRAN_MEM ||
2021                              pe == PMC_EV_P6_BUS_TRANS_IO ||
2022                              pe == PMC_EV_P6_BUS_TRANS_P ||
2023                              pe == PMC_EV_P6_BUS_TRANS_WB ||
2024                              pe == PMC_EV_P6_EMON_EST_TRANS ||
2025                              pe == PMC_EV_P6_EMON_FUSED_UOPS_RET ||
2026                              pe == PMC_EV_P6_EMON_KNI_COMP_INST_RET ||
2027                              pe == PMC_EV_P6_EMON_KNI_INST_RETIRED ||
2028                              pe == PMC_EV_P6_EMON_KNI_PREF_DISPATCHED ||
2029                              pe == PMC_EV_P6_EMON_KNI_PREF_MISS ||
2030                              pe == PMC_EV_P6_EMON_SSE_SSE2_COMP_INST_RETIRED ||
2031                              pe == PMC_EV_P6_EMON_SSE_SSE2_INST_RETIRED ||
2032                              pe == PMC_EV_P6_FP_MMX_TRANS)
2033                             && (n > 1)) /* Only one mask keyword is allowed. */
2034                                 return (-1);
2035                         pmc_config->pm_caps |= PMC_CAP_QUALIFIER;
2036                 } else if (KWMATCH(p, P6_KW_USR)) {
2037                         pmc_config->pm_caps |= PMC_CAP_USER;
2038                 } else
2039                         return (-1);
2040         }
2041
2042         /* post processing */
2043         switch (pe) {
2044
2045                 /*
2046                  * The following events default to an evmask of 0
2047                  */
2048
2049                 /* default => 'self' */
2050         case PMC_EV_P6_BUS_DRDY_CLOCKS:
2051         case PMC_EV_P6_BUS_LOCK_CLOCKS:
2052         case PMC_EV_P6_BUS_TRAN_BRD:
2053         case PMC_EV_P6_BUS_TRAN_RFO:
2054         case PMC_EV_P6_BUS_TRANS_WB:
2055         case PMC_EV_P6_BUS_TRAN_IFETCH:
2056         case PMC_EV_P6_BUS_TRAN_INVAL:
2057         case PMC_EV_P6_BUS_TRAN_PWR:
2058         case PMC_EV_P6_BUS_TRANS_P:
2059         case PMC_EV_P6_BUS_TRANS_IO:
2060         case PMC_EV_P6_BUS_TRAN_DEF:
2061         case PMC_EV_P6_BUS_TRAN_BURST:
2062         case PMC_EV_P6_BUS_TRAN_ANY:
2063         case PMC_EV_P6_BUS_TRAN_MEM:
2064
2065                 /* default => 'nta' */
2066         case PMC_EV_P6_EMON_KNI_PREF_DISPATCHED:
2067         case PMC_EV_P6_EMON_KNI_PREF_MISS:
2068
2069                 /* default => 'packed and scalar' */
2070         case PMC_EV_P6_EMON_KNI_INST_RETIRED:
2071         case PMC_EV_P6_EMON_KNI_COMP_INST_RET:
2072
2073                 /* default => 'mmx to fp transitions' */
2074         case PMC_EV_P6_FP_MMX_TRANS:
2075
2076                 /* default => 'SSE Packed Single' */
2077         case PMC_EV_P6_EMON_SSE_SSE2_INST_RETIRED:
2078         case PMC_EV_P6_EMON_SSE_SSE2_COMP_INST_RETIRED:
2079
2080                 /* default => 'all fused micro-ops' */
2081         case PMC_EV_P6_EMON_FUSED_UOPS_RET:
2082
2083                 /* default => 'all transitions' */
2084         case PMC_EV_P6_EMON_EST_TRANS:
2085                 break;
2086
2087         case PMC_EV_P6_MMX_UOPS_EXEC:
2088                 evmask = 0x0F;          /* only value allowed */
2089                 break;
2090
2091         default:
2092                 /*
2093                  * For all other events, set the default event mask
2094                  * to a logical OR of all the allowed event mask bits.
2095                  */
2096                 if (evmask == 0 && pmask) {
2097                         for (pm = pmask; pm->pm_name; pm++)
2098                                 evmask |= pm->pm_value;
2099                         pmc_config->pm_caps |= PMC_CAP_QUALIFIER;
2100                 }
2101
2102                 break;
2103         }
2104
2105         if (pmc_config->pm_caps & PMC_CAP_QUALIFIER)
2106                 pmc_config->pm_md.pm_ppro.pm_ppro_config |=
2107                     P6_EVSEL_TO_UMASK(evmask);
2108
2109         return (0);
2110 }
2111
2112 #endif
2113
2114 #if     defined(__i386__) || defined(__amd64__)
2115 static int
2116 tsc_allocate_pmc(enum pmc_event pe, char *ctrspec,
2117     struct pmc_op_pmcallocate *pmc_config)
2118 {
2119         if (pe != PMC_EV_TSC_TSC)
2120                 return (-1);
2121
2122         /* TSC events must be unqualified. */
2123         if (ctrspec && *ctrspec != '\0')
2124                 return (-1);
2125
2126         pmc_config->pm_md.pm_amd.pm_amd_config = 0;
2127         pmc_config->pm_caps |= PMC_CAP_READ;
2128
2129         return (0);
2130 }
2131 #endif
2132
2133 /*
2134  * Match an event name `name' with its canonical form.
2135  *
2136  * Matches are case insensitive and spaces, periods, underscores and
2137  * hyphen characters are considered to match each other.
2138  *
2139  * Returns 1 for a match, 0 otherwise.
2140  */
2141
2142 static int
2143 pmc_match_event_name(const char *name, const char *canonicalname)
2144 {
2145         int cc, nc;
2146         const unsigned char *c, *n;
2147
2148         c = (const unsigned char *) canonicalname;
2149         n = (const unsigned char *) name;
2150
2151         for (; (nc = *n) && (cc = *c); n++, c++) {
2152
2153                 if ((nc == ' ' || nc == '_' || nc == '-' || nc == '.') &&
2154                     (cc == ' ' || cc == '_' || cc == '-' || cc == '.'))
2155                         continue;
2156
2157                 if (toupper(nc) == toupper(cc))
2158                         continue;
2159
2160
2161                 return (0);
2162         }
2163
2164         if (*n == '\0' && *c == '\0')
2165                 return (1);
2166
2167         return (0);
2168 }
2169
2170 /*
2171  * Match an event name against all the event named supported by a
2172  * PMC class.
2173  *
2174  * Returns an event descriptor pointer on match or NULL otherwise.
2175  */
2176 static const struct pmc_event_descr *
2177 pmc_match_event_class(const char *name,
2178     const struct pmc_class_descr *pcd)
2179 {
2180         size_t n;
2181         const struct pmc_event_descr *ev;
2182
2183         ev = pcd->pm_evc_event_table;
2184         for (n = 0; n < pcd->pm_evc_event_table_size; n++, ev++)
2185                 if (pmc_match_event_name(name, ev->pm_ev_name))
2186                         return (ev);
2187
2188         return (NULL);
2189 }
2190
2191 static int
2192 pmc_mdep_is_compatible_class(enum pmc_class pc)
2193 {
2194         size_t n;
2195
2196         for (n = 0; n < pmc_mdep_class_list_size; n++)
2197                 if (pmc_mdep_class_list[n] == pc)
2198                         return (1);
2199         return (0);
2200 }
2201
2202 /*
2203  * API entry points
2204  */
2205
2206 int
2207 pmc_allocate(const char *ctrspec, enum pmc_mode mode,
2208     uint32_t flags, int cpu, pmc_id_t *pmcid)
2209 {
2210         size_t n;
2211         int retval;
2212         char *r, *spec_copy;
2213         const char *ctrname;
2214         const struct pmc_event_descr *ev;
2215         const struct pmc_event_alias *alias;
2216         struct pmc_op_pmcallocate pmc_config;
2217         const struct pmc_class_descr *pcd;
2218
2219         spec_copy = NULL;
2220         retval    = -1;
2221
2222         if (mode != PMC_MODE_SS && mode != PMC_MODE_TS &&
2223             mode != PMC_MODE_SC && mode != PMC_MODE_TC) {
2224                 errno = EINVAL;
2225                 goto out;
2226         }
2227
2228         /* replace an event alias with the canonical event specifier */
2229         if (pmc_mdep_event_aliases)
2230                 for (alias = pmc_mdep_event_aliases; alias->pm_alias; alias++)
2231                         if (!strcasecmp(ctrspec, alias->pm_alias)) {
2232                                 spec_copy = strdup(alias->pm_spec);
2233                                 break;
2234                         }
2235
2236         if (spec_copy == NULL)
2237                 spec_copy = strdup(ctrspec);
2238
2239         r = spec_copy;
2240         ctrname = strsep(&r, ",");
2241
2242         /*
2243          * If a explicit class prefix was given by the user, restrict the
2244          * search for the event to the specified PMC class.
2245          */
2246         ev = NULL;
2247         for (n = 0; n < PMC_CLASS_TABLE_SIZE; n++) {
2248                 pcd = pmc_class_table[n];
2249                 if (pmc_mdep_is_compatible_class(pcd->pm_evc_class) &&
2250                     strncasecmp(ctrname, pcd->pm_evc_name,
2251                                 pcd->pm_evc_name_size) == 0) {
2252                         if ((ev = pmc_match_event_class(ctrname +
2253                             pcd->pm_evc_name_size, pcd)) == NULL) {
2254                                 errno = EINVAL;
2255                                 goto out;
2256                         }
2257                         break;
2258                 }
2259         }
2260
2261         /*
2262          * Otherwise, search for this event in all compatible PMC
2263          * classes.
2264          */
2265         for (n = 0; ev == NULL && n < PMC_CLASS_TABLE_SIZE; n++) {
2266                 pcd = pmc_class_table[n];
2267                 if (pmc_mdep_is_compatible_class(pcd->pm_evc_class))
2268                         ev = pmc_match_event_class(ctrname, pcd);
2269         }
2270
2271         if (ev == NULL) {
2272                 errno = EINVAL;
2273                 goto out;
2274         }
2275
2276         bzero(&pmc_config, sizeof(pmc_config));
2277         pmc_config.pm_ev    = ev->pm_ev_code;
2278         pmc_config.pm_class = pcd->pm_evc_class;
2279         pmc_config.pm_cpu   = cpu;
2280         pmc_config.pm_mode  = mode;
2281         pmc_config.pm_flags = flags;
2282
2283         if (PMC_IS_SAMPLING_MODE(mode))
2284                 pmc_config.pm_caps |= PMC_CAP_INTERRUPT;
2285
2286         if (pcd->pm_evc_allocate_pmc(ev->pm_ev_code, r, &pmc_config) < 0) {
2287                 errno = EINVAL;
2288                 goto out;
2289         }
2290
2291         if (PMC_CALL(PMCALLOCATE, &pmc_config) < 0)
2292                 goto out;
2293
2294         *pmcid = pmc_config.pm_pmcid;
2295
2296         retval = 0;
2297
2298  out:
2299         if (spec_copy)
2300                 free(spec_copy);
2301
2302         return (retval);
2303 }
2304
2305 int
2306 pmc_attach(pmc_id_t pmc, pid_t pid)
2307 {
2308         struct pmc_op_pmcattach pmc_attach_args;
2309
2310         pmc_attach_args.pm_pmc = pmc;
2311         pmc_attach_args.pm_pid = pid;
2312
2313         return (PMC_CALL(PMCATTACH, &pmc_attach_args));
2314 }
2315
2316 int
2317 pmc_capabilities(pmc_id_t pmcid, uint32_t *caps)
2318 {
2319         unsigned int i;
2320         enum pmc_class cl;
2321
2322         cl = PMC_ID_TO_CLASS(pmcid);
2323         for (i = 0; i < cpu_info.pm_nclass; i++)
2324                 if (cpu_info.pm_classes[i].pm_class == cl) {
2325                         *caps = cpu_info.pm_classes[i].pm_caps;
2326                         return (0);
2327                 }
2328         errno = EINVAL;
2329         return (-1);
2330 }
2331
2332 int
2333 pmc_configure_logfile(int fd)
2334 {
2335         struct pmc_op_configurelog cla;
2336
2337         cla.pm_logfd = fd;
2338         if (PMC_CALL(CONFIGURELOG, &cla) < 0)
2339                 return (-1);
2340         return (0);
2341 }
2342
2343 int
2344 pmc_cpuinfo(const struct pmc_cpuinfo **pci)
2345 {
2346         if (pmc_syscall == -1) {
2347                 errno = ENXIO;
2348                 return (-1);
2349         }
2350
2351         *pci = &cpu_info;
2352         return (0);
2353 }
2354
2355 int
2356 pmc_detach(pmc_id_t pmc, pid_t pid)
2357 {
2358         struct pmc_op_pmcattach pmc_detach_args;
2359
2360         pmc_detach_args.pm_pmc = pmc;
2361         pmc_detach_args.pm_pid = pid;
2362         return (PMC_CALL(PMCDETACH, &pmc_detach_args));
2363 }
2364
2365 int
2366 pmc_disable(int cpu, int pmc)
2367 {
2368         struct pmc_op_pmcadmin ssa;
2369
2370         ssa.pm_cpu = cpu;
2371         ssa.pm_pmc = pmc;
2372         ssa.pm_state = PMC_STATE_DISABLED;
2373         return (PMC_CALL(PMCADMIN, &ssa));
2374 }
2375
2376 int
2377 pmc_enable(int cpu, int pmc)
2378 {
2379         struct pmc_op_pmcadmin ssa;
2380
2381         ssa.pm_cpu = cpu;
2382         ssa.pm_pmc = pmc;
2383         ssa.pm_state = PMC_STATE_FREE;
2384         return (PMC_CALL(PMCADMIN, &ssa));
2385 }
2386
2387 /*
2388  * Return a list of events known to a given PMC class.  'cl' is the
2389  * PMC class identifier, 'eventnames' is the returned list of 'const
2390  * char *' pointers pointing to the names of the events. 'nevents' is
2391  * the number of event name pointers returned.
2392  *
2393  * The space for 'eventnames' is allocated using malloc(3).  The caller
2394  * is responsible for freeing this space when done.
2395  */
2396 int
2397 pmc_event_names_of_class(enum pmc_class cl, const char ***eventnames,
2398     int *nevents)
2399 {
2400         int count;
2401         const char **names;
2402         const struct pmc_event_descr *ev;
2403
2404         switch (cl)
2405         {
2406         case PMC_CLASS_IAF:
2407                 ev = iaf_event_table;
2408                 count = PMC_EVENT_TABLE_SIZE(iaf);
2409                 break;
2410         case PMC_CLASS_IAP:
2411                 /*
2412                  * Return the most appropriate set of event name
2413                  * spellings for the current CPU.
2414                  */
2415                 switch (cpu_info.pm_cputype) {
2416                 default:
2417                 case PMC_CPU_INTEL_ATOM:
2418                         ev = atom_event_table;
2419                         count = PMC_EVENT_TABLE_SIZE(atom);
2420                         break;
2421                 case PMC_CPU_INTEL_CORE:
2422                         ev = core_event_table;
2423                         count = PMC_EVENT_TABLE_SIZE(core);
2424                         break;
2425                 case PMC_CPU_INTEL_CORE2:
2426                 case PMC_CPU_INTEL_CORE2EXTREME:
2427                         ev = core2_event_table;
2428                         count = PMC_EVENT_TABLE_SIZE(core2);
2429                         break;
2430                 case PMC_CPU_INTEL_COREI7:
2431                         ev = corei7_event_table;
2432                         count = PMC_EVENT_TABLE_SIZE(corei7);
2433                         break;
2434                 case PMC_CPU_INTEL_WESTMERE:
2435                         ev = westmere_event_table;
2436                         count = PMC_EVENT_TABLE_SIZE(westmere);
2437                         break;
2438                 }
2439                 break;
2440         case PMC_CLASS_UCF:
2441                 ev = ucf_event_table;
2442                 count = PMC_EVENT_TABLE_SIZE(ucf);
2443                 break;
2444         case PMC_CLASS_UCP:
2445                 /*
2446                  * Return the most appropriate set of event name
2447                  * spellings for the current CPU.
2448                  */
2449                 switch (cpu_info.pm_cputype) {
2450                 default:
2451                 case PMC_CPU_INTEL_COREI7:
2452                         ev = corei7uc_event_table;
2453                         count = PMC_EVENT_TABLE_SIZE(corei7uc);
2454                         break;
2455                 case PMC_CPU_INTEL_WESTMERE:
2456                         ev = westmereuc_event_table;
2457                         count = PMC_EVENT_TABLE_SIZE(westmereuc);
2458                         break;
2459                 }
2460                 break;
2461         case PMC_CLASS_TSC:
2462                 ev = tsc_event_table;
2463                 count = PMC_EVENT_TABLE_SIZE(tsc);
2464                 break;
2465         case PMC_CLASS_K7:
2466                 ev = k7_event_table;
2467                 count = PMC_EVENT_TABLE_SIZE(k7);
2468                 break;
2469         case PMC_CLASS_K8:
2470                 ev = k8_event_table;
2471                 count = PMC_EVENT_TABLE_SIZE(k8);
2472                 break;
2473         case PMC_CLASS_P4:
2474                 ev = p4_event_table;
2475                 count = PMC_EVENT_TABLE_SIZE(p4);
2476                 break;
2477         case PMC_CLASS_P5:
2478                 ev = p5_event_table;
2479                 count = PMC_EVENT_TABLE_SIZE(p5);
2480                 break;
2481         case PMC_CLASS_P6:
2482                 ev = p6_event_table;
2483                 count = PMC_EVENT_TABLE_SIZE(p6);
2484                 break;
2485         default:
2486                 errno = EINVAL;
2487                 return (-1);
2488         }
2489
2490         if ((names = malloc(count * sizeof(const char *))) == NULL)
2491                 return (-1);
2492
2493         *eventnames = names;
2494         *nevents = count;
2495
2496         for (;count--; ev++, names++)
2497                 *names = ev->pm_ev_name;
2498         return (0);
2499 }
2500
2501 int
2502 pmc_flush_logfile(void)
2503 {
2504         return (PMC_CALL(FLUSHLOG,0));
2505 }
2506
2507 int
2508 pmc_get_driver_stats(struct pmc_driverstats *ds)
2509 {
2510         struct pmc_op_getdriverstats gms;
2511
2512         if (PMC_CALL(GETDRIVERSTATS, &gms) < 0)
2513                 return (-1);
2514
2515         /* copy out fields in the current userland<->library interface */
2516         ds->pm_intr_ignored    = gms.pm_intr_ignored;
2517         ds->pm_intr_processed  = gms.pm_intr_processed;
2518         ds->pm_intr_bufferfull = gms.pm_intr_bufferfull;
2519         ds->pm_syscalls        = gms.pm_syscalls;
2520         ds->pm_syscall_errors  = gms.pm_syscall_errors;
2521         ds->pm_buffer_requests = gms.pm_buffer_requests;
2522         ds->pm_buffer_requests_failed = gms.pm_buffer_requests_failed;
2523         ds->pm_log_sweeps      = gms.pm_log_sweeps;
2524         return (0);
2525 }
2526
2527 int
2528 pmc_get_msr(pmc_id_t pmc, uint32_t *msr)
2529 {
2530         struct pmc_op_getmsr gm;
2531
2532         gm.pm_pmcid = pmc;
2533         if (PMC_CALL(PMCGETMSR, &gm) < 0)
2534                 return (-1);
2535         *msr = gm.pm_msr;
2536         return (0);
2537 }
2538
2539 int
2540 pmc_init(void)
2541 {
2542         int error, pmc_mod_id;
2543         unsigned int n;
2544         uint32_t abi_version;
2545         struct module_stat pmc_modstat;
2546         struct pmc_op_getcpuinfo op_cpu_info;
2547 #if defined(__amd64__) || defined(__i386__)
2548         int cpu_has_iaf_counters;
2549         unsigned int t;
2550 #endif
2551
2552         if (pmc_syscall != -1) /* already inited */
2553                 return (0);
2554
2555         /* retrieve the system call number from the KLD */
2556         if ((pmc_mod_id = modfind(PMC_MODULE_NAME)) < 0)
2557                 return (-1);
2558
2559         pmc_modstat.version = sizeof(struct module_stat);
2560         if ((error = modstat(pmc_mod_id, &pmc_modstat)) < 0)
2561                 return (-1);
2562
2563         pmc_syscall = pmc_modstat.data.intval;
2564
2565         /* check the kernel module's ABI against our compiled-in version */
2566         abi_version = PMC_VERSION;
2567         if (PMC_CALL(GETMODULEVERSION, &abi_version) < 0)
2568                 return (pmc_syscall = -1);
2569
2570         /* ignore patch & minor numbers for the comparision */
2571         if ((abi_version & 0xFF000000) != (PMC_VERSION & 0xFF000000)) {
2572                 errno  = EPROGMISMATCH;
2573                 return (pmc_syscall = -1);
2574         }
2575
2576         if (PMC_CALL(GETCPUINFO, &op_cpu_info) < 0)
2577                 return (pmc_syscall = -1);
2578
2579         cpu_info.pm_cputype = op_cpu_info.pm_cputype;
2580         cpu_info.pm_ncpu    = op_cpu_info.pm_ncpu;
2581         cpu_info.pm_npmc    = op_cpu_info.pm_npmc;
2582         cpu_info.pm_nclass  = op_cpu_info.pm_nclass;
2583         for (n = 0; n < cpu_info.pm_nclass; n++)
2584                 cpu_info.pm_classes[n] = op_cpu_info.pm_classes[n];
2585
2586         pmc_class_table = malloc(PMC_CLASS_TABLE_SIZE *
2587             sizeof(struct pmc_class_descr *));
2588
2589         if (pmc_class_table == NULL)
2590                 return (-1);
2591
2592         for (n = 0; n < PMC_CLASS_TABLE_SIZE; n++)
2593                 pmc_class_table[n] = NULL;
2594
2595         /*
2596          * Fill in the class table.
2597          */
2598         n = 0;
2599 #if defined(__amd64__) || defined(__i386__)
2600         pmc_class_table[n++] = &tsc_class_table_descr;
2601
2602         /*
2603          * Check if this CPU has fixed function counters.
2604          */
2605         cpu_has_iaf_counters = 0;
2606         for (t = 0; t < cpu_info.pm_nclass; t++)
2607                 if (cpu_info.pm_classes[t].pm_class == PMC_CLASS_IAF)
2608                         cpu_has_iaf_counters = 1;
2609 #endif
2610
2611 #define PMC_MDEP_INIT(C) do {                                   \
2612                 pmc_mdep_event_aliases    = C##_aliases;        \
2613                 pmc_mdep_class_list  = C##_pmc_classes;         \
2614                 pmc_mdep_class_list_size =                      \
2615                     PMC_TABLE_SIZE(C##_pmc_classes);            \
2616         } while (0)
2617
2618 #define PMC_MDEP_INIT_INTEL_V2(C) do {                                  \
2619                 PMC_MDEP_INIT(C);                                       \
2620                 if (cpu_has_iaf_counters)                               \
2621                         pmc_class_table[n++] = &iaf_class_table_descr;  \
2622                 else                                                    \
2623                         pmc_mdep_event_aliases =                        \
2624                                 C##_aliases_without_iaf;                \
2625                 pmc_class_table[n] = &C##_class_table_descr;            \
2626         } while (0)
2627
2628         /* Configure the event name parser. */
2629         switch (cpu_info.pm_cputype) {
2630 #if defined(__i386__)
2631         case PMC_CPU_AMD_K7:
2632                 PMC_MDEP_INIT(k7);
2633                 pmc_class_table[n] = &k7_class_table_descr;
2634                 break;
2635         case PMC_CPU_INTEL_P5:
2636                 PMC_MDEP_INIT(p5);
2637                 pmc_class_table[n]  = &p5_class_table_descr;
2638                 break;
2639         case PMC_CPU_INTEL_P6:          /* P6 ... Pentium M CPUs have */
2640         case PMC_CPU_INTEL_PII:         /* similar PMCs. */
2641         case PMC_CPU_INTEL_PIII:
2642         case PMC_CPU_INTEL_PM:
2643                 PMC_MDEP_INIT(p6);
2644                 pmc_class_table[n] = &p6_class_table_descr;
2645                 break;
2646 #endif
2647 #if defined(__amd64__) || defined(__i386__)
2648         case PMC_CPU_AMD_K8:
2649                 PMC_MDEP_INIT(k8);
2650                 pmc_class_table[n] = &k8_class_table_descr;
2651                 break;
2652         case PMC_CPU_INTEL_ATOM:
2653                 PMC_MDEP_INIT_INTEL_V2(atom);
2654                 break;
2655         case PMC_CPU_INTEL_CORE:
2656                 PMC_MDEP_INIT(core);
2657                 pmc_class_table[n] = &core_class_table_descr;
2658                 break;
2659         case PMC_CPU_INTEL_CORE2:
2660         case PMC_CPU_INTEL_CORE2EXTREME:
2661                 PMC_MDEP_INIT_INTEL_V2(core2);
2662                 break;
2663         case PMC_CPU_INTEL_COREI7:
2664                 pmc_class_table[n++] = &ucf_class_table_descr;
2665                 pmc_class_table[n++] = &corei7uc_class_table_descr;
2666                 PMC_MDEP_INIT_INTEL_V2(corei7);
2667                 break;
2668         case PMC_CPU_INTEL_WESTMERE:
2669                 pmc_class_table[n++] = &ucf_class_table_descr;
2670                 pmc_class_table[n++] = &westmereuc_class_table_descr;
2671                 PMC_MDEP_INIT_INTEL_V2(westmere);
2672                 break;
2673         case PMC_CPU_INTEL_PIV:
2674                 PMC_MDEP_INIT(p4);
2675                 pmc_class_table[n] = &p4_class_table_descr;
2676                 break;
2677 #endif
2678
2679
2680         default:
2681                 /*
2682                  * Some kind of CPU this version of the library knows nothing
2683                  * about.  This shouldn't happen since the abi version check
2684                  * should have caught this.
2685                  */
2686                 errno = ENXIO;
2687                 return (pmc_syscall = -1);
2688         }
2689
2690         return (0);
2691 }
2692
2693 const char *
2694 pmc_name_of_capability(enum pmc_caps cap)
2695 {
2696         int i;
2697
2698         /*
2699          * 'cap' should have a single bit set and should be in
2700          * range.
2701          */
2702         if ((cap & (cap - 1)) || cap < PMC_CAP_FIRST ||
2703             cap > PMC_CAP_LAST) {
2704                 errno = EINVAL;
2705                 return (NULL);
2706         }
2707
2708         i = ffs(cap);
2709         return (pmc_capability_names[i - 1]);
2710 }
2711
2712 const char *
2713 pmc_name_of_class(enum pmc_class pc)
2714 {
2715         if ((int) pc >= PMC_CLASS_FIRST &&
2716             pc <= PMC_CLASS_LAST)
2717                 return (pmc_class_names[pc]);
2718
2719         errno = EINVAL;
2720         return (NULL);
2721 }
2722
2723 const char *
2724 pmc_name_of_cputype(enum pmc_cputype cp)
2725 {
2726         size_t n;
2727
2728         for (n = 0; n < PMC_TABLE_SIZE(pmc_cputype_names); n++)
2729                 if (cp == pmc_cputype_names[n].pm_cputype)
2730                         return (pmc_cputype_names[n].pm_name);
2731
2732         errno = EINVAL;
2733         return (NULL);
2734 }
2735
2736 const char *
2737 pmc_name_of_disposition(enum pmc_disp pd)
2738 {
2739         if ((int) pd >= PMC_DISP_FIRST &&
2740             pd <= PMC_DISP_LAST)
2741                 return (pmc_disposition_names[pd]);
2742
2743         errno = EINVAL;
2744         return (NULL);
2745 }
2746
2747 const char *
2748 _pmc_name_of_event(enum pmc_event pe, enum pmc_cputype cpu)
2749 {
2750         const struct pmc_event_descr *ev, *evfence;
2751
2752         ev = evfence = NULL;
2753         if (pe >= PMC_EV_IAF_FIRST && pe <= PMC_EV_IAF_LAST) {
2754                 ev = iaf_event_table;
2755                 evfence = iaf_event_table + PMC_EVENT_TABLE_SIZE(iaf);
2756         } else if (pe >= PMC_EV_IAP_FIRST && pe <= PMC_EV_IAP_LAST) {
2757                 switch (cpu) {
2758                 case PMC_CPU_INTEL_ATOM:
2759                         ev = atom_event_table;
2760                         evfence = atom_event_table + PMC_EVENT_TABLE_SIZE(atom);
2761                         break;
2762                 case PMC_CPU_INTEL_CORE:
2763                         ev = core_event_table;
2764                         evfence = core_event_table + PMC_EVENT_TABLE_SIZE(core);
2765                         break;
2766                 case PMC_CPU_INTEL_CORE2:
2767                 case PMC_CPU_INTEL_CORE2EXTREME:
2768                         ev = core2_event_table;
2769                         evfence = core2_event_table + PMC_EVENT_TABLE_SIZE(core2);
2770                         break;
2771                 case PMC_CPU_INTEL_COREI7:
2772                         ev = corei7_event_table;
2773                         evfence = corei7_event_table + PMC_EVENT_TABLE_SIZE(corei7);
2774                         break;
2775                 case PMC_CPU_INTEL_WESTMERE:
2776                         ev = westmere_event_table;
2777                         evfence = westmere_event_table + PMC_EVENT_TABLE_SIZE(westmere);
2778                         break;
2779                 default:        /* Unknown CPU type. */
2780                         break;
2781                 }
2782         } else if (pe >= PMC_EV_UCF_FIRST && pe <= PMC_EV_UCF_LAST) {
2783                 ev = ucf_event_table;
2784                 evfence = ucf_event_table + PMC_EVENT_TABLE_SIZE(ucf);
2785         } else if (pe >= PMC_EV_UCP_FIRST && pe <= PMC_EV_UCP_LAST) {
2786                 switch (cpu) {
2787                 case PMC_CPU_INTEL_COREI7:
2788                         ev = corei7uc_event_table;
2789                         evfence = corei7uc_event_table + PMC_EVENT_TABLE_SIZE(corei7uc);
2790                         break;
2791                 case PMC_CPU_INTEL_WESTMERE:
2792                         ev = westmereuc_event_table;
2793                         evfence = westmereuc_event_table + PMC_EVENT_TABLE_SIZE(westmereuc);
2794                         break;
2795                 default:        /* Unknown CPU type. */
2796                         break;
2797                 }
2798         } else if (pe >= PMC_EV_K7_FIRST && pe <= PMC_EV_K7_LAST) {
2799                 ev = k7_event_table;
2800                 evfence = k7_event_table + PMC_EVENT_TABLE_SIZE(k7);
2801         } else if (pe >= PMC_EV_K8_FIRST && pe <= PMC_EV_K8_LAST) {
2802                 ev = k8_event_table;
2803                 evfence = k8_event_table + PMC_EVENT_TABLE_SIZE(k8);
2804         } else if (pe >= PMC_EV_P4_FIRST && pe <= PMC_EV_P4_LAST) {
2805                 ev = p4_event_table;
2806                 evfence = p4_event_table + PMC_EVENT_TABLE_SIZE(p4);
2807         } else if (pe >= PMC_EV_P5_FIRST && pe <= PMC_EV_P5_LAST) {
2808                 ev = p5_event_table;
2809                 evfence = p5_event_table + PMC_EVENT_TABLE_SIZE(p5);
2810         } else if (pe >= PMC_EV_P6_FIRST && pe <= PMC_EV_P6_LAST) {
2811                 ev = p6_event_table;
2812                 evfence = p6_event_table + PMC_EVENT_TABLE_SIZE(p6);
2813         } else if (pe == PMC_EV_TSC_TSC) {
2814                 ev = tsc_event_table;
2815                 evfence = tsc_event_table + PMC_EVENT_TABLE_SIZE(tsc);
2816         }
2817
2818         for (; ev != evfence; ev++)
2819                 if (pe == ev->pm_ev_code)
2820                         return (ev->pm_ev_name);
2821
2822         return (NULL);
2823 }
2824
2825 const char *
2826 pmc_name_of_event(enum pmc_event pe)
2827 {
2828         const char *n;
2829
2830         if ((n = _pmc_name_of_event(pe, cpu_info.pm_cputype)) != NULL)
2831                 return (n);
2832
2833         errno = EINVAL;
2834         return (NULL);
2835 }
2836
2837 const char *
2838 pmc_name_of_mode(enum pmc_mode pm)
2839 {
2840         if ((int) pm >= PMC_MODE_FIRST &&
2841             pm <= PMC_MODE_LAST)
2842                 return (pmc_mode_names[pm]);
2843
2844         errno = EINVAL;
2845         return (NULL);
2846 }
2847
2848 const char *
2849 pmc_name_of_state(enum pmc_state ps)
2850 {
2851         if ((int) ps >= PMC_STATE_FIRST &&
2852             ps <= PMC_STATE_LAST)
2853                 return (pmc_state_names[ps]);
2854
2855         errno = EINVAL;
2856         return (NULL);
2857 }
2858
2859 int
2860 pmc_ncpu(void)
2861 {
2862         if (pmc_syscall == -1) {
2863                 errno = ENXIO;
2864                 return (-1);
2865         }
2866
2867         return (cpu_info.pm_ncpu);
2868 }
2869
2870 int
2871 pmc_npmc(int cpu)
2872 {
2873         if (pmc_syscall == -1) {
2874                 errno = ENXIO;
2875                 return (-1);
2876         }
2877
2878         if (cpu < 0 || cpu >= (int) cpu_info.pm_ncpu) {
2879                 errno = EINVAL;
2880                 return (-1);
2881         }
2882
2883         return (cpu_info.pm_npmc);
2884 }
2885
2886 int
2887 pmc_pmcinfo(int cpu, struct pmc_pmcinfo **ppmci)
2888 {
2889         int nbytes, npmc;
2890         struct pmc_op_getpmcinfo *pmci;
2891
2892         if ((npmc = pmc_npmc(cpu)) < 0)
2893                 return (-1);
2894
2895         nbytes = sizeof(struct pmc_op_getpmcinfo) +
2896             npmc * sizeof(struct pmc_info);
2897
2898         if ((pmci = calloc(1, nbytes)) == NULL)
2899                 return (-1);
2900
2901         pmci->pm_cpu  = cpu;
2902
2903         if (PMC_CALL(GETPMCINFO, pmci) < 0) {
2904                 free(pmci);
2905                 return (-1);
2906         }
2907
2908         /* kernel<->library, library<->userland interfaces are identical */
2909         *ppmci = (struct pmc_pmcinfo *) pmci;
2910         return (0);
2911 }
2912
2913 int
2914 pmc_read(pmc_id_t pmc, pmc_value_t *value)
2915 {
2916         struct pmc_op_pmcrw pmc_read_op;
2917
2918         pmc_read_op.pm_pmcid = pmc;
2919         pmc_read_op.pm_flags = PMC_F_OLDVALUE;
2920         pmc_read_op.pm_value = -1;
2921
2922         if (PMC_CALL(PMCRW, &pmc_read_op) < 0)
2923                 return (-1);
2924
2925         *value = pmc_read_op.pm_value;
2926         return (0);
2927 }
2928
2929 int
2930 pmc_release(pmc_id_t pmc)
2931 {
2932         struct pmc_op_simple    pmc_release_args;
2933
2934         pmc_release_args.pm_pmcid = pmc;
2935         return (PMC_CALL(PMCRELEASE, &pmc_release_args));
2936 }
2937
2938 int
2939 pmc_rw(pmc_id_t pmc, pmc_value_t newvalue, pmc_value_t *oldvaluep)
2940 {
2941         struct pmc_op_pmcrw pmc_rw_op;
2942
2943         pmc_rw_op.pm_pmcid = pmc;
2944         pmc_rw_op.pm_flags = PMC_F_NEWVALUE | PMC_F_OLDVALUE;
2945         pmc_rw_op.pm_value = newvalue;
2946
2947         if (PMC_CALL(PMCRW, &pmc_rw_op) < 0)
2948                 return (-1);
2949
2950         *oldvaluep = pmc_rw_op.pm_value;
2951         return (0);
2952 }
2953
2954 int
2955 pmc_set(pmc_id_t pmc, pmc_value_t value)
2956 {
2957         struct pmc_op_pmcsetcount sc;
2958
2959         sc.pm_pmcid = pmc;
2960         sc.pm_count = value;
2961
2962         if (PMC_CALL(PMCSETCOUNT, &sc) < 0)
2963                 return (-1);
2964         return (0);
2965 }
2966
2967 int
2968 pmc_start(pmc_id_t pmc)
2969 {
2970         struct pmc_op_simple    pmc_start_args;
2971
2972         pmc_start_args.pm_pmcid = pmc;
2973         return (PMC_CALL(PMCSTART, &pmc_start_args));
2974 }
2975
2976 int
2977 pmc_stop(pmc_id_t pmc)
2978 {
2979         struct pmc_op_simple    pmc_stop_args;
2980
2981         pmc_stop_args.pm_pmcid = pmc;
2982         return (PMC_CALL(PMCSTOP, &pmc_stop_args));
2983 }
2984
2985 int
2986 pmc_width(pmc_id_t pmcid, uint32_t *width)
2987 {
2988         unsigned int i;
2989         enum pmc_class cl;
2990
2991         cl = PMC_ID_TO_CLASS(pmcid);
2992         for (i = 0; i < cpu_info.pm_nclass; i++)
2993                 if (cpu_info.pm_classes[i].pm_class == cl) {
2994                         *width = cpu_info.pm_classes[i].pm_width;
2995                         return (0);
2996                 }
2997         errno = EINVAL;
2998         return (-1);
2999 }
3000
3001 int
3002 pmc_write(pmc_id_t pmc, pmc_value_t value)
3003 {
3004         struct pmc_op_pmcrw pmc_write_op;
3005
3006         pmc_write_op.pm_pmcid = pmc;
3007         pmc_write_op.pm_flags = PMC_F_NEWVALUE;
3008         pmc_write_op.pm_value = value;
3009         return (PMC_CALL(PMCRW, &pmc_write_op));
3010 }
3011
3012 int
3013 pmc_writelog(uint32_t userdata)
3014 {
3015         struct pmc_op_writelog wl;
3016
3017         wl.pm_userdata = userdata;
3018         return (PMC_CALL(WRITELOG, &wl));
3019 }