2 * Copyright (c) 1989, 1990 William F. Jolitz.
3 * Copyright (c) 1990 The Regents of the University of California.
4 * Copyright (c) 2007 The FreeBSD Foundation
7 * Portions of this software were developed by A. Joseph Koshy under
8 * sponsorship from the FreeBSD Foundation and Google, Inc.
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 * 4. Neither the name of the University nor the names of its contributors
19 * may be used to endorse or promote products derived from this software
20 * without specific prior written permission.
22 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
37 #include "opt_atpic.h"
38 #include "opt_compat.h"
39 #include "opt_hwpmc_hooks.h"
40 #include "opt_kdtrace.h"
42 #include <machine/asmacros.h>
43 #include <machine/psl.h>
44 #include <machine/trap.h>
45 #include <machine/specialreg.h>
51 .globl dtrace_invop_jump_addr
53 .type dtrace_invop_jump_addr,@object
54 .size dtrace_invop_jump_addr,8
55 dtrace_invop_jump_addr:
57 .globl dtrace_invop_calltrap_addr
59 .type dtrace_invop_calltrap_addr,@object
60 .size dtrace_invop_calltrap_addr,8
61 dtrace_invop_calltrap_addr:
66 ENTRY(start_exceptions)
69 /*****************************************************************************/
71 /*****************************************************************************/
73 * Trap and fault vector routines.
75 * All traps are 'interrupt gates', SDT_SYSIGT. An interrupt gate pushes
76 * state on the stack but also disables interrupts. This is important for
77 * us for the use of the swapgs instruction. We cannot be interrupted
78 * until the GS.base value is correct. For most traps, we automatically
79 * then enable interrupts if the interrupted context had them enabled.
80 * This is equivalent to the i386 port's use of SDT_SYS386TGT.
82 * The cpu will push a certain amount of state onto the kernel stack for
83 * the current process. See amd64/include/frame.h.
84 * This includes the current RFLAGS (status register, which includes
85 * the interrupt disable state prior to the trap), the code segment register,
86 * and the return instruction pointer are pushed by the cpu. The cpu
87 * will also push an 'error' code for certain traps. We push a dummy
88 * error code for those traps where the cpu doesn't in order to maintain
89 * a consistent frame. We also push a contrived 'trap number'.
91 * The cpu does not push the general registers, we must do that, and we
92 * must restore them prior to calling 'iret'. The cpu adjusts the %cs and
93 * %ss segment registers, but does not mess with %ds, %es, or %fs. Thus we
94 * must load them with appropriate values for supervisor mode operation.
100 /* Traps that we leave interrupts disabled for.. */
101 #define TRAP_NOEN(a) \
103 movl $(a),TF_TRAPNO(%rsp) ; \
104 movq $0,TF_ADDR(%rsp) ; \
105 movq $0,TF_ERR(%rsp) ; \
112 /* Regular traps; The cpu does not supply tf_err for these. */
115 movl $(a),TF_TRAPNO(%rsp) ; \
116 movq $0,TF_ADDR(%rsp) ; \
117 movq $0,TF_ERR(%rsp) ; \
140 /* This group of traps have tf_err already pushed by the cpu */
141 #define TRAP_ERR(a) \
143 movl $(a),TF_TRAPNO(%rsp) ; \
144 movq $0,TF_ADDR(%rsp) ; \
156 * alltraps entry point. Use swapgs if this is the first time in the
157 * kernel from userland. Reenable interrupts if they were enabled
158 * before the trap. This approximates SDT_SYS386TGT on the i386 port.
162 .type alltraps,@function
164 movq %rdi,TF_RDI(%rsp)
165 testb $SEL_RPL_MASK,TF_CS(%rsp) /* Did we come from kernel? */
166 jz alltraps_testi /* already running with kernel GS.base */
168 movq PCPU(CURPCB),%rdi
169 movb $0,PCB_FULL_IRET(%rdi)
175 testl $PSL_I,TF_RFLAGS(%rsp)
176 jz alltraps_pushregs_no_rdi
178 alltraps_pushregs_no_rdi:
179 movq %rsi,TF_RSI(%rsp)
180 movq %rdx,TF_RDX(%rsp)
181 movq %rcx,TF_RCX(%rsp)
184 movq %rax,TF_RAX(%rsp)
185 movq %rbx,TF_RBX(%rsp)
186 movq %rbp,TF_RBP(%rsp)
187 movq %r10,TF_R10(%rsp)
188 movq %r11,TF_R11(%rsp)
189 movq %r12,TF_R12(%rsp)
190 movq %r13,TF_R13(%rsp)
191 movq %r14,TF_R14(%rsp)
192 movq %r15,TF_R15(%rsp)
193 movl $TF_HASSEGS,TF_FLAGS(%rsp)
194 FAKE_MCOUNT(TF_RIP(%rsp))
197 * DTrace Function Boundary Trace (fbt) probes are triggered
198 * by int3 (0xcc) which causes the #BP (T_BPTFLT) breakpoint
199 * interrupt. For all other trap types, just handle them in
202 cmpl $T_BPTFLT,TF_TRAPNO(%rsp)
205 /* Check if there is no DTrace hook registered. */
206 cmpq $0,dtrace_invop_jump_addr
210 * Set our jump address for the jump back in the event that
211 * the breakpoint wasn't caused by DTrace at all.
213 movq $calltrap,dtrace_invop_calltrap_addr(%rip)
215 /* Jump to the code hooked in by DTrace. */
216 movq dtrace_invop_jump_addr,%rax
217 jmpq *dtrace_invop_jump_addr
220 .type calltrap,@function
225 jmp doreti /* Handle any pending ASTs */
228 * alltraps_noen entry point. Unlike alltraps above, we want to
229 * leave the interrupts disabled. This corresponds to
230 * SDT_SYS386IGT on the i386 port.
234 .type alltraps_noen,@function
236 movq %rdi,TF_RDI(%rsp)
237 testb $SEL_RPL_MASK,TF_CS(%rsp) /* Did we come from kernel? */
238 jz 1f /* already running with kernel GS.base */
240 movq PCPU(CURPCB),%rdi
241 movb $0,PCB_FULL_IRET(%rdi)
242 1: movw %fs,TF_FS(%rsp)
246 jmp alltraps_pushregs_no_rdi
250 movl $T_DOUBLEFLT,TF_TRAPNO(%rsp)
251 movq $0,TF_ADDR(%rsp)
253 movq %rdi,TF_RDI(%rsp)
254 movq %rsi,TF_RSI(%rsp)
255 movq %rdx,TF_RDX(%rsp)
256 movq %rcx,TF_RCX(%rsp)
259 movq %rax,TF_RAX(%rsp)
260 movq %rbx,TF_RBX(%rsp)
261 movq %rbp,TF_RBP(%rsp)
262 movq %r10,TF_R10(%rsp)
263 movq %r11,TF_R11(%rsp)
264 movq %r12,TF_R12(%rsp)
265 movq %r13,TF_R13(%rsp)
266 movq %r14,TF_R14(%rsp)
267 movq %r15,TF_R15(%rsp)
272 movl $TF_HASSEGS,TF_FLAGS(%rsp)
273 testb $SEL_RPL_MASK,TF_CS(%rsp) /* Did we come from kernel? */
274 jz 1f /* already running with kernel GS.base */
278 call dblfault_handler
285 movl $T_PAGEFLT,TF_TRAPNO(%rsp)
286 movq %rdi,TF_RDI(%rsp) /* free up a GP register */
287 testb $SEL_RPL_MASK,TF_CS(%rsp) /* Did we come from kernel? */
288 jz 1f /* already running with kernel GS.base */
290 movq PCPU(CURPCB),%rdi
291 movb $0,PCB_FULL_IRET(%rdi)
292 1: movq %cr2,%rdi /* preserve %cr2 before .. */
293 movq %rdi,TF_ADDR(%rsp) /* enabling interrupts. */
298 testl $PSL_I,TF_RFLAGS(%rsp)
299 jz alltraps_pushregs_no_rdi
301 jmp alltraps_pushregs_no_rdi
304 * We have to special-case this one. If we get a trap in doreti() at
305 * the iretq stage, we'll reenter with the wrong gs state. We'll have
306 * to do a special the swapgs in this case even coming from the kernel.
307 * XXX linux has a trap handler for their equivalent of load_gs().
311 movl $T_PROTFLT,TF_TRAPNO(%rsp)
312 movq $0,TF_ADDR(%rsp)
313 movq %rdi,TF_RDI(%rsp) /* free up a GP register */
314 leaq doreti_iret(%rip),%rdi
315 cmpq %rdi,TF_RIP(%rsp)
316 je 1f /* kernel but with user gsbase!! */
317 testb $SEL_RPL_MASK,TF_CS(%rsp) /* Did we come from kernel? */
318 jz 2f /* already running with kernel GS.base */
320 2: movq PCPU(CURPCB),%rdi
321 movb $1,PCB_FULL_IRET(%rdi) /* always full iret from GPF */
326 testl $PSL_I,TF_RFLAGS(%rsp)
327 jz alltraps_pushregs_no_rdi
329 jmp alltraps_pushregs_no_rdi
332 * Fast syscall entry point. We enter here with just our new %cs/%ss set,
333 * and the new privilige level. We are still running on the old user stack
334 * pointer. We have to juggle a few things around to find our stack etc.
335 * swapgs gives us access to our PCPU space only.
339 movq %rsp,PCPU(SCRATCH_RSP)
341 /* Now emulate a trapframe. Make the 8 byte alignment odd for call. */
343 /* defer TF_RSP till we have a spare register */
344 movq %r11,TF_RFLAGS(%rsp)
345 movq %rcx,TF_RIP(%rsp) /* %rcx original value is in %r10 */
346 movq PCPU(SCRATCH_RSP),%r11 /* %r11 already saved */
347 movq %r11,TF_RSP(%rsp) /* user stack pointer */
352 movq PCPU(CURPCB),%r11
353 movb $0,PCB_FULL_IRET(%r11)
355 movq $KUDSEL,TF_SS(%rsp)
356 movq $KUCSEL,TF_CS(%rsp)
358 movq %rdi,TF_RDI(%rsp) /* arg 1 */
359 movq %rsi,TF_RSI(%rsp) /* arg 2 */
360 movq %rdx,TF_RDX(%rsp) /* arg 3 */
361 movq %r10,TF_RCX(%rsp) /* arg 4 */
362 movq %r8,TF_R8(%rsp) /* arg 5 */
363 movq %r9,TF_R9(%rsp) /* arg 6 */
364 movq %rax,TF_RAX(%rsp) /* syscall number */
365 movq %rbx,TF_RBX(%rsp) /* C preserved */
366 movq %rbp,TF_RBP(%rsp) /* C preserved */
367 movq %r12,TF_R12(%rsp) /* C preserved */
368 movq %r13,TF_R13(%rsp) /* C preserved */
369 movq %r14,TF_R14(%rsp) /* C preserved */
370 movq %r15,TF_R15(%rsp) /* C preserved */
371 movl $TF_HASSEGS,TF_FLAGS(%rsp)
372 FAKE_MCOUNT(TF_RIP(%rsp))
375 movq PCPU(CURPCB),%rax
376 andq $~PCB_FULLCTX,PCB_FLAGS(%rax)
381 * Here for CYA insurance, in case a "syscall" instruction gets
382 * issued from 32 bit compatability mode. MSR_CSTAR has to point
383 * to *something* if EFER_SCE is enabled.
385 IDTVEC(fast_syscall32)
389 * NMI handling is special.
391 * First, NMIs do not respect the state of the processor's RFLAGS.IF
392 * bit. The NMI handler may be entered at any time, including when
393 * the processor is in a critical section with RFLAGS.IF == 0.
394 * The processor's GS.base value could be invalid on entry to the
397 * Second, the processor treats NMIs specially, blocking further NMIs
398 * until an 'iretq' instruction is executed. We thus need to execute
399 * the NMI handler with interrupts disabled, to prevent a nested interrupt
400 * from executing an 'iretq' instruction and inadvertently taking the
401 * processor out of NMI mode.
403 * Third, the NMI handler runs on its own stack (tss_ist2). The canonical
404 * GS.base value for the processor is stored just above the bottom of its
405 * NMI stack. For NMIs taken from kernel mode, the current value in
406 * the processor's GS.base is saved at entry to C-preserved register %r12,
407 * the canonical value for GS.base is then loaded into the processor, and
408 * the saved value is restored at exit time. For NMIs taken from user mode,
409 * the cheaper 'SWAPGS' instructions are used for swapping GS.base.
414 movl $(T_NMI),TF_TRAPNO(%rsp)
415 movq $0,TF_ADDR(%rsp)
417 movq %rdi,TF_RDI(%rsp)
418 movq %rsi,TF_RSI(%rsp)
419 movq %rdx,TF_RDX(%rsp)
420 movq %rcx,TF_RCX(%rsp)
423 movq %rax,TF_RAX(%rsp)
424 movq %rbx,TF_RBX(%rsp)
425 movq %rbp,TF_RBP(%rsp)
426 movq %r10,TF_R10(%rsp)
427 movq %r11,TF_R11(%rsp)
428 movq %r12,TF_R12(%rsp)
429 movq %r13,TF_R13(%rsp)
430 movq %r14,TF_R14(%rsp)
431 movq %r15,TF_R15(%rsp)
436 movl $TF_HASSEGS,TF_FLAGS(%rsp)
438 testb $SEL_RPL_MASK,TF_CS(%rsp)
439 jnz nmi_fromuserspace
441 * We've interrupted the kernel. Preserve GS.base in %r12.
443 movl $MSR_GSBASE,%ecx
448 /* Retrieve and load the canonical value for GS.base. */
449 movq TF_SIZE(%rsp),%rdx
457 /* Note: this label is also used by ddb and gdb: */
459 FAKE_MCOUNT(TF_RIP(%rsp))
465 * Capture a userspace callchain if needed.
467 * - Check if the current trap was from user mode.
468 * - Check if the current thread is valid.
469 * - Check if the thread requires a user call chain to be
472 * We are still in NMI mode at this point.
475 jz nocallchain /* not from userspace */
476 movq PCPU(CURTHREAD),%rax
477 orq %rax,%rax /* curthread present? */
479 testl $TDP_CALLCHAIN,TD_PFLAGS(%rax) /* flagged for capture? */
482 * A user callchain is to be captured, so:
483 * - Move execution to the regular kernel stack, to allow for
484 * nested NMI interrupts.
485 * - Take the processor out of "NMI" mode by faking an "iret".
486 * - Enable interrupts, so that copyin() can work.
488 movq %rsp,%rsi /* source stack pointer */
492 movq %rdx,%rdi /* destination stack pointer */
494 shrq $3,%rcx /* trap frame size in long words */
497 movsq /* copy trapframe */
500 pushq %rax /* tf_ss */
501 pushq %rdx /* tf_rsp (on kernel stack) */
502 pushfq /* tf_rflags */
504 pushq %rax /* tf_cs */
505 pushq $outofnmi /* tf_rip */
509 * At this point the processor has exited NMI mode and is running
510 * with interrupts turned off on the normal kernel stack.
512 * If a pending NMI gets recognized at or after this point, it
513 * will cause a kernel callchain to be traced.
515 * We turn interrupts back on, and call the user callchain capture hook.
520 movq PCPU(CURTHREAD),%rdi /* thread */
521 movq $PMC_FN_USER_CALLCHAIN,%rsi /* command */
522 movq %rsp,%rdx /* frame */
532 * Put back the preserved MSR_GSBASE value.
534 movl $MSR_GSBASE,%ecx
540 movq TF_RDI(%rsp),%rdi
541 movq TF_RSI(%rsp),%rsi
542 movq TF_RDX(%rsp),%rdx
543 movq TF_RCX(%rsp),%rcx
546 movq TF_RAX(%rsp),%rax
547 movq TF_RBX(%rsp),%rbx
548 movq TF_RBP(%rsp),%rbp
549 movq TF_R10(%rsp),%r10
550 movq TF_R11(%rsp),%r11
551 movq TF_R12(%rsp),%r12
552 movq TF_R13(%rsp),%r13
553 movq TF_R14(%rsp),%r14
554 movq TF_R15(%rsp),%r15
558 ENTRY(fork_trampoline)
559 movq %r12,%rdi /* function */
560 movq %rbx,%rsi /* arg1 */
561 movq %rsp,%rdx /* trapframe pointer */
564 jmp doreti /* Handle any ASTs */
567 * To efficiently implement classification of trap and interrupt handlers
568 * for profiling, there must be only trap handlers between the labels btrap
569 * and bintr, and only interrupt handlers between the labels bintr and
570 * eintr. This is implemented (partly) by including files that contain
571 * some of the handlers. Before including the files, set up a normal asm
572 * environment so that the included files doen't need to know that they are
576 #ifdef COMPAT_FREEBSD32
582 #include <amd64/ia32/ia32_exception.S>
591 #include <amd64/amd64/apic_vector.S>
599 #include <amd64/isa/atpic_vector.S>
606 * void doreti(struct trapframe)
608 * Handle return from interrupts, traps and syscalls.
612 .type doreti,@function
614 FAKE_MCOUNT($bintr) /* init "from" bintr -> doreti */
616 * Check if ASTs can be handled now.
618 testb $SEL_RPL_MASK,TF_CS(%rsp) /* are we returning to user mode? */
619 jz doreti_exit /* can't handle ASTs now if not */
623 * Check for ASTs atomically with returning. Disabling CPU
624 * interrupts provides sufficient locking eve in the SMP case,
625 * since we will be informed of any new ASTs by an IPI.
628 movq PCPU(CURTHREAD),%rax
629 testl $TDF_ASTPENDING | TDF_NEEDRESCHED,TD_FLAGS(%rax)
632 movq %rsp,%rdi /* pass a pointer to the trapframe */
637 * doreti_exit: pop registers, iret.
639 * The segment register pop is a special case, since it may
640 * fault if (for example) a sigreturn specifies bad segment
641 * registers. The fault is handled in trap.c.
645 movq PCPU(CURTHREAD),%r8
649 * Do not reload segment registers for kernel.
650 * Since we do not reload segments registers with sane
651 * values on kernel entry, descriptors referenced by
652 * segments registers might be not valid. This is fatal
653 * for user mode, but is not a problem for the kernel.
655 testb $SEL_RPL_MASK,TF_CS(%rsp)
657 cmpb $0,PCB_FULL_IRET(%r8)
659 testl $TF_HASSEGS,TF_FLAGS(%rsp)
663 /* Restore %fs and fsbase */
670 movl $MSR_FSBASE,%ecx
671 movl PCB_FSBASE(%r8),%eax
672 movl PCB_FSBASE+4(%r8),%edx
677 /* Restore %gs and gsbase */
681 movl $MSR_GSBASE,%ecx
690 movl $MSR_KGSBASE,%ecx
691 movl PCB_GSBASE(%r8),%eax
692 movl PCB_GSBASE+4(%r8),%edx
704 movq TF_RDI(%rsp),%rdi
705 movq TF_RSI(%rsp),%rsi
706 movq TF_RDX(%rsp),%rdx
707 movq TF_RCX(%rsp),%rcx
710 movq TF_RAX(%rsp),%rax
711 movq TF_RBX(%rsp),%rbx
712 movq TF_RBP(%rsp),%rbp
713 movq TF_R10(%rsp),%r10
714 movq TF_R11(%rsp),%r11
715 movq TF_R12(%rsp),%r12
716 movq TF_R13(%rsp),%r13
717 movq TF_R14(%rsp),%r14
718 movq TF_R15(%rsp),%r15
719 testb $SEL_RPL_MASK,TF_CS(%rsp) /* Did we come from kernel? */
720 jz 1f /* keep running with kernel GS.base */
724 addq $TF_RIP,%rsp /* skip over tf_err, tf_trapno */
733 movw $KUF32SEL,TF_FS(%rsp)
734 movw $KUG32SEL,TF_GS(%rsp)
738 * doreti_iret_fault. Alternative return code for
739 * the case where we get a fault in the doreti_exit code
740 * above. trap() (amd64/amd64/trap.c) catches this specific
741 * case, sends the process a signal and continues in the
742 * corresponding place in the code below.
745 .globl doreti_iret_fault
747 subq $TF_RIP,%rsp /* space including tf_err, tf_trapno */
748 testl $PSL_I,TF_RFLAGS(%rsp)
756 movl $TF_HASSEGS,TF_FLAGS(%rsp)
757 movq %rdi,TF_RDI(%rsp)
758 movq %rsi,TF_RSI(%rsp)
759 movq %rdx,TF_RDX(%rsp)
760 movq %rcx,TF_RCX(%rsp)
763 movq %rax,TF_RAX(%rsp)
764 movq %rbx,TF_RBX(%rsp)
765 movq %rbp,TF_RBP(%rsp)
766 movq %r10,TF_R10(%rsp)
767 movq %r11,TF_R11(%rsp)
768 movq %r12,TF_R12(%rsp)
769 movq %r13,TF_R13(%rsp)
770 movq %r14,TF_R14(%rsp)
771 movq %r15,TF_R15(%rsp)
772 movl $T_PROTFLT,TF_TRAPNO(%rsp)
773 movq $0,TF_ERR(%rsp) /* XXX should be the error code */
774 movq $0,TF_ADDR(%rsp)
775 FAKE_MCOUNT(TF_RIP(%rsp))
781 movl $T_PROTFLT,TF_TRAPNO(%rsp)
784 movw $KUDSEL,TF_DS(%rsp)
790 movl $T_PROTFLT,TF_TRAPNO(%rsp)
793 movw $KUDSEL,TF_ES(%rsp)
799 movl $T_PROTFLT,TF_TRAPNO(%rsp)
802 movw $KUF32SEL,TF_FS(%rsp)
809 movl $T_PROTFLT,TF_TRAPNO(%rsp)
812 movw $KUG32SEL,TF_GS(%rsp)
816 .globl fsbase_load_fault
818 movl $T_PROTFLT,TF_TRAPNO(%rsp)
821 movq PCPU(CURTHREAD),%r8
823 movq $0,PCB_FSBASE(%r8)
827 .globl gsbase_load_fault
829 movl $T_PROTFLT,TF_TRAPNO(%rsp)
832 movq PCPU(CURTHREAD),%r8
834 movq $0,PCB_GSBASE(%r8)
838 ENTRY(end_exceptions)