2 * Copyright (c) 2009 Advanced Computing Technologies LLC
3 * Written by: John H. Baldwin <jhb@FreeBSD.org>
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 * Support for x86 machine check architecture.
32 #include <sys/cdefs.h>
33 __FBSDID("$FreeBSD$");
35 #include <sys/param.h>
36 #include <sys/kernel.h>
38 #include <sys/malloc.h>
39 #include <sys/mutex.h>
41 #include <sys/sched.h>
43 #include <sys/sysctl.h>
44 #include <sys/systm.h>
45 #include <sys/taskqueue.h>
46 #include <machine/cputypes.h>
47 #include <machine/mca.h>
48 #include <machine/md_var.h>
49 #include <machine/specialreg.h>
52 struct mca_record rec;
54 STAILQ_ENTRY(mca_internal) link;
57 static MALLOC_DEFINE(M_MCA, "MCA", "Machine Check Architecture");
59 static int mca_count; /* Number of records stored. */
61 SYSCTL_NODE(_hw, OID_AUTO, mca, CTLFLAG_RD, NULL, "Machine Check Architecture");
63 static int mca_enabled = 1;
64 TUNABLE_INT("hw.mca.enabled", &mca_enabled);
65 SYSCTL_INT(_hw_mca, OID_AUTO, enabled, CTLFLAG_RDTUN, &mca_enabled, 0,
66 "Administrative toggle for machine check support");
68 static int amd10h_L1TP = 1;
69 TUNABLE_INT("hw.mca.amd10h_L1TP", &amd10h_L1TP);
70 SYSCTL_INT(_hw_mca, OID_AUTO, amd10h_L1TP, CTLFLAG_RDTUN, &amd10h_L1TP, 0,
71 "Administrative toggle for logging of level one TLB parity (L1TP) errors");
73 int workaround_erratum383;
74 SYSCTL_INT(_hw_mca, OID_AUTO, erratum383, CTLFLAG_RD, &workaround_erratum383, 0,
75 "Is the workaround for Erratum 383 on AMD Family 10h processors enabled?");
77 static STAILQ_HEAD(, mca_internal) mca_records;
78 static struct callout mca_timer;
79 static int mca_ticks = 3600; /* Check hourly by default. */
80 static struct task mca_task;
81 static struct mtx mca_lock;
84 sysctl_mca_ticks(SYSCTL_HANDLER_ARGS)
89 error = sysctl_handle_int(oidp, &value, 0, req);
90 if (error || req->newptr == NULL)
99 sysctl_mca_records(SYSCTL_HANDLER_ARGS)
101 int *name = (int *)arg1;
102 u_int namelen = arg2;
103 struct mca_record record;
104 struct mca_internal *rec;
110 if (name[0] < 0 || name[0] >= mca_count)
113 mtx_lock_spin(&mca_lock);
114 if (name[0] >= mca_count) {
115 mtx_unlock_spin(&mca_lock);
119 STAILQ_FOREACH(rec, &mca_records, link) {
126 mtx_unlock_spin(&mca_lock);
127 return (SYSCTL_OUT(req, &record, sizeof(record)));
131 mca_error_ttype(uint16_t mca_error)
134 switch ((mca_error & 0x000c) >> 2) {
146 mca_error_level(uint16_t mca_error)
149 switch (mca_error & 0x0003) {
163 mca_error_request(uint16_t mca_error)
166 switch ((mca_error & 0x00f0) >> 4) {
190 mca_error_mmtype(uint16_t mca_error)
193 switch ((mca_error & 0x70) >> 4) {
208 /* Dump details about a single machine check. */
209 static void __nonnull(1)
210 mca_log(const struct mca_record *rec)
214 printf("MCA: Bank %d, Status 0x%016llx\n", rec->mr_bank,
215 (long long)rec->mr_status);
216 printf("MCA: Global Cap 0x%016llx, Status 0x%016llx\n",
217 (long long)rec->mr_mcg_cap, (long long)rec->mr_mcg_status);
218 printf("MCA: Vendor \"%s\", ID 0x%x, APIC ID %d\n", cpu_vendor,
219 rec->mr_cpu_id, rec->mr_apic_id);
220 printf("MCA: CPU %d ", rec->mr_cpu);
221 if (rec->mr_status & MC_STATUS_UC)
225 if (rec->mr_mcg_cap & MCG_CAP_TES_P)
226 printf("(%lld) ", ((long long)rec->mr_status &
227 MC_STATUS_COR_COUNT) >> 38);
229 if (rec->mr_status & MC_STATUS_PCC)
231 if (rec->mr_status & MC_STATUS_OVER)
233 mca_error = rec->mr_status & MC_STATUS_MCA_ERROR;
235 /* Simple error codes. */
240 printf("unclassified error");
243 printf("ucode ROM parity error");
246 printf("external error");
252 printf("internal parity error");
255 printf("internal timer error");
258 if ((mca_error & 0xfc00) == 0x0400) {
259 printf("internal error %x", mca_error & 0x03ff);
263 /* Compound error codes. */
265 /* Memory hierarchy error. */
266 if ((mca_error & 0xeffc) == 0x000c) {
267 printf("%s memory error", mca_error_level(mca_error));
272 if ((mca_error & 0xeff0) == 0x0010) {
273 printf("%sTLB %s error", mca_error_ttype(mca_error),
274 mca_error_level(mca_error));
278 /* Memory controller error. */
279 if ((mca_error & 0xef80) == 0x0080) {
280 printf("%s channel ", mca_error_mmtype(mca_error));
281 if ((mca_error & 0x000f) != 0x000f)
282 printf("%d", mca_error & 0x000f);
285 printf(" memory error");
290 if ((mca_error & 0xef00) == 0x0100) {
291 printf("%sCACHE %s %s error",
292 mca_error_ttype(mca_error),
293 mca_error_level(mca_error),
294 mca_error_request(mca_error));
298 /* Bus and/or Interconnect error. */
299 if ((mca_error & 0xe800) == 0x0800) {
300 printf("BUS%s ", mca_error_level(mca_error));
301 switch ((mca_error & 0x0600) >> 9) {
315 printf(" %s ", mca_error_request(mca_error));
316 switch ((mca_error & 0x000c) >> 2) {
330 if (mca_error & 0x0100)
331 printf(" timed out");
335 printf("unknown error %x", mca_error);
339 if (rec->mr_status & MC_STATUS_ADDRV)
340 printf("MCA: Address 0x%llx\n", (long long)rec->mr_addr);
341 if (rec->mr_status & MC_STATUS_MISCV)
342 printf("MCA: Misc 0x%llx\n", (long long)rec->mr_misc);
345 static int __nonnull(2)
346 mca_check_status(int bank, struct mca_record *rec)
351 status = rdmsr(MSR_MC_STATUS(bank));
352 if (!(status & MC_STATUS_VAL))
355 /* Save exception information. */
356 rec->mr_status = status;
359 if (status & MC_STATUS_ADDRV)
360 rec->mr_addr = rdmsr(MSR_MC_ADDR(bank));
362 if (status & MC_STATUS_MISCV)
363 rec->mr_misc = rdmsr(MSR_MC_MISC(bank));
364 rec->mr_tsc = rdtsc();
365 rec->mr_apic_id = PCPU_GET(apic_id);
366 rec->mr_mcg_cap = rdmsr(MSR_MCG_CAP);
367 rec->mr_mcg_status = rdmsr(MSR_MCG_STATUS);
368 rec->mr_cpu_id = cpu_id;
369 rec->mr_cpu_vendor_id = cpu_vendor_id;
370 rec->mr_cpu = PCPU_GET(cpuid);
373 * Clear machine check. Don't do this for uncorrectable
374 * errors so that the BIOS can see them.
376 if (!(rec->mr_status & (MC_STATUS_PCC | MC_STATUS_UC))) {
377 wrmsr(MSR_MC_STATUS(bank), 0);
383 static void __nonnull(1)
384 mca_record_entry(const struct mca_record *record)
386 struct mca_internal *rec;
388 rec = malloc(sizeof(*rec), M_MCA, M_NOWAIT);
390 printf("MCA: Unable to allocate space for an event.\n");
397 mtx_lock_spin(&mca_lock);
398 STAILQ_INSERT_TAIL(&mca_records, rec, link);
400 mtx_unlock_spin(&mca_lock);
404 * This scans all the machine check banks of the current CPU to see if
405 * there are any machine checks. Any non-recoverable errors are
406 * reported immediately via mca_log(). The current thread must be
407 * pinned when this is called. The 'mcip' parameter indicates if we
408 * are being called from the MC exception handler. In that case this
409 * function returns true if the system is restartable. Otherwise, it
410 * returns a count of the number of valid MC records found.
415 struct mca_record rec;
416 uint64_t mcg_cap, ucmask;
417 int count, i, recoverable;
421 ucmask = MC_STATUS_UC | MC_STATUS_PCC;
423 /* When handling a MCE#, treat the OVER flag as non-restartable. */
425 ucmask |= MC_STATUS_OVER;
426 mcg_cap = rdmsr(MSR_MCG_CAP);
427 for (i = 0; i < (mcg_cap & MCG_CAP_COUNT); i++) {
428 if (mca_check_status(i, &rec)) {
430 if (rec.mr_status & ucmask) {
434 mca_record_entry(&rec);
437 return (mcip ? recoverable : count);
441 * Scan the machine check banks on all CPUs by binding to each CPU in
442 * turn. If any of the CPUs contained new machine check records, log
443 * them to the console.
446 mca_scan_cpus(void *context, int pending)
448 struct mca_internal *mca;
455 for (cpu = 0; cpu <= mp_maxid; cpu++) {
460 count += mca_scan(0);
466 mtx_lock_spin(&mca_lock);
467 STAILQ_FOREACH(mca, &mca_records, link) {
470 mtx_unlock_spin(&mca_lock);
472 mtx_lock_spin(&mca_lock);
475 mtx_unlock_spin(&mca_lock);
480 mca_periodic_scan(void *arg)
483 taskqueue_enqueue(taskqueue_thread, &mca_task);
484 callout_reset(&mca_timer, mca_ticks * hz, mca_periodic_scan, NULL);
488 sysctl_mca_scan(SYSCTL_HANDLER_ARGS)
493 error = sysctl_handle_int(oidp, &i, 0, req);
497 taskqueue_enqueue(taskqueue_thread, &mca_task);
502 mca_startup(void *dummy)
505 if (!mca_enabled || !(cpu_feature & CPUID_MCA))
508 callout_reset(&mca_timer, mca_ticks * hz, mca_periodic_scan,
511 SYSINIT(mca_startup, SI_SUB_SMP, SI_ORDER_ANY, mca_startup, NULL);
517 mtx_init(&mca_lock, "mca", NULL, MTX_SPIN);
518 STAILQ_INIT(&mca_records);
519 TASK_INIT(&mca_task, 0x8000, mca_scan_cpus, NULL);
520 callout_init(&mca_timer, CALLOUT_MPSAFE);
521 SYSCTL_ADD_INT(NULL, SYSCTL_STATIC_CHILDREN(_hw_mca), OID_AUTO,
522 "count", CTLFLAG_RD, &mca_count, 0, "Record count");
523 SYSCTL_ADD_PROC(NULL, SYSCTL_STATIC_CHILDREN(_hw_mca), OID_AUTO,
524 "interval", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, &mca_ticks,
525 0, sysctl_mca_ticks, "I",
526 "Periodic interval in seconds to scan for machine checks");
527 SYSCTL_ADD_NODE(NULL, SYSCTL_STATIC_CHILDREN(_hw_mca), OID_AUTO,
528 "records", CTLFLAG_RD, sysctl_mca_records, "Machine check records");
529 SYSCTL_ADD_PROC(NULL, SYSCTL_STATIC_CHILDREN(_hw_mca), OID_AUTO,
530 "force_scan", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, NULL, 0,
531 sysctl_mca_scan, "I", "Force an immediate scan for machine checks");
534 /* Must be executed on each CPU. */
543 /* MCE is required. */
544 if (!mca_enabled || !(cpu_feature & CPUID_MCE))
548 * On AMD Family 10h processors, unless logging of level one TLB
549 * parity (L1TP) errors is disabled, enable the recommended workaround
552 if (cpu_vendor_id == CPU_VENDOR_AMD &&
553 CPUID_TO_FAMILY(cpu_id) == 0x10 && amd10h_L1TP)
554 workaround_erratum383 = 1;
556 if (cpu_feature & CPUID_MCA) {
557 if (PCPU_GET(cpuid) == 0)
561 mcg_cap = rdmsr(MSR_MCG_CAP);
562 if (mcg_cap & MCG_CAP_CTL_P)
563 /* Enable MCA features. */
564 wrmsr(MSR_MCG_CTL, MCG_CTL_ENABLE);
567 * Disable logging of level one TLB parity (L1TP) errors by
568 * the data cache as an alternative workaround for AMD Family
569 * 10h Erratum 383. Unlike the recommended workaround, there
570 * is no performance penalty to this workaround. However,
571 * L1TP errors will go unreported.
573 if (cpu_vendor_id == CPU_VENDOR_AMD &&
574 CPUID_TO_FAMILY(cpu_id) == 0x10 && !amd10h_L1TP) {
575 mask = rdmsr(MSR_MC0_CTL_MASK);
576 if ((mask & (1UL << 5)) == 0)
577 wrmsr(MSR_MC0_CTL_MASK, mask | (1UL << 5));
579 for (i = 0; i < (mcg_cap & MCG_CAP_COUNT); i++) {
580 /* By default enable logging of all errors. */
581 ctl = 0xffffffffffffffffUL;
584 if (cpu_vendor_id == CPU_VENDOR_INTEL) {
586 * For P6 models before Nehalem MC0_CTL is
587 * always enabled and reserved.
589 if (i == 0 && CPUID_TO_FAMILY(cpu_id) == 0x6
590 && CPUID_TO_MODEL(cpu_id) < 0x1a)
592 } else if (cpu_vendor_id == CPU_VENDOR_AMD) {
593 /* BKDG for Family 10h: unset GartTblWkEn. */
594 if (i == 4 && CPUID_TO_FAMILY(cpu_id) >= 0xf)
599 wrmsr(MSR_MC_CTL(i), ctl);
600 /* Clear all errors. */
601 wrmsr(MSR_MC_STATUS(i), 0);
606 load_cr4(rcr4() | CR4_MCE);
609 /* Called when a machine check exception fires. */
616 if (!(cpu_feature & CPUID_MCA)) {
618 * Just print the values of the old Pentium registers
621 printf("MC Type: 0x%lx Address: 0x%lx\n",
622 rdmsr(MSR_P5_MC_TYPE), rdmsr(MSR_P5_MC_ADDR));
626 /* Scan the banks and check for any non-recoverable errors. */
627 recoverable = mca_scan(1);
628 mcg_status = rdmsr(MSR_MCG_STATUS);
629 if (!(mcg_status & MCG_STATUS_RIPV))
633 wrmsr(MSR_MCG_STATUS, mcg_status & ~MCG_STATUS_MCIP);
634 return (recoverable);