2 * Copyright (c) 1996, by Steve Passe
3 * Copyright (c) 2003, by Peter Wemm
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. The name of the developer may NOT be used to endorse or promote products
12 * derived from this software without specific prior written permission.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
31 #include "opt_kstack_pages.h"
32 #include "opt_mp_watchdog.h"
33 #include "opt_sched.h"
35 #include <sys/param.h>
36 #include <sys/systm.h>
41 #include <sys/kernel.h>
44 #include <sys/malloc.h>
45 #include <sys/memrange.h>
46 #include <sys/mutex.h>
49 #include <sys/sched.h>
51 #include <sys/sysctl.h>
54 #include <vm/vm_param.h>
56 #include <vm/vm_kern.h>
57 #include <vm/vm_extern.h>
59 #include <machine/apicreg.h>
60 #include <machine/clock.h>
61 #include <machine/cputypes.h>
62 #include <machine/cpufunc.h>
63 #include <machine/mca.h>
64 #include <machine/md_var.h>
65 #include <machine/mp_watchdog.h>
66 #include <machine/pcb.h>
67 #include <machine/psl.h>
68 #include <machine/smp.h>
69 #include <machine/specialreg.h>
70 #include <machine/tss.h>
72 #define WARMBOOT_TARGET 0
73 #define WARMBOOT_OFF (KERNBASE + 0x0467)
74 #define WARMBOOT_SEG (KERNBASE + 0x0469)
76 #define CMOS_REG (0x70)
77 #define CMOS_DATA (0x71)
78 #define BIOS_RESET (0x0f)
79 #define BIOS_WARM (0x0a)
81 /* lock region used by kernel profiling */
84 int mp_naps; /* # of Applications processors */
85 int boot_cpu_id = -1; /* designated BSP */
87 extern struct pcpu __pcpu[];
89 /* AP uses this during bootstrap. Do not staticize. */
93 /* Free these after use */
94 void *bootstacks[MAXCPU];
96 /* Temporary variables for init_secondary() */
97 char *doublefault_stack;
101 /* Hotwire a 0->4MB V==P mapping */
102 extern pt_entry_t *KPTphys;
104 /* SMP page table page */
105 extern pt_entry_t *SMPpt;
107 struct pcb stoppcbs[MAXCPU];
108 struct xpcb *stopxpcbs = NULL;
110 /* Variables needed for SMP tlb shootdown. */
111 vm_offset_t smp_tlb_addr1;
112 vm_offset_t smp_tlb_addr2;
113 volatile int smp_tlb_wait;
115 extern inthand_t IDTVEC(fast_syscall), IDTVEC(fast_syscall32);
118 * Local data and functions.
121 static u_int logical_cpus;
122 static volatile cpumask_t ipi_nmi_pending;
124 /* used to hold the AP's until we are ready to release them */
125 static struct mtx ap_boot_mtx;
127 /* Set to 1 once we're ready to let the APs out of the pen. */
128 static volatile int aps_ready = 0;
131 * Store data from cpu_add() until later in the boot when we actually setup
138 int cpu_hyperthread:1;
139 } static cpu_info[MAX_APIC_ID + 1];
140 int cpu_apic_ids[MAXCPU];
141 int apic_cpuids[MAX_APIC_ID + 1];
143 /* Holds pending bitmap based IPIs per CPU */
144 static volatile u_int cpu_ipi_pending[MAXCPU];
146 static u_int boot_address;
147 static int cpu_logical;
148 static int cpu_cores;
150 static void assign_cpu_ids(void);
151 static void set_interrupt_apic_ids(void);
152 static int start_all_aps(void);
153 static int start_ap(int apic_id);
154 static void release_aps(void *dummy);
156 static int hlt_logical_cpus;
157 static u_int hyperthreading_cpus;
158 static cpumask_t hyperthreading_cpus_mask;
159 static int hyperthreading_allowed = 1;
160 static struct sysctl_ctx_list logical_cpu_clist;
161 static u_int bootMP_size;
164 mem_range_AP_init(void)
166 if (mem_range_softc.mr_op && mem_range_softc.mr_op->initAP)
167 mem_range_softc.mr_op->initAP(&mem_range_softc);
181 /* We only support two levels for now. */
182 for (i = 0; i < 3; i++) {
183 cpuid_count(0x0B, i, p);
185 logical = p[1] &= 0xffff;
186 type = (p[2] >> 8) & 0xff;
187 if (type == 0 || logical == 0)
189 for (cnt = 0, x = 0; x <= MAX_APIC_ID; x++) {
190 if (!cpu_info[x].cpu_present ||
191 cpu_info[x].cpu_disabled)
193 if (x >> bits == boot_cpu_id >> bits)
196 if (type == CPUID_TYPE_SMT)
198 else if (type == CPUID_TYPE_CORE)
201 if (cpu_logical == 0)
203 cpu_cores /= cpu_logical;
209 u_int threads_per_cache, p[4];
215 * If this CPU supports HTT or CMP then mention the
216 * number of physical/logical cores it contains.
218 if (cpu_feature & CPUID_HTT)
219 htt = (cpu_procinfo & CPUID_HTT_CORES) >> 16;
220 if (cpu_vendor_id == CPU_VENDOR_AMD && (amd_feature2 & AMDID2_CMP))
221 cmp = (cpu_procinfo2 & AMDID_CMP_CORES) + 1;
222 else if (cpu_vendor_id == CPU_VENDOR_INTEL && (cpu_high >= 4)) {
223 cpuid_count(4, 0, p);
224 if ((p[0] & 0x1f) != 0)
225 cmp = ((p[0] >> 26) & 0x3f) + 1;
228 cpu_logical = htt / cmp;
230 /* Setup the initial logical CPUs info. */
231 if (cpu_feature & CPUID_HTT)
232 logical_cpus = (cpu_procinfo & CPUID_HTT_CORES) >> 16;
235 * Work out if hyperthreading is *really* enabled. This
236 * is made really ugly by the fact that processors lie: Dual
237 * core processors claim to be hyperthreaded even when they're
238 * not, presumably because they want to be treated the same
239 * way as HTT with respect to per-cpu software licensing.
240 * At the time of writing (May 12, 2005) the only hyperthreaded
241 * cpus are from Intel, and Intel's dual-core processors can be
242 * identified via the "deterministic cache parameters" cpuid
246 * First determine if this is an Intel processor which claims
247 * to have hyperthreading support.
249 if ((cpu_feature & CPUID_HTT) && cpu_vendor_id == CPU_VENDOR_INTEL) {
251 * If the "deterministic cache parameters" cpuid calls
252 * are available, use them.
255 /* Ask the processor about the L1 cache. */
256 for (i = 0; i < 1; i++) {
257 cpuid_count(4, i, p);
258 threads_per_cache = ((p[0] & 0x3ffc000) >> 14) + 1;
259 if (hyperthreading_cpus < threads_per_cache)
260 hyperthreading_cpus = threads_per_cache;
261 if ((p[0] & 0x1f) == 0)
267 * If the deterministic cache parameters are not
268 * available, or if no caches were reported to exist,
269 * just accept what the HTT flag indicated.
271 if (hyperthreading_cpus == 0)
272 hyperthreading_cpus = logical_cpus;
279 static int cpu_topo_probed = 0;
284 logical_cpus = logical_cpus_mask = 0;
290 cpu_cores = mp_ncpus > 0 ? mp_ncpus : 1;
291 if (cpu_logical == 0)
302 * Determine whether any threading flags are
306 if (cpu_logical > 1 && hyperthreading_cpus)
307 cg_flags = CG_FLAG_HTT;
308 else if (cpu_logical > 1)
309 cg_flags = CG_FLAG_SMT;
312 if (mp_ncpus % (cpu_cores * cpu_logical) != 0) {
313 printf("WARNING: Non-uniform processors.\n");
314 printf("WARNING: Using suboptimal topology.\n");
315 return (smp_topo_none());
318 * No multi-core or hyper-threaded.
320 if (cpu_logical * cpu_cores == 1)
321 return (smp_topo_none());
323 * Only HTT no multi-core.
325 if (cpu_logical > 1 && cpu_cores == 1)
326 return (smp_topo_1level(CG_SHARE_L1, cpu_logical, cg_flags));
328 * Only multi-core no HTT.
330 if (cpu_cores > 1 && cpu_logical == 1)
331 return (smp_topo_1level(CG_SHARE_L2, cpu_cores, cg_flags));
333 * Both HTT and multi-core.
335 return (smp_topo_2level(CG_SHARE_L2, cpu_cores,
336 CG_SHARE_L1, cpu_logical, cg_flags));
340 * Calculate usable address in base memory for AP trampoline code.
343 mp_bootaddress(u_int basemem)
346 bootMP_size = mptramp_end - mptramp_start;
347 boot_address = trunc_page(basemem * 1024); /* round down to 4k boundary */
348 if (((basemem * 1024) - boot_address) < bootMP_size)
349 boot_address -= PAGE_SIZE; /* not enough, lower by 4k */
350 /* 3 levels of page table pages */
351 mptramp_pagetables = boot_address - (PAGE_SIZE * 3);
353 return mptramp_pagetables;
357 cpu_add(u_int apic_id, char boot_cpu)
360 if (apic_id > MAX_APIC_ID) {
361 panic("SMP: APIC ID %d too high", apic_id);
364 KASSERT(cpu_info[apic_id].cpu_present == 0, ("CPU %d added twice",
366 cpu_info[apic_id].cpu_present = 1;
368 KASSERT(boot_cpu_id == -1,
369 ("CPU %d claims to be BSP, but CPU %d already is", apic_id,
371 boot_cpu_id = apic_id;
372 cpu_info[apic_id].cpu_bsp = 1;
374 if (mp_ncpus < MAXCPU) {
376 mp_maxid = mp_ncpus -1;
379 printf("SMP: Added CPU %d (%s)\n", apic_id, boot_cpu ? "BSP" :
384 cpu_mp_setmaxid(void)
388 * mp_maxid should be already set by calls to cpu_add().
389 * Just sanity check its value here.
392 KASSERT(mp_maxid == 0,
393 ("%s: mp_ncpus is zero, but mp_maxid is not", __func__));
394 else if (mp_ncpus == 1)
397 KASSERT(mp_maxid >= mp_ncpus - 1,
398 ("%s: counters out of sync: max %d, count %d", __func__,
399 mp_maxid, mp_ncpus));
407 * Always record BSP in CPU map so that the mbuf init code works
413 * No CPUs were found, so this must be a UP system. Setup
414 * the variables to represent a system with a single CPU
421 /* At least one CPU was found. */
424 * One CPU was found, so this must be a UP system with
431 /* At least two CPUs were found. */
436 * Initialize the IPI handlers and start up the AP's.
443 /* Initialize the logical ID to APIC ID table. */
444 for (i = 0; i < MAXCPU; i++) {
445 cpu_apic_ids[i] = -1;
446 cpu_ipi_pending[i] = 0;
449 /* Install an inter-CPU IPI for TLB invalidation */
450 setidt(IPI_INVLTLB, IDTVEC(invltlb), SDT_SYSIGT, SEL_KPL, 0);
451 setidt(IPI_INVLPG, IDTVEC(invlpg), SDT_SYSIGT, SEL_KPL, 0);
452 setidt(IPI_INVLRNG, IDTVEC(invlrng), SDT_SYSIGT, SEL_KPL, 0);
454 /* Install an inter-CPU IPI for cache invalidation. */
455 setidt(IPI_INVLCACHE, IDTVEC(invlcache), SDT_SYSIGT, SEL_KPL, 0);
457 /* Install an inter-CPU IPI for all-CPU rendezvous */
458 setidt(IPI_RENDEZVOUS, IDTVEC(rendezvous), SDT_SYSIGT, SEL_KPL, 0);
460 /* Install generic inter-CPU IPI handler */
461 setidt(IPI_BITMAP_VECTOR, IDTVEC(ipi_intr_bitmap_handler),
462 SDT_SYSIGT, SEL_KPL, 0);
464 /* Install an inter-CPU IPI for CPU stop/restart */
465 setidt(IPI_STOP, IDTVEC(cpustop), SDT_SYSIGT, SEL_KPL, 0);
467 /* Install an inter-CPU IPI for CPU suspend/resume */
468 setidt(IPI_SUSPEND, IDTVEC(cpususpend), SDT_SYSIGT, SEL_KPL, 0);
470 /* Set boot_cpu_id if needed. */
471 if (boot_cpu_id == -1) {
472 boot_cpu_id = PCPU_GET(apic_id);
473 cpu_info[boot_cpu_id].cpu_bsp = 1;
475 KASSERT(boot_cpu_id == PCPU_GET(apic_id),
476 ("BSP's APIC ID doesn't match boot_cpu_id"));
478 /* Probe logical/physical core configuration. */
483 /* Start each Application Processor */
486 set_interrupt_apic_ids();
491 * Print various information about the SMP system hardware and setup.
494 cpu_mp_announce(void)
496 const char *hyperthread;
499 printf("FreeBSD/SMP: %d package(s) x %d core(s)",
500 mp_ncpus / (cpu_cores * cpu_logical), cpu_cores);
501 if (hyperthreading_cpus > 1)
502 printf(" x %d HTT threads", cpu_logical);
503 else if (cpu_logical > 1)
504 printf(" x %d SMT threads", cpu_logical);
507 /* List active CPUs first. */
508 printf(" cpu0 (BSP): APIC ID: %2d\n", boot_cpu_id);
509 for (i = 1; i < mp_ncpus; i++) {
510 if (cpu_info[cpu_apic_ids[i]].cpu_hyperthread)
514 printf(" cpu%d (AP%s): APIC ID: %2d\n", i, hyperthread,
518 /* List disabled CPUs last. */
519 for (i = 0; i <= MAX_APIC_ID; i++) {
520 if (!cpu_info[i].cpu_present || !cpu_info[i].cpu_disabled)
522 if (cpu_info[i].cpu_hyperthread)
526 printf(" cpu (AP%s): APIC ID: %2d (disabled)\n", hyperthread,
532 * AP CPU's call this to initialize themselves.
540 int cpu, gsel_tss, x;
541 struct region_descriptor ap_gdt;
543 /* Set by the startup code for us to use */
547 common_tss[cpu] = common_tss[0];
548 common_tss[cpu].tss_rsp0 = 0; /* not used until after switch */
549 common_tss[cpu].tss_iobase = sizeof(struct amd64tss) +
551 common_tss[cpu].tss_ist1 = (long)&doublefault_stack[PAGE_SIZE];
553 /* The NMI stack runs on IST2. */
554 np = ((struct nmi_pcpu *) &nmi_stack[PAGE_SIZE]) - 1;
555 common_tss[cpu].tss_ist2 = (long) np;
557 /* Prepare private GDT */
558 gdt_segs[GPROC0_SEL].ssd_base = (long) &common_tss[cpu];
559 for (x = 0; x < NGDT; x++) {
560 if (x != GPROC0_SEL && x != (GPROC0_SEL + 1) &&
561 x != GUSERLDT_SEL && x != (GUSERLDT_SEL + 1))
562 ssdtosd(&gdt_segs[x], &gdt[NGDT * cpu + x]);
564 ssdtosyssd(&gdt_segs[GPROC0_SEL],
565 (struct system_segment_descriptor *)&gdt[NGDT * cpu + GPROC0_SEL]);
566 ap_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1;
567 ap_gdt.rd_base = (long) &gdt[NGDT * cpu];
568 lgdt(&ap_gdt); /* does magic intra-segment return */
570 /* Get per-cpu data */
573 /* prime data page for it to use */
574 pcpu_init(pc, cpu, sizeof(struct pcpu));
575 dpcpu_init(dpcpu, cpu);
576 pc->pc_apic_id = cpu_apic_ids[cpu];
577 pc->pc_prvspace = pc;
578 pc->pc_curthread = 0;
579 pc->pc_tssp = &common_tss[cpu];
580 pc->pc_commontssp = &common_tss[cpu];
582 pc->pc_tss = (struct system_segment_descriptor *)&gdt[NGDT * cpu +
584 pc->pc_fs32p = &gdt[NGDT * cpu + GUFS32_SEL];
585 pc->pc_gs32p = &gdt[NGDT * cpu + GUGS32_SEL];
586 pc->pc_ldt = (struct system_segment_descriptor *)&gdt[NGDT * cpu +
589 /* Save the per-cpu pointer for use by the NMI handler. */
590 np->np_pcpu = (register_t) pc;
592 wrmsr(MSR_FSBASE, 0); /* User value */
593 wrmsr(MSR_GSBASE, (u_int64_t)pc);
594 wrmsr(MSR_KGSBASE, (u_int64_t)pc); /* XXX User value while we're in the kernel */
598 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL);
602 * Set to a known state:
603 * Set by mpboot.s: CR0_PG, CR0_PE
604 * Set by cpu_setregs: CR0_NE, CR0_MP, CR0_TS, CR0_WP, CR0_AM
607 cr0 &= ~(CR0_CD | CR0_NW | CR0_EM);
610 /* Set up the fast syscall stuff */
611 msr = rdmsr(MSR_EFER) | EFER_SCE;
612 wrmsr(MSR_EFER, msr);
613 wrmsr(MSR_LSTAR, (u_int64_t)IDTVEC(fast_syscall));
614 wrmsr(MSR_CSTAR, (u_int64_t)IDTVEC(fast_syscall32));
615 msr = ((u_int64_t)GSEL(GCODE_SEL, SEL_KPL) << 32) |
616 ((u_int64_t)GSEL(GUCODE32_SEL, SEL_UPL) << 48);
617 wrmsr(MSR_STAR, msr);
618 wrmsr(MSR_SF_MASK, PSL_NT|PSL_T|PSL_I|PSL_C|PSL_D);
620 /* Disable local APIC just to be sure. */
623 /* signal our startup to the BSP. */
626 /* Spin until the BSP releases the AP's. */
630 /* Initialize the PAT MSR. */
633 /* set up CPU registers and state */
636 /* set up SSE/NX registers */
639 /* set up FPU state on the AP */
642 /* A quick check from sanity claus */
643 if (PCPU_GET(apic_id) != lapic_id()) {
644 printf("SMP: cpuid = %d\n", PCPU_GET(cpuid));
645 printf("SMP: actual apic_id = %d\n", lapic_id());
646 printf("SMP: correct apic_id = %d\n", PCPU_GET(apic_id));
647 panic("cpuid mismatch! boom!!");
650 /* Initialize curthread. */
651 KASSERT(PCPU_GET(idlethread) != NULL, ("no idle thread"));
652 PCPU_SET(curthread, PCPU_GET(idlethread));
656 mtx_lock_spin(&ap_boot_mtx);
658 /* Init local apic for irq's */
661 /* Set memory range attributes for this CPU to match the BSP */
666 CTR1(KTR_SMP, "SMP: AP CPU #%d Launched", PCPU_GET(cpuid));
667 printf("SMP: AP CPU #%d Launched!\n", PCPU_GET(cpuid));
669 /* Determine if we are a logical CPU. */
670 if (logical_cpus > 1 && PCPU_GET(apic_id) % logical_cpus != 0)
671 logical_cpus_mask |= PCPU_GET(cpumask);
673 /* Determine if we are a hyperthread. */
674 if (hyperthreading_cpus > 1 &&
675 PCPU_GET(apic_id) % hyperthreading_cpus != 0)
676 hyperthreading_cpus_mask |= PCPU_GET(cpumask);
678 /* Build our map of 'other' CPUs. */
679 PCPU_SET(other_cpus, all_cpus & ~PCPU_GET(cpumask));
684 if (smp_cpus == mp_ncpus) {
685 /* enable IPI's, tlb shootdown, freezes etc */
686 atomic_store_rel_int(&smp_started, 1);
687 smp_active = 1; /* historic */
691 * Enable global pages TLB extension
692 * This also implicitly flushes the TLB
695 load_cr4(rcr4() | CR4_PGE);
699 mtx_unlock_spin(&ap_boot_mtx);
701 /* wait until all the AP's are up */
702 while (smp_started == 0)
707 panic("scheduler returned us to %s", __func__);
711 /*******************************************************************
712 * local functions and data
716 * We tell the I/O APIC code about all the CPUs we want to receive
717 * interrupts. If we don't want certain CPUs to receive IRQs we
718 * can simply not tell the I/O APIC code about them in this function.
719 * We also do not tell it about the BSP since it tells itself about
720 * the BSP internally to work with UP kernels and on UP machines.
723 set_interrupt_apic_ids(void)
727 for (i = 0; i < MAXCPU; i++) {
728 apic_id = cpu_apic_ids[i];
731 if (cpu_info[apic_id].cpu_bsp)
733 if (cpu_info[apic_id].cpu_disabled)
736 /* Don't let hyperthreads service interrupts. */
737 if (hyperthreading_cpus > 1 &&
738 apic_id % hyperthreading_cpus != 0)
746 * Assign logical CPU IDs to local APICs.
753 TUNABLE_INT_FETCH("machdep.hyperthreading_allowed",
754 &hyperthreading_allowed);
756 /* Check for explicitly disabled CPUs. */
757 for (i = 0; i <= MAX_APIC_ID; i++) {
758 if (!cpu_info[i].cpu_present || cpu_info[i].cpu_bsp)
761 if (hyperthreading_cpus > 1 && i % hyperthreading_cpus != 0) {
762 cpu_info[i].cpu_hyperthread = 1;
763 #if defined(SCHED_ULE)
765 * Don't use HT CPU if it has been disabled by a
768 if (hyperthreading_allowed == 0) {
769 cpu_info[i].cpu_disabled = 1;
775 /* Don't use this CPU if it has been disabled by a tunable. */
776 if (resource_disabled("lapic", i)) {
777 cpu_info[i].cpu_disabled = 1;
783 * Assign CPU IDs to local APIC IDs and disable any CPUs
784 * beyond MAXCPU. CPU 0 is always assigned to the BSP.
786 * To minimize confusion for userland, we attempt to number
787 * CPUs such that all threads and cores in a package are
788 * grouped together. For now we assume that the BSP is always
789 * the first thread in a package and just start adding APs
790 * starting with the BSP's APIC ID.
793 cpu_apic_ids[0] = boot_cpu_id;
794 apic_cpuids[boot_cpu_id] = 0;
795 for (i = boot_cpu_id + 1; i != boot_cpu_id;
796 i == MAX_APIC_ID ? i = 0 : i++) {
797 if (!cpu_info[i].cpu_present || cpu_info[i].cpu_bsp ||
798 cpu_info[i].cpu_disabled)
801 if (mp_ncpus < MAXCPU) {
802 cpu_apic_ids[mp_ncpus] = i;
803 apic_cpuids[i] = mp_ncpus;
806 cpu_info[i].cpu_disabled = 1;
808 KASSERT(mp_maxid >= mp_ncpus - 1,
809 ("%s: counters out of sync: max %d, count %d", __func__, mp_maxid,
814 * start each AP in our list
819 vm_offset_t va = boot_address + KERNBASE;
820 u_int64_t *pt4, *pt3, *pt2;
821 u_int32_t mpbioswarmvec;
825 mtx_init(&ap_boot_mtx, "ap boot", NULL, MTX_SPIN);
827 /* install the AP 1st level boot code */
828 pmap_kenter(va, boot_address);
829 pmap_invalidate_page(kernel_pmap, va);
830 bcopy(mptramp_start, (void *)va, bootMP_size);
832 /* Locate the page tables, they'll be below the trampoline */
833 pt4 = (u_int64_t *)(uintptr_t)(mptramp_pagetables + KERNBASE);
834 pt3 = pt4 + (PAGE_SIZE) / sizeof(u_int64_t);
835 pt2 = pt3 + (PAGE_SIZE) / sizeof(u_int64_t);
837 /* Create the initial 1GB replicated page tables */
838 for (i = 0; i < 512; i++) {
839 /* Each slot of the level 4 pages points to the same level 3 page */
840 pt4[i] = (u_int64_t)(uintptr_t)(mptramp_pagetables + PAGE_SIZE);
841 pt4[i] |= PG_V | PG_RW | PG_U;
843 /* Each slot of the level 3 pages points to the same level 2 page */
844 pt3[i] = (u_int64_t)(uintptr_t)(mptramp_pagetables + (2 * PAGE_SIZE));
845 pt3[i] |= PG_V | PG_RW | PG_U;
847 /* The level 2 page slots are mapped with 2MB pages for 1GB. */
848 pt2[i] = i * (2 * 1024 * 1024);
849 pt2[i] |= PG_V | PG_RW | PG_PS | PG_U;
852 /* save the current value of the warm-start vector */
853 mpbioswarmvec = *((u_int32_t *) WARMBOOT_OFF);
854 outb(CMOS_REG, BIOS_RESET);
855 mpbiosreason = inb(CMOS_DATA);
857 /* setup a vector to our boot code */
858 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET;
859 *((volatile u_short *) WARMBOOT_SEG) = (boot_address >> 4);
860 outb(CMOS_REG, BIOS_RESET);
861 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */
864 for (cpu = 1; cpu < mp_ncpus; cpu++) {
865 apic_id = cpu_apic_ids[cpu];
867 /* allocate and set up an idle stack data page */
868 bootstacks[cpu] = (void *)kmem_alloc(kernel_map, KSTACK_PAGES * PAGE_SIZE);
869 doublefault_stack = (char *)kmem_alloc(kernel_map, PAGE_SIZE);
870 nmi_stack = (char *)kmem_alloc(kernel_map, PAGE_SIZE);
871 dpcpu = (void *)kmem_alloc(kernel_map, DPCPU_SIZE);
873 bootSTK = (char *)bootstacks[cpu] + KSTACK_PAGES * PAGE_SIZE - 8;
876 /* attempt to start the Application Processor */
877 if (!start_ap(apic_id)) {
878 /* restore the warmstart vector */
879 *(u_int32_t *) WARMBOOT_OFF = mpbioswarmvec;
880 panic("AP #%d (PHY# %d) failed!", cpu, apic_id);
883 all_cpus |= (1 << cpu); /* record AP in CPU map */
886 /* build our map of 'other' CPUs */
887 PCPU_SET(other_cpus, all_cpus & ~PCPU_GET(cpumask));
889 /* restore the warmstart vector */
890 *(u_int32_t *) WARMBOOT_OFF = mpbioswarmvec;
892 outb(CMOS_REG, BIOS_RESET);
893 outb(CMOS_DATA, mpbiosreason);
895 /* number of APs actually started */
901 * This function starts the AP (application processor) identified
902 * by the APIC ID 'physicalCpu'. It does quite a "song and dance"
903 * to accomplish this. This is necessary because of the nuances
904 * of the different hardware we might encounter. It isn't pretty,
905 * but it seems to work.
908 start_ap(int apic_id)
913 /* calculate the vector */
914 vector = (boot_address >> 12) & 0xff;
916 /* used as a watchpoint to signal AP startup */
920 * first we do an INIT/RESET IPI this INIT IPI might be run, reseting
921 * and running the target CPU. OR this INIT IPI might be latched (P5
922 * bug), CPU waiting for STARTUP IPI. OR this INIT IPI might be
926 /* do an INIT IPI: assert RESET */
927 lapic_ipi_raw(APIC_DEST_DESTFLD | APIC_TRIGMOD_EDGE |
928 APIC_LEVEL_ASSERT | APIC_DESTMODE_PHY | APIC_DELMODE_INIT, apic_id);
930 /* wait for pending status end */
933 /* do an INIT IPI: deassert RESET */
934 lapic_ipi_raw(APIC_DEST_ALLESELF | APIC_TRIGMOD_LEVEL |
935 APIC_LEVEL_DEASSERT | APIC_DESTMODE_PHY | APIC_DELMODE_INIT, 0);
937 /* wait for pending status end */
938 DELAY(10000); /* wait ~10mS */
942 * next we do a STARTUP IPI: the previous INIT IPI might still be
943 * latched, (P5 bug) this 1st STARTUP would then terminate
944 * immediately, and the previously started INIT IPI would continue. OR
945 * the previous INIT IPI has already run. and this STARTUP IPI will
946 * run. OR the previous INIT IPI was ignored. and this STARTUP IPI
950 /* do a STARTUP IPI */
951 lapic_ipi_raw(APIC_DEST_DESTFLD | APIC_TRIGMOD_EDGE |
952 APIC_LEVEL_DEASSERT | APIC_DESTMODE_PHY | APIC_DELMODE_STARTUP |
955 DELAY(200); /* wait ~200uS */
958 * finally we do a 2nd STARTUP IPI: this 2nd STARTUP IPI should run IF
959 * the previous STARTUP IPI was cancelled by a latched INIT IPI. OR
960 * this STARTUP IPI will be ignored, as only ONE STARTUP IPI is
961 * recognized after hardware RESET or INIT IPI.
964 lapic_ipi_raw(APIC_DEST_DESTFLD | APIC_TRIGMOD_EDGE |
965 APIC_LEVEL_DEASSERT | APIC_DESTMODE_PHY | APIC_DELMODE_STARTUP |
968 DELAY(200); /* wait ~200uS */
970 /* Wait up to 5 seconds for it to start. */
971 for (ms = 0; ms < 5000; ms++) {
973 return 1; /* return SUCCESS */
976 return 0; /* return FAILURE */
980 * Flush the TLB on all other CPU's
983 smp_tlb_shootdown(u_int vector, vm_offset_t addr1, vm_offset_t addr2)
987 ncpu = mp_ncpus - 1; /* does not shootdown self */
989 return; /* no other cpus */
990 if (!(read_rflags() & PSL_I))
991 panic("%s: interrupts disabled", __func__);
992 mtx_lock_spin(&smp_ipi_mtx);
993 smp_tlb_addr1 = addr1;
994 smp_tlb_addr2 = addr2;
995 atomic_store_rel_int(&smp_tlb_wait, 0);
996 ipi_all_but_self(vector);
997 while (smp_tlb_wait < ncpu)
999 mtx_unlock_spin(&smp_ipi_mtx);
1003 smp_targeted_tlb_shootdown(cpumask_t mask, u_int vector, vm_offset_t addr1, vm_offset_t addr2)
1005 int ncpu, othercpus;
1007 othercpus = mp_ncpus - 1;
1008 if (mask == (u_int)-1) {
1013 mask &= ~PCPU_GET(cpumask);
1016 ncpu = bitcount32(mask);
1017 if (ncpu > othercpus) {
1018 /* XXX this should be a panic offence */
1019 printf("SMP: tlb shootdown to %d other cpus (only have %d)\n",
1023 /* XXX should be a panic, implied by mask == 0 above */
1027 if (!(read_rflags() & PSL_I))
1028 panic("%s: interrupts disabled", __func__);
1029 mtx_lock_spin(&smp_ipi_mtx);
1030 smp_tlb_addr1 = addr1;
1031 smp_tlb_addr2 = addr2;
1032 atomic_store_rel_int(&smp_tlb_wait, 0);
1033 if (mask == (u_int)-1)
1034 ipi_all_but_self(vector);
1036 ipi_selected(mask, vector);
1037 while (smp_tlb_wait < ncpu)
1039 mtx_unlock_spin(&smp_ipi_mtx);
1043 smp_cache_flush(void)
1047 smp_tlb_shootdown(IPI_INVLCACHE, 0, 0);
1055 smp_tlb_shootdown(IPI_INVLTLB, 0, 0);
1060 smp_invlpg(vm_offset_t addr)
1064 smp_tlb_shootdown(IPI_INVLPG, addr, 0);
1068 smp_invlpg_range(vm_offset_t addr1, vm_offset_t addr2)
1072 smp_tlb_shootdown(IPI_INVLRNG, addr1, addr2);
1077 smp_masked_invltlb(cpumask_t mask)
1081 smp_targeted_tlb_shootdown(mask, IPI_INVLTLB, 0, 0);
1086 smp_masked_invlpg(cpumask_t mask, vm_offset_t addr)
1090 smp_targeted_tlb_shootdown(mask, IPI_INVLPG, addr, 0);
1095 smp_masked_invlpg_range(cpumask_t mask, vm_offset_t addr1, vm_offset_t addr2)
1099 smp_targeted_tlb_shootdown(mask, IPI_INVLRNG, addr1, addr2);
1104 ipi_bitmap_handler(struct trapframe frame)
1106 int cpu = PCPU_GET(cpuid);
1109 ipi_bitmap = atomic_readandclear_int(&cpu_ipi_pending[cpu]);
1111 if (ipi_bitmap & (1 << IPI_PREEMPT))
1112 sched_preempt(curthread);
1114 /* Nothing to do for AST */
1116 if (ipi_bitmap & (1 << IPI_HARDCLOCK))
1117 hardclockintr(&frame);
1119 if (ipi_bitmap & (1 << IPI_STATCLOCK))
1120 statclockintr(&frame);
1122 if (ipi_bitmap & (1 << IPI_PROFCLOCK))
1123 profclockintr(&frame);
1127 * send an IPI to a set of cpus.
1130 ipi_selected(cpumask_t cpus, u_int ipi)
1137 if (IPI_IS_BITMAPED(ipi)) {
1139 ipi = IPI_BITMAP_VECTOR;
1143 * IPI_STOP_HARD maps to a NMI and the trap handler needs a bit
1144 * of help in order to understand what is the source.
1145 * Set the mask of receiving CPUs for this purpose.
1147 if (ipi == IPI_STOP_HARD)
1148 atomic_set_int(&ipi_nmi_pending, cpus);
1150 CTR3(KTR_SMP, "%s: cpus: %x ipi: %x", __func__, cpus, ipi);
1151 while ((cpu = ffs(cpus)) != 0) {
1153 cpus &= ~(1 << cpu);
1155 KASSERT(cpu_apic_ids[cpu] != -1,
1156 ("IPI to non-existent CPU %d", cpu));
1160 old_pending = cpu_ipi_pending[cpu];
1161 new_pending = old_pending | bitmap;
1162 } while (!atomic_cmpset_int(&cpu_ipi_pending[cpu],old_pending, new_pending));
1168 lapic_ipi_vectored(ipi, cpu_apic_ids[cpu]);
1174 * send an IPI to all CPUs EXCEPT myself
1177 ipi_all_but_self(u_int ipi)
1180 if (IPI_IS_BITMAPED(ipi)) {
1181 ipi_selected(PCPU_GET(other_cpus), ipi);
1186 * IPI_STOP_HARD maps to a NMI and the trap handler needs a bit
1187 * of help in order to understand what is the source.
1188 * Set the mask of receiving CPUs for this purpose.
1190 if (ipi == IPI_STOP_HARD)
1191 atomic_set_int(&ipi_nmi_pending, PCPU_GET(other_cpus));
1193 CTR2(KTR_SMP, "%s: ipi: %x", __func__, ipi);
1194 lapic_ipi_vectored(ipi, APIC_IPI_DEST_OTHERS);
1203 * As long as there is not a simple way to know about a NMI's
1204 * source, if the bitmask for the current CPU is present in
1205 * the global pending bitword an IPI_STOP_HARD has been issued
1206 * and should be handled.
1208 cpumask = PCPU_GET(cpumask);
1209 if ((ipi_nmi_pending & cpumask) == 0)
1212 atomic_clear_int(&ipi_nmi_pending, cpumask);
1218 * Handle an IPI_STOP by saving our current context and spinning until we
1222 cpustop_handler(void)
1224 int cpu = PCPU_GET(cpuid);
1225 int cpumask = PCPU_GET(cpumask);
1227 savectx(&stoppcbs[cpu]);
1229 /* Indicate that we are stopped */
1230 atomic_set_int(&stopped_cpus, cpumask);
1232 /* Wait for restart */
1233 while (!(started_cpus & cpumask))
1236 atomic_clear_int(&started_cpus, cpumask);
1237 atomic_clear_int(&stopped_cpus, cpumask);
1239 if (cpu == 0 && cpustop_restartfunc != NULL) {
1240 cpustop_restartfunc();
1241 cpustop_restartfunc = NULL;
1246 * Handle an IPI_SUSPEND by saving our current context and spinning until we
1250 cpususpend_handler(void)
1252 struct savefpu *stopfpu;
1254 int cpu = PCPU_GET(cpuid);
1255 int cpumask = PCPU_GET(cpumask);
1257 rf = intr_disable();
1259 stopfpu = &stopxpcbs[cpu].xpcb_pcb.pcb_save;
1260 if (savectx2(&stopxpcbs[cpu])) {
1261 fpugetregs(curthread, stopfpu);
1263 atomic_set_int(&stopped_cpus, cpumask);
1265 fpusetregs(curthread, stopfpu);
1267 /* Wait for resume */
1268 while (!(started_cpus & cpumask))
1271 atomic_clear_int(&started_cpus, cpumask);
1272 atomic_clear_int(&stopped_cpus, cpumask);
1274 /* Restore CR3 and enable interrupts */
1281 * This is called once the rest of the system is up and running and we're
1282 * ready to let the AP's out of the pen.
1285 release_aps(void *dummy __unused)
1290 atomic_store_rel_int(&aps_ready, 1);
1291 while (smp_started == 0)
1294 SYSINIT(start_aps, SI_SUB_SMP, SI_ORDER_FIRST, release_aps, NULL);
1297 sysctl_hlt_cpus(SYSCTL_HANDLER_ARGS)
1302 mask = hlt_cpus_mask;
1303 error = sysctl_handle_int(oidp, &mask, 0, req);
1304 if (error || !req->newptr)
1307 if (logical_cpus_mask != 0 &&
1308 (mask & logical_cpus_mask) == logical_cpus_mask)
1309 hlt_logical_cpus = 1;
1311 hlt_logical_cpus = 0;
1313 if (! hyperthreading_allowed)
1314 mask |= hyperthreading_cpus_mask;
1316 if ((mask & all_cpus) == all_cpus)
1318 hlt_cpus_mask = mask;
1321 SYSCTL_PROC(_machdep, OID_AUTO, hlt_cpus, CTLTYPE_INT|CTLFLAG_RW,
1322 0, 0, sysctl_hlt_cpus, "IU",
1323 "Bitmap of CPUs to halt. 101 (binary) will halt CPUs 0 and 2.");
1326 sysctl_hlt_logical_cpus(SYSCTL_HANDLER_ARGS)
1330 disable = hlt_logical_cpus;
1331 error = sysctl_handle_int(oidp, &disable, 0, req);
1332 if (error || !req->newptr)
1336 hlt_cpus_mask |= logical_cpus_mask;
1338 hlt_cpus_mask &= ~logical_cpus_mask;
1340 if (! hyperthreading_allowed)
1341 hlt_cpus_mask |= hyperthreading_cpus_mask;
1343 if ((hlt_cpus_mask & all_cpus) == all_cpus)
1344 hlt_cpus_mask &= ~(1<<0);
1346 hlt_logical_cpus = disable;
1351 sysctl_hyperthreading_allowed(SYSCTL_HANDLER_ARGS)
1355 allowed = hyperthreading_allowed;
1356 error = sysctl_handle_int(oidp, &allowed, 0, req);
1357 if (error || !req->newptr)
1362 * SCHED_ULE doesn't allow enabling/disabling HT cores at
1365 if (allowed != hyperthreading_allowed)
1371 hlt_cpus_mask &= ~hyperthreading_cpus_mask;
1373 hlt_cpus_mask |= hyperthreading_cpus_mask;
1375 if (logical_cpus_mask != 0 &&
1376 (hlt_cpus_mask & logical_cpus_mask) == logical_cpus_mask)
1377 hlt_logical_cpus = 1;
1379 hlt_logical_cpus = 0;
1381 if ((hlt_cpus_mask & all_cpus) == all_cpus)
1382 hlt_cpus_mask &= ~(1<<0);
1384 hyperthreading_allowed = allowed;
1389 cpu_hlt_setup(void *dummy __unused)
1392 if (logical_cpus_mask != 0) {
1393 TUNABLE_INT_FETCH("machdep.hlt_logical_cpus",
1395 sysctl_ctx_init(&logical_cpu_clist);
1396 SYSCTL_ADD_PROC(&logical_cpu_clist,
1397 SYSCTL_STATIC_CHILDREN(_machdep), OID_AUTO,
1398 "hlt_logical_cpus", CTLTYPE_INT|CTLFLAG_RW, 0, 0,
1399 sysctl_hlt_logical_cpus, "IU", "");
1400 SYSCTL_ADD_UINT(&logical_cpu_clist,
1401 SYSCTL_STATIC_CHILDREN(_machdep), OID_AUTO,
1402 "logical_cpus_mask", CTLTYPE_INT|CTLFLAG_RD,
1403 &logical_cpus_mask, 0, "");
1405 if (hlt_logical_cpus)
1406 hlt_cpus_mask |= logical_cpus_mask;
1409 * If necessary for security purposes, force
1410 * hyperthreading off, regardless of the value
1411 * of hlt_logical_cpus.
1413 if (hyperthreading_cpus_mask) {
1414 SYSCTL_ADD_PROC(&logical_cpu_clist,
1415 SYSCTL_STATIC_CHILDREN(_machdep), OID_AUTO,
1416 "hyperthreading_allowed", CTLTYPE_INT|CTLFLAG_RW,
1417 0, 0, sysctl_hyperthreading_allowed, "IU", "");
1418 if (! hyperthreading_allowed)
1419 hlt_cpus_mask |= hyperthreading_cpus_mask;
1423 SYSINIT(cpu_hlt, SI_SUB_SMP, SI_ORDER_ANY, cpu_hlt_setup, NULL);
1426 mp_grab_cpu_hlt(void)
1428 u_int mask = PCPU_GET(cpumask);
1430 u_int cpuid = PCPU_GET(cpuid);
1438 retval = mask & hlt_cpus_mask;
1439 while (mask & hlt_cpus_mask)
1440 __asm __volatile("sti; hlt" : : : "memory");