1 /* $NetBSD: cpu.c,v 1.55 2004/02/13 11:36:10 wiz Exp $ */
4 * Copyright (c) 1995 Mark Brinicombe.
5 * Copyright (c) 1995 Brini.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. All advertising materials mentioning features or use of this software
17 * must display the following acknowledgement:
18 * This product includes software developed by Brini.
19 * 4. The name of the company nor the name of the author may be used to
20 * endorse or promote products derived from this software without specific
21 * prior written permission.
23 * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED
24 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
25 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
26 * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
27 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
29 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
35 * RiscBSD kernel project
39 * Probing and configuration for the master CPU
44 #include <sys/cdefs.h>
45 __FBSDID("$FreeBSD$");
46 #include <sys/systm.h>
47 #include <sys/param.h>
48 #include <sys/malloc.h>
52 #include <sys/kernel.h>
53 #include <sys/sysctl.h>
54 #include <machine/cpu.h>
56 #include <machine/cpuconf.h>
58 char machine[] = "arm";
60 SYSCTL_STRING(_hw, HW_MACHINE, machine, CTLFLAG_RD,
61 machine, 0, "Machine class");
82 static const char * const generic_steppings[16] = {
83 "rev 0", "rev 1", "rev 2", "rev 3",
84 "rev 4", "rev 5", "rev 6", "rev 7",
85 "rev 8", "rev 9", "rev 10", "rev 11",
86 "rev 12", "rev 13", "rev 14", "rev 15",
89 static const char * const sa110_steppings[16] = {
90 "rev 0", "step J", "step K", "step S",
91 "step T", "rev 5", "rev 6", "rev 7",
92 "rev 8", "rev 9", "rev 10", "rev 11",
93 "rev 12", "rev 13", "rev 14", "rev 15",
96 static const char * const sa1100_steppings[16] = {
97 "rev 0", "step B", "step C", "rev 3",
98 "rev 4", "rev 5", "rev 6", "rev 7",
99 "step D", "step E", "rev 10" "step G",
100 "rev 12", "rev 13", "rev 14", "rev 15",
103 static const char * const sa1110_steppings[16] = {
104 "step A-0", "rev 1", "rev 2", "rev 3",
105 "step B-0", "step B-1", "step B-2", "step B-3",
106 "step B-4", "step B-5", "rev 10", "rev 11",
107 "rev 12", "rev 13", "rev 14", "rev 15",
110 static const char * const ixp12x0_steppings[16] = {
111 "(IXP1200 step A)", "(IXP1200 step B)",
112 "rev 2", "(IXP1200 step C)",
113 "(IXP1200 step D)", "(IXP1240/1250 step A)",
114 "(IXP1240 step B)", "(IXP1250 step B)",
115 "rev 8", "rev 9", "rev 10", "rev 11",
116 "rev 12", "rev 13", "rev 14", "rev 15",
119 static const char * const xscale_steppings[16] = {
120 "step A-0", "step A-1", "step B-0", "step C-0",
121 "step D-0", "rev 5", "rev 6", "rev 7",
122 "rev 8", "rev 9", "rev 10", "rev 11",
123 "rev 12", "rev 13", "rev 14", "rev 15",
126 static const char * const i80219_steppings[16] = {
127 "step A-0", "rev 1", "rev 2", "rev 3",
128 "rev 4", "rev 5", "rev 6", "rev 7",
129 "rev 8", "rev 9", "rev 10", "rev 11",
130 "rev 12", "rev 13", "rev 14", "rev 15",
133 static const char * const i80321_steppings[16] = {
134 "step A-0", "step B-0", "rev 2", "rev 3",
135 "rev 4", "rev 5", "rev 6", "rev 7",
136 "rev 8", "rev 9", "rev 10", "rev 11",
137 "rev 12", "rev 13", "rev 14", "rev 15",
140 static const char * const i81342_steppings[16] = {
141 "step A-0", "rev 1", "rev 2", "rev 3",
142 "rev 4", "rev 5", "rev 6", "rev 7",
143 "rev 8", "rev 9", "rev 10", "rev 11",
144 "rev 12", "rev 13", "rev 14", "rev 15",
147 /* Steppings for PXA2[15]0 */
148 static const char * const pxa2x0_steppings[16] = {
149 "step A-0", "step A-1", "step B-0", "step B-1",
150 "step B-2", "step C-0", "rev 6", "rev 7",
151 "rev 8", "rev 9", "rev 10", "rev 11",
152 "rev 12", "rev 13", "rev 14", "rev 15",
155 /* Steppings for PXA255/26x.
156 * rev 5: PXA26x B0, rev 6: PXA255 A0
158 static const char * const pxa255_steppings[16] = {
159 "rev 0", "rev 1", "rev 2", "step A-0",
160 "rev 4", "step B-0", "step A-0", "rev 7",
161 "rev 8", "rev 9", "rev 10", "rev 11",
162 "rev 12", "rev 13", "rev 14", "rev 15",
165 /* Stepping for PXA27x */
166 static const char * const pxa27x_steppings[16] = {
167 "step A-0", "step A-1", "step B-0", "step B-1",
168 "step C-0", "rev 5", "rev 6", "rev 7",
169 "rev 8", "rev 9", "rev 10", "rev 11",
170 "rev 12", "rev 13", "rev 14", "rev 15",
173 static const char * const ixp425_steppings[16] = {
174 "step 0 (A0)", "rev 1 (ARMv5TE)", "rev 2", "rev 3",
175 "rev 4", "rev 5", "rev 6", "rev 7",
176 "rev 8", "rev 9", "rev 10", "rev 11",
177 "rev 12", "rev 13", "rev 14", "rev 15",
182 enum cpu_class cpu_class;
183 const char *cpu_name;
184 const char * const *cpu_steppings;
187 const struct cpuidtab cpuids[] = {
188 { CPU_ID_ARM2, CPU_CLASS_ARM2, "ARM2",
190 { CPU_ID_ARM250, CPU_CLASS_ARM2AS, "ARM250",
193 { CPU_ID_ARM3, CPU_CLASS_ARM3, "ARM3",
196 { CPU_ID_ARM600, CPU_CLASS_ARM6, "ARM600",
198 { CPU_ID_ARM610, CPU_CLASS_ARM6, "ARM610",
200 { CPU_ID_ARM620, CPU_CLASS_ARM6, "ARM620",
203 { CPU_ID_ARM700, CPU_CLASS_ARM7, "ARM700",
205 { CPU_ID_ARM710, CPU_CLASS_ARM7, "ARM710",
207 { CPU_ID_ARM7500, CPU_CLASS_ARM7, "ARM7500",
209 { CPU_ID_ARM710A, CPU_CLASS_ARM7, "ARM710a",
211 { CPU_ID_ARM7500FE, CPU_CLASS_ARM7, "ARM7500FE",
213 { CPU_ID_ARM710T, CPU_CLASS_ARM7TDMI, "ARM710T",
215 { CPU_ID_ARM720T, CPU_CLASS_ARM7TDMI, "ARM720T",
217 { CPU_ID_ARM740T8K, CPU_CLASS_ARM7TDMI, "ARM740T (8 KB cache)",
219 { CPU_ID_ARM740T4K, CPU_CLASS_ARM7TDMI, "ARM740T (4 KB cache)",
222 { CPU_ID_ARM810, CPU_CLASS_ARM8, "ARM810",
225 { CPU_ID_ARM920T, CPU_CLASS_ARM9TDMI, "ARM920T",
227 { CPU_ID_ARM920T_ALT, CPU_CLASS_ARM9TDMI, "ARM920T",
229 { CPU_ID_ARM922T, CPU_CLASS_ARM9TDMI, "ARM922T",
231 { CPU_ID_ARM926EJS, CPU_CLASS_ARM9EJS, "ARM926EJ-S",
233 { CPU_ID_ARM940T, CPU_CLASS_ARM9TDMI, "ARM940T",
235 { CPU_ID_ARM946ES, CPU_CLASS_ARM9ES, "ARM946E-S",
237 { CPU_ID_ARM966ES, CPU_CLASS_ARM9ES, "ARM966E-S",
239 { CPU_ID_ARM966ESR1, CPU_CLASS_ARM9ES, "ARM966E-S",
241 { CPU_ID_TI925T, CPU_CLASS_ARM9TDMI, "TI ARM925T",
244 { CPU_ID_ARM1020E, CPU_CLASS_ARM10E, "ARM1020E",
246 { CPU_ID_ARM1022ES, CPU_CLASS_ARM10E, "ARM1022E-S",
248 { CPU_ID_ARM1026EJS, CPU_CLASS_ARM10EJ, "ARM1026EJ-S",
251 { CPU_ID_SA110, CPU_CLASS_SA1, "SA-110",
253 { CPU_ID_SA1100, CPU_CLASS_SA1, "SA-1100",
255 { CPU_ID_SA1110, CPU_CLASS_SA1, "SA-1110",
258 { CPU_ID_IXP1200, CPU_CLASS_SA1, "IXP1200",
261 { CPU_ID_80200, CPU_CLASS_XSCALE, "i80200",
264 { CPU_ID_80321_400, CPU_CLASS_XSCALE, "i80321 400MHz",
266 { CPU_ID_80321_600, CPU_CLASS_XSCALE, "i80321 600MHz",
268 { CPU_ID_80321_400_B0, CPU_CLASS_XSCALE, "i80321 400MHz",
270 { CPU_ID_80321_600_B0, CPU_CLASS_XSCALE, "i80321 600MHz",
273 { CPU_ID_81342, CPU_CLASS_XSCALE, "i81342",
276 { CPU_ID_80219_400, CPU_CLASS_XSCALE, "i80219 400MHz",
278 { CPU_ID_80219_600, CPU_CLASS_XSCALE, "i80219 600MHz",
281 { CPU_ID_PXA27X, CPU_CLASS_XSCALE, "PXA27x",
283 { CPU_ID_PXA250A, CPU_CLASS_XSCALE, "PXA250",
285 { CPU_ID_PXA210A, CPU_CLASS_XSCALE, "PXA210",
287 { CPU_ID_PXA250B, CPU_CLASS_XSCALE, "PXA250",
289 { CPU_ID_PXA210B, CPU_CLASS_XSCALE, "PXA210",
291 { CPU_ID_PXA250C, CPU_CLASS_XSCALE, "PXA255",
293 { CPU_ID_PXA210C, CPU_CLASS_XSCALE, "PXA210",
296 { CPU_ID_IXP425_533, CPU_CLASS_XSCALE, "IXP425 533MHz",
298 { CPU_ID_IXP425_400, CPU_CLASS_XSCALE, "IXP425 400MHz",
300 { CPU_ID_IXP425_266, CPU_CLASS_XSCALE, "IXP425 266MHz",
303 /* XXX ixp435 steppings? */
304 { CPU_ID_IXP435, CPU_CLASS_XSCALE, "IXP435",
307 { CPU_ID_ARM1136JS, CPU_CLASS_ARM11J, "ARM1136J-S",
309 { CPU_ID_ARM1136JSR1, CPU_CLASS_ARM11J, "ARM1136J-S R1",
312 { CPU_ID_MV88FR131, CPU_CLASS_MARVELL, "Feroceon 88FR131",
315 { CPU_ID_MV88FR571_VD, CPU_CLASS_MARVELL, "Feroceon 88FR571-VD",
318 { CPU_ID_MV88FR571_41, CPU_CLASS_MARVELL, "Early Feroceon 88FR571",
321 { 0, CPU_CLASS_NONE, NULL, NULL }
324 struct cpu_classtab {
325 const char *class_name;
326 const char *class_option;
329 const struct cpu_classtab cpu_classes[] = {
330 { "unknown", NULL }, /* CPU_CLASS_NONE */
331 { "ARM2", "CPU_ARM2" }, /* CPU_CLASS_ARM2 */
332 { "ARM2as", "CPU_ARM250" }, /* CPU_CLASS_ARM2AS */
333 { "ARM3", "CPU_ARM3" }, /* CPU_CLASS_ARM3 */
334 { "ARM6", "CPU_ARM6" }, /* CPU_CLASS_ARM6 */
335 { "ARM7", "CPU_ARM7" }, /* CPU_CLASS_ARM7 */
336 { "ARM7TDMI", "CPU_ARM7TDMI" }, /* CPU_CLASS_ARM7TDMI */
337 { "ARM8", "CPU_ARM8" }, /* CPU_CLASS_ARM8 */
338 { "ARM9TDMI", "CPU_ARM9TDMI" }, /* CPU_CLASS_ARM9TDMI */
339 { "ARM9E-S", "CPU_ARM9E" }, /* CPU_CLASS_ARM9ES */
340 { "ARM9EJ-S", "CPU_ARM9E" }, /* CPU_CLASS_ARM9EJS */
341 { "ARM10E", "CPU_ARM10" }, /* CPU_CLASS_ARM10E */
342 { "ARM10EJ", "CPU_ARM10" }, /* CPU_CLASS_ARM10EJ */
343 { "SA-1", "CPU_SA110" }, /* CPU_CLASS_SA1 */
344 { "XScale", "CPU_XSCALE_..." }, /* CPU_CLASS_XSCALE */
345 { "ARM11J", "CPU_ARM11" }, /* CPU_CLASS_ARM11J */
346 { "Marvell", "CPU_MARVELL" }, /* CPU_CLASS_MARVELL */
350 * Report the type of the specified arm processor. This uses the generic and
351 * arm specific information in the cpu structure to identify the processor.
352 * The remaining fields in the cpu structure are filled in appropriately.
355 static const char * const wtnames[] = {
361 "write-back-locking", /* XXX XScale-specific? */
362 "write-back-locking-A",
363 "write-back-locking-B",
370 "write-back-locking-C",
377 identify_arm_cpu(void)
380 enum cpu_class cpu_class = CPU_CLASS_NONE;
386 printf("Processor failed probe - no CPU ID\n");
390 for (i = 0; cpuids[i].cpuid != 0; i++)
391 if (cpuids[i].cpuid == (cpuid & CPU_ID_CPU_MASK)) {
392 cpu_class = cpuids[i].cpu_class;
393 printf("CPU: %s %s (%s core)\n",
395 cpuids[i].cpu_steppings[cpuid &
396 CPU_ID_REVISION_MASK],
397 cpu_classes[cpu_class].class_name);
400 if (cpuids[i].cpuid == 0)
401 printf("unknown CPU (ID = 0x%x)\n", cpuid);
407 case CPU_CLASS_ARM7TDMI:
409 if ((ctrl & CPU_CONTROL_IDC_ENABLE) == 0)
410 printf(" IDC disabled");
412 printf(" IDC enabled");
414 case CPU_CLASS_ARM9TDMI:
415 case CPU_CLASS_ARM9ES:
416 case CPU_CLASS_ARM9EJS:
417 case CPU_CLASS_ARM10E:
418 case CPU_CLASS_ARM10EJ:
420 case CPU_CLASS_XSCALE:
421 case CPU_CLASS_ARM11J:
422 case CPU_CLASS_MARVELL:
423 if ((ctrl & CPU_CONTROL_DC_ENABLE) == 0)
424 printf(" DC disabled");
426 printf(" DC enabled");
427 if ((ctrl & CPU_CONTROL_IC_ENABLE) == 0)
428 printf(" IC disabled");
430 printf(" IC enabled");
431 #ifdef CPU_XSCALE_81342
432 if ((ctrl & CPU_CONTROL_L2_ENABLE) == 0)
433 printf(" L2 disabled");
435 printf(" L2 enabled");
441 if ((ctrl & CPU_CONTROL_WBUF_ENABLE) == 0)
442 printf(" WB disabled");
444 printf(" WB enabled");
446 if (ctrl & CPU_CONTROL_LABT_ENABLE)
451 if (ctrl & CPU_CONTROL_BPRD_ENABLE)
452 printf(" branch prediction enabled");
455 /* Print cache info. */
456 if (arm_picache_line_size == 0 && arm_pdcache_line_size == 0)
459 if (arm_pcache_unified) {
460 printf(" %dKB/%dB %d-way %s unified cache\n",
461 arm_pdcache_size / 1024,
462 arm_pdcache_line_size, arm_pdcache_ways,
463 wtnames[arm_pcache_type]);
465 printf(" %dKB/%dB %d-way Instruction cache\n",
466 arm_picache_size / 1024,
467 arm_picache_line_size, arm_picache_ways);
468 printf(" %dKB/%dB %d-way %s Data cache\n",
469 arm_pdcache_size / 1024,
470 arm_pdcache_line_size, arm_pdcache_ways,
471 wtnames[arm_pcache_type]);