4 * These defines come from an atmel file that says specifically that it
8 //*****************************************************************************
9 // PIO DEFINITIONS FOR AT91RM9200
10 //*****************************************************************************
11 #define AT91C_PIO_PA0 (1u << 0) // Pin Controlled by PA0
12 #define AT91C_PA0_MISO (AT91C_PIO_PA0) // SPI Master In Slave
13 #define AT91C_PA0_PCK3 (AT91C_PIO_PA0) // PMC Programmable Clock Output 3
14 #define AT91C_PIO_PA1 (1u << 1) // Pin Controlled by PA1
15 #define AT91C_PA1_MOSI (AT91C_PIO_PA1) // SPI Master Out Slave
16 #define AT91C_PA1_PCK0 (AT91C_PIO_PA1) // PMC Programmable Clock Output 0
17 #define AT91C_PIO_PA10 (1u << 10) // Pin Controlled by PA10
18 #define AT91C_PA10_ETX1 (AT91C_PIO_PA10) // Ethernet MAC Transmit Data 1
19 #define AT91C_PA10_MCDB1 (AT91C_PIO_PA10) // Multimedia Card B Data 1
20 #define AT91C_PIO_PA11 (1u << 11) // Pin Controlled by PA11
21 #define AT91C_PA11_ECRS_ECRSDV (AT91C_PIO_PA11) // Ethernet MAC Carrier Sense/Carrier Sense and Data Valid
22 #define AT91C_PA11_MCDB2 (AT91C_PIO_PA11) // Multimedia Card B Data 2
23 #define AT91C_PIO_PA12 (1u << 12) // Pin Controlled by PA12
24 #define AT91C_PA12_ERX0 (AT91C_PIO_PA12) // Ethernet MAC Receive Data 0
25 #define AT91C_PA12_MCDB3 (AT91C_PIO_PA12) // Multimedia Card B Data 3
26 #define AT91C_PIO_PA13 (1u << 13) // Pin Controlled by PA13
27 #define AT91C_PA13_ERX1 (AT91C_PIO_PA13) // Ethernet MAC Receive Data 1
28 #define AT91C_PA13_TCLK0 (AT91C_PIO_PA13) // Timer Counter 0 external clock input
29 #define AT91C_PIO_PA14 (1u << 14) // Pin Controlled by PA14
30 #define AT91C_PA14_ERXER (AT91C_PIO_PA14) // Ethernet MAC Receive Error
31 #define AT91C_PA14_TCLK1 (AT91C_PIO_PA14) // Timer Counter 1 external clock input
32 #define AT91C_PIO_PA15 (1u << 15) // Pin Controlled by PA15
33 #define AT91C_PA15_EMDC (AT91C_PIO_PA15) // Ethernet MAC Management Data Clock
34 #define AT91C_PA15_TCLK2 (AT91C_PIO_PA15) // Timer Counter 2 external clock input
35 #define AT91C_PIO_PA16 (1u << 16) // Pin Controlled by PA16
36 #define AT91C_PA16_EMDIO (AT91C_PIO_PA16) // Ethernet MAC Management Data Input/Output
37 #define AT91C_PA16_IRQ6 (AT91C_PIO_PA16) // AIC Interrupt input 6
38 #define AT91C_PIO_PA17 (1u << 17) // Pin Controlled by PA17
39 #define AT91C_PA17_TXD0 (AT91C_PIO_PA17) // USART 0 Transmit Data
40 #define AT91C_PA17_TIOA0 (AT91C_PIO_PA17) // Timer Counter 0 Multipurpose Timer I/O Pin A
41 #define AT91C_PIO_PA18 (1u << 18) // Pin Controlled by PA18
42 #define AT91C_PA18_RXD0 (AT91C_PIO_PA18) // USART 0 Receive Data
43 #define AT91C_PA18_TIOB0 (AT91C_PIO_PA18) // Timer Counter 0 Multipurpose Timer I/O Pin B
44 #define AT91C_PIO_PA19 (1u << 19) // Pin Controlled by PA19
45 #define AT91C_PA19_SCK0 (AT91C_PIO_PA19) // USART 0 Serial Clock
46 #define AT91C_PA19_TIOA1 (AT91C_PIO_PA19) // Timer Counter 1 Multipurpose Timer I/O Pin A
47 #define AT91C_PIO_PA2 (1u << 2) // Pin Controlled by PA2
48 #define AT91C_PA2_SPCK (AT91C_PIO_PA2) // SPI Serial Clock
49 #define AT91C_PA2_IRQ4 (AT91C_PIO_PA2) // AIC Interrupt Input 4
50 #define AT91C_PIO_PA20 (1u << 20) // Pin Controlled by PA20
51 #define AT91C_PA20_CTS0 (AT91C_PIO_PA20) // USART 0 Clear To Send
52 #define AT91C_PA20_TIOB1 (AT91C_PIO_PA20) // Timer Counter 1 Multipurpose Timer I/O Pin B
53 #define AT91C_PIO_PA21 (1u << 21) // Pin Controlled by PA21
54 #define AT91C_PA21_RTS0 (AT91C_PIO_PA21) // Usart 0 Ready To Send
55 #define AT91C_PA21_TIOA2 (AT91C_PIO_PA21) // Timer Counter 2 Multipurpose Timer I/O Pin A
56 #define AT91C_PIO_PA22 (1u << 22) // Pin Controlled by PA22
57 #define AT91C_PA22_RXD2 (AT91C_PIO_PA22) // USART 2 Receive Data
58 #define AT91C_PA22_TIOB2 (AT91C_PIO_PA22) // Timer Counter 2 Multipurpose Timer I/O Pin B
59 #define AT91C_PIO_PA23 (1u << 23) // Pin Controlled by PA23
60 #define AT91C_PA23_TXD2 (AT91C_PIO_PA23) // USART 2 Transmit Data
61 #define AT91C_PA23_IRQ3 (AT91C_PIO_PA23) // Interrupt input 3
62 #define AT91C_PIO_PA24 (1u << 24) // Pin Controlled by PA24
63 #define AT91C_PA24_SCK2 (AT91C_PIO_PA24) // USART2 Serial Clock
64 #define AT91C_PA24_PCK1 (AT91C_PIO_PA24) // PMC Programmable Clock Output 1
65 #define AT91C_PIO_PA25 (1u << 25) // Pin Controlled by PA25
66 #define AT91C_PA25_TWD (AT91C_PIO_PA25) // TWI Two-wire Serial Data
67 #define AT91C_PA25_IRQ2 (AT91C_PIO_PA25) // Interrupt input 2
68 #define AT91C_PIO_PA26 (1u << 26) // Pin Controlled by PA26
69 #define AT91C_PA26_TWCK (AT91C_PIO_PA26) // TWI Two-wire Serial Clock
70 #define AT91C_PA26_IRQ1 (AT91C_PIO_PA26) // Interrupt input 1
71 #define AT91C_PIO_PA27 (1u << 27) // Pin Controlled by PA27
72 #define AT91C_PA27_MCCK (AT91C_PIO_PA27) // Multimedia Card Clock
73 #define AT91C_PA27_TCLK3 (AT91C_PIO_PA27) // Timer Counter 3 External Clock Input
74 #define AT91C_PIO_PA28 (1u << 28) // Pin Controlled by PA28
75 #define AT91C_PA28_MCCDA (AT91C_PIO_PA28) // Multimedia Card A Command
76 #define AT91C_PA28_TCLK4 (AT91C_PIO_PA28) // Timer Counter 4 external Clock Input
77 #define AT91C_PIO_PA29 (1u << 29) // Pin Controlled by PA29
78 #define AT91C_PA29_MCDA0 (AT91C_PIO_PA29) // Multimedia Card A Data 0
79 #define AT91C_PA29_TCLK5 (AT91C_PIO_PA29) // Timer Counter 5 external clock input
80 #define AT91C_PIO_PA3 (1u << 3) // Pin Controlled by PA3
81 #define AT91C_PA3_NPCS0 (AT91C_PIO_PA3) // SPI Peripheral Chip Select 0
82 #define AT91C_PA3_IRQ5 (AT91C_PIO_PA3) // AIC Interrupt Input 5
83 #define AT91C_PIO_PA30 (1u << 30) // Pin Controlled by PA30
84 #define AT91C_PA30_DRXD (AT91C_PIO_PA30) // DBGU Debug Receive Data
85 #define AT91C_PA30_CTS2 (AT91C_PIO_PA30) // Usart 2 Clear To Send
86 #define AT91C_PIO_PA31 (1u << 31) // Pin Controlled by PA31
87 #define AT91C_PA31_DTXD (AT91C_PIO_PA31) // DBGU Debug Transmit Data
88 #define AT91C_PA31_RTS2 (AT91C_PIO_PA31) // USART 2 Ready To Send
89 #define AT91C_PIO_PA4 (1u << 4) // Pin Controlled by PA4
90 #define AT91C_PA4_NPCS1 (AT91C_PIO_PA4) // SPI Peripheral Chip Select 1
91 #define AT91C_PA4_PCK1 (AT91C_PIO_PA4) // PMC Programmable Clock Output 1
92 #define AT91C_PIO_PA5 (1u << 5) // Pin Controlled by PA5
93 #define AT91C_PA5_NPCS2 (AT91C_PIO_PA5) // SPI Peripheral Chip Select 2
94 #define AT91C_PA5_TXD3 (AT91C_PIO_PA5) // USART 3 Transmit Data
95 #define AT91C_PIO_PA6 (1u << 6) // Pin Controlled by PA6
96 #define AT91C_PA6_NPCS3 (AT91C_PIO_PA6) // SPI Peripheral Chip Select 3
97 #define AT91C_PA6_RXD3 (AT91C_PIO_PA6) // USART 3 Receive Data
98 #define AT91C_PIO_PA7 (1u << 7) // Pin Controlled by PA7
99 #define AT91C_PA7_ETXCK_EREFCK (AT91C_PIO_PA7) // Ethernet MAC Transmit Clock/Reference Clock
100 #define AT91C_PA7_PCK2 (AT91C_PIO_PA7) // PMC Programmable Clock 2
101 #define AT91C_PIO_PA8 (1u << 8) // Pin Controlled by PA8
102 #define AT91C_PA8_ETXEN (AT91C_PIO_PA8) // Ethernet MAC Transmit Enable
103 #define AT91C_PA8_MCCDB (AT91C_PIO_PA8) // Multimedia Card B Command
104 #define AT91C_PIO_PA9 (1u << 9) // Pin Controlled by PA9
105 #define AT91C_PA9_ETX0 (AT91C_PIO_PA9) // Ethernet MAC Transmit Data 0
106 #define AT91C_PA9_MCDB0 (AT91C_PIO_PA9) // Multimedia Card B Data 0
107 #define AT91C_PIO_PB0 (1u << 0) // Pin Controlled by PB0
108 #define AT91C_PB0_TF0 (AT91C_PIO_PB0) // SSC Transmit Frame Sync 0
109 #define AT91C_PB0_TIOB3 (AT91C_PIO_PB0) // Timer Counter 3 Multipurpose Timer I/O Pin B
110 #define AT91C_PIO_PB1 (1u << 1) // Pin Controlled by PB1
111 #define AT91C_PB1_TK0 (AT91C_PIO_PB1) // SSC Transmit Clock 0
112 #define AT91C_PB1_CTS3 (AT91C_PIO_PB1) // USART 3 Clear To Send
113 #define AT91C_PIO_PB10 (1u << 10) // Pin Controlled by PB10
114 #define AT91C_PB10_RK1 (AT91C_PIO_PB10) // SSC Receive Clock 1
115 #define AT91C_PB10_TIOA5 (AT91C_PIO_PB10) // Timer Counter 5 Multipurpose Timer I/O Pin A
116 #define AT91C_PIO_PB11 (1u << 11) // Pin Controlled by PB11
117 #define AT91C_PB11_RF1 (AT91C_PIO_PB11) // SSC Receive Frame Sync 1
118 #define AT91C_PB11_TIOB5 (AT91C_PIO_PB11) // Timer Counter 5 Multipurpose Timer I/O Pin B
119 #define AT91C_PIO_PB12 (1u << 12) // Pin Controlled by PB12
120 #define AT91C_PB12_TF2 (AT91C_PIO_PB12) // SSC Transmit Frame Sync 2
121 #define AT91C_PB12_ETX2 (AT91C_PIO_PB12) // Ethernet MAC Transmit Data 2
122 #define AT91C_PIO_PB13 (1u << 13) // Pin Controlled by PB13
123 #define AT91C_PB13_TK2 (AT91C_PIO_PB13) // SSC Transmit Clock 2
124 #define AT91C_PB13_ETX3 (AT91C_PIO_PB13) // Ethernet MAC Transmit Data 3
125 #define AT91C_PIO_PB14 (1u << 14) // Pin Controlled by PB14
126 #define AT91C_PB14_TD2 (AT91C_PIO_PB14) // SSC Transmit Data 2
127 #define AT91C_PB14_ETXER (AT91C_PIO_PB14) // Ethernet MAC Transmikt Coding Error
128 #define AT91C_PIO_PB15 (1u << 15) // Pin Controlled by PB15
129 #define AT91C_PB15_RD2 (AT91C_PIO_PB15) // SSC Receive Data 2
130 #define AT91C_PB15_ERX2 (AT91C_PIO_PB15) // Ethernet MAC Receive Data 2
131 #define AT91C_PIO_PB16 (1u << 16) // Pin Controlled by PB16
132 #define AT91C_PB16_RK2 (AT91C_PIO_PB16) // SSC Receive Clock 2
133 #define AT91C_PB16_ERX3 (AT91C_PIO_PB16) // Ethernet MAC Receive Data 3
134 #define AT91C_PIO_PB17 (1u << 17) // Pin Controlled by PB17
135 #define AT91C_PB17_RF2 (AT91C_PIO_PB17) // SSC Receive Frame Sync 2
136 #define AT91C_PB17_ERXDV (AT91C_PIO_PB17) // Ethernet MAC Receive Data Valid
137 #define AT91C_PIO_PB18 (1u << 18) // Pin Controlled by PB18
138 #define AT91C_PB18_RI1 (AT91C_PIO_PB18) // USART 1 Ring Indicator
139 #define AT91C_PB18_ECOL (AT91C_PIO_PB18) // Ethernet MAC Collision Detected
140 #define AT91C_PIO_PB19 (1u << 19) // Pin Controlled by PB19
141 #define AT91C_PB19_DTR1 (AT91C_PIO_PB19) // USART 1 Data Terminal ready
142 #define AT91C_PB19_ERXCK (AT91C_PIO_PB19) // Ethernet MAC Receive Clock
143 #define AT91C_PIO_PB2 (1u << 2) // Pin Controlled by PB2
144 #define AT91C_PB2_TD0 (AT91C_PIO_PB2) // SSC Transmit data
145 #define AT91C_PB2_SCK3 (AT91C_PIO_PB2) // USART 3 Serial Clock
146 #define AT91C_PIO_PB20 (1u << 20) // Pin Controlled by PB20
147 #define AT91C_PB20_TXD1 (AT91C_PIO_PB20) // USART 1 Transmit Data
148 #define AT91C_PIO_PB21 (1u << 21) // Pin Controlled by PB21
149 #define AT91C_PB21_RXD1 (AT91C_PIO_PB21) // USART 1 Receive Data
150 #define AT91C_PIO_PB22 (1u << 22) // Pin Controlled by PB22
151 #define AT91C_PB22_SCK1 (AT91C_PIO_PB22) // USART1 Serial Clock
152 #define AT91C_PIO_PB23 (1u << 23) // Pin Controlled by PB23
153 #define AT91C_PB23_DCD1 (AT91C_PIO_PB23) // USART 1 Data Carrier Detect
154 #define AT91C_PIO_PB24 (1u << 24) // Pin Controlled by PB24
155 #define AT91C_PB24_CTS1 (AT91C_PIO_PB24) // USART 1 Clear To Send
156 #define AT91C_PIO_PB25 (1u << 25) // Pin Controlled by PB25
157 #define AT91C_PB25_DSR1 (AT91C_PIO_PB25) // USART 1 Data Set ready
158 #define AT91C_PB25_EF100 (AT91C_PIO_PB25) // Ethernet MAC Force 100 Mbits/sec
159 #define AT91C_PIO_PB26 (1u << 26) // Pin Controlled by PB26
160 #define AT91C_PB26_RTS1 (AT91C_PIO_PB26) // Usart 0 Ready To Send
161 #define AT91C_PIO_PB27 (1u << 27) // Pin Controlled by PB27
162 #define AT91C_PB27_PCK0 (AT91C_PIO_PB27) // PMC Programmable Clock Output 0
163 #define AT91C_PIO_PB28 (1u << 28) // Pin Controlled by PB28
164 #define AT91C_PB28_FIQ (AT91C_PIO_PB28) // AIC Fast Interrupt Input
165 #define AT91C_PIO_PB29 (1u << 29) // Pin Controlled by PB29
166 #define AT91C_PB29_IRQ0 (AT91C_PIO_PB29) // Interrupt input 0
167 #define AT91C_PIO_PB3 (1u << 3) // Pin Controlled by PB3
168 #define AT91C_PB3_RD0 (AT91C_PIO_PB3) // SSC Receive Data
169 #define AT91C_PB3_MCDA1 (AT91C_PIO_PB3) // Multimedia Card A Data 1
170 #define AT91C_PIO_PB4 (1u << 4) // Pin Controlled by PB4
171 #define AT91C_PB4_RK0 (AT91C_PIO_PB4) // SSC Receive Clock
172 #define AT91C_PB4_MCDA2 (AT91C_PIO_PB4) // Multimedia Card A Data 2
173 #define AT91C_PIO_PB5 (1u << 5) // Pin Controlled by PB5
174 #define AT91C_PB5_RF0 (AT91C_PIO_PB5) // SSC Receive Frame Sync 0
175 #define AT91C_PB5_MCDA3 (AT91C_PIO_PB5) // Multimedia Card A Data 3
176 #define AT91C_PIO_PB6 (1u << 6) // Pin Controlled by PB6
177 #define AT91C_PB6_TF1 (AT91C_PIO_PB6) // SSC Transmit Frame Sync 1
178 #define AT91C_PB6_TIOA3 (AT91C_PIO_PB6) // Timer Counter 4 Multipurpose Timer I/O Pin A
179 #define AT91C_PIO_PB7 (1u << 7) // Pin Controlled by PB7
180 #define AT91C_PB7_TK1 (AT91C_PIO_PB7) // SSC Transmit Clock 1
181 #define AT91C_PB7_TIOB3 (AT91C_PIO_PB7) // Timer Counter 3 Multipurpose Timer I/O Pin B
182 #define AT91C_PIO_PB8 (1u << 8) // Pin Controlled by PB8
183 #define AT91C_PB8_TD1 (AT91C_PIO_PB8) // SSC Transmit Data 1
184 #define AT91C_PB8_TIOA4 (AT91C_PIO_PB8) // Timer Counter 4 Multipurpose Timer I/O Pin A
185 #define AT91C_PIO_PB9 (1u << 9) // Pin Controlled by PB9
186 #define AT91C_PB9_RD1 (AT91C_PIO_PB9) // SSC Receive Data 1
187 #define AT91C_PB9_TIOB4 (AT91C_PIO_PB9) // Timer Counter 4 Multipurpose Timer I/O Pin B
188 #define AT91C_PIO_PC0 (1u << 0) // Pin Controlled by PC0
189 #define AT91C_PC0_BFCK (AT91C_PIO_PC0) // Burst Flash Clock
190 #define AT91C_PIO_PC1 (1u << 1) // Pin Controlled by PC1
191 #define AT91C_PC1_BFRDY_SMOE (AT91C_PIO_PC1) // Burst Flash Ready
192 #define AT91C_PIO_PC10 (1u << 10) // Pin Controlled by PC10
193 #define AT91C_PC10_NCS4_CFCS (AT91C_PIO_PC10) // Compact Flash Chip Select
194 #define AT91C_PIO_PC11 (1u << 11) // Pin Controlled by PC11
195 #define AT91C_PC11_NCS5_CFCE1 (AT91C_PIO_PC11) // Chip Select 5 / Compact Flash Chip Enable 1
196 #define AT91C_PIO_PC12 (1u << 12) // Pin Controlled by PC12
197 #define AT91C_PC12_NCS6_CFCE2 (AT91C_PIO_PC12) // Chip Select 6 / Compact Flash Chip Enable 2
198 #define AT91C_PIO_PC13 (1u << 13) // Pin Controlled by PC13
199 #define AT91C_PC13_NCS7 (AT91C_PIO_PC13) // Chip Select 7
200 #define AT91C_PIO_PC14 (1u << 14) // Pin Controlled by PC14
201 #define AT91C_PIO_PC15 (1u << 15) // Pin Controlled by PC15
202 #define AT91C_PIO_PC16 (1u << 16) // Pin Controlled by PC16
203 #define AT91C_PC16_D16 (AT91C_PIO_PC16) // Data Bus [16]
204 #define AT91C_PIO_PC17 (1u << 17) // Pin Controlled by PC17
205 #define AT91C_PC17_D17 (AT91C_PIO_PC17) // Data Bus [17]
206 #define AT91C_PIO_PC18 (1u << 18) // Pin Controlled by PC18
207 #define AT91C_PC18_D18 (AT91C_PIO_PC18) // Data Bus [18]
208 #define AT91C_PIO_PC19 (1u << 19) // Pin Controlled by PC19
209 #define AT91C_PC19_D19 (AT91C_PIO_PC19) // Data Bus [19]
210 #define AT91C_PIO_PC2 (1u << 2) // Pin Controlled by PC2
211 #define AT91C_PC2_BFAVD (AT91C_PIO_PC2)u // Burst Flash Address Valid
212 #define AT91C_PIO_PC20 (1u << 20) // Pin Controlled by PC20
213 #define AT91C_PC20_D20 (AT91C_PIO_PC20) // Data Bus [20]
214 #define AT91C_PIO_PC21 (1u << 21) // Pin Controlled by PC21
215 #define AT91C_PC21_D21 (AT91C_PIO_PC21) // Data Bus [21]
216 #define AT91C_PIO_PC22 (1u << 22) // Pin Controlled by PC22
217 #define AT91C_PC22_D22 (AT91C_PIO_PC22) // Data Bus [22]
218 #define AT91C_PIO_PC23 (1u << 23) // Pin Controlled by PC23
219 #define AT91C_PC23_D23 (AT91C_PIO_PC23) // Data Bus [23]
220 #define AT91C_PIO_PC24 (1u << 24) // Pin Controlled by PC24
221 #define AT91C_PC24_D24 (AT91C_PIO_PC24) // Data Bus [24]
222 #define AT91C_PIO_PC25 (1u << 25) // Pin Controlled by PC25
223 #define AT91C_PC25_D25 (AT91C_PIO_PC25) // Data Bus [25]
224 #define AT91C_PIO_PC26 (1u << 26) // Pin Controlled by PC26
225 #define AT91C_PC26_D26 (AT91C_PIO_PC26) // Data Bus [26]
226 #define AT91C_PIO_PC27 (1u << 27) // Pin Controlled by PC27
227 #define AT91C_PC27_D27 (AT91C_PIO_PC27) // Data Bus [27]
228 #define AT91C_PIO_PC28 (1u << 28) // Pin Controlled by PC28
229 #define AT91C_PC28_D28 (AT91C_PIO_PC28) // Data Bus [28]
230 #define AT91C_PIO_PC29 (1u << 29) // Pin Controlled by PC29
231 #define AT91C_PC29_D29 (AT91C_PIO_PC29) // Data Bus [29]
232 #define AT91C_PIO_PC3 (1u << 3) // Pin Controlled by PC3
233 #define AT91C_PC3_BFBAA_SMWE (AT91C_PIO_PC3) // Burst Flash Address Advance / SmartMedia Write Enable
234 #define AT91C_PIO_PC30 (1u << 30) // Pin Controlled by PC30
235 #define AT91C_PC30_D30 (AT91C_PIO_PC30) // Data Bus [30]
236 #define AT91C_PIO_PC31 (1u << 31) // Pin Controlled by PC31
237 #define AT91C_PC31_D31 (AT91C_PIO_PC31) // Data Bus [31]
238 #define AT91C_PIO_PC4 (1u << 4) // Pin Controlled by PC4
239 #define AT91C_PC4_BFOE (AT91C_PIO_PC4) // Burst Flash Output Enable
240 #define AT91C_PIO_PC5 (1u << 5) // Pin Controlled by PC5
241 #define AT91C_PC5_BFWE (AT91C_PIO_PC5) // Burst Flash Write Enable
242 #define AT91C_PIO_PC6 (1u << 6) // Pin Controlled by PC6
243 #define AT91C_PC6_NWAIT (AT91C_PIO_PC6) // NWAIT
244 #define AT91C_PIO_PC7 (1u << 7) // Pin Controlled by PC7
245 #define AT91C_PC7_A23 (AT91C_PIO_PC7) // Address Bus[23]
246 #define AT91C_PIO_PC8 (1u << 8) // Pin Controlled by PC8
247 #define AT91C_PC8_A24 (AT91C_PIO_PC8) // Address Bus[24]
248 #define AT91C_PIO_PC9 (1u << 9) // Pin Controlled by PC9
249 #define AT91C_PC9_A25_CFRNW (AT91C_PIO_PC9) // Address Bus[25] / Compact Flash Read Not Write
250 #define AT91C_PIO_PD0 (1u << 0) // Pin Controlled by PD0
251 #define AT91C_PD0_ETX0 (AT91C_PIO_PD0) // Ethernet MAC Transmit Data 0
252 #define AT91C_PIO_PD1 (1u << 1) // Pin Controlled by PD1
253 #define AT91C_PD1_ETX1 (AT91C_PIO_PD1) // Ethernet MAC Transmit Data 1
254 #define AT91C_PIO_PD10 (1u << 10) // Pin Controlled by PD10
255 #define AT91C_PD10_PCK3 (AT91C_PIO_PD10) // PMC Programmable Clock Output 3
256 #define AT91C_PD10_TPS1 (AT91C_PIO_PD10) // ETM ARM9 pipeline status 1
257 #define AT91C_PIO_PD11 (1u << 11) // Pin Controlled by PD11
258 #define AT91C_PD11_ (AT91C_PIO_PD11) //
259 #define AT91C_PD11_TPS2 (AT91C_PIO_PD11) // ETM ARM9 pipeline status 2
260 #define AT91C_PIO_PD12 (1u << 12) // Pin Controlled by PD12
261 #define AT91C_PD12_ (AT91C_PIO_PD12) //
262 #define AT91C_PD12_TPK0 (AT91C_PIO_PD12) // ETM Trace Packet 0
263 #define AT91C_PIO_PD13 (1u << 13) // Pin Controlled by PD13
264 #define AT91C_PD13_ (AT91C_PIO_PD13) //
265 #define AT91C_PD13_TPK1 (AT91C_PIO_PD13) // ETM Trace Packet 1
266 #define AT91C_PIO_PD14 (1u << 14) // Pin Controlled by PD14
267 #define AT91C_PD14_ (AT91C_PIO_PD14) //
268 #define AT91C_PD14_TPK2 (AT91C_PIO_PD14) // ETM Trace Packet 2
269 #define AT91C_PIO_PD15 (1u << 15) // Pin Controlled by PD15
270 #define AT91C_PD15_TD0 (AT91C_PIO_PD15) // SSC Transmit data
271 #define AT91C_PD15_TPK3 (AT91C_PIO_PD15) // ETM Trace Packet 3
272 #define AT91C_PIO_PD16 (1u << 16) // Pin Controlled by PD16
273 #define AT91C_PD16_TD1 (AT91C_PIO_PD16) // SSC Transmit Data 1
274 #define AT91C_PD16_TPK4 (AT91C_PIO_PD16) // ETM Trace Packet 4
275 #define AT91C_PIO_PD17 (1u << 17) // Pin Controlled by PD17
276 #define AT91C_PD17_TD2 (AT91C_PIO_PD17) // SSC Transmit Data 2
277 #define AT91C_PD17_TPK5 (AT91C_PIO_PD17) // ETM Trace Packet 5
278 #define AT91C_PIO_PD18 (1u << 18) // Pin Controlled by PD18
279 #define AT91C_PD18_NPCS1 (AT91C_PIO_PD18) // SPI Peripheral Chip Select 1
280 #define AT91C_PD18_TPK6 (AT91C_PIO_PD18) // ETM Trace Packet 6
281 #define AT91C_PIO_PD19 (1u << 19) // Pin Controlled by PD19
282 #define AT91C_PD19_NPCS2 (AT91C_PIO_PD19) // SPI Peripheral Chip Select 2
283 #define AT91C_PD19_TPK7 (AT91C_PIO_PD19) // ETM Trace Packet 7
284 #define AT91C_PIO_PD2 (1u << 2) // Pin Controlled by PD2
285 #define AT91C_PD2_ETX2 (AT91C_PIO_PD2) // Ethernet MAC Transmit Data 2
286 #define AT91C_PIO_PD20 (1u << 20) // Pin Controlled by PD20
287 #define AT91C_PD20_NPCS3 (AT91C_PIO_PD20) // SPI Peripheral Chip Select 3
288 #define AT91C_PD20_TPK8 (AT91C_PIO_PD20) // ETM Trace Packet 8
289 #define AT91C_PIO_PD21 (1u << 21) // Pin Controlled by PD21
290 #define AT91C_PD21_RTS0 (AT91C_PIO_PD21) // Usart 0 Ready To Send
291 #define AT91C_PD21_TPK9 (AT91C_PIO_PD21) // ETM Trace Packet 9
292 #define AT91C_PIO_PD22 (1u << 22) // Pin Controlled by PD22
293 #define AT91C_PD22_RTS1 (AT91C_PIO_PD22) // Usart 0 Ready To Send
294 #define AT91C_PD22_TPK10 (AT91C_PIO_PD22) // ETM Trace Packet 10
295 #define AT91C_PIO_PD23 (1u << 23) // Pin Controlled by PD23
296 #define AT91C_PD23_RTS2 (AT91C_PIO_PD23) // USART 2 Ready To Send
297 #define AT91C_PD23_TPK11 (AT91C_PIO_PD23) // ETM Trace Packet 11
298 #define AT91C_PIO_PD24 (1u << 24) // Pin Controlled by PD24
299 #define AT91C_PD24_RTS3 (AT91C_PIO_PD24) // USART 3 Ready To Send
300 #define AT91C_PD24_TPK12 (AT91C_PIO_PD24) // ETM Trace Packet 12
301 #define AT91C_PIO_PD25 (1u << 25) // Pin Controlled by PD25
302 #define AT91C_PD25_DTR1 (AT91C_PIO_PD25) // USART 1 Data Terminal ready
303 #define AT91C_PD25_TPK13 (AT91C_PIO_PD25) // ETM Trace Packet 13
304 #define AT91C_PIO_PD26 (1u << 26) // Pin Controlled by PD26
305 #define AT91C_PD26_TPK14 (AT91C_PIO_PD26) // ETM Trace Packet 14
306 #define AT91C_PIO_PD27 (1u << 27) // Pin Controlled by PD27
307 #define AT91C_PD27_TPK15 (AT91C_PIO_PD27) // ETM Trace Packet 15
308 #define AT91C_PIO_PD3 (1u << 3) // Pin Controlled by PD3
309 #define AT91C_PD3_ETX3 (AT91C_PIO_PD3) // Ethernet MAC Transmit Data 3
310 #define AT91C_PIO_PD4 (1u << 4) // Pin Controlled by PD4
311 #define AT91C_PD4_ETXEN (AT91C_PIO_PD4) // Ethernet MAC Transmit Enable
312 #define AT91C_PIO_PD5 (1u << 5) // Pin Controlled by PD5
313 #define AT91C_PD5_ETXER (AT91C_PIO_PD5) // Ethernet MAC Transmikt Coding Error
314 #define AT91C_PIO_PD6 (1u << 6) // Pin Controlled by PD6
315 #define AT91C_PD6_DTXD (AT91C_PIO_PD6) // DBGU Debug Transmit Data
316 #define AT91C_PIO_PD7 (1u << 7) // Pin Controlled by PD7
317 #define AT91C_PD7_PCK0 (AT91C_PIO_PD7) // PMC Programmable Clock Output 0
318 #define AT91C_PD7_TSYNC (AT91C_PIO_PD7) // ETM Synchronization signal
319 #define AT91C_PIO_PD8 (1u << 8) // Pin Controlled by PD8
320 #define AT91C_PD8_PCK1 (AT91C_PIO_PD8) // PMC Programmable Clock Output 1
321 #define AT91C_PD8_TCLK (AT91C_PIO_PD8) // ETM Trace Clock signal
322 #define AT91C_PIO_PD9 (1u << 9) // Pin Controlled by PD9
323 #define AT91C_PD9_PCK2 (AT91C_PIO_PD9) // PMC Programmable Clock 2
324 #define AT91C_PD9_TPS0 (AT91C_PIO_PD9) // ETM ARM9 pipeline status 0
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