2 * Copyright (c) 2005 M. Warner Losh
3 * Copyright (c) 2005 Olivier Houchard
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 #include <sys/cdefs.h>
30 __FBSDID("$FreeBSD$");
32 #include "opt_comconsole.h"
34 #include <sys/param.h>
35 #include <sys/systm.h>
40 #include <machine/bus.h>
42 #include <dev/uart/uart.h>
43 #include <dev/uart/uart_cpu.h>
44 #include <dev/uart/uart_bus.h>
45 #include <arm/at91/at91rm92reg.h>
46 #include <arm/at91/at91_usartreg.h>
47 #include <arm/at91/at91_pdcreg.h>
48 #include <arm/at91/at91var.h>
52 #define DEFAULT_RCLK at91_master_clock
53 #define USART_BUFFER_SIZE 128
56 * High-level UART interface.
58 struct at91_usart_rx {
60 uint8_t buffer[USART_BUFFER_SIZE];
64 struct at91_usart_softc {
65 struct uart_softc base;
66 bus_dma_tag_t dmatag; /* bus dma tag for mbufs */
70 struct at91_usart_rx ping_pong[2];
71 struct at91_usart_rx *ping;
72 struct at91_usart_rx *pong;
75 #define RD4(bas, reg) \
76 bus_space_read_4((bas)->bst, (bas)->bsh, uart_regofs(bas, reg))
77 #define WR4(bas, reg, value) \
78 bus_space_write_4((bas)->bst, (bas)->bsh, uart_regofs(bas, reg), value)
80 #define SIGCHG(c, i, s, d) \
83 i |= (i & s) ? s : s | d; \
85 i = (i & s) ? (i & ~s) | d : i; \
89 #define BAUD2DIVISOR(b) \
90 ((((DEFAULT_RCLK * 10) / ((b) * 16)) + 5) / 10)
93 * Low-level UART interface.
95 static int at91_usart_probe(struct uart_bas *bas);
96 static void at91_usart_init(struct uart_bas *bas, int, int, int, int);
97 static void at91_usart_term(struct uart_bas *bas);
98 static void at91_usart_putc(struct uart_bas *bas, int);
99 static int at91_usart_rxready(struct uart_bas *bas);
100 static int at91_usart_getc(struct uart_bas *bas, struct mtx *mtx);
102 extern SLIST_HEAD(uart_devinfo_list, uart_devinfo) uart_sysdevs;
105 at91_usart_param(struct uart_bas *bas, int baudrate, int databits,
106 int stopbits, int parity)
111 * Assume 3-write RS-232 configuration.
112 * XXX Not sure how uart will present the other modes to us, so
113 * XXX they are unimplemented. maybe ioctl?
115 mr = USART_MR_MODE_NORMAL;
116 mr |= USART_MR_USCLKS_MCK; /* Assume MCK */
119 * Or in the databits requested
122 mr &= ~USART_MR_MODE9;
125 mr |= USART_MR_CHRL_5BITS;
128 mr |= USART_MR_CHRL_6BITS;
131 mr |= USART_MR_CHRL_7BITS;
134 mr |= USART_MR_CHRL_8BITS;
137 mr |= USART_MR_CHRL_8BITS | USART_MR_MODE9;
147 case UART_PARITY_NONE:
148 mr |= USART_MR_PAR_NONE;
150 case UART_PARITY_ODD:
151 mr |= USART_MR_PAR_ODD;
153 case UART_PARITY_EVEN:
154 mr |= USART_MR_PAR_EVEN;
156 case UART_PARITY_MARK:
157 mr |= USART_MR_PAR_MARK;
159 case UART_PARITY_SPACE:
160 mr |= USART_MR_PAR_SPACE;
167 * Or in the stop bits. Note: The hardware supports 1.5 stop
168 * bits in async mode, but there's no way to specify that
169 * AFAICT. Instead, rely on the convention documented at
170 * http://www.lammertbies.nl/comm/info/RS-232_specs.html which
171 * states that 1.5 stop bits are used for 5 bit bytes and
172 * 2 stop bits only for longer bytes.
175 mr |= USART_MR_NBSTOP_1;
176 else if (databits > 5)
177 mr |= USART_MR_NBSTOP_2;
179 mr |= USART_MR_NBSTOP_1_5;
182 * We want normal plumbing mode too, none of this fancy
183 * loopback or echo mode.
185 mr |= USART_MR_CHMODE_NORMAL;
187 mr &= ~USART_MR_MSBF; /* lsb first */
188 mr &= ~USART_MR_CKLO_SCK; /* Don't drive SCK */
190 WR4(bas, USART_MR, mr);
195 WR4(bas, USART_BRGR, BAUD2DIVISOR(baudrate));
197 /* XXX Need to take possible synchronous mode into account */
201 static struct uart_ops at91_usart_ops = {
202 .probe = at91_usart_probe,
203 .init = at91_usart_init,
204 .term = at91_usart_term,
205 .putc = at91_usart_putc,
206 .rxready = at91_usart_rxready,
207 .getc = at91_usart_getc,
211 at91_usart_probe(struct uart_bas *bas)
213 /* We know that this is always here */
218 * Initialize this device for use as a console.
221 at91_usart_init(struct uart_bas *bas, int baudrate, int databits, int stopbits,
225 at91_usart_param(bas, baudrate, databits, stopbits, parity);
227 /* Reset the rx and tx buffers and turn on rx and tx */
228 WR4(bas, USART_CR, USART_CR_RSTSTA | USART_CR_RSTRX | USART_CR_RSTTX);
229 WR4(bas, USART_CR, USART_CR_RXEN | USART_CR_TXEN);
230 WR4(bas, USART_IDR, 0xffffffff);
234 * Free resources now that we're no longer the console. This appears to
235 * be never called, and I'm unsure quite what to do if I am called.
238 at91_usart_term(struct uart_bas *bas)
244 * Put a character of console output (so we do it here polling rather than
248 at91_usart_putc(struct uart_bas *bas, int c)
251 while (!(RD4(bas, USART_CSR) & USART_CSR_TXRDY))
253 WR4(bas, USART_THR, c);
257 * Check for a character available.
260 at91_usart_rxready(struct uart_bas *bas)
263 return ((RD4(bas, USART_CSR) & USART_CSR_RXRDY) != 0 ? 1 : 0);
267 * Block waiting for a character.
270 at91_usart_getc(struct uart_bas *bas, struct mtx *mtx)
274 while (!(RD4(bas, USART_CSR) & USART_CSR_RXRDY))
276 c = RD4(bas, USART_RHR);
281 static int at91_usart_bus_probe(struct uart_softc *sc);
282 static int at91_usart_bus_attach(struct uart_softc *sc);
283 static int at91_usart_bus_flush(struct uart_softc *, int);
284 static int at91_usart_bus_getsig(struct uart_softc *);
285 static int at91_usart_bus_ioctl(struct uart_softc *, int, intptr_t);
286 static int at91_usart_bus_ipend(struct uart_softc *);
287 static int at91_usart_bus_param(struct uart_softc *, int, int, int, int);
288 static int at91_usart_bus_receive(struct uart_softc *);
289 static int at91_usart_bus_setsig(struct uart_softc *, int);
290 static int at91_usart_bus_transmit(struct uart_softc *);
292 static kobj_method_t at91_usart_methods[] = {
293 KOBJMETHOD(uart_probe, at91_usart_bus_probe),
294 KOBJMETHOD(uart_attach, at91_usart_bus_attach),
295 KOBJMETHOD(uart_flush, at91_usart_bus_flush),
296 KOBJMETHOD(uart_getsig, at91_usart_bus_getsig),
297 KOBJMETHOD(uart_ioctl, at91_usart_bus_ioctl),
298 KOBJMETHOD(uart_ipend, at91_usart_bus_ipend),
299 KOBJMETHOD(uart_param, at91_usart_bus_param),
300 KOBJMETHOD(uart_receive, at91_usart_bus_receive),
301 KOBJMETHOD(uart_setsig, at91_usart_bus_setsig),
302 KOBJMETHOD(uart_transmit, at91_usart_bus_transmit),
308 at91_usart_bus_probe(struct uart_softc *sc)
311 sc->sc_txfifosz = USART_BUFFER_SIZE;
312 sc->sc_rxfifosz = USART_BUFFER_SIZE;
317 #ifndef SKYEYE_WORKAROUNDS
319 at91_getaddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
323 *(bus_addr_t *)arg = segs[0].ds_addr;
328 at91_usart_bus_attach(struct uart_softc *sc)
330 #ifndef SKYEYE_WORKAROUNDS
335 struct at91_usart_softc *atsc;
337 atsc = (struct at91_usart_softc *)sc;
340 * See if we have a TIMEOUT bit. We disable all interrupts as
341 * a side effect. Boot loaders may have enabled them. Since
342 * a TIMEOUT interrupt can't happen without other setup, the
343 * apparent race here can't actually happen.
345 WR4(&sc->sc_bas, USART_IDR, 0xffffffff);
346 WR4(&sc->sc_bas, USART_IER, USART_CSR_TIMEOUT);
347 if (RD4(&sc->sc_bas, USART_IMR) & USART_CSR_TIMEOUT)
348 atsc->flags |= HAS_TIMEOUT;
349 WR4(&sc->sc_bas, USART_IDR, 0xffffffff);
351 #ifndef SKYEYE_WORKAROUNDS
353 * Allocate DMA tags and maps
355 err = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 1, 0,
356 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
357 USART_BUFFER_SIZE, 1, USART_BUFFER_SIZE, BUS_DMA_ALLOCNOW, NULL,
358 NULL, &atsc->dmatag);
361 err = bus_dmamap_create(atsc->dmatag, 0, &atsc->tx_map);
364 if (atsc->flags & HAS_TIMEOUT) {
365 for (i = 0; i < 2; i++) {
366 err = bus_dmamap_create(atsc->dmatag, 0,
367 &atsc->ping_pong[i].map);
370 err = bus_dmamap_load(atsc->dmatag,
371 atsc->ping_pong[i].map,
372 atsc->ping_pong[i].buffer, sc->sc_rxfifosz,
373 at91_getaddr, &atsc->ping_pong[i].pa, 0);
376 bus_dmamap_sync(atsc->dmatag, atsc->ping_pong[i].map,
377 BUS_DMASYNC_PREREAD);
379 atsc->ping = &atsc->ping_pong[0];
380 atsc->pong = &atsc->ping_pong[1];
385 * Prime the pump with the RX buffer. We use two 64 byte bounce
386 * buffers here to avoid data overflow.
389 /* Turn on rx and tx */
390 cr = USART_CR_RSTSTA | USART_CR_RSTRX | USART_CR_RSTTX;
391 WR4(&sc->sc_bas, USART_CR, cr);
392 WR4(&sc->sc_bas, USART_CR, USART_CR_RXEN | USART_CR_TXEN);
395 * Setup the PDC to receive data. We use the ping-pong buffers
396 * so that we can more easily bounce between the two and so that
397 * we get an interrupt 1/2 way through the software 'fifo' we have
400 if (atsc->flags & HAS_TIMEOUT) {
401 WR4(&sc->sc_bas, PDC_RPR, atsc->ping->pa);
402 WR4(&sc->sc_bas, PDC_RCR, sc->sc_rxfifosz);
403 WR4(&sc->sc_bas, PDC_RNPR, atsc->pong->pa);
404 WR4(&sc->sc_bas, PDC_RNCR, sc->sc_rxfifosz);
405 WR4(&sc->sc_bas, PDC_PTCR, PDC_PTCR_RXTEN);
407 /* Set the receive timeout to be 1.5 character times. */
408 WR4(&sc->sc_bas, USART_RTOR, 12);
409 WR4(&sc->sc_bas, USART_CR, USART_CR_STTTO);
410 WR4(&sc->sc_bas, USART_IER, USART_CSR_TIMEOUT |
411 USART_CSR_RXBUFF | USART_CSR_ENDRX);
413 WR4(&sc->sc_bas, USART_IER, USART_CSR_RXRDY);
415 WR4(&sc->sc_bas, USART_IER, USART_CSR_RXBRK);
416 #ifndef SKYEYE_WORKAROUNDS
426 at91_usart_bus_transmit(struct uart_softc *sc)
428 #ifndef SKYEYE_WORKAROUNDS
431 struct at91_usart_softc *atsc;
433 atsc = (struct at91_usart_softc *)sc;
434 #ifndef SKYEYE_WORKAROUNDS
435 if (bus_dmamap_load(atsc->dmatag, atsc->tx_map, sc->sc_txbuf,
436 sc->sc_txdatasz, at91_getaddr, &addr, 0) != 0)
438 bus_dmamap_sync(atsc->dmatag, atsc->tx_map, BUS_DMASYNC_PREWRITE);
441 uart_lock(sc->sc_hwmtx);
443 #ifndef SKYEYE_WORKAROUNDS
445 * Setup the PDC to transfer the data and interrupt us when it
446 * is done. We've already requested the interrupt.
448 WR4(&sc->sc_bas, PDC_TPR, addr);
449 WR4(&sc->sc_bas, PDC_TCR, sc->sc_txdatasz);
450 WR4(&sc->sc_bas, PDC_PTCR, PDC_PTCR_TXTEN);
451 WR4(&sc->sc_bas, USART_IER, USART_CSR_ENDTX);
452 uart_unlock(sc->sc_hwmtx);
454 for (int i = 0; i < sc->sc_txdatasz; i++)
455 at91_usart_putc(&sc->sc_bas, sc->sc_txbuf[i]);
457 * XXX: Gross hack : Skyeye doesn't raise an interrupt once the
458 * transfer is done, so simulate it.
460 WR4(&sc->sc_bas, USART_IER, USART_CSR_TXRDY);
465 at91_usart_bus_setsig(struct uart_softc *sc, int sig)
467 uint32_t new, old, cr;
468 struct uart_bas *bas;
474 SIGCHG(sig & SER_DTR, new, SER_DTR, SER_DDTR);
476 SIGCHG(sig & SER_RTS, new, SER_RTS, SER_DRTS);
477 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new));
479 uart_lock(sc->sc_hwmtx);
482 cr |= USART_CR_DTREN;
484 cr |= USART_CR_DTRDIS;
486 cr |= USART_CR_RTSEN;
488 cr |= USART_CR_RTSDIS;
489 WR4(bas, USART_CR, cr);
490 uart_unlock(sc->sc_hwmtx);
494 at91_usart_bus_receive(struct uart_softc *sc)
500 at91_usart_bus_param(struct uart_softc *sc, int baudrate, int databits,
501 int stopbits, int parity)
504 return (at91_usart_param(&sc->sc_bas, baudrate, databits, stopbits,
509 at91_rx_put(struct uart_softc *sc, int key)
511 #if defined(KDB) && defined(ALT_BREAK_TO_DEBUGGER)
514 if (sc->sc_sysdev != NULL && sc->sc_sysdev->type == UART_DEV_CONSOLE) {
515 if ((kdb_brk = kdb_alt_break(key, &sc->sc_altbrk)) != 0) {
517 case KDB_REQ_DEBUGGER:
518 kdb_enter(KDB_WHY_BREAK,
519 "Break sequence on console");
522 kdb_panic("Panic sequence on console");
531 uart_rx_put(sc, key);
535 at91_usart_bus_ipend(struct uart_softc *sc)
537 int csr = RD4(&sc->sc_bas, USART_CSR);
538 int ipend = 0, i, len;
539 struct at91_usart_softc *atsc;
540 struct at91_usart_rx *p;
542 atsc = (struct at91_usart_softc *)sc;
543 if (csr & USART_CSR_ENDTX) {
544 bus_dmamap_sync(atsc->dmatag, atsc->tx_map,
545 BUS_DMASYNC_POSTWRITE);
546 bus_dmamap_unload(atsc->dmatag, atsc->tx_map);
548 uart_lock(sc->sc_hwmtx);
549 if (csr & USART_CSR_TXRDY) {
551 ipend |= SER_INT_TXIDLE;
552 WR4(&sc->sc_bas, USART_IDR, USART_CSR_TXRDY);
554 if (csr & USART_CSR_ENDTX) {
556 ipend |= SER_INT_TXIDLE;
557 WR4(&sc->sc_bas, USART_IDR, USART_CSR_ENDTX);
561 * Due to the contraints of the DMA engine present in the
562 * atmel chip, I can't just say I have a rx interrupt pending
563 * and do all the work elsewhere. I need to look at the CSR
564 * bits right now and do things based on them to avoid races.
566 if ((atsc->flags & HAS_TIMEOUT) && (csr & USART_CSR_RXBUFF)) {
567 // Have a buffer overflow. Copy all data from both
568 // ping and pong. Insert overflow character. Reset
569 // ping and pong and re-enable the PDC to receive
571 bus_dmamap_sync(atsc->dmatag, atsc->ping->map,
572 BUS_DMASYNC_POSTREAD);
573 bus_dmamap_sync(atsc->dmatag, atsc->pong->map,
574 BUS_DMASYNC_POSTREAD);
575 for (i = 0; i < sc->sc_rxfifosz; i++)
576 at91_rx_put(sc, atsc->ping->buffer[i]);
577 for (i = 0; i < sc->sc_rxfifosz; i++)
578 at91_rx_put(sc, atsc->pong->buffer[i]);
579 uart_rx_put(sc, UART_STAT_OVERRUN);
580 csr &= ~(USART_CSR_ENDRX | USART_CSR_TIMEOUT);
581 WR4(&sc->sc_bas, PDC_RPR, atsc->ping->pa);
582 WR4(&sc->sc_bas, PDC_RCR, sc->sc_rxfifosz);
583 WR4(&sc->sc_bas, PDC_RNPR, atsc->pong->pa);
584 WR4(&sc->sc_bas, PDC_RNCR, sc->sc_rxfifosz);
585 WR4(&sc->sc_bas, PDC_PTCR, PDC_PTCR_RXTEN);
586 ipend |= SER_INT_RXREADY;
588 if ((atsc->flags & HAS_TIMEOUT) && (csr & USART_CSR_ENDRX)) {
589 // Shuffle data from 'ping' of ping pong buffer, but
590 // leave current 'pong' in place, as it has become the
591 // new 'ping'. We need to copy data and setup the old
592 // 'ping' as the new 'pong' when we're done.
593 bus_dmamap_sync(atsc->dmatag, atsc->ping->map,
594 BUS_DMASYNC_POSTREAD);
595 for (i = 0; i < sc->sc_rxfifosz; i++)
596 at91_rx_put(sc, atsc->ping->buffer[i]);
598 atsc->ping = atsc->pong;
600 WR4(&sc->sc_bas, PDC_RNPR, atsc->pong->pa);
601 WR4(&sc->sc_bas, PDC_RNCR, sc->sc_rxfifosz);
602 ipend |= SER_INT_RXREADY;
604 if ((atsc->flags & HAS_TIMEOUT) && (csr & USART_CSR_TIMEOUT)) {
605 // We have one partial buffer. We need to stop the
606 // PDC, get the number of characters left and from
607 // that compute number of valid characters. We then
608 // need to reset ping and pong and reenable the PDC.
609 // Not sure if there's a race here at fast baud rates
610 // we need to worry about.
611 WR4(&sc->sc_bas, PDC_PTCR, PDC_PTCR_RXTDIS);
612 bus_dmamap_sync(atsc->dmatag, atsc->ping->map,
613 BUS_DMASYNC_POSTREAD);
614 len = sc->sc_rxfifosz - RD4(&sc->sc_bas, PDC_RCR);
615 for (i = 0; i < len; i++)
616 at91_rx_put(sc, atsc->ping->buffer[i]);
617 WR4(&sc->sc_bas, PDC_RPR, atsc->ping->pa);
618 WR4(&sc->sc_bas, PDC_RCR, sc->sc_rxfifosz);
619 WR4(&sc->sc_bas, USART_CR, USART_CR_STTTO);
620 WR4(&sc->sc_bas, PDC_PTCR, PDC_PTCR_RXTEN);
621 ipend |= SER_INT_RXREADY;
623 if (!(atsc->flags & HAS_TIMEOUT) && (csr & USART_CSR_RXRDY)) {
624 // We have another charater in a device that doesn't support
625 // timeouts, so we do it one character at a time.
626 at91_rx_put(sc, RD4(&sc->sc_bas, USART_RHR) & 0xff);
627 ipend |= SER_INT_RXREADY;
630 if (csr & USART_CSR_RXBRK) {
631 unsigned int cr = USART_CR_RSTSTA;
633 ipend |= SER_INT_BREAK;
634 WR4(&sc->sc_bas, USART_CR, cr);
636 uart_unlock(sc->sc_hwmtx);
640 at91_usart_bus_flush(struct uart_softc *sc, int what)
646 at91_usart_bus_getsig(struct uart_softc *sc)
651 uart_lock(sc->sc_hwmtx);
652 csr = RD4(&sc->sc_bas, USART_CSR);
654 if (csr & USART_CSR_CTS)
656 if (csr & USART_CSR_DCD)
658 if (csr & USART_CSR_DSR)
660 if (csr & USART_CSR_RI)
662 new = sig & ~SER_MASK_DELTA;
664 uart_unlock(sc->sc_hwmtx);
669 at91_usart_bus_ioctl(struct uart_softc *sc, int request, intptr_t data)
672 case UART_IOCTL_BREAK:
673 case UART_IOCTL_IFLOW:
674 case UART_IOCTL_OFLOW:
676 case UART_IOCTL_BAUD:
677 WR4(&sc->sc_bas, USART_BRGR, BAUD2DIVISOR(*(int *)data));
683 struct uart_class at91_usart_class = {
686 sizeof(struct at91_usart_softc),
687 .uc_ops = &at91_usart_ops,