2 * Copyright (C) 2008 MARVELL INTERNATIONAL LTD.
5 * Developed by Semihalf.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. Neither the name of MARVELL nor the names of contributors
16 * may be used to endorse or promote products derived from this software
17 * without specific prior written permission.
19 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 #include <sys/cdefs.h>
33 __FBSDID("$FreeBSD$");
35 #include <sys/param.h>
36 #include <sys/systm.h>
38 #include <sys/kernel.h>
43 #include <machine/bus.h>
44 #include <machine/intr.h>
45 #include <machine/pte.h>
46 #include <machine/pmap.h>
47 #include <machine/vmparam.h>
49 #include <arm/mv/mvreg.h>
50 #include <arm/mv/mvvar.h>
51 #include <arm/mv/mvwin.h>
54 * Virtual address space layout:
55 * -----------------------------
56 * 0x0000_0000 - 0xbfff_ffff : user process
58 * 0xc040_0000 - virtual_avail : kernel reserved (text, data, page tables
59 * : structures, ARM stacks etc.)
60 * virtual_avail - 0xefff_ffff : KVA (virtual_avail is typically < 0xc0a0_0000)
61 * 0xf000_0000 - 0xf0ff_ffff : no-cache allocation area (16MB)
62 * 0xf100_0000 - 0xf10f_ffff : SoC integrated devices registers range (1MB)
63 * 0xf110_0000 - 0xf11f_ffff : PCI-Express I/O space (1MB)
64 * 0xf120_0000 - 0xf12f_ffff : PCI I/O space (1MB)
65 * 0xf130_0000 - 0xf52f_ffff : PCI-Express memory space (64MB)
66 * 0xf530_0000 - 0xf92f_ffff : PCI memory space (64MB)
67 * 0xf930_0000 - 0xfffe_ffff : unused (~108MB)
68 * 0xffff_0000 - 0xffff_0fff : 'high' vectors page (4KB)
69 * 0xffff_1000 - 0xffff_1fff : ARM_TP_ADDRESS/RAS page (4KB)
70 * 0xffff_2000 - 0xffff_ffff : unused (~55KB)
73 int platform_pci_get_irq(u_int bus, u_int slot, u_int func, u_int pin);
75 /* Static device mappings. */
76 const struct pmap_devmap pmap_devmap[] = {
78 * Map the on-board devices VA == PA so that we can access them
79 * with the MMU on or off.
81 { /* SoC integrated peripherals registers range */
85 VM_PROT_READ | VM_PROT_WRITE,
92 VM_PROT_READ | VM_PROT_WRITE,
97 MV_PCIE_MEM_PHYS_BASE,
99 VM_PROT_READ | VM_PROT_WRITE,
106 VM_PROT_READ | VM_PROT_WRITE,
111 MV_PCI_MEM_PHYS_BASE,
113 VM_PROT_READ | VM_PROT_WRITE,
118 MV_DEV_CS0_PHYS_BASE,
120 VM_PROT_READ | VM_PROT_WRITE,
127 * The pci_irq_map table consists of 3 columns:
128 * - PCI slot number (less than zero means ANY).
129 * - PCI IRQ pin (less than zero means ANY).
130 * - PCI IRQ (less than zero marks end of table).
132 * IRQ number from the first matching entry is used to configure PCI device
135 /* PCI IRQ Map for DB-88F5281 */
136 const struct obio_pci_irq_map pci_irq_map[] = {
137 { 7, -1, GPIO2IRQ(12) },
138 { 8, -1, GPIO2IRQ(13) },
139 { 9, -1, GPIO2IRQ(13) },
144 /* PCI IRQ Map for DB-88F5182 */
145 const struct obio_pci_irq_map pci_irq_map[] = {
146 { 7, -1, GPIO2IRQ(0) },
147 { 8, -1, GPIO2IRQ(1) },
148 { 9, -1, GPIO2IRQ(1) },
154 * mv_gpio_config row structure:
155 * <GPIO number>, <GPIO flags>, <GPIO mode>
157 * - GPIO pin number (less than zero marks end of table)
164 * 1 - Output, set to HIGH.
165 * 0 - Output, set to LOW.
169 /* GPIO Configuration for DB-88F5281 */
170 const struct gpio_config mv_gpio_config[] = {
171 { 12, MV_GPIO_POLAR_LOW | MV_GPIO_LEVEL, -1 },
172 { 13, MV_GPIO_POLAR_LOW | MV_GPIO_LEVEL, -1 },
177 /* GPIO Configuration for DB-88F5182 */
178 const struct gpio_config mv_gpio_config[] = {
179 { 0, MV_GPIO_POLAR_LOW | MV_GPIO_LEVEL, -1 },
180 { 1, MV_GPIO_POLAR_LOW | MV_GPIO_LEVEL, -1 },
186 platform_mpp_init(void)
190 * MPP configuration for DB-88F5281
192 * MPP[2]: PCI_REQn[3]
193 * MPP[3]: PCI_GNTn[3]
194 * MPP[4]: PCI_REQn[4]
195 * MPP[5]: PCI_GNTn[4]
200 * MPP[14]: NAND Flash REn[2]
201 * MPP[15]: NAND Flash WEn[2]
209 * <UNKNOWN> entries are not documented, not on the schematics etc.
211 bus_space_write_4(obio_tag, MV_MPP_BASE, MPP_CONTROL0, 0x33222203);
212 bus_space_write_4(obio_tag, MV_MPP_BASE, MPP_CONTROL1, 0x44000033);
213 bus_space_write_4(obio_tag, MV_MPP_BASE, MPP_CONTROL2, 0x00000000);
217 * MPP configuration for DB-88F5182
219 * MPP[2]: PCI_REQn[3]
220 * MPP[3]: PCI_GNTn[3]
221 * MPP[4]: PCI_REQn[4]
222 * MPP[5]: PCI_GNTn[4]
225 * MPP[12]: SATA0_PRESENT
226 * MPP[13]: SATA1_PRESENT
227 * MPP[14]: NAND_FLASH_REn[2]
228 * MPP[15]: NAND_FLASH_WEn[2]
236 bus_space_write_4(obio_tag, MV_MPP_BASE, MPP_CONTROL0, 0x55222203);
237 bus_space_write_4(obio_tag, MV_MPP_BASE, MPP_CONTROL1, 0x44550000);
238 bus_space_write_4(obio_tag, MV_MPP_BASE, MPP_CONTROL2, 0x00000000);
243 platform_identify(void *dummy)
249 * XXX Board identification e.g. read out from FPGA or similar should
253 SYSINIT(platform_identify, SI_SUB_CPU, SI_ORDER_SECOND, platform_identify, NULL);