2 * Copyright (c) 2006 Olivier Houchard
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
16 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
17 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR
18 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
19 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
20 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
21 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
22 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
23 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
24 * POSSIBILITY OF SUCH DAMAGE.
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
30 #include <sys/param.h>
31 #include <sys/systm.h>
33 #include <sys/kernel.h>
34 #include <sys/module.h>
36 #define _ARM32_BUS_DMA_PRIVATE
37 #include <machine/bus.h>
38 #include <machine/intr.h>
40 #include <arm/xscale/i8134x/i81342reg.h>
41 #include <arm/xscale/i8134x/i81342var.h>
43 #define WDTCR_ENABLE1 0x1e1e1e1e
44 #define WDTCR_ENABLE2 0xe1e1e1e1
46 static volatile int intr_enabled0;
47 static volatile int intr_enabled1;
48 static volatile int intr_enabled2;
49 static volatile int intr_enabled3;
51 struct bus_space i81342_bs_tag;
53 /* Read the interrupt pending register */
56 uint32_t intpnd0_read(void)
60 __asm __volatile("mrc p6, 0, %0, c0, c3, 0"
66 uint32_t intpnd1_read(void)
70 __asm __volatile("mrc p6, 0, %0, c1, c3, 0"
76 uint32_t intpnd2_read(void)
80 __asm __volatile("mrc p6, 0, %0, c2, c3, 0"
86 uint32_t intpnd3_read(void)
90 __asm __volatile("mrc p6, 0, %0, c3, c3, 0"
95 /* Read the interrupt control register */
96 /* 0 masked, 1 unmasked */
98 uint32_t intctl0_read(void)
102 __asm __volatile("mrc p6, 0, %0, c0, c4, 0"
108 uint32_t intctl1_read(void)
112 __asm __volatile("mrc p6, 0, %0, c1, c4, 0"
118 uint32_t intctl2_read(void)
122 __asm __volatile("mrc p6, 0, %0, c2, c4, 0"
128 uint32_t intctl3_read(void)
132 __asm __volatile("mrc p6, 0, %0, c3, c4, 0"
137 /* Write the interrupt control register */
140 void intctl0_write(uint32_t val)
143 __asm __volatile("mcr p6, 0, %0, c0, c4, 0"
148 void intctl1_write(uint32_t val)
151 __asm __volatile("mcr p6, 0, %0, c1, c4, 0"
156 void intctl2_write(uint32_t val)
159 __asm __volatile("mcr p6, 0, %0, c2, c4, 0"
164 void intctl3_write(uint32_t val)
167 __asm __volatile("mcr p6, 0, %0, c3, c4, 0"
171 /* Read the interrupt steering register */
174 uint32_t intstr0_read(void)
178 __asm __volatile("mrc p6, 0, %0, c0, c5, 0"
184 uint32_t intstr1_read(void)
188 __asm __volatile("mrc p6, 0, %0, c1, c5, 0"
194 uint32_t intstr2_read(void)
198 __asm __volatile("mrc p6, 0, %0, c2, c5, 0"
204 uint32_t intstr3_read(void)
208 __asm __volatile("mrc p6, 0, %0, c3, c5, 0"
213 /* Write the interrupt steering register */
216 void intstr0_write(uint32_t val)
219 __asm __volatile("mcr p6, 0, %0, c0, c5, 0"
224 void intstr1_write(uint32_t val)
227 __asm __volatile("mcr p6, 0, %0, c1, c5, 0"
232 void intstr2_write(uint32_t val)
235 __asm __volatile("mcr p6, 0, %0, c2, c5, 0"
240 void intstr3_write(uint32_t val)
243 __asm __volatile("mcr p6, 0, %0, c3, c5, 0"
251 disable_interrupts(I32_bit);
252 /* XXX: Use the watchdog to reset for now */
253 __asm __volatile("mcr p6, 0, %0, c8, c9, 0\n"
254 "mcr p6, 0, %1, c7, c9, 0\n"
255 "mcr p6, 0, %2, c7, c9, 0\n"
256 : : "r" (1), "r" (WDTCR_ENABLE1), "r" (WDTCR_ENABLE2));
261 arm_mask_irq(uintptr_t nb)
265 intr_enabled0 &= ~(1 << nb);
266 intctl0_write(intr_enabled0);
267 } else if (nb < 64) {
268 intr_enabled1 &= ~(1 << (nb - 32));
269 intctl1_write(intr_enabled1);
270 } else if (nb < 96) {
271 intr_enabled2 &= ~(1 << (nb - 64));
272 intctl2_write(intr_enabled2);
274 intr_enabled3 &= ~(1 << (nb - 96));
275 intctl3_write(intr_enabled3);
280 arm_unmask_irq(uintptr_t nb)
283 intr_enabled0 |= (1 << nb);
284 intctl0_write(intr_enabled0);
285 } else if (nb < 64) {
286 intr_enabled1 |= (1 << (nb - 32));
287 intctl1_write(intr_enabled1);
288 } else if (nb < 96) {
289 intr_enabled2 |= (1 << (nb - 64));
290 intctl2_write(intr_enabled2);
292 intr_enabled3 |= (1 << (nb - 96));
293 intctl3_write(intr_enabled3);
298 arm_get_next_irq(int last __unused)
301 val = intpnd0_read() & intr_enabled0;
303 return (ffs(val) - 1);
304 val = intpnd1_read() & intr_enabled1;
306 return (32 + ffs(val) - 1);
307 val = intpnd2_read() & intr_enabled2;
309 return (64 + ffs(val) - 1);
310 val = intpnd3_read() & intr_enabled3;
312 return (96 + ffs(val) - 1);
317 bus_dma_get_range_nb(void)
322 struct arm32_dma_range *
323 bus_dma_get_range(void)
329 i81342_probe(device_t dev)
333 freq = *(volatile unsigned int *)(IOP34X_VADDR + IOP34X_PFR);
335 switch (freq & IOP34X_FREQ_MASK) {
336 case IOP34X_FREQ_600:
337 device_set_desc(dev, "Intel 81342 600MHz");
339 case IOP34X_FREQ_667:
340 device_set_desc(dev, "Intel 81342 667MHz");
342 case IOP34X_FREQ_800:
343 device_set_desc(dev, "Intel 81342 800MHz");
345 case IOP34X_FREQ_833:
346 device_set_desc(dev, "Intel 81342 833MHz");
348 case IOP34X_FREQ_1000:
349 device_set_desc(dev, "Intel 81342 1000MHz");
351 case IOP34X_FREQ_1200:
352 device_set_desc(dev, "Intel 81342 1200MHz");
355 device_set_desc(dev, "Intel 81342 unknown frequency");
362 i81342_identify(driver_t *driver, device_t parent)
365 BUS_ADD_CHILD(parent, 0, "iq", 0);
369 i81342_attach(device_t dev)
371 struct i81342_softc *sc = device_get_softc(dev);
374 i81342_bs_init(&i81342_bs_tag, sc);
375 sc->sc_st = &i81342_bs_tag;
376 sc->sc_sh = IOP34X_VADDR;
377 esstrsr = bus_space_read_4(sc->sc_st, sc->sc_sh, IOP34X_ESSTSR0);
378 sc->sc_atux_sh = IOP34X_ATUX_ADDR(esstrsr) - IOP34X_HWADDR +
380 sc->sc_atue_sh = IOP34X_ATUE_ADDR(esstrsr) - IOP34X_HWADDR +
382 /* Disable all interrupts. */
387 /* Defaults to IRQ */
392 sc->sc_irq_rman.rm_type = RMAN_ARRAY;
393 sc->sc_irq_rman.rm_descr = "i81342 IRQs";
394 if (rman_init(&sc->sc_irq_rman) != 0 ||
395 rman_manage_region(&sc->sc_irq_rman, 0, 127) != 0)
396 panic("i81342_attach: failed to set up IRQ rman");
398 device_add_child(dev, "obio", 0);
399 device_add_child(dev, "itimer", 0);
400 device_add_child(dev, "iopwdog", 0);
401 device_add_child(dev, "pcib", 0);
402 device_add_child(dev, "pcib", 1);
403 device_add_child(dev, "iqseg", 0);
404 bus_generic_probe(dev);
405 bus_generic_attach(dev);
409 static struct resource *
410 i81342_alloc_resource(device_t dev, device_t child, int type, int *rid,
411 u_long start, u_long end, u_long count, u_int flags)
413 struct i81342_softc *sc = device_get_softc(dev);
416 if (type == SYS_RES_IRQ) {
417 rv = rman_reserve_resource(&sc->sc_irq_rman,
418 start, end, count, flags, child);
420 rman_set_rid(rv, *rid);
428 i81342_setup_intr(device_t dev, device_t child, struct resource *ires,
429 int flags, driver_filter_t *filt, driver_intr_t *intr, void *arg,
434 BUS_SETUP_INTR(device_get_parent(dev), child, ires, flags, filt, intr,
436 arm_unmask_irq(rman_get_start(ires));
441 i81342_teardown_intr(device_t dev, device_t child, struct resource *res,
444 return (BUS_TEARDOWN_INTR(device_get_parent(dev), child, res, cookie));
447 static device_method_t i81342_methods[] = {
448 DEVMETHOD(device_probe, i81342_probe),
449 DEVMETHOD(device_attach, i81342_attach),
450 DEVMETHOD(device_identify, i81342_identify),
451 DEVMETHOD(bus_alloc_resource, i81342_alloc_resource),
452 DEVMETHOD(bus_setup_intr, i81342_setup_intr),
453 DEVMETHOD(bus_teardown_intr, i81342_teardown_intr),
457 static driver_t i81342_driver = {
460 sizeof(struct i81342_softc),
462 static devclass_t i81342_devclass;
464 DRIVER_MODULE(iq, nexus, i81342_driver, i81342_devclass, 0, 0);