2 * Copyright (c) 2006-2008 Sam Leffler. All rights reserved.
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
14 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
15 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
16 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
17 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
18 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
19 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
20 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
21 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
22 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 #include <sys/cdefs.h>
26 __FBSDID("$FreeBSD$");
29 * Intel XScale NPE Ethernet driver.
31 * This driver handles the two ports present on the IXP425.
32 * Packet processing is done by the Network Processing Engines
33 * (NPE's) that work together with a MAC and PHY. The MAC
34 * is also mapped to the XScale cpu; the PHY is accessed via
35 * the MAC. NPE-XScale communication happens through h/w
36 * queues managed by the Q Manager block.
38 * The code here replaces the ethAcc, ethMii, and ethDB classes
39 * in the Intel Access Library (IAL) and the OS-specific driver.
41 * XXX add vlan support
43 #ifdef HAVE_KERNEL_OPTION_HEADERS
44 #include "opt_device_polling.h"
47 #include <sys/param.h>
48 #include <sys/systm.h>
50 #include <sys/kernel.h>
52 #include <sys/malloc.h>
53 #include <sys/module.h>
55 #include <sys/socket.h>
56 #include <sys/sockio.h>
57 #include <sys/sysctl.h>
58 #include <sys/endian.h>
59 #include <machine/bus.h>
61 #include <net/ethernet.h>
63 #include <net/if_arp.h>
64 #include <net/if_dl.h>
65 #include <net/if_media.h>
66 #include <net/if_mib.h>
67 #include <net/if_types.h>
70 #include <netinet/in.h>
71 #include <netinet/in_systm.h>
72 #include <netinet/in_var.h>
73 #include <netinet/ip.h>
77 #include <net/bpfdesc.h>
79 #include <arm/xscale/ixp425/ixp425reg.h>
80 #include <arm/xscale/ixp425/ixp425var.h>
81 #include <arm/xscale/ixp425/ixp425_qmgr.h>
82 #include <arm/xscale/ixp425/ixp425_npevar.h>
84 #include <dev/mii/mii.h>
85 #include <dev/mii/miivar.h>
86 #include <arm/xscale/ixp425/if_npereg.h>
88 #include <machine/armreg.h>
90 #include "miibus_if.h"
93 * XXX: For the main bus dma tag. Can go away if the new method to get the
94 * dma tag from the parent got MFC'd into RELENG_6.
96 extern struct ixp425_softc *ixp425_softc;
99 struct npebuf *ix_next; /* chain to next buffer */
100 void *ix_m; /* backpointer to mbuf */
101 bus_dmamap_t ix_map; /* bus dma map for associated data */
102 struct npehwbuf *ix_hw; /* associated h/w block */
103 uint32_t ix_neaddr; /* phys address of ix_hw */
108 int nbuf; /* # npebuf's allocated */
109 bus_dma_tag_t mtag; /* bus dma tag for mbuf data */
110 struct npehwbuf *hwbuf; /* NPE h/w buffers */
111 bus_dma_tag_t buf_tag; /* tag+map for NPE buffers */
112 bus_dmamap_t buf_map;
113 bus_addr_t buf_phys; /* phys addr of buffers */
114 struct npebuf *buf; /* s/w buffers (1-1 w/ h/w) */
118 /* XXX mii requires this be first; do not move! */
119 struct ifnet *sc_ifp; /* ifnet pointer */
120 struct mtx sc_mtx; /* basically a perimeter lock */
122 bus_space_tag_t sc_iot;
123 bus_space_handle_t sc_ioh; /* MAC register window */
124 device_t sc_mii; /* child miibus */
125 bus_space_handle_t sc_miih; /* MII register window */
127 struct ixpnpe_softc *sc_npe; /* NPE support */
128 int sc_debug; /* DPRINTF* control */
130 struct callout tick_ch; /* Tick callout */
131 int npe_watchdog_timer;
133 struct npebuf *tx_free; /* list of free tx buffers */
135 bus_addr_t buf_phys; /* XXX for returning a value */
136 int rx_qid; /* rx qid */
137 int rx_freeqid; /* rx free buffers qid */
138 int tx_qid; /* tx qid */
139 int tx_doneqid; /* tx completed qid */
140 int sc_phy; /* PHY id */
141 struct ifmib_iso_8802_3 mibdata;
142 bus_dma_tag_t sc_stats_tag; /* bus dma tag for stats block */
143 struct npestats *sc_stats;
144 bus_dmamap_t sc_stats_map;
145 bus_addr_t sc_stats_phys; /* phys addr of sc_stats */
146 struct npestats sc_totals; /* accumulated sc_stats */
150 * Static configuration for IXP425. The tx and
151 * rx free Q id's are fixed by the NPE microcode. The
152 * rx Q id's are programmed to be separate to simplify
153 * multi-port processing. It may be better to handle
154 * all traffic through one Q (as done by the Intel drivers).
156 * Note that the PHY's are accessible only from MAC B on the
157 * IXP425 and from MAC C on other devices. This and other
158 * platform-specific assumptions are handled with hints.
160 static const struct {
163 int phy; /* phy id */
168 } npeconfig[NPE_MAX] = {
170 .macbase = IXP435_MAC_A_HWBASE,
171 .miibase = IXP425_MAC_C_HWBASE,
179 .macbase = IXP425_MAC_B_HWBASE,
180 .miibase = IXP425_MAC_B_HWBASE,
188 .macbase = IXP425_MAC_C_HWBASE,
189 .miibase = IXP425_MAC_B_HWBASE,
197 static struct npe_softc *npes[NPE_MAX]; /* NB: indexed by npeid */
199 static __inline uint32_t
200 RD4(struct npe_softc *sc, bus_size_t off)
202 return bus_space_read_4(sc->sc_iot, sc->sc_ioh, off);
206 WR4(struct npe_softc *sc, bus_size_t off, uint32_t val)
208 bus_space_write_4(sc->sc_iot, sc->sc_ioh, off, val);
211 #define NPE_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx)
212 #define NPE_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx)
213 #define NPE_LOCK_INIT(_sc) \
214 mtx_init(&_sc->sc_mtx, device_get_nameunit(_sc->sc_dev), \
215 MTX_NETWORK_LOCK, MTX_DEF)
216 #define NPE_LOCK_DESTROY(_sc) mtx_destroy(&_sc->sc_mtx);
217 #define NPE_ASSERT_LOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_OWNED);
218 #define NPE_ASSERT_UNLOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_NOTOWNED);
220 static devclass_t npe_devclass;
222 static int override_npeid(device_t, const char *resname, int *val);
223 static int npe_activate(device_t dev);
224 static void npe_deactivate(device_t dev);
225 static int npe_ifmedia_update(struct ifnet *ifp);
226 static void npe_ifmedia_status(struct ifnet *ifp, struct ifmediareq *ifmr);
227 static void npe_setmac(struct npe_softc *sc, u_char *eaddr);
228 static void npe_getmac(struct npe_softc *sc, u_char *eaddr);
229 static void npe_txdone(int qid, void *arg);
230 static int npe_rxbuf_init(struct npe_softc *, struct npebuf *,
232 static int npe_rxdone(int qid, void *arg);
233 static void npeinit(void *);
234 static void npestart_locked(struct ifnet *);
235 static void npestart(struct ifnet *);
236 static void npestop(struct npe_softc *);
237 static void npewatchdog(struct npe_softc *);
238 static int npeioctl(struct ifnet * ifp, u_long, caddr_t);
240 static int npe_setrxqosentry(struct npe_softc *, int classix,
241 int trafclass, int qid);
242 static int npe_setportaddress(struct npe_softc *, const uint8_t mac[]);
243 static int npe_setfirewallmode(struct npe_softc *, int onoff);
244 static int npe_updatestats(struct npe_softc *);
246 static int npe_getstats(struct npe_softc *);
247 static uint32_t npe_getimageid(struct npe_softc *);
248 static int npe_setloopback(struct npe_softc *, int ena);
251 /* NB: all tx done processing goes through one queue */
252 static int tx_doneqid = -1;
254 SYSCTL_NODE(_hw, OID_AUTO, npe, CTLFLAG_RD, 0, "IXP4XX NPE driver parameters");
256 static int npe_debug = 0;
257 SYSCTL_INT(_hw_npe, OID_AUTO, debug, CTLFLAG_RW, &npe_debug,
258 0, "IXP4XX NPE network interface debug msgs");
259 TUNABLE_INT("hw.npe.debug", &npe_debug);
260 #define DPRINTF(sc, fmt, ...) do { \
261 if (sc->sc_debug) device_printf(sc->sc_dev, fmt, __VA_ARGS__); \
263 #define DPRINTFn(n, sc, fmt, ...) do { \
264 if (sc->sc_debug >= n) device_printf(sc->sc_dev, fmt, __VA_ARGS__);\
266 static int npe_tickinterval = 3; /* npe_tick frequency (secs) */
267 SYSCTL_INT(_hw_npe, OID_AUTO, tickinterval, CTLFLAG_RD, &npe_tickinterval,
268 0, "periodic work interval (secs)");
269 TUNABLE_INT("hw.npe.tickinterval", &npe_tickinterval);
271 static int npe_rxbuf = 64; /* # rx buffers to allocate */
272 SYSCTL_INT(_hw_npe, OID_AUTO, rxbuf, CTLFLAG_RD, &npe_rxbuf,
273 0, "rx buffers allocated");
274 TUNABLE_INT("hw.npe.rxbuf", &npe_rxbuf);
275 static int npe_txbuf = 128; /* # tx buffers to allocate */
276 SYSCTL_INT(_hw_npe, OID_AUTO, txbuf, CTLFLAG_RD, &npe_txbuf,
277 0, "tx buffers allocated");
278 TUNABLE_INT("hw.npe.txbuf", &npe_txbuf);
283 static const int npeidmap[2][3] = {
284 /* on 425 A is for HSS, B & C are for Ethernet */
285 { NPE_B, NPE_C, -1 }, /* IXP425 */
286 /* 435 only has A & C, order C then A */
287 { NPE_C, NPE_A, -1 }, /* IXP435 */
289 /* XXX check feature register instead */
290 return (unit < 3 ? npeidmap[
291 (cpu_id() & CPU_ID_CPU_MASK) == CPU_ID_IXP435][unit] : -1);
295 npe_probe(device_t dev)
297 static const char *desc[NPE_MAX] = {
298 [NPE_A] = "IXP NPE-A",
299 [NPE_B] = "IXP NPE-B",
300 [NPE_C] = "IXP NPE-C"
302 int unit = device_get_unit(dev);
306 (ixp4xx_read_feature_bits() &
307 (unit == 0 ? EXP_FCTRL_ETH0 : EXP_FCTRL_ETH1)) == 0)
311 if (!override_npeid(dev, "npeid", &npeid))
312 npeid = unit2npeid(unit);
314 device_printf(dev, "unit %d not supported\n", unit);
317 device_set_desc(dev, desc[npeid]);
322 npe_attach(device_t dev)
324 struct npe_softc *sc = device_get_softc(dev);
325 struct ixp425_softc *sa = device_get_softc(device_get_parent(dev));
326 struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(dev);
327 struct sysctl_oid *tree = device_get_sysctl_tree(dev);
333 sc->sc_iot = sa->sc_iot;
335 callout_init_mtx(&sc->tick_ch, &sc->sc_mtx, 0);
336 sc->sc_debug = npe_debug;
337 sc->sc_tickinterval = npe_tickinterval;
339 ifp = if_alloc(IFT_ETHER);
341 device_printf(dev, "cannot allocate ifnet\n");
342 error = EIO; /* XXX */
345 /* NB: must be setup prior to invoking mii code */
348 error = npe_activate(dev);
350 device_printf(dev, "cannot activate npe\n");
354 npe_getmac(sc, eaddr);
357 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
358 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
359 ifp->if_start = npestart;
360 ifp->if_ioctl = npeioctl;
361 ifp->if_init = npeinit;
362 IFQ_SET_MAXLEN(&ifp->if_snd, sc->txdma.nbuf - 1);
363 ifp->if_snd.ifq_drv_maxlen = IFQ_MAXLEN;
364 IFQ_SET_READY(&ifp->if_snd);
365 ifp->if_linkmib = &sc->mibdata;
366 ifp->if_linkmiblen = sizeof(sc->mibdata);
367 sc->mibdata.dot3Compliance = DOT3COMPLIANCE_STATS;
368 /* device supports oversided vlan frames */
369 ifp->if_capabilities |= IFCAP_VLAN_MTU;
370 ifp->if_capenable = ifp->if_capabilities;
371 #ifdef DEVICE_POLLING
372 ifp->if_capabilities |= IFCAP_POLLING;
375 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, "debug",
376 CTLFLAG_RW, &sc->sc_debug, 0, "control debugging printfs");
377 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, "tickinterval",
378 CTLFLAG_RW, &sc->sc_tickinterval, 0, "periodic work frequency");
379 SYSCTL_ADD_STRUCT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, "stats",
380 CTLFLAG_RD, &sc->sc_totals, npestats, "onboard stats");
382 ether_ifattach(ifp, eaddr);
387 NPE_LOCK_DESTROY(sc);
393 npe_detach(device_t dev)
395 struct npe_softc *sc = device_get_softc(dev);
396 struct ifnet *ifp = sc->sc_ifp;
398 #ifdef DEVICE_POLLING
399 if (ifp->if_capenable & IFCAP_POLLING)
400 ether_poll_deregister(ifp);
407 NPE_LOCK_DESTROY(sc);
413 * Compute and install the multicast filter.
416 npe_setmcast(struct npe_softc *sc)
418 struct ifnet *ifp = sc->sc_ifp;
419 uint8_t mask[ETHER_ADDR_LEN], addr[ETHER_ADDR_LEN];
422 if (ifp->if_flags & IFF_PROMISC) {
423 memset(mask, 0, ETHER_ADDR_LEN);
424 memset(addr, 0, ETHER_ADDR_LEN);
425 } else if (ifp->if_flags & IFF_ALLMULTI) {
426 static const uint8_t allmulti[ETHER_ADDR_LEN] =
427 { 0x01, 0x00, 0x00, 0x00, 0x00, 0x00 };
428 memcpy(mask, allmulti, ETHER_ADDR_LEN);
429 memcpy(addr, allmulti, ETHER_ADDR_LEN);
431 uint8_t clr[ETHER_ADDR_LEN], set[ETHER_ADDR_LEN];
432 struct ifmultiaddr *ifma;
435 memset(clr, 0, ETHER_ADDR_LEN);
436 memset(set, 0xff, ETHER_ADDR_LEN);
439 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
440 if (ifma->ifma_addr->sa_family != AF_LINK)
442 mac = LLADDR((struct sockaddr_dl *) ifma->ifma_addr);
443 for (i = 0; i < ETHER_ADDR_LEN; i++) {
448 if_maddr_runlock(ifp);
450 for (i = 0; i < ETHER_ADDR_LEN; i++) {
451 mask[i] = set[i] | ~clr[i];
457 * Write the mask and address registers.
459 for (i = 0; i < ETHER_ADDR_LEN; i++) {
460 WR4(sc, NPE_MAC_ADDR_MASK(i), mask[i]);
461 WR4(sc, NPE_MAC_ADDR(i), addr[i]);
466 npe_getaddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
468 struct npe_softc *sc;
472 sc = (struct npe_softc *)arg;
473 sc->buf_phys = segs[0].ds_addr;
477 npe_dma_setup(struct npe_softc *sc, struct npedma *dma,
478 const char *name, int nbuf, int maxseg)
482 memset(dma, 0, sizeof(*dma));
487 /* DMA tag for mapped mbufs */
488 error = bus_dma_tag_create(ixp425_softc->sc_dmat, 1, 0,
489 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
490 MCLBYTES, maxseg, MCLBYTES, 0,
491 busdma_lock_mutex, &sc->sc_mtx, &dma->mtag);
493 device_printf(sc->sc_dev, "unable to create %s mbuf dma tag, "
494 "error %u\n", dma->name, error);
498 /* DMA tag and map for the NPE buffers */
499 error = bus_dma_tag_create(ixp425_softc->sc_dmat, sizeof(uint32_t), 0,
500 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
501 nbuf * sizeof(struct npehwbuf), 1,
502 nbuf * sizeof(struct npehwbuf), 0,
503 busdma_lock_mutex, &sc->sc_mtx, &dma->buf_tag);
505 device_printf(sc->sc_dev,
506 "unable to create %s npebuf dma tag, error %u\n",
510 /* XXX COHERENT for now */
511 if (bus_dmamem_alloc(dma->buf_tag, (void **)&dma->hwbuf,
512 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT,
513 &dma->buf_map) != 0) {
514 device_printf(sc->sc_dev,
515 "unable to allocate memory for %s h/w buffers, error %u\n",
520 dma->buf = malloc(nbuf * sizeof(struct npebuf), M_TEMP, M_NOWAIT | M_ZERO);
521 if (dma->buf == NULL) {
522 device_printf(sc->sc_dev,
523 "unable to allocate memory for %s s/w buffers\n",
527 if (bus_dmamap_load(dma->buf_tag, dma->buf_map,
528 dma->hwbuf, nbuf*sizeof(struct npehwbuf), npe_getaddr, sc, 0) != 0) {
529 device_printf(sc->sc_dev,
530 "unable to map memory for %s h/w buffers, error %u\n",
534 dma->buf_phys = sc->buf_phys;
535 for (i = 0; i < dma->nbuf; i++) {
536 struct npebuf *npe = &dma->buf[i];
537 struct npehwbuf *hw = &dma->hwbuf[i];
539 /* calculate offset to shared area */
540 npe->ix_neaddr = dma->buf_phys +
541 ((uintptr_t)hw - (uintptr_t)dma->hwbuf);
542 KASSERT((npe->ix_neaddr & 0x1f) == 0,
543 ("ixpbuf misaligned, PA 0x%x", npe->ix_neaddr));
544 error = bus_dmamap_create(dma->mtag, BUS_DMA_NOWAIT,
547 device_printf(sc->sc_dev,
548 "unable to create dmamap for %s buffer %u, "
549 "error %u\n", dma->name, i, error);
554 bus_dmamap_sync(dma->buf_tag, dma->buf_map, BUS_DMASYNC_PREWRITE);
559 npe_dma_destroy(struct npe_softc *sc, struct npedma *dma)
563 if (dma->hwbuf != NULL) {
564 for (i = 0; i < dma->nbuf; i++) {
565 struct npebuf *npe = &dma->buf[i];
566 bus_dmamap_destroy(dma->mtag, npe->ix_map);
568 bus_dmamap_unload(dma->buf_tag, dma->buf_map);
569 bus_dmamem_free(dma->buf_tag, dma->hwbuf, dma->buf_map);
571 if (dma->buf != NULL)
572 free(dma->buf, M_TEMP);
574 bus_dma_tag_destroy(dma->buf_tag);
576 bus_dma_tag_destroy(dma->mtag);
577 memset(dma, 0, sizeof(*dma));
581 override_addr(device_t dev, const char *resname, int *base)
583 int unit = device_get_unit(dev);
586 /* XXX warn for wrong hint type */
587 if (resource_string_value("npe", unit, resname, &resval) != 0)
591 *base = IXP435_MAC_A_HWBASE;
594 *base = IXP425_MAC_B_HWBASE;
597 *base = IXP425_MAC_C_HWBASE;
600 device_printf(dev, "Warning, bad value %s for "
601 "npe.%d.%s ignored\n", resval, unit, resname);
605 device_printf(dev, "using npe.%d.%s=%s override\n",
606 unit, resname, resval);
611 override_npeid(device_t dev, const char *resname, int *npeid)
613 int unit = device_get_unit(dev);
616 /* XXX warn for wrong hint type */
617 if (resource_string_value("npe", unit, resname, &resval) != 0)
620 case 'A': *npeid = NPE_A; break;
621 case 'B': *npeid = NPE_B; break;
622 case 'C': *npeid = NPE_C; break;
624 device_printf(dev, "Warning, bad value %s for "
625 "npe.%d.%s ignored\n", resval, unit, resname);
629 device_printf(dev, "using npe.%d.%s=%s override\n",
630 unit, resname, resval);
635 override_unit(device_t dev, const char *resname, int *val, int min, int max)
637 int unit = device_get_unit(dev);
640 if (resource_int_value("npe", unit, resname, &resval) != 0)
642 if (!(min <= resval && resval <= max)) {
643 device_printf(dev, "Warning, bad value %d for npe.%d.%s "
644 "ignored (value must be [%d-%d])\n", resval, unit,
649 device_printf(dev, "using npe.%d.%s=%d override\n",
650 unit, resname, resval);
656 npe_mac_reset(struct npe_softc *sc)
661 WR4(sc, NPE_MAC_CORE_CNTRL, NPE_CORE_RESET);
662 DELAY(NPE_MAC_RESET_DELAY);
663 /* configure MAC to generate MDC clock */
664 WR4(sc, NPE_MAC_CORE_CNTRL, NPE_CORE_MDC_EN);
668 npe_activate(device_t dev)
670 struct npe_softc *sc = device_get_softc(dev);
671 int error, i, macbase, miibase;
674 * Setup NEP ID, MAC, and MII bindings. We allow override
675 * via hints to handle unexpected board configs.
677 if (!override_npeid(dev, "npeid", &sc->sc_npeid))
678 sc->sc_npeid = unit2npeid(device_get_unit(dev));
679 sc->sc_npe = ixpnpe_attach(dev, sc->sc_npeid);
680 if (sc->sc_npe == NULL) {
681 device_printf(dev, "cannot attach ixpnpe\n");
682 return EIO; /* XXX */
686 if (!override_addr(dev, "mac", &macbase))
687 macbase = npeconfig[sc->sc_npeid].macbase;
688 device_printf(sc->sc_dev, "MAC at 0x%x\n", macbase);
689 if (bus_space_map(sc->sc_iot, macbase, IXP425_REG_SIZE, 0, &sc->sc_ioh)) {
690 device_printf(dev, "cannot map mac registers 0x%x:0x%x\n",
691 macbase, IXP425_REG_SIZE);
696 if (!override_unit(dev, "phy", &sc->sc_phy, 0, MII_NPHY-1))
697 sc->sc_phy = npeconfig[sc->sc_npeid].phy;
698 if (!override_addr(dev, "mii", &miibase))
699 miibase = npeconfig[sc->sc_npeid].miibase;
700 device_printf(sc->sc_dev, "MII at 0x%x\n", miibase);
701 if (miibase != macbase) {
703 * PHY is mapped through a different MAC, setup an
704 * additional mapping for frobbing the PHY registers.
706 if (bus_space_map(sc->sc_iot, miibase, IXP425_REG_SIZE, 0, &sc->sc_miih)) {
708 "cannot map MII registers 0x%x:0x%x\n",
709 miibase, IXP425_REG_SIZE);
713 sc->sc_miih = sc->sc_ioh;
716 * Load NPE firmware and start it running.
718 error = ixpnpe_init(sc->sc_npe);
720 device_printf(dev, "cannot init NPE (error %d)\n", error);
725 if (mii_phy_probe(dev, &sc->sc_mii, npe_ifmedia_update, npe_ifmedia_status)) {
726 device_printf(dev, "cannot find PHY %d.\n", sc->sc_phy);
730 error = npe_dma_setup(sc, &sc->txdma, "tx", npe_txbuf, NPE_MAXSEG);
733 error = npe_dma_setup(sc, &sc->rxdma, "rx", npe_rxbuf, 1);
737 /* setup statistics block */
738 error = bus_dma_tag_create(ixp425_softc->sc_dmat, sizeof(uint32_t), 0,
739 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
740 sizeof(struct npestats), 1, sizeof(struct npestats), 0,
741 busdma_lock_mutex, &sc->sc_mtx, &sc->sc_stats_tag);
743 device_printf(sc->sc_dev, "unable to create stats tag, "
744 "error %u\n", error);
747 if (bus_dmamem_alloc(sc->sc_stats_tag, (void **)&sc->sc_stats,
748 BUS_DMA_NOWAIT, &sc->sc_stats_map) != 0) {
749 device_printf(sc->sc_dev,
750 "unable to allocate memory for stats block, error %u\n",
754 if (bus_dmamap_load(sc->sc_stats_tag, sc->sc_stats_map,
755 sc->sc_stats, sizeof(struct npestats), npe_getaddr, sc, 0) != 0) {
756 device_printf(sc->sc_dev,
757 "unable to load memory for stats block, error %u\n",
761 sc->sc_stats_phys = sc->buf_phys;
764 * Setup h/w rx/tx queues. There are four q's:
765 * rx inbound q of rx'd frames
766 * rx_free pool of ixpbuf's for receiving frames
767 * tx outbound q of frames to send
768 * tx_done q of tx frames that have been processed
770 * The NPE handles the actual tx/rx process and the q manager
771 * handles the queues. The driver just writes entries to the
772 * q manager mailbox's and gets callbacks when there are rx'd
773 * frames to process or tx'd frames to reap. These callbacks
774 * are controlled by the q configurations; e.g. we get a
775 * callback when tx_done has 2 or more frames to process and
776 * when the rx q has at least one frame. These setings can
777 * changed at the time the q is configured.
779 sc->rx_qid = npeconfig[sc->sc_npeid].rx_qid;
780 ixpqmgr_qconfig(sc->rx_qid, npe_rxbuf, 0, 1,
781 IX_QMGR_Q_SOURCE_ID_NOT_E, (qconfig_hand_t *)npe_rxdone, sc);
782 sc->rx_freeqid = npeconfig[sc->sc_npeid].rx_freeqid;
783 ixpqmgr_qconfig(sc->rx_freeqid, npe_rxbuf, 0, npe_rxbuf/2, 0, NULL, sc);
785 * Setup the NPE to direct all traffic to rx_qid.
786 * When QoS is enabled in the firmware there are
787 * 8 traffic classes; otherwise just 4.
789 for (i = 0; i < 8; i++)
790 npe_setrxqosentry(sc, i, 0, sc->rx_qid);
792 /* disable firewall mode just in case (should be off) */
793 npe_setfirewallmode(sc, 0);
795 sc->tx_qid = npeconfig[sc->sc_npeid].tx_qid;
796 sc->tx_doneqid = npeconfig[sc->sc_npeid].tx_doneqid;
797 ixpqmgr_qconfig(sc->tx_qid, npe_txbuf, 0, npe_txbuf, 0, NULL, sc);
798 if (tx_doneqid == -1) {
799 ixpqmgr_qconfig(sc->tx_doneqid, npe_txbuf, 0, 2,
800 IX_QMGR_Q_SOURCE_ID_NOT_E, npe_txdone, sc);
801 tx_doneqid = sc->tx_doneqid;
804 KASSERT(npes[sc->sc_npeid] == NULL,
805 ("npe %u already setup", sc->sc_npeid));
806 npes[sc->sc_npeid] = sc;
812 npe_deactivate(device_t dev)
814 struct npe_softc *sc = device_get_softc(dev);
816 npes[sc->sc_npeid] = NULL;
818 /* XXX disable q's */
819 if (sc->sc_npe != NULL) {
820 ixpnpe_stop(sc->sc_npe);
821 ixpnpe_detach(sc->sc_npe);
823 if (sc->sc_stats != NULL) {
824 bus_dmamap_unload(sc->sc_stats_tag, sc->sc_stats_map);
825 bus_dmamem_free(sc->sc_stats_tag, sc->sc_stats,
828 if (sc->sc_stats_tag != NULL)
829 bus_dma_tag_destroy(sc->sc_stats_tag);
830 npe_dma_destroy(sc, &sc->txdma);
831 npe_dma_destroy(sc, &sc->rxdma);
832 bus_generic_detach(sc->sc_dev);
833 if (sc->sc_mii != NULL)
834 device_delete_child(sc->sc_dev, sc->sc_mii);
838 * Change media according to request.
841 npe_ifmedia_update(struct ifnet *ifp)
843 struct npe_softc *sc = ifp->if_softc;
844 struct mii_data *mii;
846 mii = device_get_softc(sc->sc_mii);
849 /* XXX push state ourself? */
855 * Notify the world which media we're using.
858 npe_ifmedia_status(struct ifnet *ifp, struct ifmediareq *ifmr)
860 struct npe_softc *sc = ifp->if_softc;
861 struct mii_data *mii;
863 mii = device_get_softc(sc->sc_mii);
866 ifmr->ifm_active = mii->mii_media_active;
867 ifmr->ifm_status = mii->mii_media_status;
872 npe_addstats(struct npe_softc *sc)
874 #define NPEADD(x) sc->sc_totals.x += be32toh(ns->x)
875 #define MIBADD(x) do { sc->mibdata.x += be32toh(ns->x); NPEADD(x); } while (0)
876 struct ifnet *ifp = sc->sc_ifp;
877 struct npestats *ns = sc->sc_stats;
879 MIBADD(dot3StatsAlignmentErrors);
880 MIBADD(dot3StatsFCSErrors);
881 MIBADD(dot3StatsInternalMacReceiveErrors);
882 NPEADD(RxOverrunDiscards);
883 NPEADD(RxLearnedEntryDiscards);
884 NPEADD(RxLargeFramesDiscards);
885 NPEADD(RxSTPBlockedDiscards);
886 NPEADD(RxVLANTypeFilterDiscards);
887 NPEADD(RxVLANIdFilterDiscards);
888 NPEADD(RxInvalidSourceDiscards);
889 NPEADD(RxBlackListDiscards);
890 NPEADD(RxWhiteListDiscards);
891 NPEADD(RxUnderflowEntryDiscards);
892 MIBADD(dot3StatsSingleCollisionFrames);
893 MIBADD(dot3StatsMultipleCollisionFrames);
894 MIBADD(dot3StatsDeferredTransmissions);
895 MIBADD(dot3StatsLateCollisions);
896 MIBADD(dot3StatsExcessiveCollisions);
897 MIBADD(dot3StatsInternalMacTransmitErrors);
898 MIBADD(dot3StatsCarrierSenseErrors);
899 NPEADD(TxLargeFrameDiscards);
900 NPEADD(TxVLANIdFilterDiscards);
902 sc->mibdata.dot3StatsFrameTooLongs +=
903 be32toh(ns->RxLargeFramesDiscards)
904 + be32toh(ns->TxLargeFrameDiscards);
905 sc->mibdata.dot3StatsMissedFrames +=
906 be32toh(ns->RxOverrunDiscards)
907 + be32toh(ns->RxUnderflowEntryDiscards);
910 be32toh(ns->dot3StatsInternalMacTransmitErrors)
911 + be32toh(ns->dot3StatsCarrierSenseErrors)
912 + be32toh(ns->TxVLANIdFilterDiscards)
914 ifp->if_ierrors += be32toh(ns->dot3StatsFCSErrors)
915 + be32toh(ns->dot3StatsInternalMacReceiveErrors)
916 + be32toh(ns->RxOverrunDiscards)
917 + be32toh(ns->RxUnderflowEntryDiscards)
919 ifp->if_collisions +=
920 be32toh(ns->dot3StatsSingleCollisionFrames)
921 + be32toh(ns->dot3StatsMultipleCollisionFrames)
930 #define ACK (NPE_RESETSTATS << NPE_MAC_MSGID_SHL)
931 struct npe_softc *sc = xsc;
932 struct mii_data *mii = device_get_softc(sc->sc_mii);
935 NPE_ASSERT_LOCKED(sc);
938 * NB: to avoid sleeping with the softc lock held we
939 * split the NPE msg processing into two parts. The
940 * request for statistics is sent w/o waiting for a
941 * reply and then on the next tick we retrieve the
942 * results. This works because npe_tick is the only
943 * code that talks via the mailbox's (except at setup).
944 * This likely can be handled better.
946 if (ixpnpe_recvmsg_async(sc->sc_npe, msg) == 0 && msg[0] == ACK) {
947 bus_dmamap_sync(sc->sc_stats_tag, sc->sc_stats_map,
948 BUS_DMASYNC_POSTREAD);
956 /* schedule next poll */
957 callout_reset(&sc->tick_ch, sc->sc_tickinterval * hz, npe_tick, sc);
962 npe_setmac(struct npe_softc *sc, u_char *eaddr)
964 WR4(sc, NPE_MAC_UNI_ADDR_1, eaddr[0]);
965 WR4(sc, NPE_MAC_UNI_ADDR_2, eaddr[1]);
966 WR4(sc, NPE_MAC_UNI_ADDR_3, eaddr[2]);
967 WR4(sc, NPE_MAC_UNI_ADDR_4, eaddr[3]);
968 WR4(sc, NPE_MAC_UNI_ADDR_5, eaddr[4]);
969 WR4(sc, NPE_MAC_UNI_ADDR_6, eaddr[5]);
973 npe_getmac(struct npe_softc *sc, u_char *eaddr)
975 /* NB: the unicast address appears to be loaded from EEPROM on reset */
976 eaddr[0] = RD4(sc, NPE_MAC_UNI_ADDR_1) & 0xff;
977 eaddr[1] = RD4(sc, NPE_MAC_UNI_ADDR_2) & 0xff;
978 eaddr[2] = RD4(sc, NPE_MAC_UNI_ADDR_3) & 0xff;
979 eaddr[3] = RD4(sc, NPE_MAC_UNI_ADDR_4) & 0xff;
980 eaddr[4] = RD4(sc, NPE_MAC_UNI_ADDR_5) & 0xff;
981 eaddr[5] = RD4(sc, NPE_MAC_UNI_ADDR_6) & 0xff;
986 struct npebuf **tail;
991 npe_txdone_finish(struct npe_softc *sc, const struct txdone *td)
993 struct ifnet *ifp = sc->sc_ifp;
996 *td->tail = sc->tx_free;
997 sc->tx_free = td->head;
999 * We're no longer busy, so clear the busy flag and call the
1000 * start routine to xmit more packets.
1002 ifp->if_opackets += td->count;
1003 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1004 sc->npe_watchdog_timer = 0;
1005 npestart_locked(ifp);
1010 * Q manager callback on tx done queue. Reap mbufs
1011 * and return tx buffers to the free list. Finally
1012 * restart output. Note the microcode has only one
1013 * txdone q wired into it so we must use the NPE ID
1014 * returned with each npehwbuf to decide where to
1018 npe_txdone(int qid, void *arg)
1020 #define P2V(a, dma) \
1021 &(dma)->buf[((a) - (dma)->buf_phys) / sizeof(struct npehwbuf)]
1022 struct npe_softc *sc0 = arg;
1023 struct npe_softc *sc;
1025 struct txdone *td, q[NPE_MAX];
1028 q[NPE_A].tail = &q[NPE_A].head; q[NPE_A].count = 0;
1029 q[NPE_B].tail = &q[NPE_B].head; q[NPE_B].count = 0;
1030 q[NPE_C].tail = &q[NPE_C].head; q[NPE_C].count = 0;
1031 /* XXX max # at a time? */
1032 while (ixpqmgr_qread(qid, &entry) == 0) {
1033 DPRINTF(sc0, "%s: entry 0x%x NPE %u port %u\n",
1034 __func__, entry, NPE_QM_Q_NPE(entry), NPE_QM_Q_PORT(entry));
1036 sc = npes[NPE_QM_Q_NPE(entry)];
1037 npe = P2V(NPE_QM_Q_ADDR(entry), &sc->txdma);
1041 td = &q[NPE_QM_Q_NPE(entry)];
1043 td->tail = &npe->ix_next;
1048 npe_txdone_finish(npes[NPE_A], &q[NPE_A]);
1050 npe_txdone_finish(npes[NPE_B], &q[NPE_B]);
1052 npe_txdone_finish(npes[NPE_C], &q[NPE_C]);
1057 npe_rxbuf_init(struct npe_softc *sc, struct npebuf *npe, struct mbuf *m)
1059 bus_dma_segment_t segs[1];
1060 struct npedma *dma = &sc->rxdma;
1061 struct npehwbuf *hw;
1065 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
1069 KASSERT(m->m_ext.ext_size >= 1536 + ETHER_ALIGN,
1070 ("ext_size %d", m->m_ext.ext_size));
1071 m->m_pkthdr.len = m->m_len = 1536;
1072 /* backload payload and align ip hdr */
1073 m->m_data = m->m_ext.ext_buf + (m->m_ext.ext_size - (1536+ETHER_ALIGN));
1074 error = bus_dmamap_load_mbuf_sg(dma->mtag, npe->ix_map, m,
1081 hw->ix_ne[0].data = htobe32(segs[0].ds_addr);
1082 /* NB: NPE requires length be a multiple of 64 */
1083 /* NB: buffer length is shifted in word */
1084 hw->ix_ne[0].len = htobe32(segs[0].ds_len << 16);
1085 hw->ix_ne[0].next = 0;
1087 /* Flush the memory in the mbuf */
1088 bus_dmamap_sync(dma->mtag, npe->ix_map, BUS_DMASYNC_PREREAD);
1093 * RX q processing for a specific NPE. Claim entries
1094 * from the hardware queue and pass the frames up the
1095 * stack. Pass the rx buffers to the free list.
1098 npe_rxdone(int qid, void *arg)
1100 #define P2V(a, dma) \
1101 &(dma)->buf[((a) - (dma)->buf_phys) / sizeof(struct npehwbuf)]
1102 struct npe_softc *sc = arg;
1103 struct npedma *dma = &sc->rxdma;
1107 while (ixpqmgr_qread(qid, &entry) == 0) {
1108 struct npebuf *npe = P2V(NPE_QM_Q_ADDR(entry), dma);
1111 DPRINTF(sc, "%s: entry 0x%x neaddr 0x%x ne_len 0x%x\n",
1112 __func__, entry, npe->ix_neaddr, npe->ix_hw->ix_ne[0].len);
1114 * Allocate a new mbuf to replenish the rx buffer.
1115 * If doing so fails we drop the rx'd frame so we
1116 * can reuse the previous mbuf. When we're able to
1117 * allocate a new mbuf dispatch the mbuf w/ rx'd
1118 * data up the stack and replace it with the newly
1121 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
1123 struct mbuf *mrx = npe->ix_m;
1124 struct npehwbuf *hw = npe->ix_hw;
1125 struct ifnet *ifp = sc->sc_ifp;
1127 /* Flush mbuf memory for rx'd data */
1128 bus_dmamap_sync(dma->mtag, npe->ix_map,
1129 BUS_DMASYNC_POSTREAD);
1131 /* XXX flush hw buffer; works now 'cuz coherent */
1132 /* set m_len etc. per rx frame size */
1133 mrx->m_len = be32toh(hw->ix_ne[0].len) & 0xffff;
1134 mrx->m_pkthdr.len = mrx->m_len;
1135 mrx->m_pkthdr.rcvif = ifp;
1138 ifp->if_input(ifp, mrx);
1141 /* discard frame and re-use mbuf */
1144 if (npe_rxbuf_init(sc, npe, m) == 0) {
1145 /* return npe buf to rx free list */
1146 ixpqmgr_qwrite(sc->rx_freeqid, npe->ix_neaddr);
1148 /* XXX should not happen */
1155 #ifdef DEVICE_POLLING
1157 npe_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
1159 struct npe_softc *sc = ifp->if_softc;
1162 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
1163 rx_npkts = npe_rxdone(sc->rx_qid, sc);
1164 npe_txdone(sc->tx_doneqid, sc); /* XXX polls both NPE's */
1168 #endif /* DEVICE_POLLING */
1171 npe_startxmit(struct npe_softc *sc)
1173 struct npedma *dma = &sc->txdma;
1176 NPE_ASSERT_LOCKED(sc);
1178 for (i = 0; i < dma->nbuf; i++) {
1179 struct npebuf *npe = &dma->buf[i];
1180 if (npe->ix_m != NULL) {
1181 /* NB: should not happen */
1182 device_printf(sc->sc_dev,
1183 "%s: free mbuf at entry %u\n", __func__, i);
1187 npe->ix_next = sc->tx_free;
1193 npe_startrecv(struct npe_softc *sc)
1195 struct npedma *dma = &sc->rxdma;
1199 NPE_ASSERT_LOCKED(sc);
1200 for (i = 0; i < dma->nbuf; i++) {
1202 npe_rxbuf_init(sc, npe, npe->ix_m);
1203 /* set npe buf on rx free list */
1204 ixpqmgr_qwrite(sc->rx_freeqid, npe->ix_neaddr);
1209 * Reset and initialize the chip
1212 npeinit_locked(void *xsc)
1214 struct npe_softc *sc = xsc;
1215 struct ifnet *ifp = sc->sc_ifp;
1217 NPE_ASSERT_LOCKED(sc);
1218 if (ifp->if_drv_flags & IFF_DRV_RUNNING) return;/*XXX*/
1225 /* disable transmitter and reciver in the MAC */
1226 WR4(sc, NPE_MAC_RX_CNTRL1,
1227 RD4(sc, NPE_MAC_RX_CNTRL1) &~ NPE_RX_CNTRL1_RX_EN);
1228 WR4(sc, NPE_MAC_TX_CNTRL1,
1229 RD4(sc, NPE_MAC_TX_CNTRL1) &~ NPE_TX_CNTRL1_TX_EN);
1232 * Set the MAC core registers.
1234 WR4(sc, NPE_MAC_INT_CLK_THRESH, 0x1); /* clock ratio: for ipx4xx */
1235 WR4(sc, NPE_MAC_TX_CNTRL2, 0xf); /* max retries */
1236 WR4(sc, NPE_MAC_RANDOM_SEED, 0x8); /* LFSR back-off seed */
1237 /* thresholds determined by NPE firmware FS */
1238 WR4(sc, NPE_MAC_THRESH_P_EMPTY, 0x12);
1239 WR4(sc, NPE_MAC_THRESH_P_FULL, 0x30);
1240 WR4(sc, NPE_MAC_BUF_SIZE_TX, 0x8); /* tx fifo threshold (bytes) */
1241 WR4(sc, NPE_MAC_TX_DEFER, 0x15); /* for single deferral */
1242 WR4(sc, NPE_MAC_RX_DEFER, 0x16); /* deferral on inter-frame gap*/
1243 WR4(sc, NPE_MAC_TX_TWO_DEFER_1, 0x8); /* for 2-part deferral */
1244 WR4(sc, NPE_MAC_TX_TWO_DEFER_2, 0x7); /* for 2-part deferral */
1245 WR4(sc, NPE_MAC_SLOT_TIME, 0x80); /* assumes MII mode */
1247 WR4(sc, NPE_MAC_TX_CNTRL1,
1248 NPE_TX_CNTRL1_RETRY /* retry failed xmits */
1249 | NPE_TX_CNTRL1_FCS_EN /* append FCS */
1250 | NPE_TX_CNTRL1_2DEFER /* 2-part deferal */
1251 | NPE_TX_CNTRL1_PAD_EN); /* pad runt frames */
1252 /* XXX pad strip? */
1253 /* ena pause frame handling */
1254 WR4(sc, NPE_MAC_RX_CNTRL1, NPE_RX_CNTRL1_PAUSE_EN);
1255 WR4(sc, NPE_MAC_RX_CNTRL2, 0);
1257 npe_setmac(sc, IF_LLADDR(ifp));
1258 npe_setportaddress(sc, IF_LLADDR(ifp));
1264 ifp->if_drv_flags |= IFF_DRV_RUNNING;
1265 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1266 sc->npe_watchdog_timer = 0; /* just in case */
1268 /* enable transmitter and reciver in the MAC */
1269 WR4(sc, NPE_MAC_RX_CNTRL1,
1270 RD4(sc, NPE_MAC_RX_CNTRL1) | NPE_RX_CNTRL1_RX_EN);
1271 WR4(sc, NPE_MAC_TX_CNTRL1,
1272 RD4(sc, NPE_MAC_TX_CNTRL1) | NPE_TX_CNTRL1_TX_EN);
1274 callout_reset(&sc->tick_ch, sc->sc_tickinterval * hz, npe_tick, sc);
1280 struct npe_softc *sc = xsc;
1287 * Dequeue packets and place on the h/w transmit queue.
1290 npestart_locked(struct ifnet *ifp)
1292 struct npe_softc *sc = ifp->if_softc;
1294 struct npehwbuf *hw;
1296 struct npedma *dma = &sc->txdma;
1297 bus_dma_segment_t segs[NPE_MAXSEG];
1298 int nseg, len, error, i;
1301 NPE_ASSERT_LOCKED(sc);
1302 /* XXX can this happen? */
1303 if (ifp->if_drv_flags & IFF_DRV_OACTIVE)
1306 while (sc->tx_free != NULL) {
1307 IFQ_DRV_DEQUEUE(&ifp->if_snd, m);
1310 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1314 error = bus_dmamap_load_mbuf_sg(dma->mtag, npe->ix_map,
1316 if (error == EFBIG) {
1317 n = m_collapse(m, M_DONTWAIT, NPE_MAXSEG);
1319 if_printf(ifp, "%s: too many fragments %u\n",
1325 error = bus_dmamap_load_mbuf_sg(dma->mtag, npe->ix_map,
1328 if (error != 0 || nseg == 0) {
1329 if_printf(ifp, "%s: error %u nseg %u\n",
1330 __func__, error, nseg);
1334 sc->tx_free = npe->ix_next;
1336 bus_dmamap_sync(dma->mtag, npe->ix_map, BUS_DMASYNC_PREWRITE);
1339 * Tap off here if there is a bpf listener.
1345 len = m->m_pkthdr.len;
1346 next = npe->ix_neaddr + sizeof(hw->ix_ne[0]);
1347 for (i = 0; i < nseg; i++) {
1348 hw->ix_ne[i].data = htobe32(segs[i].ds_addr);
1349 hw->ix_ne[i].len = htobe32((segs[i].ds_len<<16) | len);
1350 hw->ix_ne[i].next = htobe32(next);
1352 len = 0; /* zero for segments > 1 */
1353 next += sizeof(hw->ix_ne[0]);
1355 hw->ix_ne[i-1].next = 0; /* zero last in chain */
1356 /* XXX flush descriptor instead of using uncached memory */
1358 DPRINTF(sc, "%s: qwrite(%u, 0x%x) ne_data %x ne_len 0x%x\n",
1359 __func__, sc->tx_qid, npe->ix_neaddr,
1360 hw->ix_ne[0].data, hw->ix_ne[0].len);
1361 /* stick it on the tx q */
1362 /* XXX add vlan priority */
1363 ixpqmgr_qwrite(sc->tx_qid, npe->ix_neaddr);
1365 sc->npe_watchdog_timer = 5;
1367 if (sc->tx_free == NULL)
1368 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1372 npestart(struct ifnet *ifp)
1374 struct npe_softc *sc = ifp->if_softc;
1376 npestart_locked(ifp);
1381 npe_stopxmit(struct npe_softc *sc)
1383 struct npedma *dma = &sc->txdma;
1386 NPE_ASSERT_LOCKED(sc);
1389 for (i = 0; i < dma->nbuf; i++) {
1390 struct npebuf *npe = &dma->buf[i];
1392 if (npe->ix_m != NULL) {
1393 bus_dmamap_unload(dma->mtag, npe->ix_map);
1401 npe_stoprecv(struct npe_softc *sc)
1403 struct npedma *dma = &sc->rxdma;
1406 NPE_ASSERT_LOCKED(sc);
1409 for (i = 0; i < dma->nbuf; i++) {
1410 struct npebuf *npe = &dma->buf[i];
1412 if (npe->ix_m != NULL) {
1413 bus_dmamap_unload(dma->mtag, npe->ix_map);
1421 * Turn off interrupts, and stop the nic.
1424 npestop(struct npe_softc *sc)
1426 struct ifnet *ifp = sc->sc_ifp;
1428 /* disable transmitter and reciver in the MAC */
1429 WR4(sc, NPE_MAC_RX_CNTRL1,
1430 RD4(sc, NPE_MAC_RX_CNTRL1) &~ NPE_RX_CNTRL1_RX_EN);
1431 WR4(sc, NPE_MAC_TX_CNTRL1,
1432 RD4(sc, NPE_MAC_TX_CNTRL1) &~ NPE_TX_CNTRL1_TX_EN);
1434 sc->npe_watchdog_timer = 0;
1435 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
1437 callout_stop(&sc->tick_ch);
1441 /* XXX go into loopback & drain q's? */
1442 /* XXX but beware of disabling tx above */
1445 * The MAC core rx/tx disable may leave the MAC hardware in an
1446 * unpredictable state. A hw reset is executed before resetting
1447 * all the MAC parameters to a known value.
1449 WR4(sc, NPE_MAC_CORE_CNTRL, NPE_CORE_RESET);
1450 DELAY(NPE_MAC_RESET_DELAY);
1451 WR4(sc, NPE_MAC_INT_CLK_THRESH, NPE_MAC_INT_CLK_THRESH_DEFAULT);
1452 WR4(sc, NPE_MAC_CORE_CNTRL, NPE_CORE_MDC_EN);
1456 npewatchdog(struct npe_softc *sc)
1458 NPE_ASSERT_LOCKED(sc);
1460 if (sc->npe_watchdog_timer == 0 || --sc->npe_watchdog_timer != 0)
1463 device_printf(sc->sc_dev, "watchdog timeout\n");
1464 sc->sc_ifp->if_oerrors++;
1470 npeioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
1472 struct npe_softc *sc = ifp->if_softc;
1473 struct mii_data *mii;
1474 struct ifreq *ifr = (struct ifreq *)data;
1476 #ifdef DEVICE_POLLING
1483 if ((ifp->if_flags & IFF_UP) == 0 &&
1484 ifp->if_drv_flags & IFF_DRV_RUNNING) {
1485 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1488 /* reinitialize card on any parameter change */
1496 /* update multicast filter list. */
1505 mii = device_get_softc(sc->sc_mii);
1506 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd);
1509 #ifdef DEVICE_POLLING
1511 mask = ifp->if_capenable ^ ifr->ifr_reqcap;
1512 if (mask & IFCAP_POLLING) {
1513 if (ifr->ifr_reqcap & IFCAP_POLLING) {
1514 error = ether_poll_register(npe_poll, ifp);
1518 /* disable callbacks XXX txdone is shared */
1519 ixpqmgr_notify_disable(sc->rx_qid);
1520 ixpqmgr_notify_disable(sc->tx_doneqid);
1521 ifp->if_capenable |= IFCAP_POLLING;
1524 error = ether_poll_deregister(ifp);
1525 /* NB: always enable qmgr callbacks */
1527 /* enable qmgr callbacks */
1528 ixpqmgr_notify_enable(sc->rx_qid,
1529 IX_QMGR_Q_SOURCE_ID_NOT_E);
1530 ixpqmgr_notify_enable(sc->tx_doneqid,
1531 IX_QMGR_Q_SOURCE_ID_NOT_E);
1532 ifp->if_capenable &= ~IFCAP_POLLING;
1539 error = ether_ioctl(ifp, cmd, data);
1546 * Setup a traffic class -> rx queue mapping.
1549 npe_setrxqosentry(struct npe_softc *sc, int classix, int trafclass, int qid)
1553 msg[0] = (NPE_SETRXQOSENTRY << 24) | (sc->sc_npeid << 20) | classix;
1554 msg[1] = (trafclass << 24) | (1 << 23) | (qid << 16) | (qid << 4);
1555 return ixpnpe_sendandrecvmsg_sync(sc->sc_npe, msg, msg);
1559 npe_setportaddress(struct npe_softc *sc, const uint8_t mac[ETHER_ADDR_LEN])
1563 msg[0] = (NPE_SETPORTADDRESS << 24)
1564 | (sc->sc_npeid << 20)
1567 msg[1] = (mac[2] << 24)
1571 return ixpnpe_sendandrecvmsg_sync(sc->sc_npe, msg, msg);
1575 npe_setfirewallmode(struct npe_softc *sc, int onoff)
1579 /* XXX honor onoff */
1580 msg[0] = (NPE_SETFIREWALLMODE << 24) | (sc->sc_npeid << 20);
1582 return ixpnpe_sendandrecvmsg_sync(sc->sc_npe, msg, msg);
1586 * Update and reset the statistics in the NPE.
1589 npe_updatestats(struct npe_softc *sc)
1593 msg[0] = NPE_RESETSTATS << NPE_MAC_MSGID_SHL;
1594 msg[1] = sc->sc_stats_phys; /* physical address of stat block */
1595 return ixpnpe_sendmsg_async(sc->sc_npe, msg);
1600 * Get the current statistics block.
1603 npe_getstats(struct npe_softc *sc)
1607 msg[0] = NPE_GETSTATS << NPE_MAC_MSGID_SHL;
1608 msg[1] = sc->sc_stats_phys; /* physical address of stat block */
1609 return ixpnpe_sendandrecvmsg(sc->sc_npe, msg, msg);
1613 * Query the image id of the loaded firmware.
1616 npe_getimageid(struct npe_softc *sc)
1620 msg[0] = NPE_GETSTATUS << NPE_MAC_MSGID_SHL;
1622 return ixpnpe_sendandrecvmsg_sync(sc->sc_npe, msg, msg) == 0 ? msg[1] : 0;
1626 * Enable/disable loopback.
1629 npe_setloopback(struct npe_softc *sc, int ena)
1633 msg[0] = (NPE_SETLOOPBACK << NPE_MAC_MSGID_SHL) | (ena != 0);
1635 return ixpnpe_sendandrecvmsg_sync(sc->sc_npe, msg, msg);
1640 npe_child_detached(device_t dev, device_t child)
1642 struct npe_softc *sc;
1644 sc = device_get_softc(dev);
1645 if (child == sc->sc_mii)
1650 * MII bus support routines.
1652 #define MII_RD4(sc, reg) bus_space_read_4(sc->sc_iot, sc->sc_miih, reg)
1653 #define MII_WR4(sc, reg, v) \
1654 bus_space_write_4(sc->sc_iot, sc->sc_miih, reg, v)
1657 npe_mii_mdio_read(struct npe_softc *sc, int reg)
1661 /* NB: registers are known to be sequential */
1662 v = (MII_RD4(sc, reg+0) & 0xff) << 0;
1663 v |= (MII_RD4(sc, reg+4) & 0xff) << 8;
1664 v |= (MII_RD4(sc, reg+8) & 0xff) << 16;
1665 v |= (MII_RD4(sc, reg+12) & 0xff) << 24;
1670 npe_mii_mdio_write(struct npe_softc *sc, int reg, uint32_t cmd)
1672 /* NB: registers are known to be sequential */
1673 MII_WR4(sc, reg+0, cmd & 0xff);
1674 MII_WR4(sc, reg+4, (cmd >> 8) & 0xff);
1675 MII_WR4(sc, reg+8, (cmd >> 16) & 0xff);
1676 MII_WR4(sc, reg+12, (cmd >> 24) & 0xff);
1680 npe_mii_mdio_wait(struct npe_softc *sc)
1685 /* NB: typically this takes 25-30 trips */
1686 for (i = 0; i < 1000; i++) {
1687 v = npe_mii_mdio_read(sc, NPE_MAC_MDIO_CMD);
1688 if ((v & NPE_MII_GO) == 0)
1692 device_printf(sc->sc_dev, "%s: timeout after ~1ms, cmd 0x%x\n",
1694 return 0; /* NB: timeout */
1698 npe_miibus_readreg(device_t dev, int phy, int reg)
1700 struct npe_softc *sc = device_get_softc(dev);
1703 if (phy != sc->sc_phy) /* XXX no auto-detect */
1705 v = (phy << NPE_MII_ADDR_SHL) | (reg << NPE_MII_REG_SHL) | NPE_MII_GO;
1706 npe_mii_mdio_write(sc, NPE_MAC_MDIO_CMD, v);
1707 if (npe_mii_mdio_wait(sc))
1708 v = npe_mii_mdio_read(sc, NPE_MAC_MDIO_STS);
1710 v = 0xffff | NPE_MII_READ_FAIL;
1711 return (v & NPE_MII_READ_FAIL) ? 0xffff : (v & 0xffff);
1715 npe_miibus_writereg(device_t dev, int phy, int reg, int data)
1717 struct npe_softc *sc = device_get_softc(dev);
1720 if (phy != sc->sc_phy) /* XXX */
1722 v = (phy << NPE_MII_ADDR_SHL) | (reg << NPE_MII_REG_SHL)
1723 | data | NPE_MII_WRITE
1725 npe_mii_mdio_write(sc, NPE_MAC_MDIO_CMD, v);
1726 /* XXX complain about timeout */
1727 (void) npe_mii_mdio_wait(sc);
1732 npe_miibus_statchg(device_t dev)
1734 struct npe_softc *sc = device_get_softc(dev);
1735 struct mii_data *mii = device_get_softc(sc->sc_mii);
1738 /* sync MAC duplex state */
1739 tx1 = RD4(sc, NPE_MAC_TX_CNTRL1);
1740 rx1 = RD4(sc, NPE_MAC_RX_CNTRL1);
1741 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
1742 tx1 &= ~NPE_TX_CNTRL1_DUPLEX;
1743 rx1 |= NPE_RX_CNTRL1_PAUSE_EN;
1745 tx1 |= NPE_TX_CNTRL1_DUPLEX;
1746 rx1 &= ~NPE_RX_CNTRL1_PAUSE_EN;
1748 WR4(sc, NPE_MAC_RX_CNTRL1, rx1);
1749 WR4(sc, NPE_MAC_TX_CNTRL1, tx1);
1752 static device_method_t npe_methods[] = {
1753 /* Device interface */
1754 DEVMETHOD(device_probe, npe_probe),
1755 DEVMETHOD(device_attach, npe_attach),
1756 DEVMETHOD(device_detach, npe_detach),
1759 DEVMETHOD(bus_child_detached, npe_child_detached),
1762 DEVMETHOD(miibus_readreg, npe_miibus_readreg),
1763 DEVMETHOD(miibus_writereg, npe_miibus_writereg),
1764 DEVMETHOD(miibus_statchg, npe_miibus_statchg),
1769 static driver_t npe_driver = {
1772 sizeof(struct npe_softc),
1775 DRIVER_MODULE(npe, ixp, npe_driver, npe_devclass, 0, 0);
1776 DRIVER_MODULE(miibus, npe, miibus_driver, miibus_devclass, 0, 0);
1777 MODULE_DEPEND(npe, ixpqmgr, 1, 1, 1);
1778 MODULE_DEPEND(npe, miibus, 1, 1, 1);
1779 MODULE_DEPEND(npe, ether, 1, 1, 1);