2 * Copyright (c) 2008 Stanislav Sedov <stas@FreeBSD.org>.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
16 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
17 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
19 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
20 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
21 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
23 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 * Driver for Attansic Technology Corp. L2 FastEthernet adapter.
27 * This driver is heavily based on age(4) Attansic L1 driver by Pyun YongHyeon.
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD$");
33 #include <sys/param.h>
34 #include <sys/systm.h>
36 #include <sys/endian.h>
37 #include <sys/kernel.h>
38 #include <sys/malloc.h>
41 #include <sys/module.h>
42 #include <sys/queue.h>
43 #include <sys/socket.h>
44 #include <sys/sockio.h>
45 #include <sys/sysctl.h>
46 #include <sys/taskqueue.h>
50 #include <net/if_arp.h>
51 #include <net/ethernet.h>
52 #include <net/if_dl.h>
53 #include <net/if_media.h>
54 #include <net/if_types.h>
55 #include <net/if_vlan_var.h>
57 #include <netinet/in.h>
58 #include <netinet/in_systm.h>
59 #include <netinet/ip.h>
60 #include <netinet/tcp.h>
62 #include <dev/mii/mii.h>
63 #include <dev/mii/miivar.h>
64 #include <dev/pci/pcireg.h>
65 #include <dev/pci/pcivar.h>
67 #include <machine/bus.h>
69 #include "miibus_if.h"
75 * Devices supported by this driver.
77 static struct ae_dev {
82 { VENDORID_ATTANSIC, DEVICEID_ATTANSIC_L2,
83 "Attansic Technology Corp, L2 FastEthernet" },
85 #define AE_DEVS_COUNT (sizeof(ae_devs) / sizeof(*ae_devs))
87 static struct resource_spec ae_res_spec_mem[] = {
88 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE },
91 static struct resource_spec ae_res_spec_irq[] = {
92 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE },
95 static struct resource_spec ae_res_spec_msi[] = {
96 { SYS_RES_IRQ, 1, RF_ACTIVE },
100 static int ae_probe(device_t dev);
101 static int ae_attach(device_t dev);
102 static void ae_pcie_init(ae_softc_t *sc);
103 static void ae_phy_reset(ae_softc_t *sc);
104 static void ae_phy_init(ae_softc_t *sc);
105 static int ae_reset(ae_softc_t *sc);
106 static void ae_init(void *arg);
107 static int ae_init_locked(ae_softc_t *sc);
108 static int ae_detach(device_t dev);
109 static int ae_miibus_readreg(device_t dev, int phy, int reg);
110 static int ae_miibus_writereg(device_t dev, int phy, int reg, int val);
111 static void ae_miibus_statchg(device_t dev);
112 static void ae_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr);
113 static int ae_mediachange(struct ifnet *ifp);
114 static void ae_retrieve_address(ae_softc_t *sc);
115 static void ae_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs,
117 static int ae_alloc_rings(ae_softc_t *sc);
118 static void ae_dma_free(ae_softc_t *sc);
119 static int ae_shutdown(device_t dev);
120 static int ae_suspend(device_t dev);
121 static void ae_powersave_disable(ae_softc_t *sc);
122 static void ae_powersave_enable(ae_softc_t *sc);
123 static int ae_resume(device_t dev);
124 static unsigned int ae_tx_avail_size(ae_softc_t *sc);
125 static int ae_encap(ae_softc_t *sc, struct mbuf **m_head);
126 static void ae_start(struct ifnet *ifp);
127 static void ae_link_task(void *arg, int pending);
128 static void ae_stop_rxmac(ae_softc_t *sc);
129 static void ae_stop_txmac(ae_softc_t *sc);
130 static void ae_tx_task(void *arg, int pending);
131 static void ae_mac_config(ae_softc_t *sc);
132 static int ae_intr(void *arg);
133 static void ae_int_task(void *arg, int pending);
134 static void ae_tx_intr(ae_softc_t *sc);
135 static int ae_rxeof(ae_softc_t *sc, ae_rxd_t *rxd);
136 static void ae_rx_intr(ae_softc_t *sc);
137 static void ae_watchdog(ae_softc_t *sc);
138 static void ae_tick(void *arg);
139 static void ae_rxfilter(ae_softc_t *sc);
140 static void ae_rxvlan(ae_softc_t *sc);
141 static int ae_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data);
142 static void ae_stop(ae_softc_t *sc);
143 static int ae_check_eeprom_present(ae_softc_t *sc, int *vpdc);
144 static int ae_vpd_read_word(ae_softc_t *sc, int reg, uint32_t *word);
145 static int ae_get_vpd_eaddr(ae_softc_t *sc, uint32_t *eaddr);
146 static int ae_get_reg_eaddr(ae_softc_t *sc, uint32_t *eaddr);
147 static void ae_update_stats_rx(uint16_t flags, ae_stats_t *stats);
148 static void ae_update_stats_tx(uint16_t flags, ae_stats_t *stats);
149 static void ae_init_tunables(ae_softc_t *sc);
151 static device_method_t ae_methods[] = {
152 /* Device interface. */
153 DEVMETHOD(device_probe, ae_probe),
154 DEVMETHOD(device_attach, ae_attach),
155 DEVMETHOD(device_detach, ae_detach),
156 DEVMETHOD(device_shutdown, ae_shutdown),
157 DEVMETHOD(device_suspend, ae_suspend),
158 DEVMETHOD(device_resume, ae_resume),
161 DEVMETHOD(miibus_readreg, ae_miibus_readreg),
162 DEVMETHOD(miibus_writereg, ae_miibus_writereg),
163 DEVMETHOD(miibus_statchg, ae_miibus_statchg),
167 static driver_t ae_driver = {
172 static devclass_t ae_devclass;
174 DRIVER_MODULE(ae, pci, ae_driver, ae_devclass, 0, 0);
175 DRIVER_MODULE(miibus, ae, miibus_driver, miibus_devclass, 0, 0);
176 MODULE_DEPEND(ae, pci, 1, 1, 1);
177 MODULE_DEPEND(ae, ether, 1, 1, 1);
178 MODULE_DEPEND(ae, miibus, 1, 1, 1);
183 static int msi_disable = 0;
184 TUNABLE_INT("hw.ae.msi_disable", &msi_disable);
186 #define AE_READ_4(sc, reg) \
187 bus_read_4((sc)->mem[0], (reg))
188 #define AE_READ_2(sc, reg) \
189 bus_read_2((sc)->mem[0], (reg))
190 #define AE_READ_1(sc, reg) \
191 bus_read_1((sc)->mem[0], (reg))
192 #define AE_WRITE_4(sc, reg, val) \
193 bus_write_4((sc)->mem[0], (reg), (val))
194 #define AE_WRITE_2(sc, reg, val) \
195 bus_write_2((sc)->mem[0], (reg), (val))
196 #define AE_WRITE_1(sc, reg, val) \
197 bus_write_1((sc)->mem[0], (reg), (val))
198 #define AE_PHY_READ(sc, reg) \
199 ae_miibus_readreg(sc->dev, 0, reg)
200 #define AE_PHY_WRITE(sc, reg, val) \
201 ae_miibus_writereg(sc->dev, 0, reg, val)
202 #define AE_CHECK_EADDR_VALID(eaddr) \
203 ((eaddr[0] == 0 && eaddr[1] == 0) || \
204 (eaddr[0] == 0xffffffff && eaddr[1] == 0xffff))
205 #define AE_RXD_VLAN(vtag) \
206 (((vtag) >> 4) | (((vtag) & 0x07) << 13) | (((vtag) & 0x08) << 9))
207 #define AE_TXD_VLAN(vtag) \
208 (((vtag) << 4) | (((vtag) >> 13) & 0x07) | (((vtag) >> 9) & 0x08))
213 #define STATS_ENTRY(node, desc, field) \
214 { node, desc, offsetof(struct ae_stats, field) }
220 STATS_ENTRY("bcast", "broadcast frames", tx_bcast),
221 STATS_ENTRY("mcast", "multicast frames", tx_mcast),
222 STATS_ENTRY("pause", "PAUSE frames", tx_pause),
223 STATS_ENTRY("control", "control frames", tx_ctrl),
224 STATS_ENTRY("defers", "deferrals occuried", tx_defer),
225 STATS_ENTRY("exc_defers", "excessive deferrals occuried", tx_excdefer),
226 STATS_ENTRY("singlecols", "single collisions occuried", tx_singlecol),
227 STATS_ENTRY("multicols", "multiple collisions occuried", tx_multicol),
228 STATS_ENTRY("latecols", "late collisions occuried", tx_latecol),
229 STATS_ENTRY("aborts", "transmit aborts due collisions", tx_abortcol),
230 STATS_ENTRY("underruns", "Tx FIFO underruns", tx_underrun)
232 STATS_ENTRY("bcast", "broadcast frames", rx_bcast),
233 STATS_ENTRY("mcast", "multicast frames", rx_mcast),
234 STATS_ENTRY("pause", "PAUSE frames", rx_pause),
235 STATS_ENTRY("control", "control frames", rx_ctrl),
236 STATS_ENTRY("crc_errors", "frames with CRC errors", rx_crcerr),
237 STATS_ENTRY("code_errors", "frames with invalid opcode", rx_codeerr),
238 STATS_ENTRY("runt", "runt frames", rx_runt),
239 STATS_ENTRY("frag", "fragmented frames", rx_frag),
240 STATS_ENTRY("align_errors", "frames with alignment errors", rx_align),
241 STATS_ENTRY("truncated", "frames truncated due to Rx FIFO inderrun",
244 #define AE_STATS_RX_LEN (sizeof(ae_stats_rx) / sizeof(*ae_stats_rx))
245 #define AE_STATS_TX_LEN (sizeof(ae_stats_tx) / sizeof(*ae_stats_tx))
248 ae_probe(device_t dev)
250 uint16_t deviceid, vendorid;
253 vendorid = pci_get_vendor(dev);
254 deviceid = pci_get_device(dev);
257 * Search through the list of supported devs for matching one.
259 for (i = 0; i < AE_DEVS_COUNT; i++) {
260 if (vendorid == ae_devs[i].vendorid &&
261 deviceid == ae_devs[i].deviceid) {
262 device_set_desc(dev, ae_devs[i].name);
263 return (BUS_PROBE_DEFAULT);
270 ae_attach(device_t dev)
279 sc = device_get_softc(dev); /* Automatically allocated and zeroed
281 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL", __LINE__));
285 * Initialize mutexes and tasks.
287 mtx_init(&sc->mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, MTX_DEF);
288 callout_init_mtx(&sc->tick_ch, &sc->mtx, 0);
289 TASK_INIT(&sc->int_task, 0, ae_int_task, sc);
290 TASK_INIT(&sc->link_task, 0, ae_link_task, sc);
292 pci_enable_busmaster(dev); /* Enable bus mastering. */
294 sc->spec_mem = ae_res_spec_mem;
297 * Allocate memory-mapped registers.
299 error = bus_alloc_resources(dev, sc->spec_mem, sc->mem);
301 device_printf(dev, "could not allocate memory resources.\n");
307 * Retrieve PCI and chip revisions.
309 pcirev = pci_get_revid(dev);
310 chiprev = (AE_READ_4(sc, AE_MASTER_REG) >> AE_MASTER_REVNUM_SHIFT) &
311 AE_MASTER_REVNUM_MASK;
313 device_printf(dev, "pci device revision: %#04x\n", pcirev);
314 device_printf(dev, "chip id: %#02x\n", chiprev);
316 nmsi = pci_msi_count(dev);
318 device_printf(dev, "MSI count: %d.\n", nmsi);
321 * Allocate interrupt resources.
323 if (msi_disable == 0 && nmsi == 1) {
324 error = pci_alloc_msi(dev, &nmsi);
326 device_printf(dev, "Using MSI messages.\n");
327 sc->spec_irq = ae_res_spec_msi;
328 error = bus_alloc_resources(dev, sc->spec_irq, sc->irq);
330 device_printf(dev, "MSI allocation failed.\n");
332 pci_release_msi(dev);
334 sc->flags |= AE_FLAG_MSI;
338 if (sc->spec_irq == NULL) {
339 sc->spec_irq = ae_res_spec_irq;
340 error = bus_alloc_resources(dev, sc->spec_irq, sc->irq);
342 device_printf(dev, "could not allocate IRQ resources.\n");
348 ae_init_tunables(sc);
350 ae_phy_reset(sc); /* Reset PHY. */
351 error = ae_reset(sc); /* Reset the controller itself. */
357 ae_retrieve_address(sc); /* Load MAC address. */
359 error = ae_alloc_rings(sc); /* Allocate ring buffers. */
363 /* Set default PHY address. */
364 sc->phyaddr = AE_PHYADDR_DEFAULT;
366 ifp = sc->ifp = if_alloc(IFT_ETHER);
368 device_printf(dev, "could not allocate ifnet structure.\n");
374 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
375 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
376 ifp->if_ioctl = ae_ioctl;
377 ifp->if_start = ae_start;
378 ifp->if_init = ae_init;
379 ifp->if_capabilities = IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING;
380 ifp->if_hwassist = 0;
381 ifp->if_snd.ifq_drv_maxlen = IFQ_MAXLEN;
382 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen);
383 IFQ_SET_READY(&ifp->if_snd);
384 if (pci_find_extcap(dev, PCIY_PMG, &pmc) == 0) {
385 ifp->if_capabilities |= IFCAP_WOL_MAGIC;
386 sc->flags |= AE_FLAG_PMG;
388 ifp->if_capenable = ifp->if_capabilities;
391 * Configure and attach MII bus.
393 error = mii_phy_probe(dev, &sc->miibus, ae_mediachange,
396 device_printf(dev, "no PHY found.\n");
400 ether_ifattach(ifp, sc->eaddr);
401 /* Tell the upper layer(s) we support long frames. */
402 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
405 * Create and run all helper tasks.
407 TASK_INIT(&sc->tx_task, 1, ae_tx_task, ifp);
408 sc->tq = taskqueue_create_fast("ae_taskq", M_WAITOK,
409 taskqueue_thread_enqueue, &sc->tq);
410 if (sc->tq == NULL) {
411 device_printf(dev, "could not create taskqueue.\n");
416 taskqueue_start_threads(&sc->tq, 1, PI_NET, "%s taskq",
417 device_get_nameunit(sc->dev));
420 * Configure interrupt handlers.
422 error = bus_setup_intr(dev, sc->irq[0], INTR_TYPE_NET | INTR_MPSAFE,
423 ae_intr, NULL, sc, &sc->intrhand);
425 device_printf(dev, "could not set up interrupt handler.\n");
426 taskqueue_free(sc->tq);
440 ae_init_tunables(ae_softc_t *sc)
442 struct sysctl_ctx_list *ctx;
443 struct sysctl_oid *root, *stats, *stats_rx, *stats_tx;
444 struct ae_stats *ae_stats;
447 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL", __LINE__));
448 ae_stats = &sc->stats;
450 ctx = device_get_sysctl_ctx(sc->dev);
451 root = device_get_sysctl_tree(sc->dev);
452 stats = SYSCTL_ADD_NODE(ctx, SYSCTL_CHILDREN(root), OID_AUTO, "stats",
453 CTLFLAG_RD, NULL, "ae statistics");
456 * Receiver statistcics.
458 stats_rx = SYSCTL_ADD_NODE(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, "rx",
459 CTLFLAG_RD, NULL, "Rx MAC statistics");
460 for (i = 0; i < AE_STATS_RX_LEN; i++)
461 SYSCTL_ADD_UINT(ctx, SYSCTL_CHILDREN(stats_rx), OID_AUTO,
462 ae_stats_rx[i].node, CTLFLAG_RD, (char *)ae_stats +
463 ae_stats_rx[i].offset, 0, ae_stats_rx[i].desc);
466 * Receiver statistcics.
468 stats_tx = SYSCTL_ADD_NODE(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, "tx",
469 CTLFLAG_RD, NULL, "Tx MAC statistics");
470 for (i = 0; i < AE_STATS_TX_LEN; i++)
471 SYSCTL_ADD_UINT(ctx, SYSCTL_CHILDREN(stats_tx), OID_AUTO,
472 ae_stats_tx[i].node, CTLFLAG_RD, (char *)ae_stats +
473 ae_stats_tx[i].offset, 0, ae_stats_tx[i].desc);
477 ae_pcie_init(ae_softc_t *sc)
480 AE_WRITE_4(sc, AE_PCIE_LTSSM_TESTMODE_REG, AE_PCIE_LTSSM_TESTMODE_DEFAULT);
481 AE_WRITE_4(sc, AE_PCIE_DLL_TX_CTRL_REG, AE_PCIE_DLL_TX_CTRL_DEFAULT);
485 ae_phy_reset(ae_softc_t *sc)
488 AE_WRITE_4(sc, AE_PHY_ENABLE_REG, AE_PHY_ENABLE);
489 DELAY(1000); /* XXX: pause(9) ? */
493 ae_reset(ae_softc_t *sc)
498 * Issue a soft reset.
500 AE_WRITE_4(sc, AE_MASTER_REG, AE_MASTER_SOFT_RESET);
501 bus_barrier(sc->mem[0], AE_MASTER_REG, 4,
502 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
505 * Wait for reset to complete.
507 for (i = 0; i < AE_RESET_TIMEOUT; i++) {
508 if ((AE_READ_4(sc, AE_MASTER_REG) & AE_MASTER_SOFT_RESET) == 0)
512 if (i == AE_RESET_TIMEOUT) {
513 device_printf(sc->dev, "reset timeout.\n");
518 * Wait for everything to enter idle state.
520 for (i = 0; i < AE_IDLE_TIMEOUT; i++) {
521 if (AE_READ_4(sc, AE_IDLE_REG) == 0)
525 if (i == AE_IDLE_TIMEOUT) {
526 device_printf(sc->dev, "could not enter idle state.\n");
537 sc = (ae_softc_t *)arg;
544 ae_phy_init(ae_softc_t *sc)
548 * Enable link status change interrupt.
552 AE_PHY_WRITE(sc, 18, 0xc00);
557 ae_init_locked(ae_softc_t *sc)
560 struct mii_data *mii;
561 uint8_t eaddr[ETHER_ADDR_LEN];
568 mii = device_get_softc(sc->miibus);
572 ae_pcie_init(sc); /* Initialize PCIE stuff. */
574 ae_powersave_disable(sc);
577 * Clear and disable interrupts.
579 AE_WRITE_4(sc, AE_ISR_REG, 0xffffffff);
582 * Set the MAC address.
584 bcopy(IF_LLADDR(ifp), eaddr, ETHER_ADDR_LEN);
585 val = eaddr[2] << 24 | eaddr[3] << 16 | eaddr[4] << 8 | eaddr[5];
586 AE_WRITE_4(sc, AE_EADDR0_REG, val);
587 val = eaddr[0] << 8 | eaddr[1];
588 AE_WRITE_4(sc, AE_EADDR1_REG, val);
591 * Set ring buffers base addresses.
593 addr = sc->dma_rxd_busaddr;
594 AE_WRITE_4(sc, AE_DESC_ADDR_HI_REG, BUS_ADDR_HI(addr));
595 AE_WRITE_4(sc, AE_RXD_ADDR_LO_REG, BUS_ADDR_LO(addr));
596 addr = sc->dma_txd_busaddr;
597 AE_WRITE_4(sc, AE_TXD_ADDR_LO_REG, BUS_ADDR_LO(addr));
598 addr = sc->dma_txs_busaddr;
599 AE_WRITE_4(sc, AE_TXS_ADDR_LO_REG, BUS_ADDR_LO(addr));
602 * Configure ring buffers sizes.
604 AE_WRITE_2(sc, AE_RXD_COUNT_REG, AE_RXD_COUNT_DEFAULT);
605 AE_WRITE_2(sc, AE_TXD_BUFSIZE_REG, AE_TXD_BUFSIZE_DEFAULT / 4);
606 AE_WRITE_2(sc, AE_TXS_COUNT_REG, AE_TXS_COUNT_DEFAULT);
609 * Configure interframe gap parameters.
611 val = ((AE_IFG_TXIPG_DEFAULT << AE_IFG_TXIPG_SHIFT) &
613 ((AE_IFG_RXIPG_DEFAULT << AE_IFG_RXIPG_SHIFT) &
615 ((AE_IFG_IPGR1_DEFAULT << AE_IFG_IPGR1_SHIFT) &
617 ((AE_IFG_IPGR2_DEFAULT << AE_IFG_IPGR2_SHIFT) &
619 AE_WRITE_4(sc, AE_IFG_REG, val);
622 * Configure half-duplex operation.
624 val = ((AE_HDPX_LCOL_DEFAULT << AE_HDPX_LCOL_SHIFT) &
626 ((AE_HDPX_RETRY_DEFAULT << AE_HDPX_RETRY_SHIFT) &
627 AE_HDPX_RETRY_MASK) |
628 ((AE_HDPX_ABEBT_DEFAULT << AE_HDPX_ABEBT_SHIFT) &
629 AE_HDPX_ABEBT_MASK) |
630 ((AE_HDPX_JAMIPG_DEFAULT << AE_HDPX_JAMIPG_SHIFT) &
631 AE_HDPX_JAMIPG_MASK) | AE_HDPX_EXC_EN;
632 AE_WRITE_4(sc, AE_HDPX_REG, val);
635 * Configure interrupt moderate timer.
637 AE_WRITE_2(sc, AE_IMT_REG, AE_IMT_DEFAULT);
638 val = AE_READ_4(sc, AE_MASTER_REG);
639 val |= AE_MASTER_IMT_EN;
640 AE_WRITE_4(sc, AE_MASTER_REG, val);
643 * Configure interrupt clearing timer.
645 AE_WRITE_2(sc, AE_ICT_REG, AE_ICT_DEFAULT);
650 val = ifp->if_mtu + ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN +
652 AE_WRITE_2(sc, AE_MTU_REG, val);
655 * Configure cut-through threshold.
657 AE_WRITE_4(sc, AE_CUT_THRESH_REG, AE_CUT_THRESH_DEFAULT);
660 * Configure flow control.
662 AE_WRITE_2(sc, AE_FLOW_THRESH_HI_REG, (AE_RXD_COUNT_DEFAULT / 8) * 7);
663 AE_WRITE_2(sc, AE_FLOW_THRESH_LO_REG, (AE_RXD_COUNT_MIN / 8) >
664 (AE_RXD_COUNT_DEFAULT / 12) ? (AE_RXD_COUNT_MIN / 8) :
665 (AE_RXD_COUNT_DEFAULT / 12));
670 sc->txd_cur = sc->rxd_cur = 0;
671 sc->txs_ack = sc->txd_ack = 0;
673 AE_WRITE_2(sc, AE_MB_TXD_IDX_REG, sc->txd_cur);
674 AE_WRITE_2(sc, AE_MB_RXD_IDX_REG, sc->rxd_cur);
676 sc->tx_inproc = 0; /* Number of packets the chip processes now. */
677 sc->flags |= AE_FLAG_TXAVAIL; /* Free Tx's available. */
682 AE_WRITE_1(sc, AE_DMAREAD_REG, AE_DMAREAD_EN);
683 AE_WRITE_1(sc, AE_DMAWRITE_REG, AE_DMAWRITE_EN);
686 * Check if everything is OK.
688 val = AE_READ_4(sc, AE_ISR_REG);
689 if ((val & AE_ISR_PHY_LINKDOWN) != 0) {
690 device_printf(sc->dev, "Initialization failed.\n");
695 * Clear interrupt status.
697 AE_WRITE_4(sc, AE_ISR_REG, 0x3fffffff);
698 AE_WRITE_4(sc, AE_ISR_REG, 0x0);
703 val = AE_READ_4(sc, AE_MASTER_REG);
704 AE_WRITE_4(sc, AE_MASTER_REG, val | AE_MASTER_MANUAL_INT);
705 AE_WRITE_4(sc, AE_IMR_REG, AE_IMR_DEFAULT);
710 AE_WRITE_4(sc, AE_WOL_REG, 0);
715 val = AE_MAC_TX_CRC_EN | AE_MAC_TX_AUTOPAD |
716 AE_MAC_FULL_DUPLEX | AE_MAC_CLK_PHY |
717 AE_MAC_TX_FLOW_EN | AE_MAC_RX_FLOW_EN |
718 ((AE_HALFBUF_DEFAULT << AE_HALFBUF_SHIFT) & AE_HALFBUF_MASK) |
719 ((AE_MAC_PREAMBLE_DEFAULT << AE_MAC_PREAMBLE_SHIFT) &
720 AE_MAC_PREAMBLE_MASK);
721 AE_WRITE_4(sc, AE_MAC_REG, val);
732 val = AE_READ_4(sc, AE_MAC_REG);
733 AE_WRITE_4(sc, AE_MAC_REG, val | AE_MAC_TX_EN | AE_MAC_RX_EN);
735 sc->flags &= ~AE_FLAG_LINK;
736 mii_mediachg(mii); /* Switch to the current media. */
738 callout_reset(&sc->tick_ch, hz, ae_tick, sc);
740 ifp->if_drv_flags |= IFF_DRV_RUNNING;
741 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
744 device_printf(sc->dev, "Initialization complete.\n");
751 ae_detach(device_t dev)
756 sc = device_get_softc(dev);
757 KASSERT(sc != NULL, ("[ae: %d]: sc is NULL", __LINE__));
759 if (device_is_attached(dev)) {
761 sc->flags |= AE_FLAG_DETACH;
764 callout_drain(&sc->tick_ch);
765 taskqueue_drain(sc->tq, &sc->int_task);
766 taskqueue_drain(sc->tq, &sc->tx_task);
767 taskqueue_drain(taskqueue_swi, &sc->link_task);
770 if (sc->tq != NULL) {
771 taskqueue_drain(sc->tq, &sc->int_task);
772 taskqueue_free(sc->tq);
775 if (sc->miibus != NULL) {
776 device_delete_child(dev, sc->miibus);
779 bus_generic_detach(sc->dev);
781 if (sc->intrhand != NULL) {
782 bus_teardown_intr(dev, sc->irq[0], sc->intrhand);
789 if (sc->spec_irq != NULL)
790 bus_release_resources(dev, sc->spec_irq, sc->irq);
791 if (sc->spec_mem != NULL)
792 bus_release_resources(dev, sc->spec_mem, sc->mem);
793 if ((sc->flags & AE_FLAG_MSI) != 0)
794 pci_release_msi(dev);
795 mtx_destroy(&sc->mtx);
801 ae_miibus_readreg(device_t dev, int phy, int reg)
807 sc = device_get_softc(dev);
808 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL", __LINE__));
811 * Locking is done in upper layers.
814 if (phy != sc->phyaddr)
817 val = ((reg << AE_MDIO_REGADDR_SHIFT) & AE_MDIO_REGADDR_MASK) |
818 AE_MDIO_START | AE_MDIO_READ | AE_MDIO_SUP_PREAMBLE |
819 ((AE_MDIO_CLK_25_4 << AE_MDIO_CLK_SHIFT) & AE_MDIO_CLK_MASK);
820 AE_WRITE_4(sc, AE_MDIO_REG, val);
823 * Wait for operation to complete.
825 for (i = 0; i < AE_MDIO_TIMEOUT; i++) {
827 val = AE_READ_4(sc, AE_MDIO_REG);
828 if ((val & (AE_MDIO_START | AE_MDIO_BUSY)) == 0)
831 if (i == AE_MDIO_TIMEOUT) {
832 device_printf(sc->dev, "phy read timeout: %d.\n", reg);
835 return ((val << AE_MDIO_DATA_SHIFT) & AE_MDIO_DATA_MASK);
839 ae_miibus_writereg(device_t dev, int phy, int reg, int val)
845 sc = device_get_softc(dev);
846 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL", __LINE__));
849 * Locking is done in upper layers.
852 if (phy != sc->phyaddr)
855 aereg = ((reg << AE_MDIO_REGADDR_SHIFT) & AE_MDIO_REGADDR_MASK) |
856 AE_MDIO_START | AE_MDIO_SUP_PREAMBLE |
857 ((AE_MDIO_CLK_25_4 << AE_MDIO_CLK_SHIFT) & AE_MDIO_CLK_MASK) |
858 ((val << AE_MDIO_DATA_SHIFT) & AE_MDIO_DATA_MASK);
859 AE_WRITE_4(sc, AE_MDIO_REG, aereg);
862 * Wait for operation to complete.
864 for (i = 0; i < AE_MDIO_TIMEOUT; i++) {
866 aereg = AE_READ_4(sc, AE_MDIO_REG);
867 if ((aereg & (AE_MDIO_START | AE_MDIO_BUSY)) == 0)
870 if (i == AE_MDIO_TIMEOUT) {
871 device_printf(sc->dev, "phy write timeout: %d.\n", reg);
877 ae_miibus_statchg(device_t dev)
881 sc = device_get_softc(dev);
882 taskqueue_enqueue(taskqueue_swi, &sc->link_task);
886 ae_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr)
889 struct mii_data *mii;
892 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL", __LINE__));
895 mii = device_get_softc(sc->miibus);
897 ifmr->ifm_status = mii->mii_media_status;
898 ifmr->ifm_active = mii->mii_media_active;
903 ae_mediachange(struct ifnet *ifp)
906 struct mii_data *mii;
907 struct mii_softc *mii_sc;
910 /* XXX: check IFF_UP ?? */
912 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL", __LINE__));
914 mii = device_get_softc(sc->miibus);
915 if (mii->mii_instance != 0) {
916 LIST_FOREACH(mii_sc, &mii->mii_phys, mii_list)
917 mii_phy_reset(mii_sc);
919 error = mii_mediachg(mii);
926 ae_check_eeprom_present(ae_softc_t *sc, int *vpdc)
931 KASSERT(vpdc != NULL, ("[ae, %d]: vpdc is NULL!\n", __LINE__));
934 * Not sure why, but Linux does this.
936 val = AE_READ_4(sc, AE_SPICTL_REG);
937 if ((val & AE_SPICTL_VPD_EN) != 0) {
938 val &= ~AE_SPICTL_VPD_EN;
939 AE_WRITE_4(sc, AE_SPICTL_REG, val);
941 error = pci_find_extcap(sc->dev, PCIY_VPD, vpdc);
946 ae_vpd_read_word(ae_softc_t *sc, int reg, uint32_t *word)
951 AE_WRITE_4(sc, AE_VPD_DATA_REG, 0); /* Clear register value. */
954 * VPD registers start at offset 0x100. Read them.
956 val = 0x100 + reg * 4;
957 AE_WRITE_4(sc, AE_VPD_CAP_REG, (val << AE_VPD_CAP_ADDR_SHIFT) &
958 AE_VPD_CAP_ADDR_MASK);
959 for (i = 0; i < AE_VPD_TIMEOUT; i++) {
961 val = AE_READ_4(sc, AE_VPD_CAP_REG);
962 if ((val & AE_VPD_CAP_DONE) != 0)
965 if (i == AE_VPD_TIMEOUT) {
966 device_printf(sc->dev, "timeout reading VPD register %d.\n",
970 *word = AE_READ_4(sc, AE_VPD_DATA_REG);
975 ae_get_vpd_eaddr(ae_softc_t *sc, uint32_t *eaddr)
977 uint32_t word, reg, val;
983 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL", __LINE__));
984 KASSERT(eaddr != NULL, ("[ae, %d]: eaddr is NULL", __LINE__));
989 error = ae_check_eeprom_present(sc, &vpdc);
994 * Read the VPD configuration space.
995 * Each register is prefixed with signature,
996 * so we can check if it is valid.
998 for (i = 0, found = 0; i < AE_VPD_NREGS; i++) {
999 error = ae_vpd_read_word(sc, i, &word);
1006 if ((word & AE_VPD_SIG_MASK) != AE_VPD_SIG)
1008 reg = word >> AE_VPD_REG_SHIFT;
1009 i++; /* Move to the next word. */
1011 if (reg != AE_EADDR0_REG && reg != AE_EADDR1_REG)
1014 error = ae_vpd_read_word(sc, i, &val);
1017 if (reg == AE_EADDR0_REG)
1027 eaddr[1] &= 0xffff; /* Only last 2 bytes are used. */
1028 if (AE_CHECK_EADDR_VALID(eaddr) != 0) {
1030 device_printf(sc->dev,
1031 "VPD ethernet address registers are invalid.\n");
1038 ae_get_reg_eaddr(ae_softc_t *sc, uint32_t *eaddr)
1042 * BIOS is supposed to set this.
1044 eaddr[0] = AE_READ_4(sc, AE_EADDR0_REG);
1045 eaddr[1] = AE_READ_4(sc, AE_EADDR1_REG);
1046 eaddr[1] &= 0xffff; /* Only last 2 bytes are used. */
1048 if (AE_CHECK_EADDR_VALID(eaddr) != 0) {
1050 device_printf(sc->dev,
1051 "Ethernet address registers are invalid.\n");
1058 ae_retrieve_address(ae_softc_t *sc)
1060 uint32_t eaddr[2] = {0, 0};
1066 error = ae_get_vpd_eaddr(sc, eaddr);
1068 error = ae_get_reg_eaddr(sc, eaddr);
1071 device_printf(sc->dev,
1072 "Generating random ethernet address.\n");
1073 eaddr[0] = arc4random();
1076 * Set OUI to ASUSTek COMPUTER INC.
1078 sc->eaddr[0] = 0x02; /* U/L bit set. */
1079 sc->eaddr[1] = 0x1f;
1080 sc->eaddr[2] = 0xc6;
1081 sc->eaddr[3] = (eaddr[0] >> 16) & 0xff;
1082 sc->eaddr[4] = (eaddr[0] >> 8) & 0xff;
1083 sc->eaddr[5] = (eaddr[0] >> 0) & 0xff;
1085 sc->eaddr[0] = (eaddr[1] >> 8) & 0xff;
1086 sc->eaddr[1] = (eaddr[1] >> 0) & 0xff;
1087 sc->eaddr[2] = (eaddr[0] >> 24) & 0xff;
1088 sc->eaddr[3] = (eaddr[0] >> 16) & 0xff;
1089 sc->eaddr[4] = (eaddr[0] >> 8) & 0xff;
1090 sc->eaddr[5] = (eaddr[0] >> 0) & 0xff;
1095 ae_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
1097 bus_addr_t *addr = arg;
1101 KASSERT(nsegs == 1, ("[ae, %d]: %d segments instead of 1!", __LINE__,
1103 *addr = segs[0].ds_addr;
1107 ae_alloc_rings(ae_softc_t *sc)
1113 * Create parent DMA tag.
1115 error = bus_dma_tag_create(bus_get_dma_tag(sc->dev),
1116 1, 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR,
1117 NULL, NULL, BUS_SPACE_MAXSIZE_32BIT, 0,
1118 BUS_SPACE_MAXSIZE_32BIT, 0, NULL, NULL,
1119 &sc->dma_parent_tag);
1121 device_printf(sc->dev, "could not creare parent DMA tag.\n");
1126 * Create DMA tag for TxD.
1128 error = bus_dma_tag_create(sc->dma_parent_tag,
1129 4, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
1130 NULL, NULL, AE_TXD_BUFSIZE_DEFAULT, 1,
1131 AE_TXD_BUFSIZE_DEFAULT, 0, NULL, NULL,
1134 device_printf(sc->dev, "could not creare TxD DMA tag.\n");
1139 * Create DMA tag for TxS.
1141 error = bus_dma_tag_create(sc->dma_parent_tag,
1142 4, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
1143 NULL, NULL, AE_TXS_COUNT_DEFAULT * 4, 1,
1144 AE_TXS_COUNT_DEFAULT * 4, 0, NULL, NULL,
1147 device_printf(sc->dev, "could not creare TxS DMA tag.\n");
1152 * Create DMA tag for RxD.
1154 error = bus_dma_tag_create(sc->dma_parent_tag,
1155 128, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
1156 NULL, NULL, AE_RXD_COUNT_DEFAULT * 1536 + 120, 1,
1157 AE_RXD_COUNT_DEFAULT * 1536 + 120, 0, NULL, NULL,
1160 device_printf(sc->dev, "could not creare TxS DMA tag.\n");
1165 * Allocate TxD DMA memory.
1167 error = bus_dmamem_alloc(sc->dma_txd_tag, (void **)&sc->txd_base,
1168 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT,
1171 device_printf(sc->dev,
1172 "could not allocate DMA memory for TxD ring.\n");
1175 error = bus_dmamap_load(sc->dma_txd_tag, sc->dma_txd_map, sc->txd_base,
1176 AE_TXD_BUFSIZE_DEFAULT, ae_dmamap_cb, &busaddr, BUS_DMA_NOWAIT);
1177 if (error != 0 || busaddr == 0) {
1178 device_printf(sc->dev,
1179 "could not load DMA map for TxD ring.\n");
1182 sc->dma_txd_busaddr = busaddr;
1185 * Allocate TxS DMA memory.
1187 error = bus_dmamem_alloc(sc->dma_txs_tag, (void **)&sc->txs_base,
1188 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT,
1191 device_printf(sc->dev,
1192 "could not allocate DMA memory for TxS ring.\n");
1195 error = bus_dmamap_load(sc->dma_txs_tag, sc->dma_txs_map, sc->txs_base,
1196 AE_TXS_COUNT_DEFAULT * 4, ae_dmamap_cb, &busaddr, BUS_DMA_NOWAIT);
1197 if (error != 0 || busaddr == 0) {
1198 device_printf(sc->dev,
1199 "could not load DMA map for TxS ring.\n");
1202 sc->dma_txs_busaddr = busaddr;
1205 * Allocate RxD DMA memory.
1207 error = bus_dmamem_alloc(sc->dma_rxd_tag, (void **)&sc->rxd_base_dma,
1208 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT,
1211 device_printf(sc->dev,
1212 "could not allocate DMA memory for RxD ring.\n");
1215 error = bus_dmamap_load(sc->dma_rxd_tag, sc->dma_rxd_map,
1216 sc->rxd_base_dma, AE_RXD_COUNT_DEFAULT * 1536 + 120, ae_dmamap_cb,
1217 &busaddr, BUS_DMA_NOWAIT);
1218 if (error != 0 || busaddr == 0) {
1219 device_printf(sc->dev,
1220 "could not load DMA map for RxD ring.\n");
1223 sc->dma_rxd_busaddr = busaddr + 120;
1224 sc->rxd_base = (ae_rxd_t *)(sc->rxd_base_dma + 120);
1230 ae_dma_free(ae_softc_t *sc)
1233 if (sc->dma_txd_tag != NULL) {
1234 if (sc->dma_txd_map != NULL) {
1235 bus_dmamap_unload(sc->dma_txd_tag, sc->dma_txd_map);
1236 if (sc->txd_base != NULL)
1237 bus_dmamem_free(sc->dma_txd_tag, sc->txd_base,
1241 bus_dma_tag_destroy(sc->dma_txd_tag);
1242 sc->dma_txd_map = NULL;
1243 sc->dma_txd_tag = NULL;
1244 sc->txd_base = NULL;
1246 if (sc->dma_txs_tag != NULL) {
1247 if (sc->dma_txs_map != NULL) {
1248 bus_dmamap_unload(sc->dma_txs_tag, sc->dma_txs_map);
1249 if (sc->txs_base != NULL)
1250 bus_dmamem_free(sc->dma_txs_tag, sc->txs_base,
1254 bus_dma_tag_destroy(sc->dma_txs_tag);
1255 sc->dma_txs_map = NULL;
1256 sc->dma_txs_tag = NULL;
1257 sc->txs_base = NULL;
1259 if (sc->dma_rxd_tag != NULL) {
1260 if (sc->dma_rxd_map != NULL) {
1261 bus_dmamap_unload(sc->dma_rxd_tag, sc->dma_rxd_map);
1262 if (sc->rxd_base_dma != NULL)
1263 bus_dmamem_free(sc->dma_rxd_tag,
1264 sc->rxd_base_dma, sc->dma_rxd_map);
1267 bus_dma_tag_destroy(sc->dma_rxd_tag);
1268 sc->dma_rxd_map = NULL;
1269 sc->dma_rxd_tag = NULL;
1270 sc->rxd_base_dma = NULL;
1272 if (sc->dma_parent_tag != NULL) {
1273 bus_dma_tag_destroy(sc->dma_parent_tag);
1274 sc->dma_parent_tag = NULL;
1279 ae_shutdown(device_t dev)
1284 sc = device_get_softc(dev);
1285 KASSERT(sc != NULL, ("[ae: %d]: sc is NULL", __LINE__));
1287 error = ae_suspend(dev);
1289 ae_powersave_enable(sc);
1295 ae_powersave_disable(ae_softc_t *sc)
1301 AE_PHY_WRITE(sc, AE_PHY_DBG_ADDR, 0);
1302 val = AE_PHY_READ(sc, AE_PHY_DBG_DATA);
1303 if (val & AE_PHY_DBG_POWERSAVE) {
1304 val &= ~AE_PHY_DBG_POWERSAVE;
1305 AE_PHY_WRITE(sc, AE_PHY_DBG_DATA, val);
1311 ae_powersave_enable(ae_softc_t *sc)
1318 * XXX magic numbers.
1320 AE_PHY_WRITE(sc, AE_PHY_DBG_ADDR, 0);
1321 val = AE_PHY_READ(sc, AE_PHY_DBG_DATA);
1322 AE_PHY_WRITE(sc, AE_PHY_DBG_ADDR, val | 0x1000);
1323 AE_PHY_WRITE(sc, AE_PHY_DBG_ADDR, 2);
1324 AE_PHY_WRITE(sc, AE_PHY_DBG_DATA, 0x3000);
1325 AE_PHY_WRITE(sc, AE_PHY_DBG_ADDR, 3);
1326 AE_PHY_WRITE(sc, AE_PHY_DBG_DATA, 0);
1330 ae_pm_init(ae_softc_t *sc)
1335 struct mii_data *mii;
1341 if ((sc->flags & AE_FLAG_PMG) == 0) {
1342 /* Disable WOL entirely. */
1343 AE_WRITE_4(sc, AE_WOL_REG, 0);
1348 * Configure WOL if enabled.
1350 if ((ifp->if_capenable & IFCAP_WOL) != 0) {
1351 mii = device_get_softc(sc->miibus);
1353 if ((mii->mii_media_status & IFM_AVALID) != 0 &&
1354 (mii->mii_media_status & IFM_ACTIVE) != 0) {
1355 AE_WRITE_4(sc, AE_WOL_REG, AE_WOL_MAGIC | \
1361 val = AE_MAC_RX_EN | AE_MAC_CLK_PHY | \
1362 AE_MAC_TX_CRC_EN | AE_MAC_TX_AUTOPAD | \
1363 ((AE_HALFBUF_DEFAULT << AE_HALFBUF_SHIFT) & \
1364 AE_HALFBUF_MASK) | \
1365 ((AE_MAC_PREAMBLE_DEFAULT << \
1366 AE_MAC_PREAMBLE_SHIFT) & AE_MAC_PREAMBLE_MASK) | \
1367 AE_MAC_BCAST_EN | AE_MAC_MCAST_EN;
1368 if ((IFM_OPTIONS(mii->mii_media_active) & \
1370 val |= AE_MAC_FULL_DUPLEX;
1371 AE_WRITE_4(sc, AE_MAC_REG, val);
1373 } else { /* No link. */
1374 AE_WRITE_4(sc, AE_WOL_REG, AE_WOL_LNKCHG | \
1376 AE_WRITE_4(sc, AE_MAC_REG, 0);
1379 ae_powersave_enable(sc);
1383 * PCIE hacks. Magic numbers.
1385 val = AE_READ_4(sc, AE_PCIE_PHYMISC_REG);
1386 val |= AE_PCIE_PHYMISC_FORCE_RCV_DET;
1387 AE_WRITE_4(sc, AE_PCIE_PHYMISC_REG, val);
1388 val = AE_READ_4(sc, AE_PCIE_DLL_TX_CTRL_REG);
1389 val |= AE_PCIE_DLL_TX_CTRL_SEL_NOR_CLK;
1390 AE_WRITE_4(sc, AE_PCIE_DLL_TX_CTRL_REG, val);
1395 pci_find_extcap(sc->dev, PCIY_PMG, &pmc);
1396 pmstat = pci_read_config(sc->dev, pmc + PCIR_POWER_STATUS, 2);
1397 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE);
1398 if ((ifp->if_capenable & IFCAP_WOL) != 0)
1399 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
1400 pci_write_config(sc->dev, pmc + PCIR_POWER_STATUS, pmstat, 2);
1404 ae_suspend(device_t dev)
1408 sc = device_get_softc(dev);
1419 ae_resume(device_t dev)
1423 sc = device_get_softc(dev);
1424 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL", __LINE__));
1427 AE_READ_4(sc, AE_WOL_REG); /* Clear WOL status. */
1428 if ((sc->ifp->if_flags & IFF_UP) != 0)
1436 ae_tx_avail_size(ae_softc_t *sc)
1440 if (sc->txd_cur >= sc->txd_ack)
1441 avail = AE_TXD_BUFSIZE_DEFAULT - (sc->txd_cur - sc->txd_ack);
1443 avail = sc->txd_ack - sc->txd_cur;
1445 return (avail - 4); /* 4-byte header. */
1449 ae_encap(ae_softc_t *sc, struct mbuf **m_head)
1453 unsigned int to_end;
1459 len = m0->m_pkthdr.len;
1461 if ((sc->flags & AE_FLAG_TXAVAIL) == 0 ||
1462 ae_tx_avail_size(sc) < len) {
1464 if_printf(sc->ifp, "No free Tx available.\n");
1469 hdr = (ae_txd_t *)(sc->txd_base + sc->txd_cur);
1470 bzero(hdr, sizeof(*hdr));
1471 sc->txd_cur = (sc->txd_cur + 4) % AE_TXD_BUFSIZE_DEFAULT; /* Header
1473 to_end = AE_TXD_BUFSIZE_DEFAULT - sc->txd_cur; /* Space available to
1474 * the end of the ring
1476 if (to_end >= len) {
1477 m_copydata(m0, 0, len, (caddr_t)(sc->txd_base + sc->txd_cur));
1479 m_copydata(m0, 0, to_end, (caddr_t)(sc->txd_base +
1481 m_copydata(m0, to_end, len - to_end, (caddr_t)sc->txd_base);
1485 * Set TxD flags and parameters.
1487 if ((m0->m_flags & M_VLANTAG) != 0) {
1488 hdr->vlan = htole16(AE_TXD_VLAN(m0->m_pkthdr.ether_vtag));
1489 hdr->len = htole16(len | AE_TXD_INSERT_VTAG);
1491 hdr->len = htole16(len);
1495 * Set current TxD position and round up to a 4-byte boundary.
1497 sc->txd_cur = ((sc->txd_cur + len + 3) & ~3) % AE_TXD_BUFSIZE_DEFAULT;
1498 if (sc->txd_cur == sc->txd_ack)
1499 sc->flags &= ~AE_FLAG_TXAVAIL;
1501 if_printf(sc->ifp, "New txd_cur = %d.\n", sc->txd_cur);
1505 * Update TxS position and check if there are empty TxS available.
1507 sc->txs_base[sc->txs_cur].flags &= ~htole16(AE_TXS_UPDATE);
1508 sc->txs_cur = (sc->txs_cur + 1) % AE_TXS_COUNT_DEFAULT;
1509 if (sc->txs_cur == sc->txs_ack)
1510 sc->flags &= ~AE_FLAG_TXAVAIL;
1513 * Synchronize DMA memory.
1515 bus_dmamap_sync(sc->dma_txd_tag, sc->dma_txd_map, BUS_DMASYNC_PREREAD |
1516 BUS_DMASYNC_PREWRITE);
1517 bus_dmamap_sync(sc->dma_txs_tag, sc->dma_txs_map,
1518 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1524 ae_start(struct ifnet *ifp)
1532 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL", __LINE__));
1536 if_printf(ifp, "Start called.\n");
1539 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
1540 IFF_DRV_RUNNING || (sc->flags & AE_FLAG_LINK) == 0) {
1546 while (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) {
1547 IFQ_DRV_DEQUEUE(&ifp->if_snd, m0);
1549 break; /* Nothing to do. */
1551 error = ae_encap(sc, &m0);
1554 IFQ_DRV_PREPEND(&ifp->if_snd, m0);
1555 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1557 if_printf(ifp, "Setting OACTIVE.\n");
1565 /* Bounce a copy of the frame to BPF. */
1566 ETHER_BPF_MTAP(ifp, m0);
1571 if (count > 0) { /* Something was dequeued. */
1572 AE_WRITE_2(sc, AE_MB_TXD_IDX_REG, sc->txd_cur / 4);
1573 sc->wd_timer = AE_TX_TIMEOUT; /* Load watchdog. */
1575 if_printf(ifp, "%d packets dequeued.\n", count);
1576 if_printf(ifp, "Tx pos now is %d.\n", sc->txd_cur);
1583 ae_link_task(void *arg, int pending)
1586 struct mii_data *mii;
1590 sc = (ae_softc_t *)arg;
1591 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL", __LINE__));
1595 mii = device_get_softc(sc->miibus);
1596 if (mii == NULL || ifp == NULL ||
1597 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
1598 AE_UNLOCK(sc); /* XXX: could happen? */
1602 sc->flags &= ~AE_FLAG_LINK;
1603 if ((mii->mii_media_status & (IFM_AVALID | IFM_ACTIVE)) ==
1604 (IFM_AVALID | IFM_ACTIVE)) {
1605 switch(IFM_SUBTYPE(mii->mii_media_active)) {
1608 sc->flags |= AE_FLAG_LINK;
1621 if ((sc->flags & AE_FLAG_LINK) != 0) {
1625 * Restart DMA engines.
1627 AE_WRITE_1(sc, AE_DMAREAD_REG, AE_DMAREAD_EN);
1628 AE_WRITE_1(sc, AE_DMAWRITE_REG, AE_DMAWRITE_EN);
1631 * Enable Rx and Tx MACs.
1633 val = AE_READ_4(sc, AE_MAC_REG);
1634 val |= AE_MAC_TX_EN | AE_MAC_RX_EN;
1635 AE_WRITE_4(sc, AE_MAC_REG, val);
1641 ae_stop_rxmac(ae_softc_t *sc)
1649 * Stop Rx MAC engine.
1651 val = AE_READ_4(sc, AE_MAC_REG);
1652 if ((val & AE_MAC_RX_EN) != 0) {
1653 val &= ~AE_MAC_RX_EN;
1654 AE_WRITE_4(sc, AE_MAC_REG, val);
1658 * Stop Rx DMA engine.
1660 if (AE_READ_1(sc, AE_DMAWRITE_REG) == AE_DMAWRITE_EN)
1661 AE_WRITE_1(sc, AE_DMAWRITE_REG, 0);
1664 * Wait for IDLE state.
1666 for (i = 0; i < AE_IDLE_TIMEOUT; i--) {
1667 val = AE_READ_4(sc, AE_IDLE_REG);
1668 if ((val & (AE_IDLE_RXMAC | AE_IDLE_DMAWRITE)) == 0)
1672 if (i == AE_IDLE_TIMEOUT)
1673 device_printf(sc->dev, "timed out while stopping Rx MAC.\n");
1677 ae_stop_txmac(ae_softc_t *sc)
1685 * Stop Tx MAC engine.
1687 val = AE_READ_4(sc, AE_MAC_REG);
1688 if ((val & AE_MAC_TX_EN) != 0) {
1689 val &= ~AE_MAC_TX_EN;
1690 AE_WRITE_4(sc, AE_MAC_REG, val);
1694 * Stop Tx DMA engine.
1696 if (AE_READ_1(sc, AE_DMAREAD_REG) == AE_DMAREAD_EN)
1697 AE_WRITE_1(sc, AE_DMAREAD_REG, 0);
1700 * Wait for IDLE state.
1702 for (i = 0; i < AE_IDLE_TIMEOUT; i--) {
1703 val = AE_READ_4(sc, AE_IDLE_REG);
1704 if ((val & (AE_IDLE_TXMAC | AE_IDLE_DMAREAD)) == 0)
1708 if (i == AE_IDLE_TIMEOUT)
1709 device_printf(sc->dev, "timed out while stopping Tx MAC.\n");
1713 ae_tx_task(void *arg, int pending)
1717 ifp = (struct ifnet *)arg;
1722 ae_mac_config(ae_softc_t *sc)
1724 struct mii_data *mii;
1729 mii = device_get_softc(sc->miibus);
1730 val = AE_READ_4(sc, AE_MAC_REG);
1731 val &= ~AE_MAC_FULL_DUPLEX;
1732 /* XXX disable AE_MAC_TX_FLOW_EN? */
1734 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0)
1735 val |= AE_MAC_FULL_DUPLEX;
1737 AE_WRITE_4(sc, AE_MAC_REG, val);
1746 sc = (ae_softc_t *)arg;
1747 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL", __LINE__));
1749 val = AE_READ_4(sc, AE_ISR_REG);
1750 if (val == 0 || (val & AE_IMR_DEFAULT) == 0)
1751 return (FILTER_STRAY);
1753 /* Disable interrupts. */
1754 AE_WRITE_4(sc, AE_ISR_REG, AE_ISR_DISABLE);
1756 /* Schedule interrupt processing. */
1757 taskqueue_enqueue(sc->tq, &sc->int_task);
1759 return (FILTER_HANDLED);
1763 ae_int_task(void *arg, int pending)
1769 sc = (ae_softc_t *)arg;
1775 val = AE_READ_4(sc, AE_ISR_REG); /* Read interrupt status. */
1778 * Clear interrupts and disable them.
1780 AE_WRITE_4(sc, AE_ISR_REG, val | AE_ISR_DISABLE);
1783 if_printf(ifp, "Interrupt received: 0x%08x\n", val);
1786 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
1787 if ((val & (AE_ISR_DMAR_TIMEOUT | AE_ISR_DMAW_TIMEOUT |
1788 AE_ISR_PHY_LINKDOWN)) != 0) {
1791 if ((val & AE_ISR_TX_EVENT) != 0)
1793 if ((val & AE_ISR_RX_EVENT) != 0)
1798 * Re-enable interrupts.
1800 AE_WRITE_4(sc, AE_ISR_REG, 0);
1806 ae_tx_intr(ae_softc_t *sc)
1818 if_printf(ifp, "Tx interrupt occuried.\n");
1822 * Syncronize DMA buffers.
1824 bus_dmamap_sync(sc->dma_txd_tag, sc->dma_txd_map,
1825 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1826 bus_dmamap_sync(sc->dma_txs_tag, sc->dma_txs_map,
1827 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1830 txs = sc->txs_base + sc->txs_ack;
1831 flags = le16toh(txs->flags);
1832 if ((flags & AE_TXS_UPDATE) == 0)
1834 txs->flags = htole16(flags & ~AE_TXS_UPDATE);
1836 ae_update_stats_tx(flags, &sc->stats);
1839 * Update TxS position.
1841 sc->txs_ack = (sc->txs_ack + 1) % AE_TXS_COUNT_DEFAULT;
1842 sc->flags |= AE_FLAG_TXAVAIL;
1844 txd = (ae_txd_t *)(sc->txd_base + sc->txd_ack);
1845 if (txs->len != txd->len)
1846 device_printf(sc->dev, "Size mismatch: TxS:%d TxD:%d\n",
1847 le16toh(txs->len), le16toh(txd->len));
1850 * Move txd ack and align on 4-byte boundary.
1852 sc->txd_ack = ((sc->txd_ack + le16toh(txd->len) + 4 + 3) & ~3) %
1853 AE_TXD_BUFSIZE_DEFAULT;
1855 if ((flags & AE_TXS_SUCCESS) != 0)
1862 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1865 if (sc->tx_inproc < 0) {
1866 if_printf(ifp, "Received stray Tx interrupt(s).\n");
1870 if (sc->tx_inproc == 0)
1871 sc->wd_timer = 0; /* Unarm watchdog. */
1873 if ((sc->flags & AE_FLAG_TXAVAIL) != 0) {
1874 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1875 taskqueue_enqueue(sc->tq, &sc->tx_task);
1879 * Syncronize DMA buffers.
1881 bus_dmamap_sync(sc->dma_txd_tag, sc->dma_txd_map,
1882 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1883 bus_dmamap_sync(sc->dma_txs_tag, sc->dma_txs_map,
1884 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1888 ae_rxeof(ae_softc_t *sc, ae_rxd_t *rxd)
1898 flags = le16toh(rxd->flags);
1901 if_printf(ifp, "Rx interrupt occuried.\n");
1903 size = le16toh(rxd->len) - ETHER_CRC_LEN;
1904 if (size < (ETHER_MIN_LEN - ETHER_CRC_LEN - ETHER_VLAN_ENCAP_LEN)) {
1905 if_printf(ifp, "Runt frame received.");
1909 m = m_devget(&rxd->data[0], size, ETHER_ALIGN, ifp, NULL);
1913 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0 &&
1914 (flags & AE_RXD_HAS_VLAN) != 0) {
1915 m->m_pkthdr.ether_vtag = AE_RXD_VLAN(le16toh(rxd->vlan));
1916 m->m_flags |= M_VLANTAG;
1923 (*ifp->if_input)(ifp, m);
1930 ae_rx_intr(ae_softc_t *sc)
1937 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL!", __LINE__));
1944 * Syncronize DMA buffers.
1946 bus_dmamap_sync(sc->dma_rxd_tag, sc->dma_rxd_map,
1947 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1950 rxd = (ae_rxd_t *)(sc->rxd_base + sc->rxd_cur);
1951 flags = le16toh(rxd->flags);
1952 if ((flags & AE_RXD_UPDATE) == 0)
1954 rxd->flags = htole16(flags & ~AE_RXD_UPDATE);
1956 ae_update_stats_rx(flags, &sc->stats);
1959 * Update position index.
1961 sc->rxd_cur = (sc->rxd_cur + 1) % AE_RXD_COUNT_DEFAULT;
1963 if ((flags & AE_RXD_SUCCESS) == 0) {
1967 error = ae_rxeof(sc, rxd);
1979 AE_WRITE_2(sc, AE_MB_RXD_IDX_REG, sc->rxd_cur);
1983 ae_watchdog(ae_softc_t *sc)
1987 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL!", __LINE__));
1991 if (sc->wd_timer == 0 || --sc->wd_timer != 0)
1992 return; /* Noting to do. */
1994 if ((sc->flags & AE_FLAG_LINK) == 0)
1995 if_printf(ifp, "watchdog timeout (missed link).\n");
1997 if_printf(ifp, "watchdog timeout - resetting.\n");
2001 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
2002 taskqueue_enqueue(sc->tq, &sc->tx_task);
2009 struct mii_data *mii;
2011 sc = (ae_softc_t *)arg;
2012 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL!", __LINE__));
2015 mii = device_get_softc(sc->miibus);
2017 ae_watchdog(sc); /* Watchdog check. */
2018 callout_reset(&sc->tick_ch, hz, ae_tick, sc);
2022 ae_rxvlan(ae_softc_t *sc)
2029 val = AE_READ_4(sc, AE_MAC_REG);
2030 val &= ~AE_MAC_RMVLAN_EN;
2031 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0)
2032 val |= AE_MAC_RMVLAN_EN;
2033 AE_WRITE_4(sc, AE_MAC_REG, val);
2037 ae_rxfilter(ae_softc_t *sc)
2040 struct ifmultiaddr *ifma;
2045 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL!", __LINE__));
2051 rxcfg = AE_READ_4(sc, AE_MAC_REG);
2052 rxcfg &= ~(AE_MAC_MCAST_EN | AE_MAC_BCAST_EN | AE_MAC_PROMISC_EN);
2054 if ((ifp->if_flags & IFF_BROADCAST) != 0)
2055 rxcfg |= AE_MAC_BCAST_EN;
2056 if ((ifp->if_flags & IFF_PROMISC) != 0)
2057 rxcfg |= AE_MAC_PROMISC_EN;
2058 if ((ifp->if_flags & IFF_ALLMULTI) != 0)
2059 rxcfg |= AE_MAC_MCAST_EN;
2062 * Wipe old settings.
2064 AE_WRITE_4(sc, AE_REG_MHT0, 0);
2065 AE_WRITE_4(sc, AE_REG_MHT1, 0);
2066 if ((ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) != 0) {
2067 AE_WRITE_4(sc, AE_REG_MHT0, 0xffffffff);
2068 AE_WRITE_4(sc, AE_REG_MHT1, 0xffffffff);
2069 AE_WRITE_4(sc, AE_MAC_REG, rxcfg);
2074 * Load multicast tables.
2076 bzero(mchash, sizeof(mchash));
2077 if_maddr_rlock(ifp);
2078 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
2079 if (ifma->ifma_addr->sa_family != AF_LINK)
2081 crc = ether_crc32_be(LLADDR((struct sockaddr_dl *)
2082 ifma->ifma_addr), ETHER_ADDR_LEN);
2083 mchash[crc >> 31] |= 1 << ((crc >> 26) & 0x1f);
2085 if_maddr_runlock(ifp);
2086 AE_WRITE_4(sc, AE_REG_MHT0, mchash[0]);
2087 AE_WRITE_4(sc, AE_REG_MHT1, mchash[1]);
2088 AE_WRITE_4(sc, AE_MAC_REG, rxcfg);
2092 ae_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
2094 struct ae_softc *sc;
2096 struct mii_data *mii;
2100 ifr = (struct ifreq *)data;
2105 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > ETHERMTU)
2107 else if (ifp->if_mtu != ifr->ifr_mtu) {
2109 ifp->if_mtu = ifr->ifr_mtu;
2110 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
2117 if ((ifp->if_flags & IFF_UP) != 0) {
2118 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
2119 if (((ifp->if_flags ^ sc->if_flags)
2120 & (IFF_PROMISC | IFF_ALLMULTI)) != 0)
2123 if ((sc->flags & AE_FLAG_DETACH) == 0)
2127 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
2130 sc->if_flags = ifp->if_flags;
2136 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
2142 mii = device_get_softc(sc->miibus);
2143 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd);
2147 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
2148 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 &&
2149 (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) != 0) {
2150 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
2153 VLAN_CAPABILITIES(ifp);
2157 error = ether_ioctl(ifp, cmd, data);
2164 ae_stop(ae_softc_t *sc)
2172 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
2173 sc->flags &= ~AE_FLAG_LINK;
2174 sc->wd_timer = 0; /* Cancel watchdog. */
2175 callout_stop(&sc->tick_ch);
2178 * Clear and disable interrupts.
2180 AE_WRITE_4(sc, AE_IMR_REG, 0);
2181 AE_WRITE_4(sc, AE_ISR_REG, 0xffffffff);
2192 AE_WRITE_1(sc, AE_DMAREAD_REG, ~AE_DMAREAD_EN);
2193 AE_WRITE_1(sc, AE_DMAWRITE_REG, ~AE_DMAWRITE_EN);
2196 * Wait for everything to enter idle state.
2198 for (i = 0; i < AE_IDLE_TIMEOUT; i++) {
2199 if (AE_READ_4(sc, AE_IDLE_REG) == 0)
2203 if (i == AE_IDLE_TIMEOUT)
2204 device_printf(sc->dev, "could not enter idle state in stop.\n");
2208 ae_update_stats_tx(uint16_t flags, ae_stats_t *stats)
2211 if ((flags & AE_TXS_BCAST) != 0)
2213 if ((flags & AE_TXS_MCAST) != 0)
2215 if ((flags & AE_TXS_PAUSE) != 0)
2217 if ((flags & AE_TXS_CTRL) != 0)
2219 if ((flags & AE_TXS_DEFER) != 0)
2221 if ((flags & AE_TXS_EXCDEFER) != 0)
2222 stats->tx_excdefer++;
2223 if ((flags & AE_TXS_SINGLECOL) != 0)
2224 stats->tx_singlecol++;
2225 if ((flags & AE_TXS_MULTICOL) != 0)
2226 stats->tx_multicol++;
2227 if ((flags & AE_TXS_LATECOL) != 0)
2228 stats->tx_latecol++;
2229 if ((flags & AE_TXS_ABORTCOL) != 0)
2230 stats->tx_abortcol++;
2231 if ((flags & AE_TXS_UNDERRUN) != 0)
2232 stats->tx_underrun++;
2236 ae_update_stats_rx(uint16_t flags, ae_stats_t *stats)
2239 if ((flags & AE_RXD_BCAST) != 0)
2241 if ((flags & AE_RXD_MCAST) != 0)
2243 if ((flags & AE_RXD_PAUSE) != 0)
2245 if ((flags & AE_RXD_CTRL) != 0)
2247 if ((flags & AE_RXD_CRCERR) != 0)
2249 if ((flags & AE_RXD_CODEERR) != 0)
2250 stats->rx_codeerr++;
2251 if ((flags & AE_RXD_RUNT) != 0)
2253 if ((flags & AE_RXD_FRAG) != 0)
2255 if ((flags & AE_RXD_TRUNC) != 0)
2257 if ((flags & AE_RXD_ALIGN) != 0)