sys/dev/age/if_age.c

   1 /*-
   2  * Copyright (c) 2008, Pyun YongHyeon <yongari@FreeBSD.org>
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  * 1. Redistributions of source code must retain the above copyright
   9  *    notice unmodified, this list of conditions, and the following
  10  *    disclaimer.
  11  * 2. Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the distribution.
  14  *
  15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  16  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  17  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  18  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  19  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  20  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  21  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  22  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  23  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  24  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  25  * SUCH DAMAGE.
  26  */
  27
  28 /* Driver for Attansic Technology Corp. L1 Gigabit Ethernet. */
  29
  30 #include <sys/cdefs.h>
  31 __FBSDID("$FreeBSD$");
  32
  33 #include <sys/param.h>
  34 #include <sys/systm.h>
  35 #include <sys/bus.h>
  36 #include <sys/endian.h>
  37 #include <sys/kernel.h>
  38 #include <sys/malloc.h>
  39 #include <sys/mbuf.h>
  40 #include <sys/rman.h>
  41 #include <sys/module.h>
  42 #include <sys/queue.h>
  43 #include <sys/socket.h>
  44 #include <sys/sockio.h>
  45 #include <sys/sysctl.h>
  46 #include <sys/taskqueue.h>
  47
  48 #include <net/bpf.h>
  49 #include <net/if.h>
  50 #include <net/if_arp.h>
  51 #include <net/ethernet.h>
  52 #include <net/if_dl.h>
  53 #include <net/if_media.h>
  54 #include <net/if_types.h>
  55 #include <net/if_vlan_var.h>
  56
  57 #include <netinet/in.h>
  58 #include <netinet/in_systm.h>
  59 #include <netinet/ip.h>
  60 #include <netinet/tcp.h>
  61
  62 #include <dev/mii/mii.h>
  63 #include <dev/mii/miivar.h>
  64
  65 #include <dev/pci/pcireg.h>
  66 #include <dev/pci/pcivar.h>
  67
  68 #include <machine/bus.h>
  69 #include <machine/in_cksum.h>
  70
  71 #include <dev/age/if_agereg.h>
  72 #include <dev/age/if_agevar.h>
  73
  74 /* "device miibus" required.  See GENERIC if you get errors here. */
  75 #include "miibus_if.h"
  76
  77 #define AGE_CSUM_FEATURES       (CSUM_TCP | CSUM_UDP)
  78
  79 MODULE_DEPEND(age, pci, 1, 1, 1);
  80 MODULE_DEPEND(age, ether, 1, 1, 1);
  81 MODULE_DEPEND(age, miibus, 1, 1, 1);
  82
  83 /* Tunables. */
  84 static int msi_disable = 0;
  85 static int msix_disable = 0;
  86 TUNABLE_INT("hw.age.msi_disable", &msi_disable);
  87 TUNABLE_INT("hw.age.msix_disable", &msix_disable);
  88
  89 /*
  90  * Devices supported by this driver.
  91  */
  92 static struct age_dev {
  93         uint16_t        age_vendorid;
  94         uint16_t        age_deviceid;
  95         const char      *age_name;
  96 } age_devs[] = {
  97         { VENDORID_ATTANSIC, DEVICEID_ATTANSIC_L1,
  98             "Attansic Technology Corp, L1 Gigabit Ethernet" },
  99 };
 100
 101 static int age_miibus_readreg(device_t, int, int);
 102 static int age_miibus_writereg(device_t, int, int, int);
 103 static void age_miibus_statchg(device_t);
 104 static void age_mediastatus(struct ifnet *, struct ifmediareq *);
 105 static int age_mediachange(struct ifnet *);
 106 static int age_probe(device_t);
 107 static void age_get_macaddr(struct age_softc *);
 108 static void age_phy_reset(struct age_softc *);
 109 static int age_attach(device_t);
 110 static int age_detach(device_t);
 111 static void age_sysctl_node(struct age_softc *);
 112 static void age_dmamap_cb(void *, bus_dma_segment_t *, int, int);
 113 static int age_check_boundary(struct age_softc *);
 114 static int age_dma_alloc(struct age_softc *);
 115 static void age_dma_free(struct age_softc *);
 116 static int age_shutdown(device_t);
 117 static void age_setwol(struct age_softc *);
 118 static int age_suspend(device_t);
 119 static int age_resume(device_t);
 120 static int age_encap(struct age_softc *, struct mbuf **);
 121 static void age_tx_task(void *, int);
 122 static void age_start(struct ifnet *);
 123 static void age_watchdog(struct age_softc *);
 124 static int age_ioctl(struct ifnet *, u_long, caddr_t);
 125 static void age_mac_config(struct age_softc *);
 126 static void age_link_task(void *, int);
 127 static void age_stats_update(struct age_softc *);
 128 static int age_intr(void *);
 129 static void age_int_task(void *, int);
 130 static void age_txintr(struct age_softc *, int);
 131 static void age_rxeof(struct age_softc *sc, struct rx_rdesc *);
 132 static int age_rxintr(struct age_softc *, int, int);
 133 static void age_tick(void *);
 134 static void age_reset(struct age_softc *);
 135 static void age_init(void *);
 136 static void age_init_locked(struct age_softc *);
 137 static void age_stop(struct age_softc *);
 138 static void age_stop_txmac(struct age_softc *);
 139 static void age_stop_rxmac(struct age_softc *);
 140 static void age_init_tx_ring(struct age_softc *);
 141 static int age_init_rx_ring(struct age_softc *);
 142 static void age_init_rr_ring(struct age_softc *);
 143 static void age_init_cmb_block(struct age_softc *);
 144 static void age_init_smb_block(struct age_softc *);
 145 static int age_newbuf(struct age_softc *, struct age_rxdesc *);
 146 static void age_rxvlan(struct age_softc *);
 147 static void age_rxfilter(struct age_softc *);
 148 static int sysctl_age_stats(SYSCTL_HANDLER_ARGS);
 149 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int);
 150 static int sysctl_hw_age_proc_limit(SYSCTL_HANDLER_ARGS);
 151 static int sysctl_hw_age_int_mod(SYSCTL_HANDLER_ARGS);
 152
 153
 154 static device_method_t age_methods[] = {
 155         /* Device interface. */
 156         DEVMETHOD(device_probe,         age_probe),
 157         DEVMETHOD(device_attach,        age_attach),
 158         DEVMETHOD(device_detach,        age_detach),
 159         DEVMETHOD(device_shutdown,      age_shutdown),
 160         DEVMETHOD(device_suspend,       age_suspend),
 161         DEVMETHOD(device_resume,        age_resume),
 162
 163         /* MII interface. */
 164         DEVMETHOD(miibus_readreg,       age_miibus_readreg),
 165         DEVMETHOD(miibus_writereg,      age_miibus_writereg),
 166         DEVMETHOD(miibus_statchg,       age_miibus_statchg),
 167
 168         { NULL, NULL }
 169 };
 170
 171 static driver_t age_driver = {
 172         "age",
 173         age_methods,
 174         sizeof(struct age_softc)
 175 };
 176
 177 static devclass_t age_devclass;
 178
 179 DRIVER_MODULE(age, pci, age_driver, age_devclass, 0, 0);
 180 DRIVER_MODULE(miibus, age, miibus_driver, miibus_devclass, 0, 0);
 181
 182 static struct resource_spec age_res_spec_mem[] = {
 183         { SYS_RES_MEMORY,       PCIR_BAR(0),    RF_ACTIVE },
 184         { -1,                   0,              0 }
 185 };
 186
 187 static struct resource_spec age_irq_spec_legacy[] = {
 188         { SYS_RES_IRQ,          0,              RF_ACTIVE | RF_SHAREABLE },
 189         { -1,                   0,              0 }
 190 };
 191
 192 static struct resource_spec age_irq_spec_msi[] = {
 193         { SYS_RES_IRQ,          1,              RF_ACTIVE },
 194         { -1,                   0,              0 }
 195 };
 196
 197 static struct resource_spec age_irq_spec_msix[] = {
 198         { SYS_RES_IRQ,          1,              RF_ACTIVE },
 199         { -1,                   0,              0 }
 200 };
 201
 202 /*
 203  *      Read a PHY register on the MII of the L1.
 204  */
 205 static int
 206 age_miibus_readreg(device_t dev, int phy, int reg)
 207 {
 208         struct age_softc *sc;
 209         uint32_t v;
 210         int i;
 211
 212         sc = device_get_softc(dev);
 213         if (phy != sc->age_phyaddr)
 214                 return (0);
 215
 216         CSR_WRITE_4(sc, AGE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ |
 217             MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg));
 218         for (i = AGE_PHY_TIMEOUT; i > 0; i--) {
 219                 DELAY(1);
 220                 v = CSR_READ_4(sc, AGE_MDIO);
 221                 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0)
 222                         break;
 223         }
 224
 225         if (i == 0) {
 226                 device_printf(sc->age_dev, "phy read timeout : %d\n", reg);
 227                 return (0);
 228         }
 229
 230         return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT);
 231 }
 232
 233 /*
 234  *      Write a PHY register on the MII of the L1.
 235  */
 236 static int
 237 age_miibus_writereg(device_t dev, int phy, int reg, int val)
 238 {
 239         struct age_softc *sc;
 240         uint32_t v;
 241         int i;
 242
 243         sc = device_get_softc(dev);
 244         if (phy != sc->age_phyaddr)
 245                 return (0);
 246
 247         CSR_WRITE_4(sc, AGE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE |
 248             (val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT |
 249             MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg));
 250         for (i = AGE_PHY_TIMEOUT; i > 0; i--) {
 251                 DELAY(1);
 252                 v = CSR_READ_4(sc, AGE_MDIO);
 253                 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0)
 254                         break;
 255         }
 256
 257         if (i == 0)
 258                 device_printf(sc->age_dev, "phy write timeout : %d\n", reg);
 259
 260         return (0);
 261 }
 262
 263 /*
 264  *      Callback from MII layer when media changes.
 265  */
 266 static void
 267 age_miibus_statchg(device_t dev)
 268 {
 269         struct age_softc *sc;
 270
 271         sc = device_get_softc(dev);
 272         taskqueue_enqueue(taskqueue_swi, &sc->age_link_task);
 273 }
 274
 275 /*
 276  *      Get the current interface media status.
 277  */
 278 static void
 279 age_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr)
 280 {
 281         struct age_softc *sc;
 282         struct mii_data *mii;
 283
 284         sc = ifp->if_softc;
 285         AGE_LOCK(sc);
 286         mii = device_get_softc(sc->age_miibus);
 287
 288         mii_pollstat(mii);
 289         AGE_UNLOCK(sc);
 290         ifmr->ifm_status = mii->mii_media_status;
 291         ifmr->ifm_active = mii->mii_media_active;
 292 }
 293
 294 /*
 295  *      Set hardware to newly-selected media.
 296  */
 297 static int
 298 age_mediachange(struct ifnet *ifp)
 299 {
 300         struct age_softc *sc;
 301         struct mii_data *mii;
 302         struct mii_softc *miisc;
 303         int error;
 304
 305         sc = ifp->if_softc;
 306         AGE_LOCK(sc);
 307         mii = device_get_softc(sc->age_miibus);
 308         if (mii->mii_instance != 0) {
 309                 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
 310                         mii_phy_reset(miisc);
 311         }
 312         error = mii_mediachg(mii);
 313         AGE_UNLOCK(sc);
 314
 315         return (error);
 316 }
 317
 318 static int
 319 age_probe(device_t dev)
 320 {
 321         struct age_dev *sp;
 322         int i;
 323         uint16_t vendor, devid;
 324
 325         vendor = pci_get_vendor(dev);
 326         devid = pci_get_device(dev);
 327         sp = age_devs;
 328         for (i = 0; i < sizeof(age_devs) / sizeof(age_devs[0]);
 329             i++, sp++) {
 330                 if (vendor == sp->age_vendorid &&
 331                     devid == sp->age_deviceid) {
 332                         device_set_desc(dev, sp->age_name);
 333                         return (BUS_PROBE_DEFAULT);
 334                 }
 335         }
 336
 337         return (ENXIO);
 338 }
 339
 340 static void
 341 age_get_macaddr(struct age_softc *sc)
 342 {
 343         uint32_t ea[2], reg;
 344         int i, vpdc;
 345
 346         reg = CSR_READ_4(sc, AGE_SPI_CTRL);
 347         if ((reg & SPI_VPD_ENB) != 0) {
 348                 /* Get VPD stored in TWSI EEPROM. */
 349                 reg &= ~SPI_VPD_ENB;
 350                 CSR_WRITE_4(sc, AGE_SPI_CTRL, reg);
 351         }
 352
 353         if (pci_find_extcap(sc->age_dev, PCIY_VPD, &vpdc) == 0) {
 354                 /*
 355                  * PCI VPD capability found, let TWSI reload EEPROM.
 356                  * This will set ethernet address of controller.
 357                  */
 358                 CSR_WRITE_4(sc, AGE_TWSI_CTRL, CSR_READ_4(sc, AGE_TWSI_CTRL) |
 359                     TWSI_CTRL_SW_LD_START);
 360                 for (i = 100; i > 0; i--) {
 361                         DELAY(1000);
 362                         reg = CSR_READ_4(sc, AGE_TWSI_CTRL);
 363                         if ((reg & TWSI_CTRL_SW_LD_START) == 0)
 364                                 break;
 365                 }
 366                 if (i == 0)
 367                         device_printf(sc->age_dev,
 368                             "reloading EEPROM timeout!\n");
 369         } else {
 370                 if (bootverbose)
 371                         device_printf(sc->age_dev,
 372                             "PCI VPD capability not found!\n");
 373         }
 374
 375         ea[0] = CSR_READ_4(sc, AGE_PAR0);
 376         ea[1] = CSR_READ_4(sc, AGE_PAR1);
 377         sc->age_eaddr[0] = (ea[1] >> 8) & 0xFF;
 378         sc->age_eaddr[1] = (ea[1] >> 0) & 0xFF;
 379         sc->age_eaddr[2] = (ea[0] >> 24) & 0xFF;
 380         sc->age_eaddr[3] = (ea[0] >> 16) & 0xFF;
 381         sc->age_eaddr[4] = (ea[0] >> 8) & 0xFF;
 382         sc->age_eaddr[5] = (ea[0] >> 0) & 0xFF;
 383 }
 384
 385 static void
 386 age_phy_reset(struct age_softc *sc)
 387 {
 388         uint16_t reg, pn;
 389         int i, linkup;
 390
 391         /* Reset PHY. */
 392         CSR_WRITE_4(sc, AGE_GPHY_CTRL, GPHY_CTRL_RST);
 393         DELAY(2000);
 394         CSR_WRITE_4(sc, AGE_GPHY_CTRL, GPHY_CTRL_CLR);
 395         DELAY(2000);
 396
 397 #define ATPHY_DBG_ADDR          0x1D
 398 #define ATPHY_DBG_DATA          0x1E
 399 #define ATPHY_CDTC              0x16
 400 #define PHY_CDTC_ENB            0x0001
 401 #define PHY_CDTC_POFF           8
 402 #define ATPHY_CDTS              0x1C
 403 #define PHY_CDTS_STAT_OK        0x0000
 404 #define PHY_CDTS_STAT_SHORT     0x0100
 405 #define PHY_CDTS_STAT_OPEN      0x0200
 406 #define PHY_CDTS_STAT_INVAL     0x0300
 407 #define PHY_CDTS_STAT_MASK      0x0300
 408
 409         /* Check power saving mode. Magic from Linux. */
 410         age_miibus_writereg(sc->age_dev, sc->age_phyaddr, MII_BMCR, BMCR_RESET);
 411         for (linkup = 0, pn = 0; pn < 4; pn++) {
 412                 age_miibus_writereg(sc->age_dev, sc->age_phyaddr, ATPHY_CDTC,
 413                     (pn << PHY_CDTC_POFF) | PHY_CDTC_ENB);
 414                 for (i = 200; i > 0; i--) {
 415                         DELAY(1000);
 416                         reg = age_miibus_readreg(sc->age_dev, sc->age_phyaddr,
 417                             ATPHY_CDTC);
 418                         if ((reg & PHY_CDTC_ENB) == 0)
 419                                 break;
 420                 }
 421                 DELAY(1000);
 422                 reg = age_miibus_readreg(sc->age_dev, sc->age_phyaddr,
 423                     ATPHY_CDTS);
 424                 if ((reg & PHY_CDTS_STAT_MASK) != PHY_CDTS_STAT_OPEN) {
 425                         linkup++;
 426                         break;
 427                 }
 428         }
 429         age_miibus_writereg(sc->age_dev, sc->age_phyaddr, MII_BMCR,
 430             BMCR_RESET | BMCR_AUTOEN | BMCR_STARTNEG);
 431         if (linkup == 0) {
 432                 age_miibus_writereg(sc->age_dev, sc->age_phyaddr,
 433                     ATPHY_DBG_ADDR, 0);
 434                 age_miibus_writereg(sc->age_dev, sc->age_phyaddr,
 435                     ATPHY_DBG_DATA, 0x124E);
 436                 age_miibus_writereg(sc->age_dev, sc->age_phyaddr,
 437                     ATPHY_DBG_ADDR, 1);
 438                 reg = age_miibus_readreg(sc->age_dev, sc->age_phyaddr,
 439                     ATPHY_DBG_DATA);
 440                 age_miibus_writereg(sc->age_dev, sc->age_phyaddr,
 441                     ATPHY_DBG_DATA, reg | 0x03);
 442                 /* XXX */
 443                 DELAY(1500 * 1000);
 444                 age_miibus_writereg(sc->age_dev, sc->age_phyaddr,
 445                     ATPHY_DBG_ADDR, 0);
 446                 age_miibus_writereg(sc->age_dev, sc->age_phyaddr,
 447                     ATPHY_DBG_DATA, 0x024E);
 448     }
 449
 450 #undef  ATPHY_DBG_ADDR
 451 #undef  ATPHY_DBG_DATA
 452 #undef  ATPHY_CDTC
 453 #undef  PHY_CDTC_ENB
 454 #undef  PHY_CDTC_POFF
 455 #undef  ATPHY_CDTS
 456 #undef  PHY_CDTS_STAT_OK
 457 #undef  PHY_CDTS_STAT_SHORT
 458 #undef  PHY_CDTS_STAT_OPEN
 459 #undef  PHY_CDTS_STAT_INVAL
 460 #undef  PHY_CDTS_STAT_MASK
 461 }
 462
 463 static int
 464 age_attach(device_t dev)
 465 {
 466         struct age_softc *sc;
 467         struct ifnet *ifp;
 468         uint16_t burst;
 469         int error, i, msic, msixc, pmc;
 470
 471         error = 0;
 472         sc = device_get_softc(dev);
 473         sc->age_dev = dev;
 474
 475         mtx_init(&sc->age_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
 476             MTX_DEF);
 477         callout_init_mtx(&sc->age_tick_ch, &sc->age_mtx, 0);
 478         TASK_INIT(&sc->age_int_task, 0, age_int_task, sc);
 479         TASK_INIT(&sc->age_link_task, 0, age_link_task, sc);
 480
 481         /* Map the device. */
 482         pci_enable_busmaster(dev);
 483         sc->age_res_spec = age_res_spec_mem;
 484         sc->age_irq_spec = age_irq_spec_legacy;
 485         error = bus_alloc_resources(dev, sc->age_res_spec, sc->age_res);
 486         if (error != 0) {
 487                 device_printf(dev, "cannot allocate memory resources.\n");
 488                 goto fail;
 489         }
 490
 491         /* Set PHY address. */
 492         sc->age_phyaddr = AGE_PHY_ADDR;
 493
 494         /* Reset PHY. */
 495         age_phy_reset(sc);
 496
 497         /* Reset the ethernet controller. */
 498         age_reset(sc);
 499
 500         /* Get PCI and chip id/revision. */
 501         sc->age_rev = pci_get_revid(dev);
 502         sc->age_chip_rev = CSR_READ_4(sc, AGE_MASTER_CFG) >>
 503             MASTER_CHIP_REV_SHIFT;
 504         if (bootverbose) {
 505                 device_printf(dev, "PCI device revision : 0x%04x\n",
 506                     sc->age_rev);
 507                 device_printf(dev, "Chip id/revision : 0x%04x\n",
 508                     sc->age_chip_rev);
 509         }
 510
 511         /*
 512          * XXX
 513          * Unintialized hardware returns an invalid chip id/revision
 514          * as well as 0xFFFFFFFF for Tx/Rx fifo length. It seems that
 515          * unplugged cable results in putting hardware into automatic
 516          * power down mode which in turn returns invalld chip revision.
 517          */
 518         if (sc->age_chip_rev == 0xFFFF) {
 519                 device_printf(dev,"invalid chip revision : 0x%04x -- "
 520                     "not initialized?\n", sc->age_chip_rev);
 521                 error = ENXIO;
 522                 goto fail;
 523         }
 524
 525         device_printf(dev, "%d Tx FIFO, %d Rx FIFO\n",
 526             CSR_READ_4(sc, AGE_SRAM_TX_FIFO_LEN),
 527             CSR_READ_4(sc, AGE_SRAM_RX_FIFO_LEN));
 528
 529         /* Allocate IRQ resources. */
 530         msixc = pci_msix_count(dev);
 531         msic = pci_msi_count(dev);
 532         if (bootverbose) {
 533                 device_printf(dev, "MSIX count : %d\n", msixc);
 534                 device_printf(dev, "MSI count : %d\n", msic);
 535         }
 536
 537         /* Prefer MSIX over MSI. */
 538         if (msix_disable == 0 || msi_disable == 0) {
 539                 if (msix_disable == 0 && msixc == AGE_MSIX_MESSAGES &&
 540                     pci_alloc_msix(dev, &msixc) == 0) {
 541                         if (msic == AGE_MSIX_MESSAGES) {
 542                                 device_printf(dev, "Using %d MSIX messages.\n",
 543                                     msixc);
 544                                 sc->age_flags |= AGE_FLAG_MSIX;
 545                                 sc->age_irq_spec = age_irq_spec_msix;
 546                         } else
 547                                 pci_release_msi(dev);
 548                 }
 549                 if (msi_disable == 0 && (sc->age_flags & AGE_FLAG_MSIX) == 0 &&
 550                     msic == AGE_MSI_MESSAGES &&
 551                     pci_alloc_msi(dev, &msic) == 0) {
 552                         if (msic == AGE_MSI_MESSAGES) {
 553                                 device_printf(dev, "Using %d MSI messages.\n",
 554                                     msic);
 555                                 sc->age_flags |= AGE_FLAG_MSI;
 556                                 sc->age_irq_spec = age_irq_spec_msi;
 557                         } else
 558                                 pci_release_msi(dev);
 559                 }
 560         }
 561
 562         error = bus_alloc_resources(dev, sc->age_irq_spec, sc->age_irq);
 563         if (error != 0) {
 564                 device_printf(dev, "cannot allocate IRQ resources.\n");
 565                 goto fail;
 566         }
 567
 568
 569         /* Get DMA parameters from PCIe device control register. */
 570         if (pci_find_extcap(dev, PCIY_EXPRESS, &i) == 0) {
 571                 sc->age_flags |= AGE_FLAG_PCIE;
 572                 burst = pci_read_config(dev, i + 0x08, 2);
 573                 /* Max read request size. */
 574                 sc->age_dma_rd_burst = ((burst >> 12) & 0x07) <<
 575                     DMA_CFG_RD_BURST_SHIFT;
 576                 /* Max payload size. */
 577                 sc->age_dma_wr_burst = ((burst >> 5) & 0x07) <<
 578                     DMA_CFG_WR_BURST_SHIFT;
 579                 if (bootverbose) {
 580                         device_printf(dev, "Read request size : %d bytes.\n",
 581                             128 << ((burst >> 12) & 0x07));
 582                         device_printf(dev, "TLP payload size : %d bytes.\n",
 583                             128 << ((burst >> 5) & 0x07));
 584                 }
 585         } else {
 586                 sc->age_dma_rd_burst = DMA_CFG_RD_BURST_128;
 587                 sc->age_dma_wr_burst = DMA_CFG_WR_BURST_128;
 588         }
 589
 590         /* Create device sysctl node. */
 591         age_sysctl_node(sc);
 592
 593         if ((error = age_dma_alloc(sc) != 0))
 594                 goto fail;
 595
 596         /* Load station address. */
 597         age_get_macaddr(sc);
 598
 599         ifp = sc->age_ifp = if_alloc(IFT_ETHER);
 600         if (ifp == NULL) {
 601                 device_printf(dev, "cannot allocate ifnet structure.\n");
 602                 error = ENXIO;
 603                 goto fail;
 604         }
 605
 606         ifp->if_softc = sc;
 607         if_initname(ifp, device_get_name(dev), device_get_unit(dev));
 608         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
 609         ifp->if_ioctl = age_ioctl;
 610         ifp->if_start = age_start;
 611         ifp->if_init = age_init;
 612         ifp->if_snd.ifq_drv_maxlen = AGE_TX_RING_CNT - 1;
 613         IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen);
 614         IFQ_SET_READY(&ifp->if_snd);
 615         ifp->if_capabilities = IFCAP_HWCSUM | IFCAP_TSO4;
 616         ifp->if_hwassist = AGE_CSUM_FEATURES | CSUM_TSO;
 617         if (pci_find_extcap(dev, PCIY_PMG, &pmc) == 0) {
 618                 sc->age_flags |= AGE_FLAG_PMCAP;
 619                 ifp->if_capabilities |= IFCAP_WOL_MAGIC | IFCAP_WOL_MCAST;
 620         }
 621         ifp->if_capenable = ifp->if_capabilities;
 622
 623         /* Set up MII bus. */
 624         if ((error = mii_phy_probe(dev, &sc->age_miibus, age_mediachange,
 625             age_mediastatus)) != 0) {
 626                 device_printf(dev, "no PHY found!\n");
 627                 goto fail;
 628         }
 629
 630         ether_ifattach(ifp, sc->age_eaddr);
 631
 632         /* VLAN capability setup. */
 633         ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING |
 634             IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWTSO;
 635         ifp->if_capenable = ifp->if_capabilities;
 636
 637         /* Tell the upper layer(s) we support long frames. */
 638         ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
 639
 640         /* Create local taskq. */
 641         TASK_INIT(&sc->age_tx_task, 1, age_tx_task, ifp);
 642         sc->age_tq = taskqueue_create_fast("age_taskq", M_WAITOK,
 643             taskqueue_thread_enqueue, &sc->age_tq);
 644         if (sc->age_tq == NULL) {
 645                 device_printf(dev, "could not create taskqueue.\n");
 646                 ether_ifdetach(ifp);
 647                 error = ENXIO;
 648                 goto fail;
 649         }
 650         taskqueue_start_threads(&sc->age_tq, 1, PI_NET, "%s taskq",
 651             device_get_nameunit(sc->age_dev));
 652
 653         if ((sc->age_flags & AGE_FLAG_MSIX) != 0)
 654                 msic = AGE_MSIX_MESSAGES;
 655         else if ((sc->age_flags & AGE_FLAG_MSI) != 0)
 656                 msic = AGE_MSI_MESSAGES;
 657         else
 658                 msic = 1;
 659         for (i = 0; i < msic; i++) {
 660                 error = bus_setup_intr(dev, sc->age_irq[i],
 661                     INTR_TYPE_NET | INTR_MPSAFE, age_intr, NULL, sc,
 662                     &sc->age_intrhand[i]);
 663                 if (error != 0)
 664                         break;
 665         }
 666         if (error != 0) {
 667                 device_printf(dev, "could not set up interrupt handler.\n");
 668                 taskqueue_free(sc->age_tq);
 669                 sc->age_tq = NULL;
 670                 ether_ifdetach(ifp);
 671                 goto fail;
 672         }
 673
 674 fail:
 675         if (error != 0)
 676                 age_detach(dev);
 677
 678         return (error);
 679 }
 680
 681 static int
 682 age_detach(device_t dev)
 683 {
 684         struct age_softc *sc;
 685         struct ifnet *ifp;
 686         int i, msic;
 687
 688         sc = device_get_softc(dev);
 689
 690         ifp = sc->age_ifp;
 691         if (device_is_attached(dev)) {
 692                 AGE_LOCK(sc);
 693                 sc->age_flags |= AGE_FLAG_DETACH;
 694                 age_stop(sc);
 695                 AGE_UNLOCK(sc);
 696                 callout_drain(&sc->age_tick_ch);
 697                 taskqueue_drain(sc->age_tq, &sc->age_int_task);
 698                 taskqueue_drain(sc->age_tq, &sc->age_tx_task);
 699                 taskqueue_drain(taskqueue_swi, &sc->age_link_task);
 700                 ether_ifdetach(ifp);
 701         }
 702
 703         if (sc->age_tq != NULL) {
 704                 taskqueue_drain(sc->age_tq, &sc->age_int_task);
 705                 taskqueue_free(sc->age_tq);
 706                 sc->age_tq = NULL;
 707         }
 708
 709         if (sc->age_miibus != NULL) {
 710                 device_delete_child(dev, sc->age_miibus);
 711                 sc->age_miibus = NULL;
 712         }
 713         bus_generic_detach(dev);
 714         age_dma_free(sc);
 715
 716         if (ifp != NULL) {
 717                 if_free(ifp);
 718                 sc->age_ifp = NULL;
 719         }
 720
 721         if ((sc->age_flags & AGE_FLAG_MSIX) != 0)
 722                 msic = AGE_MSIX_MESSAGES;
 723         else if ((sc->age_flags & AGE_FLAG_MSI) != 0)
 724                 msic = AGE_MSI_MESSAGES;
 725         else
 726                 msic = 1;
 727         for (i = 0; i < msic; i++) {
 728                 if (sc->age_intrhand[i] != NULL) {
 729                         bus_teardown_intr(dev, sc->age_irq[i],
 730                             sc->age_intrhand[i]);
 731                         sc->age_intrhand[i] = NULL;
 732                 }
 733         }
 734
 735         bus_release_resources(dev, sc->age_irq_spec, sc->age_irq);
 736         if ((sc->age_flags & (AGE_FLAG_MSI | AGE_FLAG_MSIX)) != 0)
 737                 pci_release_msi(dev);
 738         bus_release_resources(dev, sc->age_res_spec, sc->age_res);
 739         mtx_destroy(&sc->age_mtx);
 740
 741         return (0);
 742 }
 743
 744 static void
 745 age_sysctl_node(struct age_softc *sc)
 746 {
 747         int error;
 748
 749         SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->age_dev),
 750             SYSCTL_CHILDREN(device_get_sysctl_tree(sc->age_dev)), OID_AUTO,
 751             "stats", CTLTYPE_INT | CTLFLAG_RW, sc, 0, sysctl_age_stats,
 752             "I", "Statistics");
 753
 754         SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->age_dev),
 755             SYSCTL_CHILDREN(device_get_sysctl_tree(sc->age_dev)), OID_AUTO,
 756             "int_mod", CTLTYPE_INT | CTLFLAG_RW, &sc->age_int_mod, 0,
 757             sysctl_hw_age_int_mod, "I", "age interrupt moderation");
 758
 759         /* Pull in device tunables. */
 760         sc->age_int_mod = AGE_IM_TIMER_DEFAULT;
 761         error = resource_int_value(device_get_name(sc->age_dev),
 762             device_get_unit(sc->age_dev), "int_mod", &sc->age_int_mod);
 763         if (error == 0) {
 764                 if (sc->age_int_mod < AGE_IM_TIMER_MIN ||
 765                     sc->age_int_mod > AGE_IM_TIMER_MAX) {
 766                         device_printf(sc->age_dev,
 767                             "int_mod value out of range; using default: %d\n",
 768                             AGE_IM_TIMER_DEFAULT);
 769                         sc->age_int_mod = AGE_IM_TIMER_DEFAULT;
 770                 }
 771         }
 772
 773         SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->age_dev),
 774             SYSCTL_CHILDREN(device_get_sysctl_tree(sc->age_dev)), OID_AUTO,
 775             "process_limit", CTLTYPE_INT | CTLFLAG_RW, &sc->age_process_limit,
 776             0, sysctl_hw_age_proc_limit, "I",
 777             "max number of Rx events to process");
 778
 779         /* Pull in device tunables. */
 780         sc->age_process_limit = AGE_PROC_DEFAULT;
 781         error = resource_int_value(device_get_name(sc->age_dev),
 782             device_get_unit(sc->age_dev), "process_limit",
 783             &sc->age_process_limit);
 784         if (error == 0) {
 785                 if (sc->age_process_limit < AGE_PROC_MIN ||
 786                     sc->age_process_limit > AGE_PROC_MAX) {
 787                         device_printf(sc->age_dev,
 788                             "process_limit value out of range; "
 789                             "using default: %d\n", AGE_PROC_DEFAULT);
 790                         sc->age_process_limit = AGE_PROC_DEFAULT;
 791                 }
 792         }
 793 }
 794
 795 struct age_dmamap_arg {
 796         bus_addr_t      age_busaddr;
 797 };
 798
 799 static void
 800 age_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
 801 {
 802         struct age_dmamap_arg *ctx;
 803
 804         if (error != 0)
 805                 return;
 806
 807         KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
 808
 809         ctx = (struct age_dmamap_arg *)arg;
 810         ctx->age_busaddr = segs[0].ds_addr;
 811 }
 812
 813 /*
 814  * Attansic L1 controller have single register to specify high
 815  * address part of DMA blocks. So all descriptor structures and
 816  * DMA memory blocks should have the same high address of given
 817  * 4GB address space(i.e. crossing 4GB boundary is not allowed).
 818  */
 819 static int
 820 age_check_boundary(struct age_softc *sc)
 821 {
 822         bus_addr_t rx_ring_end, rr_ring_end, tx_ring_end;
 823         bus_addr_t cmb_block_end, smb_block_end;
 824
 825         /* Tx/Rx descriptor queue should reside within 4GB boundary. */
 826         tx_ring_end = sc->age_rdata.age_tx_ring_paddr + AGE_TX_RING_SZ;
 827         rx_ring_end = sc->age_rdata.age_rx_ring_paddr + AGE_RX_RING_SZ;
 828         rr_ring_end = sc->age_rdata.age_rr_ring_paddr + AGE_RR_RING_SZ;
 829         cmb_block_end = sc->age_rdata.age_cmb_block_paddr + AGE_CMB_BLOCK_SZ;
 830         smb_block_end = sc->age_rdata.age_smb_block_paddr + AGE_SMB_BLOCK_SZ;
 831
 832         if ((AGE_ADDR_HI(tx_ring_end) !=
 833             AGE_ADDR_HI(sc->age_rdata.age_tx_ring_paddr)) ||
 834             (AGE_ADDR_HI(rx_ring_end) !=
 835             AGE_ADDR_HI(sc->age_rdata.age_rx_ring_paddr)) ||
 836             (AGE_ADDR_HI(rr_ring_end) !=
 837             AGE_ADDR_HI(sc->age_rdata.age_rr_ring_paddr)) ||
 838             (AGE_ADDR_HI(cmb_block_end) !=
 839             AGE_ADDR_HI(sc->age_rdata.age_cmb_block_paddr)) ||
 840             (AGE_ADDR_HI(smb_block_end) !=
 841             AGE_ADDR_HI(sc->age_rdata.age_smb_block_paddr)))
 842                 return (EFBIG);
 843
 844         if ((AGE_ADDR_HI(tx_ring_end) != AGE_ADDR_HI(rx_ring_end)) ||
 845             (AGE_ADDR_HI(tx_ring_end) != AGE_ADDR_HI(rr_ring_end)) ||
 846             (AGE_ADDR_HI(tx_ring_end) != AGE_ADDR_HI(cmb_block_end)) ||
 847             (AGE_ADDR_HI(tx_ring_end) != AGE_ADDR_HI(smb_block_end)))
 848                 return (EFBIG);
 849
 850         return (0);
 851 }
 852
 853 static int
 854 age_dma_alloc(struct age_softc *sc)
 855 {
 856         struct age_txdesc *txd;
 857         struct age_rxdesc *rxd;
 858         bus_addr_t lowaddr;
 859         struct age_dmamap_arg ctx;
 860         int error, i;
 861
 862         lowaddr = BUS_SPACE_MAXADDR;
 863
 864 again:
 865         /* Create parent ring/DMA block tag. */
 866         error = bus_dma_tag_create(
 867             bus_get_dma_tag(sc->age_dev), /* parent */
 868             1, 0,                       /* alignment, boundary */
 869             lowaddr,                    /* lowaddr */
 870             BUS_SPACE_MAXADDR,          /* highaddr */
 871             NULL, NULL,                 /* filter, filterarg */
 872             BUS_SPACE_MAXSIZE_32BIT,    /* maxsize */
 873             0,                          /* nsegments */
 874             BUS_SPACE_MAXSIZE_32BIT,    /* maxsegsize */
 875             0,                          /* flags */
 876             NULL, NULL,                 /* lockfunc, lockarg */
 877             &sc->age_cdata.age_parent_tag);
 878         if (error != 0) {
 879                 device_printf(sc->age_dev,
 880                     "could not create parent DMA tag.\n");
 881                 goto fail;
 882         }
 883
 884         /* Create tag for Tx ring. */
 885         error = bus_dma_tag_create(
 886             sc->age_cdata.age_parent_tag, /* parent */
 887             AGE_TX_RING_ALIGN, 0,       /* alignment, boundary */
 888             BUS_SPACE_MAXADDR,          /* lowaddr */
 889             BUS_SPACE_MAXADDR,          /* highaddr */
 890             NULL, NULL,                 /* filter, filterarg */
 891             AGE_TX_RING_SZ,             /* maxsize */
 892             1,                          /* nsegments */
 893             AGE_TX_RING_SZ,             /* maxsegsize */
 894             0,                          /* flags */
 895             NULL, NULL,                 /* lockfunc, lockarg */
 896             &sc->age_cdata.age_tx_ring_tag);
 897         if (error != 0) {
 898                 device_printf(sc->age_dev,
 899                     "could not create Tx ring DMA tag.\n");
 900                 goto fail;
 901         }
 902
 903         /* Create tag for Rx ring. */
 904         error = bus_dma_tag_create(
 905             sc->age_cdata.age_parent_tag, /* parent */
 906             AGE_RX_RING_ALIGN, 0,       /* alignment, boundary */
 907             BUS_SPACE_MAXADDR,          /* lowaddr */
 908             BUS_SPACE_MAXADDR,          /* highaddr */
 909             NULL, NULL,                 /* filter, filterarg */
 910             AGE_RX_RING_SZ,             /* maxsize */
 911             1,                          /* nsegments */
 912             AGE_RX_RING_SZ,             /* maxsegsize */
 913             0,                          /* flags */
 914             NULL, NULL,                 /* lockfunc, lockarg */
 915             &sc->age_cdata.age_rx_ring_tag);
 916         if (error != 0) {
 917                 device_printf(sc->age_dev,
 918                     "could not create Rx ring DMA tag.\n");
 919                 goto fail;
 920         }
 921
 922         /* Create tag for Rx return ring. */
 923         error = bus_dma_tag_create(
 924             sc->age_cdata.age_parent_tag, /* parent */
 925             AGE_RR_RING_ALIGN, 0,       /* alignment, boundary */
 926             BUS_SPACE_MAXADDR,          /* lowaddr */
 927             BUS_SPACE_MAXADDR,          /* highaddr */
 928             NULL, NULL,                 /* filter, filterarg */
 929             AGE_RR_RING_SZ,             /* maxsize */
 930             1,                          /* nsegments */
 931             AGE_RR_RING_SZ,             /* maxsegsize */
 932             0,                          /* flags */
 933             NULL, NULL,                 /* lockfunc, lockarg */
 934             &sc->age_cdata.age_rr_ring_tag);
 935         if (error != 0) {
 936                 device_printf(sc->age_dev,
 937                     "could not create Rx return ring DMA tag.\n");
 938                 goto fail;
 939         }
 940
 941         /* Create tag for coalesing message block. */
 942         error = bus_dma_tag_create(
 943             sc->age_cdata.age_parent_tag, /* parent */
 944             AGE_CMB_ALIGN, 0,           /* alignment, boundary */
 945             BUS_SPACE_MAXADDR,          /* lowaddr */
 946             BUS_SPACE_MAXADDR,          /* highaddr */
 947             NULL, NULL,                 /* filter, filterarg */
 948             AGE_CMB_BLOCK_SZ,           /* maxsize */
 949             1,                          /* nsegments */
 950             AGE_CMB_BLOCK_SZ,           /* maxsegsize */
 951             0,                          /* flags */
 952             NULL, NULL,                 /* lockfunc, lockarg */
 953             &sc->age_cdata.age_cmb_block_tag);
 954         if (error != 0) {
 955                 device_printf(sc->age_dev,
 956                     "could not create CMB DMA tag.\n");
 957                 goto fail;
 958         }
 959
 960         /* Create tag for statistics message block. */
 961         error = bus_dma_tag_create(
 962             sc->age_cdata.age_parent_tag, /* parent */
 963             AGE_SMB_ALIGN, 0,           /* alignment, boundary */
 964             BUS_SPACE_MAXADDR,          /* lowaddr */
 965             BUS_SPACE_MAXADDR,          /* highaddr */
 966             NULL, NULL,                 /* filter, filterarg */
 967             AGE_SMB_BLOCK_SZ,           /* maxsize */
 968             1,                          /* nsegments */
 969             AGE_SMB_BLOCK_SZ,           /* maxsegsize */
 970             0,                          /* flags */
 971             NULL, NULL,                 /* lockfunc, lockarg */
 972             &sc->age_cdata.age_smb_block_tag);
 973         if (error != 0) {
 974                 device_printf(sc->age_dev,
 975                     "could not create SMB DMA tag.\n");
 976                 goto fail;
 977         }
 978
 979         /* Allocate DMA'able memory and load the DMA map. */
 980         error = bus_dmamem_alloc(sc->age_cdata.age_tx_ring_tag,
 981             (void **)&sc->age_rdata.age_tx_ring,
 982             BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT,
 983             &sc->age_cdata.age_tx_ring_map);
 984         if (error != 0) {
 985                 device_printf(sc->age_dev,
 986                     "could not allocate DMA'able memory for Tx ring.\n");
 987                 goto fail;
 988         }
 989         ctx.age_busaddr = 0;
 990         error = bus_dmamap_load(sc->age_cdata.age_tx_ring_tag,
 991             sc->age_cdata.age_tx_ring_map, sc->age_rdata.age_tx_ring,
 992             AGE_TX_RING_SZ, age_dmamap_cb, &ctx, 0);
 993         if (error != 0 || ctx.age_busaddr == 0) {
 994                 device_printf(sc->age_dev,
 995                     "could not load DMA'able memory for Tx ring.\n");
 996                 goto fail;
 997         }
 998         sc->age_rdata.age_tx_ring_paddr = ctx.age_busaddr;
 999         /* Rx ring */
1000         error = bus_dmamem_alloc(sc->age_cdata.age_rx_ring_tag,
1001             (void **)&sc->age_rdata.age_rx_ring,
1002             BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT,
1003             &sc->age_cdata.age_rx_ring_map);
1004         if (error != 0) {
1005                 device_printf(sc->age_dev,
1006                     "could not allocate DMA'able memory for Rx ring.\n");
1007                 goto fail;
1008         }
1009         ctx.age_busaddr = 0;
1010         error = bus_dmamap_load(sc->age_cdata.age_rx_ring_tag,
1011             sc->age_cdata.age_rx_ring_map, sc->age_rdata.age_rx_ring,
1012             AGE_RX_RING_SZ, age_dmamap_cb, &ctx, 0);
1013         if (error != 0 || ctx.age_busaddr == 0) {
1014                 device_printf(sc->age_dev,
1015                     "could not load DMA'able memory for Rx ring.\n");
1016                 goto fail;
1017         }
1018         sc->age_rdata.age_rx_ring_paddr = ctx.age_busaddr;
1019         /* Rx return ring */
1020         error = bus_dmamem_alloc(sc->age_cdata.age_rr_ring_tag,
1021             (void **)&sc->age_rdata.age_rr_ring,
1022             BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT,
1023             &sc->age_cdata.age_rr_ring_map);
1024         if (error != 0) {
1025                 device_printf(sc->age_dev,
1026                     "could not allocate DMA'able memory for Rx return ring.\n");
1027                 goto fail;
1028         }
1029         ctx.age_busaddr = 0;
1030         error = bus_dmamap_load(sc->age_cdata.age_rr_ring_tag,
1031             sc->age_cdata.age_rr_ring_map, sc->age_rdata.age_rr_ring,
1032             AGE_RR_RING_SZ, age_dmamap_cb,
1033             &ctx, 0);
1034         if (error != 0 || ctx.age_busaddr == 0) {
1035                 device_printf(sc->age_dev,
1036                     "could not load DMA'able memory for Rx return ring.\n");
1037                 goto fail;
1038         }
1039         sc->age_rdata.age_rr_ring_paddr = ctx.age_busaddr;
1040         /* CMB block */
1041         error = bus_dmamem_alloc(sc->age_cdata.age_cmb_block_tag,
1042             (void **)&sc->age_rdata.age_cmb_block,
1043             BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT,
1044             &sc->age_cdata.age_cmb_block_map);
1045         if (error != 0) {
1046                 device_printf(sc->age_dev,
1047                     "could not allocate DMA'able memory for CMB block.\n");
1048                 goto fail;
1049         }
1050         ctx.age_busaddr = 0;
1051         error = bus_dmamap_load(sc->age_cdata.age_cmb_block_tag,
1052             sc->age_cdata.age_cmb_block_map, sc->age_rdata.age_cmb_block,
1053             AGE_CMB_BLOCK_SZ, age_dmamap_cb, &ctx, 0);
1054         if (error != 0 || ctx.age_busaddr == 0) {
1055                 device_printf(sc->age_dev,
1056                     "could not load DMA'able memory for CMB block.\n");
1057                 goto fail;
1058         }
1059         sc->age_rdata.age_cmb_block_paddr = ctx.age_busaddr;
1060         /* SMB block */
1061         error = bus_dmamem_alloc(sc->age_cdata.age_smb_block_tag,
1062             (void **)&sc->age_rdata.age_smb_block,
1063             BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT,
1064             &sc->age_cdata.age_smb_block_map);
1065         if (error != 0) {
1066                 device_printf(sc->age_dev,
1067                     "could not allocate DMA'able memory for SMB block.\n");
1068                 goto fail;
1069         }
1070         ctx.age_busaddr = 0;
1071         error = bus_dmamap_load(sc->age_cdata.age_smb_block_tag,
1072             sc->age_cdata.age_smb_block_map, sc->age_rdata.age_smb_block,
1073             AGE_SMB_BLOCK_SZ, age_dmamap_cb, &ctx, 0);
1074         if (error != 0 || ctx.age_busaddr == 0) {
1075                 device_printf(sc->age_dev,
1076                     "could not load DMA'able memory for SMB block.\n");
1077                 goto fail;
1078         }
1079         sc->age_rdata.age_smb_block_paddr = ctx.age_busaddr;
1080
1081         /*
1082          * All ring buffer and DMA blocks should have the same
1083          * high address part of 64bit DMA address space.
1084          */
1085         if (lowaddr != BUS_SPACE_MAXADDR_32BIT &&
1086             (error = age_check_boundary(sc)) != 0) {
1087                 device_printf(sc->age_dev, "4GB boundary crossed, "
1088                     "switching to 32bit DMA addressing mode.\n");
1089                 age_dma_free(sc);
1090                 /* Limit DMA address space to 32bit and try again. */
1091                 lowaddr = BUS_SPACE_MAXADDR_32BIT;
1092                 goto again;
1093         }
1094
1095         /*
1096          * Create Tx/Rx buffer parent tag.
1097          * L1 supports full 64bit DMA addressing in Tx/Rx buffers
1098          * so it needs separate parent DMA tag.
1099          */
1100         error = bus_dma_tag_create(
1101             bus_get_dma_tag(sc->age_dev), /* parent */
1102             1, 0,                       /* alignment, boundary */
1103             BUS_SPACE_MAXADDR,          /* lowaddr */
1104             BUS_SPACE_MAXADDR,          /* highaddr */
1105             NULL, NULL,                 /* filter, filterarg */
1106             BUS_SPACE_MAXSIZE_32BIT,    /* maxsize */
1107             0,                          /* nsegments */
1108             BUS_SPACE_MAXSIZE_32BIT,    /* maxsegsize */
1109             0,                          /* flags */
1110             NULL, NULL,                 /* lockfunc, lockarg */
1111             &sc->age_cdata.age_buffer_tag);
1112         if (error != 0) {
1113                 device_printf(sc->age_dev,
1114                     "could not create parent buffer DMA tag.\n");
1115                 goto fail;
1116         }
1117
1118         /* Create tag for Tx buffers. */
1119         error = bus_dma_tag_create(
1120             sc->age_cdata.age_buffer_tag, /* parent */
1121             1, 0,                       /* alignment, boundary */
1122             BUS_SPACE_MAXADDR,          /* lowaddr */
1123             BUS_SPACE_MAXADDR,          /* highaddr */
1124             NULL, NULL,                 /* filter, filterarg */
1125             AGE_TSO_MAXSIZE,            /* maxsize */
1126             AGE_MAXTXSEGS,              /* nsegments */
1127             AGE_TSO_MAXSEGSIZE,         /* maxsegsize */
1128             0,                          /* flags */
1129             NULL, NULL,                 /* lockfunc, lockarg */
1130             &sc->age_cdata.age_tx_tag);
1131         if (error != 0) {
1132                 device_printf(sc->age_dev, "could not create Tx DMA tag.\n");
1133                 goto fail;
1134         }
1135
1136         /* Create tag for Rx buffers. */
1137         error = bus_dma_tag_create(
1138             sc->age_cdata.age_buffer_tag, /* parent */
1139             1, 0,                       /* alignment, boundary */
1140             BUS_SPACE_MAXADDR,          /* lowaddr */
1141             BUS_SPACE_MAXADDR,          /* highaddr */
1142             NULL, NULL,                 /* filter, filterarg */
1143             MCLBYTES,                   /* maxsize */
1144             1,                          /* nsegments */
1145             MCLBYTES,                   /* maxsegsize */
1146             0,                          /* flags */
1147             NULL, NULL,                 /* lockfunc, lockarg */
1148             &sc->age_cdata.age_rx_tag);
1149         if (error != 0) {
1150                 device_printf(sc->age_dev, "could not create Rx DMA tag.\n");
1151                 goto fail;
1152         }
1153
1154         /* Create DMA maps for Tx buffers. */
1155         for (i = 0; i < AGE_TX_RING_CNT; i++) {
1156                 txd = &sc->age_cdata.age_txdesc[i];
1157                 txd->tx_m = NULL;
1158                 txd->tx_dmamap = NULL;
1159                 error = bus_dmamap_create(sc->age_cdata.age_tx_tag, 0,
1160                     &txd->tx_dmamap);
1161                 if (error != 0) {
1162                         device_printf(sc->age_dev,
1163                             "could not create Tx dmamap.\n");
1164                         goto fail;
1165                 }
1166         }
1167         /* Create DMA maps for Rx buffers. */
1168         if ((error = bus_dmamap_create(sc->age_cdata.age_rx_tag, 0,
1169             &sc->age_cdata.age_rx_sparemap)) != 0) {
1170                 device_printf(sc->age_dev,
1171                     "could not create spare Rx dmamap.\n");
1172                 goto fail;
1173         }
1174         for (i = 0; i < AGE_RX_RING_CNT; i++) {
1175                 rxd = &sc->age_cdata.age_rxdesc[i];
1176                 rxd->rx_m = NULL;
1177                 rxd->rx_dmamap = NULL;
1178                 error = bus_dmamap_create(sc->age_cdata.age_rx_tag, 0,
1179                     &rxd->rx_dmamap);
1180                 if (error != 0) {
1181                         device_printf(sc->age_dev,
1182                             "could not create Rx dmamap.\n");
1183                         goto fail;
1184                 }
1185         }
1186
1187 fail:
1188         return (error);
1189 }
1190
1191 static void
1192 age_dma_free(struct age_softc *sc)
1193 {
1194         struct age_txdesc *txd;
1195         struct age_rxdesc *rxd;
1196         int i;
1197
1198         /* Tx buffers */
1199         if (sc->age_cdata.age_tx_tag != NULL) {
1200                 for (i = 0; i < AGE_TX_RING_CNT; i++) {
1201                         txd = &sc->age_cdata.age_txdesc[i];
1202                         if (txd->tx_dmamap != NULL) {
1203                                 bus_dmamap_destroy(sc->age_cdata.age_tx_tag,
1204                                     txd->tx_dmamap);
1205                                 txd->tx_dmamap = NULL;
1206                         }
1207                 }
1208                 bus_dma_tag_destroy(sc->age_cdata.age_tx_tag);
1209                 sc->age_cdata.age_tx_tag = NULL;
1210         }
1211         /* Rx buffers */
1212         if (sc->age_cdata.age_rx_tag != NULL) {
1213                 for (i = 0; i < AGE_RX_RING_CNT; i++) {
1214                         rxd = &sc->age_cdata.age_rxdesc[i];
1215                         if (rxd->rx_dmamap != NULL) {
1216                                 bus_dmamap_destroy(sc->age_cdata.age_rx_tag,
1217                                     rxd->rx_dmamap);
1218                                 rxd->rx_dmamap = NULL;
1219                         }
1220                 }
1221                 if (sc->age_cdata.age_rx_sparemap != NULL) {
1222                         bus_dmamap_destroy(sc->age_cdata.age_rx_tag,
1223                             sc->age_cdata.age_rx_sparemap);
1224                         sc->age_cdata.age_rx_sparemap = NULL;
1225                 }
1226                 bus_dma_tag_destroy(sc->age_cdata.age_rx_tag);
1227                 sc->age_cdata.age_rx_tag = NULL;
1228         }
1229         /* Tx ring. */
1230         if (sc->age_cdata.age_tx_ring_tag != NULL) {
1231                 if (sc->age_cdata.age_tx_ring_map != NULL)
1232                         bus_dmamap_unload(sc->age_cdata.age_tx_ring_tag,
1233                             sc->age_cdata.age_tx_ring_map);
1234                 if (sc->age_cdata.age_tx_ring_map != NULL &&
1235                     sc->age_rdata.age_tx_ring != NULL)
1236                         bus_dmamem_free(sc->age_cdata.age_tx_ring_tag,
1237                             sc->age_rdata.age_tx_ring,
1238                             sc->age_cdata.age_tx_ring_map);
1239                 sc->age_rdata.age_tx_ring = NULL;
1240                 sc->age_cdata.age_tx_ring_map = NULL;
1241                 bus_dma_tag_destroy(sc->age_cdata.age_tx_ring_tag);
1242                 sc->age_cdata.age_tx_ring_tag = NULL;
1243         }
1244         /* Rx ring. */
1245         if (sc->age_cdata.age_rx_ring_tag != NULL) {
1246                 if (sc->age_cdata.age_rx_ring_map != NULL)
1247                         bus_dmamap_unload(sc->age_cdata.age_rx_ring_tag,
1248                             sc->age_cdata.age_rx_ring_map);
1249                 if (sc->age_cdata.age_rx_ring_map != NULL &&
1250                     sc->age_rdata.age_rx_ring != NULL)
1251                         bus_dmamem_free(sc->age_cdata.age_rx_ring_tag,
1252                             sc->age_rdata.age_rx_ring,
1253                             sc->age_cdata.age_rx_ring_map);
1254                 sc->age_rdata.age_rx_ring = NULL;
1255                 sc->age_cdata.age_rx_ring_map = NULL;
1256                 bus_dma_tag_destroy(sc->age_cdata.age_rx_ring_tag);
1257                 sc->age_cdata.age_rx_ring_tag = NULL;
1258         }
1259         /* Rx return ring. */
1260         if (sc->age_cdata.age_rr_ring_tag != NULL) {
1261                 if (sc->age_cdata.age_rr_ring_map != NULL)
1262                         bus_dmamap_unload(sc->age_cdata.age_rr_ring_tag,
1263                             sc->age_cdata.age_rr_ring_map);
1264                 if (sc->age_cdata.age_rr_ring_map != NULL &&
1265                     sc->age_rdata.age_rr_ring != NULL)
1266                         bus_dmamem_free(sc->age_cdata.age_rr_ring_tag,
1267                             sc->age_rdata.age_rr_ring,
1268                             sc->age_cdata.age_rr_ring_map);
1269                 sc->age_rdata.age_rr_ring = NULL;
1270                 sc->age_cdata.age_rr_ring_map = NULL;
1271                 bus_dma_tag_destroy(sc->age_cdata.age_rr_ring_tag);
1272                 sc->age_cdata.age_rr_ring_tag = NULL;
1273         }
1274         /* CMB block */
1275         if (sc->age_cdata.age_cmb_block_tag != NULL) {
1276                 if (sc->age_cdata.age_cmb_block_map != NULL)
1277                         bus_dmamap_unload(sc->age_cdata.age_cmb_block_tag,
1278                             sc->age_cdata.age_cmb_block_map);
1279                 if (sc->age_cdata.age_cmb_block_map != NULL &&
1280                     sc->age_rdata.age_cmb_block != NULL)
1281                         bus_dmamem_free(sc->age_cdata.age_cmb_block_tag,
1282                             sc->age_rdata.age_cmb_block,
1283                             sc->age_cdata.age_cmb_block_map);
1284                 sc->age_rdata.age_cmb_block = NULL;
1285                 sc->age_cdata.age_cmb_block_map = NULL;
1286                 bus_dma_tag_destroy(sc->age_cdata.age_cmb_block_tag);
1287                 sc->age_cdata.age_cmb_block_tag = NULL;
1288         }
1289         /* SMB block */
1290         if (sc->age_cdata.age_smb_block_tag != NULL) {
1291                 if (sc->age_cdata.age_smb_block_map != NULL)
1292                         bus_dmamap_unload(sc->age_cdata.age_smb_block_tag,
1293                             sc->age_cdata.age_smb_block_map);
1294                 if (sc->age_cdata.age_smb_block_map != NULL &&
1295                     sc->age_rdata.age_smb_block != NULL)
1296                         bus_dmamem_free(sc->age_cdata.age_smb_block_tag,
1297                             sc->age_rdata.age_smb_block,
1298                             sc->age_cdata.age_smb_block_map);
1299                 sc->age_rdata.age_smb_block = NULL;
1300                 sc->age_cdata.age_smb_block_map = NULL;
1301                 bus_dma_tag_destroy(sc->age_cdata.age_smb_block_tag);
1302                 sc->age_cdata.age_smb_block_tag = NULL;
1303         }
1304
1305         if (sc->age_cdata.age_buffer_tag != NULL) {
1306                 bus_dma_tag_destroy(sc->age_cdata.age_buffer_tag);
1307                 sc->age_cdata.age_buffer_tag = NULL;
1308         }
1309         if (sc->age_cdata.age_parent_tag != NULL) {
1310                 bus_dma_tag_destroy(sc->age_cdata.age_parent_tag);
1311                 sc->age_cdata.age_parent_tag = NULL;
1312         }
1313 }
1314
1315 /*
1316  *      Make sure the interface is stopped at reboot time.
1317  */
1318 static int
1319 age_shutdown(device_t dev)
1320 {
1321
1322         return (age_suspend(dev));
1323 }
1324
1325 static void
1326 age_setwol(struct age_softc *sc)
1327 {
1328         struct ifnet *ifp;
1329         struct mii_data *mii;
1330         uint32_t reg, pmcs;
1331         uint16_t pmstat;
1332         int aneg, i, pmc;
1333
1334         AGE_LOCK_ASSERT(sc);
1335
1336         if (pci_find_extcap(sc->age_dev, PCIY_PMG, &pmc) != 0) {
1337                 CSR_WRITE_4(sc, AGE_WOL_CFG, 0);
1338                 /*
1339                  * No PME capability, PHY power down.
1340                  * XXX
1341                  * Due to an unknown reason powering down PHY resulted
1342                  * in unexpected results such as inaccessbility of
1343                  * hardware of freshly rebooted system. Disable
1344                  * powering down PHY until I got more information for
1345                  * Attansic/Atheros PHY hardwares.
1346                  */
1347 #ifdef notyet
1348                 age_miibus_writereg(sc->age_dev, sc->age_phyaddr,
1349                     MII_BMCR, BMCR_PDOWN);
1350 #endif
1351                 return;
1352         }
1353
1354         ifp = sc->age_ifp;
1355         if ((ifp->if_capenable & IFCAP_WOL) != 0) {
1356                 /*
1357                  * Note, this driver resets the link speed to 10/100Mbps with
1358                  * auto-negotiation but we don't know whether that operation
1359                  * would succeed or not as it have no control after powering
1360                  * off. If the renegotiation fail WOL may not work. Running
1361                  * at 1Gbps will draw more power than 375mA at 3.3V which is
1362                  * specified in PCI specification and that would result in
1363                  * complete shutdowning power to ethernet controller.
1364                  *
1365                  * TODO
1366                  *  Save current negotiated media speed/duplex/flow-control
1367                  *  to softc and restore the same link again after resuming.
1368                  *  PHY handling such as power down/resetting to 100Mbps
1369                  *  may be better handled in suspend method in phy driver.
1370                  */
1371                 mii = device_get_softc(sc->age_miibus);
1372                 mii_pollstat(mii);
1373                 aneg = 0;
1374                 if ((mii->mii_media_status & IFM_AVALID) != 0) {
1375                         switch IFM_SUBTYPE(mii->mii_media_active) {
1376                         case IFM_10_T:
1377                         case IFM_100_TX:
1378                                 goto got_link;
1379                         case IFM_1000_T:
1380                                 aneg++;
1381                         default:
1382                                 break;
1383                         }
1384                 }
1385                 age_miibus_writereg(sc->age_dev, sc->age_phyaddr,
1386                     MII_100T2CR, 0);
1387                 age_miibus_writereg(sc->age_dev, sc->age_phyaddr,
1388                     MII_ANAR, ANAR_TX_FD | ANAR_TX | ANAR_10_FD |
1389                     ANAR_10 | ANAR_CSMA);
1390                 age_miibus_writereg(sc->age_dev, sc->age_phyaddr,
1391                     MII_BMCR, BMCR_RESET | BMCR_AUTOEN | BMCR_STARTNEG);
1392                 DELAY(1000);
1393                 if (aneg != 0) {
1394                         /* Poll link state until age(4) get a 10/100 link. */
1395                         for (i = 0; i < MII_ANEGTICKS_GIGE; i++) {
1396                                 mii_pollstat(mii);
1397                                 if ((mii->mii_media_status & IFM_AVALID) != 0) {
1398                                         switch (IFM_SUBTYPE(
1399                                             mii->mii_media_active)) {
1400                                         case IFM_10_T:
1401                                         case IFM_100_TX:
1402                                                 age_mac_config(sc);
1403                                                 goto got_link;
1404                                         default:
1405                                                 break;
1406                                         }
1407                                 }
1408                                 AGE_UNLOCK(sc);
1409                                 pause("agelnk", hz);
1410                                 AGE_LOCK(sc);
1411                         }
1412                         if (i == MII_ANEGTICKS_GIGE)
1413                                 device_printf(sc->age_dev,
1414                                     "establishing link failed, "
1415                                     "WOL may not work!");
1416                 }
1417                 /*
1418                  * No link, force MAC to have 100Mbps, full-duplex link.
1419                  * This is the last resort and may/may not work.
1420                  */
1421                 mii->mii_media_status = IFM_AVALID | IFM_ACTIVE;
1422                 mii->mii_media_active = IFM_ETHER | IFM_100_TX | IFM_FDX;
1423                 age_mac_config(sc);
1424         }
1425
1426 got_link:
1427         pmcs = 0;
1428         if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0)
1429                 pmcs |= WOL_CFG_MAGIC | WOL_CFG_MAGIC_ENB;
1430         CSR_WRITE_4(sc, AGE_WOL_CFG, pmcs);
1431         reg = CSR_READ_4(sc, AGE_MAC_CFG);
1432         reg &= ~(MAC_CFG_DBG | MAC_CFG_PROMISC);
1433         reg &= ~(MAC_CFG_ALLMULTI | MAC_CFG_BCAST);
1434         if ((ifp->if_capenable & IFCAP_WOL_MCAST) != 0)
1435                 reg |= MAC_CFG_ALLMULTI | MAC_CFG_BCAST;
1436         if ((ifp->if_capenable & IFCAP_WOL) != 0) {
1437                 reg |= MAC_CFG_RX_ENB;
1438                 CSR_WRITE_4(sc, AGE_MAC_CFG, reg);
1439         }
1440
1441         /* Request PME. */
1442         pmstat = pci_read_config(sc->age_dev, pmc + PCIR_POWER_STATUS, 2);
1443         pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE);
1444         if ((ifp->if_capenable & IFCAP_WOL) != 0)
1445                 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
1446         pci_write_config(sc->age_dev, pmc + PCIR_POWER_STATUS, pmstat, 2);
1447 #ifdef notyet
1448         /* See above for powering down PHY issues. */
1449         if ((ifp->if_capenable & IFCAP_WOL) == 0) {
1450                 /* No WOL, PHY power down. */
1451                 age_miibus_writereg(sc->age_dev, sc->age_phyaddr,
1452                     MII_BMCR, BMCR_PDOWN);
1453         }
1454 #endif
1455 }
1456
1457 static int
1458 age_suspend(device_t dev)
1459 {
1460         struct age_softc *sc;
1461
1462         sc = device_get_softc(dev);
1463
1464         AGE_LOCK(sc);
1465         age_stop(sc);
1466         age_setwol(sc);
1467         AGE_UNLOCK(sc);
1468
1469         return (0);
1470 }
1471
1472 static int
1473 age_resume(device_t dev)
1474 {
1475         struct age_softc *sc;
1476         struct ifnet *ifp;
1477
1478         sc = device_get_softc(dev);
1479
1480         AGE_LOCK(sc);
1481         age_phy_reset(sc);
1482         ifp = sc->age_ifp;
1483         if ((ifp->if_flags & IFF_UP) != 0)
1484                 age_init_locked(sc);
1485
1486         AGE_UNLOCK(sc);
1487
1488         return (0);
1489 }
1490
1491 static int
1492 age_encap(struct age_softc *sc, struct mbuf **m_head)
1493 {
1494         struct age_txdesc *txd, *txd_last;
1495         struct tx_desc *desc;
1496         struct mbuf *m;
1497         struct ip *ip;
1498         struct tcphdr *tcp;
1499         bus_dma_segment_t txsegs[AGE_MAXTXSEGS];
1500         bus_dmamap_t map;
1501         uint32_t cflags, ip_off, poff, vtag;
1502         int error, i, nsegs, prod, si;
1503
1504         AGE_LOCK_ASSERT(sc);
1505
1506         M_ASSERTPKTHDR((*m_head));
1507
1508         m = *m_head;
1509         ip = NULL;
1510         tcp = NULL;
1511         cflags = vtag = 0;
1512         ip_off = poff = 0;
1513         if ((m->m_pkthdr.csum_flags & (AGE_CSUM_FEATURES | CSUM_TSO)) != 0) {
1514                 /*
1515                  * L1 requires offset of TCP/UDP payload in its Tx
1516                  * descriptor to perform hardware Tx checksum offload.
1517                  * Additionally, TSO requires IP/TCP header size and
1518                  * modification of IP/TCP header in order to make TSO
1519                  * engine work. This kind of operation takes many CPU
1520                  * cycles on FreeBSD so fast host CPU is needed to get
1521                  * smooth TSO performance.
1522                  */
1523                 struct ether_header *eh;
1524
1525                 if (M_WRITABLE(m) == 0) {
1526                         /* Get a writable copy. */
1527                         m = m_dup(*m_head, M_DONTWAIT);
1528                         /* Release original mbufs. */
1529                         m_freem(*m_head);
1530                         if (m == NULL) {
1531                                 *m_head = NULL;
1532                                 return (ENOBUFS);
1533                         }
1534                         *m_head = m;
1535                 }
1536                 ip_off = sizeof(struct ether_header);
1537                 m = m_pullup(m, ip_off);
1538                 if (m == NULL) {
1539                         *m_head = NULL;
1540                         return (ENOBUFS);
1541                 }
1542                 eh = mtod(m, struct ether_header *);
1543                 /*
1544                  * Check if hardware VLAN insertion is off.
1545                  * Additional check for LLC/SNAP frame?
1546                  */
1547                 if (eh->ether_type == htons(ETHERTYPE_VLAN)) {
1548                         ip_off = sizeof(struct ether_vlan_header);
1549                         m = m_pullup(m, ip_off);
1550                         if (m == NULL) {
1551                                 *m_head = NULL;
1552                                 return (ENOBUFS);
1553                         }
1554                 }
1555                 m = m_pullup(m, ip_off + sizeof(struct ip));
1556                 if (m == NULL) {
1557                         *m_head = NULL;
1558                         return (ENOBUFS);
1559                 }
1560                 ip = (struct ip *)(mtod(m, char *) + ip_off);
1561                 poff = ip_off + (ip->ip_hl << 2);
1562                 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) {
1563                         m = m_pullup(m, poff + sizeof(struct tcphdr));
1564                         if (m == NULL) {
1565                                 *m_head = NULL;
1566                                 return (ENOBUFS);
1567                         }
1568                         tcp = (struct tcphdr *)(mtod(m, char *) + poff);
1569                         /*
1570                          * L1 requires IP/TCP header size and offset as
1571                          * well as TCP pseudo checksum which complicates
1572                          * TSO configuration. I guess this comes from the
1573                          * adherence to Microsoft NDIS Large Send
1574                          * specification which requires insertion of
1575                          * pseudo checksum by upper stack. The pseudo
1576                          * checksum that NDIS refers to doesn't include
1577                          * TCP payload length so age(4) should recompute
1578                          * the pseudo checksum here. Hopefully this wouldn't
1579                          * be much burden on modern CPUs.
1580                          * Reset IP checksum and recompute TCP pseudo
1581                          * checksum as NDIS specification said.
1582                          */
1583                         ip->ip_sum = 0;
1584                         if (poff + (tcp->th_off << 2) == m->m_pkthdr.len)
1585                                 tcp->th_sum = in_pseudo(ip->ip_src.s_addr,
1586                                     ip->ip_dst.s_addr,
1587                                     htons((tcp->th_off << 2) + IPPROTO_TCP));
1588                         else
1589                                 tcp->th_sum = in_pseudo(ip->ip_src.s_addr,
1590                                     ip->ip_dst.s_addr, htons(IPPROTO_TCP));
1591                 }
1592                 *m_head = m;
1593         }
1594
1595         si = prod = sc->age_cdata.age_tx_prod;
1596         txd = &sc->age_cdata.age_txdesc[prod];
1597         txd_last = txd;
1598         map = txd->tx_dmamap;
1599
1600         error =  bus_dmamap_load_mbuf_sg(sc->age_cdata.age_tx_tag, map,
1601             *m_head, txsegs, &nsegs, 0);
1602         if (error == EFBIG) {
1603                 m = m_collapse(*m_head, M_DONTWAIT, AGE_MAXTXSEGS);
1604                 if (m == NULL) {
1605                         m_freem(*m_head);
1606                         *m_head = NULL;
1607                         return (ENOMEM);
1608                 }
1609                 *m_head = m;
1610                 error = bus_dmamap_load_mbuf_sg(sc->age_cdata.age_tx_tag, map,
1611                     *m_head, txsegs, &nsegs, 0);
1612                 if (error != 0) {
1613                         m_freem(*m_head);
1614                         *m_head = NULL;
1615                         return (error);
1616                 }
1617         } else if (error != 0)
1618                 return (error);
1619         if (nsegs == 0) {
1620                 m_freem(*m_head);
1621                 *m_head = NULL;
1622                 return (EIO);
1623         }
1624
1625         /* Check descriptor overrun. */
1626         if (sc->age_cdata.age_tx_cnt + nsegs >= AGE_TX_RING_CNT - 2) {
1627                 bus_dmamap_unload(sc->age_cdata.age_tx_tag, map);
1628                 return (ENOBUFS);
1629         }
1630
1631         m = *m_head;
1632         if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) {
1633                 /* Configure TSO. */
1634                 if (poff + (tcp->th_off << 2) == m->m_pkthdr.len) {
1635                         /* Not TSO but IP/TCP checksum offload. */
1636                         cflags |= AGE_TD_IPCSUM | AGE_TD_TCPCSUM;
1637                         /* Clear TSO in order not to set AGE_TD_TSO_HDR. */
1638                         m->m_pkthdr.csum_flags &= ~CSUM_TSO;
1639                 } else {
1640                         /* Request TSO and set MSS. */
1641                         cflags |= AGE_TD_TSO_IPV4;
1642                         cflags |= AGE_TD_IPCSUM | AGE_TD_TCPCSUM;
1643                         cflags |= ((uint32_t)m->m_pkthdr.tso_segsz <<
1644                             AGE_TD_TSO_MSS_SHIFT);
1645                 }
1646                 /* Set IP/TCP header size. */
1647                 cflags |= ip->ip_hl << AGE_TD_IPHDR_LEN_SHIFT;
1648                 cflags |= tcp->th_off << AGE_TD_TSO_TCPHDR_LEN_SHIFT;
1649         } else if ((m->m_pkthdr.csum_flags & AGE_CSUM_FEATURES) != 0) {
1650                 /* Configure Tx IP/TCP/UDP checksum offload. */
1651                 cflags |= AGE_TD_CSUM;
1652                 if ((m->m_pkthdr.csum_flags & CSUM_TCP) != 0)
1653                         cflags |= AGE_TD_TCPCSUM;
1654                 if ((m->m_pkthdr.csum_flags & CSUM_UDP) != 0)
1655                         cflags |= AGE_TD_UDPCSUM;
1656                 /* Set checksum start offset. */
1657                 cflags |= (poff << AGE_TD_CSUM_PLOADOFFSET_SHIFT);
1658                 /* Set checksum insertion position of TCP/UDP. */
1659                 cflags |= ((poff + m->m_pkthdr.csum_data) <<
1660                     AGE_TD_CSUM_XSUMOFFSET_SHIFT);
1661         }
1662
1663         /* Configure VLAN hardware tag insertion. */
1664         if ((m->m_flags & M_VLANTAG) != 0) {
1665                 vtag = AGE_TX_VLAN_TAG(m->m_pkthdr.ether_vtag);
1666                 vtag = ((vtag << AGE_TD_VLAN_SHIFT) & AGE_TD_VLAN_MASK);
1667                 cflags |= AGE_TD_INSERT_VLAN_TAG;
1668         }
1669
1670         desc = NULL;
1671         for (i = 0; i < nsegs; i++) {
1672                 desc = &sc->age_rdata.age_tx_ring[prod];
1673                 desc->addr = htole64(txsegs[i].ds_addr);
1674                 desc->len = htole32(AGE_TX_BYTES(txsegs[i].ds_len) | vtag);
1675                 desc->flags = htole32(cflags);
1676                 sc->age_cdata.age_tx_cnt++;
1677                 AGE_DESC_INC(prod, AGE_TX_RING_CNT);
1678         }
1679         /* Update producer index. */
1680         sc->age_cdata.age_tx_prod = prod;
1681
1682         /* Set EOP on the last descriptor. */
1683         prod = (prod + AGE_TX_RING_CNT - 1) % AGE_TX_RING_CNT;
1684         desc = &sc->age_rdata.age_tx_ring[prod];
1685         desc->flags |= htole32(AGE_TD_EOP);
1686
1687         /* Lastly set TSO header and modify IP/TCP header for TSO operation. */
1688         if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) {
1689                 desc = &sc->age_rdata.age_tx_ring[si];
1690                 desc->flags |= htole32(AGE_TD_TSO_HDR);
1691         }
1692
1693         /* Swap dmamap of the first and the last. */
1694         txd = &sc->age_cdata.age_txdesc[prod];
1695         map = txd_last->tx_dmamap;
1696         txd_last->tx_dmamap = txd->tx_dmamap;
1697         txd->tx_dmamap = map;
1698         txd->tx_m = m;
1699
1700         /* Sync descriptors. */
1701         bus_dmamap_sync(sc->age_cdata.age_tx_tag, map, BUS_DMASYNC_PREWRITE);
1702         bus_dmamap_sync(sc->age_cdata.age_tx_ring_tag,
1703             sc->age_cdata.age_tx_ring_map,
1704             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1705
1706         return (0);
1707 }
1708
1709 static void
1710 age_tx_task(void *arg, int pending)
1711 {
1712         struct ifnet *ifp;
1713
1714         ifp = (struct ifnet *)arg;
1715         age_start(ifp);
1716 }
1717
1718 static void
1719 age_start(struct ifnet *ifp)
1720 {
1721         struct age_softc *sc;
1722         struct mbuf *m_head;
1723         int enq;
1724
1725         sc = ifp->if_softc;
1726
1727         AGE_LOCK(sc);
1728
1729         if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
1730             IFF_DRV_RUNNING || (sc->age_flags & AGE_FLAG_LINK) == 0) {
1731                 AGE_UNLOCK(sc);
1732                 return;
1733         }
1734
1735         for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd); ) {
1736                 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
1737                 if (m_head == NULL)
1738                         break;
1739                 /*
1740                  * Pack the data into the transmit ring. If we
1741                  * don't have room, set the OACTIVE flag and wait
1742                  * for the NIC to drain the ring.
1743                  */
1744                 if (age_encap(sc, &m_head)) {
1745                         if (m_head == NULL)
1746                                 break;
1747                         IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
1748                         ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1749                         break;
1750                 }
1751
1752                 enq++;
1753                 /*
1754                  * If there's a BPF listener, bounce a copy of this frame
1755                  * to him.
1756                  */
1757                 ETHER_BPF_MTAP(ifp, m_head);
1758         }
1759
1760         if (enq > 0) {
1761                 /* Update mbox. */
1762                 AGE_COMMIT_MBOX(sc);
1763                 /* Set a timeout in case the chip goes out to lunch. */
1764                 sc->age_watchdog_timer = AGE_TX_TIMEOUT;
1765         }
1766
1767         AGE_UNLOCK(sc);
1768 }
1769
1770 static void
1771 age_watchdog(struct age_softc *sc)
1772 {
1773         struct ifnet *ifp;
1774
1775         AGE_LOCK_ASSERT(sc);
1776
1777         if (sc->age_watchdog_timer == 0 || --sc->age_watchdog_timer)
1778                 return;
1779
1780         ifp = sc->age_ifp;
1781         if ((sc->age_flags & AGE_FLAG_LINK) == 0) {
1782                 if_printf(sc->age_ifp, "watchdog timeout (missed link)\n");
1783                 ifp->if_oerrors++;
1784                 age_init_locked(sc);
1785                 return;
1786         }
1787         if (sc->age_cdata.age_tx_cnt == 0) {
1788                 if_printf(sc->age_ifp,
1789                     "watchdog timeout (missed Tx interrupts) -- recovering\n");
1790                 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1791                         taskqueue_enqueue(sc->age_tq, &sc->age_tx_task);
1792                 return;
1793         }
1794         if_printf(sc->age_ifp, "watchdog timeout\n");
1795         ifp->if_oerrors++;
1796         age_init_locked(sc);
1797         if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1798                 taskqueue_enqueue(sc->age_tq, &sc->age_tx_task);
1799 }
1800
1801 static int
1802 age_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
1803 {
1804         struct age_softc *sc;
1805         struct ifreq *ifr;
1806         struct mii_data *mii;
1807         uint32_t reg;
1808         int error, mask;
1809
1810         sc = ifp->if_softc;
1811         ifr = (struct ifreq *)data;
1812         error = 0;
1813         switch (cmd) {
1814         case SIOCSIFMTU:
1815                 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > AGE_JUMBO_MTU)
1816                         error = EINVAL;
1817                 else if (ifp->if_mtu != ifr->ifr_mtu) {
1818                         AGE_LOCK(sc);
1819                         ifp->if_mtu = ifr->ifr_mtu;
1820                         if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
1821                                 age_init_locked(sc);
1822                         AGE_UNLOCK(sc);
1823                 }
1824                 break;
1825         case SIOCSIFFLAGS:
1826                 AGE_LOCK(sc);
1827                 if ((ifp->if_flags & IFF_UP) != 0) {
1828                         if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
1829                                 if (((ifp->if_flags ^ sc->age_if_flags)
1830                                     & (IFF_PROMISC | IFF_ALLMULTI)) != 0)
1831                                         age_rxfilter(sc);
1832                         } else {
1833                                 if ((sc->age_flags & AGE_FLAG_DETACH) == 0)
1834                                         age_init_locked(sc);
1835                         }
1836                 } else {
1837                         if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
1838                                 age_stop(sc);
1839                 }
1840                 sc->age_if_flags = ifp->if_flags;
1841                 AGE_UNLOCK(sc);
1842                 break;
1843         case SIOCADDMULTI:
1844         case SIOCDELMULTI:
1845                 AGE_LOCK(sc);
1846                 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
1847                         age_rxfilter(sc);
1848                 AGE_UNLOCK(sc);
1849                 break;
1850         case SIOCSIFMEDIA:
1851         case SIOCGIFMEDIA:
1852                 mii = device_get_softc(sc->age_miibus);
1853                 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd);
1854                 break;
1855         case SIOCSIFCAP:
1856                 AGE_LOCK(sc);
1857                 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
1858                 if ((mask & IFCAP_TXCSUM) != 0 &&
1859                     (ifp->if_capabilities & IFCAP_TXCSUM) != 0) {
1860                         ifp->if_capenable ^= IFCAP_TXCSUM;
1861                         if ((ifp->if_capenable & IFCAP_TXCSUM) != 0)
1862                                 ifp->if_hwassist |= AGE_CSUM_FEATURES;
1863                         else
1864                                 ifp->if_hwassist &= ~AGE_CSUM_FEATURES;
1865                 }
1866                 if ((mask & IFCAP_RXCSUM) != 0 &&
1867                     (ifp->if_capabilities & IFCAP_RXCSUM) != 0) {
1868                         ifp->if_capenable ^= IFCAP_RXCSUM;
1869                         reg = CSR_READ_4(sc, AGE_MAC_CFG);
1870                         reg &= ~MAC_CFG_RXCSUM_ENB;
1871                         if ((ifp->if_capenable & IFCAP_RXCSUM) != 0)
1872                                 reg |= MAC_CFG_RXCSUM_ENB;
1873                         CSR_WRITE_4(sc, AGE_MAC_CFG, reg);
1874                 }
1875                 if ((mask & IFCAP_TSO4) != 0 &&
1876                     (ifp->if_capabilities & IFCAP_TSO4) != 0) {
1877                         ifp->if_capenable ^= IFCAP_TSO4;
1878                         if ((ifp->if_capenable & IFCAP_TSO4) != 0)
1879                                 ifp->if_hwassist |= CSUM_TSO;
1880                         else
1881                                 ifp->if_hwassist &= ~CSUM_TSO;
1882                 }
1883
1884                 if ((mask & IFCAP_WOL_MCAST) != 0 &&
1885                     (ifp->if_capabilities & IFCAP_WOL_MCAST) != 0)
1886                         ifp->if_capenable ^= IFCAP_WOL_MCAST;
1887                 if ((mask & IFCAP_WOL_MAGIC) != 0 &&
1888                     (ifp->if_capabilities & IFCAP_WOL_MAGIC) != 0)
1889                         ifp->if_capenable ^= IFCAP_WOL_MAGIC;
1890                 if ((mask & IFCAP_VLAN_HWCSUM) != 0 &&
1891                     (ifp->if_capabilities & IFCAP_VLAN_HWCSUM) != 0)
1892                         ifp->if_capenable ^= IFCAP_VLAN_HWCSUM;
1893                 if ((mask & IFCAP_VLAN_HWTSO) != 0 &&
1894                     (ifp->if_capabilities & IFCAP_VLAN_HWTSO) != 0)
1895                         ifp->if_capenable ^= IFCAP_VLAN_HWTSO;
1896                 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 &&
1897                     (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) != 0) {
1898                         ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
1899                         if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) == 0)
1900                                 ifp->if_capenable &= ~IFCAP_VLAN_HWTSO;
1901                         age_rxvlan(sc);
1902                 }
1903                 AGE_UNLOCK(sc);
1904                 VLAN_CAPABILITIES(ifp);
1905                 break;
1906         default:
1907                 error = ether_ioctl(ifp, cmd, data);
1908                 break;
1909         }
1910
1911         return (error);
1912 }
1913
1914 static void
1915 age_mac_config(struct age_softc *sc)
1916 {
1917         struct mii_data *mii;
1918         uint32_t reg;
1919
1920         AGE_LOCK_ASSERT(sc);
1921
1922         mii = device_get_softc(sc->age_miibus);
1923         reg = CSR_READ_4(sc, AGE_MAC_CFG);
1924         reg &= ~MAC_CFG_FULL_DUPLEX;
1925         reg &= ~(MAC_CFG_TX_FC | MAC_CFG_RX_FC);
1926         reg &= ~MAC_CFG_SPEED_MASK;
1927         /* Reprogram MAC with resolved speed/duplex. */
1928         switch (IFM_SUBTYPE(mii->mii_media_active)) {
1929         case IFM_10_T:
1930         case IFM_100_TX:
1931                 reg |= MAC_CFG_SPEED_10_100;
1932                 break;
1933         case IFM_1000_T:
1934                 reg |= MAC_CFG_SPEED_1000;
1935                 break;
1936         }
1937         if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) {
1938                 reg |= MAC_CFG_FULL_DUPLEX;
1939 #ifdef notyet
1940                 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0)
1941                         reg |= MAC_CFG_TX_FC;
1942                 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0)
1943                         reg |= MAC_CFG_RX_FC;
1944 #endif
1945         }
1946
1947         CSR_WRITE_4(sc, AGE_MAC_CFG, reg);
1948 }
1949
1950 static void
1951 age_link_task(void *arg, int pending)
1952 {
1953         struct age_softc *sc;
1954         struct mii_data *mii;
1955         struct ifnet *ifp;
1956         uint32_t reg;
1957
1958         sc = (struct age_softc *)arg;
1959
1960         AGE_LOCK(sc);
1961         mii = device_get_softc(sc->age_miibus);
1962         ifp = sc->age_ifp;
1963         if (mii == NULL || ifp == NULL ||
1964             (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
1965                 AGE_UNLOCK(sc);
1966                 return;
1967         }
1968
1969         sc->age_flags &= ~AGE_FLAG_LINK;
1970         if ((mii->mii_media_status & IFM_AVALID) != 0) {
1971                 switch (IFM_SUBTYPE(mii->mii_media_active)) {
1972                 case IFM_10_T:
1973                 case IFM_100_TX:
1974                 case IFM_1000_T:
1975                         sc->age_flags |= AGE_FLAG_LINK;
1976                         break;
1977                 default:
1978                         break;
1979                 }
1980         }
1981
1982         /* Stop Rx/Tx MACs. */
1983         age_stop_rxmac(sc);
1984         age_stop_txmac(sc);
1985
1986         /* Program MACs with resolved speed/duplex/flow-control. */
1987         if ((sc->age_flags & AGE_FLAG_LINK) != 0) {
1988                 age_mac_config(sc);
1989                 reg = CSR_READ_4(sc, AGE_MAC_CFG);
1990                 /* Restart DMA engine and Tx/Rx MAC. */
1991                 CSR_WRITE_4(sc, AGE_DMA_CFG, CSR_READ_4(sc, AGE_DMA_CFG) |
1992                     DMA_CFG_RD_ENB | DMA_CFG_WR_ENB);
1993                 reg |= MAC_CFG_TX_ENB | MAC_CFG_RX_ENB;
1994                 CSR_WRITE_4(sc, AGE_MAC_CFG, reg);
1995         }
1996
1997         AGE_UNLOCK(sc);
1998 }
1999
2000 static void
2001 age_stats_update(struct age_softc *sc)
2002 {
2003         struct age_stats *stat;
2004         struct smb *smb;
2005         struct ifnet *ifp;
2006
2007         AGE_LOCK_ASSERT(sc);
2008
2009         stat = &sc->age_stat;
2010
2011         bus_dmamap_sync(sc->age_cdata.age_smb_block_tag,
2012             sc->age_cdata.age_smb_block_map,
2013             BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2014
2015         smb = sc->age_rdata.age_smb_block;
2016         if (smb->updated == 0)
2017                 return;
2018
2019         ifp = sc->age_ifp;
2020         /* Rx stats. */
2021         stat->rx_frames += smb->rx_frames;
2022         stat->rx_bcast_frames += smb->rx_bcast_frames;
2023         stat->rx_mcast_frames += smb->rx_mcast_frames;
2024         stat->rx_pause_frames += smb->rx_pause_frames;
2025         stat->rx_control_frames += smb->rx_control_frames;
2026         stat->rx_crcerrs += smb->rx_crcerrs;
2027         stat->rx_lenerrs += smb->rx_lenerrs;
2028         stat->rx_bytes += smb->rx_bytes;
2029         stat->rx_runts += smb->rx_runts;
2030         stat->rx_fragments += smb->rx_fragments;
2031         stat->rx_pkts_64 += smb->rx_pkts_64;
2032         stat->rx_pkts_65_127 += smb->rx_pkts_65_127;
2033         stat->rx_pkts_128_255 += smb->rx_pkts_128_255;
2034         stat->rx_pkts_256_511 += smb->rx_pkts_256_511;
2035         stat->rx_pkts_512_1023 += smb->rx_pkts_512_1023;
2036         stat->rx_pkts_1024_1518 += smb->rx_pkts_1024_1518;
2037         stat->rx_pkts_1519_max += smb->rx_pkts_1519_max;
2038         stat->rx_pkts_truncated += smb->rx_pkts_truncated;
2039         stat->rx_fifo_oflows += smb->rx_fifo_oflows;
2040         stat->rx_desc_oflows += smb->rx_desc_oflows;
2041         stat->rx_alignerrs += smb->rx_alignerrs;
2042         stat->rx_bcast_bytes += smb->rx_bcast_bytes;
2043         stat->rx_mcast_bytes += smb->rx_mcast_bytes;
2044         stat->rx_pkts_filtered += smb->rx_pkts_filtered;
2045
2046         /* Tx stats. */
2047         stat->tx_frames += smb->tx_frames;
2048         stat->tx_bcast_frames += smb->tx_bcast_frames;
2049         stat->tx_mcast_frames += smb->tx_mcast_frames;
2050         stat->tx_pause_frames += smb->tx_pause_frames;
2051         stat->tx_excess_defer += smb->tx_excess_defer;
2052         stat->tx_control_frames += smb->tx_control_frames;
2053         stat->tx_deferred += smb->tx_deferred;
2054         stat->tx_bytes += smb->tx_bytes;
2055         stat->tx_pkts_64 += smb->tx_pkts_64;
2056         stat->tx_pkts_65_127 += smb->tx_pkts_65_127;
2057         stat->tx_pkts_128_255 += smb->tx_pkts_128_255;
2058         stat->tx_pkts_256_511 += smb->tx_pkts_256_511;
2059         stat->tx_pkts_512_1023 += smb->tx_pkts_512_1023;
2060         stat->tx_pkts_1024_1518 += smb->tx_pkts_1024_1518;
2061         stat->tx_pkts_1519_max += smb->tx_pkts_1519_max;
2062         stat->tx_single_colls += smb->tx_single_colls;
2063         stat->tx_multi_colls += smb->tx_multi_colls;
2064         stat->tx_late_colls += smb->tx_late_colls;
2065         stat->tx_excess_colls += smb->tx_excess_colls;
2066         stat->tx_underrun += smb->tx_underrun;
2067         stat->tx_desc_underrun += smb->tx_desc_underrun;
2068         stat->tx_lenerrs += smb->tx_lenerrs;
2069         stat->tx_pkts_truncated += smb->tx_pkts_truncated;
2070         stat->tx_bcast_bytes += smb->tx_bcast_bytes;
2071         stat->tx_mcast_bytes += smb->tx_mcast_bytes;
2072
2073         /* Update counters in ifnet. */
2074         ifp->if_opackets += smb->tx_frames;
2075
2076         ifp->if_collisions += smb->tx_single_colls +
2077             smb->tx_multi_colls + smb->tx_late_colls +
2078             smb->tx_excess_colls * HDPX_CFG_RETRY_DEFAULT;
2079
2080         ifp->if_oerrors += smb->tx_excess_colls +
2081             smb->tx_late_colls + smb->tx_underrun +
2082             smb->tx_pkts_truncated;
2083
2084         ifp->if_ipackets += smb->rx_frames;
2085
2086         ifp->if_ierrors += smb->rx_crcerrs + smb->rx_lenerrs +
2087             smb->rx_runts + smb->rx_pkts_truncated +
2088             smb->rx_fifo_oflows + smb->rx_desc_oflows +
2089             smb->rx_alignerrs;
2090
2091         /* Update done, clear. */
2092         smb->updated = 0;
2093
2094         bus_dmamap_sync(sc->age_cdata.age_smb_block_tag,
2095             sc->age_cdata.age_smb_block_map,
2096             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2097 }
2098
2099 static int
2100 age_intr(void *arg)
2101 {
2102         struct age_softc *sc;
2103         uint32_t status;
2104
2105         sc = (struct age_softc *)arg;
2106
2107         status = CSR_READ_4(sc, AGE_INTR_STATUS);
2108         if (status == 0 || (status & AGE_INTRS) == 0)
2109                 return (FILTER_STRAY);
2110         /* Disable interrupts. */
2111         CSR_WRITE_4(sc, AGE_INTR_STATUS, status | INTR_DIS_INT);
2112         taskqueue_enqueue(sc->age_tq, &sc->age_int_task);
2113
2114         return (FILTER_HANDLED);
2115 }
2116
2117 static void
2118 age_int_task(void *arg, int pending)
2119 {
2120         struct age_softc *sc;
2121         struct ifnet *ifp;
2122         struct cmb *cmb;
2123         uint32_t status;
2124
2125         sc = (struct age_softc *)arg;
2126
2127         AGE_LOCK(sc);
2128
2129         bus_dmamap_sync(sc->age_cdata.age_cmb_block_tag,
2130             sc->age_cdata.age_cmb_block_map,
2131             BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2132         cmb = sc->age_rdata.age_cmb_block;
2133         status = le32toh(cmb->intr_status);
2134         if (sc->age_morework != 0)
2135                 status |= INTR_CMB_RX;
2136         if ((status & AGE_INTRS) == 0)
2137                 goto done;
2138
2139         sc->age_tpd_cons = (le32toh(cmb->tpd_cons) & TPD_CONS_MASK) >>
2140             TPD_CONS_SHIFT;
2141         sc->age_rr_prod = (le32toh(cmb->rprod_cons) & RRD_PROD_MASK) >>
2142             RRD_PROD_SHIFT;
2143         /* Let hardware know CMB was served. */
2144         cmb->intr_status = 0;
2145         bus_dmamap_sync(sc->age_cdata.age_cmb_block_tag,
2146             sc->age_cdata.age_cmb_block_map,
2147             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2148
2149 #if 0
2150         printf("INTR: 0x%08x\n", status);
2151         status &= ~INTR_DIS_DMA;
2152         CSR_WRITE_4(sc, AGE_INTR_STATUS, status | INTR_DIS_INT);
2153 #endif
2154         ifp = sc->age_ifp;
2155         if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
2156                 if ((status & INTR_CMB_RX) != 0)
2157                         sc->age_morework = age_rxintr(sc, sc->age_rr_prod,
2158                             sc->age_process_limit);
2159                 if ((status & INTR_CMB_TX) != 0)
2160                         age_txintr(sc, sc->age_tpd_cons);
2161                 if ((status & (INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST)) != 0) {
2162                         if ((status & INTR_DMA_RD_TO_RST) != 0)
2163                                 device_printf(sc->age_dev,
2164                                     "DMA read error! -- resetting\n");
2165                         if ((status & INTR_DMA_WR_TO_RST) != 0)
2166                                 device_printf(sc->age_dev,
2167                                     "DMA write error! -- resetting\n");
2168                         age_init_locked(sc);
2169                 }
2170                 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
2171                         taskqueue_enqueue(sc->age_tq, &sc->age_tx_task);
2172                 if ((status & INTR_SMB) != 0)
2173                         age_stats_update(sc);
2174         }
2175
2176         /* Check whether CMB was updated while serving Tx/Rx/SMB handler. */
2177         bus_dmamap_sync(sc->age_cdata.age_cmb_block_tag,
2178             sc->age_cdata.age_cmb_block_map,
2179             BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2180         status = le32toh(cmb->intr_status);
2181         if (sc->age_morework != 0 || (status & AGE_INTRS) != 0) {
2182                 taskqueue_enqueue(sc->age_tq, &sc->age_int_task);
2183                 AGE_UNLOCK(sc);
2184                 return;
2185         }
2186
2187 done:
2188         /* Re-enable interrupts. */
2189         CSR_WRITE_4(sc, AGE_INTR_STATUS, 0);
2190         AGE_UNLOCK(sc);
2191 }
2192
2193 static void
2194 age_txintr(struct age_softc *sc, int tpd_cons)
2195 {
2196         struct ifnet *ifp;
2197         struct age_txdesc *txd;
2198         int cons, prog;
2199
2200         AGE_LOCK_ASSERT(sc);
2201
2202         ifp = sc->age_ifp;
2203
2204         bus_dmamap_sync(sc->age_cdata.age_tx_ring_tag,
2205             sc->age_cdata.age_tx_ring_map,
2206             BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2207
2208         /*
2209          * Go through our Tx list and free mbufs for those
2210          * frames which have been transmitted.
2211          */
2212         cons = sc->age_cdata.age_tx_cons;
2213         for (prog = 0; cons != tpd_cons; AGE_DESC_INC(cons, AGE_TX_RING_CNT)) {
2214                 if (sc->age_cdata.age_tx_cnt <= 0)
2215                         break;
2216                 prog++;
2217                 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2218                 sc->age_cdata.age_tx_cnt--;
2219                 txd = &sc->age_cdata.age_txdesc[cons];
2220                 /*
2221                  * Clear Tx descriptors, it's not required but would
2222                  * help debugging in case of Tx issues.
2223                  */
2224                 txd->tx_desc->addr = 0;
2225                 txd->tx_desc->len = 0;
2226                 txd->tx_desc->flags = 0;
2227
2228                 if (txd->tx_m == NULL)
2229                         continue;
2230                 /* Reclaim transmitted mbufs. */
2231                 bus_dmamap_sync(sc->age_cdata.age_tx_tag, txd->tx_dmamap,
2232                     BUS_DMASYNC_POSTWRITE);
2233                 bus_dmamap_unload(sc->age_cdata.age_tx_tag, txd->tx_dmamap);
2234                 m_freem(txd->tx_m);
2235                 txd->tx_m = NULL;
2236         }
2237
2238         if (prog > 0) {
2239                 sc->age_cdata.age_tx_cons = cons;
2240
2241                 /*
2242                  * Unarm watchdog timer only when there are no pending
2243                  * Tx descriptors in queue.
2244                  */
2245                 if (sc->age_cdata.age_tx_cnt == 0)
2246                         sc->age_watchdog_timer = 0;
2247                 bus_dmamap_sync(sc->age_cdata.age_tx_ring_tag,
2248                     sc->age_cdata.age_tx_ring_map,
2249                     BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2250         }
2251 }
2252
2253 /* Receive a frame. */
2254 static void
2255 age_rxeof(struct age_softc *sc, struct rx_rdesc *rxrd)
2256 {
2257         struct age_rxdesc *rxd;
2258         struct rx_desc *desc;
2259         struct ifnet *ifp;
2260         struct mbuf *mp, *m;
2261         uint32_t status, index, vtag;
2262         int count, nsegs, pktlen;
2263         int rx_cons;
2264
2265         AGE_LOCK_ASSERT(sc);
2266
2267         ifp = sc->age_ifp;
2268         status = le32toh(rxrd->flags);
2269         index = le32toh(rxrd->index);
2270         rx_cons = AGE_RX_CONS(index);
2271         nsegs = AGE_RX_NSEGS(index);
2272
2273         sc->age_cdata.age_rxlen = AGE_RX_BYTES(le32toh(rxrd->len));
2274         if ((status & AGE_RRD_ERROR) != 0 &&
2275             (status & (AGE_RRD_CRC | AGE_RRD_CODE | AGE_RRD_DRIBBLE |
2276             AGE_RRD_RUNT | AGE_RRD_OFLOW | AGE_RRD_TRUNC)) != 0) {
2277                 /*
2278                  * We want to pass the following frames to upper
2279                  * layer regardless of error status of Rx return
2280                  * ring.
2281                  *
2282                  *  o IP/TCP/UDP checksum is bad.
2283                  *  o frame length and protocol specific length
2284                  *     does not match.
2285                  */
2286                 sc->age_cdata.age_rx_cons += nsegs;
2287                 sc->age_cdata.age_rx_cons %= AGE_RX_RING_CNT;
2288                 return;
2289         }
2290
2291         pktlen = 0;
2292         for (count = 0; count < nsegs; count++,
2293             AGE_DESC_INC(rx_cons, AGE_RX_RING_CNT)) {
2294                 rxd = &sc->age_cdata.age_rxdesc[rx_cons];
2295                 mp = rxd->rx_m;
2296                 desc = rxd->rx_desc;
2297                 /* Add a new receive buffer to the ring. */
2298                 if (age_newbuf(sc, rxd) != 0) {
2299                         ifp->if_iqdrops++;
2300                         /* Reuse Rx buffers. */
2301                         if (sc->age_cdata.age_rxhead != NULL) {
2302                                 m_freem(sc->age_cdata.age_rxhead);
2303                                 AGE_RXCHAIN_RESET(sc);
2304                         }
2305                         break;
2306                 }
2307
2308                 /* The length of the first mbuf is computed last. */
2309                 if (count != 0) {
2310                         mp->m_len = AGE_RX_BYTES(le32toh(desc->len));
2311                         pktlen += mp->m_len;
2312                 }
2313
2314                 /* Chain received mbufs. */
2315                 if (sc->age_cdata.age_rxhead == NULL) {
2316                         sc->age_cdata.age_rxhead = mp;
2317                         sc->age_cdata.age_rxtail = mp;
2318                 } else {
2319                         mp->m_flags &= ~M_PKTHDR;
2320                         sc->age_cdata.age_rxprev_tail =
2321                             sc->age_cdata.age_rxtail;
2322                         sc->age_cdata.age_rxtail->m_next = mp;
2323                         sc->age_cdata.age_rxtail = mp;
2324                 }
2325
2326                 if (count == nsegs - 1) {
2327                         /*
2328                          * It seems that L1 controller has no way
2329                          * to tell hardware to strip CRC bytes.
2330                          */
2331                         sc->age_cdata.age_rxlen -= ETHER_CRC_LEN;
2332                         if (nsegs > 1) {
2333                                 /* Remove the CRC bytes in chained mbufs. */
2334                                 pktlen -= ETHER_CRC_LEN;
2335                                 if (mp->m_len <= ETHER_CRC_LEN) {
2336                                         sc->age_cdata.age_rxtail =
2337                                             sc->age_cdata.age_rxprev_tail;
2338                                         sc->age_cdata.age_rxtail->m_len -=
2339                                             (ETHER_CRC_LEN - mp->m_len);
2340                                         sc->age_cdata.age_rxtail->m_next = NULL;
2341                                         m_freem(mp);
2342                                 } else {
2343                                         mp->m_len -= ETHER_CRC_LEN;
2344                                 }
2345                         }
2346
2347                         m = sc->age_cdata.age_rxhead;
2348                         m->m_flags |= M_PKTHDR;
2349                         m->m_pkthdr.rcvif = ifp;
2350                         m->m_pkthdr.len = sc->age_cdata.age_rxlen;
2351                         /* Set the first mbuf length. */
2352                         m->m_len = sc->age_cdata.age_rxlen - pktlen;
2353
2354                         /*
2355                          * Set checksum information.
2356                          * It seems that L1 controller can compute partial
2357                          * checksum. The partial checksum value can be used
2358                          * to accelerate checksum computation for fragmented
2359                          * TCP/UDP packets. Upper network stack already
2360                          * takes advantage of the partial checksum value in
2361                          * IP reassembly stage. But I'm not sure the
2362                          * correctness of the partial hardware checksum
2363                          * assistance due to lack of data sheet. If it is
2364                          * proven to work on L1 I'll enable it.
2365                          */
2366                         if ((ifp->if_capenable & IFCAP_RXCSUM) != 0 &&
2367                             (status & AGE_RRD_IPV4) != 0) {
2368                                 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
2369                                 if ((status & AGE_RRD_IPCSUM_NOK) == 0)
2370                                         m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
2371                                 if ((status & (AGE_RRD_TCP | AGE_RRD_UDP)) &&
2372                                     (status & AGE_RRD_TCP_UDPCSUM_NOK) == 0) {
2373                                         m->m_pkthdr.csum_flags |=
2374                                             CSUM_DATA_VALID | CSUM_PSEUDO_HDR;
2375                                         m->m_pkthdr.csum_data = 0xffff;
2376                                 }
2377                                 /*
2378                                  * Don't mark bad checksum for TCP/UDP frames
2379                                  * as fragmented frames may always have set
2380                                  * bad checksummed bit of descriptor status.
2381                                  */
2382                         }
2383
2384                         /* Check for VLAN tagged frames. */
2385                         if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0 &&
2386                             (status & AGE_RRD_VLAN) != 0) {
2387                                 vtag = AGE_RX_VLAN(le32toh(rxrd->vtags));
2388                                 m->m_pkthdr.ether_vtag = AGE_RX_VLAN_TAG(vtag);
2389                                 m->m_flags |= M_VLANTAG;
2390                         }
2391
2392                         /* Pass it on. */
2393                         AGE_UNLOCK(sc);
2394                         (*ifp->if_input)(ifp, m);
2395                         AGE_LOCK(sc);
2396
2397                         /* Reset mbuf chains. */
2398                         AGE_RXCHAIN_RESET(sc);
2399                 }
2400         }
2401
2402         if (count != nsegs) {
2403                 sc->age_cdata.age_rx_cons += nsegs;
2404                 sc->age_cdata.age_rx_cons %= AGE_RX_RING_CNT;
2405         } else
2406                 sc->age_cdata.age_rx_cons = rx_cons;
2407 }
2408
2409 static int
2410 age_rxintr(struct age_softc *sc, int rr_prod, int count)
2411 {
2412         struct rx_rdesc *rxrd;
2413         int rr_cons, nsegs, pktlen, prog;
2414
2415         AGE_LOCK_ASSERT(sc);
2416
2417         rr_cons = sc->age_cdata.age_rr_cons;
2418         if (rr_cons == rr_prod)
2419                 return (0);
2420
2421         bus_dmamap_sync(sc->age_cdata.age_rr_ring_tag,
2422             sc->age_cdata.age_rr_ring_map,
2423             BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2424
2425         for (prog = 0; rr_cons != rr_prod; prog++) {
2426                 if (count <= 0)
2427                         break;
2428                 rxrd = &sc->age_rdata.age_rr_ring[rr_cons];
2429                 nsegs = AGE_RX_NSEGS(le32toh(rxrd->index));
2430                 if (nsegs == 0)
2431                         break;
2432                 /*
2433                  * Check number of segments against received bytes.
2434                  * Non-matching value would indicate that hardware
2435                  * is still trying to update Rx return descriptors.
2436                  * I'm not sure whether this check is really needed.
2437                  */
2438                 pktlen = AGE_RX_BYTES(le32toh(rxrd->len));
2439                 if (nsegs != ((pktlen + (MCLBYTES - ETHER_ALIGN - 1)) /
2440                     (MCLBYTES - ETHER_ALIGN)))
2441                         break;
2442
2443                 prog++;
2444                 /* Received a frame. */
2445                 age_rxeof(sc, rxrd);
2446                 /* Clear return ring. */
2447                 rxrd->index = 0;
2448                 AGE_DESC_INC(rr_cons, AGE_RR_RING_CNT);
2449         }
2450
2451         if (prog > 0) {
2452                 /* Update the consumer index. */
2453                 sc->age_cdata.age_rr_cons = rr_cons;
2454
2455                 /* Sync descriptors. */
2456                 bus_dmamap_sync(sc->age_cdata.age_rr_ring_tag,
2457                     sc->age_cdata.age_rr_ring_map,
2458                     BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2459
2460                 /* Notify hardware availability of new Rx buffers. */
2461                 AGE_COMMIT_MBOX(sc);
2462         }
2463
2464         return (count > 0 ? 0 : EAGAIN);
2465 }
2466
2467 static void
2468 age_tick(void *arg)
2469 {
2470         struct age_softc *sc;
2471         struct mii_data *mii;
2472
2473         sc = (struct age_softc *)arg;
2474
2475         AGE_LOCK_ASSERT(sc);
2476
2477         mii = device_get_softc(sc->age_miibus);
2478         mii_tick(mii);
2479         age_watchdog(sc);
2480         callout_reset(&sc->age_tick_ch, hz, age_tick, sc);
2481 }
2482
2483 static void
2484 age_reset(struct age_softc *sc)
2485 {
2486         uint32_t reg;
2487         int i;
2488
2489         CSR_WRITE_4(sc, AGE_MASTER_CFG, MASTER_RESET);
2490         CSR_READ_4(sc, AGE_MASTER_CFG);
2491         DELAY(1000);
2492         for (i = AGE_RESET_TIMEOUT; i > 0; i--) {
2493                 if ((reg = CSR_READ_4(sc, AGE_IDLE_STATUS)) == 0)
2494                         break;
2495                 DELAY(10);
2496         }
2497
2498         if (i == 0)
2499                 device_printf(sc->age_dev, "reset timeout(0x%08x)!\n", reg);
2500         /* Initialize PCIe module. From Linux. */
2501         CSR_WRITE_4(sc, 0x12FC, 0x6500);
2502         CSR_WRITE_4(sc, 0x1008, CSR_READ_4(sc, 0x1008) | 0x8000);
2503 }
2504
2505 static void
2506 age_init(void *xsc)
2507 {
2508         struct age_softc *sc;
2509
2510         sc = (struct age_softc *)xsc;
2511         AGE_LOCK(sc);
2512         age_init_locked(sc);
2513         AGE_UNLOCK(sc);
2514 }
2515
2516 static void
2517 age_init_locked(struct age_softc *sc)
2518 {
2519         struct ifnet *ifp;
2520         struct mii_data *mii;
2521         uint8_t eaddr[ETHER_ADDR_LEN];
2522         bus_addr_t paddr;
2523         uint32_t reg, fsize;
2524         uint32_t rxf_hi, rxf_lo, rrd_hi, rrd_lo;
2525         int error;
2526
2527         AGE_LOCK_ASSERT(sc);
2528
2529         ifp = sc->age_ifp;
2530         mii = device_get_softc(sc->age_miibus);
2531
2532         /*
2533          * Cancel any pending I/O.
2534          */
2535         age_stop(sc);
2536
2537         /*
2538          * Reset the chip to a known state.
2539          */
2540         age_reset(sc);
2541
2542         /* Initialize descriptors. */
2543         error = age_init_rx_ring(sc);
2544         if (error != 0) {
2545                 device_printf(sc->age_dev, "no memory for Rx buffers.\n");
2546                 age_stop(sc);
2547                 return;
2548         }
2549         age_init_rr_ring(sc);
2550         age_init_tx_ring(sc);
2551         age_init_cmb_block(sc);
2552         age_init_smb_block(sc);
2553
2554         /* Reprogram the station address. */
2555         bcopy(IF_LLADDR(ifp), eaddr, ETHER_ADDR_LEN);
2556         CSR_WRITE_4(sc, AGE_PAR0,
2557             eaddr[2] << 24 | eaddr[3] << 16 | eaddr[4] << 8 | eaddr[5]);
2558         CSR_WRITE_4(sc, AGE_PAR1, eaddr[0] << 8 | eaddr[1]);
2559
2560         /* Set descriptor base addresses. */
2561         paddr = sc->age_rdata.age_tx_ring_paddr;
2562         CSR_WRITE_4(sc, AGE_DESC_ADDR_HI, AGE_ADDR_HI(paddr));
2563         paddr = sc->age_rdata.age_rx_ring_paddr;
2564         CSR_WRITE_4(sc, AGE_DESC_RD_ADDR_LO, AGE_ADDR_LO(paddr));
2565         paddr = sc->age_rdata.age_rr_ring_paddr;
2566         CSR_WRITE_4(sc, AGE_DESC_RRD_ADDR_LO, AGE_ADDR_LO(paddr));
2567         paddr = sc->age_rdata.age_tx_ring_paddr;
2568         CSR_WRITE_4(sc, AGE_DESC_TPD_ADDR_LO, AGE_ADDR_LO(paddr));
2569         paddr = sc->age_rdata.age_cmb_block_paddr;
2570         CSR_WRITE_4(sc, AGE_DESC_CMB_ADDR_LO, AGE_ADDR_LO(paddr));
2571         paddr = sc->age_rdata.age_smb_block_paddr;
2572         CSR_WRITE_4(sc, AGE_DESC_SMB_ADDR_LO, AGE_ADDR_LO(paddr));
2573         /* Set Rx/Rx return descriptor counter. */
2574         CSR_WRITE_4(sc, AGE_DESC_RRD_RD_CNT,
2575             ((AGE_RR_RING_CNT << DESC_RRD_CNT_SHIFT) &
2576             DESC_RRD_CNT_MASK) |
2577             ((AGE_RX_RING_CNT << DESC_RD_CNT_SHIFT) & DESC_RD_CNT_MASK));
2578         /* Set Tx descriptor counter. */
2579         CSR_WRITE_4(sc, AGE_DESC_TPD_CNT,
2580             (AGE_TX_RING_CNT << DESC_TPD_CNT_SHIFT) & DESC_TPD_CNT_MASK);
2581
2582         /* Tell hardware that we're ready to load descriptors. */
2583         CSR_WRITE_4(sc, AGE_DMA_BLOCK, DMA_BLOCK_LOAD);
2584
2585         /*
2586          * Initialize mailbox register.
2587          * Updated producer/consumer index information is exchanged
2588          * through this mailbox register. However Tx producer and
2589          * Rx return consumer/Rx producer are all shared such that
2590          * it's hard to separate code path between Tx and Rx without
2591          * locking. If L1 hardware have a separate mail box register
2592          * for Tx and Rx consumer/producer management we could have
2593          * indepent Tx/Rx handler which in turn Rx handler could have
2594          * been run without any locking.
2595          */
2596         AGE_COMMIT_MBOX(sc);
2597
2598         /* Configure IPG/IFG parameters. */
2599         CSR_WRITE_4(sc, AGE_IPG_IFG_CFG,
2600             ((IPG_IFG_IPG2_DEFAULT << IPG_IFG_IPG2_SHIFT) & IPG_IFG_IPG2_MASK) |
2601             ((IPG_IFG_IPG1_DEFAULT << IPG_IFG_IPG1_SHIFT) & IPG_IFG_IPG1_MASK) |
2602             ((IPG_IFG_MIFG_DEFAULT << IPG_IFG_MIFG_SHIFT) & IPG_IFG_MIFG_MASK) |
2603             ((IPG_IFG_IPGT_DEFAULT << IPG_IFG_IPGT_SHIFT) & IPG_IFG_IPGT_MASK));
2604
2605         /* Set parameters for half-duplex media. */
2606         CSR_WRITE_4(sc, AGE_HDPX_CFG,
2607             ((HDPX_CFG_LCOL_DEFAULT << HDPX_CFG_LCOL_SHIFT) &
2608             HDPX_CFG_LCOL_MASK) |
2609             ((HDPX_CFG_RETRY_DEFAULT << HDPX_CFG_RETRY_SHIFT) &
2610             HDPX_CFG_RETRY_MASK) | HDPX_CFG_EXC_DEF_EN |
2611             ((HDPX_CFG_ABEBT_DEFAULT << HDPX_CFG_ABEBT_SHIFT) &
2612             HDPX_CFG_ABEBT_MASK) |
2613             ((HDPX_CFG_JAMIPG_DEFAULT << HDPX_CFG_JAMIPG_SHIFT) &
2614             HDPX_CFG_JAMIPG_MASK));
2615
2616         /* Configure interrupt moderation timer. */
2617         CSR_WRITE_2(sc, AGE_IM_TIMER, AGE_USECS(sc->age_int_mod));
2618         reg = CSR_READ_4(sc, AGE_MASTER_CFG);
2619         reg &= ~MASTER_MTIMER_ENB;
2620         if (AGE_USECS(sc->age_int_mod) == 0)
2621                 reg &= ~MASTER_ITIMER_ENB;
2622         else
2623                 reg |= MASTER_ITIMER_ENB;
2624         CSR_WRITE_4(sc, AGE_MASTER_CFG, reg);
2625         if (bootverbose)
2626                 device_printf(sc->age_dev, "interrupt moderation is %d us.\n",
2627                     sc->age_int_mod);
2628         CSR_WRITE_2(sc, AGE_INTR_CLR_TIMER, AGE_USECS(1000));
2629
2630         /* Set Maximum frame size but don't let MTU be lass than ETHER_MTU. */
2631         if (ifp->if_mtu < ETHERMTU)
2632                 sc->age_max_frame_size = ETHERMTU;
2633         else
2634                 sc->age_max_frame_size = ifp->if_mtu;
2635         sc->age_max_frame_size += ETHER_HDR_LEN +
2636             sizeof(struct ether_vlan_header) + ETHER_CRC_LEN;
2637         CSR_WRITE_4(sc, AGE_FRAME_SIZE, sc->age_max_frame_size);
2638         /* Configure jumbo frame. */
2639         fsize = roundup(sc->age_max_frame_size, sizeof(uint64_t));
2640         CSR_WRITE_4(sc, AGE_RXQ_JUMBO_CFG,
2641             (((fsize / sizeof(uint64_t)) <<
2642             RXQ_JUMBO_CFG_SZ_THRESH_SHIFT) & RXQ_JUMBO_CFG_SZ_THRESH_MASK) |
2643             ((RXQ_JUMBO_CFG_LKAH_DEFAULT <<
2644             RXQ_JUMBO_CFG_LKAH_SHIFT) & RXQ_JUMBO_CFG_LKAH_MASK) |
2645             ((AGE_USECS(8) << RXQ_JUMBO_CFG_RRD_TIMER_SHIFT) &
2646             RXQ_JUMBO_CFG_RRD_TIMER_MASK));
2647
2648         /* Configure flow-control parameters. From Linux. */
2649         if ((sc->age_flags & AGE_FLAG_PCIE) != 0) {
2650                 /*
2651                  * Magic workaround for old-L1.
2652                  * Don't know which hw revision requires this magic.
2653                  */
2654                 CSR_WRITE_4(sc, 0x12FC, 0x6500);
2655                 /*
2656                  * Another magic workaround for flow-control mode
2657                  * change. From Linux.
2658                  */
2659                 CSR_WRITE_4(sc, 0x1008, CSR_READ_4(sc, 0x1008) | 0x8000);
2660         }
2661         /*
2662          * TODO
2663          *  Should understand pause parameter relationships between FIFO
2664          *  size and number of Rx descriptors and Rx return descriptors.
2665          *
2666          *  Magic parameters came from Linux.
2667          */
2668         switch (sc->age_chip_rev) {
2669         case 0x8001:
2670         case 0x9001:
2671         case 0x9002:
2672         case 0x9003:
2673                 rxf_hi = AGE_RX_RING_CNT / 16;
2674                 rxf_lo = (AGE_RX_RING_CNT * 7) / 8;
2675                 rrd_hi = (AGE_RR_RING_CNT * 7) / 8;
2676                 rrd_lo = AGE_RR_RING_CNT / 16;
2677                 break;
2678         default:
2679                 reg = CSR_READ_4(sc, AGE_SRAM_RX_FIFO_LEN);
2680                 rxf_lo = reg / 16;
2681                 if (rxf_lo < 192)
2682                         rxf_lo = 192;
2683                 rxf_hi = (reg * 7) / 8;
2684                 if (rxf_hi < rxf_lo)
2685                         rxf_hi = rxf_lo + 16;
2686                 reg = CSR_READ_4(sc, AGE_SRAM_RRD_LEN);
2687                 rrd_lo = reg / 8;
2688                 rrd_hi = (reg * 7) / 8;
2689                 if (rrd_lo < 2)
2690                         rrd_lo = 2;
2691                 if (rrd_hi < rrd_lo)
2692                         rrd_hi = rrd_lo + 3;
2693                 break;
2694         }
2695         CSR_WRITE_4(sc, AGE_RXQ_FIFO_PAUSE_THRESH,
2696             ((rxf_lo << RXQ_FIFO_PAUSE_THRESH_LO_SHIFT) &
2697             RXQ_FIFO_PAUSE_THRESH_LO_MASK) |
2698             ((rxf_hi << RXQ_FIFO_PAUSE_THRESH_HI_SHIFT) &
2699             RXQ_FIFO_PAUSE_THRESH_HI_MASK));
2700         CSR_WRITE_4(sc, AGE_RXQ_RRD_PAUSE_THRESH,
2701             ((rrd_lo << RXQ_RRD_PAUSE_THRESH_LO_SHIFT) &
2702             RXQ_RRD_PAUSE_THRESH_LO_MASK) |
2703             ((rrd_hi << RXQ_RRD_PAUSE_THRESH_HI_SHIFT) &
2704             RXQ_RRD_PAUSE_THRESH_HI_MASK));
2705
2706         /* Configure RxQ. */
2707         CSR_WRITE_4(sc, AGE_RXQ_CFG,
2708             ((RXQ_CFG_RD_BURST_DEFAULT << RXQ_CFG_RD_BURST_SHIFT) &
2709             RXQ_CFG_RD_BURST_MASK) |
2710             ((RXQ_CFG_RRD_BURST_THRESH_DEFAULT <<
2711             RXQ_CFG_RRD_BURST_THRESH_SHIFT) & RXQ_CFG_RRD_BURST_THRESH_MASK) |
2712             ((RXQ_CFG_RD_PREF_MIN_IPG_DEFAULT <<
2713             RXQ_CFG_RD_PREF_MIN_IPG_SHIFT) & RXQ_CFG_RD_PREF_MIN_IPG_MASK) |
2714             RXQ_CFG_CUT_THROUGH_ENB | RXQ_CFG_ENB);
2715
2716         /* Configure TxQ. */
2717         CSR_WRITE_4(sc, AGE_TXQ_CFG,
2718             ((TXQ_CFG_TPD_BURST_DEFAULT << TXQ_CFG_TPD_BURST_SHIFT) &
2719             TXQ_CFG_TPD_BURST_MASK) |
2720             ((TXQ_CFG_TX_FIFO_BURST_DEFAULT << TXQ_CFG_TX_FIFO_BURST_SHIFT) &
2721             TXQ_CFG_TX_FIFO_BURST_MASK) |
2722             ((TXQ_CFG_TPD_FETCH_DEFAULT <<
2723             TXQ_CFG_TPD_FETCH_THRESH_SHIFT) & TXQ_CFG_TPD_FETCH_THRESH_MASK) |
2724             TXQ_CFG_ENB);
2725
2726         CSR_WRITE_4(sc, AGE_TX_JUMBO_TPD_TH_IPG,
2727             (((fsize / sizeof(uint64_t) << TX_JUMBO_TPD_TH_SHIFT)) &
2728             TX_JUMBO_TPD_TH_MASK) |
2729             ((TX_JUMBO_TPD_IPG_DEFAULT << TX_JUMBO_TPD_IPG_SHIFT) &
2730             TX_JUMBO_TPD_IPG_MASK));
2731         /* Configure DMA parameters. */
2732         CSR_WRITE_4(sc, AGE_DMA_CFG,
2733             DMA_CFG_ENH_ORDER | DMA_CFG_RCB_64 |
2734             sc->age_dma_rd_burst | DMA_CFG_RD_ENB |
2735             sc->age_dma_wr_burst | DMA_CFG_WR_ENB);
2736
2737         /* Configure CMB DMA write threshold. */
2738         CSR_WRITE_4(sc, AGE_CMB_WR_THRESH,
2739             ((CMB_WR_THRESH_RRD_DEFAULT << CMB_WR_THRESH_RRD_SHIFT) &
2740             CMB_WR_THRESH_RRD_MASK) |
2741             ((CMB_WR_THRESH_TPD_DEFAULT << CMB_WR_THRESH_TPD_SHIFT) &
2742             CMB_WR_THRESH_TPD_MASK));
2743
2744         /* Set CMB/SMB timer and enable them. */
2745         CSR_WRITE_4(sc, AGE_CMB_WR_TIMER,
2746             ((AGE_USECS(2) << CMB_WR_TIMER_TX_SHIFT) & CMB_WR_TIMER_TX_MASK) |
2747             ((AGE_USECS(2) << CMB_WR_TIMER_RX_SHIFT) & CMB_WR_TIMER_RX_MASK));
2748         /* Request SMB updates for every seconds. */
2749         CSR_WRITE_4(sc, AGE_SMB_TIMER, AGE_USECS(1000 * 1000));
2750         CSR_WRITE_4(sc, AGE_CSMB_CTRL, CSMB_CTRL_SMB_ENB | CSMB_CTRL_CMB_ENB);
2751
2752         /*
2753          * Disable all WOL bits as WOL can interfere normal Rx
2754          * operation.
2755          */
2756         CSR_WRITE_4(sc, AGE_WOL_CFG, 0);
2757
2758         /*
2759          * Configure Tx/Rx MACs.
2760          *  - Auto-padding for short frames.
2761          *  - Enable CRC generation.
2762          *  Start with full-duplex/1000Mbps media. Actual reconfiguration
2763          *  of MAC is followed after link establishment.
2764          */
2765         CSR_WRITE_4(sc, AGE_MAC_CFG,
2766             MAC_CFG_TX_CRC_ENB | MAC_CFG_TX_AUTO_PAD |
2767             MAC_CFG_FULL_DUPLEX | MAC_CFG_SPEED_1000 |
2768             ((MAC_CFG_PREAMBLE_DEFAULT << MAC_CFG_PREAMBLE_SHIFT) &
2769             MAC_CFG_PREAMBLE_MASK));
2770         /* Set up the receive filter. */
2771         age_rxfilter(sc);
2772         age_rxvlan(sc);
2773
2774         reg = CSR_READ_4(sc, AGE_MAC_CFG);
2775         if ((ifp->if_capenable & IFCAP_RXCSUM) != 0)
2776                 reg |= MAC_CFG_RXCSUM_ENB;
2777
2778         /* Ack all pending interrupts and clear it. */
2779         CSR_WRITE_4(sc, AGE_INTR_STATUS, 0);
2780         CSR_WRITE_4(sc, AGE_INTR_MASK, AGE_INTRS);
2781
2782         /* Finally enable Tx/Rx MAC. */
2783         CSR_WRITE_4(sc, AGE_MAC_CFG, reg | MAC_CFG_TX_ENB | MAC_CFG_RX_ENB);
2784
2785         sc->age_flags &= ~AGE_FLAG_LINK;
2786         /* Switch to the current media. */
2787         mii_mediachg(mii);
2788
2789         callout_reset(&sc->age_tick_ch, hz, age_tick, sc);
2790
2791         ifp->if_drv_flags |= IFF_DRV_RUNNING;
2792         ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2793 }
2794
2795 static void
2796 age_stop(struct age_softc *sc)
2797 {
2798         struct ifnet *ifp;
2799         struct age_txdesc *txd;
2800         struct age_rxdesc *rxd;
2801         uint32_t reg;
2802         int i;
2803
2804         AGE_LOCK_ASSERT(sc);
2805         /*
2806          * Mark the interface down and cancel the watchdog timer.
2807          */
2808         ifp = sc->age_ifp;
2809         ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
2810         sc->age_flags &= ~AGE_FLAG_LINK;
2811         callout_stop(&sc->age_tick_ch);
2812         sc->age_watchdog_timer = 0;
2813
2814         /*
2815          * Disable interrupts.
2816          */
2817         CSR_WRITE_4(sc, AGE_INTR_MASK, 0);
2818         CSR_WRITE_4(sc, AGE_INTR_STATUS, 0xFFFFFFFF);
2819         /* Stop CMB/SMB updates. */
2820         CSR_WRITE_4(sc, AGE_CSMB_CTRL, 0);
2821         /* Stop Rx/Tx MAC. */
2822         age_stop_rxmac(sc);
2823         age_stop_txmac(sc);
2824         /* Stop DMA. */
2825         CSR_WRITE_4(sc, AGE_DMA_CFG,
2826             CSR_READ_4(sc, AGE_DMA_CFG) & ~(DMA_CFG_RD_ENB | DMA_CFG_WR_ENB));
2827         /* Stop TxQ/RxQ. */
2828         CSR_WRITE_4(sc, AGE_TXQ_CFG,
2829             CSR_READ_4(sc, AGE_TXQ_CFG) & ~TXQ_CFG_ENB);
2830         CSR_WRITE_4(sc, AGE_RXQ_CFG,
2831             CSR_READ_4(sc, AGE_RXQ_CFG) & ~RXQ_CFG_ENB);
2832         for (i = AGE_RESET_TIMEOUT; i > 0; i--) {
2833                 if ((reg = CSR_READ_4(sc, AGE_IDLE_STATUS)) == 0)
2834                         break;
2835                 DELAY(10);
2836         }
2837         if (i == 0)
2838                 device_printf(sc->age_dev,
2839                     "stopping Rx/Tx MACs timed out(0x%08x)!\n", reg);
2840
2841          /* Reclaim Rx buffers that have been processed. */
2842         if (sc->age_cdata.age_rxhead != NULL)
2843                 m_freem(sc->age_cdata.age_rxhead);
2844         AGE_RXCHAIN_RESET(sc);
2845         /*
2846          * Free RX and TX mbufs still in the queues.
2847          */
2848         for (i = 0; i < AGE_RX_RING_CNT; i++) {
2849                 rxd = &sc->age_cdata.age_rxdesc[i];
2850                 if (rxd->rx_m != NULL) {
2851                         bus_dmamap_sync(sc->age_cdata.age_rx_tag,
2852                             rxd->rx_dmamap, BUS_DMASYNC_POSTREAD);
2853                         bus_dmamap_unload(sc->age_cdata.age_rx_tag,
2854                             rxd->rx_dmamap);
2855                         m_freem(rxd->rx_m);
2856                         rxd->rx_m = NULL;
2857                 }
2858         }
2859         for (i = 0; i < AGE_TX_RING_CNT; i++) {
2860                 txd = &sc->age_cdata.age_txdesc[i];
2861                 if (txd->tx_m != NULL) {
2862                         bus_dmamap_sync(sc->age_cdata.age_tx_tag,
2863                             txd->tx_dmamap, BUS_DMASYNC_POSTWRITE);
2864                         bus_dmamap_unload(sc->age_cdata.age_tx_tag,
2865                             txd->tx_dmamap);
2866                         m_freem(txd->tx_m);
2867                         txd->tx_m = NULL;
2868                 }
2869         }
2870 }
2871
2872 static void
2873 age_stop_txmac(struct age_softc *sc)
2874 {
2875         uint32_t reg;
2876         int i;
2877
2878         AGE_LOCK_ASSERT(sc);
2879
2880         reg = CSR_READ_4(sc, AGE_MAC_CFG);
2881         if ((reg & MAC_CFG_TX_ENB) != 0) {
2882                 reg &= ~MAC_CFG_TX_ENB;
2883                 CSR_WRITE_4(sc, AGE_MAC_CFG, reg);
2884         }
2885         /* Stop Tx DMA engine. */
2886         reg = CSR_READ_4(sc, AGE_DMA_CFG);
2887         if ((reg & DMA_CFG_RD_ENB) != 0) {
2888                 reg &= ~DMA_CFG_RD_ENB;
2889                 CSR_WRITE_4(sc, AGE_DMA_CFG, reg);
2890         }
2891         for (i = AGE_RESET_TIMEOUT; i > 0; i--) {
2892                 if ((CSR_READ_4(sc, AGE_IDLE_STATUS) &
2893                     (IDLE_STATUS_TXMAC | IDLE_STATUS_DMARD)) == 0)
2894                         break;
2895                 DELAY(10);
2896         }
2897         if (i == 0)
2898                 device_printf(sc->age_dev, "stopping TxMAC timeout!\n");
2899 }
2900
2901 static void
2902 age_stop_rxmac(struct age_softc *sc)
2903 {
2904         uint32_t reg;
2905         int i;
2906
2907         AGE_LOCK_ASSERT(sc);
2908
2909         reg = CSR_READ_4(sc, AGE_MAC_CFG);
2910         if ((reg & MAC_CFG_RX_ENB) != 0) {
2911                 reg &= ~MAC_CFG_RX_ENB;
2912                 CSR_WRITE_4(sc, AGE_MAC_CFG, reg);
2913         }
2914         /* Stop Rx DMA engine. */
2915         reg = CSR_READ_4(sc, AGE_DMA_CFG);
2916         if ((reg & DMA_CFG_WR_ENB) != 0) {
2917                 reg &= ~DMA_CFG_WR_ENB;
2918                 CSR_WRITE_4(sc, AGE_DMA_CFG, reg);
2919         }
2920         for (i = AGE_RESET_TIMEOUT; i > 0; i--) {
2921                 if ((CSR_READ_4(sc, AGE_IDLE_STATUS) &
2922                     (IDLE_STATUS_RXMAC | IDLE_STATUS_DMAWR)) == 0)
2923                         break;
2924                 DELAY(10);
2925         }
2926         if (i == 0)
2927                 device_printf(sc->age_dev, "stopping RxMAC timeout!\n");
2928 }
2929
2930 static void
2931 age_init_tx_ring(struct age_softc *sc)
2932 {
2933         struct age_ring_data *rd;
2934         struct age_txdesc *txd;
2935         int i;
2936
2937         AGE_LOCK_ASSERT(sc);
2938
2939         sc->age_cdata.age_tx_prod = 0;
2940         sc->age_cdata.age_tx_cons = 0;
2941         sc->age_cdata.age_tx_cnt = 0;
2942
2943         rd = &sc->age_rdata;
2944         bzero(rd->age_tx_ring, AGE_TX_RING_SZ);
2945         for (i = 0; i < AGE_TX_RING_CNT; i++) {
2946                 txd = &sc->age_cdata.age_txdesc[i];
2947                 txd->tx_desc = &rd->age_tx_ring[i];
2948                 txd->tx_m = NULL;
2949         }
2950
2951         bus_dmamap_sync(sc->age_cdata.age_tx_ring_tag,
2952             sc->age_cdata.age_tx_ring_map,
2953             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2954 }
2955
2956 static int
2957 age_init_rx_ring(struct age_softc *sc)
2958 {
2959         struct age_ring_data *rd;
2960         struct age_rxdesc *rxd;
2961         int i;
2962
2963         AGE_LOCK_ASSERT(sc);
2964
2965         sc->age_cdata.age_rx_cons = AGE_RX_RING_CNT - 1;
2966         sc->age_morework = 0;
2967         rd = &sc->age_rdata;
2968         bzero(rd->age_rx_ring, AGE_RX_RING_SZ);
2969         for (i = 0; i < AGE_RX_RING_CNT; i++) {
2970                 rxd = &sc->age_cdata.age_rxdesc[i];
2971                 rxd->rx_m = NULL;
2972                 rxd->rx_desc = &rd->age_rx_ring[i];
2973                 if (age_newbuf(sc, rxd) != 0)
2974                         return (ENOBUFS);
2975         }
2976
2977         bus_dmamap_sync(sc->age_cdata.age_rx_ring_tag,
2978             sc->age_cdata.age_rx_ring_map,
2979             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2980
2981         return (0);
2982 }
2983
2984 static void
2985 age_init_rr_ring(struct age_softc *sc)
2986 {
2987         struct age_ring_data *rd;
2988
2989         AGE_LOCK_ASSERT(sc);
2990
2991         sc->age_cdata.age_rr_cons = 0;
2992         AGE_RXCHAIN_RESET(sc);
2993
2994         rd = &sc->age_rdata;
2995         bzero(rd->age_rr_ring, AGE_RR_RING_SZ);
2996         bus_dmamap_sync(sc->age_cdata.age_rr_ring_tag,
2997             sc->age_cdata.age_rr_ring_map,
2998             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2999 }
3000
3001 static void
3002 age_init_cmb_block(struct age_softc *sc)
3003 {
3004         struct age_ring_data *rd;
3005
3006         AGE_LOCK_ASSERT(sc);
3007
3008         rd = &sc->age_rdata;
3009         bzero(rd->age_cmb_block, AGE_CMB_BLOCK_SZ);
3010         bus_dmamap_sync(sc->age_cdata.age_cmb_block_tag,
3011             sc->age_cdata.age_cmb_block_map,
3012             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3013 }
3014
3015 static void
3016 age_init_smb_block(struct age_softc *sc)
3017 {
3018         struct age_ring_data *rd;
3019
3020         AGE_LOCK_ASSERT(sc);
3021
3022         rd = &sc->age_rdata;
3023         bzero(rd->age_smb_block, AGE_SMB_BLOCK_SZ);
3024         bus_dmamap_sync(sc->age_cdata.age_smb_block_tag,
3025             sc->age_cdata.age_smb_block_map,
3026             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3027 }
3028
3029 static int
3030 age_newbuf(struct age_softc *sc, struct age_rxdesc *rxd)
3031 {
3032         struct rx_desc *desc;
3033         struct mbuf *m;
3034         bus_dma_segment_t segs[1];
3035         bus_dmamap_t map;
3036         int nsegs;
3037
3038         AGE_LOCK_ASSERT(sc);
3039
3040         m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
3041         if (m == NULL)
3042                 return (ENOBUFS);
3043         m->m_len = m->m_pkthdr.len = MCLBYTES;
3044         m_adj(m, ETHER_ALIGN);
3045
3046         if (bus_dmamap_load_mbuf_sg(sc->age_cdata.age_rx_tag,
3047             sc->age_cdata.age_rx_sparemap, m, segs, &nsegs, 0) != 0) {
3048                 m_freem(m);
3049                 return (ENOBUFS);
3050         }
3051         KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
3052
3053         if (rxd->rx_m != NULL) {
3054                 bus_dmamap_sync(sc->age_cdata.age_rx_tag, rxd->rx_dmamap,
3055                     BUS_DMASYNC_POSTREAD);
3056                 bus_dmamap_unload(sc->age_cdata.age_rx_tag, rxd->rx_dmamap);
3057         }
3058         map = rxd->rx_dmamap;
3059         rxd->rx_dmamap = sc->age_cdata.age_rx_sparemap;
3060         sc->age_cdata.age_rx_sparemap = map;
3061         bus_dmamap_sync(sc->age_cdata.age_rx_tag, rxd->rx_dmamap,
3062             BUS_DMASYNC_PREREAD);
3063         rxd->rx_m = m;
3064
3065         desc = rxd->rx_desc;
3066         desc->addr = htole64(segs[0].ds_addr);
3067         desc->len = htole32((segs[0].ds_len & AGE_RD_LEN_MASK) <<
3068             AGE_RD_LEN_SHIFT);
3069         return (0);
3070 }
3071
3072 static void
3073 age_rxvlan(struct age_softc *sc)
3074 {
3075         struct ifnet *ifp;
3076         uint32_t reg;
3077
3078         AGE_LOCK_ASSERT(sc);
3079
3080         ifp = sc->age_ifp;
3081         reg = CSR_READ_4(sc, AGE_MAC_CFG);
3082         reg &= ~MAC_CFG_VLAN_TAG_STRIP;
3083         if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0)
3084                 reg |= MAC_CFG_VLAN_TAG_STRIP;
3085         CSR_WRITE_4(sc, AGE_MAC_CFG, reg);
3086 }
3087
3088 static void
3089 age_rxfilter(struct age_softc *sc)
3090 {
3091         struct ifnet *ifp;
3092         struct ifmultiaddr *ifma;
3093         uint32_t crc;
3094         uint32_t mchash[2];
3095         uint32_t rxcfg;
3096
3097         AGE_LOCK_ASSERT(sc);
3098
3099         ifp = sc->age_ifp;
3100
3101         rxcfg = CSR_READ_4(sc, AGE_MAC_CFG);
3102         rxcfg &= ~(MAC_CFG_ALLMULTI | MAC_CFG_BCAST | MAC_CFG_PROMISC);
3103         if ((ifp->if_flags & IFF_BROADCAST) != 0)
3104                 rxcfg |= MAC_CFG_BCAST;
3105         if ((ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) != 0) {
3106                 if ((ifp->if_flags & IFF_PROMISC) != 0)
3107                         rxcfg |= MAC_CFG_PROMISC;
3108                 if ((ifp->if_flags & IFF_ALLMULTI) != 0)
3109                         rxcfg |= MAC_CFG_ALLMULTI;
3110                 CSR_WRITE_4(sc, AGE_MAR0, 0xFFFFFFFF);
3111                 CSR_WRITE_4(sc, AGE_MAR1, 0xFFFFFFFF);
3112                 CSR_WRITE_4(sc, AGE_MAC_CFG, rxcfg);
3113                 return;
3114         }
3115
3116         /* Program new filter. */
3117         bzero(mchash, sizeof(mchash));
3118
3119         if_maddr_rlock(ifp);
3120         TAILQ_FOREACH(ifma, &sc->age_ifp->if_multiaddrs, ifma_link) {
3121                 if (ifma->ifma_addr->sa_family != AF_LINK)
3122                         continue;
3123                 crc = ether_crc32_be(LLADDR((struct sockaddr_dl *)
3124                     ifma->ifma_addr), ETHER_ADDR_LEN);
3125                 mchash[crc >> 31] |= 1 << ((crc >> 26) & 0x1f);
3126         }
3127         if_maddr_runlock(ifp);
3128
3129         CSR_WRITE_4(sc, AGE_MAR0, mchash[0]);
3130         CSR_WRITE_4(sc, AGE_MAR1, mchash[1]);
3131         CSR_WRITE_4(sc, AGE_MAC_CFG, rxcfg);
3132 }
3133
3134 static int
3135 sysctl_age_stats(SYSCTL_HANDLER_ARGS)
3136 {
3137         struct age_softc *sc;
3138         struct age_stats *stats;
3139         int error, result;
3140
3141         result = -1;
3142         error = sysctl_handle_int(oidp, &result, 0, req);
3143
3144         if (error != 0 || req->newptr == NULL)
3145                 return (error);
3146
3147         if (result != 1)
3148                 return (error);
3149
3150         sc = (struct age_softc *)arg1;
3151         stats = &sc->age_stat;
3152         printf("%s statistics:\n", device_get_nameunit(sc->age_dev));
3153         printf("Transmit good frames : %ju\n",
3154             (uintmax_t)stats->tx_frames);
3155         printf("Transmit good broadcast frames : %ju\n",
3156             (uintmax_t)stats->tx_bcast_frames);
3157         printf("Transmit good multicast frames : %ju\n",
3158             (uintmax_t)stats->tx_mcast_frames);
3159         printf("Transmit pause control frames : %u\n",
3160             stats->tx_pause_frames);
3161         printf("Transmit control frames : %u\n",
3162             stats->tx_control_frames);
3163         printf("Transmit frames with excessive deferrals : %u\n",
3164             stats->tx_excess_defer);
3165         printf("Transmit deferrals : %u\n",
3166             stats->tx_deferred);
3167         printf("Transmit good octets : %ju\n",
3168             (uintmax_t)stats->tx_bytes);
3169         printf("Transmit good broadcast octets : %ju\n",
3170             (uintmax_t)stats->tx_bcast_bytes);
3171         printf("Transmit good multicast octets : %ju\n",
3172             (uintmax_t)stats->tx_mcast_bytes);
3173         printf("Transmit frames 64 bytes : %ju\n",
3174             (uintmax_t)stats->tx_pkts_64);
3175         printf("Transmit frames 65 to 127 bytes : %ju\n",
3176             (uintmax_t)stats->tx_pkts_65_127);
3177         printf("Transmit frames 128 to 255 bytes : %ju\n",
3178             (uintmax_t)stats->tx_pkts_128_255);
3179         printf("Transmit frames 256 to 511 bytes : %ju\n",
3180             (uintmax_t)stats->tx_pkts_256_511);
3181         printf("Transmit frames 512 to 1024 bytes : %ju\n",
3182             (uintmax_t)stats->tx_pkts_512_1023);
3183         printf("Transmit frames 1024 to 1518 bytes : %ju\n",
3184             (uintmax_t)stats->tx_pkts_1024_1518);
3185         printf("Transmit frames 1519 to MTU bytes : %ju\n",
3186             (uintmax_t)stats->tx_pkts_1519_max);
3187         printf("Transmit single collisions : %u\n",
3188             stats->tx_single_colls);
3189         printf("Transmit multiple collisions : %u\n",
3190             stats->tx_multi_colls);
3191         printf("Transmit late collisions : %u\n",
3192             stats->tx_late_colls);
3193         printf("Transmit abort due to excessive collisions : %u\n",
3194             stats->tx_excess_colls);
3195         printf("Transmit underruns due to FIFO underruns : %u\n",
3196             stats->tx_underrun);
3197         printf("Transmit descriptor write-back errors : %u\n",
3198             stats->tx_desc_underrun);
3199         printf("Transmit frames with length mismatched frame size : %u\n",
3200             stats->tx_lenerrs);
3201         printf("Transmit frames with truncated due to MTU size : %u\n",
3202             stats->tx_lenerrs);
3203
3204         printf("Receive good frames : %ju\n",
3205             (uintmax_t)stats->rx_frames);
3206         printf("Receive good broadcast frames : %ju\n",
3207             (uintmax_t)stats->rx_bcast_frames);
3208         printf("Receive good multicast frames : %ju\n",
3209             (uintmax_t)stats->rx_mcast_frames);
3210         printf("Receive pause control frames : %u\n",
3211             stats->rx_pause_frames);
3212         printf("Receive control frames : %u\n",
3213             stats->rx_control_frames);
3214         printf("Receive CRC errors : %u\n",
3215             stats->rx_crcerrs);
3216         printf("Receive frames with length errors : %u\n",
3217             stats->rx_lenerrs);
3218         printf("Receive good octets : %ju\n",
3219             (uintmax_t)stats->rx_bytes);
3220         printf("Receive good broadcast octets : %ju\n",
3221             (uintmax_t)stats->rx_bcast_bytes);
3222         printf("Receive good multicast octets : %ju\n",
3223             (uintmax_t)stats->rx_mcast_bytes);
3224         printf("Receive frames too short : %u\n",
3225             stats->rx_runts);
3226         printf("Receive fragmented frames : %ju\n",
3227             (uintmax_t)stats->rx_fragments);
3228         printf("Receive frames 64 bytes : %ju\n",
3229             (uintmax_t)stats->rx_pkts_64);
3230         printf("Receive frames 65 to 127 bytes : %ju\n",
3231             (uintmax_t)stats->rx_pkts_65_127);
3232         printf("Receive frames 128 to 255 bytes : %ju\n",
3233             (uintmax_t)stats->rx_pkts_128_255);
3234         printf("Receive frames 256 to 511 bytes : %ju\n",
3235             (uintmax_t)stats->rx_pkts_256_511);
3236         printf("Receive frames 512 to 1024 bytes : %ju\n",
3237             (uintmax_t)stats->rx_pkts_512_1023);
3238         printf("Receive frames 1024 to 1518 bytes : %ju\n",
3239             (uintmax_t)stats->rx_pkts_1024_1518);
3240         printf("Receive frames 1519 to MTU bytes : %ju\n",
3241             (uintmax_t)stats->rx_pkts_1519_max);
3242         printf("Receive frames too long : %ju\n",
3243             (uint64_t)stats->rx_pkts_truncated);
3244         printf("Receive frames with FIFO overflow : %u\n",
3245             stats->rx_fifo_oflows);
3246         printf("Receive frames with return descriptor overflow : %u\n",
3247             stats->rx_desc_oflows);
3248         printf("Receive frames with alignment errors : %u\n",
3249             stats->rx_alignerrs);
3250         printf("Receive frames dropped due to address filtering : %ju\n",
3251             (uint64_t)stats->rx_pkts_filtered);
3252
3253         return (error);
3254 }
3255
3256 static int
3257 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high)
3258 {
3259         int error, value;
3260
3261         if (arg1 == NULL)
3262                 return (EINVAL);
3263         value = *(int *)arg1;
3264         error = sysctl_handle_int(oidp, &value, 0, req);
3265         if (error || req->newptr == NULL)
3266                 return (error);
3267         if (value < low || value > high)
3268                 return (EINVAL);
3269         *(int *)arg1 = value;
3270
3271         return (0);
3272 }
3273
3274 static int
3275 sysctl_hw_age_proc_limit(SYSCTL_HANDLER_ARGS)
3276 {
3277         return (sysctl_int_range(oidp, arg1, arg2, req,
3278             AGE_PROC_MIN, AGE_PROC_MAX));
3279 }
3280
3281 static int
3282 sysctl_hw_age_int_mod(SYSCTL_HANDLER_ARGS)
3283 {
3284
3285         return (sysctl_int_range(oidp, arg1, arg2, req, AGE_IM_TIMER_MIN,
3286             AGE_IM_TIMER_MAX));
3287 }