2 * Copyright (c) 2008, Pyun YongHyeon <yongari@FreeBSD.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice unmodified, this list of conditions, and the following
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 /* Driver for Atheros AR8121/AR8113/AR8114 PCIe Ethernet. */
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD$");
33 #include <sys/param.h>
34 #include <sys/systm.h>
36 #include <sys/endian.h>
37 #include <sys/kernel.h>
38 #include <sys/malloc.h>
40 #include <sys/module.h>
42 #include <sys/queue.h>
43 #include <sys/socket.h>
44 #include <sys/sockio.h>
45 #include <sys/sysctl.h>
46 #include <sys/taskqueue.h>
50 #include <net/if_arp.h>
51 #include <net/ethernet.h>
52 #include <net/if_dl.h>
53 #include <net/if_llc.h>
54 #include <net/if_media.h>
55 #include <net/if_types.h>
56 #include <net/if_vlan_var.h>
58 #include <netinet/in.h>
59 #include <netinet/in_systm.h>
60 #include <netinet/ip.h>
61 #include <netinet/tcp.h>
63 #include <dev/mii/mii.h>
64 #include <dev/mii/miivar.h>
66 #include <dev/pci/pcireg.h>
67 #include <dev/pci/pcivar.h>
69 #include <machine/atomic.h>
70 #include <machine/bus.h>
71 #include <machine/in_cksum.h>
73 #include <dev/ale/if_alereg.h>
74 #include <dev/ale/if_alevar.h>
76 /* "device miibus" required. See GENERIC if you get errors here. */
77 #include "miibus_if.h"
79 /* For more information about Tx checksum offload issues see ale_encap(). */
80 #define ALE_CSUM_FEATURES (CSUM_TCP | CSUM_UDP)
82 MODULE_DEPEND(ale, pci, 1, 1, 1);
83 MODULE_DEPEND(ale, ether, 1, 1, 1);
84 MODULE_DEPEND(ale, miibus, 1, 1, 1);
87 static int msi_disable = 0;
88 static int msix_disable = 0;
89 TUNABLE_INT("hw.ale.msi_disable", &msi_disable);
90 TUNABLE_INT("hw.ale.msix_disable", &msix_disable);
93 * Devices supported by this driver.
95 static struct ale_dev {
96 uint16_t ale_vendorid;
97 uint16_t ale_deviceid;
100 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR81XX,
101 "Atheros AR8121/AR8113/AR8114 PCIe Ethernet" },
104 static int ale_attach(device_t);
105 static int ale_check_boundary(struct ale_softc *);
106 static int ale_detach(device_t);
107 static int ale_dma_alloc(struct ale_softc *);
108 static void ale_dma_free(struct ale_softc *);
109 static void ale_dmamap_cb(void *, bus_dma_segment_t *, int, int);
110 static int ale_encap(struct ale_softc *, struct mbuf **);
111 static void ale_get_macaddr(struct ale_softc *);
112 static void ale_init(void *);
113 static void ale_init_locked(struct ale_softc *);
114 static void ale_init_rx_pages(struct ale_softc *);
115 static void ale_init_tx_ring(struct ale_softc *);
116 static void ale_int_task(void *, int);
117 static int ale_intr(void *);
118 static int ale_ioctl(struct ifnet *, u_long, caddr_t);
119 static void ale_link_task(void *, int);
120 static void ale_mac_config(struct ale_softc *);
121 static int ale_miibus_readreg(device_t, int, int);
122 static void ale_miibus_statchg(device_t);
123 static int ale_miibus_writereg(device_t, int, int, int);
124 static int ale_mediachange(struct ifnet *);
125 static void ale_mediastatus(struct ifnet *, struct ifmediareq *);
126 static void ale_phy_reset(struct ale_softc *);
127 static int ale_probe(device_t);
128 static void ale_reset(struct ale_softc *);
129 static int ale_resume(device_t);
130 static void ale_rx_update_page(struct ale_softc *, struct ale_rx_page **,
131 uint32_t, uint32_t *);
132 static void ale_rxcsum(struct ale_softc *, struct mbuf *, uint32_t);
133 static int ale_rxeof(struct ale_softc *sc, int);
134 static void ale_rxfilter(struct ale_softc *);
135 static void ale_rxvlan(struct ale_softc *);
136 static void ale_setlinkspeed(struct ale_softc *);
137 static void ale_setwol(struct ale_softc *);
138 static int ale_shutdown(device_t);
139 static void ale_start(struct ifnet *);
140 static void ale_stats_clear(struct ale_softc *);
141 static void ale_stats_update(struct ale_softc *);
142 static void ale_stop(struct ale_softc *);
143 static void ale_stop_mac(struct ale_softc *);
144 static int ale_suspend(device_t);
145 static void ale_sysctl_node(struct ale_softc *);
146 static void ale_tick(void *);
147 static void ale_tx_task(void *, int);
148 static void ale_txeof(struct ale_softc *);
149 static void ale_watchdog(struct ale_softc *);
150 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int);
151 static int sysctl_hw_ale_proc_limit(SYSCTL_HANDLER_ARGS);
152 static int sysctl_hw_ale_int_mod(SYSCTL_HANDLER_ARGS);
154 static device_method_t ale_methods[] = {
155 /* Device interface. */
156 DEVMETHOD(device_probe, ale_probe),
157 DEVMETHOD(device_attach, ale_attach),
158 DEVMETHOD(device_detach, ale_detach),
159 DEVMETHOD(device_shutdown, ale_shutdown),
160 DEVMETHOD(device_suspend, ale_suspend),
161 DEVMETHOD(device_resume, ale_resume),
164 DEVMETHOD(miibus_readreg, ale_miibus_readreg),
165 DEVMETHOD(miibus_writereg, ale_miibus_writereg),
166 DEVMETHOD(miibus_statchg, ale_miibus_statchg),
171 static driver_t ale_driver = {
174 sizeof(struct ale_softc)
177 static devclass_t ale_devclass;
179 DRIVER_MODULE(ale, pci, ale_driver, ale_devclass, 0, 0);
180 DRIVER_MODULE(miibus, ale, miibus_driver, miibus_devclass, 0, 0);
182 static struct resource_spec ale_res_spec_mem[] = {
183 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE },
187 static struct resource_spec ale_irq_spec_legacy[] = {
188 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE },
192 static struct resource_spec ale_irq_spec_msi[] = {
193 { SYS_RES_IRQ, 1, RF_ACTIVE },
197 static struct resource_spec ale_irq_spec_msix[] = {
198 { SYS_RES_IRQ, 1, RF_ACTIVE },
203 ale_miibus_readreg(device_t dev, int phy, int reg)
205 struct ale_softc *sc;
209 sc = device_get_softc(dev);
211 if (phy != sc->ale_phyaddr)
214 CSR_WRITE_4(sc, ALE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ |
215 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg));
216 for (i = ALE_PHY_TIMEOUT; i > 0; i--) {
218 v = CSR_READ_4(sc, ALE_MDIO);
219 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0)
224 device_printf(sc->ale_dev, "phy read timeout : %d\n", reg);
228 return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT);
232 ale_miibus_writereg(device_t dev, int phy, int reg, int val)
234 struct ale_softc *sc;
238 sc = device_get_softc(dev);
240 if (phy != sc->ale_phyaddr)
243 CSR_WRITE_4(sc, ALE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE |
244 (val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT |
245 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg));
246 for (i = ALE_PHY_TIMEOUT; i > 0; i--) {
248 v = CSR_READ_4(sc, ALE_MDIO);
249 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0)
254 device_printf(sc->ale_dev, "phy write timeout : %d\n", reg);
260 ale_miibus_statchg(device_t dev)
262 struct ale_softc *sc;
264 sc = device_get_softc(dev);
266 taskqueue_enqueue(taskqueue_swi, &sc->ale_link_task);
270 ale_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr)
272 struct ale_softc *sc;
273 struct mii_data *mii;
277 mii = device_get_softc(sc->ale_miibus);
281 ifmr->ifm_status = mii->mii_media_status;
282 ifmr->ifm_active = mii->mii_media_active;
286 ale_mediachange(struct ifnet *ifp)
288 struct ale_softc *sc;
289 struct mii_data *mii;
290 struct mii_softc *miisc;
295 mii = device_get_softc(sc->ale_miibus);
296 if (mii->mii_instance != 0) {
297 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
298 mii_phy_reset(miisc);
300 error = mii_mediachg(mii);
307 ale_probe(device_t dev)
311 uint16_t vendor, devid;
313 vendor = pci_get_vendor(dev);
314 devid = pci_get_device(dev);
316 for (i = 0; i < sizeof(ale_devs) / sizeof(ale_devs[0]); i++) {
317 if (vendor == sp->ale_vendorid &&
318 devid == sp->ale_deviceid) {
319 device_set_desc(dev, sp->ale_name);
320 return (BUS_PROBE_DEFAULT);
329 ale_get_macaddr(struct ale_softc *sc)
334 reg = CSR_READ_4(sc, ALE_SPI_CTRL);
335 if ((reg & SPI_VPD_ENB) != 0) {
337 CSR_WRITE_4(sc, ALE_SPI_CTRL, reg);
340 if (pci_find_extcap(sc->ale_dev, PCIY_VPD, &vpdc) == 0) {
342 * PCI VPD capability found, let TWSI reload EEPROM.
343 * This will set ethernet address of controller.
345 CSR_WRITE_4(sc, ALE_TWSI_CTRL, CSR_READ_4(sc, ALE_TWSI_CTRL) |
346 TWSI_CTRL_SW_LD_START);
347 for (i = 100; i > 0; i--) {
349 reg = CSR_READ_4(sc, ALE_TWSI_CTRL);
350 if ((reg & TWSI_CTRL_SW_LD_START) == 0)
354 device_printf(sc->ale_dev,
355 "reloading EEPROM timeout!\n");
358 device_printf(sc->ale_dev,
359 "PCI VPD capability not found!\n");
362 ea[0] = CSR_READ_4(sc, ALE_PAR0);
363 ea[1] = CSR_READ_4(sc, ALE_PAR1);
364 sc->ale_eaddr[0] = (ea[1] >> 8) & 0xFF;
365 sc->ale_eaddr[1] = (ea[1] >> 0) & 0xFF;
366 sc->ale_eaddr[2] = (ea[0] >> 24) & 0xFF;
367 sc->ale_eaddr[3] = (ea[0] >> 16) & 0xFF;
368 sc->ale_eaddr[4] = (ea[0] >> 8) & 0xFF;
369 sc->ale_eaddr[5] = (ea[0] >> 0) & 0xFF;
373 ale_phy_reset(struct ale_softc *sc)
376 /* Reset magic from Linux. */
377 CSR_WRITE_2(sc, ALE_GPHY_CTRL,
378 GPHY_CTRL_HIB_EN | GPHY_CTRL_HIB_PULSE | GPHY_CTRL_SEL_ANA_RESET |
379 GPHY_CTRL_PHY_PLL_ON);
381 CSR_WRITE_2(sc, ALE_GPHY_CTRL,
382 GPHY_CTRL_EXT_RESET | GPHY_CTRL_HIB_EN | GPHY_CTRL_HIB_PULSE |
383 GPHY_CTRL_SEL_ANA_RESET | GPHY_CTRL_PHY_PLL_ON);
386 #define ATPHY_DBG_ADDR 0x1D
387 #define ATPHY_DBG_DATA 0x1E
389 /* Enable hibernation mode. */
390 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
391 ATPHY_DBG_ADDR, 0x0B);
392 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
393 ATPHY_DBG_DATA, 0xBC00);
394 /* Set Class A/B for all modes. */
395 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
396 ATPHY_DBG_ADDR, 0x00);
397 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
398 ATPHY_DBG_DATA, 0x02EF);
399 /* Enable 10BT power saving. */
400 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
401 ATPHY_DBG_ADDR, 0x12);
402 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
403 ATPHY_DBG_DATA, 0x4C04);
404 /* Adjust 1000T power. */
405 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
406 ATPHY_DBG_ADDR, 0x04);
407 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
408 ATPHY_DBG_ADDR, 0x8BBB);
409 /* 10BT center tap voltage. */
410 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
411 ATPHY_DBG_ADDR, 0x05);
412 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
413 ATPHY_DBG_ADDR, 0x2C46);
415 #undef ATPHY_DBG_ADDR
416 #undef ATPHY_DBG_DATA
421 ale_attach(device_t dev)
423 struct ale_softc *sc;
426 int error, i, msic, msixc, pmc;
427 uint32_t rxf_len, txf_len;
430 sc = device_get_softc(dev);
433 mtx_init(&sc->ale_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
435 callout_init_mtx(&sc->ale_tick_ch, &sc->ale_mtx, 0);
436 TASK_INIT(&sc->ale_int_task, 0, ale_int_task, sc);
437 TASK_INIT(&sc->ale_link_task, 0, ale_link_task, sc);
439 /* Map the device. */
440 pci_enable_busmaster(dev);
441 sc->ale_res_spec = ale_res_spec_mem;
442 sc->ale_irq_spec = ale_irq_spec_legacy;
443 error = bus_alloc_resources(dev, sc->ale_res_spec, sc->ale_res);
445 device_printf(dev, "cannot allocate memory resources.\n");
449 /* Set PHY address. */
450 sc->ale_phyaddr = ALE_PHY_ADDR;
455 /* Reset the ethernet controller. */
458 /* Get PCI and chip id/revision. */
459 sc->ale_rev = pci_get_revid(dev);
460 if (sc->ale_rev >= 0xF0) {
461 /* L2E Rev. B. AR8114 */
462 sc->ale_flags |= ALE_FLAG_FASTETHER;
464 if ((CSR_READ_4(sc, ALE_PHY_STATUS) & PHY_STATUS_100M) != 0) {
466 sc->ale_flags |= ALE_FLAG_JUMBO;
468 /* L2E Rev. A. AR8113 */
469 sc->ale_flags |= ALE_FLAG_FASTETHER;
473 * All known controllers seems to require 4 bytes alignment
474 * of Tx buffers to make Tx checksum offload with custom
475 * checksum generation method work.
477 sc->ale_flags |= ALE_FLAG_TXCSUM_BUG;
479 * All known controllers seems to have issues on Rx checksum
480 * offload for fragmented IP datagrams.
482 sc->ale_flags |= ALE_FLAG_RXCSUM_BUG;
484 * Don't use Tx CMB. It is known to cause RRS update failure
485 * under certain circumstances. Typical phenomenon of the
486 * issue would be unexpected sequence number encountered in
489 sc->ale_flags |= ALE_FLAG_TXCMB_BUG;
490 sc->ale_chip_rev = CSR_READ_4(sc, ALE_MASTER_CFG) >>
491 MASTER_CHIP_REV_SHIFT;
493 device_printf(dev, "PCI device revision : 0x%04x\n",
495 device_printf(dev, "Chip id/revision : 0x%04x\n",
498 txf_len = CSR_READ_4(sc, ALE_SRAM_TX_FIFO_LEN);
499 rxf_len = CSR_READ_4(sc, ALE_SRAM_RX_FIFO_LEN);
501 * Uninitialized hardware returns an invalid chip id/revision
502 * as well as 0xFFFFFFFF for Tx/Rx fifo length.
504 if (sc->ale_chip_rev == 0xFFFF || txf_len == 0xFFFFFFFF ||
505 rxf_len == 0xFFFFFFF) {
506 device_printf(dev,"chip revision : 0x%04x, %u Tx FIFO "
507 "%u Rx FIFO -- not initialized?\n", sc->ale_chip_rev,
512 device_printf(dev, "%u Tx FIFO, %u Rx FIFO\n", txf_len, rxf_len);
514 /* Allocate IRQ resources. */
515 msixc = pci_msix_count(dev);
516 msic = pci_msi_count(dev);
518 device_printf(dev, "MSIX count : %d\n", msixc);
519 device_printf(dev, "MSI count : %d\n", msic);
522 /* Prefer MSIX over MSI. */
523 if (msix_disable == 0 || msi_disable == 0) {
524 if (msix_disable == 0 && msixc == ALE_MSIX_MESSAGES &&
525 pci_alloc_msix(dev, &msixc) == 0) {
526 if (msic == ALE_MSIX_MESSAGES) {
527 device_printf(dev, "Using %d MSIX messages.\n",
529 sc->ale_flags |= ALE_FLAG_MSIX;
530 sc->ale_irq_spec = ale_irq_spec_msix;
532 pci_release_msi(dev);
534 if (msi_disable == 0 && (sc->ale_flags & ALE_FLAG_MSIX) == 0 &&
535 msic == ALE_MSI_MESSAGES &&
536 pci_alloc_msi(dev, &msic) == 0) {
537 if (msic == ALE_MSI_MESSAGES) {
538 device_printf(dev, "Using %d MSI messages.\n",
540 sc->ale_flags |= ALE_FLAG_MSI;
541 sc->ale_irq_spec = ale_irq_spec_msi;
543 pci_release_msi(dev);
547 error = bus_alloc_resources(dev, sc->ale_irq_spec, sc->ale_irq);
549 device_printf(dev, "cannot allocate IRQ resources.\n");
553 /* Get DMA parameters from PCIe device control register. */
554 if (pci_find_extcap(dev, PCIY_EXPRESS, &i) == 0) {
555 sc->ale_flags |= ALE_FLAG_PCIE;
556 burst = pci_read_config(dev, i + 0x08, 2);
557 /* Max read request size. */
558 sc->ale_dma_rd_burst = ((burst >> 12) & 0x07) <<
559 DMA_CFG_RD_BURST_SHIFT;
560 /* Max payload size. */
561 sc->ale_dma_wr_burst = ((burst >> 5) & 0x07) <<
562 DMA_CFG_WR_BURST_SHIFT;
564 device_printf(dev, "Read request size : %d bytes.\n",
565 128 << ((burst >> 12) & 0x07));
566 device_printf(dev, "TLP payload size : %d bytes.\n",
567 128 << ((burst >> 5) & 0x07));
570 sc->ale_dma_rd_burst = DMA_CFG_RD_BURST_128;
571 sc->ale_dma_wr_burst = DMA_CFG_WR_BURST_128;
574 /* Create device sysctl node. */
577 if ((error = ale_dma_alloc(sc) != 0))
580 /* Load station address. */
583 ifp = sc->ale_ifp = if_alloc(IFT_ETHER);
585 device_printf(dev, "cannot allocate ifnet structure.\n");
591 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
592 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
593 ifp->if_ioctl = ale_ioctl;
594 ifp->if_start = ale_start;
595 ifp->if_init = ale_init;
596 ifp->if_snd.ifq_drv_maxlen = ALE_TX_RING_CNT - 1;
597 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen);
598 IFQ_SET_READY(&ifp->if_snd);
599 ifp->if_capabilities = IFCAP_RXCSUM | IFCAP_TXCSUM | IFCAP_TSO4;
600 ifp->if_hwassist = ALE_CSUM_FEATURES | CSUM_TSO;
601 if (pci_find_extcap(dev, PCIY_PMG, &pmc) == 0) {
602 sc->ale_flags |= ALE_FLAG_PMCAP;
603 ifp->if_capabilities |= IFCAP_WOL_MAGIC | IFCAP_WOL_MCAST;
605 ifp->if_capenable = ifp->if_capabilities;
607 /* Set up MII bus. */
608 if ((error = mii_phy_probe(dev, &sc->ale_miibus, ale_mediachange,
609 ale_mediastatus)) != 0) {
610 device_printf(dev, "no PHY found!\n");
614 ether_ifattach(ifp, sc->ale_eaddr);
616 /* VLAN capability setup. */
617 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING |
618 IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWTSO;
619 ifp->if_capenable = ifp->if_capabilities;
621 * Even though controllers supported by ale(3) have Rx checksum
622 * offload bug the workaround for fragmented frames seemed to
623 * work so far. However it seems Rx checksum offload does not
624 * work under certain conditions. So disable Rx checksum offload
625 * until I find more clue about it but allow users to override it.
627 ifp->if_capenable &= ~IFCAP_RXCSUM;
629 /* Tell the upper layer(s) we support long frames. */
630 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
632 /* Create local taskq. */
633 TASK_INIT(&sc->ale_tx_task, 1, ale_tx_task, ifp);
634 sc->ale_tq = taskqueue_create_fast("ale_taskq", M_WAITOK,
635 taskqueue_thread_enqueue, &sc->ale_tq);
636 if (sc->ale_tq == NULL) {
637 device_printf(dev, "could not create taskqueue.\n");
642 taskqueue_start_threads(&sc->ale_tq, 1, PI_NET, "%s taskq",
643 device_get_nameunit(sc->ale_dev));
645 if ((sc->ale_flags & ALE_FLAG_MSIX) != 0)
646 msic = ALE_MSIX_MESSAGES;
647 else if ((sc->ale_flags & ALE_FLAG_MSI) != 0)
648 msic = ALE_MSI_MESSAGES;
651 for (i = 0; i < msic; i++) {
652 error = bus_setup_intr(dev, sc->ale_irq[i],
653 INTR_TYPE_NET | INTR_MPSAFE, ale_intr, NULL, sc,
654 &sc->ale_intrhand[i]);
659 device_printf(dev, "could not set up interrupt handler.\n");
660 taskqueue_free(sc->ale_tq);
674 ale_detach(device_t dev)
676 struct ale_softc *sc;
680 sc = device_get_softc(dev);
683 if (device_is_attached(dev)) {
685 sc->ale_flags |= ALE_FLAG_DETACH;
688 callout_drain(&sc->ale_tick_ch);
689 taskqueue_drain(sc->ale_tq, &sc->ale_int_task);
690 taskqueue_drain(sc->ale_tq, &sc->ale_tx_task);
691 taskqueue_drain(taskqueue_swi, &sc->ale_link_task);
695 if (sc->ale_tq != NULL) {
696 taskqueue_drain(sc->ale_tq, &sc->ale_int_task);
697 taskqueue_free(sc->ale_tq);
701 if (sc->ale_miibus != NULL) {
702 device_delete_child(dev, sc->ale_miibus);
703 sc->ale_miibus = NULL;
705 bus_generic_detach(dev);
713 if ((sc->ale_flags & ALE_FLAG_MSIX) != 0)
714 msic = ALE_MSIX_MESSAGES;
715 else if ((sc->ale_flags & ALE_FLAG_MSI) != 0)
716 msic = ALE_MSI_MESSAGES;
719 for (i = 0; i < msic; i++) {
720 if (sc->ale_intrhand[i] != NULL) {
721 bus_teardown_intr(dev, sc->ale_irq[i],
722 sc->ale_intrhand[i]);
723 sc->ale_intrhand[i] = NULL;
727 bus_release_resources(dev, sc->ale_irq_spec, sc->ale_irq);
728 if ((sc->ale_flags & (ALE_FLAG_MSI | ALE_FLAG_MSIX)) != 0)
729 pci_release_msi(dev);
730 bus_release_resources(dev, sc->ale_res_spec, sc->ale_res);
731 mtx_destroy(&sc->ale_mtx);
736 #define ALE_SYSCTL_STAT_ADD32(c, h, n, p, d) \
737 SYSCTL_ADD_UINT(c, h, OID_AUTO, n, CTLFLAG_RD, p, 0, d)
739 #if __FreeBSD_version > 800000
740 #define ALE_SYSCTL_STAT_ADD64(c, h, n, p, d) \
741 SYSCTL_ADD_QUAD(c, h, OID_AUTO, n, CTLFLAG_RD, p, d)
743 #define ALE_SYSCTL_STAT_ADD64(c, h, n, p, d) \
744 SYSCTL_ADD_ULONG(c, h, OID_AUTO, n, CTLFLAG_RD, p, d)
748 ale_sysctl_node(struct ale_softc *sc)
750 struct sysctl_ctx_list *ctx;
751 struct sysctl_oid_list *child, *parent;
752 struct sysctl_oid *tree;
753 struct ale_hw_stats *stats;
756 stats = &sc->ale_stats;
757 ctx = device_get_sysctl_ctx(sc->ale_dev);
758 child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->ale_dev));
760 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "int_rx_mod",
761 CTLTYPE_INT | CTLFLAG_RW, &sc->ale_int_rx_mod, 0,
762 sysctl_hw_ale_int_mod, "I", "ale Rx interrupt moderation");
763 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "int_tx_mod",
764 CTLTYPE_INT | CTLFLAG_RW, &sc->ale_int_tx_mod, 0,
765 sysctl_hw_ale_int_mod, "I", "ale Tx interrupt moderation");
766 /* Pull in device tunables. */
767 sc->ale_int_rx_mod = ALE_IM_RX_TIMER_DEFAULT;
768 error = resource_int_value(device_get_name(sc->ale_dev),
769 device_get_unit(sc->ale_dev), "int_rx_mod", &sc->ale_int_rx_mod);
771 if (sc->ale_int_rx_mod < ALE_IM_TIMER_MIN ||
772 sc->ale_int_rx_mod > ALE_IM_TIMER_MAX) {
773 device_printf(sc->ale_dev, "int_rx_mod value out of "
774 "range; using default: %d\n",
775 ALE_IM_RX_TIMER_DEFAULT);
776 sc->ale_int_rx_mod = ALE_IM_RX_TIMER_DEFAULT;
779 sc->ale_int_tx_mod = ALE_IM_TX_TIMER_DEFAULT;
780 error = resource_int_value(device_get_name(sc->ale_dev),
781 device_get_unit(sc->ale_dev), "int_tx_mod", &sc->ale_int_tx_mod);
783 if (sc->ale_int_tx_mod < ALE_IM_TIMER_MIN ||
784 sc->ale_int_tx_mod > ALE_IM_TIMER_MAX) {
785 device_printf(sc->ale_dev, "int_tx_mod value out of "
786 "range; using default: %d\n",
787 ALE_IM_TX_TIMER_DEFAULT);
788 sc->ale_int_tx_mod = ALE_IM_TX_TIMER_DEFAULT;
791 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "process_limit",
792 CTLTYPE_INT | CTLFLAG_RW, &sc->ale_process_limit, 0,
793 sysctl_hw_ale_proc_limit, "I",
794 "max number of Rx events to process");
795 /* Pull in device tunables. */
796 sc->ale_process_limit = ALE_PROC_DEFAULT;
797 error = resource_int_value(device_get_name(sc->ale_dev),
798 device_get_unit(sc->ale_dev), "process_limit",
799 &sc->ale_process_limit);
801 if (sc->ale_process_limit < ALE_PROC_MIN ||
802 sc->ale_process_limit > ALE_PROC_MAX) {
803 device_printf(sc->ale_dev,
804 "process_limit value out of range; "
805 "using default: %d\n", ALE_PROC_DEFAULT);
806 sc->ale_process_limit = ALE_PROC_DEFAULT;
810 /* Misc statistics. */
811 ALE_SYSCTL_STAT_ADD32(ctx, child, "reset_brk_seq",
812 &stats->reset_brk_seq,
813 "Controller resets due to broken Rx sequnce number");
815 tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats", CTLFLAG_RD,
816 NULL, "ATE statistics");
817 parent = SYSCTL_CHILDREN(tree);
820 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "rx", CTLFLAG_RD,
821 NULL, "Rx MAC statistics");
822 child = SYSCTL_CHILDREN(tree);
823 ALE_SYSCTL_STAT_ADD32(ctx, child, "good_frames",
824 &stats->rx_frames, "Good frames");
825 ALE_SYSCTL_STAT_ADD32(ctx, child, "good_bcast_frames",
826 &stats->rx_bcast_frames, "Good broadcast frames");
827 ALE_SYSCTL_STAT_ADD32(ctx, child, "good_mcast_frames",
828 &stats->rx_mcast_frames, "Good multicast frames");
829 ALE_SYSCTL_STAT_ADD32(ctx, child, "pause_frames",
830 &stats->rx_pause_frames, "Pause control frames");
831 ALE_SYSCTL_STAT_ADD32(ctx, child, "control_frames",
832 &stats->rx_control_frames, "Control frames");
833 ALE_SYSCTL_STAT_ADD32(ctx, child, "crc_errs",
834 &stats->rx_crcerrs, "CRC errors");
835 ALE_SYSCTL_STAT_ADD32(ctx, child, "len_errs",
836 &stats->rx_lenerrs, "Frames with length mismatched");
837 ALE_SYSCTL_STAT_ADD64(ctx, child, "good_octets",
838 &stats->rx_bytes, "Good octets");
839 ALE_SYSCTL_STAT_ADD64(ctx, child, "good_bcast_octets",
840 &stats->rx_bcast_bytes, "Good broadcast octets");
841 ALE_SYSCTL_STAT_ADD64(ctx, child, "good_mcast_octets",
842 &stats->rx_mcast_bytes, "Good multicast octets");
843 ALE_SYSCTL_STAT_ADD32(ctx, child, "runts",
844 &stats->rx_runts, "Too short frames");
845 ALE_SYSCTL_STAT_ADD32(ctx, child, "fragments",
846 &stats->rx_fragments, "Fragmented frames");
847 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_64",
848 &stats->rx_pkts_64, "64 bytes frames");
849 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_65_127",
850 &stats->rx_pkts_65_127, "65 to 127 bytes frames");
851 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_128_255",
852 &stats->rx_pkts_128_255, "128 to 255 bytes frames");
853 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_256_511",
854 &stats->rx_pkts_256_511, "256 to 511 bytes frames");
855 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_512_1023",
856 &stats->rx_pkts_512_1023, "512 to 1023 bytes frames");
857 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_1024_1518",
858 &stats->rx_pkts_1024_1518, "1024 to 1518 bytes frames");
859 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_1519_max",
860 &stats->rx_pkts_1519_max, "1519 to max frames");
861 ALE_SYSCTL_STAT_ADD32(ctx, child, "trunc_errs",
862 &stats->rx_pkts_truncated, "Truncated frames due to MTU size");
863 ALE_SYSCTL_STAT_ADD32(ctx, child, "fifo_oflows",
864 &stats->rx_fifo_oflows, "FIFO overflows");
865 ALE_SYSCTL_STAT_ADD32(ctx, child, "rrs_errs",
866 &stats->rx_rrs_errs, "Return status write-back errors");
867 ALE_SYSCTL_STAT_ADD32(ctx, child, "align_errs",
868 &stats->rx_alignerrs, "Alignment errors");
869 ALE_SYSCTL_STAT_ADD32(ctx, child, "filtered",
870 &stats->rx_pkts_filtered,
871 "Frames dropped due to address filtering");
874 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "tx", CTLFLAG_RD,
875 NULL, "Tx MAC statistics");
876 child = SYSCTL_CHILDREN(tree);
877 ALE_SYSCTL_STAT_ADD32(ctx, child, "good_frames",
878 &stats->tx_frames, "Good frames");
879 ALE_SYSCTL_STAT_ADD32(ctx, child, "good_bcast_frames",
880 &stats->tx_bcast_frames, "Good broadcast frames");
881 ALE_SYSCTL_STAT_ADD32(ctx, child, "good_mcast_frames",
882 &stats->tx_mcast_frames, "Good multicast frames");
883 ALE_SYSCTL_STAT_ADD32(ctx, child, "pause_frames",
884 &stats->tx_pause_frames, "Pause control frames");
885 ALE_SYSCTL_STAT_ADD32(ctx, child, "control_frames",
886 &stats->tx_control_frames, "Control frames");
887 ALE_SYSCTL_STAT_ADD32(ctx, child, "excess_defers",
888 &stats->tx_excess_defer, "Frames with excessive derferrals");
889 ALE_SYSCTL_STAT_ADD32(ctx, child, "defers",
890 &stats->tx_excess_defer, "Frames with derferrals");
891 ALE_SYSCTL_STAT_ADD64(ctx, child, "good_octets",
892 &stats->tx_bytes, "Good octets");
893 ALE_SYSCTL_STAT_ADD64(ctx, child, "good_bcast_octets",
894 &stats->tx_bcast_bytes, "Good broadcast octets");
895 ALE_SYSCTL_STAT_ADD64(ctx, child, "good_mcast_octets",
896 &stats->tx_mcast_bytes, "Good multicast octets");
897 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_64",
898 &stats->tx_pkts_64, "64 bytes frames");
899 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_65_127",
900 &stats->tx_pkts_65_127, "65 to 127 bytes frames");
901 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_128_255",
902 &stats->tx_pkts_128_255, "128 to 255 bytes frames");
903 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_256_511",
904 &stats->tx_pkts_256_511, "256 to 511 bytes frames");
905 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_512_1023",
906 &stats->tx_pkts_512_1023, "512 to 1023 bytes frames");
907 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_1024_1518",
908 &stats->tx_pkts_1024_1518, "1024 to 1518 bytes frames");
909 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_1519_max",
910 &stats->tx_pkts_1519_max, "1519 to max frames");
911 ALE_SYSCTL_STAT_ADD32(ctx, child, "single_colls",
912 &stats->tx_single_colls, "Single collisions");
913 ALE_SYSCTL_STAT_ADD32(ctx, child, "multi_colls",
914 &stats->tx_multi_colls, "Multiple collisions");
915 ALE_SYSCTL_STAT_ADD32(ctx, child, "late_colls",
916 &stats->tx_late_colls, "Late collisions");
917 ALE_SYSCTL_STAT_ADD32(ctx, child, "excess_colls",
918 &stats->tx_excess_colls, "Excessive collisions");
919 ALE_SYSCTL_STAT_ADD32(ctx, child, "abort",
920 &stats->tx_abort, "Aborted frames due to Excessive collisions");
921 ALE_SYSCTL_STAT_ADD32(ctx, child, "underruns",
922 &stats->tx_underrun, "FIFO underruns");
923 ALE_SYSCTL_STAT_ADD32(ctx, child, "desc_underruns",
924 &stats->tx_desc_underrun, "Descriptor write-back errors");
925 ALE_SYSCTL_STAT_ADD32(ctx, child, "len_errs",
926 &stats->tx_lenerrs, "Frames with length mismatched");
927 ALE_SYSCTL_STAT_ADD32(ctx, child, "trunc_errs",
928 &stats->tx_pkts_truncated, "Truncated frames due to MTU size");
931 #undef ALE_SYSCTL_STAT_ADD32
932 #undef ALE_SYSCTL_STAT_ADD64
934 struct ale_dmamap_arg {
935 bus_addr_t ale_busaddr;
939 ale_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
941 struct ale_dmamap_arg *ctx;
946 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
948 ctx = (struct ale_dmamap_arg *)arg;
949 ctx->ale_busaddr = segs[0].ds_addr;
953 * Tx descriptors/RXF0/CMB DMA blocks share ALE_DESC_ADDR_HI register
954 * which specifies high address region of DMA blocks. Therefore these
955 * blocks should have the same high address of given 4GB address
956 * space(i.e. crossing 4GB boundary is not allowed).
959 ale_check_boundary(struct ale_softc *sc)
961 bus_addr_t rx_cmb_end[ALE_RX_PAGES], tx_cmb_end;
962 bus_addr_t rx_page_end[ALE_RX_PAGES], tx_ring_end;
964 rx_page_end[0] = sc->ale_cdata.ale_rx_page[0].page_paddr +
966 rx_page_end[1] = sc->ale_cdata.ale_rx_page[1].page_paddr +
968 tx_ring_end = sc->ale_cdata.ale_tx_ring_paddr + ALE_TX_RING_SZ;
969 tx_cmb_end = sc->ale_cdata.ale_tx_cmb_paddr + ALE_TX_CMB_SZ;
970 rx_cmb_end[0] = sc->ale_cdata.ale_rx_page[0].cmb_paddr + ALE_RX_CMB_SZ;
971 rx_cmb_end[1] = sc->ale_cdata.ale_rx_page[1].cmb_paddr + ALE_RX_CMB_SZ;
973 if ((ALE_ADDR_HI(tx_ring_end) !=
974 ALE_ADDR_HI(sc->ale_cdata.ale_tx_ring_paddr)) ||
975 (ALE_ADDR_HI(rx_page_end[0]) !=
976 ALE_ADDR_HI(sc->ale_cdata.ale_rx_page[0].page_paddr)) ||
977 (ALE_ADDR_HI(rx_page_end[1]) !=
978 ALE_ADDR_HI(sc->ale_cdata.ale_rx_page[1].page_paddr)) ||
979 (ALE_ADDR_HI(tx_cmb_end) !=
980 ALE_ADDR_HI(sc->ale_cdata.ale_tx_cmb_paddr)) ||
981 (ALE_ADDR_HI(rx_cmb_end[0]) !=
982 ALE_ADDR_HI(sc->ale_cdata.ale_rx_page[0].cmb_paddr)) ||
983 (ALE_ADDR_HI(rx_cmb_end[1]) !=
984 ALE_ADDR_HI(sc->ale_cdata.ale_rx_page[1].cmb_paddr)))
987 if ((ALE_ADDR_HI(tx_ring_end) != ALE_ADDR_HI(rx_page_end[0])) ||
988 (ALE_ADDR_HI(tx_ring_end) != ALE_ADDR_HI(rx_page_end[1])) ||
989 (ALE_ADDR_HI(tx_ring_end) != ALE_ADDR_HI(rx_cmb_end[0])) ||
990 (ALE_ADDR_HI(tx_ring_end) != ALE_ADDR_HI(rx_cmb_end[1])) ||
991 (ALE_ADDR_HI(tx_ring_end) != ALE_ADDR_HI(tx_cmb_end)))
998 ale_dma_alloc(struct ale_softc *sc)
1000 struct ale_txdesc *txd;
1002 struct ale_dmamap_arg ctx;
1003 int error, guard_size, i;
1005 if ((sc->ale_flags & ALE_FLAG_JUMBO) != 0)
1006 guard_size = ALE_JUMBO_FRAMELEN;
1008 guard_size = ALE_MAX_FRAMELEN;
1009 sc->ale_pagesize = roundup(guard_size + ALE_RX_PAGE_SZ,
1011 lowaddr = BUS_SPACE_MAXADDR;
1013 /* Create parent DMA tag. */
1014 error = bus_dma_tag_create(
1015 bus_get_dma_tag(sc->ale_dev), /* parent */
1016 1, 0, /* alignment, boundary */
1017 lowaddr, /* lowaddr */
1018 BUS_SPACE_MAXADDR, /* highaddr */
1019 NULL, NULL, /* filter, filterarg */
1020 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */
1022 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */
1024 NULL, NULL, /* lockfunc, lockarg */
1025 &sc->ale_cdata.ale_parent_tag);
1027 device_printf(sc->ale_dev,
1028 "could not create parent DMA tag.\n");
1032 /* Create DMA tag for Tx descriptor ring. */
1033 error = bus_dma_tag_create(
1034 sc->ale_cdata.ale_parent_tag, /* parent */
1035 ALE_TX_RING_ALIGN, 0, /* alignment, boundary */
1036 BUS_SPACE_MAXADDR, /* lowaddr */
1037 BUS_SPACE_MAXADDR, /* highaddr */
1038 NULL, NULL, /* filter, filterarg */
1039 ALE_TX_RING_SZ, /* maxsize */
1041 ALE_TX_RING_SZ, /* maxsegsize */
1043 NULL, NULL, /* lockfunc, lockarg */
1044 &sc->ale_cdata.ale_tx_ring_tag);
1046 device_printf(sc->ale_dev,
1047 "could not create Tx ring DMA tag.\n");
1051 /* Create DMA tag for Rx pages. */
1052 for (i = 0; i < ALE_RX_PAGES; i++) {
1053 error = bus_dma_tag_create(
1054 sc->ale_cdata.ale_parent_tag, /* parent */
1055 ALE_RX_PAGE_ALIGN, 0, /* alignment, boundary */
1056 BUS_SPACE_MAXADDR, /* lowaddr */
1057 BUS_SPACE_MAXADDR, /* highaddr */
1058 NULL, NULL, /* filter, filterarg */
1059 sc->ale_pagesize, /* maxsize */
1061 sc->ale_pagesize, /* maxsegsize */
1063 NULL, NULL, /* lockfunc, lockarg */
1064 &sc->ale_cdata.ale_rx_page[i].page_tag);
1066 device_printf(sc->ale_dev,
1067 "could not create Rx page %d DMA tag.\n", i);
1072 /* Create DMA tag for Tx coalescing message block. */
1073 error = bus_dma_tag_create(
1074 sc->ale_cdata.ale_parent_tag, /* parent */
1075 ALE_CMB_ALIGN, 0, /* alignment, boundary */
1076 BUS_SPACE_MAXADDR, /* lowaddr */
1077 BUS_SPACE_MAXADDR, /* highaddr */
1078 NULL, NULL, /* filter, filterarg */
1079 ALE_TX_CMB_SZ, /* maxsize */
1081 ALE_TX_CMB_SZ, /* maxsegsize */
1083 NULL, NULL, /* lockfunc, lockarg */
1084 &sc->ale_cdata.ale_tx_cmb_tag);
1086 device_printf(sc->ale_dev,
1087 "could not create Tx CMB DMA tag.\n");
1091 /* Create DMA tag for Rx coalescing message block. */
1092 for (i = 0; i < ALE_RX_PAGES; i++) {
1093 error = bus_dma_tag_create(
1094 sc->ale_cdata.ale_parent_tag, /* parent */
1095 ALE_CMB_ALIGN, 0, /* alignment, boundary */
1096 BUS_SPACE_MAXADDR, /* lowaddr */
1097 BUS_SPACE_MAXADDR, /* highaddr */
1098 NULL, NULL, /* filter, filterarg */
1099 ALE_RX_CMB_SZ, /* maxsize */
1101 ALE_RX_CMB_SZ, /* maxsegsize */
1103 NULL, NULL, /* lockfunc, lockarg */
1104 &sc->ale_cdata.ale_rx_page[i].cmb_tag);
1106 device_printf(sc->ale_dev,
1107 "could not create Rx page %d CMB DMA tag.\n", i);
1112 /* Allocate DMA'able memory and load the DMA map for Tx ring. */
1113 error = bus_dmamem_alloc(sc->ale_cdata.ale_tx_ring_tag,
1114 (void **)&sc->ale_cdata.ale_tx_ring,
1115 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT,
1116 &sc->ale_cdata.ale_tx_ring_map);
1118 device_printf(sc->ale_dev,
1119 "could not allocate DMA'able memory for Tx ring.\n");
1122 ctx.ale_busaddr = 0;
1123 error = bus_dmamap_load(sc->ale_cdata.ale_tx_ring_tag,
1124 sc->ale_cdata.ale_tx_ring_map, sc->ale_cdata.ale_tx_ring,
1125 ALE_TX_RING_SZ, ale_dmamap_cb, &ctx, 0);
1126 if (error != 0 || ctx.ale_busaddr == 0) {
1127 device_printf(sc->ale_dev,
1128 "could not load DMA'able memory for Tx ring.\n");
1131 sc->ale_cdata.ale_tx_ring_paddr = ctx.ale_busaddr;
1134 for (i = 0; i < ALE_RX_PAGES; i++) {
1135 error = bus_dmamem_alloc(sc->ale_cdata.ale_rx_page[i].page_tag,
1136 (void **)&sc->ale_cdata.ale_rx_page[i].page_addr,
1137 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT,
1138 &sc->ale_cdata.ale_rx_page[i].page_map);
1140 device_printf(sc->ale_dev,
1141 "could not allocate DMA'able memory for "
1142 "Rx page %d.\n", i);
1145 ctx.ale_busaddr = 0;
1146 error = bus_dmamap_load(sc->ale_cdata.ale_rx_page[i].page_tag,
1147 sc->ale_cdata.ale_rx_page[i].page_map,
1148 sc->ale_cdata.ale_rx_page[i].page_addr,
1149 sc->ale_pagesize, ale_dmamap_cb, &ctx, 0);
1150 if (error != 0 || ctx.ale_busaddr == 0) {
1151 device_printf(sc->ale_dev,
1152 "could not load DMA'able memory for "
1153 "Rx page %d.\n", i);
1156 sc->ale_cdata.ale_rx_page[i].page_paddr = ctx.ale_busaddr;
1160 error = bus_dmamem_alloc(sc->ale_cdata.ale_tx_cmb_tag,
1161 (void **)&sc->ale_cdata.ale_tx_cmb,
1162 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT,
1163 &sc->ale_cdata.ale_tx_cmb_map);
1165 device_printf(sc->ale_dev,
1166 "could not allocate DMA'able memory for Tx CMB.\n");
1169 ctx.ale_busaddr = 0;
1170 error = bus_dmamap_load(sc->ale_cdata.ale_tx_cmb_tag,
1171 sc->ale_cdata.ale_tx_cmb_map, sc->ale_cdata.ale_tx_cmb,
1172 ALE_TX_CMB_SZ, ale_dmamap_cb, &ctx, 0);
1173 if (error != 0 || ctx.ale_busaddr == 0) {
1174 device_printf(sc->ale_dev,
1175 "could not load DMA'able memory for Tx CMB.\n");
1178 sc->ale_cdata.ale_tx_cmb_paddr = ctx.ale_busaddr;
1181 for (i = 0; i < ALE_RX_PAGES; i++) {
1182 error = bus_dmamem_alloc(sc->ale_cdata.ale_rx_page[i].cmb_tag,
1183 (void **)&sc->ale_cdata.ale_rx_page[i].cmb_addr,
1184 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT,
1185 &sc->ale_cdata.ale_rx_page[i].cmb_map);
1187 device_printf(sc->ale_dev, "could not allocate "
1188 "DMA'able memory for Rx page %d CMB.\n", i);
1191 ctx.ale_busaddr = 0;
1192 error = bus_dmamap_load(sc->ale_cdata.ale_rx_page[i].cmb_tag,
1193 sc->ale_cdata.ale_rx_page[i].cmb_map,
1194 sc->ale_cdata.ale_rx_page[i].cmb_addr,
1195 ALE_RX_CMB_SZ, ale_dmamap_cb, &ctx, 0);
1196 if (error != 0 || ctx.ale_busaddr == 0) {
1197 device_printf(sc->ale_dev, "could not load DMA'able "
1198 "memory for Rx page %d CMB.\n", i);
1201 sc->ale_cdata.ale_rx_page[i].cmb_paddr = ctx.ale_busaddr;
1205 * Tx descriptors/RXF0/CMB DMA blocks share the same
1206 * high address region of 64bit DMA address space.
1208 if (lowaddr != BUS_SPACE_MAXADDR_32BIT &&
1209 (error = ale_check_boundary(sc)) != 0) {
1210 device_printf(sc->ale_dev, "4GB boundary crossed, "
1211 "switching to 32bit DMA addressing mode.\n");
1214 * Limit max allowable DMA address space to 32bit
1217 lowaddr = BUS_SPACE_MAXADDR_32BIT;
1222 * Create Tx buffer parent tag.
1223 * AR81xx allows 64bit DMA addressing of Tx buffers so it
1224 * needs separate parent DMA tag as parent DMA address space
1225 * could be restricted to be within 32bit address space by
1226 * 4GB boundary crossing.
1228 error = bus_dma_tag_create(
1229 bus_get_dma_tag(sc->ale_dev), /* parent */
1230 1, 0, /* alignment, boundary */
1231 BUS_SPACE_MAXADDR, /* lowaddr */
1232 BUS_SPACE_MAXADDR, /* highaddr */
1233 NULL, NULL, /* filter, filterarg */
1234 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */
1236 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */
1238 NULL, NULL, /* lockfunc, lockarg */
1239 &sc->ale_cdata.ale_buffer_tag);
1241 device_printf(sc->ale_dev,
1242 "could not create parent buffer DMA tag.\n");
1246 /* Create DMA tag for Tx buffers. */
1247 error = bus_dma_tag_create(
1248 sc->ale_cdata.ale_buffer_tag, /* parent */
1249 1, 0, /* alignment, boundary */
1250 BUS_SPACE_MAXADDR, /* lowaddr */
1251 BUS_SPACE_MAXADDR, /* highaddr */
1252 NULL, NULL, /* filter, filterarg */
1253 ALE_TSO_MAXSIZE, /* maxsize */
1254 ALE_MAXTXSEGS, /* nsegments */
1255 ALE_TSO_MAXSEGSIZE, /* maxsegsize */
1257 NULL, NULL, /* lockfunc, lockarg */
1258 &sc->ale_cdata.ale_tx_tag);
1260 device_printf(sc->ale_dev, "could not create Tx DMA tag.\n");
1264 /* Create DMA maps for Tx buffers. */
1265 for (i = 0; i < ALE_TX_RING_CNT; i++) {
1266 txd = &sc->ale_cdata.ale_txdesc[i];
1268 txd->tx_dmamap = NULL;
1269 error = bus_dmamap_create(sc->ale_cdata.ale_tx_tag, 0,
1272 device_printf(sc->ale_dev,
1273 "could not create Tx dmamap.\n");
1283 ale_dma_free(struct ale_softc *sc)
1285 struct ale_txdesc *txd;
1289 if (sc->ale_cdata.ale_tx_tag != NULL) {
1290 for (i = 0; i < ALE_TX_RING_CNT; i++) {
1291 txd = &sc->ale_cdata.ale_txdesc[i];
1292 if (txd->tx_dmamap != NULL) {
1293 bus_dmamap_destroy(sc->ale_cdata.ale_tx_tag,
1295 txd->tx_dmamap = NULL;
1298 bus_dma_tag_destroy(sc->ale_cdata.ale_tx_tag);
1299 sc->ale_cdata.ale_tx_tag = NULL;
1301 /* Tx descriptor ring. */
1302 if (sc->ale_cdata.ale_tx_ring_tag != NULL) {
1303 if (sc->ale_cdata.ale_tx_ring_map != NULL)
1304 bus_dmamap_unload(sc->ale_cdata.ale_tx_ring_tag,
1305 sc->ale_cdata.ale_tx_ring_map);
1306 if (sc->ale_cdata.ale_tx_ring_map != NULL &&
1307 sc->ale_cdata.ale_tx_ring != NULL)
1308 bus_dmamem_free(sc->ale_cdata.ale_tx_ring_tag,
1309 sc->ale_cdata.ale_tx_ring,
1310 sc->ale_cdata.ale_tx_ring_map);
1311 sc->ale_cdata.ale_tx_ring = NULL;
1312 sc->ale_cdata.ale_tx_ring_map = NULL;
1313 bus_dma_tag_destroy(sc->ale_cdata.ale_tx_ring_tag);
1314 sc->ale_cdata.ale_tx_ring_tag = NULL;
1316 /* Rx page block. */
1317 for (i = 0; i < ALE_RX_PAGES; i++) {
1318 if (sc->ale_cdata.ale_rx_page[i].page_tag != NULL) {
1319 if (sc->ale_cdata.ale_rx_page[i].page_map != NULL)
1321 sc->ale_cdata.ale_rx_page[i].page_tag,
1322 sc->ale_cdata.ale_rx_page[i].page_map);
1323 if (sc->ale_cdata.ale_rx_page[i].page_map != NULL &&
1324 sc->ale_cdata.ale_rx_page[i].page_addr != NULL)
1326 sc->ale_cdata.ale_rx_page[i].page_tag,
1327 sc->ale_cdata.ale_rx_page[i].page_addr,
1328 sc->ale_cdata.ale_rx_page[i].page_map);
1329 sc->ale_cdata.ale_rx_page[i].page_addr = NULL;
1330 sc->ale_cdata.ale_rx_page[i].page_map = NULL;
1331 bus_dma_tag_destroy(
1332 sc->ale_cdata.ale_rx_page[i].page_tag);
1333 sc->ale_cdata.ale_rx_page[i].page_tag = NULL;
1337 for (i = 0; i < ALE_RX_PAGES; i++) {
1338 if (sc->ale_cdata.ale_rx_page[i].cmb_tag != NULL) {
1339 if (sc->ale_cdata.ale_rx_page[i].cmb_map != NULL)
1341 sc->ale_cdata.ale_rx_page[i].cmb_tag,
1342 sc->ale_cdata.ale_rx_page[i].cmb_map);
1343 if (sc->ale_cdata.ale_rx_page[i].cmb_map != NULL &&
1344 sc->ale_cdata.ale_rx_page[i].cmb_addr != NULL)
1346 sc->ale_cdata.ale_rx_page[i].cmb_tag,
1347 sc->ale_cdata.ale_rx_page[i].cmb_addr,
1348 sc->ale_cdata.ale_rx_page[i].cmb_map);
1349 sc->ale_cdata.ale_rx_page[i].cmb_addr = NULL;
1350 sc->ale_cdata.ale_rx_page[i].cmb_map = NULL;
1351 bus_dma_tag_destroy(
1352 sc->ale_cdata.ale_rx_page[i].cmb_tag);
1353 sc->ale_cdata.ale_rx_page[i].cmb_tag = NULL;
1357 if (sc->ale_cdata.ale_tx_cmb_tag != NULL) {
1358 if (sc->ale_cdata.ale_tx_cmb_map != NULL)
1359 bus_dmamap_unload(sc->ale_cdata.ale_tx_cmb_tag,
1360 sc->ale_cdata.ale_tx_cmb_map);
1361 if (sc->ale_cdata.ale_tx_cmb_map != NULL &&
1362 sc->ale_cdata.ale_tx_cmb != NULL)
1363 bus_dmamem_free(sc->ale_cdata.ale_tx_cmb_tag,
1364 sc->ale_cdata.ale_tx_cmb,
1365 sc->ale_cdata.ale_tx_cmb_map);
1366 sc->ale_cdata.ale_tx_cmb = NULL;
1367 sc->ale_cdata.ale_tx_cmb_map = NULL;
1368 bus_dma_tag_destroy(sc->ale_cdata.ale_tx_cmb_tag);
1369 sc->ale_cdata.ale_tx_cmb_tag = NULL;
1371 if (sc->ale_cdata.ale_buffer_tag != NULL) {
1372 bus_dma_tag_destroy(sc->ale_cdata.ale_buffer_tag);
1373 sc->ale_cdata.ale_buffer_tag = NULL;
1375 if (sc->ale_cdata.ale_parent_tag != NULL) {
1376 bus_dma_tag_destroy(sc->ale_cdata.ale_parent_tag);
1377 sc->ale_cdata.ale_parent_tag = NULL;
1382 ale_shutdown(device_t dev)
1385 return (ale_suspend(dev));
1389 * Note, this driver resets the link speed to 10/100Mbps by
1390 * restarting auto-negotiation in suspend/shutdown phase but we
1391 * don't know whether that auto-negotiation would succeed or not
1392 * as driver has no control after powering off/suspend operation.
1393 * If the renegotiation fail WOL may not work. Running at 1Gbps
1394 * will draw more power than 375mA at 3.3V which is specified in
1395 * PCI specification and that would result in complete
1396 * shutdowning power to ethernet controller.
1399 * Save current negotiated media speed/duplex/flow-control to
1400 * softc and restore the same link again after resuming. PHY
1401 * handling such as power down/resetting to 100Mbps may be better
1402 * handled in suspend method in phy driver.
1405 ale_setlinkspeed(struct ale_softc *sc)
1407 struct mii_data *mii;
1410 mii = device_get_softc(sc->ale_miibus);
1413 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
1414 (IFM_ACTIVE | IFM_AVALID)) {
1415 switch IFM_SUBTYPE(mii->mii_media_active) {
1426 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, MII_100T2CR, 0);
1427 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
1428 MII_ANAR, ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10 | ANAR_CSMA);
1429 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
1430 MII_BMCR, BMCR_RESET | BMCR_AUTOEN | BMCR_STARTNEG);
1434 * Poll link state until ale(4) get a 10/100Mbps link.
1436 for (i = 0; i < MII_ANEGTICKS_GIGE; i++) {
1438 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID))
1439 == (IFM_ACTIVE | IFM_AVALID)) {
1440 switch (IFM_SUBTYPE(
1441 mii->mii_media_active)) {
1451 pause("alelnk", hz);
1454 if (i == MII_ANEGTICKS_GIGE)
1455 device_printf(sc->ale_dev,
1456 "establishing a link failed, WOL may not work!");
1459 * No link, force MAC to have 100Mbps, full-duplex link.
1460 * This is the last resort and may/may not work.
1462 mii->mii_media_status = IFM_AVALID | IFM_ACTIVE;
1463 mii->mii_media_active = IFM_ETHER | IFM_100_TX | IFM_FDX;
1468 ale_setwol(struct ale_softc *sc)
1475 ALE_LOCK_ASSERT(sc);
1477 if (pci_find_extcap(sc->ale_dev, PCIY_PMG, &pmc) != 0) {
1479 CSR_WRITE_4(sc, ALE_WOL_CFG, 0);
1480 reg = CSR_READ_4(sc, ALE_PCIE_PHYMISC);
1481 reg |= PCIE_PHYMISC_FORCE_RCV_DET;
1482 CSR_WRITE_4(sc, ALE_PCIE_PHYMISC, reg);
1483 /* Force PHY power down. */
1484 CSR_WRITE_2(sc, ALE_GPHY_CTRL,
1485 GPHY_CTRL_EXT_RESET | GPHY_CTRL_HIB_EN |
1486 GPHY_CTRL_HIB_PULSE | GPHY_CTRL_PHY_PLL_ON |
1487 GPHY_CTRL_SEL_ANA_RESET | GPHY_CTRL_PHY_IDDQ |
1488 GPHY_CTRL_PCLK_SEL_DIS | GPHY_CTRL_PWDOWN_HW);
1493 if ((ifp->if_capenable & IFCAP_WOL) != 0) {
1494 if ((sc->ale_flags & ALE_FLAG_FASTETHER) == 0)
1495 ale_setlinkspeed(sc);
1499 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0)
1500 pmcs |= WOL_CFG_MAGIC | WOL_CFG_MAGIC_ENB;
1501 CSR_WRITE_4(sc, ALE_WOL_CFG, pmcs);
1502 reg = CSR_READ_4(sc, ALE_MAC_CFG);
1503 reg &= ~(MAC_CFG_DBG | MAC_CFG_PROMISC | MAC_CFG_ALLMULTI |
1505 if ((ifp->if_capenable & IFCAP_WOL_MCAST) != 0)
1506 reg |= MAC_CFG_ALLMULTI | MAC_CFG_BCAST;
1507 if ((ifp->if_capenable & IFCAP_WOL) != 0)
1508 reg |= MAC_CFG_RX_ENB;
1509 CSR_WRITE_4(sc, ALE_MAC_CFG, reg);
1511 if ((ifp->if_capenable & IFCAP_WOL) == 0) {
1512 /* WOL disabled, PHY power down. */
1513 reg = CSR_READ_4(sc, ALE_PCIE_PHYMISC);
1514 reg |= PCIE_PHYMISC_FORCE_RCV_DET;
1515 CSR_WRITE_4(sc, ALE_PCIE_PHYMISC, reg);
1516 CSR_WRITE_2(sc, ALE_GPHY_CTRL,
1517 GPHY_CTRL_EXT_RESET | GPHY_CTRL_HIB_EN |
1518 GPHY_CTRL_HIB_PULSE | GPHY_CTRL_SEL_ANA_RESET |
1519 GPHY_CTRL_PHY_IDDQ | GPHY_CTRL_PCLK_SEL_DIS |
1520 GPHY_CTRL_PWDOWN_HW);
1523 pmstat = pci_read_config(sc->ale_dev, pmc + PCIR_POWER_STATUS, 2);
1524 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE);
1525 if ((ifp->if_capenable & IFCAP_WOL) != 0)
1526 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
1527 pci_write_config(sc->ale_dev, pmc + PCIR_POWER_STATUS, pmstat, 2);
1531 ale_suspend(device_t dev)
1533 struct ale_softc *sc;
1535 sc = device_get_softc(dev);
1546 ale_resume(device_t dev)
1548 struct ale_softc *sc;
1553 sc = device_get_softc(dev);
1556 if (pci_find_extcap(sc->ale_dev, PCIY_PMG, &pmc) == 0) {
1557 /* Disable PME and clear PME status. */
1558 pmstat = pci_read_config(sc->ale_dev,
1559 pmc + PCIR_POWER_STATUS, 2);
1560 if ((pmstat & PCIM_PSTAT_PMEENABLE) != 0) {
1561 pmstat &= ~PCIM_PSTAT_PMEENABLE;
1562 pci_write_config(sc->ale_dev,
1563 pmc + PCIR_POWER_STATUS, pmstat, 2);
1569 if ((ifp->if_flags & IFF_UP) != 0) {
1570 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1571 ale_init_locked(sc);
1579 ale_encap(struct ale_softc *sc, struct mbuf **m_head)
1581 struct ale_txdesc *txd, *txd_last;
1582 struct tx_desc *desc;
1586 bus_dma_segment_t txsegs[ALE_MAXTXSEGS];
1588 uint32_t cflags, hdrlen, ip_off, poff, vtag;
1589 int error, i, nsegs, prod, si;
1591 ALE_LOCK_ASSERT(sc);
1593 M_ASSERTPKTHDR((*m_head));
1600 if ((m->m_pkthdr.csum_flags & (ALE_CSUM_FEATURES | CSUM_TSO)) != 0) {
1602 * AR81xx requires offset of TCP/UDP payload in its Tx
1603 * descriptor to perform hardware Tx checksum offload.
1604 * Additionally, TSO requires IP/TCP header size and
1605 * modification of IP/TCP header in order to make TSO
1606 * engine work. This kind of operation takes many CPU
1607 * cycles on FreeBSD so fast host CPU is required to
1608 * get smooth TSO performance.
1610 struct ether_header *eh;
1612 if (M_WRITABLE(m) == 0) {
1613 /* Get a writable copy. */
1614 m = m_dup(*m_head, M_DONTWAIT);
1615 /* Release original mbufs. */
1625 * Buggy-controller requires 4 byte aligned Tx buffer
1626 * to make custom checksum offload work.
1628 if ((sc->ale_flags & ALE_FLAG_TXCSUM_BUG) != 0 &&
1629 (m->m_pkthdr.csum_flags & ALE_CSUM_FEATURES) != 0 &&
1630 (mtod(m, intptr_t) & 3) != 0) {
1631 m = m_defrag(*m_head, M_DONTWAIT);
1639 ip_off = sizeof(struct ether_header);
1640 m = m_pullup(m, ip_off);
1645 eh = mtod(m, struct ether_header *);
1647 * Check if hardware VLAN insertion is off.
1648 * Additional check for LLC/SNAP frame?
1650 if (eh->ether_type == htons(ETHERTYPE_VLAN)) {
1651 ip_off = sizeof(struct ether_vlan_header);
1652 m = m_pullup(m, ip_off);
1658 m = m_pullup(m, ip_off + sizeof(struct ip));
1663 ip = (struct ip *)(mtod(m, char *) + ip_off);
1664 poff = ip_off + (ip->ip_hl << 2);
1665 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) {
1668 * AR81xx requires the first descriptor should
1669 * not include any TCP playload for TSO case.
1670 * (i.e. ethernet header + IP + TCP header only)
1671 * m_pullup(9) above will ensure this too.
1672 * However it's not correct if the first mbuf
1673 * of the chain does not use cluster.
1675 m = m_pullup(m, poff + sizeof(struct tcphdr));
1680 tcp = (struct tcphdr *)(mtod(m, char *) + poff);
1681 m = m_pullup(m, poff + (tcp->th_off << 2));
1687 * AR81xx requires IP/TCP header size and offset as
1688 * well as TCP pseudo checksum which complicates
1689 * TSO configuration. I guess this comes from the
1690 * adherence to Microsoft NDIS Large Send
1691 * specification which requires insertion of
1692 * pseudo checksum by upper stack. The pseudo
1693 * checksum that NDIS refers to doesn't include
1694 * TCP payload length so ale(4) should recompute
1695 * the pseudo checksum here. Hopefully this wouldn't
1696 * be much burden on modern CPUs.
1697 * Reset IP checksum and recompute TCP pseudo
1698 * checksum as NDIS specification said.
1701 tcp->th_sum = in_pseudo(ip->ip_src.s_addr,
1702 ip->ip_dst.s_addr, htons(IPPROTO_TCP));
1707 si = prod = sc->ale_cdata.ale_tx_prod;
1708 txd = &sc->ale_cdata.ale_txdesc[prod];
1710 map = txd->tx_dmamap;
1712 error = bus_dmamap_load_mbuf_sg(sc->ale_cdata.ale_tx_tag, map,
1713 *m_head, txsegs, &nsegs, 0);
1714 if (error == EFBIG) {
1715 m = m_collapse(*m_head, M_DONTWAIT, ALE_MAXTXSEGS);
1722 error = bus_dmamap_load_mbuf_sg(sc->ale_cdata.ale_tx_tag, map,
1723 *m_head, txsegs, &nsegs, 0);
1729 } else if (error != 0)
1737 /* Check descriptor overrun. */
1738 if (sc->ale_cdata.ale_tx_cnt + nsegs >= ALE_TX_RING_CNT - 3) {
1739 bus_dmamap_unload(sc->ale_cdata.ale_tx_tag, map);
1742 bus_dmamap_sync(sc->ale_cdata.ale_tx_tag, map, BUS_DMASYNC_PREWRITE);
1745 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) {
1746 /* Request TSO and set MSS. */
1747 cflags |= ALE_TD_TSO;
1748 cflags |= ((uint32_t)m->m_pkthdr.tso_segsz << ALE_TD_MSS_SHIFT);
1749 /* Set IP/TCP header size. */
1750 cflags |= ip->ip_hl << ALE_TD_IPHDR_LEN_SHIFT;
1751 cflags |= tcp->th_off << ALE_TD_TCPHDR_LEN_SHIFT;
1752 } else if ((m->m_pkthdr.csum_flags & ALE_CSUM_FEATURES) != 0) {
1754 * AR81xx supports Tx custom checksum offload feature
1755 * that offloads single 16bit checksum computation.
1756 * So you can choose one among IP, TCP and UDP.
1757 * Normally driver sets checksum start/insertion
1758 * position from the information of TCP/UDP frame as
1759 * TCP/UDP checksum takes more time than that of IP.
1760 * However it seems that custom checksum offload
1761 * requires 4 bytes aligned Tx buffers due to hardware
1763 * AR81xx also supports explicit Tx checksum computation
1764 * if it is told that the size of IP header and TCP
1765 * header(for UDP, the header size does not matter
1766 * because it's fixed length). However with this scheme
1767 * TSO does not work so you have to choose one either
1768 * TSO or explicit Tx checksum offload. I chosen TSO
1769 * plus custom checksum offload with work-around which
1770 * will cover most common usage for this consumer
1771 * ethernet controller. The work-around takes a lot of
1772 * CPU cycles if Tx buffer is not aligned on 4 bytes
1775 cflags |= ALE_TD_CXSUM;
1776 /* Set checksum start offset. */
1777 cflags |= (poff << ALE_TD_CSUM_PLOADOFFSET_SHIFT);
1778 /* Set checksum insertion position of TCP/UDP. */
1779 cflags |= ((poff + m->m_pkthdr.csum_data) <<
1780 ALE_TD_CSUM_XSUMOFFSET_SHIFT);
1783 /* Configure VLAN hardware tag insertion. */
1784 if ((m->m_flags & M_VLANTAG) != 0) {
1785 vtag = ALE_TX_VLAN_TAG(m->m_pkthdr.ether_vtag);
1786 vtag = ((vtag << ALE_TD_VLAN_SHIFT) & ALE_TD_VLAN_MASK);
1787 cflags |= ALE_TD_INSERT_VLAN_TAG;
1791 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) {
1793 * Make sure the first fragment contains
1794 * only ethernet and IP/TCP header with options.
1796 hdrlen = poff + (tcp->th_off << 2);
1797 desc = &sc->ale_cdata.ale_tx_ring[prod];
1798 desc->addr = htole64(txsegs[i].ds_addr);
1799 desc->len = htole32(ALE_TX_BYTES(hdrlen) | vtag);
1800 desc->flags = htole32(cflags);
1801 sc->ale_cdata.ale_tx_cnt++;
1802 ALE_DESC_INC(prod, ALE_TX_RING_CNT);
1803 if (m->m_len - hdrlen > 0) {
1804 /* Handle remaining payload of the first fragment. */
1805 desc = &sc->ale_cdata.ale_tx_ring[prod];
1806 desc->addr = htole64(txsegs[i].ds_addr + hdrlen);
1807 desc->len = htole32(ALE_TX_BYTES(m->m_len - hdrlen) |
1809 desc->flags = htole32(cflags);
1810 sc->ale_cdata.ale_tx_cnt++;
1811 ALE_DESC_INC(prod, ALE_TX_RING_CNT);
1815 for (; i < nsegs; i++) {
1816 desc = &sc->ale_cdata.ale_tx_ring[prod];
1817 desc->addr = htole64(txsegs[i].ds_addr);
1818 desc->len = htole32(ALE_TX_BYTES(txsegs[i].ds_len) | vtag);
1819 desc->flags = htole32(cflags);
1820 sc->ale_cdata.ale_tx_cnt++;
1821 ALE_DESC_INC(prod, ALE_TX_RING_CNT);
1823 /* Update producer index. */
1824 sc->ale_cdata.ale_tx_prod = prod;
1825 /* Set TSO header on the first descriptor. */
1826 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) {
1827 desc = &sc->ale_cdata.ale_tx_ring[si];
1828 desc->flags |= htole32(ALE_TD_TSO_HDR);
1831 /* Finally set EOP on the last descriptor. */
1832 prod = (prod + ALE_TX_RING_CNT - 1) % ALE_TX_RING_CNT;
1833 desc = &sc->ale_cdata.ale_tx_ring[prod];
1834 desc->flags |= htole32(ALE_TD_EOP);
1836 /* Swap dmamap of the first and the last. */
1837 txd = &sc->ale_cdata.ale_txdesc[prod];
1838 map = txd_last->tx_dmamap;
1839 txd_last->tx_dmamap = txd->tx_dmamap;
1840 txd->tx_dmamap = map;
1843 /* Sync descriptors. */
1844 bus_dmamap_sync(sc->ale_cdata.ale_tx_ring_tag,
1845 sc->ale_cdata.ale_tx_ring_map,
1846 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1852 ale_tx_task(void *arg, int pending)
1856 ifp = (struct ifnet *)arg;
1861 ale_start(struct ifnet *ifp)
1863 struct ale_softc *sc;
1864 struct mbuf *m_head;
1871 /* Reclaim transmitted frames. */
1872 if (sc->ale_cdata.ale_tx_cnt >= ALE_TX_DESC_HIWAT)
1875 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
1876 IFF_DRV_RUNNING || (sc->ale_flags & ALE_FLAG_LINK) == 0) {
1881 for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd); ) {
1882 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
1886 * Pack the data into the transmit ring. If we
1887 * don't have room, set the OACTIVE flag and wait
1888 * for the NIC to drain the ring.
1890 if (ale_encap(sc, &m_head)) {
1893 IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
1894 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1900 * If there's a BPF listener, bounce a copy of this frame
1903 ETHER_BPF_MTAP(ifp, m_head);
1908 CSR_WRITE_4(sc, ALE_MBOX_TPD_PROD_IDX,
1909 sc->ale_cdata.ale_tx_prod);
1910 /* Set a timeout in case the chip goes out to lunch. */
1911 sc->ale_watchdog_timer = ALE_TX_TIMEOUT;
1918 ale_watchdog(struct ale_softc *sc)
1922 ALE_LOCK_ASSERT(sc);
1924 if (sc->ale_watchdog_timer == 0 || --sc->ale_watchdog_timer)
1928 if ((sc->ale_flags & ALE_FLAG_LINK) == 0) {
1929 if_printf(sc->ale_ifp, "watchdog timeout (lost link)\n");
1931 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1932 ale_init_locked(sc);
1935 if_printf(sc->ale_ifp, "watchdog timeout -- resetting\n");
1937 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1938 ale_init_locked(sc);
1939 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1940 taskqueue_enqueue(sc->ale_tq, &sc->ale_tx_task);
1944 ale_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
1946 struct ale_softc *sc;
1948 struct mii_data *mii;
1952 ifr = (struct ifreq *)data;
1956 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > ALE_JUMBO_MTU ||
1957 ((sc->ale_flags & ALE_FLAG_JUMBO) == 0 &&
1958 ifr->ifr_mtu > ETHERMTU))
1960 else if (ifp->if_mtu != ifr->ifr_mtu) {
1962 ifp->if_mtu = ifr->ifr_mtu;
1963 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
1964 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1965 ale_init_locked(sc);
1972 if ((ifp->if_flags & IFF_UP) != 0) {
1973 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
1974 if (((ifp->if_flags ^ sc->ale_if_flags)
1975 & (IFF_PROMISC | IFF_ALLMULTI)) != 0)
1978 if ((sc->ale_flags & ALE_FLAG_DETACH) == 0)
1979 ale_init_locked(sc);
1982 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
1985 sc->ale_if_flags = ifp->if_flags;
1991 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
1997 mii = device_get_softc(sc->ale_miibus);
1998 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd);
2002 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
2003 if ((mask & IFCAP_TXCSUM) != 0 &&
2004 (ifp->if_capabilities & IFCAP_TXCSUM) != 0) {
2005 ifp->if_capenable ^= IFCAP_TXCSUM;
2006 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0)
2007 ifp->if_hwassist |= ALE_CSUM_FEATURES;
2009 ifp->if_hwassist &= ~ALE_CSUM_FEATURES;
2011 if ((mask & IFCAP_RXCSUM) != 0 &&
2012 (ifp->if_capabilities & IFCAP_RXCSUM) != 0)
2013 ifp->if_capenable ^= IFCAP_RXCSUM;
2014 if ((mask & IFCAP_TSO4) != 0 &&
2015 (ifp->if_capabilities & IFCAP_TSO4) != 0) {
2016 ifp->if_capenable ^= IFCAP_TSO4;
2017 if ((ifp->if_capenable & IFCAP_TSO4) != 0)
2018 ifp->if_hwassist |= CSUM_TSO;
2020 ifp->if_hwassist &= ~CSUM_TSO;
2023 if ((mask & IFCAP_WOL_MCAST) != 0 &&
2024 (ifp->if_capabilities & IFCAP_WOL_MCAST) != 0)
2025 ifp->if_capenable ^= IFCAP_WOL_MCAST;
2026 if ((mask & IFCAP_WOL_MAGIC) != 0 &&
2027 (ifp->if_capabilities & IFCAP_WOL_MAGIC) != 0)
2028 ifp->if_capenable ^= IFCAP_WOL_MAGIC;
2029 if ((mask & IFCAP_VLAN_HWCSUM) != 0 &&
2030 (ifp->if_capabilities & IFCAP_VLAN_HWCSUM) != 0)
2031 ifp->if_capenable ^= IFCAP_VLAN_HWCSUM;
2032 if ((mask & IFCAP_VLAN_HWTSO) != 0 &&
2033 (ifp->if_capabilities & IFCAP_VLAN_HWTSO) != 0)
2034 ifp->if_capenable ^= IFCAP_VLAN_HWTSO;
2035 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 &&
2036 (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) != 0) {
2037 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
2038 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) == 0)
2039 ifp->if_capenable &= ~IFCAP_VLAN_HWTSO;
2043 VLAN_CAPABILITIES(ifp);
2046 error = ether_ioctl(ifp, cmd, data);
2054 ale_mac_config(struct ale_softc *sc)
2056 struct mii_data *mii;
2059 ALE_LOCK_ASSERT(sc);
2061 mii = device_get_softc(sc->ale_miibus);
2062 reg = CSR_READ_4(sc, ALE_MAC_CFG);
2063 reg &= ~(MAC_CFG_FULL_DUPLEX | MAC_CFG_TX_FC | MAC_CFG_RX_FC |
2064 MAC_CFG_SPEED_MASK);
2065 /* Reprogram MAC with resolved speed/duplex. */
2066 switch (IFM_SUBTYPE(mii->mii_media_active)) {
2069 reg |= MAC_CFG_SPEED_10_100;
2072 reg |= MAC_CFG_SPEED_1000;
2075 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) {
2076 reg |= MAC_CFG_FULL_DUPLEX;
2078 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0)
2079 reg |= MAC_CFG_TX_FC;
2080 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0)
2081 reg |= MAC_CFG_RX_FC;
2084 CSR_WRITE_4(sc, ALE_MAC_CFG, reg);
2088 ale_link_task(void *arg, int pending)
2090 struct ale_softc *sc;
2091 struct mii_data *mii;
2095 sc = (struct ale_softc *)arg;
2098 mii = device_get_softc(sc->ale_miibus);
2100 if (mii == NULL || ifp == NULL ||
2101 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
2106 sc->ale_flags &= ~ALE_FLAG_LINK;
2107 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
2108 (IFM_ACTIVE | IFM_AVALID)) {
2109 switch (IFM_SUBTYPE(mii->mii_media_active)) {
2112 sc->ale_flags |= ALE_FLAG_LINK;
2115 if ((sc->ale_flags & ALE_FLAG_FASTETHER) == 0)
2116 sc->ale_flags |= ALE_FLAG_LINK;
2123 /* Stop Rx/Tx MACs. */
2126 /* Program MACs with resolved speed/duplex/flow-control. */
2127 if ((sc->ale_flags & ALE_FLAG_LINK) != 0) {
2129 /* Reenable Tx/Rx MACs. */
2130 reg = CSR_READ_4(sc, ALE_MAC_CFG);
2131 reg |= MAC_CFG_TX_ENB | MAC_CFG_RX_ENB;
2132 CSR_WRITE_4(sc, ALE_MAC_CFG, reg);
2139 ale_stats_clear(struct ale_softc *sc)
2145 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; reg++) {
2146 CSR_READ_4(sc, ALE_RX_MIB_BASE + i);
2147 i += sizeof(uint32_t);
2149 /* Read Tx statistics. */
2150 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; reg++) {
2151 CSR_READ_4(sc, ALE_TX_MIB_BASE + i);
2152 i += sizeof(uint32_t);
2157 ale_stats_update(struct ale_softc *sc)
2159 struct ale_hw_stats *stat;
2160 struct smb sb, *smb;
2165 ALE_LOCK_ASSERT(sc);
2168 stat = &sc->ale_stats;
2171 /* Read Rx statistics. */
2172 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; reg++) {
2173 *reg = CSR_READ_4(sc, ALE_RX_MIB_BASE + i);
2174 i += sizeof(uint32_t);
2176 /* Read Tx statistics. */
2177 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; reg++) {
2178 *reg = CSR_READ_4(sc, ALE_TX_MIB_BASE + i);
2179 i += sizeof(uint32_t);
2183 stat->rx_frames += smb->rx_frames;
2184 stat->rx_bcast_frames += smb->rx_bcast_frames;
2185 stat->rx_mcast_frames += smb->rx_mcast_frames;
2186 stat->rx_pause_frames += smb->rx_pause_frames;
2187 stat->rx_control_frames += smb->rx_control_frames;
2188 stat->rx_crcerrs += smb->rx_crcerrs;
2189 stat->rx_lenerrs += smb->rx_lenerrs;
2190 stat->rx_bytes += smb->rx_bytes;
2191 stat->rx_runts += smb->rx_runts;
2192 stat->rx_fragments += smb->rx_fragments;
2193 stat->rx_pkts_64 += smb->rx_pkts_64;
2194 stat->rx_pkts_65_127 += smb->rx_pkts_65_127;
2195 stat->rx_pkts_128_255 += smb->rx_pkts_128_255;
2196 stat->rx_pkts_256_511 += smb->rx_pkts_256_511;
2197 stat->rx_pkts_512_1023 += smb->rx_pkts_512_1023;
2198 stat->rx_pkts_1024_1518 += smb->rx_pkts_1024_1518;
2199 stat->rx_pkts_1519_max += smb->rx_pkts_1519_max;
2200 stat->rx_pkts_truncated += smb->rx_pkts_truncated;
2201 stat->rx_fifo_oflows += smb->rx_fifo_oflows;
2202 stat->rx_rrs_errs += smb->rx_rrs_errs;
2203 stat->rx_alignerrs += smb->rx_alignerrs;
2204 stat->rx_bcast_bytes += smb->rx_bcast_bytes;
2205 stat->rx_mcast_bytes += smb->rx_mcast_bytes;
2206 stat->rx_pkts_filtered += smb->rx_pkts_filtered;
2209 stat->tx_frames += smb->tx_frames;
2210 stat->tx_bcast_frames += smb->tx_bcast_frames;
2211 stat->tx_mcast_frames += smb->tx_mcast_frames;
2212 stat->tx_pause_frames += smb->tx_pause_frames;
2213 stat->tx_excess_defer += smb->tx_excess_defer;
2214 stat->tx_control_frames += smb->tx_control_frames;
2215 stat->tx_deferred += smb->tx_deferred;
2216 stat->tx_bytes += smb->tx_bytes;
2217 stat->tx_pkts_64 += smb->tx_pkts_64;
2218 stat->tx_pkts_65_127 += smb->tx_pkts_65_127;
2219 stat->tx_pkts_128_255 += smb->tx_pkts_128_255;
2220 stat->tx_pkts_256_511 += smb->tx_pkts_256_511;
2221 stat->tx_pkts_512_1023 += smb->tx_pkts_512_1023;
2222 stat->tx_pkts_1024_1518 += smb->tx_pkts_1024_1518;
2223 stat->tx_pkts_1519_max += smb->tx_pkts_1519_max;
2224 stat->tx_single_colls += smb->tx_single_colls;
2225 stat->tx_multi_colls += smb->tx_multi_colls;
2226 stat->tx_late_colls += smb->tx_late_colls;
2227 stat->tx_excess_colls += smb->tx_excess_colls;
2228 stat->tx_abort += smb->tx_abort;
2229 stat->tx_underrun += smb->tx_underrun;
2230 stat->tx_desc_underrun += smb->tx_desc_underrun;
2231 stat->tx_lenerrs += smb->tx_lenerrs;
2232 stat->tx_pkts_truncated += smb->tx_pkts_truncated;
2233 stat->tx_bcast_bytes += smb->tx_bcast_bytes;
2234 stat->tx_mcast_bytes += smb->tx_mcast_bytes;
2236 /* Update counters in ifnet. */
2237 ifp->if_opackets += smb->tx_frames;
2239 ifp->if_collisions += smb->tx_single_colls +
2240 smb->tx_multi_colls * 2 + smb->tx_late_colls +
2241 smb->tx_abort * HDPX_CFG_RETRY_DEFAULT;
2245 * tx_pkts_truncated counter looks suspicious. It constantly
2246 * increments with no sign of Tx errors. This may indicate
2247 * the counter name is not correct one so I've removed the
2248 * counter in output errors.
2250 ifp->if_oerrors += smb->tx_abort + smb->tx_late_colls +
2253 ifp->if_ipackets += smb->rx_frames;
2255 ifp->if_ierrors += smb->rx_crcerrs + smb->rx_lenerrs +
2256 smb->rx_runts + smb->rx_pkts_truncated +
2257 smb->rx_fifo_oflows + smb->rx_rrs_errs +
2264 struct ale_softc *sc;
2267 sc = (struct ale_softc *)arg;
2269 status = CSR_READ_4(sc, ALE_INTR_STATUS);
2270 if ((status & ALE_INTRS) == 0)
2271 return (FILTER_STRAY);
2272 /* Disable interrupts. */
2273 CSR_WRITE_4(sc, ALE_INTR_STATUS, INTR_DIS_INT);
2274 taskqueue_enqueue(sc->ale_tq, &sc->ale_int_task);
2276 return (FILTER_HANDLED);
2280 ale_int_task(void *arg, int pending)
2282 struct ale_softc *sc;
2287 sc = (struct ale_softc *)arg;
2289 status = CSR_READ_4(sc, ALE_INTR_STATUS);
2290 more = atomic_readandclear_int(&sc->ale_morework);
2292 status |= INTR_RX_PKT;
2293 if ((status & ALE_INTRS) == 0)
2296 /* Acknowledge interrupts but still disable interrupts. */
2297 CSR_WRITE_4(sc, ALE_INTR_STATUS, status | INTR_DIS_INT);
2301 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
2302 more = ale_rxeof(sc, sc->ale_process_limit);
2304 atomic_set_int(&sc->ale_morework, 1);
2305 else if (more == EIO) {
2307 sc->ale_stats.reset_brk_seq++;
2308 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
2309 ale_init_locked(sc);
2314 if ((status & (INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST)) != 0) {
2315 if ((status & INTR_DMA_RD_TO_RST) != 0)
2316 device_printf(sc->ale_dev,
2317 "DMA read error! -- resetting\n");
2318 if ((status & INTR_DMA_WR_TO_RST) != 0)
2319 device_printf(sc->ale_dev,
2320 "DMA write error! -- resetting\n");
2322 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
2323 ale_init_locked(sc);
2327 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
2328 taskqueue_enqueue(sc->ale_tq, &sc->ale_tx_task);
2331 if (more == EAGAIN ||
2332 (CSR_READ_4(sc, ALE_INTR_STATUS) & ALE_INTRS) != 0) {
2333 taskqueue_enqueue(sc->ale_tq, &sc->ale_int_task);
2338 /* Re-enable interrupts. */
2339 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0x7FFFFFFF);
2343 ale_txeof(struct ale_softc *sc)
2346 struct ale_txdesc *txd;
2347 uint32_t cons, prod;
2350 ALE_LOCK_ASSERT(sc);
2354 if (sc->ale_cdata.ale_tx_cnt == 0)
2357 bus_dmamap_sync(sc->ale_cdata.ale_tx_ring_tag,
2358 sc->ale_cdata.ale_tx_ring_map,
2359 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2360 if ((sc->ale_flags & ALE_FLAG_TXCMB_BUG) == 0) {
2361 bus_dmamap_sync(sc->ale_cdata.ale_tx_cmb_tag,
2362 sc->ale_cdata.ale_tx_cmb_map,
2363 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2364 prod = *sc->ale_cdata.ale_tx_cmb & TPD_CNT_MASK;
2366 prod = CSR_READ_2(sc, ALE_TPD_CONS_IDX);
2367 cons = sc->ale_cdata.ale_tx_cons;
2369 * Go through our Tx list and free mbufs for those
2370 * frames which have been transmitted.
2372 for (prog = 0; cons != prod; prog++,
2373 ALE_DESC_INC(cons, ALE_TX_RING_CNT)) {
2374 if (sc->ale_cdata.ale_tx_cnt <= 0)
2377 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2378 sc->ale_cdata.ale_tx_cnt--;
2379 txd = &sc->ale_cdata.ale_txdesc[cons];
2380 if (txd->tx_m != NULL) {
2381 /* Reclaim transmitted mbufs. */
2382 bus_dmamap_sync(sc->ale_cdata.ale_tx_tag,
2383 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE);
2384 bus_dmamap_unload(sc->ale_cdata.ale_tx_tag,
2392 sc->ale_cdata.ale_tx_cons = cons;
2394 * Unarm watchdog timer only when there is no pending
2395 * Tx descriptors in queue.
2397 if (sc->ale_cdata.ale_tx_cnt == 0)
2398 sc->ale_watchdog_timer = 0;
2403 ale_rx_update_page(struct ale_softc *sc, struct ale_rx_page **page,
2404 uint32_t length, uint32_t *prod)
2406 struct ale_rx_page *rx_page;
2409 /* Update consumer position. */
2410 rx_page->cons += roundup(length + sizeof(struct rx_rs),
2412 if (rx_page->cons >= ALE_RX_PAGE_SZ) {
2414 * End of Rx page reached, let hardware reuse
2418 *rx_page->cmb_addr = 0;
2419 bus_dmamap_sync(rx_page->cmb_tag, rx_page->cmb_map,
2420 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2421 CSR_WRITE_1(sc, ALE_RXF0_PAGE0 + sc->ale_cdata.ale_rx_curp,
2423 /* Switch to alternate Rx page. */
2424 sc->ale_cdata.ale_rx_curp ^= 1;
2426 &sc->ale_cdata.ale_rx_page[sc->ale_cdata.ale_rx_curp];
2427 /* Page flipped, sync CMB and Rx page. */
2428 bus_dmamap_sync(rx_page->page_tag, rx_page->page_map,
2429 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2430 bus_dmamap_sync(rx_page->cmb_tag, rx_page->cmb_map,
2431 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2432 /* Sync completed, cache updated producer index. */
2433 *prod = *rx_page->cmb_addr;
2439 * It seems that AR81xx controller can compute partial checksum.
2440 * The partial checksum value can be used to accelerate checksum
2441 * computation for fragmented TCP/UDP packets. Upper network stack
2442 * already takes advantage of the partial checksum value in IP
2443 * reassembly stage. But I'm not sure the correctness of the
2444 * partial hardware checksum assistance due to lack of data sheet.
2445 * In addition, the Rx feature of controller that requires copying
2446 * for every frames effectively nullifies one of most nice offload
2447 * capability of controller.
2450 ale_rxcsum(struct ale_softc *sc, struct mbuf *m, uint32_t status)
2457 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
2458 if ((status & ALE_RD_IPCSUM_NOK) == 0)
2459 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
2461 if ((sc->ale_flags & ALE_FLAG_RXCSUM_BUG) == 0) {
2462 if (((status & ALE_RD_IPV4_FRAG) == 0) &&
2463 ((status & (ALE_RD_TCP | ALE_RD_UDP)) != 0) &&
2464 ((status & ALE_RD_TCP_UDPCSUM_NOK) == 0)) {
2465 m->m_pkthdr.csum_flags |=
2466 CSUM_DATA_VALID | CSUM_PSEUDO_HDR;
2467 m->m_pkthdr.csum_data = 0xffff;
2470 if ((status & (ALE_RD_TCP | ALE_RD_UDP)) != 0 &&
2471 (status & ALE_RD_TCP_UDPCSUM_NOK) == 0) {
2472 p = mtod(m, char *);
2474 if ((status & ALE_RD_802_3) != 0)
2475 p += LLC_SNAPFRAMELEN;
2476 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) == 0 &&
2477 (status & ALE_RD_VLAN) != 0)
2478 p += ETHER_VLAN_ENCAP_LEN;
2479 ip = (struct ip *)p;
2480 if (ip->ip_off != 0 && (status & ALE_RD_IPV4_DF) == 0)
2482 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID |
2484 m->m_pkthdr.csum_data = 0xffff;
2488 * Don't mark bad checksum for TCP/UDP frames
2489 * as fragmented frames may always have set
2490 * bad checksummed bit of frame status.
2494 /* Process received frames. */
2496 ale_rxeof(struct ale_softc *sc, int count)
2498 struct ale_rx_page *rx_page;
2502 uint32_t length, prod, seqno, status, vtags;
2506 rx_page = &sc->ale_cdata.ale_rx_page[sc->ale_cdata.ale_rx_curp];
2507 bus_dmamap_sync(rx_page->cmb_tag, rx_page->cmb_map,
2508 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2509 bus_dmamap_sync(rx_page->page_tag, rx_page->page_map,
2510 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2512 * Don't directly access producer index as hardware may
2513 * update it while Rx handler is in progress. It would
2514 * be even better if there is a way to let hardware
2515 * know how far driver processed its received frames.
2516 * Alternatively, hardware could provide a way to disable
2517 * CMB updates until driver acknowledges the end of CMB
2520 prod = *rx_page->cmb_addr;
2521 for (prog = 0; prog < count; prog++) {
2522 if (rx_page->cons >= prod)
2524 rs = (struct rx_rs *)(rx_page->page_addr + rx_page->cons);
2525 seqno = ALE_RX_SEQNO(le32toh(rs->seqno));
2526 if (sc->ale_cdata.ale_rx_seqno != seqno) {
2528 * Normally I believe this should not happen unless
2529 * severe driver bug or corrupted memory. However
2530 * it seems to happen under certain conditions which
2531 * is triggered by abrupt Rx events such as initiation
2532 * of bulk transfer of remote host. It's not easy to
2533 * reproduce this and I doubt it could be related
2534 * with FIFO overflow of hardware or activity of Tx
2535 * CMB updates. I also remember similar behaviour
2536 * seen on RealTek 8139 which uses resembling Rx
2540 device_printf(sc->ale_dev,
2541 "garbled seq: %u, expected: %u -- "
2542 "resetting!\n", seqno,
2543 sc->ale_cdata.ale_rx_seqno);
2546 /* Frame received. */
2547 sc->ale_cdata.ale_rx_seqno++;
2548 length = ALE_RX_BYTES(le32toh(rs->length));
2549 status = le32toh(rs->flags);
2550 if ((status & ALE_RD_ERROR) != 0) {
2552 * We want to pass the following frames to upper
2553 * layer regardless of error status of Rx return
2556 * o IP/TCP/UDP checksum is bad.
2557 * o frame length and protocol specific length
2560 if ((status & (ALE_RD_CRC | ALE_RD_CODE |
2561 ALE_RD_DRIBBLE | ALE_RD_RUNT | ALE_RD_OFLOW |
2562 ALE_RD_TRUNC)) != 0) {
2563 ale_rx_update_page(sc, &rx_page, length, &prod);
2568 * m_devget(9) is major bottle-neck of ale(4)(It comes
2569 * from hardware limitation). For jumbo frames we could
2570 * get a slightly better performance if driver use
2571 * m_getjcl(9) with proper buffer size argument. However
2572 * that would make code more complicated and I don't
2573 * think users would expect good Rx performance numbers
2574 * on these low-end consumer ethernet controller.
2576 m = m_devget((char *)(rs + 1), length - ETHER_CRC_LEN,
2577 ETHER_ALIGN, ifp, NULL);
2580 ale_rx_update_page(sc, &rx_page, length, &prod);
2583 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0 &&
2584 (status & ALE_RD_IPV4) != 0)
2585 ale_rxcsum(sc, m, status);
2586 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0 &&
2587 (status & ALE_RD_VLAN) != 0) {
2588 vtags = ALE_RX_VLAN(le32toh(rs->vtags));
2589 m->m_pkthdr.ether_vtag = ALE_RX_VLAN_TAG(vtags);
2590 m->m_flags |= M_VLANTAG;
2593 /* Pass it to upper layer. */
2594 (*ifp->if_input)(ifp, m);
2596 ale_rx_update_page(sc, &rx_page, length, &prod);
2599 return (count > 0 ? 0 : EAGAIN);
2605 struct ale_softc *sc;
2606 struct mii_data *mii;
2608 sc = (struct ale_softc *)arg;
2610 ALE_LOCK_ASSERT(sc);
2612 mii = device_get_softc(sc->ale_miibus);
2614 ale_stats_update(sc);
2616 * Reclaim Tx buffers that have been transferred. It's not
2617 * needed here but it would release allocated mbuf chains
2618 * faster and limit the maximum delay to a hz.
2622 callout_reset(&sc->ale_tick_ch, hz, ale_tick, sc);
2626 ale_reset(struct ale_softc *sc)
2631 /* Initialize PCIe module. From Linux. */
2632 CSR_WRITE_4(sc, 0x1008, CSR_READ_4(sc, 0x1008) | 0x8000);
2634 CSR_WRITE_4(sc, ALE_MASTER_CFG, MASTER_RESET);
2635 for (i = ALE_RESET_TIMEOUT; i > 0; i--) {
2637 if ((CSR_READ_4(sc, ALE_MASTER_CFG) & MASTER_RESET) == 0)
2641 device_printf(sc->ale_dev, "master reset timeout!\n");
2643 for (i = ALE_RESET_TIMEOUT; i > 0; i--) {
2644 if ((reg = CSR_READ_4(sc, ALE_IDLE_STATUS)) == 0)
2650 device_printf(sc->ale_dev, "reset timeout(0x%08x)!\n", reg);
2656 struct ale_softc *sc;
2658 sc = (struct ale_softc *)xsc;
2660 ale_init_locked(sc);
2665 ale_init_locked(struct ale_softc *sc)
2668 struct mii_data *mii;
2669 uint8_t eaddr[ETHER_ADDR_LEN];
2671 uint32_t reg, rxf_hi, rxf_lo;
2673 ALE_LOCK_ASSERT(sc);
2676 mii = device_get_softc(sc->ale_miibus);
2678 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
2681 * Cancel any pending I/O.
2685 * Reset the chip to a known state.
2688 /* Initialize Tx descriptors, DMA memory blocks. */
2689 ale_init_rx_pages(sc);
2690 ale_init_tx_ring(sc);
2692 /* Reprogram the station address. */
2693 bcopy(IF_LLADDR(ifp), eaddr, ETHER_ADDR_LEN);
2694 CSR_WRITE_4(sc, ALE_PAR0,
2695 eaddr[2] << 24 | eaddr[3] << 16 | eaddr[4] << 8 | eaddr[5]);
2696 CSR_WRITE_4(sc, ALE_PAR1, eaddr[0] << 8 | eaddr[1]);
2698 * Clear WOL status and disable all WOL feature as WOL
2699 * would interfere Rx operation under normal environments.
2701 CSR_READ_4(sc, ALE_WOL_CFG);
2702 CSR_WRITE_4(sc, ALE_WOL_CFG, 0);
2704 * Set Tx descriptor/RXF0/CMB base addresses. They share
2705 * the same high address part of DMAable region.
2707 paddr = sc->ale_cdata.ale_tx_ring_paddr;
2708 CSR_WRITE_4(sc, ALE_TPD_ADDR_HI, ALE_ADDR_HI(paddr));
2709 CSR_WRITE_4(sc, ALE_TPD_ADDR_LO, ALE_ADDR_LO(paddr));
2710 CSR_WRITE_4(sc, ALE_TPD_CNT,
2711 (ALE_TX_RING_CNT << TPD_CNT_SHIFT) & TPD_CNT_MASK);
2712 /* Set Rx page base address, note we use single queue. */
2713 paddr = sc->ale_cdata.ale_rx_page[0].page_paddr;
2714 CSR_WRITE_4(sc, ALE_RXF0_PAGE0_ADDR_LO, ALE_ADDR_LO(paddr));
2715 paddr = sc->ale_cdata.ale_rx_page[1].page_paddr;
2716 CSR_WRITE_4(sc, ALE_RXF0_PAGE1_ADDR_LO, ALE_ADDR_LO(paddr));
2717 /* Set Tx/Rx CMB addresses. */
2718 paddr = sc->ale_cdata.ale_tx_cmb_paddr;
2719 CSR_WRITE_4(sc, ALE_TX_CMB_ADDR_LO, ALE_ADDR_LO(paddr));
2720 paddr = sc->ale_cdata.ale_rx_page[0].cmb_paddr;
2721 CSR_WRITE_4(sc, ALE_RXF0_CMB0_ADDR_LO, ALE_ADDR_LO(paddr));
2722 paddr = sc->ale_cdata.ale_rx_page[1].cmb_paddr;
2723 CSR_WRITE_4(sc, ALE_RXF0_CMB1_ADDR_LO, ALE_ADDR_LO(paddr));
2724 /* Mark RXF0 is valid. */
2725 CSR_WRITE_1(sc, ALE_RXF0_PAGE0, RXF_VALID);
2726 CSR_WRITE_1(sc, ALE_RXF0_PAGE1, RXF_VALID);
2728 * No need to initialize RFX1/RXF2/RXF3. We don't use
2732 /* Set Rx page size, excluding guard frame size. */
2733 CSR_WRITE_4(sc, ALE_RXF_PAGE_SIZE, ALE_RX_PAGE_SZ);
2734 /* Tell hardware that we're ready to load DMA blocks. */
2735 CSR_WRITE_4(sc, ALE_DMA_BLOCK, DMA_BLOCK_LOAD);
2737 /* Set Rx/Tx interrupt trigger threshold. */
2738 CSR_WRITE_4(sc, ALE_INT_TRIG_THRESH, (1 << INT_TRIG_RX_THRESH_SHIFT) |
2739 (4 << INT_TRIG_TX_THRESH_SHIFT));
2742 * Set interrupt trigger timer, its purpose and relation
2743 * with interrupt moderation mechanism is not clear yet.
2745 CSR_WRITE_4(sc, ALE_INT_TRIG_TIMER,
2746 ((ALE_USECS(10) << INT_TRIG_RX_TIMER_SHIFT) |
2747 (ALE_USECS(1000) << INT_TRIG_TX_TIMER_SHIFT)));
2749 /* Configure interrupt moderation timer. */
2750 reg = ALE_USECS(sc->ale_int_rx_mod) << IM_TIMER_RX_SHIFT;
2751 reg |= ALE_USECS(sc->ale_int_tx_mod) << IM_TIMER_TX_SHIFT;
2752 CSR_WRITE_4(sc, ALE_IM_TIMER, reg);
2753 reg = CSR_READ_4(sc, ALE_MASTER_CFG);
2754 reg &= ~(MASTER_CHIP_REV_MASK | MASTER_CHIP_ID_MASK);
2755 reg &= ~(MASTER_IM_RX_TIMER_ENB | MASTER_IM_TX_TIMER_ENB);
2756 if (ALE_USECS(sc->ale_int_rx_mod) != 0)
2757 reg |= MASTER_IM_RX_TIMER_ENB;
2758 if (ALE_USECS(sc->ale_int_tx_mod) != 0)
2759 reg |= MASTER_IM_TX_TIMER_ENB;
2760 CSR_WRITE_4(sc, ALE_MASTER_CFG, reg);
2761 CSR_WRITE_2(sc, ALE_INTR_CLR_TIMER, ALE_USECS(1000));
2763 /* Set Maximum frame size of controller. */
2764 if (ifp->if_mtu < ETHERMTU)
2765 sc->ale_max_frame_size = ETHERMTU;
2767 sc->ale_max_frame_size = ifp->if_mtu;
2768 sc->ale_max_frame_size += ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN +
2770 CSR_WRITE_4(sc, ALE_FRAME_SIZE, sc->ale_max_frame_size);
2771 /* Configure IPG/IFG parameters. */
2772 CSR_WRITE_4(sc, ALE_IPG_IFG_CFG,
2773 ((IPG_IFG_IPGT_DEFAULT << IPG_IFG_IPGT_SHIFT) & IPG_IFG_IPGT_MASK) |
2774 ((IPG_IFG_MIFG_DEFAULT << IPG_IFG_MIFG_SHIFT) & IPG_IFG_MIFG_MASK) |
2775 ((IPG_IFG_IPG1_DEFAULT << IPG_IFG_IPG1_SHIFT) & IPG_IFG_IPG1_MASK) |
2776 ((IPG_IFG_IPG2_DEFAULT << IPG_IFG_IPG2_SHIFT) & IPG_IFG_IPG2_MASK));
2777 /* Set parameters for half-duplex media. */
2778 CSR_WRITE_4(sc, ALE_HDPX_CFG,
2779 ((HDPX_CFG_LCOL_DEFAULT << HDPX_CFG_LCOL_SHIFT) &
2780 HDPX_CFG_LCOL_MASK) |
2781 ((HDPX_CFG_RETRY_DEFAULT << HDPX_CFG_RETRY_SHIFT) &
2782 HDPX_CFG_RETRY_MASK) | HDPX_CFG_EXC_DEF_EN |
2783 ((HDPX_CFG_ABEBT_DEFAULT << HDPX_CFG_ABEBT_SHIFT) &
2784 HDPX_CFG_ABEBT_MASK) |
2785 ((HDPX_CFG_JAMIPG_DEFAULT << HDPX_CFG_JAMIPG_SHIFT) &
2786 HDPX_CFG_JAMIPG_MASK));
2788 /* Configure Tx jumbo frame parameters. */
2789 if ((sc->ale_flags & ALE_FLAG_JUMBO) != 0) {
2790 if (ifp->if_mtu < ETHERMTU)
2791 reg = sc->ale_max_frame_size;
2792 else if (ifp->if_mtu < 6 * 1024)
2793 reg = (sc->ale_max_frame_size * 2) / 3;
2795 reg = sc->ale_max_frame_size / 2;
2796 CSR_WRITE_4(sc, ALE_TX_JUMBO_THRESH,
2797 roundup(reg, TX_JUMBO_THRESH_UNIT) >>
2798 TX_JUMBO_THRESH_UNIT_SHIFT);
2800 /* Configure TxQ. */
2801 reg = (128 << (sc->ale_dma_rd_burst >> DMA_CFG_RD_BURST_SHIFT))
2802 << TXQ_CFG_TX_FIFO_BURST_SHIFT;
2803 reg |= (TXQ_CFG_TPD_BURST_DEFAULT << TXQ_CFG_TPD_BURST_SHIFT) &
2804 TXQ_CFG_TPD_BURST_MASK;
2805 CSR_WRITE_4(sc, ALE_TXQ_CFG, reg | TXQ_CFG_ENHANCED_MODE | TXQ_CFG_ENB);
2807 /* Configure Rx jumbo frame & flow control parameters. */
2808 if ((sc->ale_flags & ALE_FLAG_JUMBO) != 0) {
2809 reg = roundup(sc->ale_max_frame_size, RX_JUMBO_THRESH_UNIT);
2810 CSR_WRITE_4(sc, ALE_RX_JUMBO_THRESH,
2811 (((reg >> RX_JUMBO_THRESH_UNIT_SHIFT) <<
2812 RX_JUMBO_THRESH_MASK_SHIFT) & RX_JUMBO_THRESH_MASK) |
2813 ((RX_JUMBO_LKAH_DEFAULT << RX_JUMBO_LKAH_SHIFT) &
2814 RX_JUMBO_LKAH_MASK));
2815 reg = CSR_READ_4(sc, ALE_SRAM_RX_FIFO_LEN);
2816 rxf_hi = (reg * 7) / 10;
2817 rxf_lo = (reg * 3)/ 10;
2818 CSR_WRITE_4(sc, ALE_RX_FIFO_PAUSE_THRESH,
2819 ((rxf_lo << RX_FIFO_PAUSE_THRESH_LO_SHIFT) &
2820 RX_FIFO_PAUSE_THRESH_LO_MASK) |
2821 ((rxf_hi << RX_FIFO_PAUSE_THRESH_HI_SHIFT) &
2822 RX_FIFO_PAUSE_THRESH_HI_MASK));
2826 CSR_WRITE_4(sc, ALE_RSS_IDT_TABLE0, 0);
2827 CSR_WRITE_4(sc, ALE_RSS_CPU, 0);
2829 /* Configure RxQ. */
2830 CSR_WRITE_4(sc, ALE_RXQ_CFG,
2831 RXQ_CFG_ALIGN_32 | RXQ_CFG_CUT_THROUGH_ENB | RXQ_CFG_ENB);
2833 /* Configure DMA parameters. */
2835 if ((sc->ale_flags & ALE_FLAG_TXCMB_BUG) == 0)
2836 reg |= DMA_CFG_TXCMB_ENB;
2837 CSR_WRITE_4(sc, ALE_DMA_CFG,
2838 DMA_CFG_OUT_ORDER | DMA_CFG_RD_REQ_PRI | DMA_CFG_RCB_64 |
2839 sc->ale_dma_rd_burst | reg |
2840 sc->ale_dma_wr_burst | DMA_CFG_RXCMB_ENB |
2841 ((DMA_CFG_RD_DELAY_CNT_DEFAULT << DMA_CFG_RD_DELAY_CNT_SHIFT) &
2842 DMA_CFG_RD_DELAY_CNT_MASK) |
2843 ((DMA_CFG_WR_DELAY_CNT_DEFAULT << DMA_CFG_WR_DELAY_CNT_SHIFT) &
2844 DMA_CFG_WR_DELAY_CNT_MASK));
2847 * Hardware can be configured to issue SMB interrupt based
2848 * on programmed interval. Since there is a callout that is
2849 * invoked for every hz in driver we use that instead of
2850 * relying on periodic SMB interrupt.
2852 CSR_WRITE_4(sc, ALE_SMB_STAT_TIMER, ALE_USECS(0));
2853 /* Clear MAC statistics. */
2854 ale_stats_clear(sc);
2857 * Configure Tx/Rx MACs.
2858 * - Auto-padding for short frames.
2859 * - Enable CRC generation.
2860 * Actual reconfiguration of MAC for resolved speed/duplex
2861 * is followed after detection of link establishment.
2862 * AR81xx always does checksum computation regardless of
2863 * MAC_CFG_RXCSUM_ENB bit. In fact, setting the bit will
2864 * cause Rx handling issue for fragmented IP datagrams due
2867 reg = MAC_CFG_TX_CRC_ENB | MAC_CFG_TX_AUTO_PAD | MAC_CFG_FULL_DUPLEX |
2868 ((MAC_CFG_PREAMBLE_DEFAULT << MAC_CFG_PREAMBLE_SHIFT) &
2869 MAC_CFG_PREAMBLE_MASK);
2870 if ((sc->ale_flags & ALE_FLAG_FASTETHER) != 0)
2871 reg |= MAC_CFG_SPEED_10_100;
2873 reg |= MAC_CFG_SPEED_1000;
2874 CSR_WRITE_4(sc, ALE_MAC_CFG, reg);
2876 /* Set up the receive filter. */
2880 /* Acknowledge all pending interrupts and clear it. */
2881 CSR_WRITE_4(sc, ALE_INTR_MASK, ALE_INTRS);
2882 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0xFFFFFFFF);
2883 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0);
2885 sc->ale_flags &= ~ALE_FLAG_LINK;
2886 /* Switch to the current media. */
2889 callout_reset(&sc->ale_tick_ch, hz, ale_tick, sc);
2891 ifp->if_drv_flags |= IFF_DRV_RUNNING;
2892 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2896 ale_stop(struct ale_softc *sc)
2899 struct ale_txdesc *txd;
2903 ALE_LOCK_ASSERT(sc);
2905 * Mark the interface down and cancel the watchdog timer.
2908 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
2909 sc->ale_flags &= ~ALE_FLAG_LINK;
2910 callout_stop(&sc->ale_tick_ch);
2911 sc->ale_watchdog_timer = 0;
2912 ale_stats_update(sc);
2913 /* Disable interrupts. */
2914 CSR_WRITE_4(sc, ALE_INTR_MASK, 0);
2915 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0xFFFFFFFF);
2916 /* Disable queue processing and DMA. */
2917 reg = CSR_READ_4(sc, ALE_TXQ_CFG);
2918 reg &= ~TXQ_CFG_ENB;
2919 CSR_WRITE_4(sc, ALE_TXQ_CFG, reg);
2920 reg = CSR_READ_4(sc, ALE_RXQ_CFG);
2921 reg &= ~RXQ_CFG_ENB;
2922 CSR_WRITE_4(sc, ALE_RXQ_CFG, reg);
2923 reg = CSR_READ_4(sc, ALE_DMA_CFG);
2924 reg &= ~(DMA_CFG_TXCMB_ENB | DMA_CFG_RXCMB_ENB);
2925 CSR_WRITE_4(sc, ALE_DMA_CFG, reg);
2927 /* Stop Rx/Tx MACs. */
2929 /* Disable interrupts which might be touched in taskq handler. */
2930 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0xFFFFFFFF);
2933 * Free TX mbufs still in the queues.
2935 for (i = 0; i < ALE_TX_RING_CNT; i++) {
2936 txd = &sc->ale_cdata.ale_txdesc[i];
2937 if (txd->tx_m != NULL) {
2938 bus_dmamap_sync(sc->ale_cdata.ale_tx_tag,
2939 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE);
2940 bus_dmamap_unload(sc->ale_cdata.ale_tx_tag,
2949 ale_stop_mac(struct ale_softc *sc)
2954 ALE_LOCK_ASSERT(sc);
2956 reg = CSR_READ_4(sc, ALE_MAC_CFG);
2957 if ((reg & (MAC_CFG_TX_ENB | MAC_CFG_RX_ENB)) != 0) {
2958 reg &= ~MAC_CFG_TX_ENB | MAC_CFG_RX_ENB;
2959 CSR_WRITE_4(sc, ALE_MAC_CFG, reg);
2962 for (i = ALE_TIMEOUT; i > 0; i--) {
2963 reg = CSR_READ_4(sc, ALE_IDLE_STATUS);
2969 device_printf(sc->ale_dev,
2970 "could not disable Tx/Rx MAC(0x%08x)!\n", reg);
2974 ale_init_tx_ring(struct ale_softc *sc)
2976 struct ale_txdesc *txd;
2979 ALE_LOCK_ASSERT(sc);
2981 sc->ale_cdata.ale_tx_prod = 0;
2982 sc->ale_cdata.ale_tx_cons = 0;
2983 sc->ale_cdata.ale_tx_cnt = 0;
2985 bzero(sc->ale_cdata.ale_tx_ring, ALE_TX_RING_SZ);
2986 bzero(sc->ale_cdata.ale_tx_cmb, ALE_TX_CMB_SZ);
2987 for (i = 0; i < ALE_TX_RING_CNT; i++) {
2988 txd = &sc->ale_cdata.ale_txdesc[i];
2991 *sc->ale_cdata.ale_tx_cmb = 0;
2992 bus_dmamap_sync(sc->ale_cdata.ale_tx_cmb_tag,
2993 sc->ale_cdata.ale_tx_cmb_map,
2994 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2995 bus_dmamap_sync(sc->ale_cdata.ale_tx_ring_tag,
2996 sc->ale_cdata.ale_tx_ring_map,
2997 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3001 ale_init_rx_pages(struct ale_softc *sc)
3003 struct ale_rx_page *rx_page;
3006 ALE_LOCK_ASSERT(sc);
3008 atomic_set_int(&sc->ale_morework, 0);
3009 sc->ale_cdata.ale_rx_seqno = 0;
3010 sc->ale_cdata.ale_rx_curp = 0;
3012 for (i = 0; i < ALE_RX_PAGES; i++) {
3013 rx_page = &sc->ale_cdata.ale_rx_page[i];
3014 bzero(rx_page->page_addr, sc->ale_pagesize);
3015 bzero(rx_page->cmb_addr, ALE_RX_CMB_SZ);
3017 *rx_page->cmb_addr = 0;
3018 bus_dmamap_sync(rx_page->page_tag, rx_page->page_map,
3019 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3020 bus_dmamap_sync(rx_page->cmb_tag, rx_page->cmb_map,
3021 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3026 ale_rxvlan(struct ale_softc *sc)
3031 ALE_LOCK_ASSERT(sc);
3034 reg = CSR_READ_4(sc, ALE_MAC_CFG);
3035 reg &= ~MAC_CFG_VLAN_TAG_STRIP;
3036 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0)
3037 reg |= MAC_CFG_VLAN_TAG_STRIP;
3038 CSR_WRITE_4(sc, ALE_MAC_CFG, reg);
3042 ale_rxfilter(struct ale_softc *sc)
3045 struct ifmultiaddr *ifma;
3050 ALE_LOCK_ASSERT(sc);
3054 rxcfg = CSR_READ_4(sc, ALE_MAC_CFG);
3055 rxcfg &= ~(MAC_CFG_ALLMULTI | MAC_CFG_BCAST | MAC_CFG_PROMISC);
3056 if ((ifp->if_flags & IFF_BROADCAST) != 0)
3057 rxcfg |= MAC_CFG_BCAST;
3058 if ((ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) != 0) {
3059 if ((ifp->if_flags & IFF_PROMISC) != 0)
3060 rxcfg |= MAC_CFG_PROMISC;
3061 if ((ifp->if_flags & IFF_ALLMULTI) != 0)
3062 rxcfg |= MAC_CFG_ALLMULTI;
3063 CSR_WRITE_4(sc, ALE_MAR0, 0xFFFFFFFF);
3064 CSR_WRITE_4(sc, ALE_MAR1, 0xFFFFFFFF);
3065 CSR_WRITE_4(sc, ALE_MAC_CFG, rxcfg);
3069 /* Program new filter. */
3070 bzero(mchash, sizeof(mchash));
3072 if_maddr_rlock(ifp);
3073 TAILQ_FOREACH(ifma, &sc->ale_ifp->if_multiaddrs, ifma_link) {
3074 if (ifma->ifma_addr->sa_family != AF_LINK)
3076 crc = ether_crc32_be(LLADDR((struct sockaddr_dl *)
3077 ifma->ifma_addr), ETHER_ADDR_LEN);
3078 mchash[crc >> 31] |= 1 << ((crc >> 26) & 0x1f);
3080 if_maddr_runlock(ifp);
3082 CSR_WRITE_4(sc, ALE_MAR0, mchash[0]);
3083 CSR_WRITE_4(sc, ALE_MAR1, mchash[1]);
3084 CSR_WRITE_4(sc, ALE_MAC_CFG, rxcfg);
3088 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high)
3094 value = *(int *)arg1;
3095 error = sysctl_handle_int(oidp, &value, 0, req);
3096 if (error || req->newptr == NULL)
3098 if (value < low || value > high)
3100 *(int *)arg1 = value;
3106 sysctl_hw_ale_proc_limit(SYSCTL_HANDLER_ARGS)
3108 return (sysctl_int_range(oidp, arg1, arg2, req,
3109 ALE_PROC_MIN, ALE_PROC_MAX));
3113 sysctl_hw_ale_int_mod(SYSCTL_HANDLER_ARGS)
3116 return (sysctl_int_range(oidp, arg1, arg2, req,
3117 ALE_IM_TIMER_MIN, ALE_IM_TIMER_MAX));