2 ***********************************************************************************************
4 ** FILE NAME : arcmsr.h
6 ** Description: SCSI RAID Device Driver for
7 ** ARECA SATA RAID HOST Adapter
8 ** [RAID controller:INTEL 331(PCI-X) 341(PCI-EXPRESS) chip set]
9 ***********************************************************************************************
10 ************************************************************************
11 ** Copyright (C) 2002 - 2005, Areca Technology Corporation All rights reserved.
13 ** Web site: www.areca.com.tw
14 ** E-mail: erich@areca.com.tw
16 ** Redistribution and use in source and binary forms,with or without
17 ** modification,are permitted provided that the following conditions
19 ** 1. Redistributions of source code must retain the above copyright
20 ** notice,this list of conditions and the following disclaimer.
21 ** 2. Redistributions in binary form must reproduce the above copyright
22 ** notice,this list of conditions and the following disclaimer in the
23 ** documentation and/or other materials provided with the distribution.
24 ** 3. The name of the author may not be used to endorse or promote products
25 ** derived from this software without specific prior written permission.
27 ** THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
28 ** IMPLIED WARRANTIES,INCLUDING,BUT NOT LIMITED TO,THE IMPLIED WARRANTIES
29 ** OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
30 ** IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,INDIRECT,
31 ** INCIDENTAL,SPECIAL,EXEMPLARY,OR CONSEQUENTIAL DAMAGES(INCLUDING,BUT
32 ** NOT LIMITED TO,PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
33 ** DATA,OR PROFITS; OR BUSINESS INTERRUPTION)HOWEVER CAUSED AND ON ANY
34 ** THEORY OF LIABILITY,WHETHER IN CONTRACT,STRICT LIABILITY,OR TORT
35 **(INCLUDING NEGLIGENCE OR OTHERWISE)ARISING IN ANY WAY OUT OF THE USE OF
36 ** THIS SOFTWARE,EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37 **************************************************************************
40 #define ARCMSR_DRIVER_VERSION "Driver Version 1.20.00.16 2009-10-10"
41 #define ARCMSR_SCSI_INITIATOR_ID 255
42 #define ARCMSR_DEV_SECTOR_SIZE 512
43 #define ARCMSR_MAX_XFER_SECTORS 4096
44 #define ARCMSR_MAX_TARGETID 16 /*16 max target id + 1*/
45 #define ARCMSR_MAX_TARGETLUN 8 /*8*/
46 #define ARCMSR_MAX_CHIPTYPE_NUM 4
47 #define ARCMSR_MAX_OUTSTANDING_CMD 256
48 #define ARCMSR_MAX_START_JOB 257
49 #define ARCMSR_MAX_CMD_PERLUN ARCMSR_MAX_OUTSTANDING_CMD
50 #define ARCMSR_MAX_FREESRB_NUM 320
51 #define ARCMSR_MAX_QBUFFER 4096 /* ioctl QBUFFER */
52 #define ARCMSR_MAX_SG_ENTRIES 38 /* max 38*/
53 #define ARCMSR_MAX_ADAPTER 4
54 #define ARCMSR_RELEASE_SIMQ_LEVEL 230
55 #define ARCMSR_MAX_HBB_POSTQUEUE 264 /* (ARCMSR_MAX_OUTSTANDING_CMD+8) */
57 *********************************************************************
66 # define INTR_ENTROPY 0
70 #define offsetof(type, member) ((size_t)(&((type *)0)->member))
73 **********************************************************************************
75 **********************************************************************************
77 #define PCI_VENDOR_ID_ARECA 0x17D3 /* Vendor ID */
78 #define PCI_DEVICE_ID_ARECA_1110 0x1110 /* Device ID */
79 #define PCI_DEVICE_ID_ARECA_1120 0x1120 /* Device ID */
80 #define PCI_DEVICE_ID_ARECA_1130 0x1130 /* Device ID */
81 #define PCI_DEVICE_ID_ARECA_1160 0x1160 /* Device ID */
82 #define PCI_DEVICE_ID_ARECA_1170 0x1170 /* Device ID */
83 #define PCI_DEVICE_ID_ARECA_1210 0x1210 /* Device ID */
84 #define PCI_DEVICE_ID_ARECA_1220 0x1220 /* Device ID */
85 #define PCI_DEVICE_ID_ARECA_1230 0x1230 /* Device ID */
86 #define PCI_DEVICE_ID_ARECA_1260 0x1260 /* Device ID */
87 #define PCI_DEVICE_ID_ARECA_1270 0x1270 /* Device ID */
88 #define PCI_DEVICE_ID_ARECA_1280 0x1280 /* Device ID */
89 #define PCI_DEVICE_ID_ARECA_1380 0x1380 /* Device ID */
90 #define PCI_DEVICE_ID_ARECA_1381 0x1381 /* Device ID */
91 #define PCI_DEVICE_ID_ARECA_1680 0x1680 /* Device ID */
92 #define PCI_DEVICE_ID_ARECA_1681 0x1681 /* Device ID */
93 #define PCI_DEVICE_ID_ARECA_1201 0x1201 /* Device ID */
95 #define PCIDevVenIDARC1110 0x111017D3 /* Vendor Device ID */
96 #define PCIDevVenIDARC1120 0x112017D3 /* Vendor Device ID */
97 #define PCIDevVenIDARC1130 0x113017D3 /* Vendor Device ID */
98 #define PCIDevVenIDARC1160 0x116017D3 /* Vendor Device ID */
99 #define PCIDevVenIDARC1170 0x117017D3 /* Vendor Device ID */
100 #define PCIDevVenIDARC1210 0x121017D3 /* Vendor Device ID */
101 #define PCIDevVenIDARC1220 0x122017D3 /* Vendor Device ID */
102 #define PCIDevVenIDARC1230 0x123017D3 /* Vendor Device ID */
103 #define PCIDevVenIDARC1260 0x126017D3 /* Vendor Device ID */
104 #define PCIDevVenIDARC1270 0x127017D3 /* Vendor Device ID */
105 #define PCIDevVenIDARC1280 0x128017D3 /* Vendor Device ID */
106 #define PCIDevVenIDARC1380 0x138017D3 /* Vendor Device ID */
107 #define PCIDevVenIDARC1381 0x138117D3 /* Vendor Device ID */
108 #define PCIDevVenIDARC1680 0x168017D3 /* Vendor Device ID */
109 #define PCIDevVenIDARC1681 0x168117D3 /* Vendor Device ID */
110 #define PCIDevVenIDARC1201 0x120117D3 /* Vendor Device ID */
113 #define PCIR_BARS 0x10
114 #define PCIR_BAR(x) (PCIR_BARS + (x) * 4)
117 #define PCI_BASE_ADDR0 0x10
118 #define PCI_BASE_ADDR1 0x14
119 #define PCI_BASE_ADDR2 0x18
120 #define PCI_BASE_ADDR3 0x1C
121 #define PCI_BASE_ADDR4 0x20
122 #define PCI_BASE_ADDR5 0x24
124 **********************************************************************************
126 **********************************************************************************
128 #define ARCMSR_SCSICMD_IOCTL 0x77
129 #define ARCMSR_CDEVSW_IOCTL 0x88
130 #define ARCMSR_MESSAGE_FAIL 0x0001
131 #define ARCMSR_MESSAGE_SUCCESS 0x0000
133 **********************************************************************************
135 **********************************************************************************
137 #define arcmsr_ccbsrb_ptr spriv_ptr0
138 #define arcmsr_ccbacb_ptr spriv_ptr1
139 #define dma_addr_hi32(addr) (u_int32_t) ((addr>>16)>>16)
140 #define dma_addr_lo32(addr) (u_int32_t) (addr & 0xffffffff)
141 #define get_min(x,y) ((x) < (y) ? (x) : (y))
142 #define get_max(x,y) ((x) < (y) ? (y) : (x))
144 **********************************************************************************
146 **********************************************************************************
148 #define ARCMSR_IOP_ERROR_ILLEGALPCI 0x0001
149 #define ARCMSR_IOP_ERROR_VENDORID 0x0002
150 #define ARCMSR_IOP_ERROR_DEVICEID 0x0002
151 #define ARCMSR_IOP_ERROR_ILLEGALCDB 0x0003
152 #define ARCMSR_IOP_ERROR_UNKNOW_CDBERR 0x0004
153 #define ARCMSR_SYS_ERROR_MEMORY_ALLOCATE 0x0005
154 #define ARCMSR_SYS_ERROR_MEMORY_CROSS4G 0x0006
155 #define ARCMSR_SYS_ERROR_MEMORY_LACK 0x0007
156 #define ARCMSR_SYS_ERROR_MEMORY_RANGE 0x0008
157 #define ARCMSR_SYS_ERROR_DEVICE_BASE 0x0009
158 #define ARCMSR_SYS_ERROR_PORT_VALIDATE 0x000A
160 #define ARECA_SATA_RAID 0x90000000
162 #define FUNCTION_READ_RQBUFFER 0x0801
163 #define FUNCTION_WRITE_WQBUFFER 0x0802
164 #define FUNCTION_CLEAR_RQBUFFER 0x0803
165 #define FUNCTION_CLEAR_WQBUFFER 0x0804
166 #define FUNCTION_CLEAR_ALLQBUFFER 0x0805
167 #define FUNCTION_REQUEST_RETURNCODE_3F 0x0806
168 #define FUNCTION_SAY_HELLO 0x0807
169 #define FUNCTION_SAY_GOODBYE 0x0808
170 #define FUNCTION_FLUSH_ADAPTER_CACHE 0x0809
172 ************************************************************************
173 ** IOCTL CONTROL CODE
174 ************************************************************************
177 u_int32_t HeaderLength;
178 u_int8_t Signature[8];
180 u_int32_t ControlCode;
181 u_int32_t ReturnCode;
185 struct CMD_MESSAGE_FIELD {
186 struct CMD_MESSAGE cmdmessage; /* ioctl header */
187 u_int8_t messagedatabuffer[1032]; /* areca gui program does not accept more than 1031 byte */
189 /* ARECA IO CONTROL CODE*/
190 #define ARCMSR_MESSAGE_READ_RQBUFFER _IOWR('F', FUNCTION_READ_RQBUFFER, struct CMD_MESSAGE_FIELD)
191 #define ARCMSR_MESSAGE_WRITE_WQBUFFER _IOWR('F', FUNCTION_WRITE_WQBUFFER, struct CMD_MESSAGE_FIELD)
192 #define ARCMSR_MESSAGE_CLEAR_RQBUFFER _IOWR('F', FUNCTION_CLEAR_RQBUFFER, struct CMD_MESSAGE_FIELD)
193 #define ARCMSR_MESSAGE_CLEAR_WQBUFFER _IOWR('F', FUNCTION_CLEAR_WQBUFFER, struct CMD_MESSAGE_FIELD)
194 #define ARCMSR_MESSAGE_CLEAR_ALLQBUFFER _IOWR('F', FUNCTION_CLEAR_ALLQBUFFER, struct CMD_MESSAGE_FIELD)
195 #define ARCMSR_MESSAGE_REQUEST_RETURNCODE_3F _IOWR('F', FUNCTION_REQUEST_RETURNCODE_3F, struct CMD_MESSAGE_FIELD)
196 #define ARCMSR_MESSAGE_SAY_HELLO _IOWR('F', FUNCTION_SAY_HELLO, struct CMD_MESSAGE_FIELD)
197 #define ARCMSR_MESSAGE_SAY_GOODBYE _IOWR('F', FUNCTION_SAY_GOODBYE, struct CMD_MESSAGE_FIELD)
198 #define ARCMSR_MESSAGE_FLUSH_ADAPTER_CACHE _IOWR('F', FUNCTION_FLUSH_ADAPTER_CACHE, struct CMD_MESSAGE_FIELD)
199 /* ARECA IOCTL ReturnCode */
200 #define ARCMSR_MESSAGE_RETURNCODE_OK 0x00000001
201 #define ARCMSR_MESSAGE_RETURNCODE_ERROR 0x00000006
202 #define ARCMSR_MESSAGE_RETURNCODE_3F 0x0000003F
204 ************************************************************************
205 ** SPEC. for Areca HBB adapter
206 ************************************************************************
208 /* ARECA HBB COMMAND for its FIRMWARE */
209 #define ARCMSR_DRV2IOP_DOORBELL 0x00020400 /* window of "instruction flags" from driver to iop */
210 #define ARCMSR_DRV2IOP_DOORBELL_MASK 0x00020404
211 #define ARCMSR_IOP2DRV_DOORBELL 0x00020408 /* window of "instruction flags" from iop to driver */
212 #define ARCMSR_IOP2DRV_DOORBELL_MASK 0x0002040C
213 /* ARECA FLAG LANGUAGE */
215 #define ARCMSR_IOP2DRV_DATA_WRITE_OK 0x00000001 /* ioctl transfer */
216 #define ARCMSR_IOP2DRV_DATA_READ_OK 0x00000002 /* ioctl transfer */
217 #define ARCMSR_IOP2DRV_CDB_DONE 0x00000004
218 #define ARCMSR_IOP2DRV_MESSAGE_CMD_DONE 0x00000008
220 #define ARCMSR_DOORBELL_HANDLE_INT 0x0000000F
221 #define ARCMSR_DOORBELL_INT_CLEAR_PATTERN 0xFF00FFF0
222 #define ARCMSR_MESSAGE_INT_CLEAR_PATTERN 0xFF00FFF7
224 #define ARCMSR_MESSAGE_GET_CONFIG 0x00010008 /* (ARCMSR_INBOUND_MESG0_GET_CONFIG<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */
225 #define ARCMSR_MESSAGE_SET_CONFIG 0x00020008 /* (ARCMSR_INBOUND_MESG0_SET_CONFIG<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */
226 #define ARCMSR_MESSAGE_ABORT_CMD 0x00030008 /* (ARCMSR_INBOUND_MESG0_ABORT_CMD<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */
227 #define ARCMSR_MESSAGE_STOP_BGRB 0x00040008 /* (ARCMSR_INBOUND_MESG0_STOP_BGRB<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */
228 #define ARCMSR_MESSAGE_FLUSH_CACHE 0x00050008 /* (ARCMSR_INBOUND_MESG0_FLUSH_CACHE<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */
229 #define ARCMSR_MESSAGE_START_BGRB 0x00060008 /* (ARCMSR_INBOUND_MESG0_START_BGRB<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */
230 #define ARCMSR_MESSAGE_START_DRIVER_MODE 0x000E0008
231 #define ARCMSR_MESSAGE_SET_POST_WINDOW 0x000F0008
232 #define ARCMSR_MESSAGE_ACTIVE_EOI_MODE 0x00100008
233 #define ARCMSR_MESSAGE_FIRMWARE_OK 0x80000000 /* ARCMSR_OUTBOUND_MESG1_FIRMWARE_OK */
235 #define ARCMSR_DRV2IOP_DATA_WRITE_OK 0x00000001 /* ioctl transfer */
236 #define ARCMSR_DRV2IOP_DATA_READ_OK 0x00000002 /* ioctl transfer */
237 #define ARCMSR_DRV2IOP_CDB_POSTED 0x00000004
238 #define ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED 0x00000008
239 #define ARCMSR_DRV2IOP_END_OF_INTERRUPT 0x00000010 /* */
241 /* data tunnel buffer between user space program and its firmware */
242 #define ARCMSR_MSGCODE_RWBUFFER 0x0000fa00 /* iop msgcode_rwbuffer for message command */
243 #define ARCMSR_IOCTL_WBUFFER 0x0000fe00 /* user space data to iop 128bytes */
244 #define ARCMSR_IOCTL_RBUFFER 0x0000ff00 /* iop data to user space 128bytes */
245 #define ARCMSR_HBB_BASE0_OFFSET 0x00000010
246 #define ARCMSR_HBB_BASE1_OFFSET 0x00000018
247 #define ARCMSR_HBB_BASE0_LEN 0x00021000
248 #define ARCMSR_HBB_BASE1_LEN 0x00010000
250 *************************************************************
251 ** structure for holding DMA address data
252 *************************************************************
254 #define IS_SG64_ADDR 0x01000000 /* bit24 */
256 ************************************************************************************************
257 ** ARECA FIRMWARE SPEC
258 ************************************************************************************************
259 ** Usage of IOP331 adapter
260 ** (All In/Out is in IOP331's view)
261 ** 1. Message 0 --> InitThread message and retrun code
262 ** 2. Doorbell is used for RS-232 emulation
263 ** inDoorBell : bit0 -- data in ready (DRIVER DATA WRITE OK)
264 ** bit1 -- data out has been read (DRIVER DATA READ OK)
265 ** outDooeBell: bit0 -- data out ready (IOP331 DATA WRITE OK)
266 ** bit1 -- data in has been read (IOP331 DATA READ OK)
267 ** 3. Index Memory Usage
268 ** offset 0xf00 : for RS232 out (request buffer)
269 ** offset 0xe00 : for RS232 in (scratch buffer)
270 ** offset 0xa00 : for inbound message code msgcode_rwbuffer (driver send to IOP331)
271 ** offset 0xa00 : for outbound message code msgcode_rwbuffer (IOP331 send to driver)
272 ** 4. RS-232 emulation
273 ** Currently 128 byte buffer is used
274 ** 1st u_int32_t : Data length (1--124)
275 ** Byte 4--127 : Max 124 bytes of data
277 ** All SCSI Command must be sent through postQ:
278 ** (inbound queue port) Request frame must be 32 bytes aligned
279 ** # bit27--bit31 => flag for post ccb
280 ** # bit0--bit26 => real address (bit27--bit31) of post arcmsr_cdb
281 ** bit31 : 0 : 256 bytes frame
282 ** 1 : 512 bytes frame
283 ** bit30 : 0 : normal request
288 ** -------------------------------------------------------------------------------
289 ** (outbount queue port) Request reply
290 ** # bit27--bit31 => flag for reply
291 ** # bit0--bit26 => real address (bit27--bit31) of reply arcmsr_cdb
292 ** bit31 : must be 0 (for this type of reply)
293 ** bit30 : reserved for BIOS handshake
295 ** bit28 : 0 : no error, ignore AdapStatus/DevStatus/SenseData
296 ** 1 : Error, error code in AdapStatus/DevStatus/SenseData
299 ** All BIOS request is the same with request from PostQ
301 ** Request frame is sent from configuration space
302 ** offset: 0x78 : Request Frame (bit30 == 1)
303 ** offset: 0x18 : writeonly to generate IRQ to IOP331
304 ** Completion of request:
305 ** (bit30 == 0, bit28==err flag)
306 ** 7. Definition of SGL entry (structure)
307 ** 8. Message1 Out - Diag Status Code (????)
308 ** 9. Message0 message code :
310 ** 0x01 : Get Config ->offset 0xa00 :for outbound message code msgcode_rwbuffer (IOP331 send to driver)
311 ** Signature 0x87974060(4)
312 ** Request len 0x00000200(4)
313 ** numbers of queue 0x00000100(4)
314 ** SDRAM Size 0x00000100(4)-->256 MB
315 ** IDE Channels 0x00000008(4)
316 ** vendor 40 bytes char
317 ** model 8 bytes char
318 ** FirmVer 16 bytes char
319 ** Device Map 16 bytes char
321 ** FirmwareVersion DWORD <== Added for checking of new firmware capability
322 ** 0x02 : Set Config ->offset 0xa00 : for inbound message code msgcode_rwbuffer (driver send to IOP331)
323 ** Signature 0x87974063(4)
324 ** UPPER32 of Request Frame (4)-->Driver Only
325 ** 0x03 : Reset (Abort all queued Command)
326 ** 0x04 : Stop Background Activity
327 ** 0x05 : Flush Cache
328 ** 0x06 : Start Background Activity (re-start if background is halted)
329 ** 0x07 : Check If Host Command Pending (Novell May Need This Function)
330 ** 0x08 : Set controller time ->offset 0xa00 : for inbound message code msgcode_rwbuffer (driver to IOP331)
331 ** byte 0 : 0xaa <-- signature
332 ** byte 1 : 0x55 <-- signature
333 ** byte 2 : year (04)
334 ** byte 3 : month (1..12)
335 ** byte 4 : date (1..31)
336 ** byte 5 : hour (0..23)
337 ** byte 6 : minute (0..59)
338 ** byte 7 : second (0..59)
339 ************************************************************************************************
341 /* signature of set and get firmware config */
342 #define ARCMSR_SIGNATURE_GET_CONFIG 0x87974060
343 #define ARCMSR_SIGNATURE_SET_CONFIG 0x87974063
344 /* message code of inbound message register */
345 #define ARCMSR_INBOUND_MESG0_NOP 0x00000000
346 #define ARCMSR_INBOUND_MESG0_GET_CONFIG 0x00000001
347 #define ARCMSR_INBOUND_MESG0_SET_CONFIG 0x00000002
348 #define ARCMSR_INBOUND_MESG0_ABORT_CMD 0x00000003
349 #define ARCMSR_INBOUND_MESG0_STOP_BGRB 0x00000004
350 #define ARCMSR_INBOUND_MESG0_FLUSH_CACHE 0x00000005
351 #define ARCMSR_INBOUND_MESG0_START_BGRB 0x00000006
352 #define ARCMSR_INBOUND_MESG0_CHK331PENDING 0x00000007
353 #define ARCMSR_INBOUND_MESG0_SYNC_TIMER 0x00000008
354 /* doorbell interrupt generator */
355 #define ARCMSR_INBOUND_DRIVER_DATA_WRITE_OK 0x00000001
356 #define ARCMSR_INBOUND_DRIVER_DATA_READ_OK 0x00000002
357 #define ARCMSR_OUTBOUND_IOP331_DATA_WRITE_OK 0x00000001
358 #define ARCMSR_OUTBOUND_IOP331_DATA_READ_OK 0x00000002
359 /* srb areca cdb flag */
360 #define ARCMSR_SRBPOST_FLAG_SGL_BSIZE 0x80000000
361 #define ARCMSR_SRBPOST_FLAG_IAM_BIOS 0x40000000
362 #define ARCMSR_SRBREPLY_FLAG_IAM_BIOS 0x40000000
363 #define ARCMSR_SRBREPLY_FLAG_ERROR 0x10000000
364 /* outbound firmware ok */
365 #define ARCMSR_OUTBOUND_MESG1_FIRMWARE_OK 0x80000000
367 **********************************
369 **********************************
372 struct SG32ENTRY { /* length bit 24 == 0 */
373 u_int32_t length; /* high 8 bit == flag,low 24 bit == length */
377 struct SG64ENTRY { /* length bit 24 == 1 */
378 u_int32_t length; /* high 8 bit == flag,low 24 bit == length */
380 u_int32_t addresshigh;
382 struct SGENTRY_UNION {
384 struct SG32ENTRY sg32entry; /* 30h Scatter gather address */
385 struct SG64ENTRY sg64entry; /* 30h */
389 **********************************
391 **********************************
398 ************************************************************************************************
400 ************************************************************************************************
402 struct FIRMWARE_INFO {
403 u_int32_t signature; /*0,00-03*/
404 u_int32_t request_len; /*1,04-07*/
405 u_int32_t numbers_queue; /*2,08-11*/
406 u_int32_t sdram_size; /*3,12-15*/
407 u_int32_t ide_channels; /*4,16-19*/
408 char vendor[40]; /*5,20-59*/
409 char model[8]; /*15,60-67*/
410 char firmware_ver[16]; /*17,68-83*/
411 char device_map[16]; /*21,84-99*/
414 ************************************************************************************************
416 ************************************************************************************************
419 u_int8_t Bus; /* 00h should be 0 */
420 u_int8_t TargetID; /* 01h should be 0--15 */
421 u_int8_t LUN; /* 02h should be 0--7 */
422 u_int8_t Function; /* 03h should be 1 */
424 u_int8_t CdbLength; /* 04h not used now */
425 u_int8_t sgcount; /* 05h */
426 u_int8_t Flags; /* 06h */
427 #define ARCMSR_CDB_FLAG_SGL_BSIZE 0x01 /* bit 0: 0(256) / 1(512) bytes */
428 #define ARCMSR_CDB_FLAG_BIOS 0x02 /* bit 1: 0(from driver) / 1(from BIOS) */
429 #define ARCMSR_CDB_FLAG_WRITE 0x04 /* bit 2: 0(Data in) / 1(Data out) */
430 #define ARCMSR_CDB_FLAG_SIMPLEQ 0x00 /* bit 4/3 ,00 : simple Q,01 : head of Q,10 : ordered Q */
431 #define ARCMSR_CDB_FLAG_HEADQ 0x08
432 #define ARCMSR_CDB_FLAG_ORDEREDQ 0x10
433 u_int8_t Reserved1; /* 07h */
435 u_int32_t Context; /* 08h Address of this request */
436 u_int32_t DataLength; /* 0ch not used now */
438 u_int8_t Cdb[16]; /* 10h SCSI CDB */
440 ********************************************************
441 **Device Status : the same from SCSI bus if error occur
442 ** SCSI bus status codes.
443 ********************************************************
445 u_int8_t DeviceStatus; /* 20h if error */
446 #define SCSISTAT_GOOD 0x00
447 #define SCSISTAT_CHECK_CONDITION 0x02
448 #define SCSISTAT_CONDITION_MET 0x04
449 #define SCSISTAT_BUSY 0x08
450 #define SCSISTAT_INTERMEDIATE 0x10
451 #define SCSISTAT_INTERMEDIATE_COND_MET 0x14
452 #define SCSISTAT_RESERVATION_CONFLICT 0x18
453 #define SCSISTAT_COMMAND_TERMINATED 0x22
454 #define SCSISTAT_QUEUE_FULL 0x28
455 #define ARCMSR_DEV_SELECT_TIMEOUT 0xF0
456 #define ARCMSR_DEV_ABORTED 0xF1
457 #define ARCMSR_DEV_INIT_FAIL 0xF2
459 u_int8_t SenseData[15]; /* 21h output */
462 struct SG32ENTRY sg32entry[ARCMSR_MAX_SG_ENTRIES]; /* 30h Scatter gather address */
463 struct SG64ENTRY sg64entry[ARCMSR_MAX_SG_ENTRIES]; /* 30h */
467 *********************************************************************
468 ** Command Control Block (SrbExtension)
469 ** SRB must be not cross page boundary,and the order from offset 0
470 ** structure describing an ATA disk request
471 ** this SRB length must be 32 bytes boundary
472 *********************************************************************
474 struct CommandControlBlock {
475 struct ARCMSR_CDB arcmsr_cdb;
476 /* 0-503 (size of CDB=504): arcmsr messenger scsi command descriptor size 504 bytes */
477 u_int32_t cdb_shifted_phyaddr; /* 504-507 */
478 u_int32_t reserved1; /* 508-511*/
479 /* ======================512+32 bytes============================ */
480 #if defined(__x86_64__) || defined(__amd64__) || defined(__ia64__) || defined(__sparc64__) || defined(__powerpc__)
481 union ccb * pccb; /* 512-515 516-519 pointer of freebsd scsi command */
482 struct AdapterControlBlock * acb; /* 520-523 524-527 */
483 bus_dmamap_t dm_segs_dmamap; /* 528-531 532-535 */
484 u_int16_t srb_flags; /* 536-537 */
485 #define SRB_FLAG_READ 0x0000
486 #define SRB_FLAG_WRITE 0x0001
487 #define SRB_FLAG_ERROR 0x0002
488 #define SRB_FLAG_FLUSHCACHE 0x0004
489 #define SRB_FLAG_MASTER_ABORTED 0x0008
490 u_int16_t startdone; /* 538-539 */
491 #define ARCMSR_SRB_DONE 0x0000
492 #define ARCMSR_SRB_START 0x55AA
493 #define ARCMSR_SRB_ABORTED 0xAA55
494 #define ARCMSR_SRB_ILLEGAL 0xFFFF
495 u_int32_t reserved2; /* 540-543 */
497 union ccb * pccb; /* 512-515 pointer of freebsd scsi command */
498 struct AdapterControlBlock * acb; /* 516-519 */
499 bus_dmamap_t dm_segs_dmamap; /* 520-523 */
500 u_int16_t srb_flags; /* 524-525 */
501 #define SRB_FLAG_READ 0x0000
502 #define SRB_FLAG_WRITE 0x0001
503 #define SRB_FLAG_ERROR 0x0002
504 #define SRB_FLAG_FLUSHCACHE 0x0004
505 #define SRB_FLAG_MASTER_ABORTED 0x0008
506 u_int16_t startdone; /* 526-527 */
507 #define ARCMSR_SRB_DONE 0x0000
508 #define ARCMSR_SRB_START 0x55AA
509 #define ARCMSR_SRB_ABORTED 0xAA55
510 #define ARCMSR_SRB_ILLEGAL 0xFFFF
511 u_int32_t reserved2[4]; /* 528-531 532-535 536-539 540-543 */
513 /* ========================================================== */
516 *********************************************************************
517 ** Adapter Control Block
518 *********************************************************************
520 struct AdapterControlBlock {
521 u_int32_t adapter_type; /* adapter A,B..... */
522 #define ACB_ADAPTER_TYPE_A 0x00000001 /* hba I IOP */
523 #define ACB_ADAPTER_TYPE_B 0x00000002 /* hbb M IOP */
524 #define ACB_ADAPTER_TYPE_C 0x00000004 /* hbc P IOP */
525 #define ACB_ADAPTER_TYPE_D 0x00000008 /* hbd A IOP */
527 bus_space_tag_t btag[2];
528 bus_space_handle_t bhandle[2];
529 bus_dma_tag_t parent_dmat;
530 bus_dma_tag_t dm_segs_dmat; /* dmat for buffer I/O */
531 bus_dma_tag_t srb_dmat; /* dmat for freesrb */
532 bus_dmamap_t srb_dmamap;
534 #if __FreeBSD_version < 503000
537 struct cdev * ioctl_dev;
541 struct resource * sys_res_arcmsr[2];
542 struct resource * irqres;
543 void * ih; /* interrupt handle */
545 /* Hooks into the CAM XPT */
546 struct cam_sim *psim;
547 struct cam_path *ppath;
548 u_int8_t * uncacheptr;
549 unsigned long vir2phy_offset;
550 unsigned long srb_phyaddr;
551 /* Offset is used in making arc cdb physical to virtual calculations */
552 u_int32_t outbound_int_enable;
554 struct MessageUnit_UNION * pmu; /* message unit ATU inbound base address0 */
556 u_int8_t adapter_index; /* */
558 u_int16_t acb_flags; /* */
559 #define ACB_F_SCSISTOPADAPTER 0x0001
560 #define ACB_F_MSG_STOP_BGRB 0x0002 /* stop RAID background rebuild */
561 #define ACB_F_MSG_START_BGRB 0x0004 /* stop RAID background rebuild */
562 #define ACB_F_IOPDATA_OVERFLOW 0x0008 /* iop ioctl data rqbuffer overflow */
563 #define ACB_F_MESSAGE_WQBUFFER_CLEARED 0x0010 /* ioctl clear wqbuffer */
564 #define ACB_F_MESSAGE_RQBUFFER_CLEARED 0x0020 /* ioctl clear rqbuffer */
565 #define ACB_F_MESSAGE_WQBUFFER_READ 0x0040
566 #define ACB_F_BUS_RESET 0x0080
567 #define ACB_F_IOP_INITED 0x0100 /* iop init */
568 #define ACB_F_MAPFREESRB_FAILD 0x0200 /* arcmsr_map_freesrb faild */
569 #define ACB_F_CAM_DEV_QFRZN 0x0400
571 struct CommandControlBlock * psrb_pool[ARCMSR_MAX_FREESRB_NUM]; /* serial srb pointer array */
572 struct CommandControlBlock * srbworkingQ[ARCMSR_MAX_FREESRB_NUM]; /* working srb pointer array */
573 int32_t workingsrb_doneindex; /* done srb array index */
574 int32_t workingsrb_startindex; /* start srb array index */
575 int32_t srboutstandingcount;
577 u_int8_t rqbuffer[ARCMSR_MAX_QBUFFER]; /* data collection buffer for read from 80331 */
578 u_int32_t rqbuf_firstindex; /* first of read buffer */
579 u_int32_t rqbuf_lastindex; /* last of read buffer */
581 u_int8_t wqbuffer[ARCMSR_MAX_QBUFFER]; /* data collection buffer for write to 80331 */
582 u_int32_t wqbuf_firstindex; /* first of write buffer */
583 u_int32_t wqbuf_lastindex; /* last of write buffer */
585 arcmsr_lock_t workingQ_done_lock;
586 arcmsr_lock_t workingQ_start_lock;
587 arcmsr_lock_t qbuffer_lock;
589 u_int8_t devstate[ARCMSR_MAX_TARGETID][ARCMSR_MAX_TARGETLUN]; /* id0 ..... id15,lun0...lun7 */
590 #define ARECA_RAID_GONE 0x55
591 #define ARECA_RAID_GOOD 0xaa
592 u_int32_t num_resets;
593 u_int32_t num_aborts;
594 u_int32_t firm_request_len; /*1,04-07*/
595 u_int32_t firm_numbers_queue; /*2,08-11*/
596 u_int32_t firm_sdram_size; /*3,12-15*/
597 u_int32_t firm_ide_channels; /*4,16-19*/
598 char firm_model[12]; /*15,60-67*/
599 char firm_version[20]; /*17,68-83*/
600 };/* HW_DEVICE_EXTENSION */
602 *************************************************************
603 *************************************************************
606 u_int8_t ErrorCode:7;
608 u_int8_t SegmentNumber;
611 u_int8_t IncorrectLength:1;
612 u_int8_t EndOfMedia:1;
614 u_int8_t Information[4];
615 u_int8_t AdditionalSenseLength;
616 u_int8_t CommandSpecificInformation[4];
617 u_int8_t AdditionalSenseCode;
618 u_int8_t AdditionalSenseCodeQualifier;
619 u_int8_t FieldReplaceableUnitCode;
620 u_int8_t SenseKeySpecific[3];
623 **********************************
624 ** Peripheral Device Type definitions
625 **********************************
627 #define SCSI_DASD 0x00 /* Direct-access Device */
628 #define SCSI_SEQACESS 0x01 /* Sequential-access device */
629 #define SCSI_PRINTER 0x02 /* Printer device */
630 #define SCSI_PROCESSOR 0x03 /* Processor device */
631 #define SCSI_WRITEONCE 0x04 /* Write-once device */
632 #define SCSI_CDROM 0x05 /* CD-ROM device */
633 #define SCSI_SCANNER 0x06 /* Scanner device */
634 #define SCSI_OPTICAL 0x07 /* Optical memory device */
635 #define SCSI_MEDCHGR 0x08 /* Medium changer device */
636 #define SCSI_COMM 0x09 /* Communications device */
637 #define SCSI_NODEV 0x1F /* Unknown or no device type */
639 ************************************************************************************************************
640 ** @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
641 ** 80331 PCI-to-PCI Bridge
642 ** PCI Configuration Space
644 ** @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
645 ** Programming Interface
646 ** ========================
647 ** Configuration Register Address Space Groupings and Ranges
648 ** =============================================================
649 ** Register Group Configuration Offset
650 ** -------------------------------------------------------------
651 ** Standard PCI Configuration 00-3Fh
652 ** -------------------------------------------------------------
653 ** Device Specific Registers 40-A7h
654 ** -------------------------------------------------------------
656 ** -------------------------------------------------------------
657 ** Enhanced Capability List CC-FFh
658 ** ==========================================================================================================
659 ** Standard PCI [Type 1] Configuration Space Address Map
660 ** **********************************************************************************************************
661 ** | Byte 3 | Byte 2 | Byte 1 | Byte 0 | Configu-ration Byte Offset
662 ** ----------------------------------------------------------------------------------------------------------
663 ** | Device ID | Vendor ID | 00h
664 ** ----------------------------------------------------------------------------------------------------------
665 ** | Primary Status | Primary Command | 04h
666 ** ----------------------------------------------------------------------------------------------------------
667 ** | Class Code | RevID | 08h
668 ** ----------------------------------------------------------------------------------------------------------
669 ** | reserved | Header Type | Primary MLT | Primary CLS | 0Ch
670 ** ----------------------------------------------------------------------------------------------------------
672 ** ----------------------------------------------------------------------------------------------------------
674 ** ----------------------------------------------------------------------------------------------------------
675 ** | Secondary MLT | Subordinate Bus Number | Secondary Bus Number | Primary Bus Number | 18h
676 ** ----------------------------------------------------------------------------------------------------------
677 ** | Secondary Status | I/O Limit | I/O Base | 1Ch
678 ** ----------------------------------------------------------------------------------------------------------
679 ** | Non-prefetchable Memory Limit Address | Non-prefetchable Memory Base Address | 20h
680 ** ----------------------------------------------------------------------------------------------------------
681 ** | Prefetchable Memory Limit Address | Prefetchable Memory Base Address | 24h
682 ** ----------------------------------------------------------------------------------------------------------
683 ** | Prefetchable Memory Base Address Upper 32 Bits | 28h
684 ** ----------------------------------------------------------------------------------------------------------
685 ** | Prefetchable Memory Limit Address Upper 32 Bits | 2Ch
686 ** ----------------------------------------------------------------------------------------------------------
687 ** | I/O Limit Upper 16 Bits | I/O Base Upper 16 | 30h
688 ** ----------------------------------------------------------------------------------------------------------
689 ** | Reserved | Capabilities Pointer | 34h
690 ** ----------------------------------------------------------------------------------------------------------
692 ** ----------------------------------------------------------------------------------------------------------
693 ** | Bridge Control | Primary Interrupt Pin | Primary Interrupt Line | 3Ch
694 **=============================================================================================================
697 **=============================================================================================================
699 ** Bit Default Description
700 **31:16 0335h Device ID (DID): Indicates the unique device ID that is assigned to bridge by the PCI SIG.
701 ** ID is unique per product speed as indicated.
702 **15:00 8086h Vendor ID (VID): 16-bit field which indicates that Intel is the vendor.
703 **=============================================================================================================
705 #define ARCMSR_PCI2PCI_VENDORID_REG 0x00 /*word*/
706 #define ARCMSR_PCI2PCI_DEVICEID_REG 0x02 /*word*/
708 **==============================================================================
709 ** 0x05-0x04 : command register
710 ** Bit Default Description
712 ** 10 0 Interrupt Disable: Disables/Enables the generation of Interrupts on the primary bus.
713 ** The bridge does not support interrupts.
714 ** 09 0 FB2B Enable: Enables/Disables the generation of fast back to back
715 ** transactions on the primary bus.
716 ** The bridge does not generate fast back to back
717 ** transactions on the primary bus.
718 ** 08 0 SERR# Enable (SEE): Enables primary bus SERR# assertions.
719 ** 0=The bridge does not assert P_SERR#.
720 ** 1=The bridge may assert P_SERR#, subject to other programmable criteria.
721 ** 07 0 Wait Cycle Control (WCC): Always returns 0bzero indicating
722 ** that bridge does not perform address or data stepping,
723 ** 06 0 Parity Error Response (PER): Controls bridge response to a detected primary bus parity error.
724 ** 0=When a data parity error is detected bridge does not assert S_PERR#.
725 ** Also bridge does not assert P_SERR# in response to
726 ** a detected address or attribute parity error.
727 ** 1=When a data parity error is detected bridge asserts S_PERR#.
728 ** The bridge also asserts P_SERR#
729 ** (when enabled globally via bit(8) of this register)
730 ** in response to a detected address or attribute parity error.
731 ** 05 0 VGA Palette Snoop Enable (VGA_PSE): Controls bridge response to VGA-compatible palette write transactions.
732 ** VGA palette write transactions are I/O transactions
733 ** whose address bits are: P_AD[9:0] equal to 3C6h, 3C8h or 3C9h
734 ** P_AD[15:10] are not decoded (i.e. aliases are claimed),
735 ** or are fully decoding
736 ** (i.e., must be all 0's depending upon the VGA
737 ** aliasing bit in the Bridge Control Register, offset 3Eh.
738 ** P_AD[31:16] equal to 0000h
739 ** 0=The bridge ignores VGA palette write transactions,
740 ** unless decoded by the standard I/O address range window.
741 ** 1=The bridge responds to VGA palette write transactions
742 ** with medium DEVSEL# timing and forwards them to the secondary bus.
743 ** 04 0 Memory Write and Invalidate Enable (MWIE): The bridge does not promote MW transactions to MWI transactions.
744 ** MWI transactions targeting resources on the opposite side of the bridge,
745 ** however, are forwarded as MWI transactions.
746 ** 03 0 Special Cycle Enable (SCE): The bridge ignores special cycle transactions.
747 ** This bit is read only and always returns 0 when read
748 ** 02 0 Bus Master Enable (BME): Enables bridge to initiate memory and I/O transactions on the primary interface.
749 ** Initiation of configuration transactions is not affected by the state of this bit.
750 ** 0=The bridge does not initiate memory or I/O transactions on the primary interface.
751 ** 1=The bridge is enabled to function as an initiator on the primary interface.
752 ** 01 0 Memory Space Enable (MSE): Controls target response to memory transactions on the primary interface.
753 ** 0=The bridge target response to memory transactions on the primary interface is disabled.
754 ** 1=The bridge target response to memory transactions on the primary interface is enabled.
755 ** 00 0 I/O Space Enable (IOSE): Controls target response to I/O transactions on the primary interface.
756 ** 0=The bridge target response to I/O transactions on the primary interface is disabled.
757 ** 1=The bridge target response to I/O transactions on the primary interface is enabled.
758 **==============================================================================
760 #define ARCMSR_PCI2PCI_PRIMARY_COMMAND_REG 0x04 /*word*/
761 #define PCI_DISABLE_INTERRUPT 0x0400
763 **==============================================================================
764 ** 0x07-0x06 : status register
765 ** Bit Default Description
766 ** 15 0 Detected Parity Error: The bridge sets this bit to a 1b whenever it detects an address,
767 ** attribute or data parity error.
768 ** This bit is set regardless of the state of the PER bit in the command register.
769 ** 14 0 Signaled System Error: The bridge sets this bit to a 1b whenever it asserts SERR# on the primary bus.
770 ** 13 0 Received Master Abort: The bridge sets this bit to a 1b when,
771 ** acting as the initiator on the primary bus,
772 ** its transaction (with the exception of special cycles)
773 ** has been terminated with a Master Abort.
774 ** 12 0 Received Target Abort: The bridge sets this bit to a 1b when,
775 ** acting as the initiator on the primary bus,
776 ** its transaction has been terminated with a Target Abort.
777 ** 11 0 Signaled Target Abort: The bridge sets this bit to a 1b when it,
778 ** as the target of a transaction, terminates it with a Target Abort.
779 ** In PCI-X mode this bit is also set when it forwards a SCM with a target abort error code.
780 ** 10:09 01 DEVSEL# Timing: Indicates slowest response to a non-configuration command on the primary interface.
781 ** Returns ¡§01b¡¨ when read, indicating that bridge responds no slower than with medium timing.
782 ** 08 0 Master Data Parity Error: The bridge sets this bit to a 1b when all of the following conditions are true:
783 ** The bridge is the current master on the primary bus
784 ** S_PERR# is detected asserted or is asserted by bridge
785 ** The Parity Error Response bit is set in the Command register
786 ** 07 1 Fast Back to Back Capable: Returns a 1b when read indicating that bridge
787 ** is able to respond to fast back to back transactions on its primary interface.
789 ** 05 1 66 MHz Capable Indication: Returns a 1b when read indicating that bridge primary interface is 66 MHz capable.
791 ** 04 1 Capabilities List Enable: Returns 1b when read indicating that bridge supports PCI standard enhanced capabilities.
792 ** Offset 34h (Capability Pointer register)
793 ** provides the offset for the first entry
794 ** in the linked list of enhanced capabilities.
795 ** 03 0 Interrupt Status: Reflects the state of the interrupt in the device/function.
796 ** The bridge does not support interrupts.
797 ** 02:00 000 Reserved
798 **==============================================================================
800 #define ARCMSR_PCI2PCI_PRIMARY_STATUS_REG 0x06 /*word: 06,07 */
801 #define ARCMSR_ADAP_66MHZ 0x20
803 **==============================================================================
804 ** 0x08 : revision ID
805 ** Bit Default Description
806 ** 07:00 00000000 Revision ID (RID): '00h' indicating bridge A-0 stepping.
807 **==============================================================================
809 #define ARCMSR_PCI2PCI_REVISIONID_REG 0x08 /*byte*/
811 **==============================================================================
812 ** 0x0b-0x09 : 0180_00 (class code 1,native pci mode )
813 ** Bit Default Description
814 ** 23:16 06h Base Class Code (BCC): Indicates that this is a bridge device.
815 ** 15:08 04h Sub Class Code (SCC): Indicates this is of type PCI-to-PCI bridge.
816 ** 07:00 00h Programming Interface (PIF): Indicates that this is standard (non-subtractive) PCI-PCI bridge.
817 **==============================================================================
819 #define ARCMSR_PCI2PCI_CLASSCODE_REG 0x09 /*3bytes*/
821 **==============================================================================
822 ** 0x0c : cache line size
823 ** Bit Default Description
824 ** 07:00 00h Cache Line Size (CLS): Designates the cache line size in 32-bit dword units.
825 ** The contents of this register are factored into
826 ** internal policy decisions associated with memory read prefetching,
827 ** and the promotion of Memory Write transactions to MWI transactions.
828 ** Valid cache line sizes are 8 and 16 dwords.
829 ** When the cache line size is set to an invalid value,
830 ** bridge behaves as though the cache line size was set to 00h.
831 **==============================================================================
833 #define ARCMSR_PCI2PCI_PRIMARY_CACHELINESIZE_REG 0x0C /*byte*/
835 **==============================================================================
836 ** 0x0d : latency timer (number of pci clock 00-ff )
837 ** Bit Default Description
838 ** Primary Latency Timer (PTV):
839 ** 07:00 00h (Conventional PCI) Conventional PCI Mode: Primary bus Master latency timer. Indicates the number of PCI clock cycles,
840 ** referenced from the assertion of FRAME# to the expiration of the timer,
841 ** when bridge may continue as master of the current transaction. All bits are writable,
842 ** resulting in a granularity of 1 PCI clock cycle.
843 ** When the timer expires (i.e., equals 00h)
844 ** bridge relinquishes the bus after the first data transfer
845 ** when its PCI bus grant has been deasserted.
846 ** or 40h (PCI-X) PCI-X Mode: Primary bus Master latency timer.
847 ** Indicates the number of PCI clock cycles,
848 ** referenced from the assertion of FRAME# to the expiration of the timer,
849 ** when bridge may continue as master of the current transaction.
850 ** All bits are writable, resulting in a granularity of 1 PCI clock cycle.
851 ** When the timer expires (i.e., equals 00h) bridge relinquishes the bus at the next ADB.
852 ** (Except in the case where MLT expires within 3 data phases
853 ** of an ADB.In this case bridge continues on
854 ** until it reaches the next ADB before relinquishing the bus.)
855 **==============================================================================
857 #define ARCMSR_PCI2PCI_PRIMARY_LATENCYTIMER_REG 0x0D /*byte*/
859 **==============================================================================
860 ** 0x0e : (header type,single function )
861 ** Bit Default Description
862 ** 07 0 Multi-function device (MVD): 80331 is a single-function device.
863 ** 06:00 01h Header Type (HTYPE): Defines the layout of addresses 10h through 3Fh in configuration space.
864 ** Returns ¡§01h¡¨ when read indicating
865 ** that the register layout conforms to the standard PCI-to-PCI bridge layout.
866 **==============================================================================
868 #define ARCMSR_PCI2PCI_HEADERTYPE_REG 0x0E /*byte*/
870 **==============================================================================
872 **==============================================================================
875 **==============================================================================
877 ** PCI CFG Base Address #0 (0x10)
878 **==============================================================================
881 **==============================================================================
883 ** PCI CFG Base Address #1 (0x14)
884 **==============================================================================
887 **==============================================================================
889 ** PCI CFG Base Address #2 (0x18)
890 **-----------------0x1A,0x19,0x18--Bus Number Register - BNR
891 ** Bit Default Description
892 ** 23:16 00h Subordinate Bus Number (SBBN): Indicates the highest PCI bus number below this bridge.
893 ** Any Type 1 configuration cycle
894 ** on the primary bus whose bus number is greater than the secondary bus number,
895 ** and less than or equal to the subordinate bus number
896 ** is forwarded unaltered as a Type 1 configuration cycle on the secondary PCI bus.
897 ** 15:08 00h Secondary Bus Number (SCBN): Indicates the bus number of PCI to which the secondary interface is connected.
898 ** Any Type 1 configuration cycle matching this bus number
899 ** is translated to a Type 0 configuration cycle (or a Special Cycle)
900 ** before being executed on bridge's secondary PCI bus.
901 ** 07:00 00h Primary Bus Number (PBN): Indicates bridge primary bus number.
902 ** Any Type 1 configuration cycle on the primary interface
903 ** with a bus number that is less than the contents
904 ** of this register field does not be claimed by bridge.
905 **-----------------0x1B--Secondary Latency Timer Register - SLTR
906 ** Bit Default Description
907 ** Secondary Latency Timer (STV):
908 ** 07:00 00h (Conventional PCI) Conventional PCI Mode: Secondary bus Master latency timer.
909 ** Indicates the number of PCI clock cycles,
910 ** referenced from the assertion of FRAME# to the expiration of the timer,
911 ** when bridge may continue as master of the current transaction. All bits are writable,
912 ** resulting in a granularity of 1 PCI clock cycle.
913 ** When the timer expires (i.e., equals 00h)
914 ** bridge relinquishes the bus after the first data transfer
915 ** when its PCI bus grant has been deasserted.
916 ** or 40h (PCI-X) PCI-X Mode: Secondary bus Master latency timer.
917 ** Indicates the number of PCI clock cycles,referenced from the assertion of FRAME#
918 ** to the expiration of the timer,
919 ** when bridge may continue as master of the current transaction. All bits are writable,
920 ** resulting in a granularity of 1 PCI clock cycle.
921 ** When the timer expires (i.e., equals 00h) bridge relinquishes the bus at the next ADB.
922 ** (Except in the case where MLT expires within 3 data phases of an ADB.
923 ** In this case bridge continues on until it reaches the next ADB
924 ** before relinquishing the bus)
925 **==============================================================================
927 #define ARCMSR_PCI2PCI_PRIMARY_BUSNUMBER_REG 0x18 /*3byte 0x1A,0x19,0x18*/
928 #define ARCMSR_PCI2PCI_SECONDARY_BUSNUMBER_REG 0x19 /*byte*/
929 #define ARCMSR_PCI2PCI_SUBORDINATE_BUSNUMBER_REG 0x1A /*byte*/
930 #define ARCMSR_PCI2PCI_SECONDARY_LATENCYTIMER_REG 0x1B /*byte*/
932 **==============================================================================
934 ** PCI CFG Base Address #3 (0x1C)
935 **-----------------0x1D,0x1C--I/O Base and Limit Register - IOBL
936 ** Bit Default Description
937 ** 15:12 0h I/O Limit Address Bits [15:12]: Defines the top address of an address range to
938 ** determine when to forward I/O transactions from one interface to the other.
939 ** These bits correspond to address lines 15:12 for 4KB alignment.
940 ** Bits 11:0 are assumed to be FFFh.
941 ** 11:08 1h I/O Limit Addressing Capability: This field is hard-wired to 1h, indicating support 32-bit I/O addressing.
942 ** 07:04 0h I/O Base Address Bits [15:12]: Defines the bottom address of
943 ** an address range to determine when to forward I/O transactions
944 ** from one interface to the other.
945 ** These bits correspond to address lines 15:12 for 4KB alignment.
946 ** Bits 11:0 are assumed to be 000h.
947 ** 03:00 1h I/O Base Addressing Capability: This is hard-wired to 1h, indicating support for 32-bit I/O addressing.
948 **-----------------0x1F,0x1E--Secondary Status Register - SSR
949 ** Bit Default Description
950 ** 15 0b Detected Parity Error: The bridge sets this bit to a 1b whenever it detects an address,
951 ** attribute or data parity error on its secondary interface.
952 ** 14 0b Received System Error: The bridge sets this bit when it samples SERR# asserted on its secondary bus interface.
953 ** 13 0b Received Master Abort: The bridge sets this bit to a 1b when,
954 ** acting as the initiator on the secondary bus,
955 ** it's transaction (with the exception of special cycles)
956 ** has been terminated with a Master Abort.
957 ** 12 0b Received Target Abort: The bridge sets this bit to a 1b when,
958 ** acting as the initiator on the secondary bus,
959 ** it's transaction has been terminated with a Target Abort.
960 ** 11 0b Signaled Target Abort: The bridge sets this bit to a 1b when it,
961 ** as the target of a transaction, terminates it with a Target Abort.
962 ** In PCI-X mode this bit is also set when it forwards a SCM with a target abort error code.
963 ** 10:09 01b DEVSEL# Timing: Indicates slowest response to a non-configuration command on the secondary interface.
964 ** Returns ¡§01b¡¨ when read, indicating that bridge responds no slower than with medium timing.
965 ** 08 0b Master Data Parity Error: The bridge sets this bit to a 1b when all of the following conditions are true:
966 ** The bridge is the current master on the secondary bus
967 ** S_PERR# is detected asserted or is asserted by bridge
968 ** The Parity Error Response bit is set in the Command register
969 ** 07 1b Fast Back-to-Back Capable (FBC): Indicates that the secondary interface of bridge can receive fast back-to-back cycles.
971 ** 05 1b 66 MHz Capable (C66): Indicates the secondary interface of the bridge is 66 MHz capable.
973 ** 04:00 00h Reserved
974 **==============================================================================
976 #define ARCMSR_PCI2PCI_IO_BASE_REG 0x1C /*byte*/
977 #define ARCMSR_PCI2PCI_IO_LIMIT_REG 0x1D /*byte*/
978 #define ARCMSR_PCI2PCI_SECONDARY_STATUS_REG 0x1E /*word: 0x1F,0x1E */
980 **==============================================================================
982 ** PCI CFG Base Address #4 (0x20)
983 **-----------------0x23,0x22,0x21,0x20--Memory Base and Limit Register - MBL
984 ** Bit Default Description
985 ** 31:20 000h Memory Limit: These 12 bits are compared with P_AD[31:20] of the incoming address to determine
986 ** the upper 1MB aligned value (exclusive) of the range.
987 ** The incoming address must be less than or equal to this value.
988 ** For the purposes of address decoding the lower 20 address bits (P_AD[19:0]
989 ** are assumed to be F FFFFh.
990 ** 19:16 0h Reserved.
991 ** 15:04 000h Memory Base: These 12 bits are compared with bits P_AD[31:20]
992 ** of the incoming address to determine the lower 1MB
993 ** aligned value (inclusive) of the range.
994 ** The incoming address must be greater than or equal to this value.
995 ** For the purposes of address decoding the lower 20 address bits (P_AD[19:0])
996 ** are assumed to be 0 0000h.
997 ** 03:00 0h Reserved.
998 **==============================================================================
1000 #define ARCMSR_PCI2PCI_NONPREFETCHABLE_MEMORY_BASE_REG 0x20 /*word: 0x21,0x20 */
1001 #define ARCMSR_PCI2PCI_NONPREFETCHABLE_MEMORY_LIMIT_REG 0x22 /*word: 0x23,0x22 */
1003 **==============================================================================
1005 ** PCI CFG Base Address #5 (0x24)
1006 **-----------------0x27,0x26,0x25,0x24--Prefetchable Memory Base and Limit Register - PMBL
1007 ** Bit Default Description
1008 ** 31:20 000h Prefetchable Memory Limit: These 12 bits are compared with P_AD[31:20] of the incoming address to determine
1009 ** the upper 1MB aligned value (exclusive) of the range.
1010 ** The incoming address must be less than or equal to this value.
1011 ** For the purposes of address decoding the lower 20 address bits (P_AD[19:0]
1012 ** are assumed to be F FFFFh.
1013 ** 19:16 1h 64-bit Indicator: Indicates that 64-bit addressing is supported.
1014 ** 15:04 000h Prefetchable Memory Base: These 12 bits are compared with bits P_AD[31:20]
1015 ** of the incoming address to determine the lower 1MB aligned value (inclusive)
1017 ** The incoming address must be greater than or equal to this value.
1018 ** For the purposes of address decoding the lower 20 address bits (P_AD[19:0])
1019 ** are assumed to be 0 0000h.
1020 ** 03:00 1h 64-bit Indicator: Indicates that 64-bit addressing is supported.
1021 **==============================================================================
1023 #define ARCMSR_PCI2PCI_PREFETCHABLE_MEMORY_BASE_REG 0x24 /*word: 0x25,0x24 */
1024 #define ARCMSR_PCI2PCI_PREFETCHABLE_MEMORY_LIMIT_REG 0x26 /*word: 0x27,0x26 */
1026 **==============================================================================
1028 ** Bit Default Description
1029 ** 31:00 00000000h Prefetchable Memory Base Upper Portion: All bits are read/writable
1030 ** bridge supports full 64-bit addressing.
1031 **==============================================================================
1033 #define ARCMSR_PCI2PCI_PREFETCHABLE_MEMORY_BASE_UPPER32_REG 0x28 /*dword: 0x2b,0x2a,0x29,0x28 */
1035 **==============================================================================
1037 ** Bit Default Description
1038 ** 31:00 00000000h Prefetchable Memory Limit Upper Portion: All bits are read/writable
1039 ** bridge supports full 64-bit addressing.
1040 **==============================================================================
1042 #define ARCMSR_PCI2PCI_PREFETCHABLE_MEMORY_LIMIT_UPPER32_REG 0x2C /*dword: 0x2f,0x2e,0x2d,0x2c */
1044 **==============================================================================
1046 ** Bit Default Description
1047 ** 07:00 DCh Capabilities Pointer: Pointer to the first CAP ID entry in the capabilities list is at DCh in PCI configuration
1048 ** space. (Power Management Capability Registers)
1049 **==============================================================================
1051 #define ARCMSR_PCI2PCI_CAPABILITIES_POINTER_REG 0x34 /*byte*/
1053 **==============================================================================
1054 ** 0x3b-0x35 : reserved
1055 **==============================================================================
1058 **==============================================================================
1061 ** Bit Default Description
1062 ** 15:08 00h Interrupt Pin (PIN): Bridges do not support the generation of interrupts.
1063 ** 07:00 00h Interrupt Line (LINE): The bridge does not generate interrupts, so this is reserved as '00h'.
1064 **==============================================================================
1066 #define ARCMSR_PCI2PCI_PRIMARY_INTERRUPT_LINE_REG 0x3C /*byte*/
1067 #define ARCMSR_PCI2PCI_PRIMARY_INTERRUPT_PIN_REG 0x3D /*byte*/
1069 **==============================================================================
1071 ** Bit Default Description
1072 ** 15:12 0h Reserved
1073 ** 11 0b Discard Timer SERR# Enable: Controls the generation of SERR# on the primary interface (P_SERR#) in response
1074 ** to a timer discard on either the primary or secondary interface.
1075 ** 0b=SERR# is not asserted.
1076 ** 1b=SERR# is asserted.
1077 ** 10 0b Discard Timer Status (DTS): This bit is set to a '1b' when either the primary or secondary discard timer expires.
1078 ** The delayed completion is then discarded.
1079 ** 09 0b Secondary Discard Timer (SDT): Sets the maximum number of PCI clock cycles
1080 ** that bridge waits for an initiator on the secondary bus
1081 ** to repeat a delayed transaction request.
1082 ** The counter starts when the delayed transaction completion is ready
1083 ** to be returned to the initiator.
1084 ** When the initiator has not repeated the transaction
1085 ** at least once before the counter expires,bridge
1086 ** discards the delayed transaction from its queues.
1087 ** 0b=The secondary master time-out counter is 2 15 PCI clock cycles.
1088 ** 1b=The secondary master time-out counter is 2 10 PCI clock cycles.
1089 ** 08 0b Primary Discard Timer (PDT): Sets the maximum number of PCI clock cycles
1090 ** that bridge waits for an initiator on the primary bus
1091 ** to repeat a delayed transaction request.
1092 ** The counter starts when the delayed transaction completion
1093 ** is ready to be returned to the initiator.
1094 ** When the initiator has not repeated the transaction
1095 ** at least once before the counter expires,
1096 ** bridge discards the delayed transaction from its queues.
1097 ** 0b=The primary master time-out counter is 2 15 PCI clock cycles.
1098 ** 1b=The primary master time-out counter is 2 10 PCI clock cycles.
1099 ** 07 0b Fast Back-to-Back Enable (FBE): The bridge does not initiate back to back transactions.
1100 ** 06 0b Secondary Bus Reset (SBR):
1101 ** When cleared to 0b: The bridge deasserts S_RST#,
1102 ** when it had been asserted by writing this bit to a 1b.
1103 ** When set to 1b: The bridge asserts S_RST#.
1104 ** 05 0b Master Abort Mode (MAM): Dictates bridge behavior on the initiator bus
1105 ** when a master abort termination occurs in response to
1106 ** a delayed transaction initiated by bridge on the target bus.
1107 ** 0b=The bridge asserts TRDY# in response to a non-locked delayed transaction,
1108 ** and returns FFFF FFFFh when a read.
1109 ** 1b=When the transaction had not yet been completed on the initiator bus
1110 ** (e.g.,delayed reads, or non-posted writes),
1111 ** then bridge returns a Target Abort in response to the original requester
1112 ** when it returns looking for its delayed completion on the initiator bus.
1113 ** When the transaction had completed on the initiator bus (e.g., a PMW),
1114 ** then bridge asserts P_SERR# (when enabled).
1115 ** For PCI-X transactions this bit is an enable for the assertion of P_SERR# due to a master abort
1116 ** while attempting to deliver a posted memory write on the destination bus.
1117 ** 04 0b VGA Alias Filter Enable: This bit dictates bridge behavior in conjunction with the VGA enable bit
1118 ** (also of this register),
1119 ** and the VGA Palette Snoop Enable bit (Command Register).
1120 ** When the VGA enable, or VGA Palette Snoop enable bits are on (i.e., 1b)
1121 ** the VGA Aliasing bit for the corresponding enabled functionality,:
1122 ** 0b=Ignores address bits AD[15:10] when decoding VGA I/O addresses.
1123 ** 1b=Ensures that address bits AD[15:10] equal 000000b when decoding VGA I/O addresses.
1124 ** When all VGA cycle forwarding is disabled, (i.e., VGA Enable bit =0b and VGA Palette Snoop bit =0b),
1125 ** then this bit has no impact on bridge behavior.
1126 ** 03 0b VGA Enable: Setting this bit enables address decoding
1127 ** and transaction forwarding of the following VGA transactions from the primary bus
1128 ** to the secondary bus:
1129 ** frame buffer memory addresses 000A0000h:000BFFFFh,
1130 ** VGA I/O addresses 3B0:3BBh and 3C0h:3DFh, where AD[31:16]=¡§0000h?** ?and AD[15:10] are either not decoded (i.e., don't cares),
1131 ** or must be ¡§000000b¡¨
1132 ** depending upon the state of the VGA Alias Filter Enable bit. (bit(4) of this register)
1133 ** I/O and Memory Enable bits must be set in the Command register
1134 ** to enable forwarding of VGA cycles.
1135 ** 02 0b ISA Enable: Setting this bit enables special handling
1136 ** for the forwarding of ISA I/O transactions that fall within the address range
1137 ** specified by the I/O Base and Limit registers,
1138 ** and are within the lowest 64Kbyte of the I/O address map
1139 ** (i.e., 0000 0000h - 0000 FFFFh).
1140 ** 0b=All I/O transactions that fall within the I/O Base
1141 ** and Limit registers' specified range are forwarded
1142 ** from primary to secondary unfiltered.
1143 ** 1b=Blocks the forwarding from primary to secondary
1144 ** of the top 768 bytes of each 1Kbyte alias.
1145 ** On the secondary the top 768 bytes of each 1K alias
1146 ** are inversely decoded and forwarded
1147 ** from secondary to primary.
1148 ** 01 0b SERR# Forward Enable: 0b=The bridge does not assert P_SERR# as a result of an S_SERR# assertion.
1149 ** 1b=The bridge asserts P_SERR# whenever S_SERR# is detected
1150 ** asserted provided the SERR# Enable bit is set (PCI Command Register bit(8)=1b).
1151 ** 00 0b Parity Error Response: This bit controls bridge response to a parity error
1152 ** that is detected on its secondary interface.
1153 ** 0b=When a data parity error is detected bridge does not assert S_PERR#.
1154 ** Also bridge does not assert P_SERR# in response to a detected address
1155 ** or attribute parity error.
1156 ** 1b=When a data parity error is detected bridge asserts S_PERR#.
1157 ** The bridge also asserts P_SERR# (when enabled globally via bit(8)
1158 ** of the Command register)
1159 ** in response to a detected address or attribute parity error.
1160 **==============================================================================
1162 #define ARCMSR_PCI2PCI_BRIDGE_CONTROL_REG 0x3E /*word*/
1164 **************************************************************************
1165 ** Device Specific Registers 40-A7h
1166 **************************************************************************
1167 ** ----------------------------------------------------------------------------------------------------------
1168 ** | Byte 3 | Byte 2 | Byte 1 | Byte 0 | Configu-ration Byte Offset
1169 ** ----------------------------------------------------------------------------------------------------------
1170 ** | Bridge Control 0 | Arbiter Control/Status | Reserved | 40h
1171 ** ----------------------------------------------------------------------------------------------------------
1172 ** | Bridge Control 2 | Bridge Control 1 | 44h
1173 ** ----------------------------------------------------------------------------------------------------------
1174 ** | Reserved | Bridge Status | 48h
1175 ** ----------------------------------------------------------------------------------------------------------
1177 ** ----------------------------------------------------------------------------------------------------------
1178 ** | Prefetch Policy | Multi-Transaction Timer | 50h
1179 ** ----------------------------------------------------------------------------------------------------------
1180 ** | Reserved | Pre-boot Status | P_SERR# Assertion Control | 54h
1181 ** ----------------------------------------------------------------------------------------------------------
1182 ** | Reserved | Reserved | Secondary Decode Enable | 58h
1183 ** ----------------------------------------------------------------------------------------------------------
1184 ** | Reserved | Secondary IDSEL | 5Ch
1185 ** ----------------------------------------------------------------------------------------------------------
1187 ** ----------------------------------------------------------------------------------------------------------
1188 ** | Reserved | 68h:CBh
1189 ** ----------------------------------------------------------------------------------------------------------
1190 **************************************************************************
1191 **==============================================================================
1192 ** 0x42-0x41: Secondary Arbiter Control/Status Register - SACSR
1193 ** Bit Default Description
1194 ** 15:12 1111b Grant Time-out Violator: This field indicates the agent that violated the Grant Time-out rule
1195 ** (PCI=16 clocks,PCI-X=6 clocks).
1196 ** Note that this field is only meaningful when:
1197 ** # Bit[11] of this register is set to 1b,
1198 ** indicating that a Grant Time-out violation had occurred.
1199 ** # bridge internal arbiter is enabled.
1200 ** Bits[15:12] Violating Agent (REQ#/GNT# pair number)
1201 ** 0000b REQ#/GNT#[0]
1202 ** 0001b REQ#/GNT#[1]
1203 ** 0010b REQ#/GNT#[2]
1204 ** 0011b REQ#/GNT#[3]
1205 ** 1111b Default Value (no violation detected)
1206 ** When bit[11] is cleared by software, this field reverts back to its default value.
1207 ** All other values are Reserved
1208 ** 11 0b Grant Time-out Occurred: When set to 1b,
1209 ** this indicates that a Grant Time-out error had occurred involving one of the secondary bus agents.
1210 ** Software clears this bit by writing a 1b to it.
1211 ** 10 0b Bus Parking Control: 0=During bus idle, bridge parks the bus on the last master to use the bus.
1212 ** 1=During bus idle, bridge parks the bus on itself.
1213 ** The bus grant is removed from the last master and internally asserted to bridge.
1214 ** 09:08 00b Reserved
1215 ** 07:00 0000 0000b Secondary Bus Arbiter Priority Configuration: The bridge secondary arbiter provides two rings of arbitration priority.
1216 ** Each bit of this field assigns its corresponding secondary
1217 ** bus master to either the high priority arbiter ring (1b)
1218 ** or to the low priority arbiter ring (0b).
1219 ** Bits [3:0] correspond to request inputs S_REQ#[3:0], respectively.
1220 ** Bit [6] corresponds to the bridge internal secondary bus request
1221 ** while Bit [7] corresponds to the SATU secondary bus request.
1222 ** Bits [5:4] are unused.
1223 ** 0b=Indicates that the master belongs to the low priority group.
1224 ** 1b=Indicates that the master belongs to the high priority group
1225 **=================================================================================
1226 ** 0x43: Bridge Control Register 0 - BCR0
1227 ** Bit Default Description
1228 ** 07 0b Fully Dynamic Queue Mode: 0=The number of Posted write transactions is limited to eight
1229 ** and the Posted Write data is limited to 4KB.
1230 ** 1=Operation in fully dynamic queue mode. The bridge enqueues up to
1231 ** 14 Posted Memory Write transactions and 8KB of posted write data.
1232 ** 06:03 0H Reserved.
1233 ** 02 0b Upstream Prefetch Disable: This bit disables bridge ability
1234 ** to perform upstream prefetch operations for Memory
1235 ** Read requests received on its secondary interface.
1236 ** This bit also controls the bridge's ability to generate advanced read commands
1237 ** when forwarding a Memory Read Block transaction request upstream from a PCI-X bus
1238 ** to a Conventional PCI bus.
1239 ** 0b=bridge treats all upstream Memory Read requests as though they target prefetchable memory.
1240 ** The use of Memory Read Line and Memory Read
1241 ** Multiple is enabled when forwarding a PCI-X Memory Read Block request
1242 ** to an upstream bus operating in Conventional PCI mode.
1243 ** 1b=bridge treats upstream PCI Memory Read requests as though
1244 ** they target non-prefetchable memory and forwards upstream PCI-X Memory
1245 ** Read Block commands as Memory Read
1246 ** when the primary bus is operating
1247 ** in Conventional PCI mode.
1248 ** NOTE: This bit does not affect bridge ability to perform read prefetching
1249 ** when the received command is Memory Read Line or Memory Read Multiple.
1250 **=================================================================================
1251 ** 0x45-0x44: Bridge Control Register 1 - BCR1 (Sheet 2 of 2)
1252 ** Bit Default Description
1253 ** 15:08 0000000b Reserved
1254 ** 07:06 00b Alias Command Mapping: This two bit field determines how bridge handles PCI-X ¡§Alias¡¨ commands,
1255 ** specifically the Alias to Memory Read Block and Alias to Memory Write Block commands.
1256 ** The three options for handling these alias commands are to either pass it as is,
1257 ** re-map to the actual block memory read/write command encoding, or ignore
1258 ** the transaction forcing a Master Abort to occur on the Origination Bus.
1259 ** Bit (7:6) Handling of command
1260 ** 0 0 Re-map to Memory Read/Write Block before forwarding
1261 ** 0 1 Enqueue and forward the alias command code unaltered
1262 ** 1 0 Ignore the transaction, forcing Master Abort
1264 ** 05 1b Watchdog Timers Disable: Disables or enables all 2 24 Watchdog Timers in both directions.
1265 ** The watchdog timers are used to detect prohibitively long latencies in the system.
1266 ** The watchdog timer expires when any Posted Memory Write (PMW), Delayed Request,
1267 ** or Split Requests (PCI-X mode) is not completed within 2 24 events
1268 ** (¡§events¡¨ are defined as PCI Clocks when operating in PCI-X mode,
1269 ** and as the number of times being retried when operating in Conventional PCI mode)
1270 ** 0b=All 2 24 watchdog timers are enabled.
1271 ** 1b=All 2 24 watchdog timers are disabled and there is no limits to
1272 ** the number of attempts bridge makes when initiating a PMW,
1273 ** transacting a Delayed Transaction, or how long it waits for
1274 ** a split completion corresponding to one of its requests.
1275 ** 04 0b GRANT# time-out disable: This bit enables/disables the GNT# time-out mechanism.
1276 ** Grant time-out is 16 clocks for conventional PCI, and 6 clocks for PCI-X.
1277 ** 0b=The Secondary bus arbiter times out an agent
1278 ** that does not assert FRAME# within 16/6 clocks of receiving its grant,
1279 ** once the bus has gone idle.
1280 ** The time-out counter begins as soon as the bus goes idle with the new GNT# asserted.
1281 ** An infringing agent does not receive a subsequent GNT#
1282 ** until it de-asserts its REQ# for at least one clock cycle.
1283 ** 1b=GNT# time-out mechanism is disabled.
1285 ** 02 0b Secondary Discard Timer Disable: This bit enables/disables bridge secondary delayed transaction discard mechanism.
1286 ** The time out mechanism is used to ensure that initiators
1287 ** of delayed transactions return for their delayed completion data/status
1288 ** within a reasonable amount of time after it is available from bridge.
1289 ** 0b=The secondary master time-out counter is enabled
1290 ** and uses the value specified by the Secondary Discard Timer bit
1291 ** (see Bridge Control Register).
1292 ** 1b=The secondary master time-out counter is disabled.
1293 ** The bridge waits indefinitely for a secondary bus master
1294 ** to repeat a delayed transaction.
1295 ** 01 0b Primary Discard Timer Disable: This bit enables/disables bridge primary delayed transaction discard mechanism.
1296 ** The time out mechanism is used to ensure that initiators
1297 ** of delayed transactions return for their delayed completion data/status
1298 ** within a reasonable amount of time after it is available from bridge.
1299 ** 0b=The primary master time-out counter is enabled and uses the value specified
1300 ** by the Primary Discard Timer bit (see Bridge Control Register).
1301 ** 1b=The secondary master time-out counter is disabled.
1302 ** The bridge waits indefinitely for a secondary bus master
1303 ** to repeat a delayed transaction.
1305 **=================================================================================
1306 ** 0x47-0x46: Bridge Control Register 2 - BCR2
1307 ** Bit Default Description
1308 ** 15:07 0000b Reserved.
1309 ** 06 0b Global Clock Out Disable (External Secondary Bus Clock Source Enable):
1310 ** This bit disables all of the secondary PCI clock outputs including
1311 ** the feedback clock S_CLKOUT.
1312 ** This means that the user is required to provide an S_CLKIN input source.
1313 ** 05:04 11 (66 MHz) Preserved.
1316 ** 03:00 Fh (100 MHz & 66 MHz)
1318 ** This 4 bit field provides individual enable/disable mask bits for each of bridge
1319 ** secondary PCI clock outputs. Some, or all secondary clock outputs (S_CLKO[3:0])
1320 ** default to being enabled following the rising edge of P_RST#, depending on the
1321 ** frequency of the secondary bus clock:
1322 ** ¡E Designs with 100 MHz (or lower) Secondary PCI clock power up with
1323 ** all four S_CLKOs enabled by default. (SCLKO[3:0])¡P
1324 ** ¡E Designs with 133 MHz Secondary PCI clock power up
1325 ** with the lower order 3 S_CLKOs enabled by default.
1326 ** (S_CLKO[2:0]) Only those SCLKs that power up enabled by can be connected
1327 ** to downstream device clock inputs.
1328 **=================================================================================
1329 ** 0x49-0x48: Bridge Status Register - BSR
1330 ** Bit Default Description
1331 ** 15 0b Upstream Delayed Transaction Discard Timer Expired: This bit is set to a 1b and P_SERR#
1332 ** is conditionally asserted when the secondary discard timer expires.
1333 ** 14 0b Upstream Delayed/Split Read Watchdog Timer Expired:
1334 ** Conventional PCI Mode: This bit is set to a 1b and P_SERR#
1335 ** is conditionally asserted when bridge discards an upstream delayed read ** ** transaction request after 2 24 retries following the initial retry.
1336 ** PCI-X Mode: This bit is set to a 1b and P_SERR# is conditionally asserted
1337 ** when bridge discards an upstream split read request
1338 ** after waiting in excess of 2 24 clocks for the corresponding
1339 ** Split Completion to arrive.
1340 ** 13 0b Upstream Delayed/Split Write Watchdog Timer Expired:
1341 ** Conventional PCI Mode: This bit is set to a 1b and P_SERR#
1342 ** is conditionally asserted when bridge discards an upstream delayed write ** ** transaction request after 2 24 retries following the initial retry.
1343 ** PCI-X Mode: This bit is set to a 1b and P_SERR#
1344 ** is conditionally asserted when bridge discards an upstream split write request ** after waiting in excess of 2 24 clocks for the corresponding
1345 ** Split Completion to arrive.
1346 ** 12 0b Master Abort during Upstream Posted Write: This bit is set to a 1b and P_SERR#
1347 ** is conditionally asserted when a Master Abort occurs as a result of an attempt,
1348 ** by bridge, to retire a PMW upstream.
1349 ** 11 0b Target Abort during Upstream Posted Write: This bit is set to a 1b and P_SERR#
1350 ** is conditionally asserted when a Target Abort occurs as a result of an attempt,
1351 ** by bridge, to retire a PMW upstream.
1352 ** 10 0b Upstream Posted Write Data Discarded: This bit is set to a 1b and P_SERR#
1353 ** is conditionally asserted when bridge discards an upstream PMW transaction
1354 ** after receiving 2 24 target retries from the primary bus target
1355 ** 09 0b Upstream Posted Write Data Parity Error: This bit is set to a 1b and P_SERR#
1356 ** is conditionally asserted when a data parity error is detected by bridge
1357 ** while attempting to retire a PMW upstream
1358 ** 08 0b Secondary Bus Address Parity Error: This bit is set to a 1b and P_SERR#
1359 ** is conditionally asserted when bridge detects an address parity error on
1360 ** the secondary bus.
1361 ** 07 0b Downstream Delayed Transaction Discard Timer Expired: This bit is set to a 1b and P_SERR#
1362 ** is conditionally asserted when the primary bus discard timer expires.
1363 ** 06 0b Downstream Delayed/Split Read Watchdog Timer Expired:
1364 ** Conventional PCI Mode: This bit is set to a 1b and P_SERR#
1365 ** is conditionally asserted when bridge discards a downstream delayed read ** ** transaction request after receiving 2 24 target retries
1366 ** from the secondary bus target.
1367 ** PCI-X Mode: This bit is set to a 1b and P_SERR# is conditionally asserted
1368 ** when bridge discards a downstream split read request
1369 ** after waiting in excess of 2 24 clocks for the corresponding
1370 ** Split Completion to arrive.
1371 ** 05 0b Downstream Delayed Write/Split Watchdog Timer Expired:
1372 ** Conventional PCI Mode: This bit is set to a 1b and P_SERR# is conditionally asserted
1373 ** when bridge discards a downstream delayed write transaction request
1374 ** after receiving 2 24 target retries from the secondary bus target.
1375 ** PCI-X Mode: This bit is set to a 1b and P_SERR#
1376 ** is conditionally asserted when bridge discards a downstream
1377 ** split write request after waiting in excess of 2 24 clocks
1378 ** for the corresponding Split Completion to arrive.
1379 ** 04 0b Master Abort during Downstream Posted Write: This bit is set to a 1b and P_SERR#
1380 ** is conditionally asserted when a Master Abort occurs as a result of an attempt,
1381 ** by bridge, to retire a PMW downstream.
1382 ** 03 0b Target Abort during Downstream Posted Write: This bit is set to a 1b and P_SERR# is conditionally asserted
1383 ** when a Target Abort occurs as a result of an attempt, by bridge,
1384 ** to retire a PMW downstream.
1385 ** 02 0b Downstream Posted Write Data Discarded: This bit is set to a 1b and P_SERR#
1386 ** is conditionally asserted when bridge discards a downstream PMW transaction
1387 ** after receiving 2 24 target retries from the secondary bus target
1388 ** 01 0b Downstream Posted Write Data Parity Error: This bit is set to a 1b and P_SERR#
1389 ** is conditionally asserted when a data parity error is detected by bridge
1390 ** while attempting to retire a PMW downstream.
1391 ** 00 0b Primary Bus Address Parity Error: This bit is set to a 1b and P_SERR# is conditionally asserted
1392 ** when bridge detects an address parity error on the primary bus.
1393 **==================================================================================
1394 ** 0x51-0x50: Bridge Multi-Transaction Timer Register - BMTTR
1395 ** Bit Default Description
1396 ** 15:13 000b Reserved
1397 ** 12:10 000b GRANT# Duration: This field specifies the count (PCI clocks)
1398 ** that a secondary bus master has its grant maintained in order to enable
1399 ** multiple transactions to execute within the same arbitration cycle.
1400 ** Bit[02:00] GNT# Extended Duration
1401 ** 000 MTT Disabled (Default=no GNT# extension)
1407 ** 110 Invalid (treated as 000)
1408 ** 111 Invalid (treated as 000)
1409 ** 09:08 00b Reserved
1410 ** 07:00 FFh MTT Mask: This field enables/disables MTT usage for each REQ#/GNT#
1411 ** pair supported by bridge secondary arbiter.
1412 ** Bit(7) corresponds to SATU internal REQ#/GNT# pair,
1413 ** bit(6) corresponds to bridge internal REQ#/GNT# pair,
1414 ** bit(5) corresponds to REQ#/GNT#(5) pair, etc.
1415 ** When a given bit is set to 1b, its corresponding REQ#/GNT#
1416 ** pair is enabled for MTT functionality as determined by bits(12:10) of this register.
1417 ** When a given bit is cleared to 0b, its corresponding REQ#/GNT# pair is disabled from using the MTT.
1418 **==================================================================================
1419 ** 0x53-0x52: Read Prefetch Policy Register - RPPR
1420 ** Bit Default Description
1421 ** 15:13 000b ReRead_Primary Bus: 3-bit field indicating the multiplication factor
1422 ** to be used in calculating the number of bytes to prefetch from the secondary bus interface on ** subsequent PreFetch operations given that the read demands were not satisfied
1423 ** using the FirstRead parameter.
1424 ** The default value of 000b correlates to: Command Type Hardwired pre-fetch amount Memory Read 4 DWORDs
1425 ** Memory Read Line 1 cache lines Memory Read Multiple 2 cache lines
1426 ** 12:10 000b FirstRead_Primary Bus: 3-bit field indicating the multiplication factor to be used in calculating
1427 ** the number of bytes to prefetch from the secondary bus interface
1428 ** on the initial PreFetch operation.
1429 ** The default value of 000b correlates to: Command Type Hardwired pre-fetch amount Memory Read 4 DWORDs
1430 ** Memory Read Line 1 cache line Memory Read Multiple 2 cache lines
1431 ** 09:07 010b ReRead_Secondary Bus: 3-bit field indicating the multiplication factor to be used
1432 ** in calculating the number of bytes to prefetch from the primary
1433 ** bus interface on subsequent PreFetch operations given
1434 ** that the read demands were not satisfied using
1435 ** the FirstRead parameter.
1436 ** The default value of 010b correlates to: Command Type Hardwired pre-fetch a
1437 ** mount Memory Read 3 cache lines Memory Read Line 3 cache lines
1438 ** Memory Read Multiple 6 cache lines
1439 ** 06:04 000b FirstRead_Secondary Bus: 3-bit field indicating the multiplication factor to be used
1440 ** in calculating the number of bytes to prefetch from
1441 ** the primary bus interface on the initial PreFetch operation.
1442 ** The default value of 000b correlates to: Command Type Hardwired pre-fetch amount
1443 ** Memory Read 4 DWORDs Memory Read Line 1 cache line Memory Read Multiple 2 cache lines
1444 ** 03:00 1111b Staged Prefetch Enable: This field enables/disables the FirstRead/ReRead pre-fetch
1445 ** algorithm for the secondary and the primary bus interfaces.
1446 ** Bit(3) is a ganged enable bit for REQ#/GNT#[7:3], and bits(2:0) provide individual
1447 ** enable bits for REQ#/GNT#[2:0].
1448 ** (bit(2) is the enable bit for REQ#/GNT#[2], etc...)
1449 ** 1b: enables the staged pre-fetch feature
1450 ** 0b: disables staged pre-fetch,
1451 ** and hardwires read pre-fetch policy to the following for
1453 ** Memory Read Line,
1454 ** and Memory Read Multiple commands:
1455 ** Command Type Hardwired Pre-Fetch Amount...
1456 ** Memory Read 4 DWORDs
1457 ** Memory Read Line 1 cache line
1458 ** Memory Read Multiple 2 cache lines
1459 ** NOTE: When the starting address is not cache line aligned, bridge pre-fetches Memory Read line commands
1460 ** only to the next higher cache line boundary.For non-cache line aligned Memory Read
1461 ** Multiple commands bridge pre-fetches only to the second cache line boundary encountered.
1462 **==================================================================================
1463 ** 0x55-0x54: P_SERR# Assertion Control - SERR_CTL
1464 ** Bit Default Description
1465 ** 15 0b Upstream Delayed Transaction Discard Timer Expired: Dictates the bridge behavior
1466 ** in response to its discarding of a delayed transaction that was initiated from the primary bus.
1467 ** 0b=bridge asserts P_SERR#.
1468 ** 1b=bridge does not assert P_SERR#
1469 ** 14 0b Upstream Delayed/Split Read Watchdog Timer Expired: Dictates bridge behavior following expiration of the subject watchdog timer.
1470 ** 0b=bridge asserts P_SERR#.
1471 ** 1b=bridge does not assert P_SERR#
1472 ** 13 0b Upstream Delayed/Split Write Watchdog Timer Expired: Dictates bridge behavior following expiration of the subject watchdog timer.
1473 ** 0b=bridge asserts P_SERR#.
1474 ** 1b=bridge does not assert P_SERR#
1475 ** 12 0b Master Abort during Upstream Posted Write: Dictates bridge behavior following
1476 ** its having detected a Master Abort while attempting to retire one of its PMWs upstream.
1477 ** 0b=bridge asserts P_SERR#.
1478 ** 1b=bridge does not assert P_SERR#
1479 ** 11 0b Target Abort during Upstream Posted Write: Dictates bridge behavior following
1480 ** its having been terminated with Target Abort while attempting to retire one of its PMWs upstream.
1481 ** 0b=bridge asserts P_SERR#.
1482 ** 1b=bridge does not assert P_SERR#
1483 ** 10 0b Upstream Posted Write Data Discarded: Dictates bridge behavior in the event that
1484 ** it discards an upstream posted write transaction.
1485 ** 0b=bridge asserts P_SERR#.
1486 ** 1b=bridge does not assert P_SERR#
1487 ** 09 0b Upstream Posted Write Data Parity Error: Dictates bridge behavior
1488 ** when a data parity error is detected while attempting to retire on of its PMWs upstream.
1489 ** 0b=bridge asserts P_SERR#.
1490 ** 1b=bridge does not assert P_SERR#
1491 ** 08 0b Secondary Bus Address Parity Error: This bit dictates bridge behavior
1492 ** when it detects an address parity error on the secondary bus.
1493 ** 0b=bridge asserts P_SERR#.
1494 ** 1b=bridge does not assert P_SERR#
1495 ** 07 0b Downstream Delayed Transaction Discard Timer Expired: Dictates bridge behavior in response to
1496 ** its discarding of a delayed transaction that was initiated on the secondary bus.
1497 ** 0b=bridge asserts P_SERR#.
1498 ** 1b=bridge does not assert P_SERR#
1499 ** 06 0b Downstream Delayed/Split Read Watchdog Timer Expired: Dictates bridge behavior following expiration of the subject watchdog timer.
1500 ** 0b=bridge asserts P_SERR#.
1501 ** 1b=bridge does not assert P_SERR#
1502 ** 05 0b Downstream Delayed/Split Write Watchdog Timer Expired: Dictates bridge behavior following expiration of the subject watchdog timer.
1503 ** 0b=bridge asserts P_SERR#.
1504 ** 1b=bridge does not assert P_SERR#
1505 ** 04 0b Master Abort during Downstream Posted Write: Dictates bridge behavior following
1506 ** its having detected a Master Abort while attempting to retire one of its PMWs downstream.
1507 ** 0b=bridge asserts P_SERR#.
1508 ** 1b=bridge does not assert P_SERR#
1509 ** 03 0b Target Abort during Downstream Posted Write: Dictates bridge behavior following
1510 ** its having been terminated with Target Abort while attempting to retire one of its PMWs downstream.
1511 ** 0b=bridge asserts P_SERR#.
1512 ** 1b=bridge does not assert P_SERR#
1513 ** 02 0b Downstream Posted Write Data Discarded: Dictates bridge behavior in the event
1514 ** that it discards a downstream posted write transaction.
1515 ** 0b=bridge asserts P_SERR#.
1516 ** 1b=bridge does not assert P_SERR#
1517 ** 01 0b Downstream Posted Write Data Parity Error: Dictates bridge behavior
1518 ** when a data parity error is detected while attempting to retire on of its PMWs downstream.
1519 ** 0b=bridge asserts P_SERR#.
1520 ** 1b=bridge does not assert P_SERR#
1521 ** 00 0b Primary Bus Address Parity Error: This bit dictates bridge behavior
1522 ** when it detects an address parity error on the primary bus.
1523 ** 0b=bridge asserts P_SERR#.
1524 ** 1b=bridge does not assert P_SERR#
1525 **===============================================================================
1526 ** 0x56: Pre-Boot Status Register - PBSR
1527 ** Bit Default Description
1529 ** 06 - Reserved - value indeterminate
1531 ** 01 Varies with External State of S_133EN at PCI Bus Reset Secondary Bus Max Frequency Setting:
1532 ** This bit reflect captured S_133EN strap,
1533 ** indicating the maximum secondary bus clock frequency when in PCI-X mode.
1534 ** Max Allowable Secondary Bus Frequency
1535 ** ** S_133EN PCI-X Mode
1539 **===============================================================================
1540 ** 0x59-0x58: Secondary Decode Enable Register - SDER
1541 ** Bit Default Description
1542 ** 15:03 FFF1h Preserved.
1543 ** 02 Varies with External State of PRIVMEM at PCI Bus Reset Private Memory Space Enable - when set,
1544 ** bridge overrides its secondary inverse decode logic and not
1545 ** forward upstream any secondary bus initiated DAC Memory transactions with AD(63)=1b.
1546 ** This creates a private memory space on the Secondary PCI bus
1547 ** that allows peer-to-peer transactions.
1548 ** 01:00 10 2 Preserved.
1549 **===============================================================================
1550 ** 0x5D-0x5C: Secondary IDSEL Select Register - SISR
1551 ** Bit Default Description
1552 ** 15:10 000000 2 Reserved.
1553 ** 09 Varies with External State of PRIVDEV at PCI Bus Reset AD25- IDSEL Disable - When this bit is set,
1554 ** AD25 is deasserted for any possible Type 1 to Type 0 conversion.
1555 ** When this bit is clear,
1556 ** AD25 is asserted when Primary addresses AD[15:11]=01001 2 during a Type 1 to Type 0 conversion.
1557 ** 08 Varies with External State of PRIVDEV at PCI Bus Reset AD24- IDSEL Disable - When this bit is set,
1558 ** AD24 is deasserted for any possible Type 1 to Type 0 conversion.
1559 ** When this bit is clear,
1560 ** AD24 is asserted when Primary addresses AD[15:11]=01000 2 during a Type 1 to Type 0 conversion.
1561 ** 07 Varies with External State of PRIVDEV at PCI Bus Reset AD23- IDSEL Disable - When this bit is set,
1562 ** AD23 is deasserted for any possible Type 1 to Type 0 conversion.
1563 ** When this bit is clear,
1564 ** AD23 is asserted when Primary addresses AD[15:11]=00111 2 during a Type 1 to Type 0 conversion.
1565 ** 06 Varies with External State of PRIVDEV at PCI Bus Reset AD22- IDSEL Disable - When this bit is set,
1566 ** AD22 is deasserted for any possible Type 1 to Type 0 conversion.
1567 ** When this bit is clear,
1568 ** AD22 is asserted when Primary addresses AD[15:11]=00110 2 during a Type 1 to Type 0 conversion.
1569 ** 05 Varies with External State of PRIVDEV at PCI Bus Reset AD21- IDSEL Disable - When this bit is set,
1570 ** AD21 is deasserted for any possible Type 1 to Type 0 conversion.
1571 ** When this bit is clear,
1572 ** AD21 is asserted when Primary addresses AD[15:11]=00101 2 during a Type 1 to Type 0 conversion.
1573 ** 04 Varies with External State of PRIVDEV at PCI Bus Reset AD20- IDSEL Disable - When this bit is set,
1574 ** AD20 is deasserted for any possible Type 1 to Type 0 conversion.
1575 ** When this bit is clear,
1576 ** AD20 is asserted when Primary addresses AD[15:11]=00100 2 during a Type 1 to Type 0 conversion.
1577 ** 03 Varies with External State of PRIVDEV at PCI Bus Reset AD19- IDSEL Disable - When this bit is set,
1578 ** AD19 is deasserted for any possible Type 1 to Type 0 conversion.
1579 ** When this bit is clear,
1580 ** AD19 is asserted when Primary addresses AD[15:11]=00011 2 during a Type 1 to Type 0 conversion.
1581 ** 02 Varies with External State of PRIVDEV at PCI Bus Reset AD18- IDSEL Disable - When this bit is set,
1582 ** AD18 is deasserted for any possible Type 1 to Type 0 conversion.
1583 ** When this bit is clear,
1584 ** AD18 is asserted when Primary addresses AD[15:11]=00010 2 during a Type 1 to Type 0 conversion.
1585 ** 01 Varies with External State of PRIVDEV at PCI Bus Reset AD17- IDSEL Disable - When this bit is set,
1586 ** AD17 is deasserted for any possible Type 1 to Type 0 conversion.
1587 ** When this bit is clear,
1588 ** AD17 is asserted when Primary addresses AD[15:11]=00001 2 during a Type 1 to Type 0 conversion.
1589 ** 00 Varies with External State of PRIVDEV at PCI Bus Reset AD16- IDSEL Disable - When this bit is set,
1590 ** AD16 is deasserted for any possible Type 1 to Type 0 conversion.
1591 ** When this bit is clear,
1592 ** AD16 is asserted when Primary addresses AD[15:11]=00000 2 during a Type 1 to Type 0 conversion.
1593 **************************************************************************
1596 **************************************************************************
1598 **************************************************************************
1601 **************************************************************************
1602 ** PCI Extended Enhanced Capabilities List CC-FFh
1603 **************************************************************************
1604 ** ----------------------------------------------------------------------------------------------------------
1605 ** | Byte 3 | Byte 2 | Byte 1 | Byte 0 | Configu-ration Byte Offset
1606 ** ----------------------------------------------------------------------------------------------------------
1607 ** | Power Management Capabilities | Next Item Ptr | Capability ID | DCh
1608 ** ----------------------------------------------------------------------------------------------------------
1609 ** | PM Data | PPB Support | Extensions Power Management CSR | E0h
1610 ** ----------------------------------------------------------------------------------------------------------
1611 ** | Reserved | Reserved | Reserved | E4h
1612 ** ----------------------------------------------------------------------------------------------------------
1614 ** ----------------------------------------------------------------------------------------------------------
1615 ** | Reserved | Reserved | Reserved | Reserved | ECh
1616 ** ----------------------------------------------------------------------------------------------------------
1617 ** | PCI-X Secondary Status | Next Item Ptr | Capability ID | F0h
1618 ** ----------------------------------------------------------------------------------------------------------
1619 ** | PCI-X Bridge Status | F4h
1620 ** ----------------------------------------------------------------------------------------------------------
1621 ** | PCI-X Upstream Split Transaction Control | F8h
1622 ** ----------------------------------------------------------------------------------------------------------
1623 ** | PCI-X Downstream Split Transaction Control | FCh
1624 ** ----------------------------------------------------------------------------------------------------------
1625 **===============================================================================
1626 ** 0xDC: Power Management Capabilities Identifier - PM_CAPID
1627 ** Bit Default Description
1628 ** 07:00 01h Identifier (ID): PCI SIG assigned ID for PCI-PM register block
1629 **===============================================================================
1630 ** 0xDD: Next Item Pointer - PM_NXTP
1631 ** Bit Default Description
1632 ** 07:00 F0H Next Capabilities Pointer (PTR): The register defaults to F0H pointing to the PCI-X Extended Capability Header.
1633 **===============================================================================
1634 ** 0xDF-0xDE: Power Management Capabilities Register - PMCR
1635 ** Bit Default Description
1636 ** 15:11 00h PME Supported (PME): PME# cannot be asserted by bridge.
1637 ** 10 0h State D2 Supported (D2): Indicates no support for state D2. No power management action in this state.
1638 ** 09 1h State D1 Supported (D1): Indicates support for state D1. No power management action in this state.
1639 ** 08:06 0h Auxiliary Current (AUXC): This 3 bit field reports the 3.3Vaux auxiliary current requirements for the PCI function.
1640 ** This returns 000b as PME# wake-up for bridge is not implemented.
1641 ** 05 0 Special Initialization Required (SINT): Special initialization is not required for bridge.
1642 ** 04:03 00 Reserved
1643 ** 02:00 010 Version (VS): Indicates that this supports PCI Bus Power Management Interface Specification, Revision 1.1.
1644 **===============================================================================
1645 ** 0xE1-0xE0: Power Management Control / Status - Register - PMCSR
1646 ** Bit Default Description
1647 ** 15:09 00h Reserved
1648 ** 08 0b PME_Enable: This bit, when set to 1b enables bridge to assert PME#.
1649 ** Note that bridge never has occasion to assert PME# and implements this dummy R/W bit only for the purpose of working around an OS PCI-PM bug.
1650 ** 07:02 00h Reserved
1651 ** 01:00 00 Power State (PSTATE): This 2-bit field is used both to determine the current power state of
1652 ** a function and to set the Function into a new power state.
1656 ** 11 - D3 hot state
1657 **===============================================================================
1658 ** 0xE2: Power Management Control / Status PCI to PCI Bridge Support - PMCSR_BSE
1659 ** Bit Default Description
1660 ** 07 0 Bus Power/Clock Control Enable (BPCC_En): Indicates that the bus power/clock control policies have been disabled.
1661 ** 06 0 B2/B3 support for D3 Hot (B2_B3#): The state of this bit determines the action that
1662 ** is to occur as a direct result of programming the function to D3 hot.
1663 ** This bit is only meaningful when bit 7 (BPCC_En) is a ¡§1¡¨.
1664 ** 05:00 00h Reserved
1665 **===============================================================================
1666 ** 0xE3: Power Management Data Register - PMDR
1667 ** Bit Default Description
1668 ** 07:00 00h Reserved
1669 **===============================================================================
1670 ** 0xF0: PCI-X Capabilities Identifier - PX_CAPID
1671 ** Bit Default Description
1672 ** 07:00 07h Identifier (ID): Indicates this is a PCI-X capabilities list.
1673 **===============================================================================
1674 ** 0xF1: Next Item Pointer - PX_NXTP
1675 ** Bit Default Description
1676 ** 07:00 00h Next Item Pointer: Points to the next capability in the linked list The power on default value of this
1677 ** register is 00h indicating that this is the last entry in the linked list of capabilities.
1678 **===============================================================================
1679 ** 0xF3-0xF2: PCI-X Secondary Status - PX_SSTS
1680 ** Bit Default Description
1681 ** 15:09 00h Reserved
1682 ** 08:06 Xxx Secondary Clock Frequency (SCF): This field is set with the frequency of the secondary bus.
1684 ** ** BitsMax FrequencyClock Period
1685 ** ** 000PCI ModeN/A
1689 ** ** 1xxreservedreserved
1690 ** ** The default value for this register is the operating frequency of the secondary bus
1691 ** 05 0b Split Request Delayed. (SRD): This bit is supposed to be set by a bridge when it cannot forward a transaction on the
1692 ** secondary bus to the primary bus because there is not enough room within the limit
1693 ** specified in the Split Transaction Commitment Limit field in the Downstream Split
1694 ** Transaction Control register. The bridge does not set this bit.
1695 ** 04 0b Split Completion Overrun (SCO): This bit is supposed to be set when a bridge terminates a Split Completion on the ** ** secondary bus with retry or Disconnect at next ADB because its buffers are full.
1696 ** The bridge does not set this bit.
1697 ** 03 0b Unexpected Split Completion (USC): This bit is set when an unexpected split completion with a requester ID
1698 ** equal to bridge secondary bus number, device number 00h,
1699 ** and function number 0 is received on the secondary interface.
1700 ** This bit is cleared by software writing a '1'.
1701 ** 02 0b Split Completion Discarded (SCD): This bit is set
1702 ** when bridge discards a split completion moving toward the secondary bus
1703 ** because the requester would not accept it. This bit cleared by software writing a '1'.
1704 ** 01 1b 133 MHz Capable: Indicates that bridge is capable of running its secondary bus at 133 MHz
1705 ** 00 1b 64-bit Device (D64): Indicates the width of the secondary bus as 64-bits.
1706 **===============================================================================
1707 ** 0xF7-0xF6-0xf5-0xF4: PCI-X Bridge Status - PX_BSTS
1708 ** Bit Default Description
1710 ** 21 0 Split Request Delayed (SRD): This bit does not be set by bridge.
1711 ** 20 0 Split Completion Overrun (SCO): This bit does not be set by bridge
1712 ** because bridge throttles traffic on the completion side.
1713 ** 19 0 Unexpected Split Completion (USC): The bridge sets this bit to 1b
1714 ** when it encounters a corrupted Split Completion, possibly with an ** ** inconsistent remaining byte count.Software clears
1715 ** this bit by writing a 1b to it.
1716 ** 18 0 Split Completion Discarded (SCD): The bridge sets this bit to 1b
1717 ** when it has discarded a Split Completion.Software clears this bit by ** ** writing a 1b to it.
1718 ** 17 1 133 MHz Capable: This bit indicates that the bridge primary interface is ** capable of 133 MHz operation in PCI-X mode.
1719 ** 0=The maximum operating frequency is 66 MHz.
1720 ** 1=The maximum operating frequency is 133 MHz.
1721 ** 16 Varies with the external state of P_32BITPCI# at PCI Bus Reset 64-bit Device (D64): Indicates bus width of the Primary PCI bus interface.
1722 ** 0=Primary Interface is connected as a 32-bit PCI bus.
1723 ** 1=Primary Interface is connected as a 64-bit PCI bus.
1724 ** 15:08 00h Bus Number (BNUM): This field is simply an alias to the PBN field
1725 ** of the BNUM register at offset 18h.
1726 ** Apparently it was deemed necessary reflect it here for diagnostic purposes.
1727 ** 07:03 1fh Device Number (DNUM): Indicates which IDSEL bridge consumes.
1728 ** May be updated whenever a PCI-X
1729 ** configuration write cycle that targets bridge scores a hit.
1730 ** 02:00 0h Function Number (FNUM): The bridge Function #
1731 **===============================================================================
1732 ** 0xFB-0xFA-0xF9-0xF8: PCI-X Upstream Split Transaction Control - PX_USTC
1733 ** Bit Default Description
1734 ** 31:16 003Eh Split Transaction Limit (STL): This register indicates the size of the commitment limit in units of ADQs.
1735 ** Software is permitted to program this register to any value greater than or equal to
1736 ** the contents of the Split Transaction Capacity register. A value less than the contents
1737 ** of the Split Transaction Capacity register causes unspecified results.
1738 ** A value of 003Eh or greater enables the bridge to forward all Split Requests of any
1739 ** size regardless of the amount of buffer space available.
1740 ** 15:00 003Eh Split Transaction Capacity (STC): This read-only field indicates the size of the buffer (number of ADQs) for storing
1741 ** split completions. This register controls behavior of the bridge buffers for forwarding
1742 ** Split Transactions from a primary bus requester to a secondary bus completer.
1743 ** The default value of 003Eh indicates there is available buffer space for 62 ADQs (7936 bytes).
1744 **===============================================================================
1745 ** 0xFF-0xFE-0xFD-0xFC: PCI-X Downstream Split Transaction Control - PX_DSTC
1746 ** Bit Default Description
1747 ** 31:16 003Eh Split Transaction Limit (STL): This register indicates the size of the commitment limit in units of ADQs.
1748 ** Software is permitted to program this register to any value greater than or equal to
1749 ** the contents of the Split Transaction Capacity register. A value less than the contents
1750 ** of the Split Transaction Capacity register causes unspecified results.
1751 ** A value of 003Eh or greater enables the bridge to forward all Split Requests of any
1752 ** size regardless of the amount of buffer space available.
1753 ** 15:00 003Eh Split Transaction Capacity (STC): This read-only field indicates the size of the buffer (number of ADQs) for storing
1754 ** split completions. This register controls behavior of the bridge buffers for forwarding
1755 ** Split Transactions from a primary bus requester to a secondary bus completer.
1756 ** The default value of 003Eh indicates there is available buffer space for 62 ADQs
1758 **************************************************************************
1765 *************************************************************************************************************************************
1766 ** 80331 Address Translation Unit Register Definitions
1767 ** ATU Interface Configuration Header Format
1768 ** The ATU is programmed via a [Type 0] configuration command on the PCI interface.
1769 *************************************************************************************************************************************
1770 ** | Byte 3 | Byte 2 | Byte 1 | Byte 0 | Configuration Byte Offset
1771 **===================================================================================================================================
1772 ** | ATU Device ID | Vendor ID | 00h
1773 ** ----------------------------------------------------------------------------------------------------------
1774 ** | Status | Command | 04H
1775 ** ----------------------------------------------------------------------------------------------------------
1776 ** | ATU Class Code | Revision ID | 08H
1777 ** ----------------------------------------------------------------------------------------------------------
1778 ** | ATUBISTR | Header Type | Latency Timer | Cacheline Size | 0CH
1779 ** ----------------------------------------------------------------------------------------------------------
1780 ** | Inbound ATU Base Address 0 | 10H
1781 ** ----------------------------------------------------------------------------------------------------------
1782 ** | Inbound ATU Upper Base Address 0 | 14H
1783 ** ----------------------------------------------------------------------------------------------------------
1784 ** | Inbound ATU Base Address 1 | 18H
1785 ** ----------------------------------------------------------------------------------------------------------
1786 ** | Inbound ATU Upper Base Address 1 | 1CH
1787 ** ----------------------------------------------------------------------------------------------------------
1788 ** | Inbound ATU Base Address 2 | 20H
1789 ** ----------------------------------------------------------------------------------------------------------
1790 ** | Inbound ATU Upper Base Address 2 | 24H
1791 ** ----------------------------------------------------------------------------------------------------------
1793 ** ----------------------------------------------------------------------------------------------------------
1794 ** | ATU Subsystem ID | ATU Subsystem Vendor ID | 2CH
1795 ** ----------------------------------------------------------------------------------------------------------
1796 ** | Expansion ROM Base Address | 30H
1797 ** ----------------------------------------------------------------------------------------------------------
1798 ** | Reserved Capabilities Pointer | 34H
1799 ** ----------------------------------------------------------------------------------------------------------
1801 ** ----------------------------------------------------------------------------------------------------------
1802 ** | Maximum Latency | Minimum Grant | Interrupt Pin | Interrupt Line | 3CH
1803 ** ----------------------------------------------------------------------------------------------------------
1804 *********************************************************************************************************************
1807 ***********************************************************************************
1808 ** ATU Vendor ID Register - ATUVID
1809 ** -----------------------------------------------------------------
1810 ** Bit Default Description
1811 ** 15:00 8086H (0x17D3) ATU Vendor ID - This is a 16-bit value assigned to Intel.
1812 ** This register, combined with the DID, uniquely identify the PCI device.
1813 ** Access type is Read/Write to allow the 80331 to configure the register as a different vendor ID
1814 ** to simulate the interface of a standard mechanism currently used by existing application software.
1815 ***********************************************************************************
1817 #define ARCMSR_ATU_VENDOR_ID_REG 0x00 /*word*/
1819 ***********************************************************************************
1820 ** ATU Device ID Register - ATUDID
1821 ** -----------------------------------------------------------------
1822 ** Bit Default Description
1823 ** 15:00 0336H (0x1110) ATU Device ID - This is a 16-bit value assigned to the ATU.
1824 ** This ID, combined with the VID, uniquely identify any PCI device.
1825 ***********************************************************************************
1827 #define ARCMSR_ATU_DEVICE_ID_REG 0x02 /*word*/
1829 ***********************************************************************************
1830 ** ATU Command Register - ATUCMD
1831 ** -----------------------------------------------------------------
1832 ** Bit Default Description
1833 ** 15:11 000000 2 Reserved
1834 ** 10 0 Interrupt Disable - This bit disables 80331 from asserting the ATU interrupt signal.
1835 ** 0=enables the assertion of interrupt signal.
1836 ** 1=disables the assertion of its interrupt signal.
1837 ** 09 0 2 Fast Back to Back Enable - When cleared,
1838 ** the ATU interface is not allowed to generate fast back-to-back cycles on its bus.
1839 ** Ignored when operating in the PCI-X mode.
1840 ** 08 0 2 SERR# Enable - When cleared, the ATU interface is not allowed to assert SERR# on the PCI interface.
1841 ** 07 1 2 Address/Data Stepping Control - Address stepping is implemented for configuration transactions. The
1842 ** ATU inserts 2 clock cycles of address stepping for Conventional Mode and 4 clock cycles
1843 ** of address stepping for PCI-X mode.
1844 ** 06 0 2 Parity Error Response - When set, the ATU takes normal action when a parity error
1845 ** is detected. When cleared, parity checking is disabled.
1846 ** 05 0 2 VGA Palette Snoop Enable - The ATU interface does not support I/O writes and therefore,
1847 ** does not perform VGA palette snooping.
1848 ** 04 0 2 Memory Write and Invalidate Enable - When set, ATU may generate MWI commands.
1849 ** When clear, ATU use Memory Write commands instead of MWI. Ignored when operating in the PCI-X mode.
1850 ** 03 0 2 Special Cycle Enable - The ATU interface does not respond to special cycle commands in any way.
1851 ** Not implemented and a reserved bit field.
1852 ** 02 0 2 Bus Master Enable - The ATU interface can act as a master on the PCI bus.
1853 ** When cleared, disables the device from generating PCI accesses.
1854 ** When set, allows the device to behave as a PCI bus master.
1855 ** When operating in the PCI-X mode, ATU initiates a split completion transaction regardless
1856 ** of the state of this bit.
1857 ** 01 0 2 Memory Enable - Controls the ATU interface¡¦s response to PCI memory addresses.
1858 ** When cleared, the ATU interface does not respond to any memory access on the PCI bus.
1859 ** 00 0 2 I/O Space Enable - Controls the ATU interface response to I/O transactions.
1860 ** Not implemented and a reserved bit field.
1861 ***********************************************************************************
1863 #define ARCMSR_ATU_COMMAND_REG 0x04 /*word*/
1865 ***********************************************************************************
1866 ** ATU Status Register - ATUSR (Sheet 1 of 2)
1867 ** -----------------------------------------------------------------
1868 ** Bit Default Description
1869 ** 15 0 2 Detected Parity Error - set when a parity error is detected in data received by the ATU on the PCI bus even
1870 ** when the ATUCMD register¡¦s Parity Error Response bit is cleared. Set under the following conditions:
1871 ** ¡E Write Data Parity Error when the ATU is a target (inbound write).
1872 ** ¡E Read Data Parity Error when the ATU is a requester (outbound read).
1873 ** ¡E Any Address or Attribute (PCI-X Only) Parity Error on the Bus ** ** ** (including one generated by the ATU).
1874 ** 14 0 2 SERR# Asserted - set when SERR# is asserted on the PCI bus by the ATU.
1875 ** 13 0 2 Master Abort - set when a transaction initiated by the ATU PCI master interface, ends in a Master-Abort
1876 ** or when the ATU receives a Master Abort Split Completion Error Message in PCI-X mode.
1877 ** 12 0 2 Target Abort (master) - set when a transaction initiated by the ATU PCI master interface, ends in a target
1878 ** abort or when the ATU receives a Target Abort Split Completion Error Message in PCI-X mode.
1879 ** 11 0 2 Target Abort (target) - set when the ATU interface, acting as a target,
1880 ** terminates the transaction on the PCI bus with a target abort.
1881 ** 10:09 01 2 DEVSEL# Timing - These bits are read-only and define the slowest DEVSEL#
1882 ** timing for a target device in Conventional PCI Mode regardless of the operating mode
1883 ** (except configuration accesses).
1888 ** The ATU interface uses Medium timing.
1889 ** 08 0 2 Master Parity Error - The ATU interface sets this bit under the following conditions:
1890 ** ¡E The ATU asserted PERR# itself or the ATU observed PERR# asserted.
1891 ** ¡E And the ATU acted as the requester
1892 ** for the operation in which the error occurred.
1893 ** ¡E And the ATUCMD register¡¦s Parity Error Response bit is set
1894 ** ¡E Or (PCI-X Mode Only) the ATU received a Write Data Parity Error Message
1895 ** ¡E And the ATUCMD register¡¦s Parity Error Response bit is set
1896 ** 07 1 2 (Conventional mode)
1898 ** Fast Back-to-Back - The ATU/Messaging Unit interface is capable of accepting fast back-to-back
1899 ** transactions in Conventional PCI mode when the transactions are not to the same target. Since fast
1900 ** back-to-back transactions do not exist in PCI-X mode, this bit is forced to 0 in the PCI-X mode.
1901 ** 06 0 2 UDF Supported - User Definable Features are not supported
1902 ** 05 1 2 66 MHz. Capable - 66 MHz operation is supported.
1903 ** 04 1 2 Capabilities - When set, this function implements extended capabilities.
1904 ** 03 0 Interrupt Status - reflects the state of the ATU interrupt
1905 ** when the Interrupt Disable bit in the command register is a 0.
1906 ** 0=ATU interrupt signal deasserted.
1907 ** 1=ATU interrupt signal asserted.
1908 ** NOTE: Setting the Interrupt Disable bit to a 1 has no effect on the state of this bit. Refer to
1909 ** Section 3.10.23, ¡§ATU Interrupt Pin Register - ATUIPR¡¨ on page 236 for details on the ATU
1910 ** interrupt signal.
1911 ** 02:00 00000 2 Reserved.
1912 ***********************************************************************************
1914 #define ARCMSR_ATU_STATUS_REG 0x06 /*word*/
1916 ***********************************************************************************
1917 ** ATU Revision ID Register - ATURID
1918 ** -----------------------------------------------------------------
1919 ** Bit Default Description
1920 ** 07:00 00H ATU Revision - identifies the 80331 revision number.
1921 ***********************************************************************************
1923 #define ARCMSR_ATU_REVISION_REG 0x08 /*byte*/
1925 ***********************************************************************************
1926 ** ATU Class Code Register - ATUCCR
1927 ** -----------------------------------------------------------------
1928 ** Bit Default Description
1929 ** 23:16 05H Base Class - Memory Controller
1930 ** 15:08 80H Sub Class - Other Memory Controller
1931 ** 07:00 00H Programming Interface - None defined
1932 ***********************************************************************************
1934 #define ARCMSR_ATU_CLASS_CODE_REG 0x09 /*3bytes 0x0B,0x0A,0x09*/
1936 ***********************************************************************************
1937 ** ATU Cacheline Size Register - ATUCLSR
1938 ** -----------------------------------------------------------------
1939 ** Bit Default Description
1940 ** 07:00 00H ATU Cacheline Size - specifies the system cacheline size in DWORDs. Cacheline size is restricted to either 0, 8 or 16 DWORDs.
1941 ***********************************************************************************
1943 #define ARCMSR_ATU_CACHELINE_SIZE_REG 0x0C /*byte*/
1945 ***********************************************************************************
1946 ** ATU Latency Timer Register - ATULT
1947 ** -----------------------------------------------------------------
1948 ** Bit Default Description
1949 ** 07:03 00000 2 (for Conventional mode)
1950 ** 01000 2 (for PCI-X mode)
1951 ** Programmable Latency Timer - This field varies the latency timer for the interface from 0 to 248 clocks.
1952 ** The default value is 0 clocks for Conventional PCI mode, and 64 clocks for PCI-X mode.
1953 ** 02:00 000 2 Latency Timer Granularity - These Bits are read only giving a programmable granularity of 8 clocks for the latency timer.
1954 ***********************************************************************************
1956 #define ARCMSR_ATU_LATENCY_TIMER_REG 0x0D /*byte*/
1958 ***********************************************************************************
1959 ** ATU Header Type Register - ATUHTR
1960 ** -----------------------------------------------------------------
1961 ** Bit Default Description
1962 ** 07 0 2 Single Function/Multi-Function Device - Identifies the 80331 as a single-function PCI device.
1963 ** 06:00 000000 2 PCI Header Type - This bit field indicates the type of PCI header implemented. The ATU interface
1964 ** header conforms to PCI Local Bus Specification, Revision 2.3.
1965 ***********************************************************************************
1967 #define ARCMSR_ATU_HEADER_TYPE_REG 0x0E /*byte*/
1969 ***********************************************************************************
1970 ** ATU BIST Register - ATUBISTR
1972 ** The ATU BIST Register controls the functions the Intel XScale core performs when BIST is
1973 ** initiated. This register is the interface between the host processor requesting BIST functions and
1974 ** the 80331 replying with the results from the software implementation of the BIST functionality.
1975 ** -----------------------------------------------------------------
1976 ** Bit Default Description
1977 ** 07 0 2 BIST Capable - This bit value is always equal to the ATUCR ATU BIST Interrupt Enable bit.
1978 ** 06 0 2 Start BIST - When the ATUCR BIST Interrupt Enable bit is set:
1979 ** Setting this bit generates an interrupt to the Intel XScale core to perform a software BIST function.
1980 ** The Intel XScale core clears this bit when the BIST software has completed with the BIST results
1981 ** found in ATUBISTR register bits [3:0].
1982 ** When the ATUCR BIST Interrupt Enable bit is clear:
1983 ** Setting this bit does not generate an interrupt to the Intel XScale core and no BIST functions is performed.
1984 ** The Intel XScale core does not clear this bit.
1985 ** 05:04 00 2 Reserved
1986 ** 03:00 0000 2 BIST Completion Code - when the ATUCR BIST Interrupt Enable bit is set and the ATUBISTR Start BIST bit is set (bit 6):
1987 ** The Intel XScale core places the results of the software BIST in these bits.
1988 ** A nonzero value indicates a device-specific error.
1989 ***********************************************************************************
1991 #define ARCMSR_ATU_BIST_REG 0x0F /*byte*/
1994 ***************************************************************************************
1995 ** ATU Base Registers and Associated Limit Registers
1996 ***************************************************************************************
1997 ** Base Address Register Limit Register Description
1998 ** Inbound ATU Base Address Register 0 Inbound ATU Limit Register 0 Defines the inbound translation window 0 from the PCI bus.
1999 ** Inbound ATU Upper Base Address Register 0 N/A Together with ATU Base Address Register 0 defines the inbound ** translation window 0 from the PCI bus for DACs.
2000 ** Inbound ATU Base Address Register 1 Inbound ATU Limit Register 1 Defines inbound window 1 from the PCI bus.
2001 ** Inbound ATU Upper Base Address Register 1 N/A Together with ATU Base Address Register 1 defines inbound window ** 1 from the PCI bus for DACs.
2002 ** Inbound ATU Base Address Register 2 Inbound ATU Limit Register 2 Defines the inbound translation window 2 from the PCI bus.
2003 ** Inbound ATU Upper Base Address Register 2 N/A Together with ATU Base Address Register 2 defines the inbound ** ** translation window 2 from the PCI bus for DACs.
2004 ** Inbound ATU Base Address Register 3 Inbound ATU Limit Register 3 Defines the inbound translation window 3 from the PCI bus.
2005 ** Inbound ATU Upper Base Address Register 3 N/A Together with ATU Base Address Register 3 defines the inbound ** ** translation window 3 from the PCI bus for DACs.
2006 ** NOTE: This is a private BAR that resides outside of the standard PCI configuration header space (offsets 00H-3FH).
2007 ** Expansion ROM Base Address Register Expansion ROM Limit Register Defines the window of addresses used by a bus master for reading ** from an Expansion ROM.
2008 **--------------------------------------------------------------------------------------
2009 ** ATU Inbound Window 1 is not a translate window.
2010 ** The ATU does not claim any PCI accesses that fall within this range.
2011 ** This window is used to allocate host memory for use by Private Devices.
2012 ** When enabled, the ATU interrupts the Intel XScale core when either the IABAR1 register or the IAUBAR1 register is written from the PCI bus.
2013 ***********************************************************************************
2017 ***********************************************************************************
2018 ** Inbound ATU Base Address Register 0 - IABAR0
2020 ** . The Inbound ATU Base Address Register 0 (IABAR0) together with the Inbound ATU Upper Base Address Register 0 (IAUBAR0)
2021 ** defines the block of memory addresses where the inbound translation window 0 begins.
2022 ** . The inbound ATU decodes and forwards the bus request to the 80331 internal bus with a translated address to map into 80331 local memory.
2023 ** . The IABAR0 and IAUBAR0 define the base address and describes the required memory block size.
2024 ** . Bits 31 through 12 of the IABAR0 is either read/write bits or read only with a value of 0
2025 ** depending on the value located within the IALR0.
2026 ** This configuration allows the IABAR0 to be programmed per PCI Local Bus Specification.
2027 ** The first 4 Kbytes of memory defined by the IABAR0, IAUBAR0 and the IALR0 is reserved for the Messaging Unit.
2028 ** The programmed value within the base address register must comply with the PCI programming requirements for address alignment.
2030 ** When IALR0 is cleared prior to host configuration:
2031 ** the user should also clear the Prefetchable Indicator and the Type Indicator.
2032 ** Assuming IALR0 is not cleared:
2033 ** a. Since non prefetchable memory windows can never be placed above the 4 Gbyte address boundary,
2034 ** when the Prefetchable Indicator is cleared prior to host configuration,
2035 ** the user should also set the Type Indicator for 32 bit addressability.
2036 ** b. For compliance to the PCI-X Addendum to the PCI Local Bus Specification,
2037 ** when the Prefetchable Indicator is set prior to host configuration, the user
2038 ** should also set the Type Indicator for 64 bit addressability.
2039 ** This is the default for IABAR0.
2040 ** -----------------------------------------------------------------
2041 ** Bit Default Description
2042 ** 31:12 00000H Translation Base Address 0 - These bits define the actual location
2043 ** the translation function is to respond to when addressed from the PCI bus.
2044 ** 11:04 00H Reserved.
2045 ** 03 1 2 Prefetchable Indicator - When set, defines the memory space as prefetchable.
2046 ** 02:01 10 2 Type Indicator - Defines the width of the addressability for this memory window:
2047 ** 00 - Memory Window is locatable anywhere in 32 bit address space
2048 ** 10 - Memory Window is locatable anywhere in 64 bit address space
2049 ** 00 0 2 Memory Space Indicator - This bit field describes memory or I/O space base address.
2050 ** The ATU does not occupy I/O space,
2051 ** thus this bit must be zero.
2052 ***********************************************************************************
2054 #define ARCMSR_INBOUND_ATU_BASE_ADDRESS0_REG 0x10 /*dword 0x13,0x12,0x11,0x10*/
2055 #define ARCMSR_INBOUND_ATU_MEMORY_PREFETCHABLE 0x08
2056 #define ARCMSR_INBOUND_ATU_MEMORY_WINDOW64 0x04
2058 ***********************************************************************************
2059 ** Inbound ATU Upper Base Address Register 0 - IAUBAR0
2061 ** This register contains the upper base address when decoding PCI addresses beyond 4 GBytes.
2062 ** Together with the Translation Base Address this register defines the actual location the translation
2063 ** function is to respond to when addressed from the PCI bus for addresses > 4GBytes (for DACs).
2064 ** The programmed value within the base address register must comply with the PCI programming requirements for address alignment.
2066 ** When the Type indicator of IABAR0 is set to indicate 32 bit addressability,
2067 ** the IAUBAR0 register attributes are read-only.
2068 ** -----------------------------------------------------------------
2069 ** Bit Default Description
2070 ** 31:0 00000H Translation Upper Base Address 0 - Together with the Translation Base Address 0 these bits define the
2071 ** actual location the translation function is to respond to when addressed from the PCI bus for addresses > 4GBytes.
2072 ***********************************************************************************
2074 #define ARCMSR_INBOUND_ATU_UPPER_BASE_ADDRESS0_REG 0x14 /*dword 0x17,0x16,0x15,0x14*/
2076 ***********************************************************************************
2077 ** Inbound ATU Base Address Register 1 - IABAR1
2079 ** . The Inbound ATU Base Address Register (IABAR1) together with the Inbound ATU Upper Base Address Register 1 (IAUBAR1)
2080 ** defines the block of memory addresses where the inbound translation window 1 begins.
2081 ** . This window is used merely to allocate memory on the PCI bus and, the ATU does not process any PCI bus transactions to this memory range.
2082 ** . The programmed value within the base address register must comply with the PCI programming requirements for address alignment.
2083 ** . When enabled, the ATU interrupts the Intel XScale core when the IABAR1 register is written from the PCI bus.
2085 ** When a non-zero value is not written to IALR1 prior to host configuration,
2086 ** the user should not set either the Prefetchable Indicator or the Type Indicator for 64 bit addressability.
2087 ** This is the default for IABAR1.
2088 ** Assuming a non-zero value is written to IALR1,
2089 ** the user may set the Prefetchable Indicator
2090 ** or the Type Indicator:
2091 ** a. Since non prefetchable memory windows can never be placed above the 4 Gbyte address
2092 ** boundary, when the Prefetchable Indicator is not set prior to host configuration,
2093 ** the user should also leave the Type Indicator set for 32 bit addressability.
2094 ** This is the default for IABAR1.
2095 ** b. when the Prefetchable Indicator is set prior to host configuration,
2096 ** the user should also set the Type Indicator for 64 bit addressability.
2097 ** -----------------------------------------------------------------
2098 ** Bit Default Description
2099 ** 31:12 00000H Translation Base Address 1 - These bits define the actual location of window 1 on the PCI bus.
2100 ** 11:04 00H Reserved.
2101 ** 03 0 2 Prefetchable Indicator - When set, defines the memory space as prefetchable.
2102 ** 02:01 00 2 Type Indicator - Defines the width of the addressability for this memory window:
2103 ** 00 - Memory Window is locatable anywhere in 32 bit address space
2104 ** 10 - Memory Window is locatable anywhere in 64 bit address space
2105 ** 00 0 2 Memory Space Indicator - This bit field describes memory or I/O space base address.
2106 ** The ATU does not occupy I/O space,
2107 ** thus this bit must be zero.
2108 ***********************************************************************************
2110 #define ARCMSR_INBOUND_ATU_BASE_ADDRESS1_REG 0x18 /*dword 0x1B,0x1A,0x19,0x18*/
2112 ***********************************************************************************
2113 ** Inbound ATU Upper Base Address Register 1 - IAUBAR1
2115 ** This register contains the upper base address when locating this window for PCI addresses beyond 4 GBytes.
2116 ** Together with the IABAR1 this register defines the actual location for this memory window for addresses > 4GBytes (for DACs).
2117 ** This window is used merely to allocate memory on the PCI bus and, the ATU does not process any PCI bus transactions to this memory range.
2118 ** The programmed value within the base address register must comply with the PCI programming
2119 ** requirements for address alignment.
2120 ** When enabled, the ATU interrupts the Intel XScale core when the IAUBAR1 register is written
2121 ** from the PCI bus.
2123 ** When the Type indicator of IABAR1 is set to indicate 32 bit addressability,
2124 ** the IAUBAR1 register attributes are read-only.
2125 ** This is the default for IABAR1.
2126 ** -----------------------------------------------------------------
2127 ** Bit Default Description
2128 ** 31:0 00000H Translation Upper Base Address 1 - Together with the Translation Base Address 1
2129 ** these bits define the actual location for this memory window on the PCI bus for addresses > 4GBytes.
2130 ***********************************************************************************
2132 #define ARCMSR_INBOUND_ATU_UPPER_BASE_ADDRESS1_REG 0x1C /*dword 0x1F,0x1E,0x1D,0x1C*/
2134 ***********************************************************************************
2135 ** Inbound ATU Base Address Register 2 - IABAR2
2137 ** . The Inbound ATU Base Address Register 2 (IABAR2) together with the Inbound ATU Upper Base Address Register 2 (IAUBAR2)
2138 ** defines the block of memory addresses where the inbound translation window 2 begins.
2139 ** . The inbound ATU decodes and forwards the bus request to the 80331 internal bus with a translated address to map into 80331 local memory.
2140 ** . The IABAR2 and IAUBAR2 define the base address and describes the required memory block size
2141 ** . Bits 31 through 12 of the IABAR2 is either read/write bits or read only with a value of 0 depending on the value located within the IALR2.
2142 ** The programmed value within the base address register must comply with the PCI programming requirements for address alignment.
2144 ** When a non-zero value is not written to IALR2 prior to host configuration,
2145 ** the user should not set either the Prefetchable Indicator
2146 ** or the Type Indicator for 64 bit addressability.
2147 ** This is the default for IABAR2.
2148 ** Assuming a non-zero value is written to IALR2,
2149 ** the user may set the Prefetchable Indicator
2150 ** or the Type Indicator:
2151 ** a. Since non prefetchable memory windows can never be placed above the 4 Gbyte address boundary,
2152 ** when the Prefetchable Indicator is not set prior to host configuration,
2153 ** the user should also leave the Type Indicator set for 32 bit addressability.
2154 ** This is the default for IABAR2.
2155 ** b. when the Prefetchable Indicator is set prior to host configuration,
2156 ** the user should also set the Type Indicator for 64 bit addressability.
2157 ** -----------------------------------------------------------------
2158 ** Bit Default Description
2159 ** 31:12 00000H Translation Base Address 2 - These bits define the actual location
2160 ** the translation function is to respond to when addressed from the PCI bus.
2161 ** 11:04 00H Reserved.
2162 ** 03 0 2 Prefetchable Indicator - When set, defines the memory space as prefetchable.
2163 ** 02:01 00 2 Type Indicator - Defines the width of the addressability for this memory window:
2164 ** 00 - Memory Window is locatable anywhere in 32 bit address space
2165 ** 10 - Memory Window is locatable anywhere in 64 bit address space
2166 ** 00 0 2 Memory Space Indicator - This bit field describes memory or I/O space base address.
2167 ** The ATU does not occupy I/O space,
2168 ** thus this bit must be zero.
2169 ***********************************************************************************
2171 #define ARCMSR_INBOUND_ATU_BASE_ADDRESS2_REG 0x20 /*dword 0x23,0x22,0x21,0x20*/
2173 ***********************************************************************************
2174 ** Inbound ATU Upper Base Address Register 2 - IAUBAR2
2176 ** This register contains the upper base address when decoding PCI addresses beyond 4 GBytes.
2177 ** Together with the Translation Base Address this register defines the actual location
2178 ** the translation function is to respond to when addressed from the PCI bus for addresses > 4GBytes (for DACs).
2179 ** The programmed value within the base address register must comply with the PCI programming
2180 ** requirements for address alignment.
2182 ** When the Type indicator of IABAR2 is set to indicate 32 bit addressability,
2183 ** the IAUBAR2 register attributes are read-only.
2184 ** This is the default for IABAR2.
2185 ** -----------------------------------------------------------------
2186 ** Bit Default Description
2187 ** 31:0 00000H Translation Upper Base Address 2 - Together with the Translation Base Address 2
2188 ** these bits define the actual location the translation function is to respond to
2189 ** when addressed from the PCI bus for addresses > 4GBytes.
2190 ***********************************************************************************
2192 #define ARCMSR_INBOUND_ATU_UPPER_BASE_ADDRESS2_REG 0x24 /*dword 0x27,0x26,0x25,0x24*/
2194 ***********************************************************************************
2195 ** ATU Subsystem Vendor ID Register - ASVIR
2196 ** -----------------------------------------------------------------
2197 ** Bit Default Description
2198 ** 15:0 0000H Subsystem Vendor ID - This register uniquely identifies the add-in board or subsystem vendor.
2199 ***********************************************************************************
2201 #define ARCMSR_ATU_SUBSYSTEM_VENDOR_ID_REG 0x2C /*word 0x2D,0x2C*/
2203 ***********************************************************************************
2204 ** ATU Subsystem ID Register - ASIR
2205 ** -----------------------------------------------------------------
2206 ** Bit Default Description
2207 ** 15:0 0000H Subsystem ID - uniquely identifies the add-in board or subsystem.
2208 ***********************************************************************************
2210 #define ARCMSR_ATU_SUBSYSTEM_ID_REG 0x2E /*word 0x2F,0x2E*/
2212 ***********************************************************************************
2213 ** Expansion ROM Base Address Register -ERBAR
2214 ** -----------------------------------------------------------------
2215 ** Bit Default Description
2216 ** 31:12 00000H Expansion ROM Base Address - These bits define the actual location
2217 ** where the Expansion ROM address window resides when addressed from the PCI bus on any 4 Kbyte boundary.
2218 ** 11:01 000H Reserved
2219 ** 00 0 2 Address Decode Enable - This bit field shows the ROM address
2220 ** decoder is enabled or disabled. When cleared, indicates the address decoder is disabled.
2221 ***********************************************************************************
2223 #define ARCMSR_EXPANSION_ROM_BASE_ADDRESS_REG 0x30 /*dword 0x33,0x32,0v31,0x30*/
2224 #define ARCMSR_EXPANSION_ROM_ADDRESS_DECODE_ENABLE 0x01
2226 ***********************************************************************************
2227 ** ATU Capabilities Pointer Register - ATU_CAP_PTR
2228 ** -----------------------------------------------------------------
2229 ** Bit Default Description
2230 ** 07:00 C0H Capability List Pointer - This provides an offset in this function¡¦s configuration space
2231 ** that points to the 80331 PCl Bus Power Management extended capability.
2232 ***********************************************************************************
2234 #define ARCMSR_ATU_CAPABILITY_PTR_REG 0x34 /*byte*/
2236 ***********************************************************************************
2237 ** Determining Block Sizes for Base Address Registers
2238 ** The required address size and type can be determined by writing ones to a base address register and
2239 ** reading from the registers. By scanning the returned value from the least-significant bit of the base
2240 ** address registers upwards, the programmer can determine the required address space size. The
2241 ** binary-weighted value of the first non-zero bit found indicates the required amount of space.
2242 ** Table 105 describes the relationship between the values read back and the byte sizes the base
2243 ** address register requires.
2244 ** As an example, assume that FFFF.FFFFH is written to the ATU Inbound Base Address Register 0
2245 ** (IABAR0) and the value read back is FFF0.0008H. Bit zero is a zero, so the device requires
2246 ** memory address space. Bit three is one, so the memory does supports prefetching. Scanning
2247 ** upwards starting at bit four, bit twenty is the first one bit found. The binary-weighted value of this
2248 ** bit is 1,048,576, indicated that the device requires 1 Mbyte of memory space.
2249 ** The ATU Base Address Registers and the Expansion ROM Base Address Register use their
2250 ** associated limit registers to enable which bits within the base address register are read/write and
2251 ** which bits are read only (0). This allows the programming of these registers in a manner similar to
2252 ** other PCI devices even though the limit is variable.
2253 ** Table 105. Memory Block Size Read Response
2254 ** Response After Writing all 1s
2255 ** to the Base Address Register
2258 ** Response After Writing all 1s
2259 ** to the Base Address Register
2262 ** FFFFFFF0H 16 FFF00000H 1 M
2263 ** FFFFFFE0H 32 FFE00000H 2 M
2264 ** FFFFFFC0H 64 FFC00000H 4 M
2265 ** FFFFFF80H 128 FF800000H 8 M
2266 ** FFFFFF00H 256 FF000000H 16 M
2267 ** FFFFFE00H 512 FE000000H 32 M
2268 ** FFFFFC00H 1K FC000000H 64 M
2269 ** FFFFF800H 2K F8000000H 128 M
2270 ** FFFFF000H 4K F0000000H 256 M
2271 ** FFFFE000H 8K E0000000H 512 M
2272 ** FFFFC000H 16K C0000000H 1 G
2273 ** FFFF8000H 32K 80000000H 2 G
2286 ***************************************************************************************
2292 ***********************************************************************************
2293 ** ATU Interrupt Line Register - ATUILR
2294 ** -----------------------------------------------------------------
2295 ** Bit Default Description
2296 ** 07:00 FFH Interrupt Assigned - system-assigned value identifies which system interrupt controller¡¦s interrupt
2297 ** request line connects to the device's PCI interrupt request lines
2298 ** (as specified in the interrupt pin register).
2299 ** A value of FFH signifies ¡§no connection¡¨ or ¡§unknown¡¨.
2300 ***********************************************************************************
2302 #define ARCMSR_ATU_INTERRUPT_LINE_REG 0x3C /*byte*/
2304 ***********************************************************************************
2305 ** ATU Interrupt Pin Register - ATUIPR
2306 ** -----------------------------------------------------------------
2307 ** Bit Default Description
2308 ** 07:00 01H Interrupt Used - A value of 01H signifies that the ATU interface unit uses INTA# as the interrupt pin.
2309 ***********************************************************************************
2311 #define ARCMSR_ATU_INTERRUPT_PIN_REG 0x3D /*byte*/
2313 ***********************************************************************************
2314 ** ATU Minimum Grant Register - ATUMGNT
2315 ** -----------------------------------------------------------------
2316 ** Bit Default Description
2317 ** 07:00 80H This register specifies how long a burst period the device needs in increments of 8 PCI clocks.
2318 ***********************************************************************************
2320 #define ARCMSR_ATU_MINIMUM_GRANT_REG 0x3E /*byte*/
2322 ***********************************************************************************
2323 ** ATU Maximum Latency Register - ATUMLAT
2324 ** -----------------------------------------------------------------
2325 ** Bit Default Description
2326 ** 07:00 00H Specifies frequency (how often) the device needs to access the PCI bus
2327 ** in increments of 8 PCI clocks. A zero value indicates the device has no stringent requirement.
2328 ***********************************************************************************
2330 #define ARCMSR_ATU_MAXIMUM_LATENCY_REG 0x3F /*byte*/
2332 ***********************************************************************************
2333 ** Inbound Address Translation
2335 ** The ATU allows external PCI bus initiators to directly access the internal bus.
2336 ** These PCI bus initiators can read or write 80331 memory-mapped registers or 80331 local memory space.
2337 ** The process of inbound address translation involves two steps:
2338 ** 1. Address Detection.
2339 ** ¡E Determine when the 32-bit PCI address (64-bit PCI address during DACs) is
2340 ** within the address windows defined for the inbound ATU.
2341 ** ¡E Claim the PCI transaction with medium DEVSEL# timing in the conventional PCI
2342 ** mode and with Decode A DEVSEL# timing in the PCI-X mode.
2343 ** 2. Address Translation.
2344 ** ¡E Translate the 32-bit PCI address (lower 32-bit PCI address during DACs) to a 32-bit 80331 internal bus address.
2345 ** The ATU uses the following registers in inbound address window 0 translation:
2346 ** ¡E Inbound ATU Base Address Register 0
2347 ** ¡E Inbound ATU Limit Register 0
2348 ** ¡E Inbound ATU Translate Value Register 0
2349 ** The ATU uses the following registers in inbound address window 2 translation:
2350 ** ¡E Inbound ATU Base Address Register 2
2351 ** ¡E Inbound ATU Limit Register 2
2352 ** ¡E Inbound ATU Translate Value Register 2
2353 ** The ATU uses the following registers in inbound address window 3 translation:
2354 ** ¡E Inbound ATU Base Address Register 3
2355 ** ¡E Inbound ATU Limit Register 3
2356 ** ¡E Inbound ATU Translate Value Register 3
2357 ** Note: Inbound Address window 1 is not a translate window.
2358 ** Instead, window 1 may be used to allocate host memory for Private Devices.
2359 ** Inbound Address window 3 does not reside in the standard section of the configuration header (offsets 00H - 3CH),
2360 ** thus the host BIOS does not configure window 3.
2361 ** Window 3 is intended to be used as a special window into local memory for private PCI
2362 ** agents controlled by the 80331 in conjunction with the Private Memory Space of the bridge.
2363 ** PCI-to-PCI Bridge in 80331 or
2364 ** Inbound address detection is determined from the 32-bit PCI address,
2365 ** (64-bit PCI address during DACs) the base address register and the limit register.
2366 ** In the case of DACs none of the upper 32-bits of the address is masked during address comparison.
2368 ** The algorithm for detection is:
2370 ** Equation 1. Inbound Address Detection
2371 ** When (PCI_Address [31:0] & Limit_Register[31:0]) == (Base_Register[31:0] & PCI_Address [63:32]) == Base_Register[63:32] (for DACs only)
2372 ** the PCI Address is claimed by the Inbound ATU.
2374 ** The incoming 32-bit PCI address (lower 32-bits of the address in case of DACs) is bitwise ANDed
2375 ** with the associated inbound limit register.
2376 ** When the result matches the base register (and upper base address matches upper PCI address in case of DACs),
2377 ** the inbound PCI address is detected as being within the inbound translation window and is claimed by the ATU.
2379 ** Note: The first 4 Kbytes of the ATU inbound address translation window 0 are reserved for the Messaging Unit.
2380 ** Once the transaction is claimed, the address must be translated from a PCI address to a 32-bit
2381 ** internal bus address. In case of DACs upper 32-bits of the address is simply discarded and only the
2382 ** lower 32-bits are used during address translation.
2383 ** The algorithm is:
2386 ** Equation 2. Inbound Translation
2387 ** Intel I/O processor Internal Bus Address=(PCI_Address[31:0] & ~Limit_Register[31:0]) | ATU_Translate_Value_Register[31:0].
2389 ** The incoming 32-bit PCI address (lower 32-bits in case of DACs) is first bitwise ANDed with the
2390 ** bitwise inverse of the limit register. This result is bitwise ORed with the ATU Translate Value and
2391 ** the result is the internal bus address. This translation mechanism is used for all inbound memory
2392 ** read and write commands excluding inbound configuration read and writes.
2393 ** In the PCI mode for inbound memory transactions, the only burst order supported is Linear
2394 ** Incrementing. For any other burst order, the ATU signals a Disconnect after the first data phase.
2395 ** The PCI-X supports linear incrementing only, and hence above situation is not encountered in the PCI-X mode.
2398 ** Base_Register=3A00 0000H
2399 ** Limit_Register=FF80 0000H (8 Mbyte limit value)
2400 ** Value_Register=B100 0000H
2401 ** Inbound Translation Window ranges from 3A00 0000H to 3A7F FFFFH (8 Mbytes)
2403 ** Address Detection (32-bit address)
2405 ** PCI_Address & Limit_Register == Base_Register
2406 ** 3A45 012CH & FF80 0000H == 3A00 0000H
2408 ** ANS: PCI_Address is in the Inbound Translation Window
2409 ** Address Translation (to get internal bus address)
2411 ** IB_Address=(PCI_Address & ~Limit_Register) | Value_Reg
2412 ** IB_Address=(3A45 012CH & 007F FFFFH) | B100 0000H
2414 ** ANS:IB_Address=B145 012CH
2415 ***********************************************************************************
2421 ***********************************************************************************
2422 ** Inbound ATU Limit Register 0 - IALR0
2424 ** Inbound address translation for memory window 0 occurs for data transfers occurring from the PCI
2425 ** bus (originated from the PCI bus) to the 80331 internal bus. The address translation block converts
2426 ** PCI addresses to internal bus addresses.
2427 ** The 80331 translate value register¡¦s programmed value must be naturally aligned with the base
2428 ** address register¡¦s programmed value. The limit register is used as a mask; thus, the lower address
2429 ** bits programmed into the 80331 translate value register are invalid. Refer to the PCI Local Bus
2430 ** Specification, Revision 2.3 for additional information on programming base address registers.
2431 ** Bits 31 to 12 within the IALR0 have a direct effect on the IABAR0 register, bits 31 to 12, with a
2432 ** one to one correspondence. A value of 0 in a bit within the IALR0 makes the corresponding bit
2433 ** within the IABAR0 a read only bit which always returns 0. A value of 1 in a bit within the IALR0
2434 ** makes the corresponding bit within the IABAR0 read/write from PCI. Note that a consequence of
2435 ** this programming scheme is that unless a valid value exists within the IALR0, all writes to the
2436 ** IABAR0 has no effect since a value of all zeros within the IALR0 makes the IABAR0 a read only register.
2437 ** -----------------------------------------------------------------
2438 ** Bit Default Description
2439 ** 31:12 FF000H Inbound Translation Limit 0 - This readback value determines the memory block size required for
2440 ** inbound memory window 0 of the address translation unit. This defaults to an inbound window of 16MB.
2441 ** 11:00 000H Reserved
2442 ***********************************************************************************
2444 #define ARCMSR_INBOUND_ATU_LIMIT0_REG 0x40 /*dword 0x43,0x42,0x41,0x40*/
2446 ***********************************************************************************
2447 ** Inbound ATU Translate Value Register 0 - IATVR0
2449 ** The Inbound ATU Translate Value Register 0 (IATVR0) contains the internal bus address used to
2450 ** convert PCI bus addresses. The converted address is driven on the internal bus as a result of the
2451 ** inbound ATU address translation.
2452 ** -----------------------------------------------------------------
2453 ** Bit Default Description
2454 ** 31:12 FF000H Inbound ATU Translation Value 0 - This value is used to convert the PCI address to internal bus addresses.
2455 ** This value must be 64-bit aligned on the internal bus.
2456 ** The default address allows the ATU to access the internal 80331 memory-mapped registers.
2457 ** 11:00 000H Reserved
2458 ***********************************************************************************
2460 #define ARCMSR_INBOUND_ATU_TRANSLATE_VALUE0_REG 0x44 /*dword 0x47,0x46,0x45,0x44*/
2462 ***********************************************************************************
2463 ** Expansion ROM Limit Register - ERLR
2465 ** The Expansion ROM Limit Register (ERLR) defines the block size of addresses the ATU defines
2466 ** as Expansion ROM address space. The block size is programmed by writing a value into the ERLR.
2467 ** Bits 31 to 12 within the ERLR have a direct effect on the ERBAR register, bits 31 to 12, with a one
2468 ** to one correspondence. A value of 0 in a bit within the ERLR makes the corresponding bit within
2469 ** the ERBAR a read only bit which always returns 0. A value of 1 in a bit within the ERLR makes
2470 ** the corresponding bit within the ERBAR read/write from PCI.
2471 ** -----------------------------------------------------------------
2472 ** Bit Default Description
2473 ** 31:12 000000H Expansion ROM Limit - Block size of memory required for the Expansion ROM translation unit. Default
2474 ** value is 0, which indicates no Expansion ROM address space and all bits within the ERBAR are read only with a value of 0.
2475 ** 11:00 000H Reserved.
2476 ***********************************************************************************
2478 #define ARCMSR_EXPANSION_ROM_LIMIT_REG 0x48 /*dword 0x4B,0x4A,0x49,0x48*/
2480 ***********************************************************************************
2481 ** Expansion ROM Translate Value Register - ERTVR
2483 ** The Expansion ROM Translate Value Register contains the 80331 internal bus address which the
2484 ** ATU converts the PCI bus access. This address is driven on the internal bus as a result of the
2485 ** Expansion ROM address translation.
2486 ** -----------------------------------------------------------------
2487 ** Bit Default Description
2488 ** 31:12 00000H Expansion ROM Translation Value - Used to convert PCI addresses to 80331 internal bus addresses
2489 ** for Expansion ROM accesses. The Expansion ROM address translation value must be word aligned on the internal bus.
2490 ** 11:00 000H Reserved
2491 ***********************************************************************************
2493 #define ARCMSR_EXPANSION_ROM_TRANSLATE_VALUE_REG 0x4C /*dword 0x4F,0x4E,0x4D,0x4C*/
2495 ***********************************************************************************
2496 ** Inbound ATU Limit Register 1 - IALR1
2498 ** Bits 31 to 12 within the IALR1 have a direct effect on the IABAR1 register, bits 31 to 12, with a
2499 ** one to one correspondence. A value of 0 in a bit within the IALR1 makes the corresponding bit
2500 ** within the IABAR1 a read only bit which always returns 0. A value of 1 in a bit within the IALR1
2501 ** makes the corresponding bit within the IABAR1 read/write from PCI. Note that a consequence of
2502 ** this programming scheme is that unless a valid value exists within the IALR1, all writes to the
2503 ** IABAR1 has no effect since a value of all zeros within the IALR1 makes the IABAR1 a read only
2505 ** The inbound memory window 1 is used merely to allocate memory on the PCI bus. The ATU does
2506 ** not process any PCI bus transactions to this memory range.
2507 ** Warning: The ATU does not claim any PCI accesses that fall within the range defined by IABAR1,
2508 ** IAUBAR1, and IALR1.
2509 ** -----------------------------------------------------------------
2510 ** Bit Default Description
2511 ** 31:12 00000H Inbound Translation Limit 1 - This readback value determines the memory block size
2512 ** required for the ATUs memory window 1.
2513 ** 11:00 000H Reserved
2514 ***********************************************************************************
2516 #define ARCMSR_INBOUND_ATU_LIMIT1_REG 0x50 /*dword 0x53,0x52,0x51,0x50*/
2518 ***********************************************************************************
2519 ** Inbound ATU Limit Register 2 - IALR2
2521 ** Inbound address translation for memory window 2 occurs for data transfers occurring from the PCI
2522 ** bus (originated from the PCI bus) to the 80331 internal bus. The address translation block converts
2523 ** PCI addresses to internal bus addresses.
2524 ** The inbound translation base address for inbound window 2 is specified in Section 3.10.15. When
2525 ** determining block size requirements ¡X as described in Section 3.10.21 ¡X the translation limit
2526 ** register provides the block size requirements for the base address register. The remaining registers
2527 ** used for performing address translation are discussed in Section 3.2.1.1.
2528 ** The 80331 translate value register¡¦s programmed value must be naturally aligned with the base
2529 ** address register¡¦s programmed value. The limit register is used as a mask; thus, the lower address
2530 ** bits programmed into the 80331 translate value register are invalid. Refer to the PCI Local Bus
2531 ** Specification, Revision 2.3 for additional information on programming base address registers.
2532 ** Bits 31 to 12 within the IALR2 have a direct effect on the IABAR2 register, bits 31 to 12, with a
2533 ** one to one correspondence. A value of 0 in a bit within the IALR2 makes the corresponding bit
2534 ** within the IABAR2 a read only bit which always returns 0. A value of 1 in a bit within the IALR2
2535 ** makes the corresponding bit within the IABAR2 read/write from PCI. Note that a consequence of
2536 ** this programming scheme is that unless a valid value exists within the IALR2, all writes to the
2537 ** IABAR2 has no effect since a value of all zeros within the IALR2 makes the IABAR2 a read only
2539 ** -----------------------------------------------------------------
2540 ** Bit Default Description
2541 ** 31:12 00000H Inbound Translation Limit 2 - This readback value determines the memory block size
2542 ** required for the ATUs memory window 2.
2543 ** 11:00 000H Reserved
2544 ***********************************************************************************
2546 #define ARCMSR_INBOUND_ATU_LIMIT2_REG 0x54 /*dword 0x57,0x56,0x55,0x54*/
2548 ***********************************************************************************
2549 ** Inbound ATU Translate Value Register 2 - IATVR2
2551 ** The Inbound ATU Translate Value Register 2 (IATVR2) contains the internal bus address used to
2552 ** convert PCI bus addresses. The converted address is driven on the internal bus as a result of the
2553 ** inbound ATU address translation.
2554 ** -----------------------------------------------------------------
2555 ** Bit Default Description
2556 ** 31:12 00000H Inbound ATU Translation Value 2 - This value is used to convert the PCI address to internal bus addresses.
2557 ** This value must be 64-bit aligned on the internal bus.
2558 ** The default address allows the ATU to access the internal 80331 ** ** memory-mapped registers.
2559 ** 11:00 000H Reserved
2560 ***********************************************************************************
2562 #define ARCMSR_INBOUND_ATU_TRANSLATE_VALUE2_REG 0x58 /*dword 0x5B,0x5A,0x59,0x58*/
2564 ***********************************************************************************
2565 ** Outbound I/O Window Translate Value Register - OIOWTVR
2567 ** The Outbound I/O Window Translate Value Register (OIOWTVR) contains the PCI I/O address
2568 ** used to convert the internal bus access to a PCI address. This address is driven on the PCI bus as a
2569 ** result of the outbound ATU address translation.
2570 ** The I/O window is from 80331 internal bus address 9000 000H to 9000 FFFFH with the fixed
2571 ** length of 64 Kbytes.
2572 ** -----------------------------------------------------------------
2573 ** Bit Default Description
2574 ** 31:16 0000H Outbound I/O Window Translate Value - Used to convert internal bus addresses to PCI addresses.
2575 ** 15:00 0000H Reserved
2576 ***********************************************************************************
2578 #define ARCMSR_OUTBOUND_IO_WINDOW_TRANSLATE_VALUE_REG 0x5C /*dword 0x5F,0x5E,0x5D,0x5C*/
2580 ***********************************************************************************
2581 ** Outbound Memory Window Translate Value Register 0 -OMWTVR0
2583 ** The Outbound Memory Window Translate Value Register 0 (OMWTVR0) contains the PCI
2584 ** address used to convert 80331 internal bus addresses for outbound transactions. This address is
2585 ** driven on the PCI bus as a result of the outbound ATU address translation.
2586 ** The memory window is from internal bus address 8000 000H to 83FF FFFFH with the fixed length
2588 ** -----------------------------------------------------------------
2589 ** Bit Default Description
2590 ** 31:26 00H Outbound MW Translate Value - Used to convert 80331 internal bus addresses to PCI addresses.
2591 ** 25:02 00 0000H Reserved
2592 ** 01:00 00 2 Burst Order - This bit field shows the address sequence during a memory burst.
2593 ** Only linear incrementing mode is supported.
2594 ***********************************************************************************
2596 #define ARCMSR_OUTBOUND_MEMORY_WINDOW_TRANSLATE_VALUE0_REG 0x60 /*dword 0x63,0x62,0x61,0x60*/
2598 ***********************************************************************************
2599 ** Outbound Upper 32-bit Memory Window Translate Value Register 0 - OUMWTVR0
2601 ** The Outbound Upper 32-bit Memory Window Translate Value Register 0 (OUMWTVR0) defines
2602 ** the upper 32-bits of address used during a dual address cycle. This enables the outbound ATU to
2603 ** directly address anywhere within the 64-bit host address space. When this register is all-zero, then
2604 ** a SAC is generated on the PCI bus.
2605 ** The memory window is from internal bus address 8000 000H to 83FF FFFFH with the fixed
2606 ** length of 64 Mbytes.
2607 ** -----------------------------------------------------------------
2608 ** Bit Default Description
2609 ** 31:00 0000 0000H These bits define the upper 32-bits of address driven during the dual address cycle (DAC).
2610 ***********************************************************************************
2612 #define ARCMSR_OUTBOUND_UPPER32_MEMORY_WINDOW_TRANSLATE_VALUE0_REG 0x64 /*dword 0x67,0x66,0x65,0x64*/
2614 ***********************************************************************************
2615 ** Outbound Memory Window Translate Value Register 1 -OMWTVR1
2617 ** The Outbound Memory Window Translate Value Register 1 (OMWTVR1) contains the PCI
2618 ** address used to convert 80331 internal bus addresses for outbound transactions. This address is
2619 ** driven on the PCI bus as a result of the outbound ATU address translation.
2620 ** The memory window is from internal bus address 8400 000H to 87FF FFFFH with the fixed length
2622 ** -----------------------------------------------------------------
2623 ** Bit Default Description
2624 ** 31:26 00H Outbound MW Translate Value - Used to convert 80331 internal bus addresses to PCI addresses.
2625 ** 25:02 00 0000H Reserved
2626 ** 01:00 00 2 Burst Order - This bit field shows the address sequence during a memory burst.
2627 ** Only linear incrementing mode is supported.
2628 ***********************************************************************************
2630 #define ARCMSR_OUTBOUND_MEMORY_WINDOW_TRANSLATE_VALUE1_REG 0x68 /*dword 0x6B,0x6A,0x69,0x68*/
2632 ***********************************************************************************
2633 ** Outbound Upper 32-bit Memory Window Translate Value Register 1 - OUMWTVR1
2635 ** The Outbound Upper 32-bit Memory Window Translate Value Register 1 (OUMWTVR1) defines
2636 ** the upper 32-bits of address used during a dual address cycle. This enables the outbound ATU to
2637 ** directly address anywhere within the 64-bit host address space. When this register is all-zero, then
2638 ** a SAC is generated on the PCI bus.
2639 ** The memory window is from internal bus address 8400 000H to 87FF FFFFH with the fixed length
2641 ** -----------------------------------------------------------------
2642 ** Bit Default Description
2643 ** 31:00 0000 0000H These bits define the upper 32-bits of address driven during the dual address cycle (DAC).
2644 ***********************************************************************************
2646 #define ARCMSR_OUTBOUND_UPPER32_MEMORY_WINDOW_TRANSLATE_VALUE1_REG 0x6C /*dword 0x6F,0x6E,0x6D,0x6C*/
2648 ***********************************************************************************
2649 ** Outbound Upper 32-bit Direct Window Translate Value Register - OUDWTVR
2651 ** The Outbound Upper 32-bit Direct Window Translate Value Register (OUDWTVR) defines the
2652 ** upper 32-bits of address used during a dual address cycle for the transactions via Direct Addressing
2653 ** Window. This enables the outbound ATU to directly address anywhere within the 64-bit host
2654 ** address space. When this register is all-zero, then a SAC is generated on the PCI bus.
2655 ** -----------------------------------------------------------------
2656 ** Bit Default Description
2657 ** 31:00 0000 0000H These bits define the upper 32-bits of address driven during the dual address cycle (DAC).
2658 ***********************************************************************************
2660 #define ARCMSR_OUTBOUND_UPPER32_DIRECT_WINDOW_TRANSLATE_VALUE_REG 0x78 /*dword 0x7B,0x7A,0x79,0x78*/
2662 ***********************************************************************************
2663 ** ATU Configuration Register - ATUCR
2665 ** The ATU Configuration Register controls the outbound address translation for address translation
2666 ** unit. It also contains bits for Conventional PCI Delayed Read Command (DRC) aliasing, discard
2667 ** timer status, SERR# manual assertion, SERR# detection interrupt masking, and ATU BIST
2668 ** interrupt enabling.
2669 ** -----------------------------------------------------------------
2670 ** Bit Default Description
2671 ** 31:20 00H Reserved
2672 ** 19 0 2 ATU DRC Alias - when set, the ATU does not distinguish read commands when attempting to match a
2673 ** current PCI read transaction with read data enqueued within the DRC buffer. When clear, a current read
2674 ** transaction must have the exact same read command as the DRR for the ATU to deliver DRC data. Not
2675 ** applicable in the PCI-X mode.
2676 ** 18 0 2 Direct Addressing Upper 2Gbytes Translation Enable - When set,
2677 ** with Direct Addressing enabled (bit 7 of the ATUCR set),
2678 ** the ATU forwards internal bus cycles with an address between 0000.0040H and
2679 ** 7FFF.FFFFH to the PCI bus with bit 31 of the address set (8000.0000H - FFFF.FFFFH).
2680 ** When clear, no translation occurs.
2682 ** 16 0 2 SERR# Manual Assertion - when set, the ATU asserts SERR# for one clock on the PCI interface. Until
2683 ** cleared, SERR# may not be manually asserted again. Once cleared, operation proceeds as specified.
2684 ** 15 0 2 ATU Discard Timer Status - when set, one of the 4 discard timers within the ATU has expired and
2685 ** discarded the delayed completion transaction within the queue. When clear, no timer has expired.
2686 ** 14:10 00000 2 Reserved
2687 ** 09 0 2 SERR# Detected Interrupt Enable - When set, the Intel XScale core is signalled an HPI# interrupt
2688 ** when the ATU detects that SERR# was asserted. When clear,
2689 ** the Intel XScale core is not interrupted when SERR# is detected.
2690 ** 08 0 2 Direct Addressing Enable - Setting this bit enables direct outbound addressing through the ATU.
2691 ** Internal bus cycles with an address between 0000.0040H and 7FFF.FFFFH automatically forwards to
2692 ** the PCI bus with or without translation of address bit 31 based on the setting of bit 18 of
2694 ** 07:04 0000 2 Reserved
2695 ** 03 0 2 ATU BIST Interrupt Enable - When set, enables an interrupt to the Intel XScale core when the start
2696 ** BIST bit is set in the ATUBISTR register. This bit is also reflected as the BIST Capable bit 7
2697 ** in the ATUBISTR register.
2699 ** 01 0 2 Outbound ATU Enable - When set, enables the outbound address translation unit.
2700 ** When cleared, disables the outbound ATU.
2702 ***********************************************************************************
2704 #define ARCMSR_ATU_CONFIGURATION_REG 0x80 /*dword 0x83,0x82,0x81,0x80*/
2706 ***********************************************************************************
2707 ** PCI Configuration and Status Register - PCSR
2709 ** The PCI Configuration and Status Register has additional bits for controlling and monitoring
2710 ** various features of the PCI bus interface.
2711 ** -----------------------------------------------------------------
2712 ** Bit Default Description
2713 ** 31:19 0000H Reserved
2714 ** 18 0 2 Detected Address or Attribute Parity Error - set when a parity error is detected during either the address
2715 ** or attribute phase of a transaction on the PCI bus even when the ATUCMD register Parity Error
2716 ** Response bit is cleared. Set under the following conditions:
2717 ** ¡E Any Address or Attribute (PCI-X Only) Parity Error on the Bus (including one generated by the ATU).
2718 ** 17:16 Varies with
2725 ** PCI-X capability - These two bits define the mode of
2726 ** the PCI bus (conventional or PCI-X) as well as the
2727 ** operating frequency in the case of PCI-X mode.
2728 ** 00 - Conventional PCI mode
2732 ** As defined by the PCI-X Addendum to the PCI Local Bus Specification,
2733 ** Revision 1.0a, the operating
2734 ** mode is determined by an initialization pattern on the PCI bus during
2735 ** P_RST# assertion:
2736 ** DEVSEL# STOP# TRDY# Mode
2737 ** Deasserted Deasserted Deasserted Conventional
2738 ** Deasserted Deasserted Asserted PCI-X 66
2739 ** Deasserted Asserted Deasserted PCI-X 100
2740 ** Deasserted Asserted Asserted PCI-X 133
2741 ** All other patterns are reserved.
2743 ** Outbound Transaction Queue Busy:
2744 ** 0=Outbound Transaction Queue Empty
2745 ** 1=Outbound Transaction Queue Busy
2747 ** Inbound Transaction Queue Busy:
2748 ** 0=Inbound Transaction Queue Empty
2749 ** 1=Inbound Transaction Queue Busy
2751 ** 12 0 2 Discard Timer Value - This bit controls the time-out value
2752 ** for the four discard timers attached to the queues holding read data.
2753 ** A value of 0 indicates the time-out value is 2 15 clocks.
2754 ** A value of 1 indicates the time-out value is 2 10 clocks.
2761 ** Bus Operating at 66 MHz - When set, the interface has been initialized to function at 66 MHz in
2762 ** Conventional PCI mode by the assertion of M66EN during bus initialization.
2763 ** When clear, the interface
2764 ** has been initialized as a 33 MHz bus.
2765 ** NOTE: When PCSR bits 17:16 are not equal to zero, then this bit is meaningless since the 80331 is operating in PCI-X mode.
2772 ** PCI Bus 64-Bit Capable - When clear, the PCI bus interface has been
2773 ** configured as 64-bit capable by
2774 ** the assertion of REQ64# on the rising edge of P_RST#. When set,
2775 ** the PCI interface is configured as
2777 ** 07:06 00 2 Reserved.
2778 ** 05 0 2 Reset Internal Bus - This bit controls the reset of the Intel XScale core
2779 ** and all units on the internal
2780 ** bus. In addition to the internal bus initialization,
2781 ** this bit triggers the assertion of the M_RST# pin for
2782 ** initialization of registered DIMMs. When set:
2783 ** When operating in the conventional PCI mode:
2784 ** ¡E All current PCI transactions being mastered by the ATU completes,
2785 ** and the ATU master interfaces
2786 ** proceeds to an idle state. No additional transactions is mastered by these units
2787 ** until the internal bus reset is complete.
2788 ** ¡E All current transactions being slaved by the ATU on either the PCI bus
2789 ** or the internal bus
2790 ** completes, and the ATU target interfaces proceeds to an idle state.
2791 ** All future slave transactions master aborts,
2792 ** with the exception of the completion cycle for the transaction that set the Reset
2793 ** Internal Bus bit in the PCSR.
2794 ** ¡E When the value of the Core Processor Reset bit in the PCSR (upon P_RST# assertion)
2795 ** is set, the Intel XScale core is held in reset when the internal bus reset is complete.
2796 ** ¡E The ATU ignores configuration cycles, and they appears as master aborts for: 32
2797 ** Internal Bus clocks.
2798 ** ¡E The 80331 hardware clears this bit after the reset operation completes.
2799 ** When operating in the PCI-X mode:
2800 ** The ATU hardware responds the same as in Conventional PCI-X mode.
2801 ** However, this may create a problem in PCI-X mode for split requests in
2802 ** that there may still be an outstanding split completion that the
2803 ** ATU is either waiting to receive (Outbound Request) or initiate
2804 ** (Inbound Read Request). For a cleaner
2805 ** internal bus reset, host software can take the following steps prior
2806 ** to asserting Reset Internal bus:
2807 ** 1. Clear the Bus Master (bit 2 of the ATUCMD) and the Memory Enable (bit 1 of the ATUCMD) bits in
2808 ** the ATUCMD. This ensures that no new transactions, either outbound or inbound are enqueued.
2809 ** 2. Wait for both the Outbound (bit 15 of the PCSR) and Inbound Read (bit 14 of the PCSR) Transaction
2810 ** queue busy bits to be clear.
2811 ** 3. Set the Reset Internal Bus bit
2812 ** As a result, the ATU hardware resets the internal bus using the same logic as in conventional mode,
2813 ** however the user is now assured that the ATU no longer has any pending inbound or outbound split
2814 ** completion transactions.
2815 ** NOTE: Since the Reset Internal Bus bit is set using an inbound configuration cycle, the user is
2816 ** guaranteed that any prior configuration cycles have properly completed since there is only a one
2817 ** deep transaction queue for configuration transaction requests. The ATU sends the appropriate
2818 ** Split Write Completion Message to the Requester prior to the onset of Internal Bus Reset.
2819 ** 04 0 2 Bus Master Indicator Enable: Provides software control for the
2820 ** Bus Master Indicator signal P_BMI used
2821 ** for external RAIDIOS logic control of private devices. Only valid when operating with the bridge and
2822 ** central resource/arbiter disabled (BRG_EN =low, ARB_EN=low).
2823 ** 03 Varies with external state of PRIVDEV during
2825 ** Private Device Enable - This bit indicates the state of the reset strap which enables the private device
2826 ** control mechanism within the PCI-to-PCI Bridge SISR configuration register.
2827 ** 0=Private Device control Disabled - SISR register bits default to zero
2828 ** 1=Private Device control Enabled - SISR register bits default to one
2829 ** 02 Varies with external state of RETRY during P_RST#
2830 ** Configuration Cycle Retry - When this bit is set, the PCI interface of the 80331 responds to all
2831 ** configuration cycles with a Retry condition. When clear, the 80331 responds to the appropriate
2832 ** configuration cycles.
2833 ** The default condition for this bit is based on the external state of the RETRY pin at the rising edge of
2834 ** P_RST#. When the external state of the pin is high, the bit is set. When the external state of the pin is
2835 ** low, the bit is cleared.
2836 ** 01 Varies with external state of CORE_RST# during P_RST#
2837 ** Core Processor Reset - This bit is set to its default value by the hardware when either P_RST# is
2838 ** asserted or the Reset Internal Bus bit in PCSR is set. When this bit is set, the Intel XScale core is
2839 ** being held in reset. Software cannot set this bit. Software is required to clear this bit to deassert Intel
2840 ** XScale core reset.
2841 ** The default condition for this bit is based on the external state of the CORE_RST# pin at the rising edge
2842 ** of P_RST#. When the external state of the pin is low, the bit is set. When the external state of the pin is
2843 ** high, the bit is clear.
2844 ** 00 Varies with external state of PRIVMEM during P_RST#
2845 ** Private Memory Enable - This bit indicates the state of the reset strap which enables the private device
2846 ** control mechanism within the PCI-to-PCI Bridge SDER configuration register.
2847 ** 0=Private Memory control Disabled - SDER register bit 2 default to zero
2848 ** 1=Private Memory control Enabled - SDER register bits 2 default to one
2849 ***********************************************************************************
2851 #define ARCMSR_PCI_CONFIGURATION_STATUS_REG 0x84 /*dword 0x87,0x86,0x85,0x84*/
2853 ***********************************************************************************
2854 ** ATU Interrupt Status Register - ATUISR
2856 ** The ATU Interrupt Status Register is used to notify the core processor of the source of an ATU
2857 ** interrupt. In addition, this register is written to clear the source of the interrupt to the interrupt unit
2858 ** of the 80331. All bits in this register are Read/Clear.
2859 ** Bits 4:0 are a direct reflection of bits 14:11 and bit 8 (respectively) of the ATU Status Register
2860 ** (these bits are set at the same time by hardware but need to be cleared independently). Bit 7 is set
2861 ** by an error associated with the internal bus of the 80331. Bit 8 is for software BIST. The
2862 ** conditions that result in an ATU interrupt are cleared by writing a 1 to the appropriate bits in this
2864 ** Note: Bits 4:0, and bits 15 and 13:7 can result in an interrupt being driven to the Intel XScale core.
2865 ** -----------------------------------------------------------------
2866 ** Bit Default Description
2867 ** 31:18 0000H Reserved
2868 ** 17 0 2 VPD Address Register Updated - This bit is set when a PCI bus configuration write occurs to the VPDAR
2869 ** register. Configuration register writes to the VPDAR does NOT result in bit 15 also being set. When set,
2870 ** this bit results in the assertion of the ATU Configure Register Write Interrupt.
2872 ** 15 0 2 ATU Configuration Write - This bit is set when a PCI bus configuration write occurs to any ATU register.
2873 ** When set, this bit results in the assertion of the ATU Configure Register Write Interrupt.
2874 ** 14 0 2 ATU Inbound Memory Window 1 Base Updated - This bit is set when a PCI bus configuration write
2875 ** occurs to either the IABAR1 register or the IAUBAR1 register. Configuration register writes to these
2876 ** registers deos NOT result in bit 15 also being set. When set, this bit results in the assertion of the ATU
2877 ** Configure Register Write Interrupt.
2878 ** 13 0 2 Initiated Split Completion Error Message - This bit is set when the device initiates a Split Completion
2879 ** Message on the PCI Bus with the Split Completion Error attribute bit set.
2880 ** 12 0 2 Received Split Completion Error Message - This bit is set when the device receives a Split Completion
2881 ** Message from the PCI Bus with the Split Completion Error attribute bit set.
2882 ** 11 0 2 Power State Transition - When the Power State Field of the ATU Power Management Control/Status
2883 ** Register is written to transition the ATU function Power State from D0 to D3, D0 to D1, or D3 to D0 and
2884 ** the ATU Power State Transition Interrupt mask bit is cleared, this bit is set.
2885 ** 10 0 2 P_SERR# Asserted - set when P_SERR# is asserted on the PCI bus by the ATU.
2886 ** 09 0 2 Detected Parity Error - set when a parity error is detected on the PCI bus even when the ATUCMD
2887 ** register¡¦s Parity Error Response bit is cleared. Set under the following conditions:
2888 ** ¡E Write Data Parity Error when the ATU is a target (inbound write).
2889 ** ¡E Read Data Parity Error when the ATU is an initiator (outbound read).
2890 ** ¡E Any Address or Attribute (PCI-X Only) Parity Error on the Bus.
2891 ** 08 0 2 ATU BIST Interrupt - When set, generates the ATU BIST Start Interrupt and indicates the host processor
2892 ** has set the Start BIST bit (ATUBISTR register bit 6), when the ATU BIST interrupt is enabled (ATUCR
2893 ** register bit 3). The Intel XScale core can initiate the software BIST and store the result in ATUBISTR
2894 ** register bits 3:0.
2895 ** Configuration register writes to the ATUBISTR does NOT result in bit 15 also being set or the assertion
2896 ** of the ATU Configure Register Write Interrupt.
2897 ** 07 0 2 Internal Bus Master Abort - set when a transaction initiated by the ATU internal bus initiator interface ends in a Master-abort.
2898 ** 06:05 00 2 Reserved.
2899 ** 04 0 2 P_SERR# Detected - set when P_SERR# is detected on the PCI bus by the ATU.
2900 ** 03 0 2 PCI Master Abort - set when a transaction initiated by the ATU PCI initiator interface ends in a Master-abort.
2901 ** 02 0 2 PCI Target Abort (master) - set when a transaction initiated by the ATU PCI master interface ends in a Target-abort.
2902 ** 01 0 2 PCI Target Abort (target) - set when the ATU interface, acting as a target, terminates the transaction on the PCI bus with a target abort.
2903 ** 00 0 2 PCI Master Parity Error - Master Parity Error - The ATU interface sets this bit under the following
2905 ** ¡E The ATU asserted PERR# itself or the ATU observed PERR# asserted.
2906 ** ¡E And the ATU acted as the requester for the operation in which the error occurred.
2907 ** ¡E And the ATUCMD register¡¦s Parity Error Response bit is set
2908 ** ¡E Or (PCI-X Mode Only) the ATU received a Write Data Parity Error Message
2909 ** ¡E And the ATUCMD register¡¦s Parity Error Response bit is set
2910 ***********************************************************************************
2912 #define ARCMSR_ATU_INTERRUPT_STATUS_REG 0x88 /*dword 0x8B,0x8A,0x89,0x88*/
2914 ***********************************************************************************
2915 ** ATU Interrupt Mask Register - ATUIMR
2917 ** The ATU Interrupt Mask Register contains the control bit to enable and disable interrupts
2918 ** generated by the ATU.
2919 ** -----------------------------------------------------------------
2920 ** Bit Default Description
2921 ** 31:15 0 0000H Reserved
2922 ** 14 0 2 VPD Address Register Updated Mask - Controls the setting of bit 17 of the ATUISR and generation of the
2923 ** ATU Configuration Register Write interrupt when a PCI bus write occurs to the VPDAR register.
2927 ** 12 0 2 Configuration Register Write Mask - Controls the setting of bit 15 of the ATUISR and generation of the
2928 ** ATU Configuration Register Write interrupt when a PCI bus write occurs to any ATU configuration register
2929 ** except those covered by mask bit 11 and bit 14 of this register, and ATU BIST enable bit 3 of the ATUCR.
2932 ** 11 1 2 ATU Inbound Memory Window 1 Base Updated Mask - Controls the setting of bit 14 of the ATUISR and
2933 ** generation of the ATU Configuration Register Write interrupt when a PCI bus write occurs to either the
2934 ** IABAR1 register or the IAUBAR1 register.
2937 ** 10 0 2 Initiated Split Completion Error Message Interrupt Mask - Controls the setting of bit 13 of the ATUISR and
2938 ** generation of the ATU Error interrupt when the ATU initiates a Split Completion Error Message.
2941 ** 09 0 2 Received Split Completion Error Message Interrupt Mask- Controls the setting of bit 12 of the ATUISR
2942 ** and generation of the ATU Error interrupt when a Split Completion Error Message results in bit 29 of the
2943 ** PCIXSR being set.
2946 ** 08 1 2 Power State Transition Interrupt Mask - Controls the setting of bit 12 of the ATUISR and generation of the
2947 ** ATU Error interrupt when ATU Power Management Control/Status Register is written to transition the
2948 ** ATU Function Power State from D0 to D3, D0 to D1, D1 to D3 or D3 to D0.
2951 ** 07 0 2 ATU Detected Parity Error Interrupt Mask - Controls the setting of bit 9 of the ATUISR and generation of
2952 ** the ATU Error interrupt when a parity error detected on the PCI bus that sets bit 15 of the ATUSR.
2955 ** 06 0 2 ATU SERR# Asserted Interrupt Mask - Controls the setting of bit 10 of the ATUISR and generation of the
2956 ** ATU Error interrupt when SERR# is asserted on the PCI interface resulting in bit 14 of the ATUSR being set.
2959 ** NOTE: This bit is specific to the ATU asserting SERR# and not detecting SERR# from another master.
2960 ** 05 0 2 ATU PCI Master Abort Interrupt Mask - Controls the setting of bit 3 of the ATUISR and generation of the
2961 ** ATU Error interrupt when a master abort error resulting in bit 13 of the ATUSR being set.
2964 ** 04 0 2 ATU PCI Target Abort (Master) Interrupt Mask- Controls the setting of bit 12 of the ATUISR and ATU Error
2965 ** generation of the interrupt when a target abort error resulting in bit 12 of the ATUSR being set
2968 ** 03 0 2 ATU PCI Target Abort (Target) Interrupt Mask- Controls the setting of bit 1 of the ATUISR and generation
2969 ** of the ATU Error interrupt when a target abort error resulting in bit 11 of the ATUSR being set.
2972 ** 02 0 2 ATU PCI Master Parity Error Interrupt Mask - Controls the setting of bit 0 of the ATUISR and generation
2973 ** of the ATU Error interrupt when a parity error resulting in bit 8 of the ATUSR being set.
2976 ** 01 0 2 ATU Inbound Error SERR# Enable - Controls when the ATU asserts (when enabled through the
2977 ** ATUCMD) SERR# on the PCI interface in response to a master abort on the internal bus during an
2978 ** inbound write transaction.
2979 ** 0=SERR# Not Asserted due to error
2980 ** 1=SERR# Asserted due to error
2981 ** 00 0 2 ATU ECC Target Abort Enable - Controls the ATU response on the PCI interface to a target abort (ECC
2982 ** error) from the memory controller on the internal bus. In conventional mode, this action only occurs
2983 ** during an inbound read transaction where the data phase that was target aborted on the internal bus is
2984 ** actually requested from the inbound read queue.
2985 ** 0=Disconnect with data
2986 ** (the data being up to 64 bits of 1¡¦s)
2988 ** NOTE: In PCI-X Mode, The ATU initiates a Split Completion Error Message (with message class=2h -
2989 ** completer error and message index=81h - 80331 internal bus target abort) on the PCI bus,
2990 ** independent of the setting of this bit.
2991 ***********************************************************************************
2993 #define ARCMSR_ATU_INTERRUPT_MASK_REG 0x8C /*dword 0x8F,0x8E,0x8D,0x8C*/
2995 ***********************************************************************************
2996 ** Inbound ATU Base Address Register 3 - IABAR3
2998 ** . The Inbound ATU Base Address Register 3 (IABAR3) together with the Inbound ATU Upper Base Address Register 3 (IAUBAR3) defines the block
2999 ** of memory addresses where the inbound translation window 3 begins.
3000 ** . The inbound ATU decodes and forwards the bus request to the 80331 internal bus with a translated address to map into 80331 local memory.
3001 ** . The IABAR3 and IAUBAR3 define the base address and describes the required memory block size.
3002 ** . Bits 31 through 12 of the IABAR3 is either read/write bits or read only with a value of 0 depending on the value located within the IALR3.
3003 ** The programmed value within the base address register must comply with the PCI programming requirements for address alignment.
3005 ** Since IABAR3 does not appear in the standard PCI configuration header space (offsets 00H - 3CH),
3006 ** IABAR3 is not configured by the host during normal system initialization.
3008 ** When a non-zero value is not written to IALR3,
3009 ** the user should not set either the Prefetchable Indicator
3010 ** or the Type Indicator for 64 bit addressability.
3011 ** This is the default for IABAR3.
3012 ** Assuming a non-zero value is written to IALR3,
3013 ** the user may set the Prefetchable Indicator
3014 ** or the Type Indicator:
3015 ** a. Since non prefetchable memory windows can never be placed above the 4 Gbyte address boundary,
3016 ** when the Prefetchable Indicator is not set,
3017 ** the user should also leave the Type Indicator set for 32 bit addressability.
3018 ** This is the default for IABAR3.
3019 ** b. when the Prefetchable Indicator is set,
3020 ** the user should also set the Type Indicator for 64 bit addressability.
3021 ** -----------------------------------------------------------------
3022 ** Bit Default Description
3023 ** 31:12 00000H Translation Base Address 3 - These bits define the actual location
3024 ** the translation function is to respond to when addressed from the PCI bus.
3025 ** 11:04 00H Reserved.
3026 ** 03 0 2 Prefetchable Indicator - When set, defines the memory space as prefetchable.
3027 ** 02:01 00 2 Type Indicator - Defines the width of the addressability for this memory window:
3028 ** 00 - Memory Window is locatable anywhere in 32 bit address space
3029 ** 10 - Memory Window is locatable anywhere in 64 bit address space
3030 ** 00 0 2 Memory Space Indicator - This bit field describes memory or I/O space base address.
3031 ** The ATU does not occupy I/O space,
3032 ** thus this bit must be zero.
3033 ***********************************************************************************
3035 #define ARCMSR_INBOUND_ATU_BASE_ADDRESS3_REG 0x90 /*dword 0x93,0x92,0x91,0x90*/
3037 ***********************************************************************************
3038 ** Inbound ATU Upper Base Address Register 3 - IAUBAR3
3040 ** This register contains the upper base address when decoding PCI addresses beyond 4 GBytes.
3041 ** Together with the Translation Base Address this register defines the actual location
3042 ** the translation function is to respond to when addressed from the PCI bus for addresses > 4GBytes (for DACs).
3043 ** The programmed value within the base address register must comply with the PCI programming
3044 ** requirements for address alignment.
3046 ** When the Type indicator of IABAR3 is set to indicate 32 bit addressability,
3047 ** the IAUBAR3 register attributes are read-only.
3048 ** This is the default for IABAR3.
3049 ** -----------------------------------------------------------------
3050 ** Bit Default Description
3051 ** 31:0 00000H Translation Upper Base Address 3 - Together with the Translation Base Address 3 these bits define
3052 ** the actual location the translation function is to respond to when addressed from the PCI bus for addresses > 4GBytes.
3053 ***********************************************************************************
3055 #define ARCMSR_INBOUND_ATU_UPPER_BASE_ADDRESS3_REG 0x94 /*dword 0x97,0x96,0x95,0x94*/
3057 ***********************************************************************************
3058 ** Inbound ATU Limit Register 3 - IALR3
3060 ** Inbound address translation for memory window 3 occurs for data transfers occurring from the PCI
3061 ** bus (originated from the PCI bus) to the 80331 internal bus. The address translation block converts
3062 ** PCI addresses to internal bus addresses.
3063 ** The inbound translation base address for inbound window 3 is specified in Section 3.10.15. When
3064 ** determining block size requirements ¡X as described in Section 3.10.21 ¡X the translation limit
3065 ** register provides the block size requirements for the base address register. The remaining registers
3066 ** used for performing address translation are discussed in Section 3.2.1.1.
3067 ** The 80331 translate value register¡¦s programmed value must be naturally aligned with the base
3068 ** address register¡¦s programmed value. The limit register is used as a mask; thus, the lower address
3069 ** bits programmed into the 80331 translate value register are invalid. Refer to the PCI Local Bus
3070 ** Specification, Revision 2.3 for additional information on programming base address registers.
3071 ** Bits 31 to 12 within the IALR3 have a direct effect on the IABAR3 register, bits 31 to 12, with a
3072 ** one to one correspondence. A value of 0 in a bit within the IALR3 makes the corresponding bit
3073 ** within the IABAR3 a read only bit which always returns 0. A value of 1 in a bit within the IALR3
3074 ** makes the corresponding bit within the IABAR3 read/write from PCI. Note that a consequence of
3075 ** this programming scheme is that unless a valid value exists within the IALR3, all writes to the
3076 ** IABAR3 has no effect since a value of all zeros within the IALR3 makes the IABAR3 a read only
3078 ** -----------------------------------------------------------------
3079 ** Bit Default Description
3080 ** 31:12 00000H Inbound Translation Limit 3 - This readback value determines the memory block size required
3081 ** for the ATUs memory window 3.
3082 ** 11:00 000H Reserved
3083 ***********************************************************************************
3085 #define ARCMSR_INBOUND_ATU_LIMIT3_REG 0x98 /*dword 0x9B,0x9A,0x99,0x98*/
3087 ***********************************************************************************
3088 ** Inbound ATU Translate Value Register 3 - IATVR3
3090 ** The Inbound ATU Translate Value Register 3 (IATVR3) contains the internal bus address used to
3091 ** convert PCI bus addresses. The converted address is driven on the internal bus as a result of the
3092 ** inbound ATU address translation.
3093 ** -----------------------------------------------------------------
3094 ** Bit Default Description
3095 ** 31:12 00000H Inbound ATU Translation Value 3 - This value is used to convert the PCI address to internal bus addresses.
3096 ** This value must be 64-bit aligned on the internal bus. The default address allows the ATU to
3097 ** access the internal 80331 memory-mapped registers.
3098 ** 11:00 000H Reserved
3099 ***********************************************************************************
3101 #define ARCMSR_INBOUND_ATU_TRANSLATE_VALUE3_REG 0x9C /*dword 0x9F,0x9E,0x9D,0x9C*/
3103 ***********************************************************************************
3104 ** Outbound Configuration Cycle Address Register - OCCAR
3106 ** The Outbound Configuration Cycle Address Register is used to hold the 32-bit PCI configuration
3107 ** cycle address. The Intel XScale core writes the PCI configuration cycles address which then
3108 ** enables the outbound configuration read or write. The Intel XScale core then performs a read or
3109 ** write to the Outbound Configuration Cycle Data Register to initiate the configuration cycle on the
3111 ** Note: Bits 15:11 of the configuration cycle address for Type 0 configuration cycles are defined differently
3112 ** for Conventional versus PCI-X modes. When 80331 software programs the OCCAR to initiate a
3113 ** Type 0 configuration cycle, the OCCAR should always be loaded based on the PCI-X definition for
3114 ** the Type 0 configuration cycle address. When operating in Conventional mode, the 80331 clears
3115 ** bits 15:11 of the OCCAR prior to initiating an outbound Type 0 configuration cycle. See the PCI-X
3116 ** Addendum to the PCI Local Bus Specification, Revision 1.0a for details on the two formats.
3117 ** -----------------------------------------------------------------
3118 ** Bit Default Description
3119 ** 31:00 0000 0000H Configuration Cycle Address - These bits define the 32-bit PCI address used during an outbound
3120 ** configuration read or write cycle.
3121 ***********************************************************************************
3123 #define ARCMSR_OUTBOUND_CONFIGURATION_CYCLE_ADDRESS_REG 0xA4 /*dword 0xA7,0xA6,0xA5,0xA4*/
3125 ***********************************************************************************
3126 ** Outbound Configuration Cycle Data Register - OCCDR
3128 ** The Outbound Configuration Cycle Data Register is used to initiate a configuration read or write
3129 ** on the PCI bus. The register is logical rather than physical meaning that it is an address not a
3130 ** register. The Intel XScale core reads or writes the data registers memory-mapped address to
3131 ** initiate the configuration cycle on the PCI bus with the address found in the OCCAR. For a
3132 ** configuration write, the data is latched from the internal bus and forwarded directly to the OWQ.
3133 ** For a read, the data is returned directly from the ORQ to the Intel XScale core and is never
3134 ** actually entered into the data register (which does not physically exist).
3135 ** The OCCDR is only visible from 80331 internal bus address space and appears as a reserved value
3136 ** within the ATU configuration space.
3137 ** -----------------------------------------------------------------
3138 ** Bit Default Description
3139 ** 31:00 0000 0000H Configuration Cycle Data - These bits define the data used during an outbound configuration read
3141 ***********************************************************************************
3143 #define ARCMSR_OUTBOUND_CONFIGURATION_CYCLE_DATA_REG 0xAC /*dword 0xAF,0xAE,0xAD,0xAC*/
3145 ***********************************************************************************
3146 ** VPD Capability Identifier Register - VPD_CAPID
3148 ** The Capability Identifier Register bits adhere to the definitions in the PCI Local Bus Specification,
3149 ** Revision 2.3. This register in the PCI Extended Capability header identifies the type of Extended
3150 ** Capability contained in that header. In the case of the 80331, this is the VPD extended capability
3151 ** with an ID of 03H as defined by the PCI Local Bus Specification, Revision 2.3.
3152 ** -----------------------------------------------------------------
3153 ** Bit Default Description
3154 ** 07:00 03H Cap_Id - This field with its¡¦ 03H value identifies this item in the linked list of Extended Capability
3155 ** Headers as being the VPD capability registers.
3156 ***********************************************************************************
3158 #define ARCMSR_VPD_CAPABILITY_IDENTIFIER_REG 0xB8 /*byte*/
3160 ***********************************************************************************
3161 ** VPD Next Item Pointer Register - VPD_NXTP
3163 ** The Next Item Pointer Register bits adhere to the definitions in the PCI Local Bus Specification,
3164 ** Revision 2.3. This register describes the location of the next item in the function¡¦s capability list.
3165 ** For the 80331, this the final capability list, and hence, this register is set to 00H.
3166 ** -----------------------------------------------------------------
3167 ** Bit Default Description
3168 ** 07:00 00H Next_ Item_ Pointer - This field provides an offset into the function¡¦s configuration space pointing to the
3169 ** next item in the function¡¦s capability list. Since the VPD capabilities are the last in the linked list of
3170 ** extended capabilities in the 80331, the register is set to 00H.
3171 ***********************************************************************************
3173 #define ARCMSR_VPD_NEXT_ITEM_PTR_REG 0xB9 /*byte*/
3175 ***********************************************************************************
3176 ** VPD Address Register - VPD_AR
3178 ** The VPD Address register (VPDAR) contains the DWORD-aligned byte address of the VPD to be
3179 ** accessed. The register is read/write and the initial value at power-up is indeterminate.
3180 ** A PCI Configuration Write to the VPDAR interrupts the Intel XScale core. Software can use
3181 ** the Flag setting to determine whether the configuration write was intended to initiate a read or
3182 ** write of the VPD through the VPD Data Register.
3183 ** -----------------------------------------------------------------
3184 ** Bit Default Description
3185 ** 15 0 2 Flag - A flag is used to indicate when a transfer of data between the VPD Data Register and the storage
3186 ** component has completed. Please see Section 3.9, ¡§Vital Product Data¡¨ on page 201 for more details on
3187 ** how the 80331 handles the data transfer.
3188 ** 14:0 0000H VPD Address - This register is written to set the DWORD-aligned byte address used to read or write
3189 ** Vital Product Data from the VPD storage component.
3190 ***********************************************************************************
3192 #define ARCMSR_VPD_ADDRESS_REG 0xBA /*word 0xBB,0xBA*/
3194 ***********************************************************************************
3195 ** VPD Data Register - VPD_DR
3197 ** This register is used to transfer data between the 80331 and the VPD storage component.
3198 ** -----------------------------------------------------------------
3199 ** Bit Default Description
3200 ** 31:00 0000H VPD Data - Four bytes are always read or written through this register to/from the VPD storage component.
3201 ***********************************************************************************
3203 #define ARCMSR_VPD_DATA_REG 0xBC /*dword 0xBF,0xBE,0xBD,0xBC*/
3205 ***********************************************************************************
3206 ** Power Management Capability Identifier Register -PM_CAPID
3208 ** The Capability Identifier Register bits adhere to the definitions in the PCI Local Bus Specification,
3209 ** Revision 2.3. This register in the PCI Extended Capability header identifies the type of Extended
3210 ** Capability contained in that header. In the case of the 80331, this is the PCI Bus Power
3211 ** Management extended capability with an ID of 01H as defined by the PCI Bus Power Management
3212 ** Interface Specification, Revision 1.1.
3213 ** -----------------------------------------------------------------
3214 ** Bit Default Description
3215 ** 07:00 01H Cap_Id - This field with its¡¦ 01H value identifies this item in the linked list of Extended Capability
3216 ** Headers as being the PCI Power Management Registers.
3217 ***********************************************************************************
3219 #define ARCMSR_POWER_MANAGEMENT_CAPABILITY_IDENTIFIER_REG 0xC0 /*byte*/
3221 ***********************************************************************************
3222 ** Power Management Next Item Pointer Register - PM_NXTP
3224 ** The Next Item Pointer Register bits adhere to the definitions in the PCI Local Bus Specification,
3225 ** Revision 2.3. This register describes the location of the next item in the function¡¦s capability list.
3226 ** For the 80331, the next capability (MSI capability list) is located at off-set D0H.
3227 ** -----------------------------------------------------------------
3228 ** Bit Default Description
3229 ** 07:00 D0H Next_ Item_ Pointer - This field provides an offset into the function¡¦s configuration space pointing to the
3230 ** next item in the function¡¦s capability list which in the 80331 is the MSI extended capabilities header.
3231 ***********************************************************************************
3233 #define ARCMSR_POWER_NEXT_ITEM_PTR_REG 0xC1 /*byte*/
3235 ***********************************************************************************
3236 ** Power Management Capabilities Register - PM_CAP
3238 ** Power Management Capabilities bits adhere to the definitions in the PCI Bus Power Management
3239 ** Interface Specification, Revision 1.1. This register is a 16-bit read-only register which provides
3240 ** information on the capabilities of the ATU function related to power management.
3241 ** -----------------------------------------------------------------
3242 ** Bit Default Description
3243 ** 15:11 00000 2 PME_Support - This function is not capable of asserting the PME# signal in any state, since PME#
3244 ** is not supported by the 80331.
3245 ** 10 0 2 D2_Support - This bit is set to 0 2 indicating that the 80331 does not support the D2 Power Management State
3246 ** 9 1 2 D1_Support - This bit is set to 1 2 indicating that the 80331 supports the D1 Power Management State
3247 ** 8:6 000 2 Aux_Current - This field is set to 000 2 indicating that the 80331 has no current requirements for the
3248 ** 3.3Vaux signal as defined in the PCI Bus Power Management Interface Specification, Revision 1.1
3249 ** 5 0 2 DSI - This field is set to 0 2 meaning that this function requires a device specific initialization sequence
3250 ** following the transition to the D0 uninitialized state.
3252 ** 3 0 2 PME Clock - Since the 80331 does not support PME# signal generation this bit is cleared to 0 2 .
3253 ** 2:0 010 2 Version - Setting these bits to 010 2 means that this function complies with PCI Bus Power Management
3254 ** Interface Specification, Revision 1.1
3255 ***********************************************************************************
3257 #define ARCMSR_POWER_MANAGEMENT_CAPABILITY_REG 0xC2 /*word 0xC3,0xC2*/
3259 ***********************************************************************************
3260 ** Power Management Control/Status Register - PM_CSR
3262 ** Power Management Control/Status bits adhere to the definitions in the PCI Bus Power
3263 ** Management Interface Specification, Revision 1.1. This 16-bit register is the control and status
3264 ** interface for the power management extended capability.
3265 ** -----------------------------------------------------------------
3266 ** Bit Default Description
3267 ** 15 0 2 PME_Status - This function is not capable of asserting the PME# signal in any state, since PME## is not
3268 ** supported by the 80331.
3269 ** 14:9 00H Reserved
3270 ** 8 0 2 PME_En - This bit is hardwired to read-only 0 2 since this function does not support PME#
3271 ** generation from any power state.
3272 ** 7:2 000000 2 Reserved
3273 ** 1:0 00 2 Power State - This 2-bit field is used both to determine the current power state
3274 ** of a function and to set the function into a new power state. The definition of the values is:
3277 ** 10 2 - D2 (Unsupported)
3279 ** The 80331 supports only the D0 and D3 hot states.
3281 ***********************************************************************************
3283 #define ARCMSR_POWER_MANAGEMENT_CONTROL_STATUS_REG 0xC4 /*word 0xC5,0xC4*/
3285 ***********************************************************************************
3286 ** PCI-X Capability Identifier Register - PX_CAPID
3288 ** The Capability Identifier Register bits adhere to the definitions in the PCI Local Bus Specification,
3289 ** Revision 2.3. This register in the PCI Extended Capability header identifies the type of Extended
3290 ** Capability contained in that header. In the case of the 80331, this is the PCI-X extended capability with
3291 ** an ID of 07H as defined by the PCI-X Addendum to the PCI Local Bus Specification, Revision 1.0a.
3292 ** -----------------------------------------------------------------
3293 ** Bit Default Description
3294 ** 07:00 07H Cap_Id - This field with its¡¦ 07H value identifies this item in the linked list of Extended Capability
3295 ** Headers as being the PCI-X capability registers.
3296 ***********************************************************************************
3298 #define ARCMSR_PCIX_CAPABILITY_IDENTIFIER_REG 0xE0 /*byte*/
3300 ***********************************************************************************
3301 ** PCI-X Next Item Pointer Register - PX_NXTP
3303 ** The Next Item Pointer Register bits adhere to the definitions in the PCI Local Bus Specification,
3304 ** Revision 2.3. This register describes the location of the next item in the function¡¦s capability list.
3305 ** By default, the PCI-X capability is the last capabilities list for the 80331, thus this register defaults
3307 ** However, this register may be written to B8H prior to host configuration to include the VPD
3308 ** capability located at off-set B8H.
3309 ** Warning: Writing this register to any value other than 00H (default) or B8H is not supported and may
3310 ** produce unpredictable system behavior.
3311 ** In order to guarantee that this register is written prior to host configuration, the 80331 must be
3312 ** initialized at P_RST# assertion to Retry Type 0 configuration cycles (bit 2 of PCSR). Typically,
3313 ** the Intel XScale core would be enabled to boot immediately following P_RST# assertion in
3314 ** this case (bit 1 of PCSR), as well. Please see Table 125, ¡§PCI Configuration and Status Register -
3315 ** PCSR¡¨ on page 253 for more details on the 80331 initialization modes.
3316 ** -----------------------------------------------------------------
3317 ** Bit Default Description
3318 ** 07:00 00H Next_ Item_ Pointer - This field provides an offset into the function¡¦s configuration space pointing to the
3319 ** next item in the function¡¦s capability list. Since the PCI-X capabilities are the last in the linked list of
3320 ** extended capabilities in the 80331, the register is set to 00H.
3321 ** However, this field may be written prior to host configuration with B8H to extend the list to include the
3322 ** VPD extended capabilities header.
3323 ***********************************************************************************
3325 #define ARCMSR_PCIX_NEXT_ITEM_PTR_REG 0xE1 /*byte*/
3327 ***********************************************************************************
3328 ** PCI-X Command Register - PX_CMD
3330 ** This register controls various modes and features of ATU and Message Unit when operating in the
3332 ** -----------------------------------------------------------------
3333 ** Bit Default Description
3334 ** 15:7 000000000 2 Reserved.
3335 ** 6:4 011 2 Maximum Outstanding Split Transactions - This register sets the maximum number of Split Transactions
3336 ** the device is permitted to have outstanding at one time.
3337 ** Register Maximum Outstanding
3346 ** 3:2 00 2 Maximum Memory Read Byte Count - This register sets the maximum byte count the device uses when
3347 ** initiating a Sequence with one of the burst memory read commands.
3348 ** Register Maximum Byte Count
3354 ** Enable Relaxed Ordering - The 80331 does not set the relaxed ordering bit in the Requester Attributes
3356 ** 0 0 2 Data Parity Error Recovery Enable - The device driver sets this bit to enable the device to attempt to
3357 ** recover from data parity errors. When this bit is 0 and the device is in PCI-X mode, the device asserts
3358 ** SERR# (when enabled) whenever the Master Data Parity Error bit (Status register, bit 8) is set.
3359 ***********************************************************************************
3361 #define ARCMSR_PCIX_COMMAND_REG 0xE2 /*word 0xE3,0xE2*/
3363 ***********************************************************************************
3364 ** PCI-X Status Register - PX_SR
3366 ** This register identifies the capabilities and current operating mode of ATU, DMAs and Message
3367 ** Unit when operating in the PCI-X mode.
3368 ** -----------------------------------------------------------------
3369 ** Bit Default Description
3370 ** 31:30 00 2 Reserved
3371 ** 29 0 2 Received Split Completion Error Message - This bit is set when the device receives a Split Completion
3372 ** Message with the Split Completion Error attribute bit set. Once set, this bit remains set until software
3373 ** writes a 1 to this location.
3374 ** 0=no Split Completion error message received.
3375 ** 1=a Split Completion error message has been received.
3376 ** 28:26 001 2 Designed Maximum Cumulative Read Size (DMCRS) - The value of this register depends on the setting
3377 ** of the Maximum Memory Read Byte Count field of the PCIXCMD register:
3378 ** DMCRS Max ADQs Maximum Memory Read Byte Count Register Setting
3379 ** 1 16 512 (Default)
3383 ** 25:23 011 2 Designed Maximum Outstanding Split Transactions - The 80331 can have up to four outstanding split transactions.
3384 ** 22:21 01 2 Designed Maximum Memory Read Byte Count - The 80331 can generate memory reads with byte counts up
3386 ** 20 1 2 80331 is a complex device.
3387 ** 19 0 2 Unexpected Split Completion - This bit is set when an unexpected Split Completion with this device¡¦s
3388 ** Requester ID is received. Once set, this bit remains set until software writes a 1 to this location.
3389 ** 0=no unexpected Split Completion has been received.
3390 ** 1=an unexpected Split Completion has been received.
3391 ** 18 0 2 Split Completion Discarded - This bit is set when the device discards a Split Completion because the
3392 ** requester would not accept it. See Section 5.4.4 of the PCI-X Addendum to the PCI Local Bus
3393 ** Specification, Revision 1.0a for details. Once set, this bit remains set until software writes a 1 to this
3395 ** 0=no Split Completion has been discarded.
3396 ** 1=a Split Completion has been discarded.
3397 ** NOTE: The 80331 does not set this bit since there is no Inbound address responding to Inbound Read
3398 ** Requests with Split Responses (Memory or Register) that has ¡§read side effects.¡¨
3399 ** 17 1 2 80331 is a 133 MHz capable device.
3400 ** 16 1 2 or P_32BITPCI# 80331 with bridge enabled (BRG_EN=1) implements the ATU with a 64-bit interface on the secondary PCI bus,
3401 ** therefore this bit is always set.
3402 ** 80331 with no bridge and central resource disabled (BRG_EN=0, ARB_EN=0),
3403 ** use this bit to identify the add-in card to the system as 64-bit or 32-bit wide via a user-configurable strap (P_32BITPCI#).
3404 ** This strap, by default, identifies the add in card based on 80331 with bridge disabled
3405 ** as 64-bit unless the user attaches the appropriate pull-down resistor to the strap.
3406 ** 0=The bus is 32 bits wide.
3407 ** 1=The bus is 64 bits wide.
3408 ** 15:8 FFH Bus Number - This register is read for diagnostic purposes only. It indicates the number of the bus
3409 ** segment for the device containing this function. The function uses this number as part of its Requester
3410 ** ID and Completer ID. For all devices other than the source bridge, each time the function is addressed
3411 ** by a Configuration Write transaction, the function must update this register with the contents of AD[7::0]
3412 ** of the attribute phase of the Configuration Write, regardless of which register in the function is
3413 ** addressed by the transaction. The function is addressed by a Configuration Write transaction when all of
3414 ** the following are true:
3415 ** 1. The transaction uses a Configuration Write command.
3416 ** 2. IDSEL is asserted during the address phase.
3417 ** 3. AD[1::0] are 00b (Type 0 configuration transaction).
3418 ** 4. AD[10::08] of the configuration address contain the appropriate function number.
3419 ** 7:3 1FH Device Number - This register is read for diagnostic purposes only. It indicates the number of the device
3420 ** containing this function, i.e., the number in the Device Number field (AD[15::11]) of the address of a
3421 ** Type 0 configuration transaction that is assigned to the device containing this function by the connection
3422 ** of the system hardware. The system must assign a device number other than 00h (00h is reserved for
3423 ** the source bridge). The function uses this number as part of its Requester ID and Completer ID. Each
3424 ** time the function is addressed by a Configuration Write transaction, the device must update this register
3425 ** with the contents of AD[15::11] of the address phase of the Configuration Write, regardless of which
3426 ** register in the function is addressed by the transaction. The function is addressed by a Configuration
3427 ** Write transaction when all of the following are true:
3428 ** 1. The transaction uses a Configuration Write command.
3429 ** 2. IDSEL is asserted during the address phase.
3430 ** 3. AD[1::0] are 00b (Type 0 configuration transaction).
3431 ** 4. AD[10::08] of the configuration address contain the appropriate function number.
3432 ** 2:0 000 2 Function Number - This register is read for diagnostic purposes only. It indicates the number of this
3433 ** function; i.e., the number in the Function Number field (AD[10::08]) of the address of a Type 0
3434 ** configuration transaction to which this function responds. The function uses this number as part of its
3435 ** Requester ID and Completer ID.
3437 **************************************************************************
3439 #define ARCMSR_PCIX_STATUS_REG 0xE4 /*dword 0xE7,0xE6,0xE5,0xE4*/
3442 **************************************************************************
3443 ** Inbound Read Transaction
3444 ** ========================================================================
3445 ** An inbound read transaction is initiated by a PCI initiator and is targeted at either 80331 local
3446 ** memory or a 80331 memory-mapped register space. The read transaction is propagated through
3447 ** the inbound transaction queue (ITQ) and read data is returned through the inbound read queue
3449 ** When operating in the conventional PCI mode, all inbound read transactions are processed as
3450 ** delayed read transactions. When operating in the PCI-X mode, all inbound read transactions are
3451 ** processed as split transactions. The ATUs PCI interface claims the read transaction and forwards
3452 ** the read request through to the internal bus and returns the read data to the PCI bus. Data flow for
3453 ** an inbound read transaction on the PCI bus is summarized in the following statements:
3454 ** ¡E The ATU claims the PCI read transaction when the PCI address is within the inbound
3455 ** translation window defined by ATU Inbound Base Address Register (and Inbound Upper Base
3456 ** Address Register during DACs) and Inbound Limit Register.
3457 ** ¡E When operating in the conventional PCI mode, when the ITQ is currently holding transaction
3458 ** information from a previous delayed read, the current transaction information is compared to
3459 ** the previous transaction information (based on the setting of the DRC Alias bit in
3460 ** Section 3.10.39, ¡§ATU Configuration Register - ATUCR¡¨ on page 252). When there is a
3461 ** match and the data is in the IRQ, return the data to the master on the PCI bus. When there is a
3462 ** match and the data is not available, a Retry is signaled with no other action taken. When there
3463 ** is not a match and when the ITQ has less than eight entries, capture the transaction
3464 ** information, signal a Retry and initiate a delayed transaction. When there is not a match and
3465 ** when the ITQ is full, then signal a Retry with no other action taken.
3466 ** ¡X When an address parity error is detected, the address parity response defined in
3467 ** Section 3.7 is used.
3468 ** ¡E When operating in the conventional PCI mode, once read data is driven onto the PCI bus from
3469 ** the IRQ, it continues until one of the following is true:
3470 ** ¡X The initiator completes the PCI transaction. When there is data left unread in the IRQ, the
3472 ** ¡X An internal bus Target Abort was detected. In this case, the QWORD associated with the
3473 ** Target Abort is never entered into the IRQ, and therefore is never returned.
3474 ** ¡X Target Abort or a Disconnect with Data is returned in response to the Internal Bus Error.
3475 ** ¡X The IRQ becomes empty. In this case, the PCI interface signals a Disconnect with data to
3476 ** the initiator on the last data word available.
3477 ** ¡E When operating in the PCI-X mode, when ITQ is not full, the PCI address, attribute and
3478 ** command are latched into the available ITQ and a Split Response Termination is signalled to
3480 ** ¡E When operating in the PCI-X mode, when the transaction does not cross a 1024 byte aligned
3481 ** boundary, then the ATU waits until it receives the full byte count from the internal bus target
3482 ** before returning read data by generating the split completion transaction on the PCI-X bus.
3483 ** When the read requested crosses at least one 1024 byte boundary, then ATU completes the
3484 ** transfer by returning data in 1024 byte aligned chunks.
3485 ** ¡E When operating in the PCI-X mode, once a split completion transaction has started, it
3486 ** continues until one of the following is true:
3487 ** ¡X The requester (now the target) generates a Retry Termination, or a Disconnection at Next
3488 ** ADB (when the requester is a bridge)
3489 ** ¡X The byte count is satisfied.
3490 ** ¡X An internal bus Target Abort was detected. The ATU generates a Split Completion
3491 ** Message (message class=2h - completer error, and message index=81h - target abort) to
3492 ** inform the requester about the abnormal condition. The ITQ for this transaction is flushed.
3493 ** Refer to Section 3.7.1.
3494 ** ¡X An internal bus Master Abort was detected. The ATU generates a Split Completion
3495 ** Message (message class=2h - completer error, and message index=80h - Master abort) to
3496 ** inform the requester about the abnormal condition. The ITQ for this transaction is flushed.
3497 ** Refer to Section 3.7.1
3498 ** ¡E When operating in the conventional PCI mode, when the master inserts wait states on the PCI
3499 ** bus, the ATU PCI slave interface waits with no premature disconnects.
3500 ** ¡E When a data parity error occurs signified by PERR# asserted from the initiator, no action is
3501 ** taken by the target interface. Refer to Section 3.7.2.5.
3502 ** ¡E When operating in the conventional PCI mode, when the read on the internal bus is
3503 ** target-aborted, either a target-abort or a disconnect with data is signaled to the initiator. This is
3504 ** based on the ATU ECC Target Abort Enable bit (bit 0 of the ATUIMR for ATU). When set, a
3505 ** target abort is used, when clear, a disconnect is used.
3506 ** ¡E When operating in the PCI-X mode (with the exception of the MU queue ports at offsets 40h
3507 ** and 44h), when the transaction on the internal bus resulted in a target abort, the ATU generates
3508 ** a Split Completion Message (message class=2h - completer error, and message index=81h -
3509 ** internal bus target abort) to inform the requester about the abnormal condition. For the MU
3510 ** queue ports, the ATU returns either a target abort or a single data phase disconnect depending
3511 ** on the ATU ECC Target Abort Enable bit (bit 0 of the ATUIMR for ATU). The ITQ for this
3512 ** transaction is flushed. Refer to Section 3.7.1.
3513 ** ¡E When operating in the conventional PCI mode, when the transaction on the internal bus
3514 ** resulted in a master abort, the ATU returns a target abort to inform the requester about the
3515 ** abnormal condition. The ITQ for this transaction is flushed. Refer to Section 3.7.1
3516 ** ¡E When operating in the PCI-X mode, when the transaction on the internal bus resulted in a
3517 ** master abort, the ATU generates a Split Completion Message (message class=2h - completer
3518 ** error, and message index=80h - internal bus master abort) to inform the requester about the
3519 ** abnormal condition. The ITQ for this transaction is flushed. Refer to Section 3.7.1.
3520 ** ¡E When operating in the PCI-X mode, when the Split Completion transaction completes with
3521 ** either Master-Abort or Target-Abort, the requester is indicating a failure condition that
3522 ** prevents it from accepting the completion it requested. In this case, since the Split Request
3523 ** addresses a location that has no read side effects, the completer must discard the Split
3524 ** Completion and take no further action.
3525 ** The data flow for an inbound read transaction on the internal bus is summarized in the following
3527 ** ¡E The ATU internal bus master interface requests the internal bus when a PCI address appears in
3528 ** an ITQ and transaction ordering has been satisfied. When operating in the PCI-X mode the
3529 ** ATU does not use the information provided by the Relax Ordering Attribute bit. That is, ATU
3530 ** always uses conventional PCI ordering rules.
3531 ** ¡E Once the internal bus is granted, the internal bus master interface drives the translated address
3532 ** onto the bus and wait for IB_DEVSEL#. When a Retry is signaled, the request is repeated.
3533 ** When a master abort occurs, the transaction is considered complete and a target abort is loaded
3534 ** into the associated IRQ for return to the PCI initiator (transaction is flushed once the PCI
3535 ** master has been delivered the target abort).
3536 ** ¡E Once the translated address is on the bus and the transaction has been accepted, the internal
3537 ** bus target starts returning data with the assertion of IB_TRDY#. Read data is continuously
3538 ** received by the IRQ until one of the following is true:
3539 ** ¡X The full byte count requested by the ATU read request is received. The ATU internal bus
3540 ** initiator interface performs a initiator completion in this case.
3541 ** ¡X When operating in the conventional PCI mode, a Target Abort is received on the internal
3542 ** bus from the internal bus target. In this case, the transaction is aborted and the PCI side is
3544 ** ¡X When operating in the PCI-X mode, a Target Abort is received on the internal bus from
3545 ** the internal bus target. In this case, the transaction is aborted. The ATU generates a Split
3546 ** Completion Message (message class=2h - completer error, and message index=81h -
3547 ** target abort) on the PCI bus to inform the requester about the abnormal condition. The
3548 ** ITQ for this transaction is flushed.
3549 ** ¡X When operating in the conventional PCI mode, a single data phase disconnection is
3550 ** received from the internal bus target. When the data has not been received up to the next
3551 ** QWORD boundary, the ATU internal bus master interface attempts to reacquire the bus.
3552 ** When not, the bus returns to idle.
3553 ** ¡X When operating in the PCI-X mode, a single data phase disconnection is received from
3554 ** the internal bus target. The ATU IB initiator interface attempts to reacquire the bus to
3555 ** obtain remaining data.
3556 ** ¡X When operating in the conventional PCI mode, a disconnection at Next ADB is received
3557 ** from the internal bus target. The bus returns to idle.
3558 ** ¡X When operating in the PCI-X mode, a disconnection at Next ADB is received from the
3559 ** internal bus target. The ATU IB initiator interface attempts to reacquire the bus to obtain
3561 ** To support PCI Local Bus Specification, Revision 2.0 devices, the ATU can be programmed to
3562 ** ignore the memory read command (Memory Read, Memory Read Line, and Memory Read
3563 ** Multiple) when trying to match the current inbound read transaction with data in a DRC queue
3564 ** which was read previously (DRC on target bus). When the Read Command Alias Bit in the
3565 ** ATUCR register is set, the ATU does not distinguish the read commands on transactions. For
3566 ** example, the ATU enqueues a DRR with a Memory Read Multiple command and performs the read
3567 ** on the internal bus. Some time later, a PCI master attempts a Memory Read with the same address
3568 ** as the previous Memory Read Multiple. When the Read Command Bit is set, the ATU would return
3569 ** the read data from the DRC queue and consider the Delayed Read transaction complete. When the
3570 ** Read Command bit in the ATUCR was clear, the ATU would not return data since the PCI read
3571 ** commands did not match, only the address.
3572 **************************************************************************
3575 **************************************************************************
3576 ** Inbound Write Transaction
3577 **========================================================================
3578 ** An inbound write transaction is initiated by a PCI master and is targeted at either 80331 local
3579 ** memory or a 80331 memory-mapped register.
3580 ** Data flow for an inbound write transaction on the PCI bus is summarized as:
3581 ** ¡E The ATU claims the PCI write transaction when the PCI address is within the inbound
3582 ** translation window defined by the ATU Inbound Base Address Register (and Inbound Upper
3583 ** Base Address Register during DACs) and Inbound Limit Register.
3584 ** ¡E When the IWADQ has at least one address entry available and the IWQ has at least one buffer
3585 ** available, the address is captured and the first data phase is accepted.
3586 ** ¡E The PCI interface continues to accept write data until one of the following is true:
3587 ** ¡X The initiator performs a disconnect.
3588 ** ¡X The transaction crosses a buffer boundary.
3589 ** ¡E When an address parity error is detected during the address phase of the transaction, the
3590 ** address parity error mechanisms are used. Refer to Section 3.7.1 for details of the address
3591 ** parity error response.
3592 ** ¡E When operating in the PCI-X mode when an attribute parity error is detected, the attribute
3593 ** parity error mechanism described in Section 3.7.1 is used.
3594 ** ¡E When a data parity error is detected while accepting data, the slave interface sets the
3595 ** appropriate bits based on PCI specifications. No other action is taken. Refer to Section 3.7.2.6
3596 ** for details of the inbound write data parity error response.
3597 ** Once the PCI interface places a PCI address in the IWADQ, when IWQ has received data sufficient
3598 ** to cross a buffer boundary or the master disconnects on the PCI bus, the ATUs internal bus
3599 ** interface becomes aware of the inbound write. When there are additional write transactions ahead
3600 ** in the IWQ/IWADQ, the current transaction remains posted until ordering and priority have been
3601 ** satisfied (Refer to Section 3.5.3) and the transaction is attempted on the internal bus by the ATU
3602 ** internal master interface. The ATU does not insert target wait states nor do data merging on the PCI
3603 ** interface, when operating in the PCI mode.
3604 ** In the PCI-X mode memory writes are always executed as immediate transactions, while
3605 ** configuration write transactions are processed as split transactions. The ATU generates a Split
3606 ** Completion Message, (with Message class=0h - Write Completion Class and Message index =
3607 ** 00h - Write Completion Message) once a configuration write is successfully executed.
3608 ** Also, when operating in the PCI-X mode a write sequence may contain multiple write transactions.
3609 ** The ATU handles such transactions as independent transactions.
3610 ** Data flow for the inbound write transaction on the internal bus is summarized as:
3611 ** ¡E The ATU internal bus master requests the internal bus when IWADQ has at least one entry
3612 ** with associated data in the IWQ.
3613 ** ¡E When the internal bus is granted, the internal bus master interface initiates the write
3614 ** transaction by driving the translated address onto the internal bus. For details on inbound
3615 ** address translation.
3616 ** ¡E When IB_DEVSEL# is not returned, a master abort condition is signaled on the internal bus.
3617 ** The current transaction is flushed from the queue and SERR# may be asserted on the PCI
3619 ** ¡E The ATU initiator interface asserts IB_REQ64# to attempt a 64-bit transfer. When
3620 ** IB_ACK64# is not returned, a 32-bit transfer is used. Transfers of less than 64-bits use the
3621 ** IB_C/BE[7:0]# to mask the bytes not written in the 64-bit data phase. Write data is transferred
3622 ** from the IWQ to the internal bus when data is available and the internal bus interface retains
3623 ** internal bus ownership.
3624 ** ¡E The internal bus interface stops transferring data from the current transaction to the internal
3625 ** bus when one of the following conditions becomes true:
3626 ** ¡X The internal bus initiator interface loses bus ownership. The ATU internal initiator
3627 ** terminates the transfer (initiator disconnection) at the next ADB (for the internal bus ADB
3628 ** is defined as a naturally aligned 128-byte boundary) and attempt to reacquire the bus to
3629 ** complete the delivery of remaining data using the same sequence ID but with the
3630 ** modified starting address and byte count.
3631 ** ¡X A Disconnect at Next ADB is signaled on the internal bus from the internal target. When
3632 ** the transaction in the IWQ completes at that ADB, the initiator returns to idle. When the
3633 ** transaction in the IWQ is not complete, the initiator attempts to reacquire the bus to
3634 ** complete the delivery of remaining data using the same sequence ID but with the
3635 ** modified starting address and byte count.
3636 ** ¡X A Single Data Phase Disconnect is signaled on the internal bus from the internal target.
3637 ** When the transaction in the IWQ needs only a single data phase, the master returns to idle.
3638 ** When the transaction in the IWQ is not complete, the initiator attempts to reacquire the
3639 ** bus to complete the delivery of remaining data using the same sequence ID but with the
3640 ** modified starting address and byte count.
3641 ** ¡X The data from the current transaction has completed (satisfaction of byte count). An
3642 ** initiator termination is performed and the bus returns to idle.
3643 ** ¡X A Master Abort is signaled on the internal bus. SERR# may be asserted on the PCI bus.
3644 ** Data is flushed from the IWQ.
3645 *****************************************************************
3651 **************************************************************************
3652 ** Inbound Read Completions Data Parity Errors
3653 **========================================================================
3654 ** As an initiator, the ATU may encounter this error condition when operating in the PCI-X mode.
3655 ** When as the completer of a Split Read Request the ATU observes PERR# assertion during the split
3656 ** completion transaction, the ATU attempts to complete the transaction normally and no further
3658 **************************************************************************
3662 **************************************************************************
3663 ** Inbound Configuration Write Completion Message Data Parity Errors
3664 **========================================================================
3665 ** As an initiator, the ATU may encounter this error condition when operating in the PCI-X mode.
3666 ** When as the completer of a Configuration (Split) Write Request the ATU observes PERR#
3667 ** assertion during the split completion transaction, the ATU attempts to complete the transaction
3668 ** normally and no further action is taken.
3669 **************************************************************************
3673 **************************************************************************
3674 ** Inbound Read Request Data Parity Errors
3675 **===================== Immediate Data Transfer ==========================
3676 ** As a target, the ATU may encounter this error when operating in the Conventional PCI or PCI-X modes.
3677 ** Inbound read data parity errors occur when read data delivered from the IRQ is detected as having
3678 ** bad parity by the initiator of the transaction who is receiving the data. The initiator may optionally
3679 ** report the error to the system by asserting PERR#. As a target device in this scenario, no action is
3680 ** required and no error bits are set.
3681 **=====================Split Response Termination=========================
3682 ** As a target, the ATU may encounter this error when operating in the PCI-X mode.
3683 ** Inbound read data parity errors occur during the Split Response Termination. The initiator may
3684 ** optionally report the error to the system by asserting PERR#. As a target device in this scenario, no
3685 ** action is required and no error bits are set.
3686 **************************************************************************
3690 **************************************************************************
3691 ** Inbound Write Request Data Parity Errors
3692 **========================================================================
3693 ** As a target, the ATU may encounter this error when operating in the Conventional or PCI-X modes.
3694 ** Data parity errors occurring during write operations received by the ATU may assert PERR# on
3695 ** the PCI Bus. When an error occurs, the ATU continues accepting data until the initiator of the write
3696 ** transaction completes or a queue fill condition is reached. Specifically, the following actions with
3697 ** the given constraints are taken by the ATU:
3698 ** ¡E PERR# is asserted two clocks cycles (three clock cycles when operating in the PCI-X mode)
3699 ** following the data phase in which the data parity error is detected on the bus. This is only
3700 ** done when the Parity Error Response bit in the ATUCMD is set.
3701 ** ¡E The Detected Parity Error bit in the ATUSR is set. When the ATU sets this bit, additional
3702 ** actions is taken:
3703 ** ¡X When the ATU Detected Parity Error Interrupt Mask bit in the ATUIMR is clear, set the
3704 ** Detected Parity Error bit in the ATUISR. When set, no action.
3705 ***************************************************************************
3710 ***************************************************************************
3711 ** Inbound Configuration Write Request
3712 ** =====================================================================
3713 ** As a target, the ATU may encounter this error when operating in the Conventional or PCI-X modes.
3714 ** ===============================================
3715 ** Conventional PCI Mode
3716 ** ===============================================
3717 ** To allow for correct data parity calculations for delayed write transactions, the ATU delays the
3718 ** assertion of STOP# (signalling a Retry) until PAR is driven by the master. A parity error during a
3719 ** delayed write transaction (inbound configuration write cycle) can occur in any of the following
3720 ** parts of the transactions:
3721 ** ¡E During the initial Delayed Write Request cycle on the PCI bus when the ATU latches the
3722 ** address/command and data for delayed delivery to the internal configuration register.
3723 ** ¡E During the Delayed Write Completion cycle on the PCI bus when the ATU delivers the status
3724 ** of the operation back to the original master.
3725 ** The 80331 ATU PCI interface has the following responses to a delayed write parity error for
3726 ** inbound transactions during Delayed Write Request cycles with the given constraints:
3727 ** ¡E When the Parity Error Response bit in the ATUCMD is set, the ATU asserts TRDY#
3728 ** (disconnects with data) and two clock cycles later asserts PERR# notifying the initiator of the
3729 ** parity error. The delayed write cycle is not enqueued and forwarded to the internal bus.
3730 ** When the Parity Error Response bit in the ATUCMD is cleared, the ATU retries the
3731 ** transaction by asserting STOP# and enqueues the Delayed Write Request cycle to be
3732 ** forwarded to the internal bus. PERR# is not asserted.
3733 ** ¡E The Detected Parity Error bit in the ATUSR is set. When the ATU sets this bit, additional
3734 ** actions is taken:
3735 ** ¡X When the ATU Detected Parity Error Interrupt Mask bit in the ATUIMR is clear, set the
3736 ** Detected Parity Error bit in the ATUISR. When set, no action.
3737 ** For the original write transaction to be completed, the initiator retries the transaction on the PCI
3738 ** bus and the ATU returns the status from the internal bus, completing the transaction.
3739 ** For the Delayed Write Completion transaction on the PCI bus where a data parity error occurs and
3740 ** therefore does not agree with the status being returned from the internal bus (i.e. status being
3741 ** returned is normal completion) the ATU performs the following actions with the given constraints:
3742 ** ¡E When the Parity Error Response Bit is set in the ATUCMD, the ATU asserts TRDY#
3743 ** (disconnects with data) and two clocks later asserts PERR#. The Delayed Completion cycle in
3744 ** the IDWQ remains since the data of retried command did not match the data within the queue.
3745 ** ¡E The Detected Parity Error bit in the ATUSR is set. When the ATU sets this bit, additional
3746 ** actions is taken:
3747 ** ¡X When the ATU Detected Parity Error Interrupt Mask bit in the ATUIMR is clear, set the
3748 ** Detected Parity Error bit in the ATUISR. When set, no action.
3749 ** ===================================================
3751 ** ===================================================
3752 ** Data parity errors occurring during configuration write operations received by the ATU may cause
3753 ** PERR# assertion and delivery of a Split Completion Error Message on the PCI Bus. When an error
3754 ** occurs, the ATU accepts the write data and complete with a Split Response Termination.
3755 ** Specifically, the following actions with the given constraints are then taken by the ATU:
3756 ** ¡E When the Parity Error Response bit in the ATUCMD is set, PERR# is asserted three clocks
3757 ** cycles following the Split Response Termination in which the data parity error is detected on
3758 ** the bus. When the ATU asserts PERR#, additional actions is taken:
3759 ** ¡X A Split Write Data Parity Error message (with message class=2h - completer error and
3760 ** message index=01h - Split Write Data Parity Error) is initiated by the ATU on the PCI bus
3761 ** that addresses the requester of the configuration write.
3762 ** ¡X When the Initiated Split Completion Error Message Interrupt Mask in the ATUIMR is
3763 ** clear, set the Initiated Split Completion Error Message bit in the ATUISR. When set, no
3765 ** ¡X The Split Write Request is not enqueued and forwarded to the internal bus.
3766 ** ¡E The Detected Parity Error bit in the ATUSR is set. When the ATU sets this bit, additional
3767 ** actions is taken:
3768 ** ¡X When the ATU Detected Parity Error Interrupt Mask bit in the ATUIMR is clear, set the
3769 ** Detected Parity Error bit in the ATUISR. When set, no action.
3771 ***************************************************************************
3775 ***************************************************************************
3776 ** Split Completion Messages
3777 ** =======================================================================
3778 ** As a target, the ATU may encounter this error when operating in the PCI-X mode.
3779 ** Data parity errors occurring during Split Completion Messages claimed by the ATU may assert
3780 ** PERR# (when enabled) or SERR# (when enabled) on the PCI Bus. When an error occurs, the
3781 ** ATU accepts the data and complete normally. Specifically, the following actions with the given
3782 ** constraints are taken by the ATU:
3783 ** ¡E PERR# is asserted three clocks cycles following the data phase in which the data parity error
3784 ** is detected on the bus. This is only done when the Parity Error Response bit in the ATUCMD
3785 ** is set. When the ATU asserts PERR#, additional actions is taken:
3786 ** ¡X The Master Parity Error bit in the ATUSR is set.
3787 ** ¡X When the ATU PCI Master Parity Error Interrupt Mask Bit in the ATUIMR is clear, set the
3788 ** PCI Master Parity Error bit in the ATUISR. When set, no action.
3789 ** ¡X When the SERR# Enable bit in the ATUCMD is set, and the Data Parity Error Recover
3790 ** Enable bit in the PCIXCMD register is clear, assert SERR#; otherwise no action is taken.
3791 ** When the ATU asserts SERR#, additional actions is taken:
3792 ** Set the SERR# Asserted bit in the ATUSR.
3793 ** When the ATU SERR# Asserted Interrupt Mask Bit in the ATUIMR is clear, set the
3794 ** SERR# Asserted bit in the ATUISR. When set, no action.
3795 ** When the ATU SERR# Detected Interrupt Enable Bit in the ATUCR is set, set the
3796 ** SERR# Detected bit in the ATUISR. When clear, no action.
3797 ** ¡E When the SCE bit (Split Completion Error -- bit 30 of the Completer Attributes) is set during
3798 ** the Attribute phase, the Received Split Completion Error Message bit in the PCIXSR is set.
3799 ** When the ATU sets this bit, additional actions is taken:
3800 ** ¡X When the ATU Received Split Completion Error Message Interrupt Mask bit in the
3801 ** ATUIMR is clear, set the Received Split Completion Error Message bit in the ATUISR.
3802 ** When set, no action.
3803 ** ¡E The Detected Parity Error bit in the ATUSR is set. When the ATU sets this bit, additional
3804 ** actions is taken:
3805 ** ¡X When the ATU Detected Parity Error Interrupt Mask bit in the ATUIMR is clear, set the
3806 ** Detected Parity Error bit in the ATUISR. When set, no action.
3807 ** ¡E The transaction associated with the Split Completion Message is discarded.
3808 ** ¡E When the discarded transaction was a read, a completion error message (with message
3809 ** class=2h - completer error and message index=82h - PCI bus read parity error) is generated on
3810 ** the internal bus of the 80331.
3811 *****************************************************************************
3816 ******************************************************************************************************
3817 ** Messaging Unit (MU) of the Intel R 80331 I/O processor (80331)
3818 ** ==================================================================================================
3819 ** The Messaging Unit (MU) transfers data between the PCI system and the 80331
3820 ** notifies the respective system when new data arrives.
3821 ** The PCI window for messaging transactions is always the first 4 Kbytes of the inbound translation.
3822 ** window defined by:
3823 ** 1.Inbound ATU Base Address Register 0 (IABAR0)
3824 ** 2.Inbound ATU Limit Register 0 (IALR0)
3825 ** All of the Messaging Unit errors are reported in the same manner as ATU errors.
3826 ** Error conditions and status can be found in :
3829 **====================================================================================================
3830 ** Mechanism Quantity Assert PCI Interrupt Signals Generate I/O Processor Interrupt
3831 **----------------------------------------------------------------------------------------------------
3832 ** Message Registers 2 Inbound Optional Optional
3834 **----------------------------------------------------------------------------------------------------
3835 ** Doorbell Registers 1 Inbound Optional Optional
3837 **----------------------------------------------------------------------------------------------------
3838 ** Circular Queues 4 Circular Queues Under certain conditions Under certain conditions
3839 **----------------------------------------------------------------------------------------------------
3840 ** Index Registers 1004 32-bit Memory Locations No Optional
3841 **====================================================================================================
3842 ** PCI Memory Map: First 4 Kbytes of the ATU Inbound PCI Address Space
3843 **====================================================================================================
3848 **------------------------------------------------------------------------
3849 ** 0010H Inbound Message Register 0 ]
3850 ** 0014H Inbound Message Register 1 ]
3851 ** 0018H Outbound Message Register 0 ]
3852 ** 001CH Outbound Message Register 1 ] 4 Message Registers
3853 **------------------------------------------------------------------------
3854 ** 0020H Inbound Doorbell Register ]
3855 ** 0024H Inbound Interrupt Status Register ]
3856 ** 0028H Inbound Interrupt Mask Register ]
3857 ** 002CH Outbound Doorbell Register ]
3858 ** 0030H Outbound Interrupt Status Register ]
3859 ** 0034H Outbound Interrupt Mask Register ] 2 Doorbell Registers and 4 Interrupt Registers
3860 **------------------------------------------------------------------------
3863 **------------------------------------------------------------------------
3864 ** 0040H Inbound Queue Port ]
3865 ** 0044H Outbound Queue Port ] 2 Queue Ports
3866 **------------------------------------------------------------------------
3869 **------------------------------------------------------------------------
3872 ** : Intel Xscale Microarchitecture Local Memory ]
3874 ** 0FFCH ] 1004 Index Registers
3875 *******************************************************************************
3877 struct HBA_MessageUnit
3879 u_int32_t resrved0[4]; /*0000 000F*/
3880 u_int32_t inbound_msgaddr0; /*0010 0013*/
3881 u_int32_t inbound_msgaddr1; /*0014 0017*/
3882 u_int32_t outbound_msgaddr0; /*0018 001B*/
3883 u_int32_t outbound_msgaddr1; /*001C 001F*/
3884 u_int32_t inbound_doorbell; /*0020 0023*/
3885 u_int32_t inbound_intstatus; /*0024 0027*/
3886 u_int32_t inbound_intmask; /*0028 002B*/
3887 u_int32_t outbound_doorbell; /*002C 002F*/
3888 u_int32_t outbound_intstatus; /*0030 0033*/
3889 u_int32_t outbound_intmask; /*0034 0037*/
3890 u_int32_t reserved1[2]; /*0038 003F*/
3891 u_int32_t inbound_queueport; /*0040 0043*/
3892 u_int32_t outbound_queueport; /*0044 0047*/
3893 u_int32_t reserved2[2]; /*0048 004F*/
3894 u_int32_t reserved3[492]; /*0050 07FF ......local_buffer 492*/
3895 u_int32_t reserved4[128]; /*0800 09FF 128*/
3896 u_int32_t msgcode_rwbuffer[256]; /*0a00 0DFF 256*/
3897 u_int32_t message_wbuffer[32]; /*0E00 0E7F 32*/
3898 u_int32_t reserved5[32]; /*0E80 0EFF 32*/
3899 u_int32_t message_rbuffer[32]; /*0F00 0F7F 32*/
3900 u_int32_t reserved6[32]; /*0F80 0FFF 32*/
3903 *********************************************************************
3905 *********************************************************************
3909 u_int8_t doorbell_reserved[132096]; /*reserved */
3910 u_int32_t drv2iop_doorbell; /*offset 0x00020400:00,01,02,03: window of "instruction flags" from driver to iop */
3911 u_int32_t drv2iop_doorbell_mask; /* 04,05,06,07: doorbell mask */
3912 u_int32_t iop2drv_doorbell; /* 08,09,10,11: window of "instruction flags" from iop to driver */
3913 u_int32_t iop2drv_doorbell_mask; /* 12,13,14,15: doorbell mask */
3916 *********************************************************************
3918 *********************************************************************
3922 u_int8_t message_reserved0[64000]; /*reserved */
3923 u_int32_t msgcode_rwbuffer[256]; /*offset 0x0000fa00: 0, 1, 2, 3,...,1023: message code read write 1024bytes */
3924 u_int32_t message_wbuffer[32]; /*offset 0x0000fe00:1024,1025,1026,1027,...,1151: user space data to iop 128bytes */
3925 u_int32_t message_reserved1[32]; /* 1152,1153,1154,1155,...,1279: message reserved*/
3926 u_int32_t message_rbuffer[32]; /*offset 0x0000ff00:1280,1281,1282,1283,...,1407: iop data to user space 128bytes */
3929 *********************************************************************
3931 *********************************************************************
3933 struct HBB_MessageUnit
3935 u_int32_t post_qbuffer[ARCMSR_MAX_HBB_POSTQUEUE]; /* post queue buffer for iop */
3936 u_int32_t done_qbuffer[ARCMSR_MAX_HBB_POSTQUEUE]; /* done queue buffer for iop */
3937 int32_t postq_index; /* post queue index */
3938 int32_t doneq_index; /* done queue index */
3939 struct HBB_DOORBELL *hbb_doorbell;
3940 struct HBB_RWBUFFER *hbb_rwbuffer;
3943 *********************************************************************
3945 *********************************************************************
3947 struct MessageUnit_UNION
3950 struct HBA_MessageUnit hbamu;
3951 struct HBB_MessageUnit hbbmu;
3955 *****************************************************************************
3956 ** Theory of MU Operation
3957 *****************************************************************************
3958 **--------------------
3959 ** inbound_msgaddr0:
3960 ** inbound_msgaddr1:
3961 ** outbound_msgaddr0:
3962 ** outbound_msgaddr1:
3963 ** . The MU has four independent messaging mechanisms.
3964 ** There are four Message Registers that are similar to a combination of mailbox and doorbell registers.
3965 ** Each holds a 32-bit value and generates an interrupt when written.
3966 **--------------------
3967 ** inbound_doorbell:
3968 ** outbound_doorbell:
3969 ** . The two Doorbell Registers support software interrupts.
3970 ** When a bit is set in a Doorbell Register, an interrupt is generated.
3971 **--------------------
3972 ** inbound_queueport:
3973 ** outbound_queueport:
3976 ** . The Circular Queues support a message passing scheme that uses 4 circular queues.
3977 ** The 4 circular queues are implemented in 80331 local memory.
3978 ** Two queues are used for inbound messages and two are used for outbound messages.
3979 ** Interrupts may be generated when the queue is written.
3980 **--------------------
3981 ** local_buffer 0x0050 ....0x0FFF
3982 ** . The Index Registers use a portion of the 80331 local memory to implement a large set of message registers.
3983 ** When one of the Index Registers is written, an interrupt is generated and the address of the register written is captured.
3984 ** Interrupt status for all interrupts is recorded in the Inbound Interrupt Status Register and the Outbound Interrupt Status Register.
3985 ** Each interrupt generated by the Messaging Unit can be masked.
3986 **--------------------
3987 ** . Multi-DWORD PCI burst accesses are not supported by the Messaging Unit,
3988 ** with the exception of Multi-DWORD reads to the index registers.
3989 ** In Conventional mode: the MU terminates Multi-DWORD PCI transactions
3990 ** (other than index register reads) with a disconnect at the next Qword boundary, with the exception of queue ports.
3991 ** In PCI-X mode : the MU terminates a Multi-DWORD PCI read transaction with a Split Response
3992 ** and the data is returned through split completion transaction(s).
3993 ** however, when the burst request crosses into or through the range of offsets 40h to 4Ch
3994 ** (e.g., this includes the queue ports) the transaction is signaled target-abort immediately on the PCI bus.
3995 ** In PCI-X mode, Multi-DWORD PCI writes is signaled a Single-Data-Phase Disconnect
3996 ** which means that no data beyond the first Qword (Dword when the MU does not assert P_ACK64#) is written.
3997 **--------------------
3998 ** . All registers needed to configure and control the Messaging Unit are memory-mapped registers.
3999 ** The MU uses the first 4 Kbytes of the inbound translation window in the Address Translation Unit (ATU).
4000 ** This PCI address window is used for PCI transactions that access the 80331 local memory.
4001 ** The PCI address of the inbound translation window is contained in the Inbound ATU Base Address Register.
4002 **--------------------
4003 ** . From the PCI perspective, the Messaging Unit is part of the Address Translation Unit.
4004 ** The Messaging Unit uses the PCI configuration registers of the ATU for control and status information.
4005 ** The Messaging Unit must observe all PCI control bits in the ATU Command Register and ATU Configuration Register.
4006 ** The Messaging Unit reports all PCI errors in the ATU Status Register.
4007 **--------------------
4008 ** . Parts of the Messaging Unit can be accessed as a 64-bit PCI device.
4009 ** The register interface, message registers, doorbell registers,
4010 ** and index registers returns a P_ACK64# in response to a P_REQ64# on the PCI interface.
4011 ** Up to 1 Qword of data can be read or written per transaction (except Index Register reads).
4012 ** The Inbound and Outbound Queue Ports are always 32-bit addresses and the MU does not assert P_ACK64# to offsets 40H and 44H.
4013 **************************************************************************
4016 **************************************************************************
4017 ** Message Registers
4018 ** ==============================
4019 ** . Messages can be sent and received by the 80331 through the use of the Message Registers.
4020 ** . When written, the message registers may cause an interrupt to be generated to either the Intel XScale core or the host processor.
4021 ** . Inbound messages are sent by the host processor and received by the 80331.
4022 ** Outbound messages are sent by the 80331 and received by the host processor.
4023 ** . The interrupt status for outbound messages is recorded in the Outbound Interrupt Status Register.
4024 ** Interrupt status for inbound messages is recorded in the Inbound Interrupt Status Register.
4026 ** Inbound Messages:
4027 ** -----------------
4028 ** . When an inbound message register is written by an external PCI agent, an interrupt may be generated to the Intel XScale core.
4029 ** . The interrupt may be masked by the mask bits in the Inbound Interrupt Mask Register.
4030 ** . The Intel XScale core interrupt is recorded in the Inbound Interrupt Status Register.
4031 ** The interrupt causes the Inbound Message Interrupt bit to be set in the Inbound Interrupt Status Register.
4032 ** This is a Read/Clear bit that is set by the MU hardware and cleared by software.
4033 ** The interrupt is cleared when the Intel XScale core writes a value of
4034 ** 1 to the Inbound Message Interrupt bit in the Inbound Interrupt Status Register.
4035 ** ------------------------------------------------------------------------
4036 ** Inbound Message Register - IMRx
4038 ** . There are two Inbound Message Registers: IMR0 and IMR1.
4039 ** . When the IMR register is written, an interrupt to the Intel XScale core may be generated.
4040 ** The interrupt is recorded in the Inbound Interrupt Status Register and may be masked
4041 ** by the Inbound Message Interrupt Mask bit in the Inbound Interrupt Mask Register.
4042 ** -----------------------------------------------------------------
4043 ** Bit Default Description
4044 ** 31:00 0000 0000H Inbound Message - This is a 32-bit message written by an external PCI agent.
4045 ** When written, an interrupt to the Intel XScale core may be generated.
4046 **************************************************************************
4048 #define ARCMSR_MU_INBOUND_MESSAGE_REG0 0x10 /*dword 0x13,0x12,0x11,0x10*/
4049 #define ARCMSR_MU_INBOUND_MESSAGE_REG1 0x14 /*dword 0x17,0x16,0x15,0x14*/
4051 **************************************************************************
4052 ** Outbound Message Register - OMRx
4053 ** --------------------------------
4054 ** There are two Outbound Message Registers: OMR0 and OMR1. When the OMR register is
4055 ** written, a PCI interrupt may be generated. The interrupt is recorded in the Outbound Interrupt
4056 ** Status Register and may be masked by the Outbound Message Interrupt Mask bit in the Outbound
4057 ** Interrupt Mask Register.
4059 ** Bit Default Description
4060 ** 31:00 00000000H Outbound Message - This is 32-bit message written by the Intel XScale core. When written, an
4061 ** interrupt may be generated on the PCI Interrupt pin determined by the ATU Interrupt Pin Register.
4062 **************************************************************************
4064 #define ARCMSR_MU_OUTBOUND_MESSAGE_REG0 0x18 /*dword 0x1B,0x1A,0x19,0x18*/
4065 #define ARCMSR_MU_OUTBOUND_MESSAGE_REG1 0x1C /*dword 0x1F,0x1E,0x1D,0x1C*/
4067 **************************************************************************
4068 ** Doorbell Registers
4069 ** ==============================
4070 ** There are two Doorbell Registers:
4071 ** Inbound Doorbell Register
4072 ** Outbound Doorbell Register
4073 ** The Inbound Doorbell Register allows external PCI agents to generate interrupts to the Intel R XScale core.
4074 ** The Outbound Doorbell Register allows the Intel R XScale core to generate a PCI interrupt.
4075 ** Both Doorbell Registers may generate interrupts whenever a bit in the register is set.
4077 ** Inbound Doorbells:
4078 ** ------------------
4079 ** . When the Inbound Doorbell Register is written by an external PCI agent, an interrupt may be generated to the Intel R XScale core.
4080 ** An interrupt is generated when any of the bits in the doorbell register is written to a value of 1.
4081 ** Writing a value of 0 to any bit does not change the value of that bit and does not cause an interrupt to be generated.
4082 ** . Once a bit is set in the Inbound Doorbell Register, it cannot be cleared by any external PCI agent.
4083 ** The interrupt is recorded in the Inbound Interrupt Status Register.
4084 ** . The interrupt may be masked by the Inbound Doorbell Interrupt mask bit in the Inbound Interrupt Mask Register.
4085 ** When the mask bit is set for a particular bit, no interrupt is generated for that bit.
4086 ** The Inbound Interrupt Mask Register affects only the generation of the normal messaging unit interrupt
4087 ** and not the values written to the Inbound Doorbell Register.
4088 ** One bit in the Inbound Doorbell Register is reserved for an Error Doorbell interrupt.
4089 ** . The interrupt is cleared when the Intel R XScale core writes a value of 1 to the bits in the Inbound Doorbell Register that are set.
4090 ** Writing a value of 0 to any bit does not change the value of that bit and does not clear the interrupt.
4091 ** ------------------------------------------------------------------------
4092 ** Inbound Doorbell Register - IDR
4094 ** . The Inbound Doorbell Register (IDR) is used to generate interrupts to the Intel XScale core.
4095 ** . Bit 31 is reserved for generating an Error Doorbell interrupt.
4096 ** When bit 31 is set, an Error interrupt may be generated to the Intel XScale core.
4097 ** All other bits, when set, cause the Normal Messaging Unit interrupt line of the Intel XScale core to be asserted,
4098 ** when the interrupt is not masked by the Inbound Doorbell Interrupt Mask bit in the Inbound Interrupt Mask Register.
4099 ** The bits in the IDR register can only be set by an external PCI agent and can only be cleared by the Intel XScale core.
4100 ** ------------------------------------------------------------------------
4101 ** Bit Default Description
4102 ** 31 0 2 Error Interrupt - Generate an Error Interrupt to the Intel XScale core.
4103 ** 30:00 00000000H Normal Interrupt - When any bit is set, generate a Normal interrupt to the Intel XScale core.
4104 ** When all bits are clear, do not generate a Normal Interrupt.
4105 **************************************************************************
4107 #define ARCMSR_MU_INBOUND_DOORBELL_REG 0x20 /*dword 0x23,0x22,0x21,0x20*/
4109 **************************************************************************
4110 ** Inbound Interrupt Status Register - IISR
4112 ** . The Inbound Interrupt Status Register (IISR) contains hardware interrupt status.
4113 ** It records the status of Intel XScale core interrupts generated by the Message Registers, Doorbell Registers, and the Circular Queues.
4114 ** All interrupts are routed to the Normal Messaging Unit interrupt input of the Intel XScale core,
4115 ** except for the Error Doorbell Interrupt and the Outbound Free Queue Full interrupt;
4116 ** these two are routed to the Messaging Unit Error interrupt input.
4117 ** The generation of interrupts recorded in the Inbound Interrupt Status Register
4118 ** may be masked by setting the corresponding bit in the Inbound Interrupt Mask Register.
4119 ** Some of the bits in this register are Read Only.
4120 ** For those bits, the interrupt must be cleared through another register.
4122 ** Bit Default Description
4123 ** 31:07 0000000H 0 2 Reserved
4124 ** 06 0 2 Index Register Interrupt - This bit is set by the MU hardware
4125 ** when an Index Register has been written after a PCI transaction.
4126 ** 05 0 2 Outbound Free Queue Full Interrupt - This bit is set
4127 ** when the Outbound Free Head Pointer becomes equal to the Tail Pointer and the queue is full.
4128 ** An Error interrupt is generated for this condition.
4129 ** 04 0 2 Inbound Post Queue Interrupt - This bit is set by the MU hardware when the Inbound Post Queue has been written.
4130 ** Once cleared, an interrupt does NOT be generated
4131 ** when the head and tail pointers remain unequal (i.e. queue status is Not Empty).
4132 ** Therefore, when software leaves any unprocessed messages in the post queue when the interrupt is cleared,
4133 ** software must retain the information that the Inbound Post queue status is not empty.
4134 ** NOTE: This interrupt is provided with dedicated support in the 80331 Interrupt Controller.
4135 ** 03 0 2 Error Doorbell Interrupt - This bit is set when the Error Interrupt of the Inbound Doorbell Register is set.
4136 ** To clear this bit (and the interrupt), the Error Interrupt bit of the Inbound Doorbell Register must be clear.
4137 ** 02 0 2 Inbound Doorbell Interrupt - This bit is set when at least one
4138 ** Normal Interrupt bit in the Inbound Doorbell Register is set.
4139 ** To clear this bit (and the interrupt), the Normal Interrupt bits in the Inbound Doorbell Register must all be clear.
4140 ** 01 0 2 Inbound Message 1 Interrupt - This bit is set by the MU hardware when the Inbound Message 1 Register has been written.
4141 ** 00 0 2 Inbound Message 0 Interrupt - This bit is set by the MU hardware when the Inbound Message 0 Register has been written.
4142 **************************************************************************
4144 #define ARCMSR_MU_INBOUND_INTERRUPT_STATUS_REG 0x24 /*dword 0x27,0x26,0x25,0x24*/
4145 #define ARCMSR_MU_INBOUND_INDEX_INT 0x40
4146 #define ARCMSR_MU_INBOUND_QUEUEFULL_INT 0x20
4147 #define ARCMSR_MU_INBOUND_POSTQUEUE_INT 0x10
4148 #define ARCMSR_MU_INBOUND_ERROR_DOORBELL_INT 0x08
4149 #define ARCMSR_MU_INBOUND_DOORBELL_INT 0x04
4150 #define ARCMSR_MU_INBOUND_MESSAGE1_INT 0x02
4151 #define ARCMSR_MU_INBOUND_MESSAGE0_INT 0x01
4153 **************************************************************************
4154 ** Inbound Interrupt Mask Register - IIMR
4156 ** . The Inbound Interrupt Mask Register (IIMR) provides the ability to mask Intel XScale core interrupts generated by the Messaging Unit.
4157 ** Each bit in the Mask register corresponds to an interrupt bit in the Inbound Interrupt Status Register.
4158 ** Setting or clearing bits in this register does not affect the Inbound Interrupt Status Register.
4159 ** They only affect the generation of the Intel XScale core interrupt.
4160 ** ------------------------------------------------------------------------
4161 ** Bit Default Description
4162 ** 31:07 000000H 0 2 Reserved
4163 ** 06 0 2 Index Register Interrupt Mask - When set, this bit masks the interrupt generated by the MU hardware
4164 ** when an Index Register has been written after a PCI transaction.
4165 ** 05 0 2 Outbound Free Queue Full Interrupt Mask - When set, this bit masks the Error interrupt generated
4166 ** when the Outbound Free Head Pointer becomes equal to the Tail Pointer and the queue is full.
4167 ** 04 0 2 Inbound Post Queue Interrupt Mask - When set, this bit masks the interrupt generated
4168 ** by the MU hardware when the Inbound Post Queue has been written.
4169 ** 03 0 2 Error Doorbell Interrupt Mask - When set, this bit masks the Error Interrupt
4170 ** when the Error Interrupt bit of the Inbound Doorbell Register is set.
4171 ** 02 0 2 Inbound Doorbell Interrupt Mask - When set, this bit masks the interrupt generated
4172 ** when at least one Normal Interrupt bit in the Inbound Doorbell Register is set.
4173 ** 01 0 2 Inbound Message 1 Interrupt Mask - When set, this bit masks the Inbound Message 1
4174 ** Interrupt generated by a write to the Inbound Message 1 Register.
4175 ** 00 0 2 Inbound Message 0 Interrupt Mask - When set,
4176 ** this bit masks the Inbound Message 0 Interrupt generated by a write to the Inbound Message 0 Register.
4177 **************************************************************************
4179 #define ARCMSR_MU_INBOUND_INTERRUPT_MASK_REG 0x28 /*dword 0x2B,0x2A,0x29,0x28*/
4180 #define ARCMSR_MU_INBOUND_INDEX_INTMASKENABLE 0x40
4181 #define ARCMSR_MU_INBOUND_QUEUEFULL_INTMASKENABLE 0x20
4182 #define ARCMSR_MU_INBOUND_POSTQUEUE_INTMASKENABLE 0x10
4183 #define ARCMSR_MU_INBOUND_DOORBELL_ERROR_INTMASKENABLE 0x08
4184 #define ARCMSR_MU_INBOUND_DOORBELL_INTMASKENABLE 0x04
4185 #define ARCMSR_MU_INBOUND_MESSAGE1_INTMASKENABLE 0x02
4186 #define ARCMSR_MU_INBOUND_MESSAGE0_INTMASKENABLE 0x01
4188 **************************************************************************
4189 ** Outbound Doorbell Register - ODR
4191 ** The Outbound Doorbell Register (ODR) allows software interrupt generation. It allows the Intel
4192 ** XScale core to generate PCI interrupts to the host processor by writing to this register. The
4193 ** generation of PCI interrupts through the Outbound Doorbell Register may be masked by setting the
4194 ** Outbound Doorbell Interrupt Mask bit in the Outbound Interrupt Mask Register.
4195 ** The Software Interrupt bits in this register can only be set by the Intel XScale core and can only
4196 ** be cleared by an external PCI agent.
4197 ** ----------------------------------------------------------------------
4198 ** Bit Default Description
4202 ** 28 0000 0000H PCI Interrupt - When set, this bit causes the P_INTC# interrupt output
4203 ** (P_INTA# with BRG_EN and ARB_EN straps low)
4204 ** signal to be asserted or a Message-signaled Interrupt is generated (when enabled).
4205 ** When this bit is cleared, the P_INTC# interrupt output
4206 ** (P_INTA# with BRG_EN and ARB_EN straps low)
4207 ** signal is deasserted.
4208 ** 27:00 000 0000H Software Interrupts - When any bit is set the P_INTC# interrupt output
4209 ** (P_INTA# with BRG_EN and ARB_EN straps low)
4210 ** signal is asserted or a Message-signaled Interrupt is generated (when enabled).
4211 ** When all bits are cleared, the P_INTC# interrupt output (P_INTA# with BRG_EN and ARB_EN straps low)
4212 ** signal is deasserted.
4213 **************************************************************************
4215 #define ARCMSR_MU_OUTBOUND_DOORBELL_REG 0x2C /*dword 0x2F,0x2E,0x2D,0x2C*/
4217 **************************************************************************
4218 ** Outbound Interrupt Status Register - OISR
4220 ** The Outbound Interrupt Status Register (OISR) contains hardware interrupt status. It records the
4221 ** status of PCI interrupts generated by the Message Registers, Doorbell Registers, and the Circular
4222 ** Queues. The generation of PCI interrupts recorded in the Outbound Interrupt Status Register may
4223 ** be masked by setting the corresponding bit in the Outbound Interrupt Mask Register. Some of the
4224 ** bits in this register are Read Only. For those bits, the interrupt must be cleared through another
4226 ** ----------------------------------------------------------------------
4227 ** Bit Default Description
4228 ** 31:05 000000H 000 2 Reserved
4229 ** 04 0 2 PCI Interrupt - This bit is set when the PCI Interrupt bit (bit 28) is set in the Outbound Doorbell Register.
4230 ** To clear this bit (and the interrupt), the PCI Interrupt bit must be cleared.
4231 ** 03 0 2 Outbound Post Queue Interrupt - This bit is set when data in the prefetch buffer is valid. This bit is
4232 ** cleared when any prefetch data has been read from the Outbound Queue Port.
4233 ** 02 0 2 Outbound Doorbell Interrupt - This bit is set when at least one Software Interrupt bit in the Outbound
4234 ** Doorbell Register is set. To clear this bit (and the interrupt), the Software Interrupt bits in the Outbound
4235 ** Doorbell Register must all be clear.
4236 ** 01 0 2 Outbound Message 1 Interrupt - This bit is set by the MU when the Outbound Message 1 Register is
4237 ** written. Clearing this bit clears the interrupt.
4238 ** 00 0 2 Outbound Message 0 Interrupt - This bit is set by the MU when the Outbound Message 0 Register is
4239 ** written. Clearing this bit clears the interrupt.
4240 **************************************************************************
4242 #define ARCMSR_MU_OUTBOUND_INTERRUPT_STATUS_REG 0x30 /*dword 0x33,0x32,0x31,0x30*/
4243 #define ARCMSR_MU_OUTBOUND_PCI_INT 0x10
4244 #define ARCMSR_MU_OUTBOUND_POSTQUEUE_INT 0x08
4245 #define ARCMSR_MU_OUTBOUND_DOORBELL_INT 0x04
4246 #define ARCMSR_MU_OUTBOUND_MESSAGE1_INT 0x02
4247 #define ARCMSR_MU_OUTBOUND_MESSAGE0_INT 0x01
4249 **************************************************************************
4250 ** Outbound Interrupt Mask Register - OIMR
4251 ** The Outbound Interrupt Mask Register (OIMR) provides the ability to mask outbound PCI
4252 ** interrupts generated by the Messaging Unit. Each bit in the mask register corresponds to a
4253 ** hardware interrupt bit in the Outbound Interrupt Status Register. When the bit is set, the PCI
4254 ** interrupt is not generated. When the bit is clear, the interrupt is allowed to be generated.
4255 ** Setting or clearing bits in this register does not affect the Outbound Interrupt Status Register. They
4256 ** only affect the generation of the PCI interrupt.
4257 ** ----------------------------------------------------------------------
4258 ** Bit Default Description
4259 ** 31:05 000000H Reserved
4260 ** 04 0 2 PCI Interrupt Mask - When set, this bit masks the interrupt generation when the PCI Interrupt bit (bit 28)
4261 ** in the Outbound Doorbell Register is set.
4262 ** 03 0 2 Outbound Post Queue Interrupt Mask - When set, this bit masks the interrupt generated when data in
4263 ** the prefetch buffer is valid.
4264 ** 02 0 2 Outbound Doorbell Interrupt Mask - When set, this bit masks the interrupt generated by the Outbound
4265 ** Doorbell Register.
4266 ** 01 0 2 Outbound Message 1 Interrupt Mask - When set, this bit masks the Outbound Message 1 Interrupt
4267 ** generated by a write to the Outbound Message 1 Register.
4268 ** 00 0 2 Outbound Message 0 Interrupt Mask- When set, this bit masks the Outbound Message 0 Interrupt
4269 ** generated by a write to the Outbound Message 0 Register.
4270 **************************************************************************
4272 #define ARCMSR_MU_OUTBOUND_INTERRUPT_MASK_REG 0x34 /*dword 0x37,0x36,0x35,0x34*/
4273 #define ARCMSR_MU_OUTBOUND_PCI_INTMASKENABLE 0x10
4274 #define ARCMSR_MU_OUTBOUND_POSTQUEUE_INTMASKENABLE 0x08
4275 #define ARCMSR_MU_OUTBOUND_DOORBELL_INTMASKENABLE 0x04
4276 #define ARCMSR_MU_OUTBOUND_MESSAGE1_INTMASKENABLE 0x02
4277 #define ARCMSR_MU_OUTBOUND_MESSAGE0_INTMASKENABLE 0x01
4278 #define ARCMSR_MU_OUTBOUND_ALL_INTMASKENABLE 0x1F
4280 **************************************************************************
4282 **************************************************************************
4284 #define ARCMSR_MU_INBOUND_QUEUE_PORT_REG 0x40 /*dword 0x43,0x42,0x41,0x40*/
4285 #define ARCMSR_MU_OUTBOUND_QUEUE_PORT_REG 0x44 /*dword 0x47,0x46,0x45,0x44*/
4287 **************************************************************************
4289 ** ======================================================================
4290 ** The MU implements four circular queues. There are 2 inbound queues and 2 outbound queues. In
4291 ** this case, inbound and outbound refer to the direction of the flow of posted messages.
4292 ** Inbound messages are either:
4293 ** ¡E posted messages by other processors for the Intel XScale core to process or
4294 ** ¡E free (or empty) messages that can be reused by other processors.
4295 ** Outbound messages are either:
4296 ** ¡E posted messages by the Intel XScale core for other processors to process or
4297 ** ¡E free (or empty) messages that can be reused by the Intel XScale core.
4298 ** Therefore, free inbound messages flow away from the 80331 and free outbound messages flow toward the 80331.
4299 ** The four Circular Queues are used to pass messages in the following manner.
4300 ** . The two inbound queues are used to handle inbound messages
4301 ** and the two outbound queues are used to handle outbound messages.
4302 ** . One of the inbound queues is designated the Free queue and it contains inbound free messages.
4303 ** The other inbound queue is designated the Post queue and it contains inbound posted messages.
4304 ** Similarly, one of the outbound queues is designated the Free queue and the other outbound queue is designated the Post queue.
4306 ** =============================================================================================================
4307 ** Circular Queue Summary
4308 ** _____________________________________________________________________________________________________________
4309 ** | Queue Name | Purpose | Action on PCI Interface|
4310 ** |______________________|____________________________________________________________|_________________________|
4311 ** |Inbound Post Queue | Queue for inbound messages from other processors | Written |
4312 ** | | waiting to be processed by the 80331 | |
4313 ** |Inbound Free Queue | Queue for empty inbound messages from the 80331 | Read |
4314 ** | | available for use by other processors | |
4315 ** |Outbound Post Queue | Queue for outbound messages from the 80331 | Read |
4316 ** | | that are being posted to the other processors | |
4317 ** |Outbound Free Queue | Queue for empty outbound messages from other processors | Written |
4318 ** | | available for use by the 80331 | |
4319 ** |______________________|____________________________________________________________|_________________________|
4321 ** . The two inbound queues allow the host processor to post inbound messages for the 80331 in one
4322 ** queue and to receive free messages returning from the 80331.
4323 ** The host processor posts inbound messages,
4324 ** the Intel XScale core receives the posted message and when it is finished with the message,
4325 ** places it back on the inbound free queue for reuse by the host processor.
4327 ** The circular queues are accessed by external PCI agents through two port locations in the PCI
4329 ** Inbound Queue Port
4330 ** and Outbound Queue Port.
4331 ** The Inbound Queue Port is used by external PCI agents to read the Inbound Free Queue and write the Inbound Post Queue.
4332 ** The Outbound Queue Port is used by external PCI agents to read the Outbound Post Queue and write the Outbound Free Queue.
4333 ** Note that a PCI transaction to the inbound or outbound queue ports with null byte enables (P_C/BE[3:0]#=1111 2 )
4334 ** does not cause the MU hardware to increment the queue pointers.
4335 ** This is treated as when the PCI transaction did not occur.
4336 ** The Inbound and Outbound Queue Ports never respond with P_ACK64# on the PCI interface.
4337 ** ======================================================================================
4338 ** Overview of Circular Queue Operation
4339 ** ======================================================================================
4340 ** . The data storage for the circular queues must be provided by the 80331 local memory.
4341 ** . The base address of the circular queues is contained in the Queue Base Address Register.
4342 ** Each entry in the queue is a 32-bit data value.
4343 ** . Each read from or write to the queue may access only one queue entry.
4344 ** . Multi-DWORD accesses to the circular queues are not allowed.
4345 ** Sub-DWORD accesses are promoted to DWORD accesses.
4346 ** . Each circular queue has a head pointer and a tail pointer.
4347 ** The pointers are offsets from the Queue Base Address.
4348 ** . Writes to a queue occur at the head of the queue and reads occur from the tail.
4349 ** The head and tail pointers are incremented by either the Intel XScale core or the Messaging Unit hardware.
4350 ** Which unit maintains the pointer is determined by the writer of the queue.
4351 ** More details about the pointers are given in the queue descriptions below.
4352 ** The pointers are incremented after the queue access.
4353 ** Both pointers wrap around to the first address of the circular queue when they reach the circular queue size.
4355 ** Messaging Unit...
4357 ** The Messaging Unit generates an interrupt to the Intel XScale core or generate a PCI interrupt under certain conditions.
4358 ** . In general, when a Post queue is written, an interrupt is generated to notify the receiver that a message was posted.
4359 ** The size of each circular queue can range from 4K entries (16 Kbytes) to 64K entries (256 Kbytes).
4360 ** . All four queues must be the same size and may be contiguous.
4361 ** Therefore, the total amount of local memory needed by the circular queues ranges from 64 Kbytes to 1 Mbytes.
4362 ** The Queue size is determined by the Queue Size field in the MU Configuration Register.
4363 ** . There is one base address for all four queues.
4364 ** It is stored in the Queue Base Address Register (QBAR).
4365 ** The starting addresses of each queue is based on the Queue Base Address and the Queue Size field.
4366 ** here shows an example of how the circular queues should be set up based on the
4367 ** Intelligent I/O (I 2 O) Architecture Specification.
4368 ** Other ordering of the circular queues is possible.
4370 ** Queue Starting Address
4371 ** Inbound Free Queue QBAR
4372 ** Inbound Post Queue QBAR + Queue Size
4373 ** Outbound Post Queue QBAR + 2 * Queue Size
4374 ** Outbound Free Queue QBAR + 3 * Queue Size
4375 ** ===================================================================================
4376 ** Inbound Post Queue
4377 ** ------------------
4378 ** The Inbound Post Queue holds posted messages placed there by other processors for the Intel XScale core to process.
4379 ** This queue is read from the queue tail by the Intel XScale core. It is written to the queue head by external PCI agents.
4380 ** The tail pointer is maintained by the Intel XScale core. The head pointer is maintained by the MU hardware.
4381 ** For a PCI write transaction that accesses the Inbound Queue Port,
4382 ** the MU writes the data to the local memory location address in the Inbound Post Head Pointer Register.
4383 ** When the data written to the Inbound Queue Port is written to local memory, the MU hardware increments the Inbound Post Head Pointer Register.
4384 ** An Intel XScale core interrupt may be generated when the Inbound Post Queue is written.
4385 ** The Inbound Post Queue Interrupt bit in the Inbound Interrupt Status Register indicates the interrupt status.
4386 ** The interrupt is cleared when the Inbound Post Queue Interrupt bit is cleared.
4387 ** The interrupt can be masked by the Inbound Interrupt Mask Register.
4388 ** Software must be aware of the state of the Inbound Post Queue Interrupt Mask bit to guarantee
4389 ** that the full condition is recognized by the core processor.
4390 ** In addition, to guarantee that the queue does not get overwritten,
4391 ** software must process messages from the tail of the queue before incrementing the tail pointer and clearing this interrupt.
4392 ** Once cleared, an interrupt is NOT generated when the head and tail pointers remain unequal (i.e. queue status is Not Empty).
4393 ** Only a new message posting the in the inbound queue generates a new interrupt.
4394 ** Therefore, when software leaves any unprocessed messages in the post queue when the interrupt is cleared,
4395 ** software must retain the information that the Inbound Post queue status.
4396 ** From the time that the PCI write transaction is received until the data is written
4397 ** in local memory and the Inbound Post Head Pointer Register is incremented,
4398 ** any PCI transaction that attempts to access the Inbound Post Queue Port is signalled a Retry.
4399 ** The Intel XScale core may read messages from the Inbound Post Queue
4400 ** by reading the data from the local memory location pointed to by the Inbound Post Tail Pointer Register.
4401 ** The Intel XScale core must then increment the Inbound Post Tail Pointer Register.
4402 ** When the Inbound Post Queue is full (head and tail pointers are equal and the head pointer was last updated by hardware),
4403 ** the hardware retries any PCI writes until a slot in the queue becomes available.
4404 ** A slot in the post queue becomes available by the Intel XScale core incrementing the tail pointer.
4405 ** ===================================================================================
4406 ** Inbound Free Queue
4407 ** ------------------
4408 ** The Inbound Free Queue holds free inbound messages placed there by the Intel XScale core for other processors to use.
4409 ** This queue is read from the queue tail by external PCI agents.
4410 ** It is written to the queue head by the Intel XScale core.
4411 ** The tail pointer is maintained by the MU hardware.
4412 ** The head pointer is maintained by the Intel XScale core.
4413 ** For a PCI read transaction that accesses the Inbound Queue Port,
4414 ** the MU attempts to read the data at the local memory address in the Inbound Free Tail Pointer.
4415 ** When the queue is not empty (head and tail pointers are not equal)
4416 ** or full (head and tail pointers are equal but the head pointer was last written by software), the data is returned.
4417 ** When the queue is empty (head and tail pointers are equal and the head pointer was last updated by hardware),
4418 ** the value of -1 (FFFF.FFFFH) is returned.
4419 ** When the queue was not empty and the MU succeeded in returning the data at the tail,
4420 ** the MU hardware must increment the value in the Inbound Free Tail Pointer Register.
4421 ** To reduce latency for the PCI read access, the MU implements a prefetch mechanism to anticipate accesses to the Inbound Free Queue.
4422 ** The MU hardware prefetches the data at the tail of the Inbound Free Queue and load it into an internal prefetch register.
4423 ** When the PCI read access occurs, the data is read directly from the prefetch register.
4424 ** The prefetch mechanism loads a value of -1 (FFFF.FFFFH) into the prefetch register
4425 ** when the head and tail pointers are equal and the queue is empty.
4426 ** In order to update the prefetch register when messages are added to the queue and it becomes non-empty,
4427 ** the prefetch mechanism automatically starts a prefetch when the prefetch register contains FFFF.FFFFH
4428 ** and the Inbound Free Head Pointer Register is written.
4429 ** The Intel XScale core needs to update the Inbound Free Head Pointer Register when it adds messages to the queue.
4430 ** A prefetch must appear atomic from the perspective of the external PCI agent.
4431 ** When a prefetch is started, any PCI transaction that attempts to access the Inbound Free Queue is signalled a Retry until the prefetch is completed.
4432 ** The Intel XScale core may place messages in the Inbound Free Queue by writing the data to the
4433 ** local memory location pointed to by the Inbound Free Head Pointer Register.
4434 ** The processor must then increment the Inbound Free Head Pointer Register.
4435 ** ==================================================================================
4436 ** Outbound Post Queue
4437 ** -------------------
4438 ** The Outbound Post Queue holds outbound posted messages placed there by the Intel XScale
4439 ** core for other processors to process. This queue is read from the queue tail by external PCI agents.
4440 ** It is written to the queue head by the Intel XScale core. The tail pointer is maintained by the
4441 ** MU hardware. The head pointer is maintained by the Intel XScale core.
4442 ** For a PCI read transaction that accesses the Outbound Queue Port, the MU attempts to read the
4443 ** data at the local memory address in the Outbound Post Tail Pointer Register. When the queue is not
4444 ** empty (head and tail pointers are not equal) or full (head and tail pointers are equal but the head
4445 ** pointer was last written by software), the data is returned. When the queue is empty (head and tail
4446 ** pointers are equal and the head pointer was last updated by hardware), the value of -1
4447 ** (FFFF.FFFFH) is returned. When the queue was not empty and the MU succeeded in returning the
4448 ** data at the tail, the MU hardware must increment the value in the Outbound Post Tail Pointer
4450 ** To reduce latency for the PCI read access, the MU implements a prefetch mechanism to anticipate
4451 ** accesses to the Outbound Post Queue. The MU hardware prefetches the data at the tail of the
4452 ** Outbound Post Queue and load it into an internal prefetch register. When the PCI read access
4453 ** occurs, the data is read directly from the prefetch register.
4454 ** The prefetch mechanism loads a value of -1 (FFFF.FFFFH) into the prefetch register when the head
4455 ** and tail pointers are equal and the queue is empty. In order to update the prefetch register when
4456 ** messages are added to the queue and it becomes non-empty, the prefetch mechanism automatically
4457 ** starts a prefetch when the prefetch register contains FFFF.FFFFH and the Outbound Post Head
4458 ** Pointer Register is written. The Intel XScale core needs to update the Outbound Post Head
4459 ** Pointer Register when it adds messages to the queue.
4460 ** A prefetch must appear atomic from the perspective of the external PCI agent. When a prefetch is
4461 ** started, any PCI transaction that attempts to access the Outbound Post Queue is signalled a Retry
4462 ** until the prefetch is completed.
4463 ** A PCI interrupt may be generated when data in the prefetch buffer is valid. When the prefetch
4464 ** queue is clear, no interrupt is generated. The Outbound Post Queue Interrupt bit in the Outbound
4465 ** Interrupt Status Register shall indicate the status of the prefetch buffer data and therefore the
4466 ** interrupt status. The interrupt is cleared when any prefetched data has been read from the Outbound
4467 ** Queue Port. The interrupt can be masked by the Outbound Interrupt Mask Register.
4468 ** The Intel XScale core may place messages in the Outbound Post Queue by writing the data to
4469 ** the local memory address in the Outbound Post Head Pointer Register. The processor must then
4470 ** increment the Outbound Post Head Pointer Register.
4471 ** ==================================================
4472 ** Outbound Free Queue
4473 ** -----------------------
4474 ** The Outbound Free Queue holds free messages placed there by other processors for the Intel
4475 ** XScale core to use. This queue is read from the queue tail by the Intel XScale core. It is
4476 ** written to the queue head by external PCI agents. The tail pointer is maintained by the Intel
4477 ** XScale core. The head pointer is maintained by the MU hardware.
4478 ** For a PCI write transaction that accesses the Outbound Queue Port, the MU writes the data to the
4479 ** local memory address in the Outbound Free Head Pointer Register. When the data written to the
4480 ** Outbound Queue Port is written to local memory, the MU hardware increments the Outbound Free
4481 ** Head Pointer Register.
4482 ** When the head pointer and the tail pointer become equal and the queue is full, the MU may signal
4483 ** an interrupt to the Intel XScale core to register the queue full condition. This interrupt is
4484 ** recorded in the Inbound Interrupt Status Register. The interrupt is cleared when the Outbound Free
4485 ** Queue Full Interrupt bit is cleared and not by writing to the head or tail pointers. The interrupt can
4486 ** be masked by the Inbound Interrupt Mask Register. Software must be aware of the state of the
4487 ** Outbound Free Queue Interrupt Mask bit to guarantee that the full condition is recognized by the
4489 ** From the time that a PCI write transaction is received until the data is written in local memory and
4490 ** the Outbound Free Head Pointer Register is incremented, any PCI transaction that attempts to
4491 ** access the Outbound Free Queue Port is signalled a retry.
4492 ** The Intel XScale core may read messages from the Outbound Free Queue by reading the data
4493 ** from the local memory address in the Outbound Free Tail Pointer Register. The processor must
4494 ** then increment the Outbound Free Tail Pointer Register. When the Outbound Free Queue is full,
4495 ** the hardware must retry any PCI writes until a slot in the queue becomes available.
4497 ** ==================================================================================
4498 ** Circular Queue Summary
4499 ** ----------------------
4500 ** ________________________________________________________________________________________________________________________________________________
4501 ** | Queue Name | PCI Port |Generate PCI Interrupt |Generate Intel Xscale Core Interrupt|Head Pointer maintained by|Tail Pointer maintained by|
4502 ** |_____________|_______________|_______________________|____________________________________|__________________________|__________________________|
4503 ** |Inbound Post | Inbound Queue | | | | |
4504 ** | Queue | Port | NO | Yes, when queue is written | MU hardware | Intel XScale |
4505 ** |_____________|_______________|_______________________|____________________________________|__________________________|__________________________|
4506 ** |Inbound Free | Inbound Queue | | | | |
4507 ** | Queue | Port | NO | NO | Intel XScale | MU hardware |
4508 ** |_____________|_______________|_______________________|____________________________________|__________________________|__________________________|
4509 ** ==================================================================================
4510 ** Circular Queue Status Summary
4511 ** ----------------------
4512 ** ____________________________________________________________________________________________________
4513 ** | Queue Name | Queue Status | Head & Tail Pointer | Last Pointer Update |
4514 ** |_____________________|________________|_____________________|_______________________________________|
4515 ** | Inbound Post Queue | Empty | Equal | Tail pointer last updated by software |
4516 ** |_____________________|________________|_____________________|_______________________________________|
4517 ** | Inbound Free Queue | Empty | Equal | Head pointer last updated by hardware |
4518 ** |_____________________|________________|_____________________|_______________________________________|
4519 **************************************************************************
4523 **************************************************************************
4525 ** ========================
4526 ** . The Index Registers are a set of 1004 registers that when written by an external PCI agent can generate an interrupt to the Intel XScale core.
4527 ** These registers are for inbound messages only.
4528 ** The interrupt is recorded in the Inbound Interrupt Status Register.
4529 ** The storage for the Index Registers is allocated from the 80331 local memory.
4530 ** PCI write accesses to the Index Registers write the data to local memory.
4531 ** PCI read accesses to the Index Registers read the data from local memory.
4532 ** . The local memory used for the Index Registers ranges from Inbound ATU Translate Value Register + 050H
4533 ** to Inbound ATU Translate Value Register + FFFH.
4534 ** . The address of the first write access is stored in the Index Address Register.
4535 ** This register is written during the earliest write access and provides a means to determine which Index Register was written.
4536 ** Once updated by the MU, the Index Address Register is not updated until the Index Register
4537 ** Interrupt bit in the Inbound Interrupt Status Register is cleared.
4538 ** . When the interrupt is cleared, the Index Address Register is re-enabled and stores the address of the next Index Register write access.
4539 ** Writes by the Intel XScale core to the local memory used by the Index Registers
4540 ** does not cause an interrupt and does not update the Index Address Register.
4541 ** . The index registers can be accessed with Multi-DWORD reads and single QWORD aligned writes.
4542 **************************************************************************
4545 **************************************************************************
4546 ** Messaging Unit Internal Bus Memory Map
4547 ** =======================================
4548 ** Internal Bus Address___Register Description (Name)____________________|_PCI Configuration Space Register Number_
4549 ** FFFF E300H reserved |
4551 ** FFFF E30CH reserved |
4552 ** FFFF E310H Inbound Message Register 0 | Available through
4553 ** FFFF E314H Inbound Message Register 1 | ATU Inbound Translation Window
4554 ** FFFF E318H Outbound Message Register 0 |
4555 ** FFFF E31CH Outbound Message Register 1 | or
4556 ** FFFF E320H Inbound Doorbell Register |
4557 ** FFFF E324H Inbound Interrupt Status Register | must translate PCI address to
4558 ** FFFF E328H Inbound Interrupt Mask Register | the Intel Xscale Core
4559 ** FFFF E32CH Outbound Doorbell Register | Memory-Mapped Address
4560 ** FFFF E330H Outbound Interrupt Status Register |
4561 ** FFFF E334H Outbound Interrupt Mask Register |
4562 ** ______________________________________________________________________|________________________________________
4563 ** FFFF E338H reserved |
4564 ** FFFF E33CH reserved |
4565 ** FFFF E340H reserved |
4566 ** FFFF E344H reserved |
4567 ** FFFF E348H reserved |
4568 ** FFFF E34CH reserved |
4569 ** FFFF E350H MU Configuration Register |
4570 ** FFFF E354H Queue Base Address Register |
4571 ** FFFF E358H reserved |
4572 ** FFFF E35CH reserved | must translate PCI address to
4573 ** FFFF E360H Inbound Free Head Pointer Register | the Intel Xscale Core
4574 ** FFFF E364H Inbound Free Tail Pointer Register | Memory-Mapped Address
4575 ** FFFF E368H Inbound Post Head pointer Register |
4576 ** FFFF E36CH Inbound Post Tail Pointer Register |
4577 ** FFFF E370H Outbound Free Head Pointer Register |
4578 ** FFFF E374H Outbound Free Tail Pointer Register |
4579 ** FFFF E378H Outbound Post Head pointer Register |
4580 ** FFFF E37CH Outbound Post Tail Pointer Register |
4581 ** FFFF E380H Index Address Register |
4582 ** FFFF E384H reserved |
4584 ** FFFF E3FCH reserved |
4585 ** ______________________________________________________________________|_______________________________________
4586 **************************************************************************
4589 **************************************************************************
4590 ** MU Configuration Register - MUCR FFFF.E350H
4592 ** . The MU Configuration Register (MUCR) contains the Circular Queue Enable bit and the size of one Circular Queue.
4593 ** . The Circular Queue Enable bit enables or disables the Circular Queues.
4594 ** The Circular Queues are disabled at reset to allow the software to initialize the head
4595 ** and tail pointer registers before any PCI accesses to the Queue Ports.
4596 ** . Each Circular Queue may range from 4 K entries (16 Kbytes) to 64 K entries (256 Kbytes) and there are four Circular Queues.
4597 ** ------------------------------------------------------------------------
4598 ** Bit Default Description
4599 ** 31:06 000000H 00 2 Reserved
4600 ** 05:01 00001 2 Circular Queue Size - This field determines the size of each Circular Queue.
4601 ** All four queues are the same size.
4602 ** ¡E 00001 2 - 4K Entries (16 Kbytes)
4603 ** ¡E 00010 2 - 8K Entries (32 Kbytes)
4604 ** ¡E 00100 2 - 16K Entries (64 Kbytes)
4605 ** ¡E 01000 2 - 32K Entries (128 Kbytes)
4606 ** ¡E 10000 2 - 64K Entries (256 Kbytes)
4607 ** 00 0 2 Circular Queue Enable - This bit enables or disables the Circular Queues. When clear the Circular
4608 ** Queues are disabled, however the MU accepts PCI accesses to the Circular Queue Ports but ignores
4609 ** the data for Writes and return FFFF.FFFFH for Reads. Interrupts are not generated to the core when
4610 ** disabled. When set, the Circular Queues are fully enabled.
4611 **************************************************************************
4613 #define ARCMSR_MU_CONFIGURATION_REG 0xFFFFE350
4614 #define ARCMSR_MU_CIRCULAR_QUEUE_SIZE64K 0x0020
4615 #define ARCMSR_MU_CIRCULAR_QUEUE_SIZE32K 0x0010
4616 #define ARCMSR_MU_CIRCULAR_QUEUE_SIZE16K 0x0008
4617 #define ARCMSR_MU_CIRCULAR_QUEUE_SIZE8K 0x0004
4618 #define ARCMSR_MU_CIRCULAR_QUEUE_SIZE4K 0x0002
4619 #define ARCMSR_MU_CIRCULAR_QUEUE_ENABLE 0x0001 /*0:disable 1:enable*/
4621 **************************************************************************
4622 ** Queue Base Address Register - QBAR
4624 ** . The Queue Base Address Register (QBAR) contains the local memory address of the Circular Queues.
4625 ** The base address is required to be located on a 1 Mbyte address boundary.
4626 ** . All Circular Queue head and tail pointers are based on the QBAR.
4627 ** When the head and tail pointer registers are read, the Queue Base Address is returned in the upper 12 bits.
4628 ** Writing to the upper 12 bits of the head and tail pointer registers does not affect the Queue Base Address or Queue Base Address Register.
4630 ** The QBAR must designate a range allocated to the 80331 DDR SDRAM interface
4631 ** ------------------------------------------------------------------------
4632 ** Bit Default Description
4633 ** 31:20 000H Queue Base Address - Local memory address of the circular queues.
4634 ** 19:00 00000H Reserved
4635 **************************************************************************
4637 #define ARCMSR_MU_QUEUE_BASE_ADDRESS_REG 0xFFFFE354
4639 **************************************************************************
4640 ** Inbound Free Head Pointer Register - IFHPR
4642 ** . The Inbound Free Head Pointer Register (IFHPR) contains the local memory offset from
4643 ** the Queue Base Address of the head pointer for the Inbound Free Queue.
4644 ** The Head Pointer must be aligned on a DWORD address boundary.
4645 ** When read, the Queue Base Address is provided in the upper 12 bits of the register.
4646 ** Writes to the upper 12 bits of the register are ignored.
4647 ** This register is maintained by software.
4648 ** ------------------------------------------------------------------------
4649 ** Bit Default Description
4650 ** 31:20 000H Queue Base Address - Local memory address of the circular queues.
4651 ** 19:02 0000H 00 2 Inbound Free Head Pointer - Local memory offset of the head pointer for the Inbound Free Queue.
4652 ** 01:00 00 2 Reserved
4653 **************************************************************************
4655 #define ARCMSR_MU_INBOUND_FREE_HEAD_PTR_REG 0xFFFFE360
4657 **************************************************************************
4658 ** Inbound Free Tail Pointer Register - IFTPR
4660 ** . The Inbound Free Tail Pointer Register (IFTPR) contains the local memory offset from the Queue
4661 ** Base Address of the tail pointer for the Inbound Free Queue. The Tail Pointer must be aligned on a
4662 ** DWORD address boundary. When read, the Queue Base Address is provided in the upper 12 bits
4663 ** of the register. Writes to the upper 12 bits of the register are ignored.
4664 ** ------------------------------------------------------------------------
4665 ** Bit Default Description
4666 ** 31:20 000H Queue Base Address - Local memory address of the circular queues.
4667 ** 19:02 0000H 00 2 Inbound Free Tail Pointer - Local memory offset of the tail pointer for the Inbound Free Queue.
4668 ** 01:00 00 2 Reserved
4669 **************************************************************************
4671 #define ARCMSR_MU_INBOUND_FREE_TAIL_PTR_REG 0xFFFFE364
4673 **************************************************************************
4674 ** Inbound Post Head Pointer Register - IPHPR
4676 ** . The Inbound Post Head Pointer Register (IPHPR) contains the local memory offset from the Queue
4677 ** Base Address of the head pointer for the Inbound Post Queue. The Head Pointer must be aligned on
4678 ** a DWORD address boundary. When read, the Queue Base Address is provided in the upper 12 bits
4679 ** of the register. Writes to the upper 12 bits of the register are ignored.
4680 ** ------------------------------------------------------------------------
4681 ** Bit Default Description
4682 ** 31:20 000H Queue Base Address - Local memory address of the circular queues.
4683 ** 19:02 0000H 00 2 Inbound Post Head Pointer - Local memory offset of the head pointer for the Inbound Post Queue.
4684 ** 01:00 00 2 Reserved
4685 **************************************************************************
4687 #define ARCMSR_MU_INBOUND_POST_HEAD_PTR_REG 0xFFFFE368
4689 **************************************************************************
4690 ** Inbound Post Tail Pointer Register - IPTPR
4692 ** . The Inbound Post Tail Pointer Register (IPTPR) contains the local memory offset from the Queue
4693 ** Base Address of the tail pointer for the Inbound Post Queue. The Tail Pointer must be aligned on a
4694 ** DWORD address boundary. When read, the Queue Base Address is provided in the upper 12 bits
4695 ** of the register. Writes to the upper 12 bits of the register are ignored.
4696 ** ------------------------------------------------------------------------
4697 ** Bit Default Description
4698 ** 31:20 000H Queue Base Address - Local memory address of the circular queues.
4699 ** 19:02 0000H 00 2 Inbound Post Tail Pointer - Local memory offset of the tail pointer for the Inbound Post Queue.
4700 ** 01:00 00 2 Reserved
4701 **************************************************************************
4703 #define ARCMSR_MU_INBOUND_POST_TAIL_PTR_REG 0xFFFFE36C
4705 **************************************************************************
4706 ** Index Address Register - IAR
4708 ** . The Index Address Register (IAR) contains the offset of the least recently accessed Index Register.
4709 ** It is written by the MU when the Index Registers are written by a PCI agent.
4710 ** The register is not updated until the Index Interrupt bit in the Inbound Interrupt Status Register is cleared.
4711 ** . The local memory address of the Index Register least recently accessed is computed
4712 ** by adding the Index Address Register to the Inbound ATU Translate Value Register.
4713 ** ------------------------------------------------------------------------
4714 ** Bit Default Description
4715 ** 31:12 000000H Reserved
4716 ** 11:02 00H 00 2 Index Address - is the local memory offset of the Index Register written (050H to FFCH)
4717 ** 01:00 00 2 Reserved
4718 **************************************************************************
4720 #define ARCMSR_MU_LOCAL_MEMORY_INDEX_REG 0xFFFFE380 /*1004 dwords 0x0050....0x0FFC, 4016 bytes 0x0050...0x0FFF*/
4722 **********************************************************************************************************
4723 ** RS-232 Interface for Areca Raid Controller
4724 ** The low level command interface is exclusive with VT100 terminal
4725 ** --------------------------------------------------------------------
4726 ** 1. Sequence of command execution
4727 ** --------------------------------------------------------------------
4728 ** (A) Header : 3 bytes sequence (0x5E, 0x01, 0x61)
4729 ** (B) Command block : variable length of data including length, command code, data and checksum byte
4730 ** (C) Return data : variable length of data
4731 ** --------------------------------------------------------------------
4733 ** --------------------------------------------------------------------
4734 ** (A) 1st byte : command block length (low byte)
4735 ** (B) 2nd byte : command block length (high byte)
4736 ** note ..command block length shouldn't > 2040 bytes, length excludes these two bytes
4737 ** (C) 3rd byte : command code
4738 ** (D) 4th and following bytes : variable length data bytes depends on command code
4739 ** (E) last byte : checksum byte (sum of 1st byte until last data byte)
4740 ** --------------------------------------------------------------------
4741 ** 3. Command code and associated data
4742 ** --------------------------------------------------------------------
4743 ** The following are command code defined in raid controller Command code 0x10--0x1? are used for system level management,
4744 ** no password checking is needed and should be implemented in separate well controlled utility and not for end user access.
4745 ** Command code 0x20--0x?? always check the password, password must be entered to enable these command.
4748 ** GUI_SET_SERIAL=0x10,
4752 ** GUI_CHECK_PASSWORD,
4755 ** GUI_SET_ETHERNET_ADDR,
4759 ** GUI_GET_HW_MONITOR,
4761 ** // GUI_QUICK_CREATE=0x20, (function removed)
4762 ** GUI_GET_INFO_R=0x20,
4768 ** GUI_MUTE_BEEPER=0x30,
4769 ** GUI_BEEPER_SETTING,
4770 ** GUI_SET_PASSWORD,
4771 ** GUI_HOST_INTERFACE_MODE,
4772 ** GUI_REBUILD_PRIORITY,
4773 ** GUI_MAX_ATA_MODE,
4774 ** GUI_RESET_CONTROLLER,
4775 ** GUI_COM_PORT_SETTING,
4776 ** GUI_NO_OPERATION,
4779 ** GUI_CREATE_PASS_THROUGH=0x40,
4780 ** GUI_MODIFY_PASS_THROUGH,
4781 ** GUI_DELETE_PASS_THROUGH,
4782 ** GUI_IDENTIFY_DEVICE,
4784 ** GUI_CREATE_RAIDSET=0x50,
4785 ** GUI_DELETE_RAIDSET,
4786 ** GUI_EXPAND_RAIDSET,
4787 ** GUI_ACTIVATE_RAIDSET,
4788 ** GUI_CREATE_HOT_SPARE,
4789 ** GUI_DELETE_HOT_SPARE,
4791 ** GUI_CREATE_VOLUME=0x60,
4792 ** GUI_MODIFY_VOLUME,
4793 ** GUI_DELETE_VOLUME,
4794 ** GUI_START_CHECK_VOLUME,
4795 ** GUI_STOP_CHECK_VOLUME
4798 ** Command description :
4800 ** GUI_SET_SERIAL : Set the controller serial#
4801 ** byte 0,1 : length
4802 ** byte 2 : command code 0x10
4803 ** byte 3 : password length (should be 0x0f)
4804 ** byte 4-0x13 : should be "ArEcATecHnoLogY"
4805 ** byte 0x14--0x23 : Serial number string (must be 16 bytes)
4806 ** GUI_SET_VENDOR : Set vendor string for the controller
4807 ** byte 0,1 : length
4808 ** byte 2 : command code 0x11
4809 ** byte 3 : password length (should be 0x08)
4810 ** byte 4-0x13 : should be "ArEcAvAr"
4811 ** byte 0x14--0x3B : vendor string (must be 40 bytes)
4812 ** GUI_SET_MODEL : Set the model name of the controller
4813 ** byte 0,1 : length
4814 ** byte 2 : command code 0x12
4815 ** byte 3 : password length (should be 0x08)
4816 ** byte 4-0x13 : should be "ArEcAvAr"
4817 ** byte 0x14--0x1B : model string (must be 8 bytes)
4818 ** GUI_IDENTIFY : Identify device
4819 ** byte 0,1 : length
4820 ** byte 2 : command code 0x13
4821 ** return "Areca RAID Subsystem "
4822 ** GUI_CHECK_PASSWORD : Verify password
4823 ** byte 0,1 : length
4824 ** byte 2 : command code 0x14
4825 ** byte 3 : password length
4826 ** byte 4-0x?? : user password to be checked
4827 ** GUI_LOGOUT : Logout GUI (force password checking on next command)
4828 ** byte 0,1 : length
4829 ** byte 2 : command code 0x15
4830 ** GUI_HTTP : HTTP interface (reserved for Http proxy service)(0x16)
4832 ** GUI_SET_ETHERNET_ADDR : Set the ethernet MAC address
4833 ** byte 0,1 : length
4834 ** byte 2 : command code 0x17
4835 ** byte 3 : password length (should be 0x08)
4836 ** byte 4-0x13 : should be "ArEcAvAr"
4837 ** byte 0x14--0x19 : Ethernet MAC address (must be 6 bytes)
4838 ** GUI_SET_LOGO : Set logo in HTTP
4839 ** byte 0,1 : length
4840 ** byte 2 : command code 0x18
4841 ** byte 3 : Page# (0/1/2/3) (0xff --> clear OEM logo)
4842 ** byte 4/5/6/7 : 0x55/0xaa/0xa5/0x5a
4843 ** byte 8 : TITLE.JPG data (each page must be 2000 bytes)
4844 ** note .... page0 1st 2 byte must be actual length of the JPG file
4845 ** GUI_POLL_EVENT : Poll If Event Log Changed
4846 ** byte 0,1 : length
4847 ** byte 2 : command code 0x19
4848 ** GUI_GET_EVENT : Read Event
4849 ** byte 0,1 : length
4850 ** byte 2 : command code 0x1a
4851 ** byte 3 : Event Page (0:1st page/1/2/3:last page)
4852 ** GUI_GET_HW_MONITOR : Get HW monitor data
4853 ** byte 0,1 : length
4854 ** byte 2 : command code 0x1b
4855 ** byte 3 : # of FANs(example 2)
4856 ** byte 4 : # of Voltage sensor(example 3)
4857 ** byte 5 : # of temperature sensor(example 2)
4858 ** byte 6 : # of power
4859 ** byte 7/8 : Fan#0 (RPM)
4860 ** byte 9/10 : Fan#1
4861 ** byte 11/12 : Voltage#0 original value in *1000
4862 ** byte 13/14 : Voltage#0 value
4863 ** byte 15/16 : Voltage#1 org
4864 ** byte 17/18 : Voltage#1
4865 ** byte 19/20 : Voltage#2 org
4866 ** byte 21/22 : Voltage#2
4869 ** byte 25 : Power indicator (bit0 : power#0, bit1 : power#1)
4870 ** byte 26 : UPS indicator
4871 ** GUI_QUICK_CREATE : Quick create raid/volume set
4872 ** byte 0,1 : length
4873 ** byte 2 : command code 0x20
4874 ** byte 3/4/5/6 : raw capacity
4875 ** byte 7 : raid level
4876 ** byte 8 : stripe size
4878 ** byte 10/11/12/13: device mask (the devices to create raid/volume)
4879 ** This function is removed, application like to implement quick create function
4880 ** need to use GUI_CREATE_RAIDSET and GUI_CREATE_VOLUMESET function.
4881 ** GUI_GET_INFO_R : Get Raid Set Information
4882 ** byte 0,1 : length
4883 ** byte 2 : command code 0x20
4884 ** byte 3 : raidset#
4886 ** typedef struct sGUI_RAIDSET
4888 ** BYTE grsRaidSetName[16];
4889 ** DWORD grsCapacity;
4890 ** DWORD grsCapacityX;
4891 ** DWORD grsFailMask;
4892 ** BYTE grsDevArray[32];
4893 ** BYTE grsMemberDevices;
4894 ** BYTE grsNewMemberDevices;
4895 ** BYTE grsRaidState;
4897 ** BYTE grsVolumeList[16];
4901 ** BYTE grsFreeSegments;
4902 ** DWORD grsRawStripes[8];
4904 ** DWORD grsRes5; // Total to 128 bytes
4905 ** DWORD grsRes6; // Total to 128 bytes
4906 ** } sGUI_RAIDSET, *pGUI_RAIDSET;
4907 ** GUI_GET_INFO_V : Get Volume Set Information
4908 ** byte 0,1 : length
4909 ** byte 2 : command code 0x21
4910 ** byte 3 : volumeset#
4912 ** typedef struct sGUI_VOLUMESET
4914 ** BYTE gvsVolumeName[16]; // 16
4915 ** DWORD gvsCapacity;
4916 ** DWORD gvsCapacityX;
4917 ** DWORD gvsFailMask;
4918 ** DWORD gvsStripeSize;
4919 ** DWORD gvsNewFailMask;
4920 ** DWORD gvsNewStripeSize;
4921 ** DWORD gvsVolumeStatus;
4922 ** DWORD gvsProgress; // 32
4923 ** sSCSI_ATTR gvsScsi;
4924 ** BYTE gvsMemberDisks;
4925 ** BYTE gvsRaidLevel; // 8
4927 ** BYTE gvsNewMemberDisks;
4928 ** BYTE gvsNewRaidLevel;
4929 ** BYTE gvsRaidSetNumber;
4930 ** BYTE gvsRes0; // 4
4931 ** BYTE gvsRes1[4]; // 64 bytes
4932 ** } sGUI_VOLUMESET, *pGUI_VOLUMESET;
4934 ** GUI_GET_INFO_P : Get Physical Drive Information
4935 ** byte 0,1 : length
4936 ** byte 2 : command code 0x22
4937 ** byte 3 : drive # (from 0 to max-channels - 1)
4939 ** typedef struct sGUI_PHY_DRV
4941 ** BYTE gpdModelName[40];
4942 ** BYTE gpdSerialNumber[20];
4943 ** BYTE gpdFirmRev[8];
4944 ** DWORD gpdCapacity;
4945 ** DWORD gpdCapacityX; // Reserved for expansion
4946 ** BYTE gpdDeviceState;
4948 ** BYTE gpdCurrentUdmaMode;
4949 ** BYTE gpdUdmaMode;
4950 ** BYTE gpdDriveSelect;
4951 ** BYTE gpdRaidNumber; // 0xff if not belongs to a raid set
4952 ** sSCSI_ATTR gpdScsi;
4953 ** BYTE gpdReserved[40]; // Total to 128 bytes
4954 ** } sGUI_PHY_DRV, *pGUI_PHY_DRV;
4956 ** GUI_GET_INFO_S : Get System Information
4957 ** byte 0,1 : length
4958 ** byte 2 : command code 0x23
4960 ** typedef struct sCOM_ATTR
4962 ** BYTE comBaudRate;
4963 ** BYTE comDataBits;
4964 ** BYTE comStopBits;
4966 ** BYTE comFlowControl;
4967 ** } sCOM_ATTR, *pCOM_ATTR;
4969 ** typedef struct sSYSTEM_INFO
4971 ** BYTE gsiVendorName[40];
4972 ** BYTE gsiSerialNumber[16];
4973 ** BYTE gsiFirmVersion[16];
4974 ** BYTE gsiBootVersion[16];
4975 ** BYTE gsiMbVersion[16];
4976 ** BYTE gsiModelName[8];
4977 ** BYTE gsiLocalIp[4];
4978 ** BYTE gsiCurrentIp[4];
4979 ** DWORD gsiTimeTick;
4980 ** DWORD gsiCpuSpeed;
4984 ** DWORD gsiMemorySize;
4985 ** DWORD gsiMemorySpeed;
4987 ** BYTE gsiMacAddress[6];
4990 ** BYTE gsiChannelUsage;
4991 ** BYTE gsiMaxAtaMode;
4992 ** BYTE gsiSdramEcc; // 1:if ECC enabled
4993 ** BYTE gsiRebuildPriority;
4994 ** sCOM_ATTR gsiComA; // 5 bytes
4995 ** sCOM_ATTR gsiComB; // 5 bytes
4996 ** BYTE gsiIdeChannels;
4997 ** BYTE gsiScsiHostChannels;
4998 ** BYTE gsiIdeHostChannels;
4999 ** BYTE gsiMaxVolumeSet;
5000 ** BYTE gsiMaxRaidSet;
5001 ** BYTE gsiEtherPort; // 1:if ether net port supported
5002 ** BYTE gsiRaid6Engine; // 1:Raid6 engine supported
5004 ** } sSYSTEM_INFO, *pSYSTEM_INFO;
5006 ** GUI_CLEAR_EVENT : Clear System Event
5007 ** byte 0,1 : length
5008 ** byte 2 : command code 0x24
5010 ** GUI_MUTE_BEEPER : Mute current beeper
5011 ** byte 0,1 : length
5012 ** byte 2 : command code 0x30
5014 ** GUI_BEEPER_SETTING : Disable beeper
5015 ** byte 0,1 : length
5016 ** byte 2 : command code 0x31
5017 ** byte 3 : 0->disable, 1->enable
5019 ** GUI_SET_PASSWORD : Change password
5020 ** byte 0,1 : length
5021 ** byte 2 : command code 0x32
5022 ** byte 3 : pass word length ( must <= 15 )
5023 ** byte 4 : password (must be alpha-numerical)
5025 ** GUI_HOST_INTERFACE_MODE : Set host interface mode
5026 ** byte 0,1 : length
5027 ** byte 2 : command code 0x33
5028 ** byte 3 : 0->Independent, 1->cluster
5030 ** GUI_REBUILD_PRIORITY : Set rebuild priority
5031 ** byte 0,1 : length
5032 ** byte 2 : command code 0x34
5033 ** byte 3 : 0/1/2/3 (low->high)
5035 ** GUI_MAX_ATA_MODE : Set maximum ATA mode to be used
5036 ** byte 0,1 : length
5037 ** byte 2 : command code 0x35
5038 ** byte 3 : 0/1/2/3 (133/100/66/33)
5040 ** GUI_RESET_CONTROLLER : Reset Controller
5041 ** byte 0,1 : length
5042 ** byte 2 : command code 0x36
5043 ** *Response with VT100 screen (discard it)
5045 ** GUI_COM_PORT_SETTING : COM port setting
5046 ** byte 0,1 : length
5047 ** byte 2 : command code 0x37
5048 ** byte 3 : 0->COMA (term port), 1->COMB (debug port)
5049 ** byte 4 : 0/1/2/3/4/5/6/7 (1200/2400/4800/9600/19200/38400/57600/115200)
5050 ** byte 5 : data bit (0:7 bit, 1:8 bit : must be 8 bit)
5051 ** byte 6 : stop bit (0:1, 1:2 stop bits)
5052 ** byte 7 : parity (0:none, 1:off, 2:even)
5053 ** byte 8 : flow control (0:none, 1:xon/xoff, 2:hardware => must use none)
5055 ** GUI_NO_OPERATION : No operation
5056 ** byte 0,1 : length
5057 ** byte 2 : command code 0x38
5059 ** GUI_DHCP_IP : Set DHCP option and local IP address
5060 ** byte 0,1 : length
5061 ** byte 2 : command code 0x39
5062 ** byte 3 : 0:dhcp disabled, 1:dhcp enabled
5063 ** byte 4/5/6/7 : IP address
5065 ** GUI_CREATE_PASS_THROUGH : Create pass through disk
5066 ** byte 0,1 : length
5067 ** byte 2 : command code 0x40
5068 ** byte 3 : device #
5069 ** byte 4 : scsi channel (0/1)
5070 ** byte 5 : scsi id (0-->15)
5071 ** byte 6 : scsi lun (0-->7)
5072 ** byte 7 : tagged queue (1 : enabled)
5073 ** byte 8 : cache mode (1 : enabled)
5074 ** byte 9 : max speed (0/1/2/3/4, async/20/40/80/160 for scsi)
5075 ** (0/1/2/3/4, 33/66/100/133/150 for ide )
5077 ** GUI_MODIFY_PASS_THROUGH : Modify pass through disk
5078 ** byte 0,1 : length
5079 ** byte 2 : command code 0x41
5080 ** byte 3 : device #
5081 ** byte 4 : scsi channel (0/1)
5082 ** byte 5 : scsi id (0-->15)
5083 ** byte 6 : scsi lun (0-->7)
5084 ** byte 7 : tagged queue (1 : enabled)
5085 ** byte 8 : cache mode (1 : enabled)
5086 ** byte 9 : max speed (0/1/2/3/4, async/20/40/80/160 for scsi)
5087 ** (0/1/2/3/4, 33/66/100/133/150 for ide )
5089 ** GUI_DELETE_PASS_THROUGH : Delete pass through disk
5090 ** byte 0,1 : length
5091 ** byte 2 : command code 0x42
5092 ** byte 3 : device# to be deleted
5094 ** GUI_IDENTIFY_DEVICE : Identify Device
5095 ** byte 0,1 : length
5096 ** byte 2 : command code 0x43
5097 ** byte 3 : Flash Method(0:flash selected, 1:flash not selected)
5098 ** byte 4/5/6/7 : IDE device mask to be flashed
5099 ** note .... no response data available
5101 ** GUI_CREATE_RAIDSET : Create Raid Set
5102 ** byte 0,1 : length
5103 ** byte 2 : command code 0x50
5104 ** byte 3/4/5/6 : device mask
5105 ** byte 7-22 : raidset name (if byte 7 == 0:use default)
5107 ** GUI_DELETE_RAIDSET : Delete Raid Set
5108 ** byte 0,1 : length
5109 ** byte 2 : command code 0x51
5110 ** byte 3 : raidset#
5112 ** GUI_EXPAND_RAIDSET : Expand Raid Set
5113 ** byte 0,1 : length
5114 ** byte 2 : command code 0x52
5115 ** byte 3 : raidset#
5116 ** byte 4/5/6/7 : device mask for expansion
5117 ** byte 8/9/10 : (8:0 no change, 1 change, 0xff:terminate, 9:new raid level,10:new stripe size 0/1/2/3/4/5->4/8/16/32/64/128K )
5118 ** byte 11/12/13 : repeat for each volume in the raidset ....
5120 ** GUI_ACTIVATE_RAIDSET : Activate incomplete raid set
5121 ** byte 0,1 : length
5122 ** byte 2 : command code 0x53
5123 ** byte 3 : raidset#
5125 ** GUI_CREATE_HOT_SPARE : Create hot spare disk
5126 ** byte 0,1 : length
5127 ** byte 2 : command code 0x54
5128 ** byte 3/4/5/6 : device mask for hot spare creation
5130 ** GUI_DELETE_HOT_SPARE : Delete hot spare disk
5131 ** byte 0,1 : length
5132 ** byte 2 : command code 0x55
5133 ** byte 3/4/5/6 : device mask for hot spare deletion
5135 ** GUI_CREATE_VOLUME : Create volume set
5136 ** byte 0,1 : length
5137 ** byte 2 : command code 0x60
5138 ** byte 3 : raidset#
5139 ** byte 4-19 : volume set name (if byte4 == 0, use default)
5140 ** byte 20-27 : volume capacity (blocks)
5141 ** byte 28 : raid level
5142 ** byte 29 : stripe size (0/1/2/3/4/5->4/8/16/32/64/128K)
5143 ** byte 30 : channel
5146 ** byte 33 : 1 enable tag
5147 ** byte 34 : 1 enable cache
5148 ** byte 35 : speed (0/1/2/3/4->async/20/40/80/160 for scsi)
5149 ** (0/1/2/3/4->33/66/100/133/150 for IDE )
5150 ** byte 36 : 1 to select quick init
5152 ** GUI_MODIFY_VOLUME : Modify volume Set
5153 ** byte 0,1 : length
5154 ** byte 2 : command code 0x61
5155 ** byte 3 : volumeset#
5156 ** byte 4-19 : new volume set name (if byte4 == 0, not change)
5157 ** byte 20-27 : new volume capacity (reserved)
5158 ** byte 28 : new raid level
5159 ** byte 29 : new stripe size (0/1/2/3/4/5->4/8/16/32/64/128K)
5160 ** byte 30 : new channel
5162 ** byte 32 : new LUN
5163 ** byte 33 : 1 enable tag
5164 ** byte 34 : 1 enable cache
5165 ** byte 35 : speed (0/1/2/3/4->async/20/40/80/160 for scsi)
5166 ** (0/1/2/3/4->33/66/100/133/150 for IDE )
5168 ** GUI_DELETE_VOLUME : Delete volume set
5169 ** byte 0,1 : length
5170 ** byte 2 : command code 0x62
5171 ** byte 3 : volumeset#
5173 ** GUI_START_CHECK_VOLUME : Start volume consistency check
5174 ** byte 0,1 : length
5175 ** byte 2 : command code 0x63
5176 ** byte 3 : volumeset#
5178 ** GUI_STOP_CHECK_VOLUME : Stop volume consistency check
5179 ** byte 0,1 : length
5180 ** byte 2 : command code 0x64
5181 ** ---------------------------------------------------------------------
5183 ** ---------------------------------------------------------------------
5184 ** (A) Header : 3 bytes sequence (0x5E, 0x01, 0x61)
5185 ** (B) Length : 2 bytes (low byte 1st, excludes length and checksum byte)
5186 ** (C) status or data :
5187 ** <1> If length == 1 ==> 1 byte status code
5188 ** #define GUI_OK 0x41
5189 ** #define GUI_RAIDSET_NOT_NORMAL 0x42
5190 ** #define GUI_VOLUMESET_NOT_NORMAL 0x43
5191 ** #define GUI_NO_RAIDSET 0x44
5192 ** #define GUI_NO_VOLUMESET 0x45
5193 ** #define GUI_NO_PHYSICAL_DRIVE 0x46
5194 ** #define GUI_PARAMETER_ERROR 0x47
5195 ** #define GUI_UNSUPPORTED_COMMAND 0x48
5196 ** #define GUI_DISK_CONFIG_CHANGED 0x49
5197 ** #define GUI_INVALID_PASSWORD 0x4a
5198 ** #define GUI_NO_DISK_SPACE 0x4b
5199 ** #define GUI_CHECKSUM_ERROR 0x4c
5200 ** #define GUI_PASSWORD_REQUIRED 0x4d
5201 ** <2> If length > 1 ==> data block returned from controller and the contents depends on the command code
5202 ** (E) Checksum : checksum of length and status or data byte
5203 **************************************************************************
projects / FreeBSD / releng / 8.1.git / blob