2 * Copyright (c) 1998 - 2008 Søren Schmidt <sos@FreeBSD.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification, immediately at the beginning of the file.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
31 #include <sys/param.h>
32 #include <sys/module.h>
33 #include <sys/systm.h>
34 #include <sys/kernel.h>
37 #include <sys/endian.h>
38 #include <sys/malloc.h>
40 #include <sys/mutex.h>
42 #include <sys/taskqueue.h>
45 #include <machine/intr_machdep.h>
47 #include <machine/stdarg.h>
48 #include <machine/resource.h>
49 #include <machine/bus.h>
51 #include <dev/pci/pcivar.h>
52 #include <dev/pci/pcireg.h>
53 #include <dev/ata/ata-all.h>
54 #include <dev/ata/ata-pci.h>
57 /* local prototypes */
58 static int ata_serverworks_chipinit(device_t dev);
59 static int ata_serverworks_ch_attach(device_t dev);
60 static int ata_serverworks_ch_detach(device_t dev);
61 static void ata_serverworks_tf_read(struct ata_request *request);
62 static void ata_serverworks_tf_write(struct ata_request *request);
63 static int ata_serverworks_setmode(device_t dev, int target, int mode);
65 static int ata_serverworks_status(device_t dev);
76 * ServerWorks chipset support functions
79 ata_serverworks_probe(device_t dev)
81 struct ata_pci_controller *ctlr = device_get_softc(dev);
82 static struct ata_chip_id ids[] =
83 {{ ATA_ROSB4, 0x00, SWKS_33, 0, ATA_WDMA2, "ROSB4" },
84 { ATA_CSB5, 0x92, SWKS_100, 0, ATA_UDMA5, "CSB5" },
85 { ATA_CSB5, 0x00, SWKS_66, 0, ATA_UDMA4, "CSB5" },
86 { ATA_CSB6, 0x00, SWKS_100, 0, ATA_UDMA5, "CSB6" },
87 { ATA_CSB6_1, 0x00, SWKS_66, 0, ATA_UDMA4, "CSB6" },
88 { ATA_HT1000, 0x00, SWKS_100, 0, ATA_UDMA5, "HT1000" },
89 { ATA_HT1000_S1, 0x00, SWKS_MIO, 4, ATA_SA150, "HT1000" },
90 { ATA_HT1000_S2, 0x00, SWKS_MIO, 4, ATA_SA150, "HT1000" },
91 { ATA_K2, 0x00, SWKS_MIO, 4, ATA_SA150, "K2" },
92 { ATA_FRODO4, 0x00, SWKS_MIO, 4, ATA_SA150, "Frodo4" },
93 { ATA_FRODO8, 0x00, SWKS_MIO, 8, ATA_SA150, "Frodo8" },
96 if (pci_get_vendor(dev) != ATA_SERVERWORKS_ID)
99 if (!(ctlr->chip = ata_match_chip(dev, ids)))
103 ctlr->chipinit = ata_serverworks_chipinit;
104 return (BUS_PROBE_DEFAULT);
109 ata_serverworks_status(device_t dev)
111 struct ata_channel *ch = device_get_softc(dev);
112 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
115 * Check if this interrupt belongs to our channel.
117 if (!(ATA_INL(ctlr->r_res2, 0x1f80) & (1 << ch->unit)))
121 * We need to do a 4-byte read on the status reg before the values
122 * will report correctly
125 ATA_IDX_INL(ch,ATA_STATUS);
127 return ata_pci_status(dev);
132 ata_serverworks_chipinit(device_t dev)
134 struct ata_pci_controller *ctlr = device_get_softc(dev);
136 if (ata_setup_interrupt(dev, ata_generic_intr))
139 if (ctlr->chip->cfg1 == SWKS_MIO) {
140 ctlr->r_type2 = SYS_RES_MEMORY;
141 ctlr->r_rid2 = PCIR_BAR(5);
142 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
143 &ctlr->r_rid2, RF_ACTIVE)))
146 ctlr->channels = ctlr->chip->cfg2;
147 ctlr->ch_attach = ata_serverworks_ch_attach;
148 ctlr->ch_detach = ata_serverworks_ch_detach;
149 ctlr->setmode = ata_sata_setmode;
150 ctlr->getrev = ata_sata_getrev;
153 else if (ctlr->chip->cfg1 == SWKS_33) {
157 /* locate the ISA part in the southbridge and enable UDMA33 */
158 if (!device_get_children(device_get_parent(dev), &children,&nchildren)){
159 for (i = 0; i < nchildren; i++) {
160 if (pci_get_devid(children[i]) == ATA_ROSB4_ISA) {
161 pci_write_config(children[i], 0x64,
162 (pci_read_config(children[i], 0x64, 4) &
163 ~0x00002000) | 0x00004000, 4);
167 free(children, M_TEMP);
171 pci_write_config(dev, 0x5a,
172 (pci_read_config(dev, 0x5a, 1) & ~0x40) |
173 (ctlr->chip->cfg1 == SWKS_100) ? 0x03 : 0x02, 1);
175 ctlr->setmode = ata_serverworks_setmode;
180 ata_serverworks_ch_attach(device_t dev)
182 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
183 struct ata_channel *ch = device_get_softc(dev);
187 ata_pci_dmainit(dev);
189 ch_offset = ch->unit * 0x100;
191 for (i = ATA_DATA; i < ATA_MAX_RES; i++)
192 ch->r_io[i].res = ctlr->r_res2;
194 /* setup ATA registers */
195 ch->r_io[ATA_DATA].offset = ch_offset + 0x00;
196 ch->r_io[ATA_FEATURE].offset = ch_offset + 0x04;
197 ch->r_io[ATA_COUNT].offset = ch_offset + 0x08;
198 ch->r_io[ATA_SECTOR].offset = ch_offset + 0x0c;
199 ch->r_io[ATA_CYL_LSB].offset = ch_offset + 0x10;
200 ch->r_io[ATA_CYL_MSB].offset = ch_offset + 0x14;
201 ch->r_io[ATA_DRIVE].offset = ch_offset + 0x18;
202 ch->r_io[ATA_COMMAND].offset = ch_offset + 0x1c;
203 ch->r_io[ATA_CONTROL].offset = ch_offset + 0x20;
204 ata_default_registers(dev);
206 /* setup DMA registers */
207 ch->r_io[ATA_BMCMD_PORT].offset = ch_offset + 0x30;
208 ch->r_io[ATA_BMSTAT_PORT].offset = ch_offset + 0x32;
209 ch->r_io[ATA_BMDTP_PORT].offset = ch_offset + 0x34;
211 /* setup SATA registers */
212 ch->r_io[ATA_SSTATUS].offset = ch_offset + 0x40;
213 ch->r_io[ATA_SERROR].offset = ch_offset + 0x44;
214 ch->r_io[ATA_SCONTROL].offset = ch_offset + 0x48;
216 ch->flags |= ATA_NO_SLAVE;
217 ch->flags |= ATA_SATA;
219 ch->hw.tf_read = ata_serverworks_tf_read;
220 ch->hw.tf_write = ata_serverworks_tf_write;
222 ch->hw.status = ata_serverworks_status;
224 /* Make sure that our interrupt is level low */
225 powerpc_config_intr(bus_get_resource_start(device_get_parent(dev),
226 SYS_RES_IRQ, 0), INTR_TRIGGER_LEVEL, INTR_POLARITY_LOW);
229 if (ctlr->chip->chipid == ATA_K2) {
231 * The revision 1 K2 SATA controller has interesting bugs. Patch them.
232 * These magic numbers regulate interrupt delivery in the first few
233 * cases and are pure magic in the last case.
235 * Values obtained from the Darwin driver.
238 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, 0x04);
239 ATA_IDX_OUTL(ch, ATA_SERROR, 0xffffffff);
240 ATA_IDX_OUTL(ch, ATA_SCONTROL, 0x00000300);
241 ATA_OUTL(ctlr->r_res2, ch_offset + 0x88, 0);
242 ATA_OUTL(ctlr->r_res2, ch_offset + 0x80,
243 ATA_INL(ctlr->r_res2, ch_offset + 0x80) & ~0x00040000);
246 * Some controllers have a bug where they will send the command
247 * to the drive before seeing a DMA start, and then can begin
248 * receiving data before the DMA start arrives. The controller
249 * will then become confused and either corrupt the data or crash.
250 * Remedy this by starting DMA before sending the drive command.
253 ch->flags |= ATA_DMA_BEFORE_CMD;
256 /* chip does not reliably do 64K DMA transfers */
257 ch->dma.max_iosize = 64 * DEV_BSIZE;
263 ata_serverworks_ch_detach(device_t dev)
266 ata_pci_dmafini(dev);
271 ata_serverworks_tf_read(struct ata_request *request)
273 struct ata_channel *ch = device_get_softc(request->parent);
275 if (request->flags & ATA_R_48BIT) {
278 request->u.ata.count = ATA_IDX_INW(ch, ATA_COUNT);
279 temp = ATA_IDX_INW(ch, ATA_SECTOR);
280 request->u.ata.lba = (u_int64_t)(temp & 0x00ff) |
281 ((u_int64_t)(temp & 0xff00) << 24);
282 temp = ATA_IDX_INW(ch, ATA_CYL_LSB);
283 request->u.ata.lba |= ((u_int64_t)(temp & 0x00ff) << 8) |
284 ((u_int64_t)(temp & 0xff00) << 32);
285 temp = ATA_IDX_INW(ch, ATA_CYL_MSB);
286 request->u.ata.lba |= ((u_int64_t)(temp & 0x00ff) << 16) |
287 ((u_int64_t)(temp & 0xff00) << 40);
290 request->u.ata.count = ATA_IDX_INW(ch, ATA_COUNT) & 0x00ff;
291 request->u.ata.lba = (ATA_IDX_INW(ch, ATA_SECTOR) & 0x00ff) |
292 ((ATA_IDX_INW(ch, ATA_CYL_LSB) & 0x00ff) << 8) |
293 ((ATA_IDX_INW(ch, ATA_CYL_MSB) & 0x00ff) << 16) |
294 ((ATA_IDX_INW(ch, ATA_DRIVE) & 0xf) << 24);
299 ata_serverworks_tf_write(struct ata_request *request)
301 struct ata_channel *ch = device_get_softc(request->parent);
303 struct ata_device *atadev = device_get_softc(request->dev);
306 if (request->flags & ATA_R_48BIT) {
307 ATA_IDX_OUTW(ch, ATA_FEATURE, request->u.ata.feature);
308 ATA_IDX_OUTW(ch, ATA_COUNT, request->u.ata.count);
309 ATA_IDX_OUTW(ch, ATA_SECTOR, ((request->u.ata.lba >> 16) & 0xff00) |
310 (request->u.ata.lba & 0x00ff));
311 ATA_IDX_OUTW(ch, ATA_CYL_LSB, ((request->u.ata.lba >> 24) & 0xff00) |
312 ((request->u.ata.lba >> 8) & 0x00ff));
313 ATA_IDX_OUTW(ch, ATA_CYL_MSB, ((request->u.ata.lba >> 32) & 0xff00) |
314 ((request->u.ata.lba >> 16) & 0x00ff));
315 ATA_IDX_OUTW(ch, ATA_DRIVE, ATA_D_LBA | ATA_DEV(request->unit));
318 ATA_IDX_OUTW(ch, ATA_FEATURE, request->u.ata.feature);
319 ATA_IDX_OUTW(ch, ATA_COUNT, request->u.ata.count);
321 if (atadev->flags & ATA_D_USE_CHS) {
324 if (atadev->param.atavalid & ATA_FLAG_54_58) {
325 heads = atadev->param.current_heads;
326 sectors = atadev->param.current_sectors;
329 heads = atadev->param.heads;
330 sectors = atadev->param.sectors;
332 ATA_IDX_OUTW(ch, ATA_SECTOR, (request->u.ata.lba % sectors)+1);
333 ATA_IDX_OUTW(ch, ATA_CYL_LSB,
334 (request->u.ata.lba / (sectors * heads)));
335 ATA_IDX_OUTW(ch, ATA_CYL_MSB,
336 (request->u.ata.lba / (sectors * heads)) >> 8);
337 ATA_IDX_OUTW(ch, ATA_DRIVE, ATA_D_IBM | ATA_DEV(request->unit) |
338 (((request->u.ata.lba% (sectors * heads)) /
343 ATA_IDX_OUTW(ch, ATA_SECTOR, request->u.ata.lba);
344 ATA_IDX_OUTW(ch, ATA_CYL_LSB, request->u.ata.lba >> 8);
345 ATA_IDX_OUTW(ch, ATA_CYL_MSB, request->u.ata.lba >> 16);
346 ATA_IDX_OUTW(ch, ATA_DRIVE,
347 ATA_D_IBM | ATA_D_LBA | ATA_DEV(request->unit) |
348 ((request->u.ata.lba >> 24) & 0x0f));
356 ata_serverworks_setmode(device_t dev, int target, int mode)
358 device_t parent = device_get_parent(dev);
359 struct ata_pci_controller *ctlr = device_get_softc(parent);
360 struct ata_channel *ch = device_get_softc(dev);
361 int devno = (ch->unit << 1) + target;
362 int offset = (devno ^ 0x01) << 3;
364 u_int8_t piotimings[] = { 0x5d, 0x47, 0x34, 0x22, 0x20 };
365 u_int8_t dmatimings[] = { 0x77, 0x21, 0x20 };
367 mode = min(mode, ctlr->chip->max_dma);
368 if (mode >= ATA_UDMA0) {
369 /* Set UDMA mode, enable UDMA, set WDMA2/PIO4 */
370 pci_write_config(parent, 0x56,
371 (pci_read_config(parent, 0x56, 2) &
372 ~(0xf << (devno << 2))) |
373 ((mode & ATA_MODE_MASK) << (devno << 2)), 2);
374 pci_write_config(parent, 0x54,
375 pci_read_config(parent, 0x54, 1) |
377 pci_write_config(parent, 0x44,
378 (pci_read_config(parent, 0x44, 4) &
380 (dmatimings[2] << offset), 4);
382 } else if (mode >= ATA_WDMA0) {
383 /* Disable UDMA, set WDMA mode and timings, calculate PIO. */
384 pci_write_config(parent, 0x54,
385 pci_read_config(parent, 0x54, 1) &
386 ~(0x01 << devno), 1);
387 pci_write_config(parent, 0x44,
388 (pci_read_config(parent, 0x44, 4) &
390 (dmatimings[mode & ATA_MODE_MASK] << offset), 4);
391 piomode = (mode == ATA_WDMA0) ? ATA_PIO0 :
392 (mode == ATA_WDMA1) ? ATA_PIO3 : ATA_PIO4;
394 /* Disable UDMA, set requested PIO. */
395 pci_write_config(parent, 0x54,
396 pci_read_config(parent, 0x54, 1) &
397 ~(0x01 << devno), 1);
400 /* Set PIO mode and timings, calculated above. */
401 if (ctlr->chip->cfg1 != SWKS_33) {
402 pci_write_config(parent, 0x4a,
403 (pci_read_config(parent, 0x4a, 2) &
404 ~(0xf << (devno << 2))) |
405 ((piomode - ATA_PIO0) << (devno<<2)),2);
407 pci_write_config(parent, 0x40,
408 (pci_read_config(parent, 0x40, 4) &
410 (piotimings[ata_mode2idx(piomode)] << offset), 4);
414 ATA_DECLARE_DRIVER(ata_serverworks);