2 * Copyright (c) 1998 - 2008 Søren Schmidt <sos@FreeBSD.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification, immediately at the beginning of the file.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
31 #include <sys/param.h>
32 #include <sys/module.h>
33 #include <sys/systm.h>
34 #include <sys/kernel.h>
37 #include <sys/endian.h>
38 #include <sys/malloc.h>
40 #include <sys/mutex.h>
42 #include <sys/taskqueue.h>
44 #include <machine/stdarg.h>
45 #include <machine/resource.h>
46 #include <machine/bus.h>
48 #include <dev/pci/pcivar.h>
49 #include <dev/pci/pcireg.h>
50 #include <dev/ata/ata-all.h>
51 #include <dev/ata/ata-pci.h>
54 /* local prototypes */
55 static int ata_cmd_ch_attach(device_t dev);
56 static int ata_cmd_status(device_t dev);
57 static int ata_cmd_setmode(device_t dev, int target, int mode);
58 static int ata_sii_ch_attach(device_t dev);
59 static int ata_sii_ch_detach(device_t dev);
60 static int ata_sii_status(device_t dev);
61 static void ata_sii_reset(device_t dev);
62 static int ata_sii_setmode(device_t dev, int target, int mode);
63 static int ata_siiprb_ch_attach(device_t dev);
64 static int ata_siiprb_ch_detach(device_t dev);
65 static int ata_siiprb_status(device_t dev);
66 static int ata_siiprb_begin_transaction(struct ata_request *request);
67 static int ata_siiprb_end_transaction(struct ata_request *request);
68 static int ata_siiprb_pm_read(device_t dev, int port, int reg, u_int32_t *result);
69 static int ata_siiprb_pm_write(device_t dev, int port, int reg, u_int32_t result);
70 static u_int32_t ata_siiprb_softreset(device_t dev, int port);
71 static void ata_siiprb_reset(device_t dev);
72 static void ata_siiprb_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error);
73 static void ata_siiprb_dmainit(device_t dev);
79 #define SII_SETCLK 0x02
85 * Silicon Image Inc. (SiI) (former CMD) chipset support functions
88 ata_sii_probe(device_t dev)
90 struct ata_pci_controller *ctlr = device_get_softc(dev);
91 static struct ata_chip_id ids[] =
92 {{ ATA_SII3114, 0x00, SII_MEMIO, SII_4CH, ATA_SA150, "3114" },
93 { ATA_SII3512, 0x02, SII_MEMIO, 0, ATA_SA150, "3512" },
94 { ATA_SII3112, 0x02, SII_MEMIO, 0, ATA_SA150, "3112" },
95 { ATA_SII3112_1, 0x02, SII_MEMIO, 0, ATA_SA150, "3112" },
96 { ATA_SII3512, 0x00, SII_MEMIO, SII_BUG, ATA_SA150, "3512" },
97 { ATA_SII3112, 0x00, SII_MEMIO, SII_BUG, ATA_SA150, "3112" },
98 { ATA_SII3112_1, 0x00, SII_MEMIO, SII_BUG, ATA_SA150, "3112" },
99 { ATA_SII3124, 0x00, SII_PRBIO, SII_4CH, ATA_SA300, "3124" },
100 { ATA_SII3132, 0x00, SII_PRBIO, 0, ATA_SA300, "3132" },
101 { ATA_SII3132_1, 0x00, SII_PRBIO, 0, ATA_SA300, "3132" },
102 { ATA_SII3132_2, 0x00, SII_PRBIO, 0, ATA_SA300, "3132" },
103 { ATA_SII0680, 0x00, SII_MEMIO, SII_SETCLK, ATA_UDMA6, "680" },
104 { ATA_CMD649, 0x00, 0, SII_INTR, ATA_UDMA5, "(CMD) 649" },
105 { ATA_CMD648, 0x00, 0, SII_INTR, ATA_UDMA4, "(CMD) 648" },
106 { ATA_CMD646, 0x07, 0, 0, ATA_UDMA2, "(CMD) 646U2" },
107 { ATA_CMD646, 0x00, 0, 0, ATA_WDMA2, "(CMD) 646" },
108 { 0, 0, 0, 0, 0, 0}};
110 if (pci_get_vendor(dev) != ATA_SILICON_IMAGE_ID)
113 if (!(ctlr->chip = ata_match_chip(dev, ids)))
117 ctlr->chipinit = ata_sii_chipinit;
118 return (BUS_PROBE_DEFAULT);
122 ata_sii_chipinit(device_t dev)
124 struct ata_pci_controller *ctlr = device_get_softc(dev);
126 if (ata_setup_interrupt(dev, ata_generic_intr))
129 switch (ctlr->chip->cfg1) {
131 ctlr->r_type1 = SYS_RES_MEMORY;
132 ctlr->r_rid1 = PCIR_BAR(0);
133 if (!(ctlr->r_res1 = bus_alloc_resource_any(dev, ctlr->r_type1,
134 &ctlr->r_rid1, RF_ACTIVE)))
137 ctlr->r_rid2 = PCIR_BAR(2);
138 ctlr->r_type2 = SYS_RES_MEMORY;
139 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
140 &ctlr->r_rid2, RF_ACTIVE))){
141 bus_release_resource(dev, ctlr->r_type1, ctlr->r_rid1,ctlr->r_res1);
144 ctlr->ch_attach = ata_siiprb_ch_attach;
145 ctlr->ch_detach = ata_siiprb_ch_detach;
146 ctlr->reset = ata_siiprb_reset;
147 ctlr->setmode = ata_sata_setmode;
148 ctlr->getrev = ata_sata_getrev;
149 ctlr->channels = (ctlr->chip->cfg2 == SII_4CH) ? 4 : 2;
151 /* reset controller */
152 ATA_OUTL(ctlr->r_res1, 0x0040, 0x80000000);
154 ATA_OUTL(ctlr->r_res1, 0x0040, 0x0000000f);
158 ctlr->r_type2 = SYS_RES_MEMORY;
159 ctlr->r_rid2 = PCIR_BAR(5);
160 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
161 &ctlr->r_rid2, RF_ACTIVE))){
162 if (ctlr->chip->chipid != ATA_SII0680 ||
163 (pci_read_config(dev, 0x8a, 1) & 1))
167 if (ctlr->chip->cfg2 & SII_SETCLK) {
168 if ((pci_read_config(dev, 0x8a, 1) & 0x30) != 0x10)
169 pci_write_config(dev, 0x8a,
170 (pci_read_config(dev, 0x8a, 1) & 0xcf)|0x10,1);
171 if ((pci_read_config(dev, 0x8a, 1) & 0x30) != 0x10)
172 device_printf(dev, "%s could not set ATA133 clock\n",
176 /* if we have 4 channels enable the second set */
177 if (ctlr->chip->cfg2 & SII_4CH) {
178 ATA_OUTL(ctlr->r_res2, 0x0200, 0x00000002);
182 /* dont block interrupts from any channel */
183 pci_write_config(dev, 0x48,
184 (pci_read_config(dev, 0x48, 4) & ~0x03c00000), 4);
186 /* enable PCI interrupt as BIOS might not */
187 pci_write_config(dev, 0x8a, (pci_read_config(dev, 0x8a, 1) & 0x3f), 1);
190 ctlr->ch_attach = ata_sii_ch_attach;
191 ctlr->ch_detach = ata_sii_ch_detach;
194 if (ctlr->chip->max_dma >= ATA_SA150) {
195 ctlr->reset = ata_sii_reset;
196 ctlr->setmode = ata_sata_setmode;
197 ctlr->getrev = ata_sata_getrev;
200 ctlr->setmode = ata_sii_setmode;
204 if ((pci_read_config(dev, 0x51, 1) & 0x08) != 0x08) {
205 device_printf(dev, "HW has secondary channel disabled\n");
209 /* enable interrupt as BIOS might not */
210 pci_write_config(dev, 0x71, 0x01, 1);
212 ctlr->ch_attach = ata_cmd_ch_attach;
213 ctlr->ch_detach = ata_pci_ch_detach;
214 ctlr->setmode = ata_cmd_setmode;
221 ata_cmd_ch_attach(device_t dev)
223 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
224 struct ata_channel *ch = device_get_softc(dev);
226 /* setup the usual register normal pci style */
227 if (ata_pci_ch_attach(dev))
230 if (ctlr->chip->cfg2 & SII_INTR)
231 ch->hw.status = ata_cmd_status;
237 ata_cmd_status(device_t dev)
239 struct ata_channel *ch = device_get_softc(dev);
242 if (((reg71 = pci_read_config(device_get_parent(dev), 0x71, 1)) &
243 (ch->unit ? 0x08 : 0x04))) {
244 pci_write_config(device_get_parent(dev), 0x71,
245 reg71 & ~(ch->unit ? 0x04 : 0x08), 1);
246 return ata_pci_status(dev);
252 ata_cmd_setmode(device_t dev, int target, int mode)
254 device_t parent = device_get_parent(dev);
255 struct ata_pci_controller *ctlr = device_get_softc(parent);
256 struct ata_channel *ch = device_get_softc(dev);
257 int devno = (ch->unit << 1) + target;
258 int treg = 0x54 + ((devno < 3) ? (devno << 1) : 7);
259 int ureg = ch->unit ? 0x7b : 0x73;
261 uint8_t piotimings[] = { 0xa9, 0x57, 0x44, 0x32, 0x3f, 0x87, 0x32, 0x3f };
262 uint8_t udmatimings[][2] = { { 0x31, 0xc2 }, { 0x21, 0x82 },
263 { 0x11, 0x42 }, { 0x25, 0x8a },
264 { 0x15, 0x4a }, { 0x05, 0x0a } };
266 mode = min(mode, ctlr->chip->max_dma);
267 if (mode >= ATA_UDMA0) {
268 u_int8_t umode = pci_read_config(parent, ureg, 1);
270 umode &= ~(target == 0 ? 0x35 : 0xca);
271 umode |= udmatimings[mode & ATA_MODE_MASK][target];
272 pci_write_config(parent, ureg, umode, 1);
275 pci_write_config(parent, ureg,
276 pci_read_config(parent, ureg, 1) &
277 ~(target == 0 ? 0x35 : 0xca), 1);
280 pci_write_config(parent, treg, piotimings[ata_mode2idx(piomode)], 1);
285 ata_sii_ch_attach(device_t dev)
287 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
288 struct ata_channel *ch = device_get_softc(dev);
289 int unit01 = (ch->unit & 1), unit10 = (ch->unit & 2);
292 ata_pci_dmainit(dev);
294 for (i = ATA_DATA; i <= ATA_COMMAND; i++) {
295 ch->r_io[i].res = ctlr->r_res2;
296 ch->r_io[i].offset = 0x80 + i + (unit01 << 6) + (unit10 << 8);
298 ch->r_io[ATA_CONTROL].res = ctlr->r_res2;
299 ch->r_io[ATA_CONTROL].offset = 0x8a + (unit01 << 6) + (unit10 << 8);
300 ch->r_io[ATA_IDX_ADDR].res = ctlr->r_res2;
301 ata_default_registers(dev);
303 ch->r_io[ATA_BMCMD_PORT].res = ctlr->r_res2;
304 ch->r_io[ATA_BMCMD_PORT].offset = 0x00 + (unit01 << 3) + (unit10 << 8);
305 ch->r_io[ATA_BMSTAT_PORT].res = ctlr->r_res2;
306 ch->r_io[ATA_BMSTAT_PORT].offset = 0x02 + (unit01 << 3) + (unit10 << 8);
307 ch->r_io[ATA_BMDTP_PORT].res = ctlr->r_res2;
308 ch->r_io[ATA_BMDTP_PORT].offset = 0x04 + (unit01 << 3) + (unit10 << 8);
310 if (ctlr->chip->max_dma >= ATA_SA150) {
311 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2;
312 ch->r_io[ATA_SSTATUS].offset = 0x104 + (unit01 << 7) + (unit10 << 8);
313 ch->r_io[ATA_SERROR].res = ctlr->r_res2;
314 ch->r_io[ATA_SERROR].offset = 0x108 + (unit01 << 7) + (unit10 << 8);
315 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2;
316 ch->r_io[ATA_SCONTROL].offset = 0x100 + (unit01 << 7) + (unit10 << 8);
317 ch->flags |= ATA_NO_SLAVE;
318 ch->flags |= ATA_SATA;
320 /* enable PHY state change interrupt */
321 ATA_OUTL(ctlr->r_res2, 0x148 + (unit01 << 7) + (unit10 << 8),(1 << 16));
324 if (ctlr->chip->cfg2 & SII_BUG) {
325 /* work around errata in early chips */
326 ch->dma.boundary = 8192;
327 ch->dma.segsize = 15 * DEV_BSIZE;
331 ch->hw.status = ata_sii_status;
332 if (ctlr->chip->cfg2 & SII_SETCLK)
333 ch->flags |= ATA_CHECKS_CABLE;
338 ata_sii_ch_detach(device_t dev)
341 ata_pci_dmafini(dev);
346 ata_sii_status(device_t dev)
348 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
349 struct ata_channel *ch = device_get_softc(dev);
350 int offset0 = ((ch->unit & 1) << 3) + ((ch->unit & 2) << 8);
351 int offset1 = ((ch->unit & 1) << 6) + ((ch->unit & 2) << 8);
353 /* do we have any PHY events ? */
354 if (ctlr->chip->max_dma >= ATA_SA150 &&
355 (ATA_INL(ctlr->r_res2, 0x10 + offset0) & 0x00000010))
356 ata_sata_phy_check_events(dev);
358 if (ATA_INL(ctlr->r_res2, 0xa0 + offset1) & 0x00000800)
359 return ata_pci_status(dev);
365 ata_sii_reset(device_t dev)
367 if (ata_sata_phy_reset(dev, -1, 1))
368 ata_generic_reset(dev);
372 ata_sii_setmode(device_t dev, int target, int mode)
374 device_t parent = device_get_parent(dev);
375 struct ata_pci_controller *ctlr = device_get_softc(parent);
376 struct ata_channel *ch = device_get_softc(dev);
377 int rego = (ch->unit << 4) + (target << 1);
378 int mreg = ch->unit ? 0x84 : 0x80;
379 int mask = 0x03 << (target << 2);
380 int mval = pci_read_config(parent, mreg, 1) & ~mask;
382 u_int8_t preg = 0xa4 + rego;
383 u_int8_t dreg = 0xa8 + rego;
384 u_int8_t ureg = 0xac + rego;
385 u_int16_t piotimings[] = { 0x328a, 0x2283, 0x1104, 0x10c3, 0x10c1 };
386 u_int16_t dmatimings[] = { 0x2208, 0x10c2, 0x10c1 };
387 u_int8_t udmatimings[] = { 0xf, 0xb, 0x7, 0x5, 0x3, 0x2, 0x1 };
389 mode = min(mode, ctlr->chip->max_dma);
391 if (ctlr->chip->cfg2 & SII_SETCLK) {
392 if (mode > ATA_UDMA2 && (pci_read_config(parent, 0x79, 1) &
393 (ch->unit ? 0x02 : 0x01))) {
394 ata_print_cable(dev, "controller");
398 if (mode >= ATA_UDMA0) {
399 pci_write_config(parent, mreg,
400 mval | (0x03 << (target << 2)), 1);
401 pci_write_config(parent, ureg,
402 (pci_read_config(parent, ureg, 1) & ~0x3f) |
403 udmatimings[mode & ATA_MODE_MASK], 1);
405 } else if (mode >= ATA_WDMA0) {
406 pci_write_config(parent, mreg,
407 mval | (0x02 << (target << 2)), 1);
408 pci_write_config(parent, dreg, dmatimings[mode & ATA_MODE_MASK], 2);
409 piomode = (mode == ATA_WDMA0) ? ATA_PIO0 :
410 (mode == ATA_WDMA1) ? ATA_PIO3 : ATA_PIO4;
412 pci_write_config(parent, mreg,
413 mval | (0x01 << (target << 2)), 1);
416 pci_write_config(parent, preg, piotimings[ata_mode2idx(piomode)], 2);
421 struct ata_siiprb_dma_prdentry {
427 #define ATA_SIIPRB_DMA_ENTRIES 129
428 struct ata_siiprb_ata_command {
429 struct ata_siiprb_dma_prdentry prd[ATA_SIIPRB_DMA_ENTRIES];
432 struct ata_siiprb_atapi_command {
434 struct ata_siiprb_dma_prdentry prd[ATA_SIIPRB_DMA_ENTRIES];
437 struct ata_siiprb_command {
439 u_int16_t protocol_override;
440 u_int32_t transfer_count;
443 struct ata_siiprb_ata_command ata;
444 struct ata_siiprb_atapi_command atapi;
449 ata_siiprb_ch_attach(device_t dev)
451 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
452 struct ata_channel *ch = device_get_softc(dev);
453 int offset = ch->unit * 0x2000;
455 ata_siiprb_dmainit(dev);
457 /* set the SATA resources */
458 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2;
459 ch->r_io[ATA_SSTATUS].offset = 0x1f04 + offset;
460 ch->r_io[ATA_SERROR].res = ctlr->r_res2;
461 ch->r_io[ATA_SERROR].offset = 0x1f08 + offset;
462 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2;
463 ch->r_io[ATA_SCONTROL].offset = 0x1f00 + offset;
464 ch->r_io[ATA_SACTIVE].res = ctlr->r_res2;
465 ch->r_io[ATA_SACTIVE].offset = 0x1f0c + offset;
467 ch->hw.status = ata_siiprb_status;
468 ch->hw.begin_transaction = ata_siiprb_begin_transaction;
469 ch->hw.end_transaction = ata_siiprb_end_transaction;
470 ch->hw.command = NULL; /* not used here */
471 ch->hw.softreset = ata_siiprb_softreset;
472 ch->hw.pm_read = ata_siiprb_pm_read;
473 ch->hw.pm_write = ata_siiprb_pm_write;
474 ch->flags |= ATA_NO_SLAVE;
475 ch->flags |= ATA_SATA;
480 ata_siiprb_ch_detach(device_t dev)
488 ata_siiprb_status(device_t dev)
490 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
491 struct ata_channel *ch = device_get_softc(dev);
492 u_int32_t action = ATA_INL(ctlr->r_res1, 0x0044);
493 int offset = ch->unit * 0x2000;
495 if (action & (1 << ch->unit)) {
496 u_int32_t istatus = ATA_INL(ctlr->r_res2, 0x1008 + offset);
498 /* do we have any PHY events ? */
499 ata_sata_phy_check_events(dev);
501 /* clear interrupt(s) */
502 ATA_OUTL(ctlr->r_res2, 0x1008 + offset, istatus);
504 /* do we have any device action ? */
505 return (istatus & 0x00000003);
511 ata_siiprb_begin_transaction(struct ata_request *request)
513 struct ata_pci_controller *ctlr=device_get_softc(device_get_parent(request->parent));
514 struct ata_channel *ch = device_get_softc(request->parent);
515 struct ata_siiprb_command *prb;
516 struct ata_siiprb_dma_prdentry *prd;
517 int offset = ch->unit * 0x2000;
521 if (request->u.ata.command == ATA_DEVICE_RESET) {
523 return ATA_OP_FINISHED;
526 /* get a piece of the workspace for this request */
527 prb = (struct ata_siiprb_command *)ch->dma.work;
529 /* clear the prb structure */
530 bzero(prb, sizeof(struct ata_siiprb_command));
532 /* setup the FIS for this request */
533 if (!ata_request2fis_h2d(request, &prb->fis[0])) {
534 device_printf(request->parent, "setting up SATA FIS failed\n");
535 request->result = EIO;
536 return ATA_OP_FINISHED;
539 /* setup transfer type */
540 if (request->flags & ATA_R_ATAPI) {
541 bcopy(request->u.atapi.ccb, prb->u.atapi.ccb, 16);
542 if (request->flags & ATA_R_ATAPI16)
543 ATA_OUTL(ctlr->r_res2, 0x1000 + offset, 0x00000020);
545 ATA_OUTL(ctlr->r_res2, 0x1004 + offset, 0x00000020);
546 if (request->flags & ATA_R_READ)
547 prb->control = htole16(0x0010);
548 if (request->flags & ATA_R_WRITE)
549 prb->control = htole16(0x0020);
550 prd = &prb->u.atapi.prd[0];
553 prd = &prb->u.ata.prd[0];
555 /* if request moves data setup and load SG list */
556 if (request->flags & (ATA_R_READ | ATA_R_WRITE)) {
557 if (ch->dma.load(request, prd, NULL)) {
558 device_printf(request->parent, "setting up DMA failed\n");
559 request->result = EIO;
560 return ATA_OP_FINISHED;
564 /* activate the prb */
565 prb_bus = ch->dma.work_bus;
566 ATA_OUTL(ctlr->r_res2, 0x1c00 + offset, prb_bus);
567 ATA_OUTL(ctlr->r_res2, 0x1c04 + offset, prb_bus>>32);
569 /* start the timeout */
570 callout_reset(&request->callout, request->timeout * hz,
571 (timeout_t*)ata_timeout, request);
572 return ATA_OP_CONTINUES;
576 ata_siiprb_end_transaction(struct ata_request *request)
578 struct ata_pci_controller *ctlr=device_get_softc(device_get_parent(request->parent));
579 struct ata_channel *ch = device_get_softc(request->parent);
580 struct ata_siiprb_command *prb;
581 int offset = ch->unit * 0x2000;
584 /* kill the timeout */
585 callout_stop(&request->callout);
587 prb = (struct ata_siiprb_command *)
588 ((u_int8_t *)rman_get_virtual(ctlr->r_res2) + offset);
590 /* any controller errors flagged ? */
591 if ((error = ATA_INL(ctlr->r_res2, 0x1024 + offset))) {
593 printf("ata_siiprb_end_transaction %s error=%08x\n",
594 ata_cmd2str(request), error);
596 /* if device error status get details */
597 if (error == 1 || error == 2) {
598 request->status = prb->fis[2];
599 if (request->status & ATA_S_ERROR)
600 request->error = prb->fis[3];
603 /* SOS XXX handle other controller errors here */
605 /* initialize port */
606 ATA_OUTL(ctlr->r_res2, 0x1000 + offset, 0x00000004);
608 /* poll for port ready */
609 for (timeout = 0; timeout < 1000; timeout++) {
611 if (ATA_INL(ctlr->r_res2, 0x1008 + offset) & 0x00040000)
616 device_printf(ch->dev, "port initialize timeout\n");
618 device_printf(ch->dev, "port initialize time=%dms\n", timeout);
622 /* on control commands read back registers to the request struct */
623 if (request->flags & ATA_R_CONTROL) {
624 request->u.ata.count = prb->fis[12] | ((u_int16_t)prb->fis[13] << 8);
625 request->u.ata.lba = prb->fis[4] | ((u_int64_t)prb->fis[5] << 8) |
626 ((u_int64_t)prb->fis[6] << 16);
627 if (request->flags & ATA_R_48BIT)
628 request->u.ata.lba |= ((u_int64_t)prb->fis[8] << 24) |
629 ((u_int64_t)prb->fis[9] << 32) |
630 ((u_int64_t)prb->fis[10] << 40);
632 request->u.ata.lba |= ((u_int64_t)(prb->fis[7] & 0x0f) << 24);
635 /* update progress */
636 if (!(request->status & ATA_S_ERROR) && !(request->flags & ATA_R_TIMEOUT)) {
637 if (request->flags & ATA_R_READ)
638 request->donecount = prb->transfer_count;
640 request->donecount = request->bytecount;
643 /* release SG list etc */
644 ch->dma.unload(request);
646 return ATA_OP_FINISHED;
650 ata_siiprb_issue_cmd(device_t dev)
652 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
653 struct ata_channel *ch = device_get_softc(dev);
654 u_int64_t prb_bus = ch->dma.work_bus;
656 int offset = ch->unit * 0x2000;
659 /* issue command to chip */
660 ATA_OUTL(ctlr->r_res2, 0x1c00 + offset, prb_bus);
661 ATA_OUTL(ctlr->r_res2, 0x1c04 + offset, prb_bus >> 32);
663 /* poll for command finished */
664 for (timeout = 0; timeout < 10000; timeout++) {
666 if ((status = ATA_INL(ctlr->r_res2, 0x1008 + offset)) & 0x00010000)
669 // SOS XXX ATA_OUTL(ctlr->r_res2, 0x1008 + offset, 0x00010000);
670 ATA_OUTL(ctlr->r_res2, 0x1008 + offset, 0x08ff08ff);
676 device_printf(dev, "siiprb_issue_cmd time=%dms status=%08x\n",
682 ata_siiprb_pm_read(device_t dev, int port, int reg, u_int32_t *result)
684 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
685 struct ata_channel *ch = device_get_softc(dev);
686 struct ata_siiprb_command *prb = (struct ata_siiprb_command *)ch->dma.work;
687 int offset = ch->unit * 0x2000;
689 bzero(prb, sizeof(struct ata_siiprb_command));
690 prb->fis[0] = 0x27; /* host to device */
691 prb->fis[1] = 0x8f; /* command FIS to PM port */
692 prb->fis[2] = ATA_READ_PM;
695 if (ata_siiprb_issue_cmd(dev)) {
696 device_printf(dev, "error reading PM port\n");
699 prb = (struct ata_siiprb_command *)
700 ((u_int8_t *)rman_get_virtual(ctlr->r_res2) + offset);
701 *result = prb->fis[12]|(prb->fis[4]<<8)|(prb->fis[5]<<16)|(prb->fis[6]<<24);
706 ata_siiprb_pm_write(device_t dev, int port, int reg, u_int32_t value)
708 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
709 struct ata_channel *ch = device_get_softc(dev);
710 struct ata_siiprb_command *prb = (struct ata_siiprb_command *)ch->dma.work;
711 int offset = ch->unit * 0x2000;
713 bzero(prb, sizeof(struct ata_siiprb_command));
714 prb->fis[0] = 0x27; /* host to device */
715 prb->fis[1] = 0x8f; /* command FIS to PM port */
716 prb->fis[2] = ATA_WRITE_PM;
719 prb->fis[12] = value & 0xff;
720 prb->fis[4] = (value >> 8) & 0xff;
721 prb->fis[5] = (value >> 16) & 0xff;
722 prb->fis[6] = (value >> 24) & 0xff;
723 if (ata_siiprb_issue_cmd(dev)) {
724 device_printf(dev, "error writing PM port\n");
727 prb = (struct ata_siiprb_command *)
728 ((u_int8_t *)rman_get_virtual(ctlr->r_res2) + offset);
733 ata_siiprb_softreset(device_t dev, int port)
735 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
736 struct ata_channel *ch = device_get_softc(dev);
737 struct ata_siiprb_command *prb = (struct ata_siiprb_command *)ch->dma.work;
739 int offset = ch->unit * 0x2000;
741 /* setup the workspace for a soft reset command */
742 bzero(prb, sizeof(struct ata_siiprb_command));
743 prb->control = htole16(0x0080);
744 prb->fis[1] = port & 0x0f;
746 /* issue soft reset */
747 if (ata_siiprb_issue_cmd(dev))
752 /* get possible signature */
753 prb = (struct ata_siiprb_command *)
754 ((u_int8_t *)rman_get_virtual(ctlr->r_res2) + offset);
755 signature=prb->fis[12]|(prb->fis[4]<<8)|(prb->fis[5]<<16)|(prb->fis[6]<<24);
757 /* clear error bits/interrupt */
758 ATA_IDX_OUTL(ch, ATA_SERROR, 0xffffffff);
764 ata_siiprb_reset(device_t dev)
766 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
767 struct ata_channel *ch = device_get_softc(dev);
768 int offset = ch->unit * 0x2000;
769 u_int32_t status, signature;
772 /* disable interrupts */
773 ATA_OUTL(ctlr->r_res2, 0x1014 + offset, 0x000000ff);
775 /* reset channel HW */
776 ATA_OUTL(ctlr->r_res2, 0x1000 + offset, 0x00000001);
778 ATA_OUTL(ctlr->r_res2, 0x1004 + offset, 0x00000001);
781 /* poll for channel ready */
782 for (timeout = 0; timeout < 1000; timeout++) {
783 if ((status = ATA_INL(ctlr->r_res2, 0x1008 + offset)) & 0x00040000)
790 device_printf(dev, "channel HW reset timeout\n");
792 device_printf(dev, "channel HW reset time=%dms\n", timeout);
796 if (!ata_sata_phy_reset(dev, -1, 1)) {
798 device_printf(dev, "phy reset found no device\n");
803 /* issue soft reset */
804 signature = ata_siiprb_softreset(dev, ATA_PM);
806 device_printf(dev, "SIGNATURE=%08x\n", signature);
808 /* figure out whats there */
809 switch (signature >> 16) {
811 ch->devices = ATA_ATA_MASTER;
814 ch->devices = ATA_PORTMULTIPLIER;
815 ATA_OUTL(ctlr->r_res2, 0x1000 + offset, 0x2000); /* enable PM support */
816 //SOS XXX need to clear all PM status and interrupts!!!!
817 ata_pm_identify(dev);
820 ch->devices = ATA_ATAPI_MASTER;
826 device_printf(dev, "siiprb_reset devices=%08x\n", ch->devices);
829 /* clear interrupt(s) */
830 ATA_OUTL(ctlr->r_res2, 0x1008 + offset, 0x000008ff);
832 /* require explicit interrupt ack */
833 ATA_OUTL(ctlr->r_res2, 0x1000 + offset, 0x00000008);
836 ATA_OUTL(ctlr->r_res2, 0x1004 + offset, 0x00000400);
838 /* enable interrupts wanted */
839 ATA_OUTL(ctlr->r_res2, 0x1010 + offset, 0x000000ff);
843 ata_siiprb_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error)
845 struct ata_dmasetprd_args *args = xsc;
846 struct ata_siiprb_dma_prdentry *prd = args->dmatab;
849 if ((args->error = error))
852 for (i = 0; i < nsegs; i++) {
853 prd[i].addr = htole64(segs[i].ds_addr);
854 prd[i].count = htole32(segs[i].ds_len);
856 prd[i - 1].control = htole32(ATA_DMA_EOT);
857 KASSERT(nsegs <= ATA_SIIPRB_DMA_ENTRIES,("too many DMA segment entries\n"));
862 ata_siiprb_dmainit(device_t dev)
864 struct ata_channel *ch = device_get_softc(dev);
867 /* note start and stop are not used here */
868 ch->dma.setprd = ata_siiprb_dmasetprd;
869 ch->dma.max_address = BUS_SPACE_MAXADDR;
870 ch->dma.max_iosize = (ATA_SIIPRB_DMA_ENTRIES - 1) * PAGE_SIZE;
873 ATA_DECLARE_DRIVER(ata_sii);