2 * Copyright (c) 1998 - 2008 Søren Schmidt <sos@FreeBSD.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification, immediately at the beginning of the file.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
31 #include <sys/param.h>
32 #include <sys/module.h>
33 #include <sys/systm.h>
34 #include <sys/kernel.h>
37 #include <sys/endian.h>
38 #include <sys/malloc.h>
40 #include <sys/mutex.h>
42 #include <sys/taskqueue.h>
44 #include <machine/stdarg.h>
45 #include <machine/resource.h>
46 #include <machine/bus.h>
48 #include <dev/pci/pcivar.h>
49 #include <dev/pci/pcireg.h>
50 #include <dev/ata/ata-all.h>
51 #include <dev/ata/ata-pci.h>
54 /* local prototypes */
55 static int ata_via_chipinit(device_t dev);
56 static int ata_via_ch_attach(device_t dev);
57 static int ata_via_ch_detach(device_t dev);
58 static void ata_via_reset(device_t dev);
59 static int ata_via_old_setmode(device_t dev, int target, int mode);
60 static void ata_via_southbridge_fixup(device_t dev);
61 static int ata_via_new_setmode(device_t dev, int target, int mode);
62 static int ata_via_sata_ch_attach(device_t dev);
63 static int ata_via_sata_getrev(device_t dev, int target);
64 static int ata_via_sata_setmode(device_t dev, int target, int mode);
80 * VIA Technologies Inc. chipset support functions
83 ata_via_probe(device_t dev)
85 struct ata_pci_controller *ctlr = device_get_softc(dev);
86 static struct ata_chip_id ids[] =
87 {{ ATA_VIA82C586, 0x02, VIA33, 0x00, ATA_UDMA2, "82C586B" },
88 { ATA_VIA82C586, 0x00, VIA33, 0x00, ATA_WDMA2, "82C586" },
89 { ATA_VIA82C596, 0x12, VIA66, VIACLK, ATA_UDMA4, "82C596B" },
90 { ATA_VIA82C596, 0x00, VIA33, 0x00, ATA_UDMA2, "82C596" },
91 { ATA_VIA82C686, 0x40, VIA100, VIABUG, ATA_UDMA5, "82C686B"},
92 { ATA_VIA82C686, 0x10, VIA66, VIACLK, ATA_UDMA4, "82C686A" },
93 { ATA_VIA82C686, 0x00, VIA33, 0x00, ATA_UDMA2, "82C686" },
94 { ATA_VIA8231, 0x00, VIA100, VIABUG, ATA_UDMA5, "8231" },
95 { ATA_VIA8233, 0x00, VIA100, 0x00, ATA_UDMA5, "8233" },
96 { ATA_VIA8233C, 0x00, VIA100, 0x00, ATA_UDMA5, "8233C" },
97 { ATA_VIA8233A, 0x00, VIA133, 0x00, ATA_UDMA6, "8233A" },
98 { ATA_VIA8235, 0x00, VIA133, 0x00, ATA_UDMA6, "8235" },
99 { ATA_VIA8237, 0x00, VIA133, 0x00, ATA_UDMA6, "8237" },
100 { ATA_VIA8237A, 0x00, VIA133, 0x00, ATA_UDMA6, "8237A" },
101 { ATA_VIA8237S, 0x00, VIA133, 0x00, ATA_UDMA6, "8237S" },
102 { ATA_VIA8237_5372, 0x00, VIA133, 0x00, ATA_UDMA6, "8237" },
103 { ATA_VIA8237_7372, 0x00, VIA133, 0x00, ATA_UDMA6, "8237" },
104 { ATA_VIA8251, 0x00, VIA133, 0x00, ATA_UDMA6, "8251" },
105 { ATA_VIACX700, 0x00, VIA133, VIASATA, ATA_SA150, "CX700" },
106 { ATA_VIAVX800, 0x00, VIA133, VIASATA, ATA_SA150, "VX800" },
107 { ATA_VIAVX855, 0x00, VIA133, 0x00, ATA_UDMA6, "VX855" },
108 { 0, 0, 0, 0, 0, 0 }};
109 static struct ata_chip_id new_ids[] =
110 {{ ATA_VIA6410, 0x00, 0, 0x00, ATA_UDMA6, "6410" },
111 { ATA_VIA6420, 0x00, 7, 0x00, ATA_SA150, "6420" },
112 { ATA_VIA6421, 0x00, 6, VIABAR, ATA_SA150, "6421" },
113 { ATA_VIA8237A, 0x00, 7, 0x00, ATA_SA150, "8237A" },
114 { ATA_VIA8237S, 0x00, 7, 0x00, ATA_SA150, "8237S" },
115 { ATA_VIA8237_5372, 0x00, 7, 0x00, ATA_SA300, "8237" },
116 { ATA_VIA8237_7372, 0x00, 7, 0x00, ATA_SA300, "8237" },
117 { ATA_VIA8251, 0x00, 0, VIAAHCI, ATA_SA300, "8251" },
118 { 0, 0, 0, 0, 0, 0 }};
120 if (pci_get_vendor(dev) != ATA_VIA_ID)
123 if (pci_get_devid(dev) == ATA_VIA82C571 ||
124 pci_get_devid(dev) == ATA_VIACX700IDE ||
125 pci_get_devid(dev) == ATA_VIASATAIDE) {
126 if (!(ctlr->chip = ata_find_chip(dev, ids, -99)))
130 if (!(ctlr->chip = ata_match_chip(dev, new_ids)))
135 ctlr->chipinit = ata_via_chipinit;
136 return (BUS_PROBE_DEFAULT);
140 ata_via_chipinit(device_t dev)
142 struct ata_pci_controller *ctlr = device_get_softc(dev);
144 if (ata_setup_interrupt(dev, ata_generic_intr))
148 if (ctlr->chip->cfg2 & VIAAHCI) {
149 if (ata_ahci_chipinit(dev) != ENXIO)
152 /* 2 SATA without SATA registers on first channel + 1 PATA on second */
153 if (ctlr->chip->cfg2 & VIASATA) {
154 ctlr->ch_attach = ata_via_sata_ch_attach;
155 ctlr->setmode = ata_via_sata_setmode;
156 ctlr->getrev = ata_via_sata_getrev;
159 /* Legacy SATA/SATA+PATA with SATA registers in BAR(5). */
160 if (ctlr->chip->max_dma >= ATA_SA150) {
161 ctlr->r_type2 = SYS_RES_IOPORT;
162 ctlr->r_rid2 = PCIR_BAR(5);
163 if ((ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
164 &ctlr->r_rid2, RF_ACTIVE))) {
165 ctlr->ch_attach = ata_via_ch_attach;
166 ctlr->ch_detach = ata_via_ch_detach;
167 ctlr->reset = ata_via_reset;
169 if (ctlr->chip->cfg2 & VIABAR) {
171 ctlr->setmode = ata_via_new_setmode;
173 ctlr->setmode = ata_sata_setmode;
174 ctlr->getrev = ata_sata_getrev;
178 /* prepare for ATA-66 on the 82C686a and 82C596b */
179 if (ctlr->chip->cfg2 & VIACLK)
180 pci_write_config(dev, 0x50, 0x030b030b, 4);
182 /* the southbridge might need the data corruption fix */
183 if (ctlr->chip->cfg2 & VIABUG)
184 ata_via_southbridge_fixup(dev);
186 /* set fifo configuration half'n'half */
187 pci_write_config(dev, 0x43,
188 (pci_read_config(dev, 0x43, 1) & 0x90) | 0x2a, 1);
190 /* set status register read retry */
191 pci_write_config(dev, 0x44, pci_read_config(dev, 0x44, 1) | 0x08, 1);
193 /* set DMA read & end-of-sector fifo flush */
194 pci_write_config(dev, 0x46,
195 (pci_read_config(dev, 0x46, 1) & 0x0c) | 0xf0, 1);
197 /* set sector size */
198 pci_write_config(dev, 0x60, DEV_BSIZE, 2);
199 pci_write_config(dev, 0x68, DEV_BSIZE, 2);
201 ctlr->setmode = ata_via_old_setmode;
206 ata_via_ch_attach(device_t dev)
208 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
209 struct ata_channel *ch = device_get_softc(dev);
211 /* newer SATA chips has resources in one BAR for each channel */
212 if (ctlr->chip->cfg2 & VIABAR) {
213 struct resource *r_io;
216 ata_pci_dmainit(dev);
218 rid = PCIR_BAR(ch->unit);
219 if (!(r_io = bus_alloc_resource_any(device_get_parent(dev),
224 for (i = ATA_DATA; i <= ATA_COMMAND; i ++) {
225 ch->r_io[i].res = r_io;
226 ch->r_io[i].offset = i;
228 ch->r_io[ATA_CONTROL].res = r_io;
229 ch->r_io[ATA_CONTROL].offset = 2 + ATA_IOSIZE;
230 ch->r_io[ATA_IDX_ADDR].res = r_io;
231 ata_default_registers(dev);
232 for (i = ATA_BMCMD_PORT; i <= ATA_BMDTP_PORT; i++) {
233 ch->r_io[i].res = ctlr->r_res1;
234 ch->r_io[i].offset = (i - ATA_BMCMD_PORT)+(ch->unit * ATA_BMIOSIZE);
241 /* setup the usual register normal pci style */
242 if (ata_pci_ch_attach(dev))
246 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2;
247 ch->r_io[ATA_SSTATUS].offset = (ch->unit << ctlr->chip->cfg1);
248 ch->r_io[ATA_SERROR].res = ctlr->r_res2;
249 ch->r_io[ATA_SERROR].offset = 0x04 + (ch->unit << ctlr->chip->cfg1);
250 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2;
251 ch->r_io[ATA_SCONTROL].offset = 0x08 + (ch->unit << ctlr->chip->cfg1);
252 ch->flags |= ATA_NO_SLAVE;
253 ch->flags |= ATA_SATA;
255 /* XXX SOS PHY hotplug handling missing in VIA chip ?? */
256 /* XXX SOS unknown how to enable PHY state change interrupt */
261 ata_via_ch_detach(device_t dev)
263 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
264 struct ata_channel *ch = device_get_softc(dev);
266 /* newer SATA chips has resources in one BAR for each channel */
267 if (ctlr->chip->cfg2 & VIABAR) {
270 rid = PCIR_BAR(ch->unit);
271 bus_release_resource(device_get_parent(dev),
272 SYS_RES_IOPORT, rid, ch->r_io[ATA_CONTROL].res);
274 ata_pci_dmafini(dev);
277 /* setup the usual register normal pci style */
278 if (ata_pci_ch_detach(dev))
286 ata_via_reset(device_t dev)
288 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
289 struct ata_channel *ch = device_get_softc(dev);
291 if ((ctlr->chip->cfg2 & VIABAR) && (ch->unit > 1))
292 ata_generic_reset(dev);
294 if (ata_sata_phy_reset(dev, -1, 1))
295 ata_generic_reset(dev);
299 ata_via_new_setmode(device_t dev, int target, int mode)
301 device_t parent = device_get_parent(dev);
302 struct ata_pci_controller *ctlr = device_get_softc(parent);
303 struct ata_channel *ch = device_get_softc(dev);
305 if ((ctlr->chip->cfg2 & VIABAR) && (ch->unit > 1)) {
307 u_int8_t pio_timings[] = { 0xa8, 0x65, 0x65, 0x32, 0x20 };
308 u_int8_t dma_timings[] = { 0xee, 0xe8, 0xe6, 0xe4, 0xe2, 0xe1, 0xe0 };
310 /* This chip can't do WDMA. */
311 if (mode >= ATA_WDMA0 && mode < ATA_UDMA0)
313 if (mode >= ATA_UDMA0) {
314 pci_write_config(parent, 0xb3,
315 dma_timings[mode & ATA_MODE_MASK], 1);
319 pci_write_config(parent, 0xab, pio_timings[ata_mode2idx(piomode)], 1);
321 mode = ata_sata_setmode(dev, target, mode);
326 ata_via_old_setmode(device_t dev, int target, int mode)
328 device_t parent = device_get_parent(dev);
329 struct ata_pci_controller *ctlr = device_get_softc(parent);
330 struct ata_channel *ch = device_get_softc(dev);
331 int devno = (ch->unit << 1) + target;
332 int reg = 0x53 - devno;
334 uint8_t timings[] = { 0xa8, 0x65, 0x42, 0x22, 0x20, 0xa8, 0x22, 0x20 };
335 uint8_t modes[][7] = {
336 { 0xc2, 0xc1, 0xc0, 0x00, 0x00, 0x00, 0x00 }, /* VIA ATA33 */
337 { 0xee, 0xec, 0xea, 0xe9, 0xe8, 0x00, 0x00 }, /* VIA ATA66 */
338 { 0xf7, 0xf6, 0xf4, 0xf2, 0xf1, 0xf0, 0x00 }, /* VIA ATA100 */
339 { 0xf7, 0xf7, 0xf6, 0xf4, 0xf2, 0xf1, 0xf0 } }; /* VIA ATA133 */
341 mode = min(mode, ctlr->chip->max_dma);
342 /* Set UDMA timings */
343 if (mode >= ATA_UDMA0) {
344 pci_write_config(parent, reg,
345 modes[ctlr->chip->cfg1][mode & ATA_MODE_MASK], 1);
348 pci_write_config(parent, reg, 0x8b, 1);
351 /* Set WDMA/PIO timings */
352 if (ctlr->chip->cfg1 != VIA133)
353 pci_write_config(parent, reg - 0x08,timings[ata_mode2idx(piomode)], 1);
358 ata_via_southbridge_fixup(device_t dev)
363 if (device_get_children(device_get_parent(dev), &children, &nchildren))
366 for (i = 0; i < nchildren; i++) {
367 if (pci_get_devid(children[i]) == ATA_VIA8363 ||
368 pci_get_devid(children[i]) == ATA_VIA8371 ||
369 pci_get_devid(children[i]) == ATA_VIA8662 ||
370 pci_get_devid(children[i]) == ATA_VIA8361) {
371 u_int8_t reg76 = pci_read_config(children[i], 0x76, 1);
373 if ((reg76 & 0xf0) != 0xd0) {
375 "Correcting VIA config for southbridge data corruption bug\n");
376 pci_write_config(children[i], 0x75, 0x80, 1);
377 pci_write_config(children[i], 0x76, (reg76 & 0x0f) | 0xd0, 1);
382 free(children, M_TEMP);
386 ata_via_sata_ch_attach(device_t dev)
388 struct ata_channel *ch = device_get_softc(dev);
390 if (ata_pci_ch_attach(dev))
393 ch->flags |= ATA_SATA;
398 ata_via_sata_getrev(device_t dev, int target)
400 struct ata_channel *ch = device_get_softc(dev);
408 ata_via_sata_setmode(device_t dev, int target, int mode)
410 struct ata_channel *ch = device_get_softc(dev);
414 return (ata_via_old_setmode(dev, target, mode));
417 ATA_DECLARE_DRIVER(ata_via);
418 MODULE_DEPEND(ata_via, ata_ahci, 1, 1, 1);