2 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
3 * Copyright (c) 2002-2008 Atheros Communications, Inc.
5 * Permission to use, copy, modify, and/or distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
22 #include "ah_internal.h"
25 #include "ah_eeprom_v14.h"
27 #include "ar5416/ar5416.h"
28 #include "ar5416/ar5416reg.h"
29 #include "ar5416/ar5416phy.h"
31 #include "ar5416/ar5416.ini"
33 static void ar5416ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore);
34 static void ar5416WriteIni(struct ath_hal *ah,
35 const struct ieee80211_channel *chan);
36 static void ar5416SpurMitigate(struct ath_hal *ah,
37 const struct ieee80211_channel *chan);
40 ar5416AniSetup(struct ath_hal *ah)
42 static const struct ar5212AniParams aniparams = {
43 .maxNoiseImmunityLevel = 4, /* levels 0..4 */
44 .totalSizeDesired = { -55, -55, -55, -55, -62 },
45 .coarseHigh = { -14, -14, -14, -14, -12 },
46 .coarseLow = { -64, -64, -64, -64, -70 },
47 .firpwr = { -78, -78, -78, -78, -80 },
48 .maxSpurImmunityLevel = 2,
49 .cycPwrThr1 = { 2, 4, 6 },
50 .maxFirstepLevel = 2, /* levels 0..2 */
51 .firstep = { 0, 4, 8 },
60 /* NB: ANI is not enabled yet */
61 ar5212AniAttach(ah, &aniparams, &aniparams, AH_FALSE);
65 * Attach for an AR5416 part.
68 ar5416InitState(struct ath_hal_5416 *ahp5416, uint16_t devid, HAL_SOFTC sc,
69 HAL_BUS_TAG st, HAL_BUS_HANDLE sh, HAL_STATUS *status)
71 struct ath_hal_5212 *ahp;
74 ahp = &ahp5416->ah_5212;
75 ar5212InitState(ahp, devid, sc, st, sh, status);
78 /* override 5212 methods for our needs */
79 ah->ah_magic = AR5416_MAGIC;
80 ah->ah_getRateTable = ar5416GetRateTable;
81 ah->ah_detach = ar5416Detach;
84 ah->ah_reset = ar5416Reset;
85 ah->ah_phyDisable = ar5416PhyDisable;
86 ah->ah_disable = ar5416Disable;
87 ah->ah_configPCIE = ar5416ConfigPCIE;
88 ah->ah_perCalibration = ar5416PerCalibration;
89 ah->ah_perCalibrationN = ar5416PerCalibrationN,
90 ah->ah_resetCalValid = ar5416ResetCalValid,
91 ah->ah_setTxPowerLimit = ar5416SetTxPowerLimit;
92 ah->ah_setTxPower = ar5416SetTransmitPower;
93 ah->ah_setBoardValues = ar5416SetBoardValues;
95 /* Transmit functions */
96 ah->ah_stopTxDma = ar5416StopTxDma;
97 ah->ah_setupTxDesc = ar5416SetupTxDesc;
98 ah->ah_setupXTxDesc = ar5416SetupXTxDesc;
99 ah->ah_fillTxDesc = ar5416FillTxDesc;
100 ah->ah_procTxDesc = ar5416ProcTxDesc;
102 /* Receive Functions */
103 ah->ah_startPcuReceive = ar5416StartPcuReceive;
104 ah->ah_stopPcuReceive = ar5416StopPcuReceive;
105 ah->ah_setupRxDesc = ar5416SetupRxDesc;
106 ah->ah_procRxDesc = ar5416ProcRxDesc;
107 ah->ah_rxMonitor = ar5416AniPoll,
108 ah->ah_procMibEvent = ar5416ProcessMibIntr,
111 ah->ah_getDiagState = ar5416GetDiagState;
112 ah->ah_setLedState = ar5416SetLedState;
113 ah->ah_gpioCfgOutput = ar5416GpioCfgOutput;
114 ah->ah_gpioCfgInput = ar5416GpioCfgInput;
115 ah->ah_gpioGet = ar5416GpioGet;
116 ah->ah_gpioSet = ar5416GpioSet;
117 ah->ah_gpioSetIntr = ar5416GpioSetIntr;
118 ah->ah_resetTsf = ar5416ResetTsf;
119 ah->ah_getRfGain = ar5416GetRfgain;
120 ah->ah_setAntennaSwitch = ar5416SetAntennaSwitch;
121 ah->ah_setDecompMask = ar5416SetDecompMask;
122 ah->ah_setCoverageClass = ar5416SetCoverageClass;
124 ah->ah_resetKeyCacheEntry = ar5416ResetKeyCacheEntry;
125 ah->ah_setKeyCacheEntry = ar5416SetKeyCacheEntry;
127 /* Power Management Functions */
128 ah->ah_setPowerMode = ar5416SetPowerMode;
130 /* Beacon Management Functions */
131 ah->ah_setBeaconTimers = ar5416SetBeaconTimers;
132 ah->ah_beaconInit = ar5416BeaconInit;
133 ah->ah_setStationBeaconTimers = ar5416SetStaBeaconTimers;
134 ah->ah_resetStationBeaconTimers = ar5416ResetStaBeaconTimers;
136 /* XXX 802.11n Functions */
138 ah->ah_chainTxDesc = ar5416ChainTxDesc;
139 ah->ah_setupFirstTxDesc = ar5416SetupFirstTxDesc;
140 ah->ah_setupLastTxDesc = ar5416SetupLastTxDesc;
141 ah->ah_set11nRateScenario = ar5416Set11nRateScenario;
142 ah->ah_set11nAggrMiddle = ar5416Set11nAggrMiddle;
143 ah->ah_clr11nAggr = ar5416Clr11nAggr;
144 ah->ah_set11nBurstDuration = ar5416Set11nBurstDuration;
145 ah->ah_get11nExtBusy = ar5416Get11nExtBusy;
146 ah->ah_set11nMac2040 = ar5416Set11nMac2040;
147 ah->ah_get11nRxClear = ar5416Get11nRxClear;
148 ah->ah_set11nRxClear = ar5416Set11nRxClear;
151 /* Interrupt functions */
152 ah->ah_isInterruptPending = ar5416IsInterruptPending;
153 ah->ah_getPendingInterrupts = ar5416GetPendingInterrupts;
154 ah->ah_setInterrupts = ar5416SetInterrupts;
156 ahp->ah_priv.ah_getWirelessModes= ar5416GetWirelessModes;
157 ahp->ah_priv.ah_eepromRead = ar5416EepromRead;
158 #ifdef AH_SUPPORT_WRITE_EEPROM
159 ahp->ah_priv.ah_eepromWrite = ar5416EepromWrite;
161 ahp->ah_priv.ah_getChipPowerLimits = ar5416GetChipPowerLimits;
163 AH5416(ah)->ah_writeIni = ar5416WriteIni;
164 AH5416(ah)->ah_spurMitigate = ar5416SpurMitigate;
166 * Start by setting all Owl devices to 2x2
168 AH5416(ah)->ah_rx_chainmask = AR5416_DEFAULT_RXCHAINMASK;
169 AH5416(ah)->ah_tx_chainmask = AR5416_DEFAULT_TXCHAINMASK;
173 ar5416GetRadioRev(struct ath_hal *ah)
178 /* Read Radio Chip Rev Extract */
179 OS_REG_WRITE(ah, AR_PHY(0x36), 0x00007058);
180 for (i = 0; i < 8; i++)
181 OS_REG_WRITE(ah, AR_PHY(0x20), 0x00010000);
182 val = (OS_REG_READ(ah, AR_PHY(256)) >> 24) & 0xff;
183 val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4);
184 return ath_hal_reverseBits(val, 8);
188 * Attach for an AR5416 part.
190 static struct ath_hal *
191 ar5416Attach(uint16_t devid, HAL_SOFTC sc,
192 HAL_BUS_TAG st, HAL_BUS_HANDLE sh, HAL_STATUS *status)
194 struct ath_hal_5416 *ahp5416;
195 struct ath_hal_5212 *ahp;
201 HALDEBUG(AH_NULL, HAL_DEBUG_ATTACH, "%s: sc %p st %p sh %p\n",
202 __func__, sc, (void*) st, (void*) sh);
204 /* NB: memory is returned zero'd */
205 ahp5416 = ath_hal_malloc(sizeof (struct ath_hal_5416) +
206 /* extra space for Owl 2.1/2.2 WAR */
209 if (ahp5416 == AH_NULL) {
210 HALDEBUG(AH_NULL, HAL_DEBUG_ANY,
211 "%s: cannot allocate memory for state block\n", __func__);
212 *status = HAL_ENOMEM;
215 ar5416InitState(ahp5416, devid, sc, st, sh, status);
216 ahp = &ahp5416->ah_5212;
217 ah = &ahp->ah_priv.h;
219 if (!ar5416SetResetReg(ah, HAL_RESET_POWER_ON)) {
221 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't reset chip\n", __func__);
226 if (!ar5416SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) {
227 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't wakeup chip\n", __func__);
231 /* Read Revisions from Chips before taking out of reset */
232 val = OS_REG_READ(ah, AR_SREV) & AR_SREV_ID;
233 AH_PRIVATE(ah)->ah_macVersion = val >> AR_SREV_ID_S;
234 AH_PRIVATE(ah)->ah_macRev = val & AR_SREV_REVISION;
235 AH_PRIVATE(ah)->ah_ispcie = (devid == AR5416_DEVID_PCIE);
237 /* setup common ini data; rf backends handle remainder */
238 HAL_INI_INIT(&ahp->ah_ini_modes, ar5416Modes, 6);
239 HAL_INI_INIT(&ahp->ah_ini_common, ar5416Common, 2);
241 HAL_INI_INIT(&AH5416(ah)->ah_ini_bb_rfgain, ar5416BB_RfGain, 3);
242 HAL_INI_INIT(&AH5416(ah)->ah_ini_bank0, ar5416Bank0, 2);
243 HAL_INI_INIT(&AH5416(ah)->ah_ini_bank1, ar5416Bank1, 2);
244 HAL_INI_INIT(&AH5416(ah)->ah_ini_bank2, ar5416Bank2, 2);
245 HAL_INI_INIT(&AH5416(ah)->ah_ini_bank3, ar5416Bank3, 3);
246 HAL_INI_INIT(&AH5416(ah)->ah_ini_bank6, ar5416Bank6, 3);
247 HAL_INI_INIT(&AH5416(ah)->ah_ini_bank7, ar5416Bank7, 2);
248 HAL_INI_INIT(&AH5416(ah)->ah_ini_addac, ar5416Addac, 2);
250 if (!IS_5416V2_2(ah)) { /* Owl 2.1/2.0 */
252 uint32_t *data; /* NB: !const */
255 /* override CLKDRV value */
256 OS_MEMCPY(&AH5416(ah)[1], ar5416Addac, sizeof(ar5416Addac));
257 AH5416(ah)->ah_ini_addac.data = (uint32_t *) &AH5416(ah)[1];
258 HAL_INI_VAL((struct ini *)&AH5416(ah)->ah_ini_addac, 31, 1) = 0;
261 HAL_INI_INIT(&AH5416(ah)->ah_ini_pcieserdes, ar5416PciePhy, 2);
262 ar5416AttachPCIE(ah);
264 ecode = ath_hal_v14EepromAttach(ah);
268 if (!ar5416ChipReset(ah, AH_NULL)) { /* reset chip */
269 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: chip reset failed\n",
275 AH_PRIVATE(ah)->ah_phyRev = OS_REG_READ(ah, AR_PHY_CHIP_ID);
277 if (!ar5212ChipTest(ah)) {
278 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: hardware self-test failed\n",
280 ecode = HAL_ESELFTEST;
285 * Set correct Baseband to analog shift
286 * setting to access analog chips.
288 OS_REG_WRITE(ah, AR_PHY(0), 0x00000007);
290 /* Read Radio Chip Rev Extract */
291 AH_PRIVATE(ah)->ah_analog5GhzRev = ar5212GetRadioRev(ah);
292 switch (AH_PRIVATE(ah)->ah_analog5GhzRev & AR_RADIO_SREV_MAJOR) {
293 case AR_RAD5122_SREV_MAJOR: /* Fowl: 5G/2x2 */
294 case AR_RAD2122_SREV_MAJOR: /* Fowl: 2+5G/2x2 */
295 case AR_RAD2133_SREV_MAJOR: /* Fowl: 2G/3x3 */
296 case AR_RAD5133_SREV_MAJOR: /* Fowl: 2+5G/3x3 */
299 if (AH_PRIVATE(ah)->ah_analog5GhzRev == 0) {
301 * When RF_Silen is used the analog chip is reset.
302 * So when the system boots with radio switch off
303 * the RF chip rev reads back as zero and we need
304 * to use the mac+phy revs to set the radio rev.
306 AH_PRIVATE(ah)->ah_analog5GhzRev =
307 AR_RAD5133_SREV_MAJOR;
310 /* NB: silently accept anything in release code per Atheros */
312 HALDEBUG(ah, HAL_DEBUG_ANY,
313 "%s: 5G Radio Chip Rev 0x%02X is not supported by "
314 "this driver\n", __func__,
315 AH_PRIVATE(ah)->ah_analog5GhzRev);
316 ecode = HAL_ENOTSUPP;
322 * Got everything we need now to setup the capabilities.
324 if (!ar5416FillCapabilityInfo(ah)) {
329 ecode = ath_hal_eepromGet(ah, AR_EEP_MACADDR, ahp->ah_macaddr);
330 if (ecode != HAL_OK) {
331 HALDEBUG(ah, HAL_DEBUG_ANY,
332 "%s: error getting mac address from EEPROM\n", __func__);
335 /* XXX How about the serial number ? */
336 /* Read Reg Domain */
337 AH_PRIVATE(ah)->ah_currentRD =
338 ath_hal_eepromGet(ah, AR_EEP_REGDMN_0, AH_NULL);
341 * ah_miscMode is populated by ar5416FillCapabilityInfo()
342 * starting from griffin. Set here to make sure that
343 * AR_MISC_MODE_MIC_NEW_LOC_ENABLE is set before a GTK is
344 * placed into hardware.
346 if (ahp->ah_miscMode != 0)
347 OS_REG_WRITE(ah, AR_MISC_MODE, ahp->ah_miscMode);
349 rfStatus = ar2133RfAttach(ah, &ecode);
351 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: RF setup failed, status %u\n",
356 ar5416AniSetup(ah); /* Anti Noise Immunity */
357 ar5416InitNfHistBuff(AH5416(ah)->ah_cal.nfCalHist);
359 HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s: return\n", __func__);
364 ar5416Detach((struct ath_hal *) ahp);
371 ar5416Detach(struct ath_hal *ah)
373 HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s:\n", __func__);
375 HALASSERT(ah != AH_NULL);
376 HALASSERT(ah->ah_magic == AR5416_MAGIC);
381 ar5416SetPowerMode(ah, HAL_PM_FULL_SLEEP, AH_TRUE);
382 ath_hal_eepromDetach(ah);
387 ar5416AttachPCIE(struct ath_hal *ah)
389 if (AH_PRIVATE(ah)->ah_ispcie)
390 ath_hal_configPCIE(ah, AH_FALSE);
392 ath_hal_disablePCIE(ah);
396 ar5416ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore)
398 if (AH_PRIVATE(ah)->ah_ispcie && !restore) {
399 ath_hal_ini_write(ah, &AH5416(ah)->ah_ini_pcieserdes, 1, 0);
401 OS_REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
402 OS_REG_WRITE(ah, AR_WA, AR_WA_DEFAULT);
407 ar5416WriteIni(struct ath_hal *ah, const struct ieee80211_channel *chan)
409 u_int modesIndex, freqIndex;
412 /* Setup the indices for the next set of register array writes */
413 /* XXX Ignore 11n dynamic mode on the AR5416 for the moment */
414 if (IEEE80211_IS_CHAN_2GHZ(chan)) {
416 if (IEEE80211_IS_CHAN_HT40(chan))
418 else if (IEEE80211_IS_CHAN_108G(chan))
424 if (IEEE80211_IS_CHAN_HT40(chan) ||
425 IEEE80211_IS_CHAN_TURBO(chan))
431 /* Set correct Baseband to analog shift setting to access analog chips. */
432 OS_REG_WRITE(ah, AR_PHY(0), 0x00000007);
437 OS_REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO);
439 /* NB: only required for Sowl */
440 ar5416EepromSetAddac(ah, chan);
442 regWrites = ath_hal_ini_write(ah, &AH5416(ah)->ah_ini_addac, 1,
444 OS_REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC);
446 regWrites = ath_hal_ini_write(ah, &AH5212(ah)->ah_ini_modes,
447 modesIndex, regWrites);
448 regWrites = ath_hal_ini_write(ah, &AH5212(ah)->ah_ini_common,
451 /* XXX updated regWrites? */
452 AH5212(ah)->ah_rfHal->writeRegs(ah, modesIndex, freqIndex, regWrites);
456 * Convert to baseband spur frequency given input channel frequency
457 * and compute register settings below.
461 ar5416SpurMitigate(struct ath_hal *ah, const struct ieee80211_channel *chan)
463 uint16_t freq = ath_hal_gethwchannel(ah, chan);
464 static const int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
465 AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60 };
466 static const int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
467 AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60 };
468 static const int inc[4] = { 0, 100, 0, 0 };
470 int bb_spur = AR_NO_SPUR;
473 int spur_delta_phase;
475 int upper, lower, cur_vit_mask;
484 HAL_BOOL is2GHz = IEEE80211_IS_CHAN_2GHZ(chan);
486 OS_MEMZERO(mask_m, sizeof(mask_m));
487 OS_MEMZERO(mask_p, sizeof(mask_p));
490 * Need to verify range +/- 9.5 for static ht20, otherwise spur
491 * is out-of-band and can be ignored.
493 /* XXX ath9k changes */
494 for (i = 0; i < AR5416_EEPROM_MODAL_SPURS; i++) {
495 cur_bb_spur = ath_hal_getSpurChan(ah, i, is2GHz);
496 if (AR_NO_SPUR == cur_bb_spur)
498 cur_bb_spur = cur_bb_spur - (freq * 10);
499 if ((cur_bb_spur > -95) && (cur_bb_spur < 95)) {
500 bb_spur = cur_bb_spur;
504 if (AR_NO_SPUR == bb_spur)
509 tmp = OS_REG_READ(ah, AR_PHY_TIMING_CTRL4_CHAIN(0));
510 new = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
511 AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
512 AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
513 AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
515 OS_REG_WRITE(ah, AR_PHY_TIMING_CTRL4_CHAIN(0), new);
517 new = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
518 AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
519 AR_PHY_SPUR_REG_MASK_RATE_SELECT |
520 AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
521 SM(AR5416_SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
522 OS_REG_WRITE(ah, AR_PHY_SPUR_REG, new);
524 * Should offset bb_spur by +/- 10 MHz for dynamic 2040 MHz
525 * config, no offset for HT20.
526 * spur_delta_phase = bb_spur/40 * 2**21 for static ht20,
529 spur_delta_phase = ((bb_spur * 524288) / 100) &
530 AR_PHY_TIMING11_SPUR_DELTA_PHASE;
532 * in 11A mode the denominator of spur_freq_sd should be 40 and
533 * it should be 44 in 11G
535 denominator = IEEE80211_IS_CHAN_2GHZ(chan) ? 440 : 400;
536 spur_freq_sd = ((bb_spur * 2048) / denominator) & 0x3ff;
538 new = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
539 SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
540 SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
541 OS_REG_WRITE(ah, AR_PHY_TIMING11, new);
545 * ============================================
546 * pilot mask 1 [31:0] = +6..-26, no 0 bin
547 * pilot mask 2 [19:0] = +26..+7
549 * channel mask 1 [31:0] = +6..-26, no 0 bin
550 * channel mask 2 [19:0] = +26..+7
557 for (i = 0; i < 4; i++) {
561 for (bp = 0; bp < 30; bp++) {
562 if ((cur_bin > lower) && (cur_bin < upper)) {
563 pilot_mask = pilot_mask | 0x1 << bp;
564 chan_mask = chan_mask | 0x1 << bp;
569 OS_REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
570 OS_REG_WRITE(ah, chan_mask_reg[i], chan_mask);
573 /* =================================================
574 * viterbi mask 1 based on channel magnitude
576 * - mask (-27 to 27) (reg 64,0x9900 to 67,0x990c)
577 * [1 2 2 1] for -9.6 or [1 2 1] for +16
578 * - enable_mask_ppm, all bins move with freq
580 * - mask_select, 8 bits for rates (reg 67,0x990c)
581 * - mask_rate_cntl, 8 bits for rates (reg 67,0x990c)
582 * choose which mask to use mask or mask2
586 * viterbi mask 2 2nd set for per data rate puncturing
588 * - mask_select, 8 bits for rates (reg 67)
589 * - mask (-27 to 27) (reg 98,0x9988 to 101,0x9994)
590 * [1 2 2 1] for -9.6 or [1 2 1] for +16
596 for (i = 0; i < 123; i++) {
597 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
598 if ((abs(cur_vit_mask - bin)) < 75) {
603 if (cur_vit_mask < 0) {
604 mask_m[abs(cur_vit_mask / 100)] = mask_amt;
606 mask_p[cur_vit_mask / 100] = mask_amt;
612 tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
613 | (mask_m[48] << 26) | (mask_m[49] << 24)
614 | (mask_m[50] << 22) | (mask_m[51] << 20)
615 | (mask_m[52] << 18) | (mask_m[53] << 16)
616 | (mask_m[54] << 14) | (mask_m[55] << 12)
617 | (mask_m[56] << 10) | (mask_m[57] << 8)
618 | (mask_m[58] << 6) | (mask_m[59] << 4)
619 | (mask_m[60] << 2) | (mask_m[61] << 0);
620 OS_REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
621 OS_REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
623 tmp_mask = (mask_m[31] << 28)
624 | (mask_m[32] << 26) | (mask_m[33] << 24)
625 | (mask_m[34] << 22) | (mask_m[35] << 20)
626 | (mask_m[36] << 18) | (mask_m[37] << 16)
627 | (mask_m[48] << 14) | (mask_m[39] << 12)
628 | (mask_m[40] << 10) | (mask_m[41] << 8)
629 | (mask_m[42] << 6) | (mask_m[43] << 4)
630 | (mask_m[44] << 2) | (mask_m[45] << 0);
631 OS_REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
632 OS_REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
634 tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
635 | (mask_m[18] << 26) | (mask_m[18] << 24)
636 | (mask_m[20] << 22) | (mask_m[20] << 20)
637 | (mask_m[22] << 18) | (mask_m[22] << 16)
638 | (mask_m[24] << 14) | (mask_m[24] << 12)
639 | (mask_m[25] << 10) | (mask_m[26] << 8)
640 | (mask_m[27] << 6) | (mask_m[28] << 4)
641 | (mask_m[29] << 2) | (mask_m[30] << 0);
642 OS_REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
643 OS_REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
645 tmp_mask = (mask_m[ 0] << 30) | (mask_m[ 1] << 28)
646 | (mask_m[ 2] << 26) | (mask_m[ 3] << 24)
647 | (mask_m[ 4] << 22) | (mask_m[ 5] << 20)
648 | (mask_m[ 6] << 18) | (mask_m[ 7] << 16)
649 | (mask_m[ 8] << 14) | (mask_m[ 9] << 12)
650 | (mask_m[10] << 10) | (mask_m[11] << 8)
651 | (mask_m[12] << 6) | (mask_m[13] << 4)
652 | (mask_m[14] << 2) | (mask_m[15] << 0);
653 OS_REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
654 OS_REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
656 tmp_mask = (mask_p[15] << 28)
657 | (mask_p[14] << 26) | (mask_p[13] << 24)
658 | (mask_p[12] << 22) | (mask_p[11] << 20)
659 | (mask_p[10] << 18) | (mask_p[ 9] << 16)
660 | (mask_p[ 8] << 14) | (mask_p[ 7] << 12)
661 | (mask_p[ 6] << 10) | (mask_p[ 5] << 8)
662 | (mask_p[ 4] << 6) | (mask_p[ 3] << 4)
663 | (mask_p[ 2] << 2) | (mask_p[ 1] << 0);
664 OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
665 OS_REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
667 tmp_mask = (mask_p[30] << 28)
668 | (mask_p[29] << 26) | (mask_p[28] << 24)
669 | (mask_p[27] << 22) | (mask_p[26] << 20)
670 | (mask_p[25] << 18) | (mask_p[24] << 16)
671 | (mask_p[23] << 14) | (mask_p[22] << 12)
672 | (mask_p[21] << 10) | (mask_p[20] << 8)
673 | (mask_p[19] << 6) | (mask_p[18] << 4)
674 | (mask_p[17] << 2) | (mask_p[16] << 0);
675 OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
676 OS_REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
678 tmp_mask = (mask_p[45] << 28)
679 | (mask_p[44] << 26) | (mask_p[43] << 24)
680 | (mask_p[42] << 22) | (mask_p[41] << 20)
681 | (mask_p[40] << 18) | (mask_p[39] << 16)
682 | (mask_p[38] << 14) | (mask_p[37] << 12)
683 | (mask_p[36] << 10) | (mask_p[35] << 8)
684 | (mask_p[34] << 6) | (mask_p[33] << 4)
685 | (mask_p[32] << 2) | (mask_p[31] << 0);
686 OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
687 OS_REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
689 tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
690 | (mask_p[59] << 26) | (mask_p[58] << 24)
691 | (mask_p[57] << 22) | (mask_p[56] << 20)
692 | (mask_p[55] << 18) | (mask_p[54] << 16)
693 | (mask_p[53] << 14) | (mask_p[52] << 12)
694 | (mask_p[51] << 10) | (mask_p[50] << 8)
695 | (mask_p[49] << 6) | (mask_p[48] << 4)
696 | (mask_p[47] << 2) | (mask_p[46] << 0);
697 OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
698 OS_REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
702 * Fill all software cached or static hardware state information.
703 * Return failure if capabilities are to come from EEPROM and
707 ar5416FillCapabilityInfo(struct ath_hal *ah)
709 struct ath_hal_private *ahpriv = AH_PRIVATE(ah);
710 HAL_CAPABILITIES *pCap = &ahpriv->ah_caps;
713 /* Construct wireless mode from EEPROM */
714 pCap->halWirelessModes = 0;
715 if (ath_hal_eepromGetFlag(ah, AR_EEP_AMODE)) {
716 pCap->halWirelessModes |= HAL_MODE_11A
718 | HAL_MODE_11NA_HT40PLUS
719 | HAL_MODE_11NA_HT40MINUS
722 if (ath_hal_eepromGetFlag(ah, AR_EEP_GMODE)) {
723 pCap->halWirelessModes |= HAL_MODE_11G
725 | HAL_MODE_11NG_HT40PLUS
726 | HAL_MODE_11NG_HT40MINUS
728 pCap->halWirelessModes |= HAL_MODE_11A
730 | HAL_MODE_11NA_HT40PLUS
731 | HAL_MODE_11NA_HT40MINUS
735 pCap->halLow2GhzChan = 2312;
736 pCap->halHigh2GhzChan = 2732;
738 pCap->halLow5GhzChan = 4915;
739 pCap->halHigh5GhzChan = 6100;
741 pCap->halCipherCkipSupport = AH_FALSE;
742 pCap->halCipherTkipSupport = AH_TRUE;
743 pCap->halCipherAesCcmSupport = ath_hal_eepromGetFlag(ah, AR_EEP_AES);
745 pCap->halMicCkipSupport = AH_FALSE;
746 pCap->halMicTkipSupport = AH_TRUE;
747 pCap->halMicAesCcmSupport = ath_hal_eepromGetFlag(ah, AR_EEP_AES);
749 * Starting with Griffin TX+RX mic keys can be combined
750 * in one key cache slot.
752 pCap->halTkipMicTxRxKeySupport = AH_TRUE;
753 pCap->halChanSpreadSupport = AH_TRUE;
754 pCap->halSleepAfterBeaconBroken = AH_TRUE;
756 pCap->halCompressSupport = AH_FALSE;
757 pCap->halBurstSupport = AH_TRUE;
758 pCap->halFastFramesSupport = AH_FALSE; /* XXX? */
759 pCap->halChapTuningSupport = AH_TRUE;
760 pCap->halTurboPrimeSupport = AH_TRUE;
762 pCap->halTurboGSupport = pCap->halWirelessModes & HAL_MODE_108G;
764 pCap->halPSPollBroken = AH_TRUE; /* XXX fixed in later revs? */
765 pCap->halVEOLSupport = AH_TRUE;
766 pCap->halBssIdMaskSupport = AH_TRUE;
767 pCap->halMcastKeySrchSupport = AH_FALSE;
768 pCap->halTsfAddSupport = AH_TRUE;
770 if (ath_hal_eepromGet(ah, AR_EEP_MAXQCU, &val) == HAL_OK)
771 pCap->halTotalQueues = val;
773 pCap->halTotalQueues = HAL_NUM_TX_QUEUES;
775 if (ath_hal_eepromGet(ah, AR_EEP_KCENTRIES, &val) == HAL_OK)
776 pCap->halKeyCacheSize = val;
778 pCap->halKeyCacheSize = AR5416_KEYTABLE_SIZE;
781 pCap->halChanHalfRate = AH_FALSE; /* XXX ? */
782 pCap->halChanQuarterRate = AH_FALSE; /* XXX ? */
784 pCap->halTstampPrecision = 32;
785 pCap->halHwPhyCounterSupport = AH_TRUE;
786 pCap->halIntrMask = HAL_INT_COMMON
798 pCap->halFastCCSupport = AH_TRUE;
799 pCap->halNumGpioPins = 6;
800 pCap->halWowSupport = AH_FALSE;
801 pCap->halWowMatchPatternExact = AH_FALSE;
802 pCap->halBtCoexSupport = AH_FALSE; /* XXX need support */
803 pCap->halAutoSleepSupport = AH_FALSE;
804 #if 0 /* XXX not yet */
805 pCap->halNumAntCfg2GHz = ar5416GetNumAntConfig(ahp, HAL_FREQ_BAND_2GHZ);
806 pCap->halNumAntCfg5GHz = ar5416GetNumAntConfig(ahp, HAL_FREQ_BAND_5GHZ);
808 pCap->halHTSupport = AH_TRUE;
809 pCap->halTxChainMask = ath_hal_eepromGet(ah, AR_EEP_TXMASK, AH_NULL);
810 /* XXX CB71 uses GPIO 0 to indicate 3 rx chains */
811 pCap->halRxChainMask = ath_hal_eepromGet(ah, AR_EEP_RXMASK, AH_NULL);
812 pCap->halRtsAggrLimit = 8*1024; /* Owl 2.0 limit */
813 pCap->halMbssidAggrSupport = AH_TRUE;
814 pCap->halForcePpmSupport = AH_TRUE;
815 pCap->halEnhancedPmSupport = AH_TRUE;
816 pCap->halBssidMatchSupport = AH_TRUE;
818 if (ath_hal_eepromGetFlag(ah, AR_EEP_RFKILL) &&
819 ath_hal_eepromGet(ah, AR_EEP_RFSILENT, &ahpriv->ah_rfsilent) == HAL_OK) {
820 /* NB: enabled by default */
821 ahpriv->ah_rfkillEnabled = AH_TRUE;
822 pCap->halRfSilentSupport = AH_TRUE;
825 ahpriv->ah_rxornIsFatal = AH_FALSE;
831 ar5416Probe(uint16_t vendorid, uint16_t devid)
833 if (vendorid == ATHEROS_VENDOR_ID &&
834 (devid == AR5416_DEVID_PCI || devid == AR5416_DEVID_PCIE))
835 return "Atheros 5416";
838 AH_CHIP(AR5416, ar5416Probe, ar5416Attach);