2 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
3 * Copyright (c) 2002-2008 Atheros Communications, Inc.
5 * Permission to use, copy, modify, and/or distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
22 #include "ah_internal.h"
24 #include "ar5416/ar5416.h"
25 #include "ar5416/ar5416reg.h"
28 * Checks to see if an interrupt is pending on our NIC
30 * Returns: TRUE if an interrupt is pending
34 ar5416IsInterruptPending(struct ath_hal *ah)
38 * Some platforms trigger our ISR before applying power to
39 * the card, so make sure the INTPEND is really 1, not 0xffffffff.
41 isr = OS_REG_READ(ah, AR_INTR_ASYNC_CAUSE);
42 if (isr != AR_INTR_SPURIOUS && (isr & AR_INTR_MAC_IRQ) != 0)
45 isr = OS_REG_READ(ah, AR_INTR_SYNC_CAUSE);
46 if (isr != AR_INTR_SPURIOUS && (isr & AR_INTR_SYNC_DEFAULT))
53 * Reads the Interrupt Status Register value from the NIC, thus deasserting
54 * the interrupt line, and returns both the masked and unmasked mapped ISR
55 * values. The value returned is mapped to abstract the hw-specific bit
56 * locations in the Interrupt Status Register.
58 * Returns: A hardware-abstracted bitmap of all non-masked-out
59 * interrupts pending, as well as an unmasked value
62 ar5416GetPendingInterrupts(struct ath_hal *ah, HAL_INT *masked)
64 uint32_t isr, isr0, isr1, sync_cause;
67 * Verify there's a mac interrupt and the RTC is on.
69 if ((OS_REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) &&
70 (OS_REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M) == AR_RTC_STATUS_ON)
71 isr = OS_REG_READ(ah, AR_ISR);
74 sync_cause = OS_REG_READ(ah, AR_INTR_SYNC_CAUSE);
75 sync_cause &= AR_INTR_SYNC_DEFAULT;
76 if (isr == 0 && sync_cause == 0) {
82 struct ath_hal_5212 *ahp = AH5212(ah);
86 if (isr & AR_ISR_BCNMISC) {
87 uint32_t isr2 = OS_REG_READ(ah, AR_ISR_S2);
88 if (isr2 & AR_ISR_S2_TIM)
90 if (isr2 & AR_ISR_S2_DTIM)
91 mask2 |= HAL_INT_DTIM;
92 if (isr2 & AR_ISR_S2_DTIMSYNC)
93 mask2 |= HAL_INT_DTIMSYNC;
94 if (isr2 & (AR_ISR_S2_CABEND ))
95 mask2 |= HAL_INT_CABEND;
96 if (isr2 & AR_ISR_S2_GTT)
98 if (isr2 & AR_ISR_S2_CST)
100 if (isr2 & AR_ISR_S2_TSFOOR)
101 mask2 |= HAL_INT_TSFOOR;
104 isr = OS_REG_READ(ah, AR_ISR_RAC);
105 if (isr == 0xffffffff) {
110 *masked = isr & HAL_INT_COMMON;
111 if (isr & (AR_ISR_RXOK | AR_ISR_RXERR))
112 *masked |= HAL_INT_RX;
113 if (isr & (AR_ISR_TXOK | AR_ISR_TXDESC | AR_ISR_TXERR | AR_ISR_TXEOL)) {
114 *masked |= HAL_INT_TX;
115 isr0 = OS_REG_READ(ah, AR_ISR_S0_S);
116 ahp->ah_intrTxqs |= MS(isr0, AR_ISR_S0_QCU_TXOK);
117 ahp->ah_intrTxqs |= MS(isr0, AR_ISR_S0_QCU_TXDESC);
118 isr1 = OS_REG_READ(ah, AR_ISR_S1_S);
119 ahp->ah_intrTxqs |= MS(isr1, AR_ISR_S1_QCU_TXERR);
120 ahp->ah_intrTxqs |= MS(isr1, AR_ISR_S1_QCU_TXEOL);
123 if (AR_SREV_MERLIN(ah) || AR_SREV_KITE(ah)) {
125 isr5 = OS_REG_READ(ah, AR_ISR_S5_S);
126 if (isr5 & AR_ISR_S5_TIM_TIMER)
127 *masked |= HAL_INT_TIM_TIMER;
130 /* Interrupt Mitigation on AR5416 */
131 #ifdef AR5416_INT_MITIGATION
132 if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM))
133 *masked |= HAL_INT_RX;
134 if (isr & (AR_ISR_TXMINTR | AR_ISR_TXINTM))
135 *masked |= HAL_INT_TX;
139 if (sync_cause != 0) {
140 if (sync_cause & (AR_INTR_SYNC_HOST1_FATAL | AR_INTR_SYNC_HOST1_PERR)) {
141 *masked |= HAL_INT_FATAL;
143 if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) {
144 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: RADM CPL timeout\n",
146 OS_REG_WRITE(ah, AR_RC, AR_RC_HOSTIF);
147 OS_REG_WRITE(ah, AR_RC, 0);
148 *masked |= HAL_INT_FATAL;
151 * On fatal errors collect ISR state for debugging.
153 if (*masked & HAL_INT_FATAL) {
154 AH_PRIVATE(ah)->ah_fatalState[0] = isr;
155 AH_PRIVATE(ah)->ah_fatalState[1] = sync_cause;
156 HALDEBUG(ah, HAL_DEBUG_ANY,
157 "%s: fatal error, ISR_RAC 0x%x SYNC_CAUSE 0x%x\n",
158 __func__, isr, sync_cause);
161 OS_REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause);
162 /* NB: flush write */
163 (void) OS_REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR);
169 * Atomically enables NIC interrupts. Interrupts are passed in
170 * via the enumerated bitmask in ints.
173 ar5416SetInterrupts(struct ath_hal *ah, HAL_INT ints)
175 struct ath_hal_5212 *ahp = AH5212(ah);
176 uint32_t omask = ahp->ah_maskReg;
177 uint32_t mask, mask2;
179 HALDEBUG(ah, HAL_DEBUG_INTERRUPT, "%s: 0x%x => 0x%x\n",
180 __func__, omask, ints);
182 if (omask & HAL_INT_GLOBAL) {
183 HALDEBUG(ah, HAL_DEBUG_INTERRUPT, "%s: disable IER\n", __func__);
184 OS_REG_WRITE(ah, AR_IER, AR_IER_DISABLE);
185 (void) OS_REG_READ(ah, AR_IER);
187 OS_REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, 0);
188 (void) OS_REG_READ(ah, AR_INTR_ASYNC_ENABLE);
190 OS_REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
191 (void) OS_REG_READ(ah, AR_INTR_SYNC_ENABLE);
194 mask = ints & HAL_INT_COMMON;
197 if (ints & HAL_INT_TX) {
198 if (ahp->ah_txOkInterruptMask)
200 if (ahp->ah_txErrInterruptMask)
201 mask |= AR_IMR_TXERR;
202 if (ahp->ah_txDescInterruptMask)
203 mask |= AR_IMR_TXDESC;
204 if (ahp->ah_txEolInterruptMask)
205 mask |= AR_IMR_TXEOL;
207 if (ints & HAL_INT_RX)
208 mask |= AR_IMR_RXOK | AR_IMR_RXERR | AR_IMR_RXDESC;
209 #ifdef AR5416_INT_MITIGATION
211 * Overwrite default mask if Interrupt mitigation
212 * is specified for AR5416
214 mask = ints & HAL_INT_COMMON;
215 if (ints & HAL_INT_TX)
216 mask |= AR_IMR_TXMINTR | AR_IMR_TXINTM;
217 if (ints & HAL_INT_RX)
218 mask |= AR_IMR_RXERR | AR_IMR_RXMINTR | AR_IMR_RXINTM;
220 if (ints & (HAL_INT_BMISC)) {
221 mask |= AR_IMR_BCNMISC;
222 if (ints & HAL_INT_TIM)
223 mask2 |= AR_IMR_S2_TIM;
224 if (ints & HAL_INT_DTIM)
225 mask2 |= AR_IMR_S2_DTIM;
226 if (ints & HAL_INT_DTIMSYNC)
227 mask2 |= AR_IMR_S2_DTIMSYNC;
228 if (ints & HAL_INT_CABEND)
229 mask2 |= (AR_IMR_S2_CABEND );
230 if (ints & HAL_INT_GTT)
231 mask2 |= AR_IMR_S2_GTT;
232 if (ints & HAL_INT_CST)
233 mask2 |= AR_IMR_S2_CST;
234 if (ints & HAL_INT_TSFOOR)
235 mask2 |= AR_IMR_S2_TSFOOR;
238 /* Write the new IMR and store off our SW copy. */
239 HALDEBUG(ah, HAL_DEBUG_INTERRUPT, "%s: new IMR 0x%x\n", __func__, mask);
240 OS_REG_WRITE(ah, AR_IMR, mask);
241 mask = OS_REG_READ(ah, AR_IMR_S2) & ~(AR_IMR_S2_TIM |
249 OS_REG_WRITE(ah, AR_IMR_S2, mask | mask2);
251 ahp->ah_maskReg = ints;
253 /* Re-enable interrupts if they were enabled before. */
254 if (ints & HAL_INT_GLOBAL) {
255 HALDEBUG(ah, HAL_DEBUG_INTERRUPT, "%s: enable IER\n", __func__);
256 OS_REG_WRITE(ah, AR_IER, AR_IER_ENABLE);
258 mask = AR_INTR_MAC_IRQ;
259 if (ints & HAL_INT_GPIO)
260 mask |= SM(AH5416(ah)->ah_gpioMask,
261 AR_INTR_ASYNC_MASK_GPIO);
262 OS_REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, mask);
263 OS_REG_WRITE(ah, AR_INTR_ASYNC_MASK, mask);
265 mask = AR_INTR_SYNC_DEFAULT;
266 if (ints & HAL_INT_GPIO)
267 mask |= SM(AH5416(ah)->ah_gpioMask,
268 AR_INTR_SYNC_MASK_GPIO);
269 OS_REG_WRITE(ah, AR_INTR_SYNC_ENABLE, mask);
270 OS_REG_WRITE(ah, AR_INTR_SYNC_MASK, mask);