2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification.
11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
12 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
13 * redistribution must be conditioned upon including a substantially
14 * similar Disclaimer requirement for further binary redistribution.
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
20 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
21 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
22 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
25 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
27 * THE POSSIBILITY OF SUCH DAMAGES.
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD$");
34 * Driver for the Atheros Wireless LAN controller.
36 * This software is derived from work of Atsushi Onoe; his contribution
37 * is greatly appreciated.
44 #include <sys/param.h>
45 #include <sys/systm.h>
46 #include <sys/sysctl.h>
48 #include <sys/malloc.h>
50 #include <sys/mutex.h>
51 #include <sys/kernel.h>
52 #include <sys/socket.h>
53 #include <sys/sockio.h>
54 #include <sys/errno.h>
55 #include <sys/callout.h>
57 #include <sys/endian.h>
58 #include <sys/kthread.h>
59 #include <sys/taskqueue.h>
62 #include <machine/bus.h>
65 #include <net/if_dl.h>
66 #include <net/if_media.h>
67 #include <net/if_types.h>
68 #include <net/if_arp.h>
69 #include <net/ethernet.h>
70 #include <net/if_llc.h>
72 #include <net80211/ieee80211_var.h>
73 #include <net80211/ieee80211_regdomain.h>
74 #ifdef IEEE80211_SUPPORT_SUPERG
75 #include <net80211/ieee80211_superg.h>
77 #ifdef IEEE80211_SUPPORT_TDMA
78 #include <net80211/ieee80211_tdma.h>
84 #include <netinet/in.h>
85 #include <netinet/if_ether.h>
88 #include <dev/ath/if_athvar.h>
89 #include <dev/ath/ath_hal/ah_devid.h> /* XXX for softled */
92 #include <dev/ath/ath_tx99/ath_tx99.h>
96 * ATH_BCBUF determines the number of vap's that can transmit
97 * beacons and also (currently) the number of vap's that can
98 * have unique mac addresses/bssid. When staggering beacons
99 * 4 is probably a good max as otherwise the beacons become
100 * very closely spaced and there is limited time for cab q traffic
101 * to go out. You can burst beacons instead but that is not good
102 * for stations in power save and at some point you really want
103 * another radio (and channel).
105 * The limit on the number of mac addresses is tied to our use of
106 * the U/L bit and tracking addresses in a byte; it would be
107 * worthwhile to allow more for applications like proxy sta.
109 CTASSERT(ATH_BCBUF <= 8);
111 /* unaligned little endian access */
112 #define LE_READ_2(p) \
114 ((((u_int8_t *)(p))[0] ) | (((u_int8_t *)(p))[1] << 8)))
115 #define LE_READ_4(p) \
117 ((((u_int8_t *)(p))[0] ) | (((u_int8_t *)(p))[1] << 8) | \
118 (((u_int8_t *)(p))[2] << 16) | (((u_int8_t *)(p))[3] << 24)))
120 static struct ieee80211vap *ath_vap_create(struct ieee80211com *,
121 const char name[IFNAMSIZ], int unit, int opmode,
122 int flags, const uint8_t bssid[IEEE80211_ADDR_LEN],
123 const uint8_t mac[IEEE80211_ADDR_LEN]);
124 static void ath_vap_delete(struct ieee80211vap *);
125 static void ath_init(void *);
126 static void ath_stop_locked(struct ifnet *);
127 static void ath_stop(struct ifnet *);
128 static void ath_start(struct ifnet *);
129 static int ath_reset(struct ifnet *);
130 static int ath_reset_vap(struct ieee80211vap *, u_long);
131 static int ath_media_change(struct ifnet *);
132 static void ath_watchdog(void *);
133 static int ath_ioctl(struct ifnet *, u_long, caddr_t);
134 static void ath_fatal_proc(void *, int);
135 static void ath_bmiss_vap(struct ieee80211vap *);
136 static void ath_bmiss_proc(void *, int);
137 static int ath_keyset(struct ath_softc *, const struct ieee80211_key *,
138 struct ieee80211_node *);
139 static int ath_key_alloc(struct ieee80211vap *,
140 struct ieee80211_key *,
141 ieee80211_keyix *, ieee80211_keyix *);
142 static int ath_key_delete(struct ieee80211vap *,
143 const struct ieee80211_key *);
144 static int ath_key_set(struct ieee80211vap *, const struct ieee80211_key *,
145 const u_int8_t mac[IEEE80211_ADDR_LEN]);
146 static void ath_key_update_begin(struct ieee80211vap *);
147 static void ath_key_update_end(struct ieee80211vap *);
148 static void ath_update_mcast(struct ifnet *);
149 static void ath_update_promisc(struct ifnet *);
150 static void ath_mode_init(struct ath_softc *);
151 static void ath_setslottime(struct ath_softc *);
152 static void ath_updateslot(struct ifnet *);
153 static int ath_beaconq_setup(struct ath_hal *);
154 static int ath_beacon_alloc(struct ath_softc *, struct ieee80211_node *);
155 static void ath_beacon_update(struct ieee80211vap *, int item);
156 static void ath_beacon_setup(struct ath_softc *, struct ath_buf *);
157 static void ath_beacon_proc(void *, int);
158 static struct ath_buf *ath_beacon_generate(struct ath_softc *,
159 struct ieee80211vap *);
160 static void ath_bstuck_proc(void *, int);
161 static void ath_beacon_return(struct ath_softc *, struct ath_buf *);
162 static void ath_beacon_free(struct ath_softc *);
163 static void ath_beacon_config(struct ath_softc *, struct ieee80211vap *);
164 static void ath_descdma_cleanup(struct ath_softc *sc,
165 struct ath_descdma *, ath_bufhead *);
166 static int ath_desc_alloc(struct ath_softc *);
167 static void ath_desc_free(struct ath_softc *);
168 static struct ieee80211_node *ath_node_alloc(struct ieee80211vap *,
169 const uint8_t [IEEE80211_ADDR_LEN]);
170 static void ath_node_free(struct ieee80211_node *);
171 static void ath_node_getsignal(const struct ieee80211_node *,
173 static int ath_rxbuf_init(struct ath_softc *, struct ath_buf *);
174 static void ath_recv_mgmt(struct ieee80211_node *ni, struct mbuf *m,
175 int subtype, int rssi, int nf);
176 static void ath_setdefantenna(struct ath_softc *, u_int);
177 static void ath_rx_proc(void *, int);
178 static void ath_txq_init(struct ath_softc *sc, struct ath_txq *, int);
179 static struct ath_txq *ath_txq_setup(struct ath_softc*, int qtype, int subtype);
180 static int ath_tx_setup(struct ath_softc *, int, int);
181 static int ath_wme_update(struct ieee80211com *);
182 static void ath_tx_cleanupq(struct ath_softc *, struct ath_txq *);
183 static void ath_tx_cleanup(struct ath_softc *);
184 static void ath_freetx(struct mbuf *);
185 static int ath_tx_start(struct ath_softc *, struct ieee80211_node *,
186 struct ath_buf *, struct mbuf *);
187 static void ath_tx_proc_q0(void *, int);
188 static void ath_tx_proc_q0123(void *, int);
189 static void ath_tx_proc(void *, int);
190 static void ath_tx_draintxq(struct ath_softc *, struct ath_txq *);
191 static int ath_chan_set(struct ath_softc *, struct ieee80211_channel *);
192 static void ath_draintxq(struct ath_softc *);
193 static void ath_stoprecv(struct ath_softc *);
194 static int ath_startrecv(struct ath_softc *);
195 static void ath_chan_change(struct ath_softc *, struct ieee80211_channel *);
196 static void ath_scan_start(struct ieee80211com *);
197 static void ath_scan_end(struct ieee80211com *);
198 static void ath_set_channel(struct ieee80211com *);
199 static void ath_calibrate(void *);
200 static int ath_newstate(struct ieee80211vap *, enum ieee80211_state, int);
201 static void ath_setup_stationkey(struct ieee80211_node *);
202 static void ath_newassoc(struct ieee80211_node *, int);
203 static int ath_setregdomain(struct ieee80211com *,
204 struct ieee80211_regdomain *, int,
205 struct ieee80211_channel []);
206 static void ath_getradiocaps(struct ieee80211com *, int, int *,
207 struct ieee80211_channel []);
208 static int ath_getchannels(struct ath_softc *);
209 static void ath_led_event(struct ath_softc *, int);
211 static int ath_rate_setup(struct ath_softc *, u_int mode);
212 static void ath_setcurmode(struct ath_softc *, enum ieee80211_phymode);
214 static void ath_sysctlattach(struct ath_softc *);
215 static int ath_raw_xmit(struct ieee80211_node *,
216 struct mbuf *, const struct ieee80211_bpf_params *);
217 static void ath_announce(struct ath_softc *);
219 #ifdef IEEE80211_SUPPORT_TDMA
220 static void ath_tdma_settimers(struct ath_softc *sc, u_int32_t nexttbtt,
222 static void ath_tdma_bintvalsetup(struct ath_softc *sc,
223 const struct ieee80211_tdma_state *tdma);
224 static void ath_tdma_config(struct ath_softc *sc, struct ieee80211vap *vap);
225 static void ath_tdma_update(struct ieee80211_node *ni,
226 const struct ieee80211_tdma_param *tdma, int);
227 static void ath_tdma_beacon_send(struct ath_softc *sc,
228 struct ieee80211vap *vap);
231 ath_hal_setcca(struct ath_hal *ah, int ena)
234 * NB: fill me in; this is not provided by default because disabling
235 * CCA in most locales violates regulatory.
240 ath_hal_getcca(struct ath_hal *ah)
243 if (ath_hal_getcapability(ah, HAL_CAP_DIAG, 0, &diag) != HAL_OK)
245 return ((diag & 0x500000) == 0);
248 #define TDMA_EP_MULTIPLIER (1<<10) /* pow2 to optimize out * and / */
249 #define TDMA_LPF_LEN 6
250 #define TDMA_DUMMY_MARKER 0x127
251 #define TDMA_EP_MUL(x, mul) ((x) * (mul))
252 #define TDMA_IN(x) (TDMA_EP_MUL((x), TDMA_EP_MULTIPLIER))
253 #define TDMA_LPF(x, y, len) \
254 ((x != TDMA_DUMMY_MARKER) ? (((x) * ((len)-1) + (y)) / (len)) : (y))
255 #define TDMA_SAMPLE(x, y) do { \
256 x = TDMA_LPF((x), TDMA_IN(y), TDMA_LPF_LEN); \
258 #define TDMA_EP_RND(x,mul) \
259 ((((x)%(mul)) >= ((mul)/2)) ? ((x) + ((mul) - 1)) / (mul) : (x)/(mul))
260 #define TDMA_AVG(x) TDMA_EP_RND(x, TDMA_EP_MULTIPLIER)
261 #endif /* IEEE80211_SUPPORT_TDMA */
263 SYSCTL_DECL(_hw_ath);
265 /* XXX validate sysctl values */
266 static int ath_longcalinterval = 30; /* long cals every 30 secs */
267 SYSCTL_INT(_hw_ath, OID_AUTO, longcal, CTLFLAG_RW, &ath_longcalinterval,
268 0, "long chip calibration interval (secs)");
269 static int ath_shortcalinterval = 100; /* short cals every 100 ms */
270 SYSCTL_INT(_hw_ath, OID_AUTO, shortcal, CTLFLAG_RW, &ath_shortcalinterval,
271 0, "short chip calibration interval (msecs)");
272 static int ath_resetcalinterval = 20*60; /* reset cal state 20 mins */
273 SYSCTL_INT(_hw_ath, OID_AUTO, resetcal, CTLFLAG_RW, &ath_resetcalinterval,
274 0, "reset chip calibration results (secs)");
276 static int ath_rxbuf = ATH_RXBUF; /* # rx buffers to allocate */
277 SYSCTL_INT(_hw_ath, OID_AUTO, rxbuf, CTLFLAG_RW, &ath_rxbuf,
278 0, "rx buffers allocated");
279 TUNABLE_INT("hw.ath.rxbuf", &ath_rxbuf);
280 static int ath_txbuf = ATH_TXBUF; /* # tx buffers to allocate */
281 SYSCTL_INT(_hw_ath, OID_AUTO, txbuf, CTLFLAG_RW, &ath_txbuf,
282 0, "tx buffers allocated");
283 TUNABLE_INT("hw.ath.txbuf", &ath_txbuf);
285 static int ath_bstuck_threshold = 4; /* max missed beacons */
286 SYSCTL_INT(_hw_ath, OID_AUTO, bstuck, CTLFLAG_RW, &ath_bstuck_threshold,
287 0, "max missed beacon xmits before chip reset");
291 ATH_DEBUG_XMIT = 0x00000001, /* basic xmit operation */
292 ATH_DEBUG_XMIT_DESC = 0x00000002, /* xmit descriptors */
293 ATH_DEBUG_RECV = 0x00000004, /* basic recv operation */
294 ATH_DEBUG_RECV_DESC = 0x00000008, /* recv descriptors */
295 ATH_DEBUG_RATE = 0x00000010, /* rate control */
296 ATH_DEBUG_RESET = 0x00000020, /* reset processing */
297 ATH_DEBUG_MODE = 0x00000040, /* mode init/setup */
298 ATH_DEBUG_BEACON = 0x00000080, /* beacon handling */
299 ATH_DEBUG_WATCHDOG = 0x00000100, /* watchdog timeout */
300 ATH_DEBUG_INTR = 0x00001000, /* ISR */
301 ATH_DEBUG_TX_PROC = 0x00002000, /* tx ISR proc */
302 ATH_DEBUG_RX_PROC = 0x00004000, /* rx ISR proc */
303 ATH_DEBUG_BEACON_PROC = 0x00008000, /* beacon ISR proc */
304 ATH_DEBUG_CALIBRATE = 0x00010000, /* periodic calibration */
305 ATH_DEBUG_KEYCACHE = 0x00020000, /* key cache management */
306 ATH_DEBUG_STATE = 0x00040000, /* 802.11 state transitions */
307 ATH_DEBUG_NODE = 0x00080000, /* node management */
308 ATH_DEBUG_LED = 0x00100000, /* led management */
309 ATH_DEBUG_FF = 0x00200000, /* fast frames */
310 ATH_DEBUG_DFS = 0x00400000, /* DFS processing */
311 ATH_DEBUG_TDMA = 0x00800000, /* TDMA processing */
312 ATH_DEBUG_TDMA_TIMER = 0x01000000, /* TDMA timer processing */
313 ATH_DEBUG_REGDOMAIN = 0x02000000, /* regulatory processing */
314 ATH_DEBUG_FATAL = 0x80000000, /* fatal errors */
315 ATH_DEBUG_ANY = 0xffffffff
317 static int ath_debug = 0;
318 SYSCTL_INT(_hw_ath, OID_AUTO, debug, CTLFLAG_RW, &ath_debug,
319 0, "control debugging printfs");
320 TUNABLE_INT("hw.ath.debug", &ath_debug);
322 #define IFF_DUMPPKTS(sc, m) \
323 ((sc->sc_debug & (m)) || \
324 (sc->sc_ifp->if_flags & (IFF_DEBUG|IFF_LINK2)) == (IFF_DEBUG|IFF_LINK2))
325 #define DPRINTF(sc, m, fmt, ...) do { \
326 if (sc->sc_debug & (m)) \
327 printf(fmt, __VA_ARGS__); \
329 #define KEYPRINTF(sc, ix, hk, mac) do { \
330 if (sc->sc_debug & ATH_DEBUG_KEYCACHE) \
331 ath_keyprint(sc, __func__, ix, hk, mac); \
333 static void ath_printrxbuf(struct ath_softc *, const struct ath_buf *bf,
335 static void ath_printtxbuf(struct ath_softc *, const struct ath_buf *bf,
336 u_int qnum, u_int ix, int done);
338 #define IFF_DUMPPKTS(sc, m) \
339 ((sc->sc_ifp->if_flags & (IFF_DEBUG|IFF_LINK2)) == (IFF_DEBUG|IFF_LINK2))
340 #define DPRINTF(sc, m, fmt, ...) do { \
343 #define KEYPRINTF(sc, k, ix, mac) do { \
348 MALLOC_DEFINE(M_ATHDEV, "athdev", "ath driver dma buffers");
351 ath_attach(u_int16_t devid, struct ath_softc *sc)
354 struct ieee80211com *ic;
355 struct ath_hal *ah = NULL;
359 uint8_t macaddr[IEEE80211_ADDR_LEN];
361 DPRINTF(sc, ATH_DEBUG_ANY, "%s: devid 0x%x\n", __func__, devid);
363 ifp = sc->sc_ifp = if_alloc(IFT_IEEE80211);
365 device_printf(sc->sc_dev, "can not if_alloc()\n");
371 /* set these up early for if_printf use */
372 if_initname(ifp, device_get_name(sc->sc_dev),
373 device_get_unit(sc->sc_dev));
375 ah = ath_hal_attach(devid, sc, sc->sc_st, sc->sc_sh, &status);
377 if_printf(ifp, "unable to attach hardware; HAL status %u\n",
383 sc->sc_invalid = 0; /* ready to go, enable interrupt handling */
385 sc->sc_debug = ath_debug;
389 * Check if the MAC has multi-rate retry support.
390 * We do this by trying to setup a fake extended
391 * descriptor. MAC's that don't have support will
392 * return false w/o doing anything. MAC's that do
393 * support it will return true w/o doing anything.
395 sc->sc_mrretry = ath_hal_setupxtxdesc(ah, NULL, 0,0, 0,0, 0,0);
398 * Check if the device has hardware counters for PHY
399 * errors. If so we need to enable the MIB interrupt
400 * so we can act on stat triggers.
402 if (ath_hal_hwphycounters(ah))
406 * Get the hardware key cache size.
408 sc->sc_keymax = ath_hal_keycachesize(ah);
409 if (sc->sc_keymax > ATH_KEYMAX) {
410 if_printf(ifp, "Warning, using only %u of %u key cache slots\n",
411 ATH_KEYMAX, sc->sc_keymax);
412 sc->sc_keymax = ATH_KEYMAX;
415 * Reset the key cache since some parts do not
416 * reset the contents on initial power up.
418 for (i = 0; i < sc->sc_keymax; i++)
419 ath_hal_keyreset(ah, i);
422 * Collect the default channel list.
424 error = ath_getchannels(sc);
429 * Setup rate tables for all potential media types.
431 ath_rate_setup(sc, IEEE80211_MODE_11A);
432 ath_rate_setup(sc, IEEE80211_MODE_11B);
433 ath_rate_setup(sc, IEEE80211_MODE_11G);
434 ath_rate_setup(sc, IEEE80211_MODE_TURBO_A);
435 ath_rate_setup(sc, IEEE80211_MODE_TURBO_G);
436 ath_rate_setup(sc, IEEE80211_MODE_STURBO_A);
437 ath_rate_setup(sc, IEEE80211_MODE_11NA);
438 ath_rate_setup(sc, IEEE80211_MODE_11NG);
439 ath_rate_setup(sc, IEEE80211_MODE_HALF);
440 ath_rate_setup(sc, IEEE80211_MODE_QUARTER);
442 /* NB: setup here so ath_rate_update is happy */
443 ath_setcurmode(sc, IEEE80211_MODE_11A);
446 * Allocate tx+rx descriptors and populate the lists.
448 error = ath_desc_alloc(sc);
450 if_printf(ifp, "failed to allocate descriptors: %d\n", error);
453 callout_init_mtx(&sc->sc_cal_ch, &sc->sc_mtx, 0);
454 callout_init_mtx(&sc->sc_wd_ch, &sc->sc_mtx, 0);
456 ATH_TXBUF_LOCK_INIT(sc);
458 sc->sc_tq = taskqueue_create("ath_taskq", M_NOWAIT,
459 taskqueue_thread_enqueue, &sc->sc_tq);
460 taskqueue_start_threads(&sc->sc_tq, 1, PI_NET,
461 "%s taskq", ifp->if_xname);
463 TASK_INIT(&sc->sc_rxtask, 0, ath_rx_proc, sc);
464 TASK_INIT(&sc->sc_bmisstask, 0, ath_bmiss_proc, sc);
465 TASK_INIT(&sc->sc_bstucktask,0, ath_bstuck_proc, sc);
468 * Allocate hardware transmit queues: one queue for
469 * beacon frames and one data queue for each QoS
470 * priority. Note that the hal handles reseting
471 * these queues at the needed time.
475 sc->sc_bhalq = ath_beaconq_setup(ah);
476 if (sc->sc_bhalq == (u_int) -1) {
477 if_printf(ifp, "unable to setup a beacon xmit queue!\n");
481 sc->sc_cabq = ath_txq_setup(sc, HAL_TX_QUEUE_CAB, 0);
482 if (sc->sc_cabq == NULL) {
483 if_printf(ifp, "unable to setup CAB xmit queue!\n");
487 /* NB: insure BK queue is the lowest priority h/w queue */
488 if (!ath_tx_setup(sc, WME_AC_BK, HAL_WME_AC_BK)) {
489 if_printf(ifp, "unable to setup xmit queue for %s traffic!\n",
490 ieee80211_wme_acnames[WME_AC_BK]);
494 if (!ath_tx_setup(sc, WME_AC_BE, HAL_WME_AC_BE) ||
495 !ath_tx_setup(sc, WME_AC_VI, HAL_WME_AC_VI) ||
496 !ath_tx_setup(sc, WME_AC_VO, HAL_WME_AC_VO)) {
498 * Not enough hardware tx queues to properly do WME;
499 * just punt and assign them all to the same h/w queue.
500 * We could do a better job of this if, for example,
501 * we allocate queues when we switch from station to
504 if (sc->sc_ac2q[WME_AC_VI] != NULL)
505 ath_tx_cleanupq(sc, sc->sc_ac2q[WME_AC_VI]);
506 if (sc->sc_ac2q[WME_AC_BE] != NULL)
507 ath_tx_cleanupq(sc, sc->sc_ac2q[WME_AC_BE]);
508 sc->sc_ac2q[WME_AC_BE] = sc->sc_ac2q[WME_AC_BK];
509 sc->sc_ac2q[WME_AC_VI] = sc->sc_ac2q[WME_AC_BK];
510 sc->sc_ac2q[WME_AC_VO] = sc->sc_ac2q[WME_AC_BK];
514 * Special case certain configurations. Note the
515 * CAB queue is handled by these specially so don't
516 * include them when checking the txq setup mask.
518 switch (sc->sc_txqsetup &~ (1<<sc->sc_cabq->axq_qnum)) {
520 TASK_INIT(&sc->sc_txtask, 0, ath_tx_proc_q0, sc);
523 TASK_INIT(&sc->sc_txtask, 0, ath_tx_proc_q0123, sc);
526 TASK_INIT(&sc->sc_txtask, 0, ath_tx_proc, sc);
531 * Setup rate control. Some rate control modules
532 * call back to change the anntena state so expose
533 * the necessary entry points.
534 * XXX maybe belongs in struct ath_ratectrl?
536 sc->sc_setdefantenna = ath_setdefantenna;
537 sc->sc_rc = ath_rate_attach(sc);
538 if (sc->sc_rc == NULL) {
545 sc->sc_ledon = 0; /* low true */
546 sc->sc_ledidle = (2700*hz)/1000; /* 2.7sec */
547 callout_init(&sc->sc_ledtimer, CALLOUT_MPSAFE);
549 * Auto-enable soft led processing for IBM cards and for
550 * 5211 minipci cards. Users can also manually enable/disable
551 * support with a sysctl.
553 sc->sc_softled = (devid == AR5212_DEVID_IBM || devid == AR5211_DEVID);
554 if (sc->sc_softled) {
555 ath_hal_gpioCfgOutput(ah, sc->sc_ledpin,
556 HAL_GPIO_MUX_MAC_NETWORK_LED);
557 ath_hal_gpioset(ah, sc->sc_ledpin, !sc->sc_ledon);
561 ifp->if_flags = IFF_SIMPLEX | IFF_BROADCAST | IFF_MULTICAST;
562 ifp->if_start = ath_start;
563 ifp->if_watchdog = NULL;
564 ifp->if_ioctl = ath_ioctl;
565 ifp->if_init = ath_init;
566 IFQ_SET_MAXLEN(&ifp->if_snd, IFQ_MAXLEN);
567 ifp->if_snd.ifq_drv_maxlen = IFQ_MAXLEN;
568 IFQ_SET_READY(&ifp->if_snd);
571 /* XXX not right but it's not used anywhere important */
572 ic->ic_phytype = IEEE80211_T_OFDM;
573 ic->ic_opmode = IEEE80211_M_STA;
575 IEEE80211_C_STA /* station mode */
576 | IEEE80211_C_IBSS /* ibss, nee adhoc, mode */
577 | IEEE80211_C_HOSTAP /* hostap mode */
578 | IEEE80211_C_MONITOR /* monitor mode */
579 | IEEE80211_C_AHDEMO /* adhoc demo mode */
580 | IEEE80211_C_WDS /* 4-address traffic works */
581 | IEEE80211_C_MBSS /* mesh point link mode */
582 | IEEE80211_C_SHPREAMBLE /* short preamble supported */
583 | IEEE80211_C_SHSLOT /* short slot time supported */
584 | IEEE80211_C_WPA /* capable of WPA1+WPA2 */
585 | IEEE80211_C_BGSCAN /* capable of bg scanning */
586 | IEEE80211_C_TXFRAG /* handle tx frags */
589 * Query the hal to figure out h/w crypto support.
591 if (ath_hal_ciphersupported(ah, HAL_CIPHER_WEP))
592 ic->ic_cryptocaps |= IEEE80211_CRYPTO_WEP;
593 if (ath_hal_ciphersupported(ah, HAL_CIPHER_AES_OCB))
594 ic->ic_cryptocaps |= IEEE80211_CRYPTO_AES_OCB;
595 if (ath_hal_ciphersupported(ah, HAL_CIPHER_AES_CCM))
596 ic->ic_cryptocaps |= IEEE80211_CRYPTO_AES_CCM;
597 if (ath_hal_ciphersupported(ah, HAL_CIPHER_CKIP))
598 ic->ic_cryptocaps |= IEEE80211_CRYPTO_CKIP;
599 if (ath_hal_ciphersupported(ah, HAL_CIPHER_TKIP)) {
600 ic->ic_cryptocaps |= IEEE80211_CRYPTO_TKIP;
602 * Check if h/w does the MIC and/or whether the
603 * separate key cache entries are required to
604 * handle both tx+rx MIC keys.
606 if (ath_hal_ciphersupported(ah, HAL_CIPHER_MIC))
607 ic->ic_cryptocaps |= IEEE80211_CRYPTO_TKIPMIC;
609 * If the h/w supports storing tx+rx MIC keys
610 * in one cache slot automatically enable use.
612 if (ath_hal_hastkipsplit(ah) ||
613 !ath_hal_settkipsplit(ah, AH_FALSE))
616 * If the h/w can do TKIP MIC together with WME then
617 * we use it; otherwise we force the MIC to be done
618 * in software by the net80211 layer.
620 if (ath_hal_haswmetkipmic(ah))
621 sc->sc_wmetkipmic = 1;
623 sc->sc_hasclrkey = ath_hal_ciphersupported(ah, HAL_CIPHER_CLR);
625 * Check for multicast key search support.
627 if (ath_hal_hasmcastkeysearch(sc->sc_ah) &&
628 !ath_hal_getmcastkeysearch(sc->sc_ah)) {
629 ath_hal_setmcastkeysearch(sc->sc_ah, 1);
631 sc->sc_mcastkey = ath_hal_getmcastkeysearch(ah);
633 * Mark key cache slots associated with global keys
634 * as in use. If we knew TKIP was not to be used we
635 * could leave the +32, +64, and +32+64 slots free.
637 for (i = 0; i < IEEE80211_WEP_NKID; i++) {
638 setbit(sc->sc_keymap, i);
639 setbit(sc->sc_keymap, i+64);
640 if (sc->sc_splitmic) {
641 setbit(sc->sc_keymap, i+32);
642 setbit(sc->sc_keymap, i+32+64);
646 * TPC support can be done either with a global cap or
647 * per-packet support. The latter is not available on
648 * all parts. We're a bit pedantic here as all parts
649 * support a global cap.
651 if (ath_hal_hastpc(ah) || ath_hal_hastxpowlimit(ah))
652 ic->ic_caps |= IEEE80211_C_TXPMGT;
655 * Mark WME capability only if we have sufficient
656 * hardware queues to do proper priority scheduling.
658 if (sc->sc_ac2q[WME_AC_BE] != sc->sc_ac2q[WME_AC_BK])
659 ic->ic_caps |= IEEE80211_C_WME;
661 * Check for misc other capabilities.
663 if (ath_hal_hasbursting(ah))
664 ic->ic_caps |= IEEE80211_C_BURST;
665 sc->sc_hasbmask = ath_hal_hasbssidmask(ah);
666 sc->sc_hasbmatch = ath_hal_hasbssidmatch(ah);
667 sc->sc_hastsfadd = ath_hal_hastsfadjust(ah);
668 if (ath_hal_hasfastframes(ah))
669 ic->ic_caps |= IEEE80211_C_FF;
670 wmodes = ath_hal_getwirelessmodes(ah);
671 if (wmodes & (HAL_MODE_108G|HAL_MODE_TURBO))
672 ic->ic_caps |= IEEE80211_C_TURBOP;
673 #ifdef IEEE80211_SUPPORT_TDMA
674 if (ath_hal_macversion(ah) > 0x78) {
675 ic->ic_caps |= IEEE80211_C_TDMA; /* capable of TDMA */
676 ic->ic_tdma_update = ath_tdma_update;
680 * Indicate we need the 802.11 header padded to a
681 * 32-bit boundary for 4-address and QoS frames.
683 ic->ic_flags |= IEEE80211_F_DATAPAD;
686 * Query the hal about antenna support.
688 sc->sc_defant = ath_hal_getdefantenna(ah);
691 * Not all chips have the VEOL support we want to
692 * use with IBSS beacons; check here for it.
694 sc->sc_hasveol = ath_hal_hasveol(ah);
696 /* get mac address from hardware */
697 ath_hal_getmac(ah, macaddr);
699 ath_hal_getbssidmask(ah, sc->sc_hwbssidmask);
701 /* NB: used to size node table key mapping array */
702 ic->ic_max_keyix = sc->sc_keymax;
703 /* call MI attach routine. */
704 ieee80211_ifattach(ic, macaddr);
705 ic->ic_setregdomain = ath_setregdomain;
706 ic->ic_getradiocaps = ath_getradiocaps;
707 sc->sc_opmode = HAL_M_STA;
709 /* override default methods */
710 ic->ic_newassoc = ath_newassoc;
711 ic->ic_updateslot = ath_updateslot;
712 ic->ic_wme.wme_update = ath_wme_update;
713 ic->ic_vap_create = ath_vap_create;
714 ic->ic_vap_delete = ath_vap_delete;
715 ic->ic_raw_xmit = ath_raw_xmit;
716 ic->ic_update_mcast = ath_update_mcast;
717 ic->ic_update_promisc = ath_update_promisc;
718 ic->ic_node_alloc = ath_node_alloc;
719 sc->sc_node_free = ic->ic_node_free;
720 ic->ic_node_free = ath_node_free;
721 ic->ic_node_getsignal = ath_node_getsignal;
722 ic->ic_scan_start = ath_scan_start;
723 ic->ic_scan_end = ath_scan_end;
724 ic->ic_set_channel = ath_set_channel;
726 ieee80211_radiotap_attach(ic,
727 &sc->sc_tx_th.wt_ihdr, sizeof(sc->sc_tx_th),
728 ATH_TX_RADIOTAP_PRESENT,
729 &sc->sc_rx_th.wr_ihdr, sizeof(sc->sc_rx_th),
730 ATH_RX_RADIOTAP_PRESENT);
733 * Setup dynamic sysctl's now that country code and
734 * regdomain are available from the hal.
736 ath_sysctlattach(sc);
739 ieee80211_announce(ic);
755 ath_detach(struct ath_softc *sc)
757 struct ifnet *ifp = sc->sc_ifp;
759 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags %x\n",
760 __func__, ifp->if_flags);
763 * NB: the order of these is important:
764 * o stop the chip so no more interrupts will fire
765 * o call the 802.11 layer before detaching the hal to
766 * insure callbacks into the driver to delete global
767 * key cache entries can be handled
768 * o free the taskqueue which drains any pending tasks
769 * o reclaim the tx queue data structures after calling
770 * the 802.11 layer as we'll get called back to reclaim
771 * node state and potentially want to use them
772 * o to cleanup the tx queues the hal is called, so detach
774 * Other than that, it's straightforward...
777 ieee80211_ifdetach(ifp->if_l2com);
778 taskqueue_free(sc->sc_tq);
780 if (sc->sc_tx99 != NULL)
781 sc->sc_tx99->detach(sc->sc_tx99);
783 ath_rate_detach(sc->sc_rc);
786 ath_hal_detach(sc->sc_ah); /* NB: sets chip in full sleep */
793 * MAC address handling for multiple BSS on the same radio.
794 * The first vap uses the MAC address from the EEPROM. For
795 * subsequent vap's we set the U/L bit (bit 1) in the MAC
796 * address and use the next six bits as an index.
799 assign_address(struct ath_softc *sc, uint8_t mac[IEEE80211_ADDR_LEN], int clone)
803 if (clone && sc->sc_hasbmask) {
804 /* NB: we only do this if h/w supports multiple bssid */
805 for (i = 0; i < 8; i++)
806 if ((sc->sc_bssidmask & (1<<i)) == 0)
809 mac[0] |= (i << 2)|0x2;
812 sc->sc_bssidmask |= 1<<i;
813 sc->sc_hwbssidmask[0] &= ~mac[0];
819 reclaim_address(struct ath_softc *sc, const uint8_t mac[IEEE80211_ADDR_LEN])
824 if (i != 0 || --sc->sc_nbssid0 == 0) {
825 sc->sc_bssidmask &= ~(1<<i);
826 /* recalculate bssid mask from remaining addresses */
828 for (i = 1; i < 8; i++)
829 if (sc->sc_bssidmask & (1<<i))
830 mask &= ~((i<<2)|0x2);
831 sc->sc_hwbssidmask[0] |= mask;
836 * Assign a beacon xmit slot. We try to space out
837 * assignments so when beacons are staggered the
838 * traffic coming out of the cab q has maximal time
839 * to go out before the next beacon is scheduled.
842 assign_bslot(struct ath_softc *sc)
847 for (slot = 0; slot < ATH_BCBUF; slot++)
848 if (sc->sc_bslot[slot] == NULL) {
849 if (sc->sc_bslot[(slot+1)%ATH_BCBUF] == NULL &&
850 sc->sc_bslot[(slot-1)%ATH_BCBUF] == NULL)
853 /* NB: keep looking for a double slot */
858 static struct ieee80211vap *
859 ath_vap_create(struct ieee80211com *ic,
860 const char name[IFNAMSIZ], int unit, int opmode, int flags,
861 const uint8_t bssid[IEEE80211_ADDR_LEN],
862 const uint8_t mac0[IEEE80211_ADDR_LEN])
864 struct ath_softc *sc = ic->ic_ifp->if_softc;
866 struct ieee80211vap *vap;
867 uint8_t mac[IEEE80211_ADDR_LEN];
868 int ic_opmode, needbeacon, error;
870 avp = (struct ath_vap *) malloc(sizeof(struct ath_vap),
871 M_80211_VAP, M_WAITOK | M_ZERO);
873 IEEE80211_ADDR_COPY(mac, mac0);
876 ic_opmode = opmode; /* default to opmode of new vap */
878 case IEEE80211_M_STA:
879 if (sc->sc_nstavaps != 0) { /* XXX only 1 for now */
880 device_printf(sc->sc_dev, "only 1 sta vap supported\n");
885 * With multiple vaps we must fall back
886 * to s/w beacon miss handling.
888 flags |= IEEE80211_CLONE_NOBEACONS;
890 if (flags & IEEE80211_CLONE_NOBEACONS) {
892 * Station mode w/o beacons are implemented w/ AP mode.
894 ic_opmode = IEEE80211_M_HOSTAP;
897 case IEEE80211_M_IBSS:
898 if (sc->sc_nvaps != 0) { /* XXX only 1 for now */
899 device_printf(sc->sc_dev,
900 "only 1 ibss vap supported\n");
905 case IEEE80211_M_AHDEMO:
906 #ifdef IEEE80211_SUPPORT_TDMA
907 if (flags & IEEE80211_CLONE_TDMA) {
908 if (sc->sc_nvaps != 0) {
909 device_printf(sc->sc_dev,
910 "only 1 tdma vap supported\n");
914 flags |= IEEE80211_CLONE_NOBEACONS;
918 case IEEE80211_M_MONITOR:
919 if (sc->sc_nvaps != 0 && ic->ic_opmode != opmode) {
921 * Adopt existing mode. Adding a monitor or ahdemo
922 * vap to an existing configuration is of dubious
923 * value but should be ok.
925 /* XXX not right for monitor mode */
926 ic_opmode = ic->ic_opmode;
929 case IEEE80211_M_HOSTAP:
930 case IEEE80211_M_MBSS:
933 case IEEE80211_M_WDS:
934 if (sc->sc_nvaps != 0 && ic->ic_opmode == IEEE80211_M_STA) {
935 device_printf(sc->sc_dev,
936 "wds not supported in sta mode\n");
940 * Silently remove any request for a unique
941 * bssid; WDS vap's always share the local
944 flags &= ~IEEE80211_CLONE_BSSID;
945 if (sc->sc_nvaps == 0)
946 ic_opmode = IEEE80211_M_HOSTAP;
948 ic_opmode = ic->ic_opmode;
951 device_printf(sc->sc_dev, "unknown opmode %d\n", opmode);
955 * Check that a beacon buffer is available; the code below assumes it.
957 if (needbeacon & STAILQ_EMPTY(&sc->sc_bbuf)) {
958 device_printf(sc->sc_dev, "no beacon buffer available\n");
963 if (opmode == IEEE80211_M_HOSTAP || opmode == IEEE80211_M_MBSS) {
964 assign_address(sc, mac, flags & IEEE80211_CLONE_BSSID);
965 ath_hal_setbssidmask(sc->sc_ah, sc->sc_hwbssidmask);
969 /* XXX can't hold mutex across if_alloc */
971 error = ieee80211_vap_setup(ic, vap, name, unit, opmode, flags,
975 device_printf(sc->sc_dev, "%s: error %d creating vap\n",
980 /* h/w crypto support */
981 vap->iv_key_alloc = ath_key_alloc;
982 vap->iv_key_delete = ath_key_delete;
983 vap->iv_key_set = ath_key_set;
984 vap->iv_key_update_begin = ath_key_update_begin;
985 vap->iv_key_update_end = ath_key_update_end;
987 /* override various methods */
988 avp->av_recv_mgmt = vap->iv_recv_mgmt;
989 vap->iv_recv_mgmt = ath_recv_mgmt;
990 vap->iv_reset = ath_reset_vap;
991 vap->iv_update_beacon = ath_beacon_update;
992 avp->av_newstate = vap->iv_newstate;
993 vap->iv_newstate = ath_newstate;
994 avp->av_bmiss = vap->iv_bmiss;
995 vap->iv_bmiss = ath_bmiss_vap;
1000 * Allocate beacon state and setup the q for buffered
1001 * multicast frames. We know a beacon buffer is
1002 * available because we checked above.
1004 avp->av_bcbuf = STAILQ_FIRST(&sc->sc_bbuf);
1005 STAILQ_REMOVE_HEAD(&sc->sc_bbuf, bf_list);
1006 if (opmode != IEEE80211_M_IBSS || !sc->sc_hasveol) {
1008 * Assign the vap to a beacon xmit slot. As above
1009 * this cannot fail to find a free one.
1011 avp->av_bslot = assign_bslot(sc);
1012 KASSERT(sc->sc_bslot[avp->av_bslot] == NULL,
1013 ("beacon slot %u not empty", avp->av_bslot));
1014 sc->sc_bslot[avp->av_bslot] = vap;
1017 if (sc->sc_hastsfadd && sc->sc_nbcnvaps > 0) {
1019 * Multple vaps are to transmit beacons and we
1020 * have h/w support for TSF adjusting; enable
1021 * use of staggered beacons.
1023 sc->sc_stagbeacons = 1;
1025 ath_txq_init(sc, &avp->av_mcastq, ATH_TXQ_SWQ);
1028 ic->ic_opmode = ic_opmode;
1029 if (opmode != IEEE80211_M_WDS) {
1031 if (opmode == IEEE80211_M_STA)
1033 if (opmode == IEEE80211_M_MBSS)
1036 switch (ic_opmode) {
1037 case IEEE80211_M_IBSS:
1038 sc->sc_opmode = HAL_M_IBSS;
1040 case IEEE80211_M_STA:
1041 sc->sc_opmode = HAL_M_STA;
1043 case IEEE80211_M_AHDEMO:
1044 #ifdef IEEE80211_SUPPORT_TDMA
1045 if (vap->iv_caps & IEEE80211_C_TDMA) {
1047 /* NB: disable tsf adjust */
1048 sc->sc_stagbeacons = 0;
1051 * NB: adhoc demo mode is a pseudo mode; to the hal it's
1056 case IEEE80211_M_HOSTAP:
1057 case IEEE80211_M_MBSS:
1058 sc->sc_opmode = HAL_M_HOSTAP;
1060 case IEEE80211_M_MONITOR:
1061 sc->sc_opmode = HAL_M_MONITOR;
1064 /* XXX should not happen */
1067 if (sc->sc_hastsfadd) {
1069 * Configure whether or not TSF adjust should be done.
1071 ath_hal_settsfadjust(sc->sc_ah, sc->sc_stagbeacons);
1073 if (flags & IEEE80211_CLONE_NOBEACONS) {
1075 * Enable s/w beacon miss handling.
1081 /* complete setup */
1082 ieee80211_vap_attach(vap, ath_media_change, ieee80211_media_status);
1085 reclaim_address(sc, mac);
1086 ath_hal_setbssidmask(sc->sc_ah, sc->sc_hwbssidmask);
1088 free(avp, M_80211_VAP);
1094 ath_vap_delete(struct ieee80211vap *vap)
1096 struct ieee80211com *ic = vap->iv_ic;
1097 struct ifnet *ifp = ic->ic_ifp;
1098 struct ath_softc *sc = ifp->if_softc;
1099 struct ath_hal *ah = sc->sc_ah;
1100 struct ath_vap *avp = ATH_VAP(vap);
1102 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
1104 * Quiesce the hardware while we remove the vap. In
1105 * particular we need to reclaim all references to
1106 * the vap state by any frames pending on the tx queues.
1108 ath_hal_intrset(ah, 0); /* disable interrupts */
1109 ath_draintxq(sc); /* stop xmit side */
1110 ath_stoprecv(sc); /* stop recv side */
1113 ieee80211_vap_detach(vap);
1116 * Reclaim beacon state. Note this must be done before
1117 * the vap instance is reclaimed as we may have a reference
1118 * to it in the buffer for the beacon frame.
1120 if (avp->av_bcbuf != NULL) {
1121 if (avp->av_bslot != -1) {
1122 sc->sc_bslot[avp->av_bslot] = NULL;
1125 ath_beacon_return(sc, avp->av_bcbuf);
1126 avp->av_bcbuf = NULL;
1127 if (sc->sc_nbcnvaps == 0) {
1128 sc->sc_stagbeacons = 0;
1129 if (sc->sc_hastsfadd)
1130 ath_hal_settsfadjust(sc->sc_ah, 0);
1133 * Reclaim any pending mcast frames for the vap.
1135 ath_tx_draintxq(sc, &avp->av_mcastq);
1136 ATH_TXQ_LOCK_DESTROY(&avp->av_mcastq);
1139 * Update bookkeeping.
1141 if (vap->iv_opmode == IEEE80211_M_STA) {
1143 if (sc->sc_nstavaps == 0 && sc->sc_swbmiss)
1145 } else if (vap->iv_opmode == IEEE80211_M_HOSTAP ||
1146 vap->iv_opmode == IEEE80211_M_MBSS) {
1147 reclaim_address(sc, vap->iv_myaddr);
1148 ath_hal_setbssidmask(ah, sc->sc_hwbssidmask);
1149 if (vap->iv_opmode == IEEE80211_M_MBSS)
1152 if (vap->iv_opmode != IEEE80211_M_WDS)
1154 #ifdef IEEE80211_SUPPORT_TDMA
1155 /* TDMA operation ceases when the last vap is destroyed */
1156 if (sc->sc_tdma && sc->sc_nvaps == 0) {
1162 free(avp, M_80211_VAP);
1164 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
1166 * Restart rx+tx machines if still running (RUNNING will
1167 * be reset if we just destroyed the last vap).
1169 if (ath_startrecv(sc) != 0)
1170 if_printf(ifp, "%s: unable to restart recv logic\n",
1172 if (sc->sc_beacons) { /* restart beacons */
1173 #ifdef IEEE80211_SUPPORT_TDMA
1175 ath_tdma_config(sc, NULL);
1178 ath_beacon_config(sc, NULL);
1180 ath_hal_intrset(ah, sc->sc_imask);
1185 ath_suspend(struct ath_softc *sc)
1187 struct ifnet *ifp = sc->sc_ifp;
1188 struct ieee80211com *ic = ifp->if_l2com;
1190 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags %x\n",
1191 __func__, ifp->if_flags);
1193 sc->sc_resume_up = (ifp->if_flags & IFF_UP) != 0;
1194 if (ic->ic_opmode == IEEE80211_M_STA)
1197 ieee80211_suspend_all(ic);
1199 * NB: don't worry about putting the chip in low power
1200 * mode; pci will power off our socket on suspend and
1201 * cardbus detaches the device.
1206 * Reset the key cache since some parts do not reset the
1207 * contents on resume. First we clear all entries, then
1208 * re-load keys that the 802.11 layer assumes are setup
1212 ath_reset_keycache(struct ath_softc *sc)
1214 struct ifnet *ifp = sc->sc_ifp;
1215 struct ieee80211com *ic = ifp->if_l2com;
1216 struct ath_hal *ah = sc->sc_ah;
1219 for (i = 0; i < sc->sc_keymax; i++)
1220 ath_hal_keyreset(ah, i);
1221 ieee80211_crypto_reload_keys(ic);
1225 ath_resume(struct ath_softc *sc)
1227 struct ifnet *ifp = sc->sc_ifp;
1228 struct ieee80211com *ic = ifp->if_l2com;
1229 struct ath_hal *ah = sc->sc_ah;
1232 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags %x\n",
1233 __func__, ifp->if_flags);
1236 * Must reset the chip before we reload the
1237 * keycache as we were powered down on suspend.
1239 ath_hal_reset(ah, sc->sc_opmode,
1240 sc->sc_curchan != NULL ? sc->sc_curchan : ic->ic_curchan,
1242 ath_reset_keycache(sc);
1243 if (sc->sc_resume_up) {
1244 if (ic->ic_opmode == IEEE80211_M_STA) {
1247 * Program the beacon registers using the last rx'd
1248 * beacon frame and enable sync on the next beacon
1249 * we see. This should handle the case where we
1250 * wakeup and find the same AP and also the case where
1251 * we wakeup and need to roam. For the latter we
1252 * should get bmiss events that trigger a roam.
1254 ath_beacon_config(sc, NULL);
1255 sc->sc_syncbeacon = 1;
1257 ieee80211_resume_all(ic);
1259 if (sc->sc_softled) {
1260 ath_hal_gpioCfgOutput(ah, sc->sc_ledpin,
1261 HAL_GPIO_MUX_MAC_NETWORK_LED);
1262 ath_hal_gpioset(ah, sc->sc_ledpin, !sc->sc_ledon);
1267 ath_shutdown(struct ath_softc *sc)
1269 struct ifnet *ifp = sc->sc_ifp;
1271 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags %x\n",
1272 __func__, ifp->if_flags);
1275 /* NB: no point powering down chip as we're about to reboot */
1279 * Interrupt handler. Most of the actual processing is deferred.
1284 struct ath_softc *sc = arg;
1285 struct ifnet *ifp = sc->sc_ifp;
1286 struct ath_hal *ah = sc->sc_ah;
1289 if (sc->sc_invalid) {
1291 * The hardware is not ready/present, don't touch anything.
1292 * Note this can happen early on if the IRQ is shared.
1294 DPRINTF(sc, ATH_DEBUG_ANY, "%s: invalid; ignored\n", __func__);
1297 if (!ath_hal_intrpend(ah)) /* shared irq, not for us */
1299 if ((ifp->if_flags & IFF_UP) == 0 ||
1300 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
1303 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags 0x%x\n",
1304 __func__, ifp->if_flags);
1305 ath_hal_getisr(ah, &status); /* clear ISR */
1306 ath_hal_intrset(ah, 0); /* disable further intr's */
1310 * Figure out the reason(s) for the interrupt. Note
1311 * that the hal returns a pseudo-ISR that may include
1312 * bits we haven't explicitly enabled so we mask the
1313 * value to insure we only process bits we requested.
1315 ath_hal_getisr(ah, &status); /* NB: clears ISR too */
1316 DPRINTF(sc, ATH_DEBUG_INTR, "%s: status 0x%x\n", __func__, status);
1317 status &= sc->sc_imask; /* discard unasked for bits */
1318 if (status & HAL_INT_FATAL) {
1319 sc->sc_stats.ast_hardware++;
1320 ath_hal_intrset(ah, 0); /* disable intr's until reset */
1321 ath_fatal_proc(sc, 0);
1323 if (status & HAL_INT_SWBA) {
1325 * Software beacon alert--time to send a beacon.
1326 * Handle beacon transmission directly; deferring
1327 * this is too slow to meet timing constraints
1330 #ifdef IEEE80211_SUPPORT_TDMA
1332 if (sc->sc_tdmaswba == 0) {
1333 struct ieee80211com *ic = ifp->if_l2com;
1334 struct ieee80211vap *vap =
1335 TAILQ_FIRST(&ic->ic_vaps);
1336 ath_tdma_beacon_send(sc, vap);
1338 vap->iv_tdma->tdma_bintval;
1344 ath_beacon_proc(sc, 0);
1345 #ifdef IEEE80211_SUPPORT_SUPERG
1347 * Schedule the rx taskq in case there's no
1348 * traffic so any frames held on the staging
1349 * queue are aged and potentially flushed.
1351 taskqueue_enqueue(sc->sc_tq, &sc->sc_rxtask);
1355 if (status & HAL_INT_RXEOL) {
1357 * NB: the hardware should re-read the link when
1358 * RXE bit is written, but it doesn't work at
1359 * least on older hardware revs.
1361 sc->sc_stats.ast_rxeol++;
1362 sc->sc_rxlink = NULL;
1364 if (status & HAL_INT_TXURN) {
1365 sc->sc_stats.ast_txurn++;
1366 /* bump tx trigger level */
1367 ath_hal_updatetxtriglevel(ah, AH_TRUE);
1369 if (status & HAL_INT_RX)
1370 taskqueue_enqueue(sc->sc_tq, &sc->sc_rxtask);
1371 if (status & HAL_INT_TX)
1372 taskqueue_enqueue(sc->sc_tq, &sc->sc_txtask);
1373 if (status & HAL_INT_BMISS) {
1374 sc->sc_stats.ast_bmiss++;
1375 taskqueue_enqueue(sc->sc_tq, &sc->sc_bmisstask);
1377 if (status & HAL_INT_MIB) {
1378 sc->sc_stats.ast_mib++;
1380 * Disable interrupts until we service the MIB
1381 * interrupt; otherwise it will continue to fire.
1383 ath_hal_intrset(ah, 0);
1385 * Let the hal handle the event. We assume it will
1386 * clear whatever condition caused the interrupt.
1388 ath_hal_mibevent(ah, &sc->sc_halstats);
1389 ath_hal_intrset(ah, sc->sc_imask);
1391 if (status & HAL_INT_RXORN) {
1392 /* NB: hal marks HAL_INT_FATAL when RXORN is fatal */
1393 sc->sc_stats.ast_rxorn++;
1399 ath_fatal_proc(void *arg, int pending)
1401 struct ath_softc *sc = arg;
1402 struct ifnet *ifp = sc->sc_ifp;
1407 if_printf(ifp, "hardware error; resetting\n");
1409 * Fatal errors are unrecoverable. Typically these
1410 * are caused by DMA errors. Collect h/w state from
1411 * the hal so we can diagnose what's going on.
1413 if (ath_hal_getfatalstate(sc->sc_ah, &sp, &len)) {
1414 KASSERT(len >= 6*sizeof(u_int32_t), ("len %u bytes", len));
1416 if_printf(ifp, "0x%08x 0x%08x 0x%08x, 0x%08x 0x%08x 0x%08x\n",
1417 state[0], state[1] , state[2], state[3],
1418 state[4], state[5]);
1424 ath_bmiss_vap(struct ieee80211vap *vap)
1427 * Workaround phantom bmiss interrupts by sanity-checking
1428 * the time of our last rx'd frame. If it is within the
1429 * beacon miss interval then ignore the interrupt. If it's
1430 * truly a bmiss we'll get another interrupt soon and that'll
1431 * be dispatched up for processing. Note this applies only
1432 * for h/w beacon miss events.
1434 if ((vap->iv_flags_ext & IEEE80211_FEXT_SWBMISS) == 0) {
1435 struct ifnet *ifp = vap->iv_ic->ic_ifp;
1436 struct ath_softc *sc = ifp->if_softc;
1437 u_int64_t lastrx = sc->sc_lastrx;
1438 u_int64_t tsf = ath_hal_gettsf64(sc->sc_ah);
1439 u_int bmisstimeout =
1440 vap->iv_bmissthreshold * vap->iv_bss->ni_intval * 1024;
1442 DPRINTF(sc, ATH_DEBUG_BEACON,
1443 "%s: tsf %llu lastrx %lld (%llu) bmiss %u\n",
1444 __func__, (unsigned long long) tsf,
1445 (unsigned long long)(tsf - lastrx),
1446 (unsigned long long) lastrx, bmisstimeout);
1448 if (tsf - lastrx <= bmisstimeout) {
1449 sc->sc_stats.ast_bmiss_phantom++;
1453 ATH_VAP(vap)->av_bmiss(vap);
1457 ath_hal_gethangstate(struct ath_hal *ah, uint32_t mask, uint32_t *hangs)
1462 if (!ath_hal_getdiagstate(ah, 32, &mask, sizeof(&mask), &sp, &rsize))
1464 KASSERT(rsize == sizeof(uint32_t), ("resultsize %u", rsize));
1465 *hangs = *(uint32_t *)sp;
1470 ath_bmiss_proc(void *arg, int pending)
1472 struct ath_softc *sc = arg;
1473 struct ifnet *ifp = sc->sc_ifp;
1476 DPRINTF(sc, ATH_DEBUG_ANY, "%s: pending %u\n", __func__, pending);
1478 if (ath_hal_gethangstate(sc->sc_ah, 0xff, &hangs) && hangs != 0) {
1479 if_printf(ifp, "bb hang detected (0x%x), reseting\n", hangs);
1482 ieee80211_beacon_miss(ifp->if_l2com);
1486 * Handle TKIP MIC setup to deal hardware that doesn't do MIC
1487 * calcs together with WME. If necessary disable the crypto
1488 * hardware and mark the 802.11 state so keys will be setup
1489 * with the MIC work done in software.
1492 ath_settkipmic(struct ath_softc *sc)
1494 struct ifnet *ifp = sc->sc_ifp;
1495 struct ieee80211com *ic = ifp->if_l2com;
1497 if ((ic->ic_cryptocaps & IEEE80211_CRYPTO_TKIP) && !sc->sc_wmetkipmic) {
1498 if (ic->ic_flags & IEEE80211_F_WME) {
1499 ath_hal_settkipmic(sc->sc_ah, AH_FALSE);
1500 ic->ic_cryptocaps &= ~IEEE80211_CRYPTO_TKIPMIC;
1502 ath_hal_settkipmic(sc->sc_ah, AH_TRUE);
1503 ic->ic_cryptocaps |= IEEE80211_CRYPTO_TKIPMIC;
1511 struct ath_softc *sc = (struct ath_softc *) arg;
1512 struct ifnet *ifp = sc->sc_ifp;
1513 struct ieee80211com *ic = ifp->if_l2com;
1514 struct ath_hal *ah = sc->sc_ah;
1517 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags 0x%x\n",
1518 __func__, ifp->if_flags);
1522 * Stop anything previously setup. This is safe
1523 * whether this is the first time through or not.
1525 ath_stop_locked(ifp);
1528 * The basic interface to setting the hardware in a good
1529 * state is ``reset''. On return the hardware is known to
1530 * be powered up and with interrupts disabled. This must
1531 * be followed by initialization of the appropriate bits
1532 * and then setup of the interrupt mask.
1535 if (!ath_hal_reset(ah, sc->sc_opmode, ic->ic_curchan, AH_FALSE, &status)) {
1536 if_printf(ifp, "unable to reset hardware; hal status %u\n",
1541 ath_chan_change(sc, ic->ic_curchan);
1544 * Likewise this is set during reset so update
1545 * state cached in the driver.
1547 sc->sc_diversity = ath_hal_getdiversity(ah);
1548 sc->sc_lastlongcal = 0;
1549 sc->sc_resetcal = 1;
1550 sc->sc_lastcalreset = 0;
1553 * Setup the hardware after reset: the key cache
1554 * is filled as needed and the receive engine is
1555 * set going. Frame transmit is handled entirely
1556 * in the frame output path; there's nothing to do
1557 * here except setup the interrupt mask.
1559 if (ath_startrecv(sc) != 0) {
1560 if_printf(ifp, "unable to start recv logic\n");
1566 * Enable interrupts.
1568 sc->sc_imask = HAL_INT_RX | HAL_INT_TX
1569 | HAL_INT_RXEOL | HAL_INT_RXORN
1570 | HAL_INT_FATAL | HAL_INT_GLOBAL;
1572 * Enable MIB interrupts when there are hardware phy counters.
1573 * Note we only do this (at the moment) for station mode.
1575 if (sc->sc_needmib && ic->ic_opmode == IEEE80211_M_STA)
1576 sc->sc_imask |= HAL_INT_MIB;
1578 ifp->if_drv_flags |= IFF_DRV_RUNNING;
1579 callout_reset(&sc->sc_wd_ch, hz, ath_watchdog, sc);
1580 ath_hal_intrset(ah, sc->sc_imask);
1584 #ifdef ATH_TX99_DIAG
1585 if (sc->sc_tx99 != NULL)
1586 sc->sc_tx99->start(sc->sc_tx99);
1589 ieee80211_start_all(ic); /* start all vap's */
1593 ath_stop_locked(struct ifnet *ifp)
1595 struct ath_softc *sc = ifp->if_softc;
1596 struct ath_hal *ah = sc->sc_ah;
1598 DPRINTF(sc, ATH_DEBUG_ANY, "%s: invalid %u if_flags 0x%x\n",
1599 __func__, sc->sc_invalid, ifp->if_flags);
1601 ATH_LOCK_ASSERT(sc);
1602 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
1604 * Shutdown the hardware and driver:
1605 * reset 802.11 state machine
1607 * disable interrupts
1608 * turn off the radio
1609 * clear transmit machinery
1610 * clear receive machinery
1611 * drain and release tx queues
1612 * reclaim beacon resources
1613 * power down hardware
1615 * Note that some of this work is not possible if the
1616 * hardware is gone (invalid).
1618 #ifdef ATH_TX99_DIAG
1619 if (sc->sc_tx99 != NULL)
1620 sc->sc_tx99->stop(sc->sc_tx99);
1622 callout_stop(&sc->sc_wd_ch);
1623 sc->sc_wd_timer = 0;
1624 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1625 if (!sc->sc_invalid) {
1626 if (sc->sc_softled) {
1627 callout_stop(&sc->sc_ledtimer);
1628 ath_hal_gpioset(ah, sc->sc_ledpin,
1630 sc->sc_blinking = 0;
1632 ath_hal_intrset(ah, 0);
1635 if (!sc->sc_invalid) {
1637 ath_hal_phydisable(ah);
1639 sc->sc_rxlink = NULL;
1640 ath_beacon_free(sc); /* XXX not needed */
1645 ath_stop(struct ifnet *ifp)
1647 struct ath_softc *sc = ifp->if_softc;
1650 ath_stop_locked(ifp);
1655 * Reset the hardware w/o losing operational state. This is
1656 * basically a more efficient way of doing ath_stop, ath_init,
1657 * followed by state transitions to the current 802.11
1658 * operational state. Used to recover from various errors and
1659 * to reset or reload hardware state.
1662 ath_reset(struct ifnet *ifp)
1664 struct ath_softc *sc = ifp->if_softc;
1665 struct ieee80211com *ic = ifp->if_l2com;
1666 struct ath_hal *ah = sc->sc_ah;
1669 ath_hal_intrset(ah, 0); /* disable interrupts */
1670 ath_draintxq(sc); /* stop xmit side */
1671 ath_stoprecv(sc); /* stop recv side */
1672 ath_settkipmic(sc); /* configure TKIP MIC handling */
1673 /* NB: indicate channel change so we do a full reset */
1674 if (!ath_hal_reset(ah, sc->sc_opmode, ic->ic_curchan, AH_TRUE, &status))
1675 if_printf(ifp, "%s: unable to reset hardware; hal status %u\n",
1677 sc->sc_diversity = ath_hal_getdiversity(ah);
1678 if (ath_startrecv(sc) != 0) /* restart recv */
1679 if_printf(ifp, "%s: unable to start recv logic\n", __func__);
1681 * We may be doing a reset in response to an ioctl
1682 * that changes the channel so update any state that
1683 * might change as a result.
1685 ath_chan_change(sc, ic->ic_curchan);
1686 if (sc->sc_beacons) { /* restart beacons */
1687 #ifdef IEEE80211_SUPPORT_TDMA
1689 ath_tdma_config(sc, NULL);
1692 ath_beacon_config(sc, NULL);
1694 ath_hal_intrset(ah, sc->sc_imask);
1696 ath_start(ifp); /* restart xmit */
1701 ath_reset_vap(struct ieee80211vap *vap, u_long cmd)
1703 struct ieee80211com *ic = vap->iv_ic;
1704 struct ifnet *ifp = ic->ic_ifp;
1705 struct ath_softc *sc = ifp->if_softc;
1706 struct ath_hal *ah = sc->sc_ah;
1709 case IEEE80211_IOC_TXPOWER:
1711 * If per-packet TPC is enabled, then we have nothing
1712 * to do; otherwise we need to force the global limit.
1713 * All this can happen directly; no need to reset.
1715 if (!ath_hal_gettpc(ah))
1716 ath_hal_settxpowlimit(ah, ic->ic_txpowlimit);
1719 return ath_reset(ifp);
1722 static struct ath_buf *
1723 _ath_getbuf_locked(struct ath_softc *sc)
1727 ATH_TXBUF_LOCK_ASSERT(sc);
1729 bf = STAILQ_FIRST(&sc->sc_txbuf);
1730 if (bf != NULL && (bf->bf_flags & ATH_BUF_BUSY) == 0)
1731 STAILQ_REMOVE_HEAD(&sc->sc_txbuf, bf_list);
1735 DPRINTF(sc, ATH_DEBUG_XMIT, "%s: %s\n", __func__,
1736 STAILQ_FIRST(&sc->sc_txbuf) == NULL ?
1737 "out of xmit buffers" : "xmit buffer busy");
1742 static struct ath_buf *
1743 ath_getbuf(struct ath_softc *sc)
1748 bf = _ath_getbuf_locked(sc);
1750 struct ifnet *ifp = sc->sc_ifp;
1752 DPRINTF(sc, ATH_DEBUG_XMIT, "%s: stop queue\n", __func__);
1753 sc->sc_stats.ast_tx_qstop++;
1754 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1756 ATH_TXBUF_UNLOCK(sc);
1761 * Cleanup driver resources when we run out of buffers
1762 * while processing fragments; return the tx buffers
1763 * allocated and drop node references.
1766 ath_txfrag_cleanup(struct ath_softc *sc,
1767 ath_bufhead *frags, struct ieee80211_node *ni)
1769 struct ath_buf *bf, *next;
1771 ATH_TXBUF_LOCK_ASSERT(sc);
1773 STAILQ_FOREACH_SAFE(bf, frags, bf_list, next) {
1774 /* NB: bf assumed clean */
1775 STAILQ_REMOVE_HEAD(frags, bf_list);
1776 STAILQ_INSERT_HEAD(&sc->sc_txbuf, bf, bf_list);
1777 ieee80211_node_decref(ni);
1782 * Setup xmit of a fragmented frame. Allocate a buffer
1783 * for each frag and bump the node reference count to
1784 * reflect the held reference to be setup by ath_tx_start.
1787 ath_txfrag_setup(struct ath_softc *sc, ath_bufhead *frags,
1788 struct mbuf *m0, struct ieee80211_node *ni)
1794 for (m = m0->m_nextpkt; m != NULL; m = m->m_nextpkt) {
1795 bf = _ath_getbuf_locked(sc);
1796 if (bf == NULL) { /* out of buffers, cleanup */
1797 ath_txfrag_cleanup(sc, frags, ni);
1800 ieee80211_node_incref(ni);
1801 STAILQ_INSERT_TAIL(frags, bf, bf_list);
1803 ATH_TXBUF_UNLOCK(sc);
1805 return !STAILQ_EMPTY(frags);
1809 ath_start(struct ifnet *ifp)
1811 struct ath_softc *sc = ifp->if_softc;
1812 struct ieee80211_node *ni;
1814 struct mbuf *m, *next;
1817 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 || sc->sc_invalid)
1821 * Grab a TX buffer and associated resources.
1823 bf = ath_getbuf(sc);
1827 IFQ_DEQUEUE(&ifp->if_snd, m);
1830 STAILQ_INSERT_HEAD(&sc->sc_txbuf, bf, bf_list);
1831 ATH_TXBUF_UNLOCK(sc);
1834 ni = (struct ieee80211_node *) m->m_pkthdr.rcvif;
1836 * Check for fragmentation. If this frame
1837 * has been broken up verify we have enough
1838 * buffers to send all the fragments so all
1841 STAILQ_INIT(&frags);
1842 if ((m->m_flags & M_FRAG) &&
1843 !ath_txfrag_setup(sc, &frags, m, ni)) {
1844 DPRINTF(sc, ATH_DEBUG_XMIT,
1845 "%s: out of txfrag buffers\n", __func__);
1846 sc->sc_stats.ast_tx_nofrag++;
1854 * Pass the frame to the h/w for transmission.
1855 * Fragmented frames have each frag chained together
1856 * with m_nextpkt. We know there are sufficient ath_buf's
1857 * to send all the frags because of work done by
1858 * ath_txfrag_setup. We leave m_nextpkt set while
1859 * calling ath_tx_start so it can use it to extend the
1860 * the tx duration to cover the subsequent frag and
1861 * so it can reclaim all the mbufs in case of an error;
1862 * ath_tx_start clears m_nextpkt once it commits to
1863 * handing the frame to the hardware.
1865 next = m->m_nextpkt;
1866 if (ath_tx_start(sc, ni, bf, m)) {
1873 STAILQ_INSERT_HEAD(&sc->sc_txbuf, bf, bf_list);
1874 ath_txfrag_cleanup(sc, &frags, ni);
1875 ATH_TXBUF_UNLOCK(sc);
1877 ieee80211_free_node(ni);
1882 * Beware of state changing between frags.
1883 * XXX check sta power-save state?
1885 if (ni->ni_vap->iv_state != IEEE80211_S_RUN) {
1886 DPRINTF(sc, ATH_DEBUG_XMIT,
1887 "%s: flush fragmented packet, state %s\n",
1889 ieee80211_state_name[ni->ni_vap->iv_state]);
1894 bf = STAILQ_FIRST(&frags);
1895 KASSERT(bf != NULL, ("no buf for txfrag"));
1896 STAILQ_REMOVE_HEAD(&frags, bf_list);
1900 sc->sc_wd_timer = 5;
1905 ath_media_change(struct ifnet *ifp)
1907 int error = ieee80211_media_change(ifp);
1908 /* NB: only the fixed rate can change and that doesn't need a reset */
1909 return (error == ENETRESET ? 0 : error);
1914 ath_keyprint(struct ath_softc *sc, const char *tag, u_int ix,
1915 const HAL_KEYVAL *hk, const u_int8_t mac[IEEE80211_ADDR_LEN])
1917 static const char *ciphers[] = {
1927 printf("%s: [%02u] %-7s ", tag, ix, ciphers[hk->kv_type]);
1928 for (i = 0, n = hk->kv_len; i < n; i++)
1929 printf("%02x", hk->kv_val[i]);
1930 printf(" mac %s", ether_sprintf(mac));
1931 if (hk->kv_type == HAL_CIPHER_TKIP) {
1932 printf(" %s ", sc->sc_splitmic ? "mic" : "rxmic");
1933 for (i = 0; i < sizeof(hk->kv_mic); i++)
1934 printf("%02x", hk->kv_mic[i]);
1935 if (!sc->sc_splitmic) {
1937 for (i = 0; i < sizeof(hk->kv_txmic); i++)
1938 printf("%02x", hk->kv_txmic[i]);
1946 * Set a TKIP key into the hardware. This handles the
1947 * potential distribution of key state to multiple key
1948 * cache slots for TKIP.
1951 ath_keyset_tkip(struct ath_softc *sc, const struct ieee80211_key *k,
1952 HAL_KEYVAL *hk, const u_int8_t mac[IEEE80211_ADDR_LEN])
1954 #define IEEE80211_KEY_XR (IEEE80211_KEY_XMIT | IEEE80211_KEY_RECV)
1955 static const u_int8_t zerobssid[IEEE80211_ADDR_LEN];
1956 struct ath_hal *ah = sc->sc_ah;
1958 KASSERT(k->wk_cipher->ic_cipher == IEEE80211_CIPHER_TKIP,
1959 ("got a non-TKIP key, cipher %u", k->wk_cipher->ic_cipher));
1960 if ((k->wk_flags & IEEE80211_KEY_XR) == IEEE80211_KEY_XR) {
1961 if (sc->sc_splitmic) {
1963 * TX key goes at first index, RX key at the rx index.
1964 * The hal handles the MIC keys at index+64.
1966 memcpy(hk->kv_mic, k->wk_txmic, sizeof(hk->kv_mic));
1967 KEYPRINTF(sc, k->wk_keyix, hk, zerobssid);
1968 if (!ath_hal_keyset(ah, k->wk_keyix, hk, zerobssid))
1971 memcpy(hk->kv_mic, k->wk_rxmic, sizeof(hk->kv_mic));
1972 KEYPRINTF(sc, k->wk_keyix+32, hk, mac);
1973 /* XXX delete tx key on failure? */
1974 return ath_hal_keyset(ah, k->wk_keyix+32, hk, mac);
1977 * Room for both TX+RX MIC keys in one key cache
1978 * slot, just set key at the first index; the hal
1979 * will handle the rest.
1981 memcpy(hk->kv_mic, k->wk_rxmic, sizeof(hk->kv_mic));
1982 memcpy(hk->kv_txmic, k->wk_txmic, sizeof(hk->kv_txmic));
1983 KEYPRINTF(sc, k->wk_keyix, hk, mac);
1984 return ath_hal_keyset(ah, k->wk_keyix, hk, mac);
1986 } else if (k->wk_flags & IEEE80211_KEY_XMIT) {
1987 if (sc->sc_splitmic) {
1989 * NB: must pass MIC key in expected location when
1990 * the keycache only holds one MIC key per entry.
1992 memcpy(hk->kv_mic, k->wk_txmic, sizeof(hk->kv_txmic));
1994 memcpy(hk->kv_txmic, k->wk_txmic, sizeof(hk->kv_txmic));
1995 KEYPRINTF(sc, k->wk_keyix, hk, mac);
1996 return ath_hal_keyset(ah, k->wk_keyix, hk, mac);
1997 } else if (k->wk_flags & IEEE80211_KEY_RECV) {
1998 memcpy(hk->kv_mic, k->wk_rxmic, sizeof(hk->kv_mic));
1999 KEYPRINTF(sc, k->wk_keyix, hk, mac);
2000 return ath_hal_keyset(ah, k->wk_keyix, hk, mac);
2003 #undef IEEE80211_KEY_XR
2007 * Set a net80211 key into the hardware. This handles the
2008 * potential distribution of key state to multiple key
2009 * cache slots for TKIP with hardware MIC support.
2012 ath_keyset(struct ath_softc *sc, const struct ieee80211_key *k,
2013 struct ieee80211_node *bss)
2015 #define N(a) (sizeof(a)/sizeof(a[0]))
2016 static const u_int8_t ciphermap[] = {
2017 HAL_CIPHER_WEP, /* IEEE80211_CIPHER_WEP */
2018 HAL_CIPHER_TKIP, /* IEEE80211_CIPHER_TKIP */
2019 HAL_CIPHER_AES_OCB, /* IEEE80211_CIPHER_AES_OCB */
2020 HAL_CIPHER_AES_CCM, /* IEEE80211_CIPHER_AES_CCM */
2021 (u_int8_t) -1, /* 4 is not allocated */
2022 HAL_CIPHER_CKIP, /* IEEE80211_CIPHER_CKIP */
2023 HAL_CIPHER_CLR, /* IEEE80211_CIPHER_NONE */
2025 struct ath_hal *ah = sc->sc_ah;
2026 const struct ieee80211_cipher *cip = k->wk_cipher;
2027 u_int8_t gmac[IEEE80211_ADDR_LEN];
2028 const u_int8_t *mac;
2031 memset(&hk, 0, sizeof(hk));
2033 * Software crypto uses a "clear key" so non-crypto
2034 * state kept in the key cache are maintained and
2035 * so that rx frames have an entry to match.
2037 if ((k->wk_flags & IEEE80211_KEY_SWCRYPT) == 0) {
2038 KASSERT(cip->ic_cipher < N(ciphermap),
2039 ("invalid cipher type %u", cip->ic_cipher));
2040 hk.kv_type = ciphermap[cip->ic_cipher];
2041 hk.kv_len = k->wk_keylen;
2042 memcpy(hk.kv_val, k->wk_key, k->wk_keylen);
2044 hk.kv_type = HAL_CIPHER_CLR;
2046 if ((k->wk_flags & IEEE80211_KEY_GROUP) && sc->sc_mcastkey) {
2048 * Group keys on hardware that supports multicast frame
2049 * key search use a MAC that is the sender's address with
2050 * the high bit set instead of the app-specified address.
2052 IEEE80211_ADDR_COPY(gmac, bss->ni_macaddr);
2056 mac = k->wk_macaddr;
2058 if (hk.kv_type == HAL_CIPHER_TKIP &&
2059 (k->wk_flags & IEEE80211_KEY_SWMIC) == 0) {
2060 return ath_keyset_tkip(sc, k, &hk, mac);
2062 KEYPRINTF(sc, k->wk_keyix, &hk, mac);
2063 return ath_hal_keyset(ah, k->wk_keyix, &hk, mac);
2069 * Allocate tx/rx key slots for TKIP. We allocate two slots for
2070 * each key, one for decrypt/encrypt and the other for the MIC.
2073 key_alloc_2pair(struct ath_softc *sc,
2074 ieee80211_keyix *txkeyix, ieee80211_keyix *rxkeyix)
2076 #define N(a) (sizeof(a)/sizeof(a[0]))
2079 KASSERT(sc->sc_splitmic, ("key cache !split"));
2080 /* XXX could optimize */
2081 for (i = 0; i < N(sc->sc_keymap)/4; i++) {
2082 u_int8_t b = sc->sc_keymap[i];
2085 * One or more slots in this byte are free.
2093 /* XXX IEEE80211_KEY_XMIT | IEEE80211_KEY_RECV */
2094 if (isset(sc->sc_keymap, keyix+32) ||
2095 isset(sc->sc_keymap, keyix+64) ||
2096 isset(sc->sc_keymap, keyix+32+64)) {
2097 /* full pair unavailable */
2099 if (keyix == (i+1)*NBBY) {
2100 /* no slots were appropriate, advance */
2105 setbit(sc->sc_keymap, keyix);
2106 setbit(sc->sc_keymap, keyix+64);
2107 setbit(sc->sc_keymap, keyix+32);
2108 setbit(sc->sc_keymap, keyix+32+64);
2109 DPRINTF(sc, ATH_DEBUG_KEYCACHE,
2110 "%s: key pair %u,%u %u,%u\n",
2111 __func__, keyix, keyix+64,
2112 keyix+32, keyix+32+64);
2114 *rxkeyix = keyix+32;
2118 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s: out of pair space\n", __func__);
2124 * Allocate tx/rx key slots for TKIP. We allocate two slots for
2125 * each key, one for decrypt/encrypt and the other for the MIC.
2128 key_alloc_pair(struct ath_softc *sc,
2129 ieee80211_keyix *txkeyix, ieee80211_keyix *rxkeyix)
2131 #define N(a) (sizeof(a)/sizeof(a[0]))
2134 KASSERT(!sc->sc_splitmic, ("key cache split"));
2135 /* XXX could optimize */
2136 for (i = 0; i < N(sc->sc_keymap)/4; i++) {
2137 u_int8_t b = sc->sc_keymap[i];
2140 * One or more slots in this byte are free.
2148 if (isset(sc->sc_keymap, keyix+64)) {
2149 /* full pair unavailable */
2151 if (keyix == (i+1)*NBBY) {
2152 /* no slots were appropriate, advance */
2157 setbit(sc->sc_keymap, keyix);
2158 setbit(sc->sc_keymap, keyix+64);
2159 DPRINTF(sc, ATH_DEBUG_KEYCACHE,
2160 "%s: key pair %u,%u\n",
2161 __func__, keyix, keyix+64);
2162 *txkeyix = *rxkeyix = keyix;
2166 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s: out of pair space\n", __func__);
2172 * Allocate a single key cache slot.
2175 key_alloc_single(struct ath_softc *sc,
2176 ieee80211_keyix *txkeyix, ieee80211_keyix *rxkeyix)
2178 #define N(a) (sizeof(a)/sizeof(a[0]))
2181 /* XXX try i,i+32,i+64,i+32+64 to minimize key pair conflicts */
2182 for (i = 0; i < N(sc->sc_keymap); i++) {
2183 u_int8_t b = sc->sc_keymap[i];
2186 * One or more slots are free.
2191 setbit(sc->sc_keymap, keyix);
2192 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s: key %u\n",
2194 *txkeyix = *rxkeyix = keyix;
2198 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s: out of space\n", __func__);
2204 * Allocate one or more key cache slots for a uniacst key. The
2205 * key itself is needed only to identify the cipher. For hardware
2206 * TKIP with split cipher+MIC keys we allocate two key cache slot
2207 * pairs so that we can setup separate TX and RX MIC keys. Note
2208 * that the MIC key for a TKIP key at slot i is assumed by the
2209 * hardware to be at slot i+64. This limits TKIP keys to the first
2213 ath_key_alloc(struct ieee80211vap *vap, struct ieee80211_key *k,
2214 ieee80211_keyix *keyix, ieee80211_keyix *rxkeyix)
2216 struct ath_softc *sc = vap->iv_ic->ic_ifp->if_softc;
2219 * Group key allocation must be handled specially for
2220 * parts that do not support multicast key cache search
2221 * functionality. For those parts the key id must match
2222 * the h/w key index so lookups find the right key. On
2223 * parts w/ the key search facility we install the sender's
2224 * mac address (with the high bit set) and let the hardware
2225 * find the key w/o using the key id. This is preferred as
2226 * it permits us to support multiple users for adhoc and/or
2227 * multi-station operation.
2229 if (k->wk_keyix != IEEE80211_KEYIX_NONE) {
2231 * Only global keys should have key index assigned.
2233 if (!(&vap->iv_nw_keys[0] <= k &&
2234 k < &vap->iv_nw_keys[IEEE80211_WEP_NKID])) {
2235 /* should not happen */
2236 DPRINTF(sc, ATH_DEBUG_KEYCACHE,
2237 "%s: bogus group key\n", __func__);
2240 if (vap->iv_opmode != IEEE80211_M_HOSTAP ||
2241 !(k->wk_flags & IEEE80211_KEY_GROUP) ||
2244 * XXX we pre-allocate the global keys so
2245 * have no way to check if they've already
2248 *keyix = *rxkeyix = k - vap->iv_nw_keys;
2252 * Group key and device supports multicast key search.
2254 k->wk_keyix = IEEE80211_KEYIX_NONE;
2258 * We allocate two pair for TKIP when using the h/w to do
2259 * the MIC. For everything else, including software crypto,
2260 * we allocate a single entry. Note that s/w crypto requires
2261 * a pass-through slot on the 5211 and 5212. The 5210 does
2262 * not support pass-through cache entries and we map all
2263 * those requests to slot 0.
2265 if (k->wk_flags & IEEE80211_KEY_SWCRYPT) {
2266 return key_alloc_single(sc, keyix, rxkeyix);
2267 } else if (k->wk_cipher->ic_cipher == IEEE80211_CIPHER_TKIP &&
2268 (k->wk_flags & IEEE80211_KEY_SWMIC) == 0) {
2269 if (sc->sc_splitmic)
2270 return key_alloc_2pair(sc, keyix, rxkeyix);
2272 return key_alloc_pair(sc, keyix, rxkeyix);
2274 return key_alloc_single(sc, keyix, rxkeyix);
2279 * Delete an entry in the key cache allocated by ath_key_alloc.
2282 ath_key_delete(struct ieee80211vap *vap, const struct ieee80211_key *k)
2284 struct ath_softc *sc = vap->iv_ic->ic_ifp->if_softc;
2285 struct ath_hal *ah = sc->sc_ah;
2286 const struct ieee80211_cipher *cip = k->wk_cipher;
2287 u_int keyix = k->wk_keyix;
2289 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s: delete key %u\n", __func__, keyix);
2291 ath_hal_keyreset(ah, keyix);
2293 * Handle split tx/rx keying required for TKIP with h/w MIC.
2295 if (cip->ic_cipher == IEEE80211_CIPHER_TKIP &&
2296 (k->wk_flags & IEEE80211_KEY_SWMIC) == 0 && sc->sc_splitmic)
2297 ath_hal_keyreset(ah, keyix+32); /* RX key */
2298 if (keyix >= IEEE80211_WEP_NKID) {
2300 * Don't touch keymap entries for global keys so
2301 * they are never considered for dynamic allocation.
2303 clrbit(sc->sc_keymap, keyix);
2304 if (cip->ic_cipher == IEEE80211_CIPHER_TKIP &&
2305 (k->wk_flags & IEEE80211_KEY_SWMIC) == 0) {
2306 clrbit(sc->sc_keymap, keyix+64); /* TX key MIC */
2307 if (sc->sc_splitmic) {
2308 /* +32 for RX key, +32+64 for RX key MIC */
2309 clrbit(sc->sc_keymap, keyix+32);
2310 clrbit(sc->sc_keymap, keyix+32+64);
2318 * Set the key cache contents for the specified key. Key cache
2319 * slot(s) must already have been allocated by ath_key_alloc.
2322 ath_key_set(struct ieee80211vap *vap, const struct ieee80211_key *k,
2323 const u_int8_t mac[IEEE80211_ADDR_LEN])
2325 struct ath_softc *sc = vap->iv_ic->ic_ifp->if_softc;
2327 return ath_keyset(sc, k, vap->iv_bss);
2331 * Block/unblock tx+rx processing while a key change is done.
2332 * We assume the caller serializes key management operations
2333 * so we only need to worry about synchronization with other
2334 * uses that originate in the driver.
2337 ath_key_update_begin(struct ieee80211vap *vap)
2339 struct ifnet *ifp = vap->iv_ic->ic_ifp;
2340 struct ath_softc *sc = ifp->if_softc;
2342 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s:\n", __func__);
2343 taskqueue_block(sc->sc_tq);
2344 IF_LOCK(&ifp->if_snd); /* NB: doesn't block mgmt frames */
2348 ath_key_update_end(struct ieee80211vap *vap)
2350 struct ifnet *ifp = vap->iv_ic->ic_ifp;
2351 struct ath_softc *sc = ifp->if_softc;
2353 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s:\n", __func__);
2354 IF_UNLOCK(&ifp->if_snd);
2355 taskqueue_unblock(sc->sc_tq);
2359 * Calculate the receive filter according to the
2360 * operating mode and state:
2362 * o always accept unicast, broadcast, and multicast traffic
2363 * o accept PHY error frames when hardware doesn't have MIB support
2364 * to count and we need them for ANI (sta mode only until recently)
2365 * and we are not scanning (ANI is disabled)
2366 * NB: older hal's add rx filter bits out of sight and we need to
2367 * blindly preserve them
2368 * o probe request frames are accepted only when operating in
2369 * hostap, adhoc, mesh, or monitor modes
2370 * o enable promiscuous mode
2371 * - when in monitor mode
2372 * - if interface marked PROMISC (assumes bridge setting is filtered)
2374 * - when operating in station mode for collecting rssi data when
2375 * the station is otherwise quiet, or
2376 * - when operating in adhoc mode so the 802.11 layer creates
2377 * node table entries for peers,
2379 * - when doing s/w beacon miss (e.g. for ap+sta)
2380 * - when operating in ap mode in 11g to detect overlapping bss that
2381 * require protection
2382 * - when operating in mesh mode to detect neighbors
2383 * o accept control frames:
2384 * - when in monitor mode
2385 * XXX BAR frames for 11n
2386 * XXX HT protection for 11n
2389 ath_calcrxfilter(struct ath_softc *sc)
2391 struct ifnet *ifp = sc->sc_ifp;
2392 struct ieee80211com *ic = ifp->if_l2com;
2395 rfilt = HAL_RX_FILTER_UCAST | HAL_RX_FILTER_BCAST | HAL_RX_FILTER_MCAST;
2396 if (!sc->sc_needmib && !sc->sc_scanning)
2397 rfilt |= HAL_RX_FILTER_PHYERR;
2398 if (ic->ic_opmode != IEEE80211_M_STA)
2399 rfilt |= HAL_RX_FILTER_PROBEREQ;
2400 /* XXX ic->ic_monvaps != 0? */
2401 if (ic->ic_opmode == IEEE80211_M_MONITOR || (ifp->if_flags & IFF_PROMISC))
2402 rfilt |= HAL_RX_FILTER_PROM;
2403 if (ic->ic_opmode == IEEE80211_M_STA ||
2404 ic->ic_opmode == IEEE80211_M_IBSS ||
2405 sc->sc_swbmiss || sc->sc_scanning)
2406 rfilt |= HAL_RX_FILTER_BEACON;
2408 * NB: We don't recalculate the rx filter when
2409 * ic_protmode changes; otherwise we could do
2410 * this only when ic_protmode != NONE.
2412 if (ic->ic_opmode == IEEE80211_M_HOSTAP &&
2413 IEEE80211_IS_CHAN_ANYG(ic->ic_curchan))
2414 rfilt |= HAL_RX_FILTER_BEACON;
2415 if (sc->sc_nmeshvaps) {
2416 rfilt |= HAL_RX_FILTER_BEACON;
2417 if (sc->sc_hasbmatch)
2418 rfilt |= HAL_RX_FILTER_BSSID;
2420 rfilt |= HAL_RX_FILTER_PROM;
2422 if (ic->ic_opmode == IEEE80211_M_MONITOR)
2423 rfilt |= HAL_RX_FILTER_CONTROL;
2424 DPRINTF(sc, ATH_DEBUG_MODE, "%s: RX filter 0x%x, %s if_flags 0x%x\n",
2425 __func__, rfilt, ieee80211_opmode_name[ic->ic_opmode], ifp->if_flags);
2430 ath_update_promisc(struct ifnet *ifp)
2432 struct ath_softc *sc = ifp->if_softc;
2435 /* configure rx filter */
2436 rfilt = ath_calcrxfilter(sc);
2437 ath_hal_setrxfilter(sc->sc_ah, rfilt);
2439 DPRINTF(sc, ATH_DEBUG_MODE, "%s: RX filter 0x%x\n", __func__, rfilt);
2443 ath_update_mcast(struct ifnet *ifp)
2445 struct ath_softc *sc = ifp->if_softc;
2448 /* calculate and install multicast filter */
2449 if ((ifp->if_flags & IFF_ALLMULTI) == 0) {
2450 struct ifmultiaddr *ifma;
2452 * Merge multicast addresses to form the hardware filter.
2454 mfilt[0] = mfilt[1] = 0;
2455 if_maddr_rlock(ifp); /* XXX need some fiddling to remove? */
2456 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
2461 /* calculate XOR of eight 6bit values */
2462 dl = LLADDR((struct sockaddr_dl *) ifma->ifma_addr);
2463 val = LE_READ_4(dl + 0);
2464 pos = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
2465 val = LE_READ_4(dl + 3);
2466 pos ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
2468 mfilt[pos / 32] |= (1 << (pos % 32));
2470 if_maddr_runlock(ifp);
2472 mfilt[0] = mfilt[1] = ~0;
2473 ath_hal_setmcastfilter(sc->sc_ah, mfilt[0], mfilt[1]);
2474 DPRINTF(sc, ATH_DEBUG_MODE, "%s: MC filter %08x:%08x\n",
2475 __func__, mfilt[0], mfilt[1]);
2479 ath_mode_init(struct ath_softc *sc)
2481 struct ifnet *ifp = sc->sc_ifp;
2482 struct ath_hal *ah = sc->sc_ah;
2485 /* configure rx filter */
2486 rfilt = ath_calcrxfilter(sc);
2487 ath_hal_setrxfilter(ah, rfilt);
2489 /* configure operational mode */
2490 ath_hal_setopmode(ah);
2492 /* handle any link-level address change */
2493 ath_hal_setmac(ah, IF_LLADDR(ifp));
2495 /* calculate and install multicast filter */
2496 ath_update_mcast(ifp);
2500 * Set the slot time based on the current setting.
2503 ath_setslottime(struct ath_softc *sc)
2505 struct ieee80211com *ic = sc->sc_ifp->if_l2com;
2506 struct ath_hal *ah = sc->sc_ah;
2509 if (IEEE80211_IS_CHAN_HALF(ic->ic_curchan))
2511 else if (IEEE80211_IS_CHAN_QUARTER(ic->ic_curchan))
2513 else if (IEEE80211_IS_CHAN_ANYG(ic->ic_curchan)) {
2514 /* honor short/long slot time only in 11g */
2515 /* XXX shouldn't honor on pure g or turbo g channel */
2516 if (ic->ic_flags & IEEE80211_F_SHSLOT)
2517 usec = HAL_SLOT_TIME_9;
2519 usec = HAL_SLOT_TIME_20;
2521 usec = HAL_SLOT_TIME_9;
2523 DPRINTF(sc, ATH_DEBUG_RESET,
2524 "%s: chan %u MHz flags 0x%x %s slot, %u usec\n",
2525 __func__, ic->ic_curchan->ic_freq, ic->ic_curchan->ic_flags,
2526 ic->ic_flags & IEEE80211_F_SHSLOT ? "short" : "long", usec);
2528 ath_hal_setslottime(ah, usec);
2529 sc->sc_updateslot = OK;
2533 * Callback from the 802.11 layer to update the
2534 * slot time based on the current setting.
2537 ath_updateslot(struct ifnet *ifp)
2539 struct ath_softc *sc = ifp->if_softc;
2540 struct ieee80211com *ic = ifp->if_l2com;
2543 * When not coordinating the BSS, change the hardware
2544 * immediately. For other operation we defer the change
2545 * until beacon updates have propagated to the stations.
2547 if (ic->ic_opmode == IEEE80211_M_HOSTAP ||
2548 ic->ic_opmode == IEEE80211_M_MBSS)
2549 sc->sc_updateslot = UPDATE;
2551 ath_setslottime(sc);
2555 * Setup a h/w transmit queue for beacons.
2558 ath_beaconq_setup(struct ath_hal *ah)
2562 memset(&qi, 0, sizeof(qi));
2563 qi.tqi_aifs = HAL_TXQ_USEDEFAULT;
2564 qi.tqi_cwmin = HAL_TXQ_USEDEFAULT;
2565 qi.tqi_cwmax = HAL_TXQ_USEDEFAULT;
2566 /* NB: for dynamic turbo, don't enable any other interrupts */
2567 qi.tqi_qflags = HAL_TXQ_TXDESCINT_ENABLE;
2568 return ath_hal_setuptxqueue(ah, HAL_TX_QUEUE_BEACON, &qi);
2572 * Setup the transmit queue parameters for the beacon queue.
2575 ath_beaconq_config(struct ath_softc *sc)
2577 #define ATH_EXPONENT_TO_VALUE(v) ((1<<(v))-1)
2578 struct ieee80211com *ic = sc->sc_ifp->if_l2com;
2579 struct ath_hal *ah = sc->sc_ah;
2582 ath_hal_gettxqueueprops(ah, sc->sc_bhalq, &qi);
2583 if (ic->ic_opmode == IEEE80211_M_HOSTAP ||
2584 ic->ic_opmode == IEEE80211_M_MBSS) {
2586 * Always burst out beacon and CAB traffic.
2588 qi.tqi_aifs = ATH_BEACON_AIFS_DEFAULT;
2589 qi.tqi_cwmin = ATH_BEACON_CWMIN_DEFAULT;
2590 qi.tqi_cwmax = ATH_BEACON_CWMAX_DEFAULT;
2592 struct wmeParams *wmep =
2593 &ic->ic_wme.wme_chanParams.cap_wmeParams[WME_AC_BE];
2595 * Adhoc mode; important thing is to use 2x cwmin.
2597 qi.tqi_aifs = wmep->wmep_aifsn;
2598 qi.tqi_cwmin = 2*ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmin);
2599 qi.tqi_cwmax = ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmax);
2602 if (!ath_hal_settxqueueprops(ah, sc->sc_bhalq, &qi)) {
2603 device_printf(sc->sc_dev, "unable to update parameters for "
2604 "beacon hardware queue!\n");
2607 ath_hal_resettxqueue(ah, sc->sc_bhalq); /* push to h/w */
2610 #undef ATH_EXPONENT_TO_VALUE
2614 * Allocate and setup an initial beacon frame.
2617 ath_beacon_alloc(struct ath_softc *sc, struct ieee80211_node *ni)
2619 struct ieee80211vap *vap = ni->ni_vap;
2620 struct ath_vap *avp = ATH_VAP(vap);
2626 if (bf->bf_m != NULL) {
2627 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap);
2631 if (bf->bf_node != NULL) {
2632 ieee80211_free_node(bf->bf_node);
2637 * NB: the beacon data buffer must be 32-bit aligned;
2638 * we assume the mbuf routines will return us something
2639 * with this alignment (perhaps should assert).
2641 m = ieee80211_beacon_alloc(ni, &avp->av_boff);
2643 device_printf(sc->sc_dev, "%s: cannot get mbuf\n", __func__);
2644 sc->sc_stats.ast_be_nombuf++;
2647 error = bus_dmamap_load_mbuf_sg(sc->sc_dmat, bf->bf_dmamap, m,
2648 bf->bf_segs, &bf->bf_nseg,
2651 device_printf(sc->sc_dev,
2652 "%s: cannot map mbuf, bus_dmamap_load_mbuf_sg returns %d\n",
2659 * Calculate a TSF adjustment factor required for staggered
2660 * beacons. Note that we assume the format of the beacon
2661 * frame leaves the tstamp field immediately following the
2664 if (sc->sc_stagbeacons && avp->av_bslot > 0) {
2666 struct ieee80211_frame *wh;
2669 * The beacon interval is in TU's; the TSF is in usecs.
2670 * We figure out how many TU's to add to align the timestamp
2671 * then convert to TSF units and handle byte swapping before
2672 * inserting it in the frame. The hardware will then add this
2673 * each time a beacon frame is sent. Note that we align vap's
2674 * 1..N and leave vap 0 untouched. This means vap 0 has a
2675 * timestamp in one beacon interval while the others get a
2676 * timstamp aligned to the next interval.
2678 tsfadjust = ni->ni_intval *
2679 (ATH_BCBUF - avp->av_bslot) / ATH_BCBUF;
2680 tsfadjust = htole64(tsfadjust << 10); /* TU -> TSF */
2682 DPRINTF(sc, ATH_DEBUG_BEACON,
2683 "%s: %s beacons bslot %d intval %u tsfadjust %llu\n",
2684 __func__, sc->sc_stagbeacons ? "stagger" : "burst",
2685 avp->av_bslot, ni->ni_intval,
2686 (long long unsigned) le64toh(tsfadjust));
2688 wh = mtod(m, struct ieee80211_frame *);
2689 memcpy(&wh[1], &tsfadjust, sizeof(tsfadjust));
2692 bf->bf_node = ieee80211_ref_node(ni);
2698 * Setup the beacon frame for transmit.
2701 ath_beacon_setup(struct ath_softc *sc, struct ath_buf *bf)
2703 #define USE_SHPREAMBLE(_ic) \
2704 (((_ic)->ic_flags & (IEEE80211_F_SHPREAMBLE | IEEE80211_F_USEBARKER))\
2705 == IEEE80211_F_SHPREAMBLE)
2706 struct ieee80211_node *ni = bf->bf_node;
2707 struct ieee80211com *ic = ni->ni_ic;
2708 struct mbuf *m = bf->bf_m;
2709 struct ath_hal *ah = sc->sc_ah;
2710 struct ath_desc *ds;
2712 const HAL_RATE_TABLE *rt;
2715 DPRINTF(sc, ATH_DEBUG_BEACON_PROC, "%s: m %p len %u\n",
2716 __func__, m, m->m_len);
2718 /* setup descriptors */
2721 flags = HAL_TXDESC_NOACK;
2722 if (ic->ic_opmode == IEEE80211_M_IBSS && sc->sc_hasveol) {
2723 ds->ds_link = bf->bf_daddr; /* self-linked */
2724 flags |= HAL_TXDESC_VEOL;
2726 * Let hardware handle antenna switching.
2728 antenna = sc->sc_txantenna;
2732 * Switch antenna every 4 beacons.
2733 * XXX assumes two antenna
2735 if (sc->sc_txantenna != 0)
2736 antenna = sc->sc_txantenna;
2737 else if (sc->sc_stagbeacons && sc->sc_nbcnvaps != 0)
2738 antenna = ((sc->sc_stats.ast_be_xmit / sc->sc_nbcnvaps) & 4 ? 2 : 1);
2740 antenna = (sc->sc_stats.ast_be_xmit & 4 ? 2 : 1);
2743 KASSERT(bf->bf_nseg == 1,
2744 ("multi-segment beacon frame; nseg %u", bf->bf_nseg));
2745 ds->ds_data = bf->bf_segs[0].ds_addr;
2747 * Calculate rate code.
2748 * XXX everything at min xmit rate
2751 rt = sc->sc_currates;
2752 rate = rt->info[rix].rateCode;
2753 if (USE_SHPREAMBLE(ic))
2754 rate |= rt->info[rix].shortPreamble;
2755 ath_hal_setuptxdesc(ah, ds
2756 , m->m_len + IEEE80211_CRC_LEN /* frame length */
2757 , sizeof(struct ieee80211_frame)/* header length */
2758 , HAL_PKT_TYPE_BEACON /* Atheros packet type */
2759 , ni->ni_txpower /* txpower XXX */
2760 , rate, 1 /* series 0 rate/tries */
2761 , HAL_TXKEYIX_INVALID /* no encryption */
2762 , antenna /* antenna mode */
2763 , flags /* no ack, veol for beacons */
2764 , 0 /* rts/cts rate */
2765 , 0 /* rts/cts duration */
2767 /* NB: beacon's BufLen must be a multiple of 4 bytes */
2768 ath_hal_filltxdesc(ah, ds
2769 , roundup(m->m_len, 4) /* buffer length */
2770 , AH_TRUE /* first segment */
2771 , AH_TRUE /* last segment */
2772 , ds /* first descriptor */
2777 #undef USE_SHPREAMBLE
2781 ath_beacon_update(struct ieee80211vap *vap, int item)
2783 struct ieee80211_beacon_offsets *bo = &ATH_VAP(vap)->av_boff;
2785 setbit(bo->bo_flags, item);
2789 * Append the contents of src to dst; both queues
2790 * are assumed to be locked.
2793 ath_txqmove(struct ath_txq *dst, struct ath_txq *src)
2795 STAILQ_CONCAT(&dst->axq_q, &src->axq_q);
2796 dst->axq_link = src->axq_link;
2797 src->axq_link = NULL;
2798 dst->axq_depth += src->axq_depth;
2803 * Transmit a beacon frame at SWBA. Dynamic updates to the
2804 * frame contents are done as needed and the slot time is
2805 * also adjusted based on current state.
2808 ath_beacon_proc(void *arg, int pending)
2810 struct ath_softc *sc = arg;
2811 struct ath_hal *ah = sc->sc_ah;
2812 struct ieee80211vap *vap;
2817 DPRINTF(sc, ATH_DEBUG_BEACON_PROC, "%s: pending %u\n",
2820 * Check if the previous beacon has gone out. If
2821 * not don't try to post another, skip this period
2822 * and wait for the next. Missed beacons indicate
2823 * a problem and should not occur. If we miss too
2824 * many consecutive beacons reset the device.
2826 if (ath_hal_numtxpending(ah, sc->sc_bhalq) != 0) {
2827 sc->sc_bmisscount++;
2828 DPRINTF(sc, ATH_DEBUG_BEACON,
2829 "%s: missed %u consecutive beacons\n",
2830 __func__, sc->sc_bmisscount);
2831 if (sc->sc_bmisscount >= ath_bstuck_threshold)
2832 taskqueue_enqueue(sc->sc_tq, &sc->sc_bstucktask);
2835 if (sc->sc_bmisscount != 0) {
2836 DPRINTF(sc, ATH_DEBUG_BEACON,
2837 "%s: resume beacon xmit after %u misses\n",
2838 __func__, sc->sc_bmisscount);
2839 sc->sc_bmisscount = 0;
2842 if (sc->sc_stagbeacons) { /* staggered beacons */
2843 struct ieee80211com *ic = sc->sc_ifp->if_l2com;
2846 tsftu = ath_hal_gettsf32(ah) >> 10;
2848 slot = ((tsftu % ic->ic_lintval) * ATH_BCBUF) / ic->ic_lintval;
2849 vap = sc->sc_bslot[(slot+1) % ATH_BCBUF];
2851 if (vap != NULL && vap->iv_state >= IEEE80211_S_RUN) {
2852 bf = ath_beacon_generate(sc, vap);
2854 bfaddr = bf->bf_daddr;
2856 } else { /* burst'd beacons */
2857 uint32_t *bflink = &bfaddr;
2859 for (slot = 0; slot < ATH_BCBUF; slot++) {
2860 vap = sc->sc_bslot[slot];
2861 if (vap != NULL && vap->iv_state >= IEEE80211_S_RUN) {
2862 bf = ath_beacon_generate(sc, vap);
2864 *bflink = bf->bf_daddr;
2865 bflink = &bf->bf_desc->ds_link;
2869 *bflink = 0; /* terminate list */
2873 * Handle slot time change when a non-ERP station joins/leaves
2874 * an 11g network. The 802.11 layer notifies us via callback,
2875 * we mark updateslot, then wait one beacon before effecting
2876 * the change. This gives associated stations at least one
2877 * beacon interval to note the state change.
2880 if (sc->sc_updateslot == UPDATE) {
2881 sc->sc_updateslot = COMMIT; /* commit next beacon */
2882 sc->sc_slotupdate = slot;
2883 } else if (sc->sc_updateslot == COMMIT && sc->sc_slotupdate == slot)
2884 ath_setslottime(sc); /* commit change to h/w */
2887 * Check recent per-antenna transmit statistics and flip
2888 * the default antenna if noticeably more frames went out
2889 * on the non-default antenna.
2890 * XXX assumes 2 anntenae
2892 if (!sc->sc_diversity && (!sc->sc_stagbeacons || slot == 0)) {
2893 otherant = sc->sc_defant & 1 ? 2 : 1;
2894 if (sc->sc_ant_tx[otherant] > sc->sc_ant_tx[sc->sc_defant] + 2)
2895 ath_setdefantenna(sc, otherant);
2896 sc->sc_ant_tx[1] = sc->sc_ant_tx[2] = 0;
2901 * Stop any current dma and put the new frame on the queue.
2902 * This should never fail since we check above that no frames
2903 * are still pending on the queue.
2905 if (!ath_hal_stoptxdma(ah, sc->sc_bhalq)) {
2906 DPRINTF(sc, ATH_DEBUG_ANY,
2907 "%s: beacon queue %u did not stop?\n",
2908 __func__, sc->sc_bhalq);
2910 /* NB: cabq traffic should already be queued and primed */
2911 ath_hal_puttxbuf(ah, sc->sc_bhalq, bfaddr);
2912 ath_hal_txstart(ah, sc->sc_bhalq);
2914 sc->sc_stats.ast_be_xmit++;
2918 static struct ath_buf *
2919 ath_beacon_generate(struct ath_softc *sc, struct ieee80211vap *vap)
2921 struct ath_vap *avp = ATH_VAP(vap);
2922 struct ath_txq *cabq = sc->sc_cabq;
2927 KASSERT(vap->iv_state >= IEEE80211_S_RUN,
2928 ("not running, state %d", vap->iv_state));
2929 KASSERT(avp->av_bcbuf != NULL, ("no beacon buffer"));
2932 * Update dynamic beacon contents. If this returns
2933 * non-zero then we need to remap the memory because
2934 * the beacon frame changed size (probably because
2935 * of the TIM bitmap).
2939 nmcastq = avp->av_mcastq.axq_depth;
2940 if (ieee80211_beacon_update(bf->bf_node, &avp->av_boff, m, nmcastq)) {
2941 /* XXX too conservative? */
2942 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap);
2943 error = bus_dmamap_load_mbuf_sg(sc->sc_dmat, bf->bf_dmamap, m,
2944 bf->bf_segs, &bf->bf_nseg,
2947 if_printf(vap->iv_ifp,
2948 "%s: bus_dmamap_load_mbuf_sg failed, error %u\n",
2953 if ((avp->av_boff.bo_tim[4] & 1) && cabq->axq_depth) {
2954 DPRINTF(sc, ATH_DEBUG_BEACON,
2955 "%s: cabq did not drain, mcastq %u cabq %u\n",
2956 __func__, nmcastq, cabq->axq_depth);
2957 sc->sc_stats.ast_cabq_busy++;
2958 if (sc->sc_nvaps > 1 && sc->sc_stagbeacons) {
2960 * CABQ traffic from a previous vap is still pending.
2961 * We must drain the q before this beacon frame goes
2962 * out as otherwise this vap's stations will get cab
2963 * frames from a different vap.
2964 * XXX could be slow causing us to miss DBA
2966 ath_tx_draintxq(sc, cabq);
2969 ath_beacon_setup(sc, bf);
2970 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_PREWRITE);
2973 * Enable the CAB queue before the beacon queue to
2974 * insure cab frames are triggered by this beacon.
2976 if (avp->av_boff.bo_tim[4] & 1) {
2977 struct ath_hal *ah = sc->sc_ah;
2979 /* NB: only at DTIM */
2981 ATH_TXQ_LOCK(&avp->av_mcastq);
2983 struct ath_buf *bfm;
2986 * Move frames from the s/w mcast q to the h/w cab q.
2989 bfm = STAILQ_FIRST(&avp->av_mcastq.axq_q);
2990 if (cabq->axq_link != NULL) {
2991 *cabq->axq_link = bfm->bf_daddr;
2993 ath_hal_puttxbuf(ah, cabq->axq_qnum,
2995 ath_txqmove(cabq, &avp->av_mcastq);
2997 sc->sc_stats.ast_cabq_xmit += nmcastq;
2999 /* NB: gated by beacon so safe to start here */
3000 ath_hal_txstart(ah, cabq->axq_qnum);
3001 ATH_TXQ_UNLOCK(cabq);
3002 ATH_TXQ_UNLOCK(&avp->av_mcastq);
3008 ath_beacon_start_adhoc(struct ath_softc *sc, struct ieee80211vap *vap)
3010 struct ath_vap *avp = ATH_VAP(vap);
3011 struct ath_hal *ah = sc->sc_ah;
3016 KASSERT(avp->av_bcbuf != NULL, ("no beacon buffer"));
3019 * Update dynamic beacon contents. If this returns
3020 * non-zero then we need to remap the memory because
3021 * the beacon frame changed size (probably because
3022 * of the TIM bitmap).
3026 if (ieee80211_beacon_update(bf->bf_node, &avp->av_boff, m, 0)) {
3027 /* XXX too conservative? */
3028 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap);
3029 error = bus_dmamap_load_mbuf_sg(sc->sc_dmat, bf->bf_dmamap, m,
3030 bf->bf_segs, &bf->bf_nseg,
3033 if_printf(vap->iv_ifp,
3034 "%s: bus_dmamap_load_mbuf_sg failed, error %u\n",
3039 ath_beacon_setup(sc, bf);
3040 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_PREWRITE);
3042 /* NB: caller is known to have already stopped tx dma */
3043 ath_hal_puttxbuf(ah, sc->sc_bhalq, bf->bf_daddr);
3044 ath_hal_txstart(ah, sc->sc_bhalq);
3048 * Reset the hardware after detecting beacons have stopped.
3051 ath_bstuck_proc(void *arg, int pending)
3053 struct ath_softc *sc = arg;
3054 struct ifnet *ifp = sc->sc_ifp;
3056 if_printf(ifp, "stuck beacon; resetting (bmiss count %u)\n",
3058 sc->sc_stats.ast_bstuck++;
3063 * Reclaim beacon resources and return buffer to the pool.
3066 ath_beacon_return(struct ath_softc *sc, struct ath_buf *bf)
3069 if (bf->bf_m != NULL) {
3070 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap);
3074 if (bf->bf_node != NULL) {
3075 ieee80211_free_node(bf->bf_node);
3078 STAILQ_INSERT_TAIL(&sc->sc_bbuf, bf, bf_list);
3082 * Reclaim beacon resources.
3085 ath_beacon_free(struct ath_softc *sc)
3089 STAILQ_FOREACH(bf, &sc->sc_bbuf, bf_list) {
3090 if (bf->bf_m != NULL) {
3091 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap);
3095 if (bf->bf_node != NULL) {
3096 ieee80211_free_node(bf->bf_node);
3103 * Configure the beacon and sleep timers.
3105 * When operating as an AP this resets the TSF and sets
3106 * up the hardware to notify us when we need to issue beacons.
3108 * When operating in station mode this sets up the beacon
3109 * timers according to the timestamp of the last received
3110 * beacon and the current TSF, configures PCF and DTIM
3111 * handling, programs the sleep registers so the hardware
3112 * will wakeup in time to receive beacons, and configures
3113 * the beacon miss handling so we'll receive a BMISS
3114 * interrupt when we stop seeing beacons from the AP
3115 * we've associated with.
3118 ath_beacon_config(struct ath_softc *sc, struct ieee80211vap *vap)
3120 #define TSF_TO_TU(_h,_l) \
3121 ((((u_int32_t)(_h)) << 22) | (((u_int32_t)(_l)) >> 10))
3123 struct ath_hal *ah = sc->sc_ah;
3124 struct ieee80211com *ic = sc->sc_ifp->if_l2com;
3125 struct ieee80211_node *ni;
3126 u_int32_t nexttbtt, intval, tsftu;
3130 vap = TAILQ_FIRST(&ic->ic_vaps); /* XXX */
3133 /* extract tstamp from last beacon and convert to TU */
3134 nexttbtt = TSF_TO_TU(LE_READ_4(ni->ni_tstamp.data + 4),
3135 LE_READ_4(ni->ni_tstamp.data));
3136 if (ic->ic_opmode == IEEE80211_M_HOSTAP ||
3137 ic->ic_opmode == IEEE80211_M_MBSS) {
3139 * For multi-bss ap/mesh support beacons are either staggered
3140 * evenly over N slots or burst together. For the former
3141 * arrange for the SWBA to be delivered for each slot.
3142 * Slots that are not occupied will generate nothing.
3144 /* NB: the beacon interval is kept internally in TU's */
3145 intval = ni->ni_intval & HAL_BEACON_PERIOD;
3146 if (sc->sc_stagbeacons)
3147 intval /= ATH_BCBUF;
3149 /* NB: the beacon interval is kept internally in TU's */
3150 intval = ni->ni_intval & HAL_BEACON_PERIOD;
3152 if (nexttbtt == 0) /* e.g. for ap mode */
3154 else if (intval) /* NB: can be 0 for monitor mode */
3155 nexttbtt = roundup(nexttbtt, intval);
3156 DPRINTF(sc, ATH_DEBUG_BEACON, "%s: nexttbtt %u intval %u (%u)\n",
3157 __func__, nexttbtt, intval, ni->ni_intval);
3158 if (ic->ic_opmode == IEEE80211_M_STA && !sc->sc_swbmiss) {
3159 HAL_BEACON_STATE bs;
3160 int dtimperiod, dtimcount;
3161 int cfpperiod, cfpcount;
3164 * Setup dtim and cfp parameters according to
3165 * last beacon we received (which may be none).
3167 dtimperiod = ni->ni_dtim_period;
3168 if (dtimperiod <= 0) /* NB: 0 if not known */
3170 dtimcount = ni->ni_dtim_count;
3171 if (dtimcount >= dtimperiod) /* NB: sanity check */
3172 dtimcount = 0; /* XXX? */
3173 cfpperiod = 1; /* NB: no PCF support yet */
3176 * Pull nexttbtt forward to reflect the current
3177 * TSF and calculate dtim+cfp state for the result.
3179 tsf = ath_hal_gettsf64(ah);
3180 tsftu = TSF_TO_TU(tsf>>32, tsf) + FUDGE;
3183 if (--dtimcount < 0) {
3184 dtimcount = dtimperiod - 1;
3186 cfpcount = cfpperiod - 1;
3188 } while (nexttbtt < tsftu);
3189 memset(&bs, 0, sizeof(bs));
3190 bs.bs_intval = intval;
3191 bs.bs_nexttbtt = nexttbtt;
3192 bs.bs_dtimperiod = dtimperiod*intval;
3193 bs.bs_nextdtim = bs.bs_nexttbtt + dtimcount*intval;
3194 bs.bs_cfpperiod = cfpperiod*bs.bs_dtimperiod;
3195 bs.bs_cfpnext = bs.bs_nextdtim + cfpcount*bs.bs_dtimperiod;
3196 bs.bs_cfpmaxduration = 0;
3199 * The 802.11 layer records the offset to the DTIM
3200 * bitmap while receiving beacons; use it here to
3201 * enable h/w detection of our AID being marked in
3202 * the bitmap vector (to indicate frames for us are
3203 * pending at the AP).
3204 * XXX do DTIM handling in s/w to WAR old h/w bugs
3205 * XXX enable based on h/w rev for newer chips
3207 bs.bs_timoffset = ni->ni_timoff;
3210 * Calculate the number of consecutive beacons to miss
3211 * before taking a BMISS interrupt.
3212 * Note that we clamp the result to at most 10 beacons.
3214 bs.bs_bmissthreshold = vap->iv_bmissthreshold;
3215 if (bs.bs_bmissthreshold > 10)
3216 bs.bs_bmissthreshold = 10;
3217 else if (bs.bs_bmissthreshold <= 0)
3218 bs.bs_bmissthreshold = 1;
3221 * Calculate sleep duration. The configuration is
3222 * given in ms. We insure a multiple of the beacon
3223 * period is used. Also, if the sleep duration is
3224 * greater than the DTIM period then it makes senses
3225 * to make it a multiple of that.
3227 * XXX fixed at 100ms
3229 bs.bs_sleepduration =
3230 roundup(IEEE80211_MS_TO_TU(100), bs.bs_intval);
3231 if (bs.bs_sleepduration > bs.bs_dtimperiod)
3232 bs.bs_sleepduration = roundup(bs.bs_sleepduration, bs.bs_dtimperiod);
3234 DPRINTF(sc, ATH_DEBUG_BEACON,
3235 "%s: tsf %ju tsf:tu %u intval %u nexttbtt %u dtim %u nextdtim %u bmiss %u sleep %u cfp:period %u maxdur %u next %u timoffset %u\n"
3242 , bs.bs_bmissthreshold
3243 , bs.bs_sleepduration
3245 , bs.bs_cfpmaxduration
3249 ath_hal_intrset(ah, 0);
3250 ath_hal_beacontimers(ah, &bs);
3251 sc->sc_imask |= HAL_INT_BMISS;
3252 ath_hal_intrset(ah, sc->sc_imask);
3254 ath_hal_intrset(ah, 0);
3255 if (nexttbtt == intval)
3256 intval |= HAL_BEACON_RESET_TSF;
3257 if (ic->ic_opmode == IEEE80211_M_IBSS) {
3259 * In IBSS mode enable the beacon timers but only
3260 * enable SWBA interrupts if we need to manually
3261 * prepare beacon frames. Otherwise we use a
3262 * self-linked tx descriptor and let the hardware
3265 intval |= HAL_BEACON_ENA;
3266 if (!sc->sc_hasveol)
3267 sc->sc_imask |= HAL_INT_SWBA;
3268 if ((intval & HAL_BEACON_RESET_TSF) == 0) {
3270 * Pull nexttbtt forward to reflect
3273 tsf = ath_hal_gettsf64(ah);
3274 tsftu = TSF_TO_TU(tsf>>32, tsf) + FUDGE;
3277 } while (nexttbtt < tsftu);
3279 ath_beaconq_config(sc);
3280 } else if (ic->ic_opmode == IEEE80211_M_HOSTAP ||
3281 ic->ic_opmode == IEEE80211_M_MBSS) {
3283 * In AP/mesh mode we enable the beacon timers
3284 * and SWBA interrupts to prepare beacon frames.
3286 intval |= HAL_BEACON_ENA;
3287 sc->sc_imask |= HAL_INT_SWBA; /* beacon prepare */
3288 ath_beaconq_config(sc);
3290 ath_hal_beaconinit(ah, nexttbtt, intval);
3291 sc->sc_bmisscount = 0;
3292 ath_hal_intrset(ah, sc->sc_imask);
3294 * When using a self-linked beacon descriptor in
3295 * ibss mode load it once here.
3297 if (ic->ic_opmode == IEEE80211_M_IBSS && sc->sc_hasveol)
3298 ath_beacon_start_adhoc(sc, vap);
3300 sc->sc_syncbeacon = 0;
3306 ath_load_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
3308 bus_addr_t *paddr = (bus_addr_t*) arg;
3309 KASSERT(error == 0, ("error %u on bus_dma callback", error));
3310 *paddr = segs->ds_addr;
3314 ath_descdma_setup(struct ath_softc *sc,
3315 struct ath_descdma *dd, ath_bufhead *head,
3316 const char *name, int nbuf, int ndesc)
3318 #define DS2PHYS(_dd, _ds) \
3319 ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
3320 struct ifnet *ifp = sc->sc_ifp;
3321 struct ath_desc *ds;
3323 int i, bsize, error;
3325 DPRINTF(sc, ATH_DEBUG_RESET, "%s: %s DMA: %u buffers %u desc/buf\n",
3326 __func__, name, nbuf, ndesc);
3329 dd->dd_desc_len = sizeof(struct ath_desc) * nbuf * ndesc;
3332 * Setup DMA descriptor area.
3334 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), /* parent */
3335 PAGE_SIZE, 0, /* alignment, bounds */
3336 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
3337 BUS_SPACE_MAXADDR, /* highaddr */
3338 NULL, NULL, /* filter, filterarg */
3339 dd->dd_desc_len, /* maxsize */
3341 dd->dd_desc_len, /* maxsegsize */
3342 BUS_DMA_ALLOCNOW, /* flags */
3343 NULL, /* lockfunc */
3347 if_printf(ifp, "cannot allocate %s DMA tag\n", dd->dd_name);
3351 /* allocate descriptors */
3352 error = bus_dmamap_create(dd->dd_dmat, BUS_DMA_NOWAIT, &dd->dd_dmamap);
3354 if_printf(ifp, "unable to create dmamap for %s descriptors, "
3355 "error %u\n", dd->dd_name, error);
3359 error = bus_dmamem_alloc(dd->dd_dmat, (void**) &dd->dd_desc,
3360 BUS_DMA_NOWAIT | BUS_DMA_COHERENT,
3363 if_printf(ifp, "unable to alloc memory for %u %s descriptors, "
3364 "error %u\n", nbuf * ndesc, dd->dd_name, error);
3368 error = bus_dmamap_load(dd->dd_dmat, dd->dd_dmamap,
3369 dd->dd_desc, dd->dd_desc_len,
3370 ath_load_cb, &dd->dd_desc_paddr,
3373 if_printf(ifp, "unable to map %s descriptors, error %u\n",
3374 dd->dd_name, error);
3379 DPRINTF(sc, ATH_DEBUG_RESET, "%s: %s DMA map: %p (%lu) -> %p (%lu)\n",
3380 __func__, dd->dd_name, ds, (u_long) dd->dd_desc_len,
3381 (caddr_t) dd->dd_desc_paddr, /*XXX*/ (u_long) dd->dd_desc_len);
3383 /* allocate rx buffers */
3384 bsize = sizeof(struct ath_buf) * nbuf;
3385 bf = malloc(bsize, M_ATHDEV, M_NOWAIT | M_ZERO);
3387 if_printf(ifp, "malloc of %s buffers failed, size %u\n",
3388 dd->dd_name, bsize);
3394 for (i = 0; i < nbuf; i++, bf++, ds += ndesc) {
3396 bf->bf_daddr = DS2PHYS(dd, ds);
3397 error = bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT,
3400 if_printf(ifp, "unable to create dmamap for %s "
3401 "buffer %u, error %u\n", dd->dd_name, i, error);
3402 ath_descdma_cleanup(sc, dd, head);
3405 STAILQ_INSERT_TAIL(head, bf, bf_list);
3409 bus_dmamap_unload(dd->dd_dmat, dd->dd_dmamap);
3411 bus_dmamem_free(dd->dd_dmat, dd->dd_desc, dd->dd_dmamap);
3413 bus_dmamap_destroy(dd->dd_dmat, dd->dd_dmamap);
3415 bus_dma_tag_destroy(dd->dd_dmat);
3416 memset(dd, 0, sizeof(*dd));
3422 ath_descdma_cleanup(struct ath_softc *sc,
3423 struct ath_descdma *dd, ath_bufhead *head)
3426 struct ieee80211_node *ni;
3428 bus_dmamap_unload(dd->dd_dmat, dd->dd_dmamap);
3429 bus_dmamem_free(dd->dd_dmat, dd->dd_desc, dd->dd_dmamap);
3430 bus_dmamap_destroy(dd->dd_dmat, dd->dd_dmamap);
3431 bus_dma_tag_destroy(dd->dd_dmat);
3433 STAILQ_FOREACH(bf, head, bf_list) {
3438 if (bf->bf_dmamap != NULL) {
3439 bus_dmamap_destroy(sc->sc_dmat, bf->bf_dmamap);
3440 bf->bf_dmamap = NULL;
3446 * Reclaim node reference.
3448 ieee80211_free_node(ni);
3453 free(dd->dd_bufptr, M_ATHDEV);
3454 memset(dd, 0, sizeof(*dd));
3458 ath_desc_alloc(struct ath_softc *sc)
3462 error = ath_descdma_setup(sc, &sc->sc_rxdma, &sc->sc_rxbuf,
3463 "rx", ath_rxbuf, 1);
3467 error = ath_descdma_setup(sc, &sc->sc_txdma, &sc->sc_txbuf,
3468 "tx", ath_txbuf, ATH_TXDESC);
3470 ath_descdma_cleanup(sc, &sc->sc_rxdma, &sc->sc_rxbuf);
3474 error = ath_descdma_setup(sc, &sc->sc_bdma, &sc->sc_bbuf,
3475 "beacon", ATH_BCBUF, 1);
3477 ath_descdma_cleanup(sc, &sc->sc_txdma, &sc->sc_txbuf);
3478 ath_descdma_cleanup(sc, &sc->sc_rxdma, &sc->sc_rxbuf);
3485 ath_desc_free(struct ath_softc *sc)
3488 if (sc->sc_bdma.dd_desc_len != 0)
3489 ath_descdma_cleanup(sc, &sc->sc_bdma, &sc->sc_bbuf);
3490 if (sc->sc_txdma.dd_desc_len != 0)
3491 ath_descdma_cleanup(sc, &sc->sc_txdma, &sc->sc_txbuf);
3492 if (sc->sc_rxdma.dd_desc_len != 0)
3493 ath_descdma_cleanup(sc, &sc->sc_rxdma, &sc->sc_rxbuf);
3496 static struct ieee80211_node *
3497 ath_node_alloc(struct ieee80211vap *vap, const uint8_t mac[IEEE80211_ADDR_LEN])
3499 struct ieee80211com *ic = vap->iv_ic;
3500 struct ath_softc *sc = ic->ic_ifp->if_softc;
3501 const size_t space = sizeof(struct ath_node) + sc->sc_rc->arc_space;
3502 struct ath_node *an;
3504 an = malloc(space, M_80211_NODE, M_NOWAIT|M_ZERO);
3509 ath_rate_node_init(sc, an);
3511 DPRINTF(sc, ATH_DEBUG_NODE, "%s: an %p\n", __func__, an);
3512 return &an->an_node;
3516 ath_node_free(struct ieee80211_node *ni)
3518 struct ieee80211com *ic = ni->ni_ic;
3519 struct ath_softc *sc = ic->ic_ifp->if_softc;
3521 DPRINTF(sc, ATH_DEBUG_NODE, "%s: ni %p\n", __func__, ni);
3523 ath_rate_node_cleanup(sc, ATH_NODE(ni));
3524 sc->sc_node_free(ni);
3528 ath_node_getsignal(const struct ieee80211_node *ni, int8_t *rssi, int8_t *noise)
3530 struct ieee80211com *ic = ni->ni_ic;
3531 struct ath_softc *sc = ic->ic_ifp->if_softc;
3532 struct ath_hal *ah = sc->sc_ah;
3534 *rssi = ic->ic_node_getrssi(ni);
3535 if (ni->ni_chan != IEEE80211_CHAN_ANYC)
3536 *noise = ath_hal_getchannoise(ah, ni->ni_chan);
3538 *noise = -95; /* nominally correct */
3542 ath_rxbuf_init(struct ath_softc *sc, struct ath_buf *bf)
3544 struct ath_hal *ah = sc->sc_ah;
3547 struct ath_desc *ds;
3552 * NB: by assigning a page to the rx dma buffer we
3553 * implicitly satisfy the Atheros requirement that
3554 * this buffer be cache-line-aligned and sized to be
3555 * multiple of the cache line size. Not doing this
3556 * causes weird stuff to happen (for the 5210 at least).
3558 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
3560 DPRINTF(sc, ATH_DEBUG_ANY,
3561 "%s: no mbuf/cluster\n", __func__);
3562 sc->sc_stats.ast_rx_nombuf++;
3565 m->m_pkthdr.len = m->m_len = m->m_ext.ext_size;
3567 error = bus_dmamap_load_mbuf_sg(sc->sc_dmat,
3569 bf->bf_segs, &bf->bf_nseg,
3572 DPRINTF(sc, ATH_DEBUG_ANY,
3573 "%s: bus_dmamap_load_mbuf_sg failed; error %d\n",
3575 sc->sc_stats.ast_rx_busdma++;
3579 KASSERT(bf->bf_nseg == 1,
3580 ("multi-segment packet; nseg %u", bf->bf_nseg));
3583 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_PREREAD);
3586 * Setup descriptors. For receive we always terminate
3587 * the descriptor list with a self-linked entry so we'll
3588 * not get overrun under high load (as can happen with a
3589 * 5212 when ANI processing enables PHY error frames).
3591 * To insure the last descriptor is self-linked we create
3592 * each descriptor as self-linked and add it to the end. As
3593 * each additional descriptor is added the previous self-linked
3594 * entry is ``fixed'' naturally. This should be safe even
3595 * if DMA is happening. When processing RX interrupts we
3596 * never remove/process the last, self-linked, entry on the
3597 * descriptor list. This insures the hardware always has
3598 * someplace to write a new frame.
3601 ds->ds_link = bf->bf_daddr; /* link to self */
3602 ds->ds_data = bf->bf_segs[0].ds_addr;
3603 ath_hal_setuprxdesc(ah, ds
3604 , m->m_len /* buffer size */
3608 if (sc->sc_rxlink != NULL)
3609 *sc->sc_rxlink = bf->bf_daddr;
3610 sc->sc_rxlink = &ds->ds_link;
3615 * Extend 15-bit time stamp from rx descriptor to
3616 * a full 64-bit TSF using the specified TSF.
3618 static __inline u_int64_t
3619 ath_extend_tsf(u_int32_t rstamp, u_int64_t tsf)
3621 if ((tsf & 0x7fff) < rstamp)
3623 return ((tsf &~ 0x7fff) | rstamp);
3627 * Intercept management frames to collect beacon rssi data
3628 * and to do ibss merges.
3631 ath_recv_mgmt(struct ieee80211_node *ni, struct mbuf *m,
3632 int subtype, int rssi, int nf)
3634 struct ieee80211vap *vap = ni->ni_vap;
3635 struct ath_softc *sc = vap->iv_ic->ic_ifp->if_softc;
3638 * Call up first so subsequent work can use information
3639 * potentially stored in the node (e.g. for ibss merge).
3641 ATH_VAP(vap)->av_recv_mgmt(ni, m, subtype, rssi, nf);
3643 case IEEE80211_FC0_SUBTYPE_BEACON:
3644 /* update rssi statistics for use by the hal */
3645 ATH_RSSI_LPF(sc->sc_halstats.ns_avgbrssi, rssi);
3646 if (sc->sc_syncbeacon &&
3647 ni == vap->iv_bss && vap->iv_state == IEEE80211_S_RUN) {
3649 * Resync beacon timers using the tsf of the beacon
3650 * frame we just received.
3652 ath_beacon_config(sc, vap);
3655 case IEEE80211_FC0_SUBTYPE_PROBE_RESP:
3656 if (vap->iv_opmode == IEEE80211_M_IBSS &&
3657 vap->iv_state == IEEE80211_S_RUN) {
3658 uint32_t rstamp = sc->sc_lastrs->rs_tstamp;
3659 u_int64_t tsf = ath_extend_tsf(rstamp,
3660 ath_hal_gettsf64(sc->sc_ah));
3662 * Handle ibss merge as needed; check the tsf on the
3663 * frame before attempting the merge. The 802.11 spec
3664 * says the station should change it's bssid to match
3665 * the oldest station with the same ssid, where oldest
3666 * is determined by the tsf. Note that hardware
3667 * reconfiguration happens through callback to
3668 * ath_newstate as the state machine will go from
3669 * RUN -> RUN when this happens.
3671 if (le64toh(ni->ni_tstamp.tsf) >= tsf) {
3672 DPRINTF(sc, ATH_DEBUG_STATE,
3673 "ibss merge, rstamp %u tsf %ju "
3674 "tstamp %ju\n", rstamp, (uintmax_t)tsf,
3675 (uintmax_t)ni->ni_tstamp.tsf);
3676 (void) ieee80211_ibss_merge(ni);
3684 * Set the default antenna.
3687 ath_setdefantenna(struct ath_softc *sc, u_int antenna)
3689 struct ath_hal *ah = sc->sc_ah;
3691 /* XXX block beacon interrupts */
3692 ath_hal_setdefantenna(ah, antenna);
3693 if (sc->sc_defant != antenna)
3694 sc->sc_stats.ast_ant_defswitch++;
3695 sc->sc_defant = antenna;
3696 sc->sc_rxotherant = 0;
3700 ath_rx_tap(struct ifnet *ifp, struct mbuf *m,
3701 const struct ath_rx_status *rs, u_int64_t tsf, int16_t nf)
3703 #define CHAN_HT20 htole32(IEEE80211_CHAN_HT20)
3704 #define CHAN_HT40U htole32(IEEE80211_CHAN_HT40U)
3705 #define CHAN_HT40D htole32(IEEE80211_CHAN_HT40D)
3706 #define CHAN_HT (CHAN_HT20|CHAN_HT40U|CHAN_HT40D)
3707 struct ath_softc *sc = ifp->if_softc;
3708 const HAL_RATE_TABLE *rt;
3711 rt = sc->sc_currates;
3712 KASSERT(rt != NULL, ("no rate table, mode %u", sc->sc_curmode));
3713 rix = rt->rateCodeToIndex[rs->rs_rate];
3714 sc->sc_rx_th.wr_rate = sc->sc_hwmap[rix].ieeerate;
3715 sc->sc_rx_th.wr_flags = sc->sc_hwmap[rix].rxflags;
3716 #ifdef AH_SUPPORT_AR5416
3717 sc->sc_rx_th.wr_chan_flags &= ~CHAN_HT;
3718 if (sc->sc_rx_th.wr_rate & IEEE80211_RATE_MCS) { /* HT rate */
3719 struct ieee80211com *ic = ifp->if_l2com;
3721 if ((rs->rs_flags & HAL_RX_2040) == 0)
3722 sc->sc_rx_th.wr_chan_flags |= CHAN_HT20;
3723 else if (IEEE80211_IS_CHAN_HT40U(ic->ic_curchan))
3724 sc->sc_rx_th.wr_chan_flags |= CHAN_HT40U;
3726 sc->sc_rx_th.wr_chan_flags |= CHAN_HT40D;
3727 if ((rs->rs_flags & HAL_RX_GI) == 0)
3728 sc->sc_rx_th.wr_flags |= IEEE80211_RADIOTAP_F_SHORTGI;
3731 sc->sc_rx_th.wr_tsf = htole64(ath_extend_tsf(rs->rs_tstamp, tsf));
3732 if (rs->rs_status & HAL_RXERR_CRC)
3733 sc->sc_rx_th.wr_flags |= IEEE80211_RADIOTAP_F_BADFCS;
3734 /* XXX propagate other error flags from descriptor */
3735 sc->sc_rx_th.wr_antnoise = nf;
3736 sc->sc_rx_th.wr_antsignal = nf + rs->rs_rssi;
3737 sc->sc_rx_th.wr_antenna = rs->rs_antenna;
3745 ath_handle_micerror(struct ieee80211com *ic,
3746 struct ieee80211_frame *wh, int keyix)
3748 struct ieee80211_node *ni;
3750 /* XXX recheck MIC to deal w/ chips that lie */
3751 /* XXX discard MIC errors on !data frames */
3752 ni = ieee80211_find_rxnode(ic, (const struct ieee80211_frame_min *) wh);
3754 ieee80211_notify_michael_failure(ni->ni_vap, wh, keyix);
3755 ieee80211_free_node(ni);
3760 ath_rx_proc(void *arg, int npending)
3762 #define PA2DESC(_sc, _pa) \
3763 ((struct ath_desc *)((caddr_t)(_sc)->sc_rxdma.dd_desc + \
3764 ((_pa) - (_sc)->sc_rxdma.dd_desc_paddr)))
3765 struct ath_softc *sc = arg;
3767 struct ifnet *ifp = sc->sc_ifp;
3768 struct ieee80211com *ic = ifp->if_l2com;
3769 struct ath_hal *ah = sc->sc_ah;
3770 struct ath_desc *ds;
3771 struct ath_rx_status *rs;
3773 struct ieee80211_node *ni;
3774 int len, type, ngood;
3780 DPRINTF(sc, ATH_DEBUG_RX_PROC, "%s: pending %u\n", __func__, npending);
3782 nf = ath_hal_getchannoise(ah, sc->sc_curchan);
3783 sc->sc_stats.ast_rx_noise = nf;
3784 tsf = ath_hal_gettsf64(ah);
3786 bf = STAILQ_FIRST(&sc->sc_rxbuf);
3787 if (bf == NULL) { /* NB: shouldn't happen */
3788 if_printf(ifp, "%s: no buffer!\n", __func__);
3792 if (m == NULL) { /* NB: shouldn't happen */
3794 * If mbuf allocation failed previously there
3795 * will be no mbuf; try again to re-populate it.
3797 /* XXX make debug msg */
3798 if_printf(ifp, "%s: no mbuf!\n", __func__);
3799 STAILQ_REMOVE_HEAD(&sc->sc_rxbuf, bf_list);
3803 if (ds->ds_link == bf->bf_daddr) {
3804 /* NB: never process the self-linked entry at the end */
3807 /* XXX sync descriptor memory */
3809 * Must provide the virtual address of the current
3810 * descriptor, the physical address, and the virtual
3811 * address of the next descriptor in the h/w chain.
3812 * This allows the HAL to look ahead to see if the
3813 * hardware is done with a descriptor by checking the
3814 * done bit in the following descriptor and the address
3815 * of the current descriptor the DMA engine is working
3816 * on. All this is necessary because of our use of
3817 * a self-linked list to avoid rx overruns.
3819 rs = &bf->bf_status.ds_rxstat;
3820 status = ath_hal_rxprocdesc(ah, ds,
3821 bf->bf_daddr, PA2DESC(sc, ds->ds_link), rs);
3823 if (sc->sc_debug & ATH_DEBUG_RECV_DESC)
3824 ath_printrxbuf(sc, bf, 0, status == HAL_OK);
3826 if (status == HAL_EINPROGRESS)
3828 STAILQ_REMOVE_HEAD(&sc->sc_rxbuf, bf_list);
3829 if (rs->rs_status != 0) {
3830 if (rs->rs_status & HAL_RXERR_CRC)
3831 sc->sc_stats.ast_rx_crcerr++;
3832 if (rs->rs_status & HAL_RXERR_FIFO)
3833 sc->sc_stats.ast_rx_fifoerr++;
3834 if (rs->rs_status & HAL_RXERR_PHY) {
3835 sc->sc_stats.ast_rx_phyerr++;
3836 phyerr = rs->rs_phyerr & 0x1f;
3837 sc->sc_stats.ast_rx_phy[phyerr]++;
3838 goto rx_error; /* NB: don't count in ierrors */
3840 if (rs->rs_status & HAL_RXERR_DECRYPT) {
3842 * Decrypt error. If the error occurred
3843 * because there was no hardware key, then
3844 * let the frame through so the upper layers
3845 * can process it. This is necessary for 5210
3846 * parts which have no way to setup a ``clear''
3849 * XXX do key cache faulting
3851 if (rs->rs_keyix == HAL_RXKEYIX_INVALID)
3853 sc->sc_stats.ast_rx_badcrypt++;
3855 if (rs->rs_status & HAL_RXERR_MIC) {
3856 sc->sc_stats.ast_rx_badmic++;
3858 * Do minimal work required to hand off
3859 * the 802.11 header for notification.
3861 /* XXX frag's and qos frames */
3862 len = rs->rs_datalen;
3863 if (len >= sizeof (struct ieee80211_frame)) {
3864 bus_dmamap_sync(sc->sc_dmat,
3866 BUS_DMASYNC_POSTREAD);
3867 ath_handle_micerror(ic,
3868 mtod(m, struct ieee80211_frame *),
3870 rs->rs_keyix-32 : rs->rs_keyix);
3876 * Cleanup any pending partial frame.
3878 if (sc->sc_rxpending != NULL) {
3879 m_freem(sc->sc_rxpending);
3880 sc->sc_rxpending = NULL;
3883 * When a tap is present pass error frames
3884 * that have been requested. By default we
3885 * pass decrypt+mic errors but others may be
3886 * interesting (e.g. crc).
3888 if (ieee80211_radiotap_active(ic) &&
3889 (rs->rs_status & sc->sc_monpass)) {
3890 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap,
3891 BUS_DMASYNC_POSTREAD);
3892 /* NB: bpf needs the mbuf length setup */
3893 len = rs->rs_datalen;
3894 m->m_pkthdr.len = m->m_len = len;
3895 ath_rx_tap(ifp, m, rs, tsf, nf);
3896 ieee80211_radiotap_rx_all(ic, m);
3898 /* XXX pass MIC errors up for s/w reclaculation */
3903 * Sync and unmap the frame. At this point we're
3904 * committed to passing the mbuf somewhere so clear
3905 * bf_m; this means a new mbuf must be allocated
3906 * when the rx descriptor is setup again to receive
3909 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap,
3910 BUS_DMASYNC_POSTREAD);
3911 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap);
3914 len = rs->rs_datalen;
3919 * Frame spans multiple descriptors; save
3920 * it for the next completed descriptor, it
3921 * will be used to construct a jumbogram.
3923 if (sc->sc_rxpending != NULL) {
3924 /* NB: max frame size is currently 2 clusters */
3925 sc->sc_stats.ast_rx_toobig++;
3926 m_freem(sc->sc_rxpending);
3928 m->m_pkthdr.rcvif = ifp;
3929 m->m_pkthdr.len = len;
3930 sc->sc_rxpending = m;
3932 } else if (sc->sc_rxpending != NULL) {
3934 * This is the second part of a jumbogram,
3935 * chain it to the first mbuf, adjust the
3936 * frame length, and clear the rxpending state.
3938 sc->sc_rxpending->m_next = m;
3939 sc->sc_rxpending->m_pkthdr.len += len;
3940 m = sc->sc_rxpending;
3941 sc->sc_rxpending = NULL;
3944 * Normal single-descriptor receive; setup
3945 * the rcvif and packet length.
3947 m->m_pkthdr.rcvif = ifp;
3948 m->m_pkthdr.len = len;
3952 sc->sc_stats.ast_ant_rx[rs->rs_antenna]++;
3955 * Populate the rx status block. When there are bpf
3956 * listeners we do the additional work to provide
3957 * complete status. Otherwise we fill in only the
3958 * material required by ieee80211_input. Note that
3959 * noise setting is filled in above.
3961 if (ieee80211_radiotap_active(ic))
3962 ath_rx_tap(ifp, m, rs, tsf, nf);
3965 * From this point on we assume the frame is at least
3966 * as large as ieee80211_frame_min; verify that.
3968 if (len < IEEE80211_MIN_LEN) {
3969 if (!ieee80211_radiotap_active(ic)) {
3970 DPRINTF(sc, ATH_DEBUG_RECV,
3971 "%s: short packet %d\n", __func__, len);
3972 sc->sc_stats.ast_rx_tooshort++;
3974 /* NB: in particular this captures ack's */
3975 ieee80211_radiotap_rx_all(ic, m);
3981 if (IFF_DUMPPKTS(sc, ATH_DEBUG_RECV)) {
3982 const HAL_RATE_TABLE *rt = sc->sc_currates;
3983 uint8_t rix = rt->rateCodeToIndex[rs->rs_rate];
3985 ieee80211_dump_pkt(ic, mtod(m, caddr_t), len,
3986 sc->sc_hwmap[rix].ieeerate, rs->rs_rssi);
3989 m_adj(m, -IEEE80211_CRC_LEN);
3992 * Locate the node for sender, track state, and then
3993 * pass the (referenced) node up to the 802.11 layer
3996 ni = ieee80211_find_rxnode_withkey(ic,
3997 mtod(m, const struct ieee80211_frame_min *),
3998 rs->rs_keyix == HAL_RXKEYIX_INVALID ?
3999 IEEE80211_KEYIX_NONE : rs->rs_keyix);
4002 * Sending station is known, dispatch directly.
4005 type = ieee80211_input(ni, m, rs->rs_rssi, nf);
4006 ieee80211_free_node(ni);
4008 * Arrange to update the last rx timestamp only for
4009 * frames from our ap when operating in station mode.
4010 * This assumes the rx key is always setup when
4013 if (ic->ic_opmode == IEEE80211_M_STA &&
4014 rs->rs_keyix != HAL_RXKEYIX_INVALID)
4017 type = ieee80211_input_all(ic, m, rs->rs_rssi, nf);
4020 * Track rx rssi and do any rx antenna management.
4022 ATH_RSSI_LPF(sc->sc_halstats.ns_avgrssi, rs->rs_rssi);
4023 if (sc->sc_diversity) {
4025 * When using fast diversity, change the default rx
4026 * antenna if diversity chooses the other antenna 3
4029 if (sc->sc_defant != rs->rs_antenna) {
4030 if (++sc->sc_rxotherant >= 3)
4031 ath_setdefantenna(sc, rs->rs_antenna);
4033 sc->sc_rxotherant = 0;
4035 if (sc->sc_softled) {
4037 * Blink for any data frame. Otherwise do a
4038 * heartbeat-style blink when idle. The latter
4039 * is mainly for station mode where we depend on
4040 * periodic beacon frames to trigger the poll event.
4042 if (type == IEEE80211_FC0_TYPE_DATA) {
4043 const HAL_RATE_TABLE *rt = sc->sc_currates;
4045 rt->rateCodeToIndex[rs->rs_rate]);
4046 } else if (ticks - sc->sc_ledevent >= sc->sc_ledidle)
4047 ath_led_event(sc, 0);
4050 STAILQ_INSERT_TAIL(&sc->sc_rxbuf, bf, bf_list);
4051 } while (ath_rxbuf_init(sc, bf) == 0);
4053 /* rx signal state monitoring */
4054 ath_hal_rxmonitor(ah, &sc->sc_halstats, sc->sc_curchan);
4056 sc->sc_lastrx = tsf;
4058 if ((ifp->if_drv_flags & IFF_DRV_OACTIVE) == 0) {
4059 #ifdef IEEE80211_SUPPORT_SUPERG
4060 ieee80211_ff_age_all(ic, 100);
4062 if (!IFQ_IS_EMPTY(&ifp->if_snd))
4069 ath_txq_init(struct ath_softc *sc, struct ath_txq *txq, int qnum)
4071 txq->axq_qnum = qnum;
4074 txq->axq_intrcnt = 0;
4075 txq->axq_link = NULL;
4076 STAILQ_INIT(&txq->axq_q);
4077 ATH_TXQ_LOCK_INIT(sc, txq);
4081 * Setup a h/w transmit queue.
4083 static struct ath_txq *
4084 ath_txq_setup(struct ath_softc *sc, int qtype, int subtype)
4086 #define N(a) (sizeof(a)/sizeof(a[0]))
4087 struct ath_hal *ah = sc->sc_ah;
4091 memset(&qi, 0, sizeof(qi));
4092 qi.tqi_subtype = subtype;
4093 qi.tqi_aifs = HAL_TXQ_USEDEFAULT;
4094 qi.tqi_cwmin = HAL_TXQ_USEDEFAULT;
4095 qi.tqi_cwmax = HAL_TXQ_USEDEFAULT;
4097 * Enable interrupts only for EOL and DESC conditions.
4098 * We mark tx descriptors to receive a DESC interrupt
4099 * when a tx queue gets deep; otherwise waiting for the
4100 * EOL to reap descriptors. Note that this is done to
4101 * reduce interrupt load and this only defers reaping
4102 * descriptors, never transmitting frames. Aside from
4103 * reducing interrupts this also permits more concurrency.
4104 * The only potential downside is if the tx queue backs
4105 * up in which case the top half of the kernel may backup
4106 * due to a lack of tx descriptors.
4108 qi.tqi_qflags = HAL_TXQ_TXEOLINT_ENABLE | HAL_TXQ_TXDESCINT_ENABLE;
4109 qnum = ath_hal_setuptxqueue(ah, qtype, &qi);
4112 * NB: don't print a message, this happens
4113 * normally on parts with too few tx queues
4117 if (qnum >= N(sc->sc_txq)) {
4118 device_printf(sc->sc_dev,
4119 "hal qnum %u out of range, max %zu!\n",
4120 qnum, N(sc->sc_txq));
4121 ath_hal_releasetxqueue(ah, qnum);
4124 if (!ATH_TXQ_SETUP(sc, qnum)) {
4125 ath_txq_init(sc, &sc->sc_txq[qnum], qnum);
4126 sc->sc_txqsetup |= 1<<qnum;
4128 return &sc->sc_txq[qnum];
4133 * Setup a hardware data transmit queue for the specified
4134 * access control. The hal may not support all requested
4135 * queues in which case it will return a reference to a
4136 * previously setup queue. We record the mapping from ac's
4137 * to h/w queues for use by ath_tx_start and also track
4138 * the set of h/w queues being used to optimize work in the
4139 * transmit interrupt handler and related routines.
4142 ath_tx_setup(struct ath_softc *sc, int ac, int haltype)
4144 #define N(a) (sizeof(a)/sizeof(a[0]))
4145 struct ath_txq *txq;
4147 if (ac >= N(sc->sc_ac2q)) {
4148 device_printf(sc->sc_dev, "AC %u out of range, max %zu!\n",
4149 ac, N(sc->sc_ac2q));
4152 txq = ath_txq_setup(sc, HAL_TX_QUEUE_DATA, haltype);
4155 sc->sc_ac2q[ac] = txq;
4163 * Update WME parameters for a transmit queue.
4166 ath_txq_update(struct ath_softc *sc, int ac)
4168 #define ATH_EXPONENT_TO_VALUE(v) ((1<<v)-1)
4169 #define ATH_TXOP_TO_US(v) (v<<5)
4170 struct ifnet *ifp = sc->sc_ifp;
4171 struct ieee80211com *ic = ifp->if_l2com;
4172 struct ath_txq *txq = sc->sc_ac2q[ac];
4173 struct wmeParams *wmep = &ic->ic_wme.wme_chanParams.cap_wmeParams[ac];
4174 struct ath_hal *ah = sc->sc_ah;
4177 ath_hal_gettxqueueprops(ah, txq->axq_qnum, &qi);
4178 #ifdef IEEE80211_SUPPORT_TDMA
4181 * AIFS is zero so there's no pre-transmit wait. The
4182 * burst time defines the slot duration and is configured
4183 * through net80211. The QCU is setup to not do post-xmit
4184 * back off, lockout all lower-priority QCU's, and fire
4185 * off the DMA beacon alert timer which is setup based
4186 * on the slot configuration.
4188 qi.tqi_qflags = HAL_TXQ_TXOKINT_ENABLE
4189 | HAL_TXQ_TXERRINT_ENABLE
4190 | HAL_TXQ_TXURNINT_ENABLE
4191 | HAL_TXQ_TXEOLINT_ENABLE
4193 | HAL_TXQ_BACKOFF_DISABLE
4194 | HAL_TXQ_ARB_LOCKOUT_GLOBAL
4198 qi.tqi_readyTime = sc->sc_tdmaslotlen;
4199 qi.tqi_burstTime = qi.tqi_readyTime;
4202 qi.tqi_qflags = HAL_TXQ_TXOKINT_ENABLE
4203 | HAL_TXQ_TXERRINT_ENABLE
4204 | HAL_TXQ_TXDESCINT_ENABLE
4205 | HAL_TXQ_TXURNINT_ENABLE
4207 qi.tqi_aifs = wmep->wmep_aifsn;
4208 qi.tqi_cwmin = ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmin);
4209 qi.tqi_cwmax = ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmax);
4210 qi.tqi_readyTime = 0;
4211 qi.tqi_burstTime = ATH_TXOP_TO_US(wmep->wmep_txopLimit);
4212 #ifdef IEEE80211_SUPPORT_TDMA
4216 DPRINTF(sc, ATH_DEBUG_RESET,
4217 "%s: Q%u qflags 0x%x aifs %u cwmin %u cwmax %u burstTime %u\n",
4218 __func__, txq->axq_qnum, qi.tqi_qflags,
4219 qi.tqi_aifs, qi.tqi_cwmin, qi.tqi_cwmax, qi.tqi_burstTime);
4221 if (!ath_hal_settxqueueprops(ah, txq->axq_qnum, &qi)) {
4222 if_printf(ifp, "unable to update hardware queue "
4223 "parameters for %s traffic!\n",
4224 ieee80211_wme_acnames[ac]);
4227 ath_hal_resettxqueue(ah, txq->axq_qnum); /* push to h/w */
4230 #undef ATH_TXOP_TO_US
4231 #undef ATH_EXPONENT_TO_VALUE
4235 * Callback from the 802.11 layer to update WME parameters.
4238 ath_wme_update(struct ieee80211com *ic)
4240 struct ath_softc *sc = ic->ic_ifp->if_softc;
4242 return !ath_txq_update(sc, WME_AC_BE) ||
4243 !ath_txq_update(sc, WME_AC_BK) ||
4244 !ath_txq_update(sc, WME_AC_VI) ||
4245 !ath_txq_update(sc, WME_AC_VO) ? EIO : 0;
4249 * Reclaim resources for a setup queue.
4252 ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq)
4255 ath_hal_releasetxqueue(sc->sc_ah, txq->axq_qnum);
4256 ATH_TXQ_LOCK_DESTROY(txq);
4257 sc->sc_txqsetup &= ~(1<<txq->axq_qnum);
4261 * Reclaim all tx queue resources.
4264 ath_tx_cleanup(struct ath_softc *sc)
4268 ATH_TXBUF_LOCK_DESTROY(sc);
4269 for (i = 0; i < HAL_NUM_TX_QUEUES; i++)
4270 if (ATH_TXQ_SETUP(sc, i))
4271 ath_tx_cleanupq(sc, &sc->sc_txq[i]);
4275 * Return h/w rate index for an IEEE rate (w/o basic rate bit)
4276 * using the current rates in sc_rixmap.
4279 ath_tx_findrix(const struct ath_softc *sc, uint8_t rate)
4281 int rix = sc->sc_rixmap[rate];
4282 /* NB: return lowest rix for invalid rate */
4283 return (rix == 0xff ? 0 : rix);
4287 * Reclaim mbuf resources. For fragmented frames we
4288 * need to claim each frag chained with m_nextpkt.
4291 ath_freetx(struct mbuf *m)
4296 next = m->m_nextpkt;
4297 m->m_nextpkt = NULL;
4299 } while ((m = next) != NULL);
4303 ath_tx_dmasetup(struct ath_softc *sc, struct ath_buf *bf, struct mbuf *m0)
4309 * Load the DMA map so any coalescing is done. This
4310 * also calculates the number of descriptors we need.
4312 error = bus_dmamap_load_mbuf_sg(sc->sc_dmat, bf->bf_dmamap, m0,
4313 bf->bf_segs, &bf->bf_nseg,
4315 if (error == EFBIG) {
4316 /* XXX packet requires too many descriptors */
4317 bf->bf_nseg = ATH_TXDESC+1;
4318 } else if (error != 0) {
4319 sc->sc_stats.ast_tx_busdma++;
4324 * Discard null packets and check for packets that
4325 * require too many TX descriptors. We try to convert
4326 * the latter to a cluster.
4328 if (bf->bf_nseg > ATH_TXDESC) { /* too many desc's, linearize */
4329 sc->sc_stats.ast_tx_linear++;
4330 m = m_collapse(m0, M_DONTWAIT, ATH_TXDESC);
4333 sc->sc_stats.ast_tx_nombuf++;
4337 error = bus_dmamap_load_mbuf_sg(sc->sc_dmat, bf->bf_dmamap, m0,
4338 bf->bf_segs, &bf->bf_nseg,
4341 sc->sc_stats.ast_tx_busdma++;
4345 KASSERT(bf->bf_nseg <= ATH_TXDESC,
4346 ("too many segments after defrag; nseg %u", bf->bf_nseg));
4347 } else if (bf->bf_nseg == 0) { /* null packet, discard */
4348 sc->sc_stats.ast_tx_nodata++;
4352 DPRINTF(sc, ATH_DEBUG_XMIT, "%s: m %p len %u\n",
4353 __func__, m0, m0->m_pkthdr.len);
4354 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_PREWRITE);
4361 ath_tx_handoff(struct ath_softc *sc, struct ath_txq *txq, struct ath_buf *bf)
4363 struct ath_hal *ah = sc->sc_ah;
4364 struct ath_desc *ds, *ds0;
4368 * Fillin the remainder of the descriptor info.
4370 ds0 = ds = bf->bf_desc;
4371 for (i = 0; i < bf->bf_nseg; i++, ds++) {
4372 ds->ds_data = bf->bf_segs[i].ds_addr;
4373 if (i == bf->bf_nseg - 1)
4376 ds->ds_link = bf->bf_daddr + sizeof(*ds) * (i + 1);
4377 ath_hal_filltxdesc(ah, ds
4378 , bf->bf_segs[i].ds_len /* segment length */
4379 , i == 0 /* first segment */
4380 , i == bf->bf_nseg - 1 /* last segment */
4381 , ds0 /* first descriptor */
4383 DPRINTF(sc, ATH_DEBUG_XMIT,
4384 "%s: %d: %08x %08x %08x %08x %08x %08x\n",
4385 __func__, i, ds->ds_link, ds->ds_data,
4386 ds->ds_ctl0, ds->ds_ctl1, ds->ds_hw[0], ds->ds_hw[1]);
4389 * Insert the frame on the outbound list and pass it on
4390 * to the hardware. Multicast frames buffered for power
4391 * save stations and transmit from the CAB queue are stored
4392 * on a s/w only queue and loaded on to the CAB queue in
4393 * the SWBA handler since frames only go out on DTIM and
4394 * to avoid possible races.
4397 KASSERT((bf->bf_flags & ATH_BUF_BUSY) == 0,
4398 ("busy status 0x%x", bf->bf_flags));
4399 if (txq->axq_qnum != ATH_TXQ_SWQ) {
4400 #ifdef IEEE80211_SUPPORT_TDMA
4403 ATH_TXQ_INSERT_TAIL(txq, bf, bf_list);
4404 qbusy = ath_hal_txqenabled(ah, txq->axq_qnum);
4405 if (txq->axq_link == NULL) {
4407 * Be careful writing the address to TXDP. If
4408 * the tx q is enabled then this write will be
4409 * ignored. Normally this is not an issue but
4410 * when tdma is in use and the q is beacon gated
4411 * this race can occur. If the q is busy then
4412 * defer the work to later--either when another
4413 * packet comes along or when we prepare a beacon
4417 ath_hal_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr);
4418 txq->axq_flags &= ~ATH_TXQ_PUTPENDING;
4419 DPRINTF(sc, ATH_DEBUG_XMIT,
4420 "%s: TXDP[%u] = %p (%p) depth %d\n",
4421 __func__, txq->axq_qnum,
4422 (caddr_t)bf->bf_daddr, bf->bf_desc,
4425 txq->axq_flags |= ATH_TXQ_PUTPENDING;
4426 DPRINTF(sc, ATH_DEBUG_TDMA | ATH_DEBUG_XMIT,
4427 "%s: Q%u busy, defer enable\n", __func__,
4431 *txq->axq_link = bf->bf_daddr;
4432 DPRINTF(sc, ATH_DEBUG_XMIT,
4433 "%s: link[%u](%p)=%p (%p) depth %d\n", __func__,
4434 txq->axq_qnum, txq->axq_link,
4435 (caddr_t)bf->bf_daddr, bf->bf_desc, txq->axq_depth);
4436 if ((txq->axq_flags & ATH_TXQ_PUTPENDING) && !qbusy) {
4438 * The q was busy when we previously tried
4439 * to write the address of the first buffer
4440 * in the chain. Since it's not busy now
4441 * handle this chore. We are certain the
4442 * buffer at the front is the right one since
4443 * axq_link is NULL only when the buffer list
4446 ath_hal_puttxbuf(ah, txq->axq_qnum,
4447 STAILQ_FIRST(&txq->axq_q)->bf_daddr);
4448 txq->axq_flags &= ~ATH_TXQ_PUTPENDING;
4449 DPRINTF(sc, ATH_DEBUG_TDMA | ATH_DEBUG_XMIT,
4450 "%s: Q%u restarted\n", __func__,
4455 ATH_TXQ_INSERT_TAIL(txq, bf, bf_list);
4456 if (txq->axq_link == NULL) {
4457 ath_hal_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr);
4458 DPRINTF(sc, ATH_DEBUG_XMIT,
4459 "%s: TXDP[%u] = %p (%p) depth %d\n",
4460 __func__, txq->axq_qnum,
4461 (caddr_t)bf->bf_daddr, bf->bf_desc,
4464 *txq->axq_link = bf->bf_daddr;
4465 DPRINTF(sc, ATH_DEBUG_XMIT,
4466 "%s: link[%u](%p)=%p (%p) depth %d\n", __func__,
4467 txq->axq_qnum, txq->axq_link,
4468 (caddr_t)bf->bf_daddr, bf->bf_desc, txq->axq_depth);
4470 #endif /* IEEE80211_SUPPORT_TDMA */
4471 txq->axq_link = &bf->bf_desc[bf->bf_nseg - 1].ds_link;
4472 ath_hal_txstart(ah, txq->axq_qnum);
4474 if (txq->axq_link != NULL) {
4475 struct ath_buf *last = ATH_TXQ_LAST(txq);
4476 struct ieee80211_frame *wh;
4478 /* mark previous frame */
4479 wh = mtod(last->bf_m, struct ieee80211_frame *);
4480 wh->i_fc[1] |= IEEE80211_FC1_MORE_DATA;
4481 bus_dmamap_sync(sc->sc_dmat, last->bf_dmamap,
4482 BUS_DMASYNC_PREWRITE);
4484 /* link descriptor */
4485 *txq->axq_link = bf->bf_daddr;
4487 ATH_TXQ_INSERT_TAIL(txq, bf, bf_list);
4488 txq->axq_link = &bf->bf_desc[bf->bf_nseg - 1].ds_link;
4490 ATH_TXQ_UNLOCK(txq);
4494 ath_tx_start(struct ath_softc *sc, struct ieee80211_node *ni, struct ath_buf *bf,
4497 struct ieee80211vap *vap = ni->ni_vap;
4498 struct ath_vap *avp = ATH_VAP(vap);
4499 struct ath_hal *ah = sc->sc_ah;
4500 struct ifnet *ifp = sc->sc_ifp;
4501 struct ieee80211com *ic = ifp->if_l2com;
4502 const struct chanAccParams *cap = &ic->ic_wme.wme_chanParams;
4503 int error, iswep, ismcast, isfrag, ismrr;
4504 int keyix, hdrlen, pktlen, try0;
4505 u_int8_t rix, txrate, ctsrate;
4506 u_int8_t cix = 0xff; /* NB: silence compiler */
4507 struct ath_desc *ds;
4508 struct ath_txq *txq;
4509 struct ieee80211_frame *wh;
4510 u_int subtype, flags, ctsduration;
4512 const HAL_RATE_TABLE *rt;
4513 HAL_BOOL shortPreamble;
4514 struct ath_node *an;
4517 wh = mtod(m0, struct ieee80211_frame *);
4518 iswep = wh->i_fc[1] & IEEE80211_FC1_WEP;
4519 ismcast = IEEE80211_IS_MULTICAST(wh->i_addr1);
4520 isfrag = m0->m_flags & M_FRAG;
4521 hdrlen = ieee80211_anyhdrsize(wh);
4523 * Packet length must not include any
4524 * pad bytes; deduct them here.
4526 pktlen = m0->m_pkthdr.len - (hdrlen & 3);
4529 const struct ieee80211_cipher *cip;
4530 struct ieee80211_key *k;
4533 * Construct the 802.11 header+trailer for an encrypted
4534 * frame. The only reason this can fail is because of an
4535 * unknown or unsupported cipher/key type.
4537 k = ieee80211_crypto_encap(ni, m0);
4540 * This can happen when the key is yanked after the
4541 * frame was queued. Just discard the frame; the
4542 * 802.11 layer counts failures and provides
4543 * debugging/diagnostics.
4549 * Adjust the packet + header lengths for the crypto
4550 * additions and calculate the h/w key index. When
4551 * a s/w mic is done the frame will have had any mic
4552 * added to it prior to entry so m0->m_pkthdr.len will
4553 * account for it. Otherwise we need to add it to the
4557 hdrlen += cip->ic_header;
4558 pktlen += cip->ic_header + cip->ic_trailer;
4559 /* NB: frags always have any TKIP MIC done in s/w */
4560 if ((k->wk_flags & IEEE80211_KEY_SWMIC) == 0 && !isfrag)
4561 pktlen += cip->ic_miclen;
4562 keyix = k->wk_keyix;
4564 /* packet header may have moved, reset our local pointer */
4565 wh = mtod(m0, struct ieee80211_frame *);
4566 } else if (ni->ni_ucastkey.wk_cipher == &ieee80211_cipher_none) {
4568 * Use station key cache slot, if assigned.
4570 keyix = ni->ni_ucastkey.wk_keyix;
4571 if (keyix == IEEE80211_KEYIX_NONE)
4572 keyix = HAL_TXKEYIX_INVALID;
4574 keyix = HAL_TXKEYIX_INVALID;
4576 pktlen += IEEE80211_CRC_LEN;
4579 * Load the DMA map so any coalescing is done. This
4580 * also calculates the number of descriptors we need.
4582 error = ath_tx_dmasetup(sc, bf, m0);
4585 bf->bf_node = ni; /* NB: held reference */
4586 m0 = bf->bf_m; /* NB: may have changed */
4587 wh = mtod(m0, struct ieee80211_frame *);
4589 /* setup descriptors */
4591 rt = sc->sc_currates;
4592 KASSERT(rt != NULL, ("no rate table, mode %u", sc->sc_curmode));
4595 * NB: the 802.11 layer marks whether or not we should
4596 * use short preamble based on the current mode and
4597 * negotiated parameters.
4599 if ((ic->ic_flags & IEEE80211_F_SHPREAMBLE) &&
4600 (ni->ni_capinfo & IEEE80211_CAPINFO_SHORT_PREAMBLE)) {
4601 shortPreamble = AH_TRUE;
4602 sc->sc_stats.ast_tx_shortpre++;
4604 shortPreamble = AH_FALSE;
4608 flags = HAL_TXDESC_CLRDMASK; /* XXX needed for crypto errs */
4609 ismrr = 0; /* default no multi-rate retry*/
4610 pri = M_WME_GETAC(m0); /* honor classification */
4611 /* XXX use txparams instead of fixed values */
4613 * Calculate Atheros packet type from IEEE80211 packet header,
4614 * setup for rate calculations, and select h/w transmit queue.
4616 switch (wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) {
4617 case IEEE80211_FC0_TYPE_MGT:
4618 subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK;
4619 if (subtype == IEEE80211_FC0_SUBTYPE_BEACON)
4620 atype = HAL_PKT_TYPE_BEACON;
4621 else if (subtype == IEEE80211_FC0_SUBTYPE_PROBE_RESP)
4622 atype = HAL_PKT_TYPE_PROBE_RESP;
4623 else if (subtype == IEEE80211_FC0_SUBTYPE_ATIM)
4624 atype = HAL_PKT_TYPE_ATIM;
4626 atype = HAL_PKT_TYPE_NORMAL; /* XXX */
4627 rix = an->an_mgmtrix;
4628 txrate = rt->info[rix].rateCode;
4630 txrate |= rt->info[rix].shortPreamble;
4631 try0 = ATH_TXMGTTRY;
4632 flags |= HAL_TXDESC_INTREQ; /* force interrupt */
4634 case IEEE80211_FC0_TYPE_CTL:
4635 atype = HAL_PKT_TYPE_PSPOLL; /* stop setting of duration */
4636 rix = an->an_mgmtrix;
4637 txrate = rt->info[rix].rateCode;
4639 txrate |= rt->info[rix].shortPreamble;
4640 try0 = ATH_TXMGTTRY;
4641 flags |= HAL_TXDESC_INTREQ; /* force interrupt */
4643 case IEEE80211_FC0_TYPE_DATA:
4644 atype = HAL_PKT_TYPE_NORMAL; /* default */
4646 * Data frames: multicast frames go out at a fixed rate,
4647 * EAPOL frames use the mgmt frame rate; otherwise consult
4648 * the rate control module for the rate to use.
4651 rix = an->an_mcastrix;
4652 txrate = rt->info[rix].rateCode;
4654 txrate |= rt->info[rix].shortPreamble;
4656 } else if (m0->m_flags & M_EAPOL) {
4657 /* XXX? maybe always use long preamble? */
4658 rix = an->an_mgmtrix;
4659 txrate = rt->info[rix].rateCode;
4661 txrate |= rt->info[rix].shortPreamble;
4662 try0 = ATH_TXMAXTRY; /* XXX?too many? */
4664 ath_rate_findrate(sc, an, shortPreamble, pktlen,
4665 &rix, &try0, &txrate);
4666 sc->sc_txrix = rix; /* for LED blinking */
4667 sc->sc_lastdatarix = rix; /* for fast frames */
4668 if (try0 != ATH_TXMAXTRY)
4671 if (cap->cap_wmeParams[pri].wmep_noackPolicy)
4672 flags |= HAL_TXDESC_NOACK;
4675 if_printf(ifp, "bogus frame type 0x%x (%s)\n",
4676 wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK, __func__);
4681 txq = sc->sc_ac2q[pri];
4684 * When servicing one or more stations in power-save mode
4685 * (or) if there is some mcast data waiting on the mcast
4686 * queue (to prevent out of order delivery) multicast
4687 * frames must be buffered until after the beacon.
4689 if (ismcast && (vap->iv_ps_sta || avp->av_mcastq.axq_depth))
4690 txq = &avp->av_mcastq;
4693 * Calculate miscellaneous flags.
4696 flags |= HAL_TXDESC_NOACK; /* no ack on broad/multicast */
4697 } else if (pktlen > vap->iv_rtsthreshold &&
4698 (ni->ni_ath_flags & IEEE80211_NODE_FF) == 0) {
4699 flags |= HAL_TXDESC_RTSENA; /* RTS based on frame length */
4700 cix = rt->info[rix].controlRate;
4701 sc->sc_stats.ast_tx_rts++;
4703 if (flags & HAL_TXDESC_NOACK) /* NB: avoid double counting */
4704 sc->sc_stats.ast_tx_noack++;
4705 #ifdef IEEE80211_SUPPORT_TDMA
4706 if (sc->sc_tdma && (flags & HAL_TXDESC_NOACK) == 0) {
4707 DPRINTF(sc, ATH_DEBUG_TDMA,
4708 "%s: discard frame, ACK required w/ TDMA\n", __func__);
4709 sc->sc_stats.ast_tdma_ack++;
4716 * If 802.11g protection is enabled, determine whether
4717 * to use RTS/CTS or just CTS. Note that this is only
4718 * done for OFDM unicast frames.
4720 if ((ic->ic_flags & IEEE80211_F_USEPROT) &&
4721 rt->info[rix].phy == IEEE80211_T_OFDM &&
4722 (flags & HAL_TXDESC_NOACK) == 0) {
4723 /* XXX fragments must use CCK rates w/ protection */
4724 if (ic->ic_protmode == IEEE80211_PROT_RTSCTS)
4725 flags |= HAL_TXDESC_RTSENA;
4726 else if (ic->ic_protmode == IEEE80211_PROT_CTSONLY)
4727 flags |= HAL_TXDESC_CTSENA;
4730 * For frags it would be desirable to use the
4731 * highest CCK rate for RTS/CTS. But stations
4732 * farther away may detect it at a lower CCK rate
4733 * so use the configured protection rate instead
4736 cix = rt->info[sc->sc_protrix].controlRate;
4738 cix = rt->info[sc->sc_protrix].controlRate;
4739 sc->sc_stats.ast_tx_protect++;
4743 * Calculate duration. This logically belongs in the 802.11
4744 * layer but it lacks sufficient information to calculate it.
4746 if ((flags & HAL_TXDESC_NOACK) == 0 &&
4747 (wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) != IEEE80211_FC0_TYPE_CTL) {
4750 dur = rt->info[rix].spAckDuration;
4752 dur = rt->info[rix].lpAckDuration;
4753 if (wh->i_fc[1] & IEEE80211_FC1_MORE_FRAG) {
4754 dur += dur; /* additional SIFS+ACK */
4755 KASSERT(m0->m_nextpkt != NULL, ("no fragment"));
4757 * Include the size of next fragment so NAV is
4758 * updated properly. The last fragment uses only
4761 dur += ath_hal_computetxtime(ah, rt,
4762 m0->m_nextpkt->m_pkthdr.len,
4763 rix, shortPreamble);
4767 * Force hardware to use computed duration for next
4768 * fragment by disabling multi-rate retry which updates
4769 * duration based on the multi-rate duration table.
4772 try0 = ATH_TXMGTTRY; /* XXX? */
4774 *(u_int16_t *)wh->i_dur = htole16(dur);
4778 * Calculate RTS/CTS rate and duration if needed.
4781 if (flags & (HAL_TXDESC_RTSENA|HAL_TXDESC_CTSENA)) {
4783 * CTS transmit rate is derived from the transmit rate
4784 * by looking in the h/w rate table. We must also factor
4785 * in whether or not a short preamble is to be used.
4787 /* NB: cix is set above where RTS/CTS is enabled */
4788 KASSERT(cix != 0xff, ("cix not setup"));
4789 ctsrate = rt->info[cix].rateCode;
4791 * Compute the transmit duration based on the frame
4792 * size and the size of an ACK frame. We call into the
4793 * HAL to do the computation since it depends on the
4794 * characteristics of the actual PHY being used.
4796 * NB: CTS is assumed the same size as an ACK so we can
4797 * use the precalculated ACK durations.
4799 if (shortPreamble) {
4800 ctsrate |= rt->info[cix].shortPreamble;
4801 if (flags & HAL_TXDESC_RTSENA) /* SIFS + CTS */
4802 ctsduration += rt->info[cix].spAckDuration;
4803 ctsduration += ath_hal_computetxtime(ah,
4804 rt, pktlen, rix, AH_TRUE);
4805 if ((flags & HAL_TXDESC_NOACK) == 0) /* SIFS + ACK */
4806 ctsduration += rt->info[rix].spAckDuration;
4808 if (flags & HAL_TXDESC_RTSENA) /* SIFS + CTS */
4809 ctsduration += rt->info[cix].lpAckDuration;
4810 ctsduration += ath_hal_computetxtime(ah,
4811 rt, pktlen, rix, AH_FALSE);
4812 if ((flags & HAL_TXDESC_NOACK) == 0) /* SIFS + ACK */
4813 ctsduration += rt->info[rix].lpAckDuration;
4816 * Must disable multi-rate retry when using RTS/CTS.
4819 try0 = ATH_TXMGTTRY; /* XXX */
4824 * At this point we are committed to sending the frame
4825 * and we don't need to look at m_nextpkt; clear it in
4826 * case this frame is part of frag chain.
4828 m0->m_nextpkt = NULL;
4830 if (IFF_DUMPPKTS(sc, ATH_DEBUG_XMIT))
4831 ieee80211_dump_pkt(ic, mtod(m0, const uint8_t *), m0->m_len,
4832 sc->sc_hwmap[rix].ieeerate, -1);
4834 if (ieee80211_radiotap_active_vap(vap)) {
4835 u_int64_t tsf = ath_hal_gettsf64(ah);
4837 sc->sc_tx_th.wt_tsf = htole64(tsf);
4838 sc->sc_tx_th.wt_flags = sc->sc_hwmap[rix].txflags;
4840 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_WEP;
4842 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_FRAG;
4843 sc->sc_tx_th.wt_rate = sc->sc_hwmap[rix].ieeerate;
4844 sc->sc_tx_th.wt_txpower = ni->ni_txpower;
4845 sc->sc_tx_th.wt_antenna = sc->sc_txantenna;
4847 ieee80211_radiotap_tx(vap, m0);
4851 * Determine if a tx interrupt should be generated for
4852 * this descriptor. We take a tx interrupt to reap
4853 * descriptors when the h/w hits an EOL condition or
4854 * when the descriptor is specifically marked to generate
4855 * an interrupt. We periodically mark descriptors in this
4856 * way to insure timely replenishing of the supply needed
4857 * for sending frames. Defering interrupts reduces system
4858 * load and potentially allows more concurrent work to be
4859 * done but if done to aggressively can cause senders to
4862 * NB: use >= to deal with sc_txintrperiod changing
4863 * dynamically through sysctl.
4865 if (flags & HAL_TXDESC_INTREQ) {
4866 txq->axq_intrcnt = 0;
4867 } else if (++txq->axq_intrcnt >= sc->sc_txintrperiod) {
4868 flags |= HAL_TXDESC_INTREQ;
4869 txq->axq_intrcnt = 0;
4873 * Formulate first tx descriptor with tx controls.
4875 /* XXX check return value? */
4876 ath_hal_setuptxdesc(ah, ds
4877 , pktlen /* packet length */
4878 , hdrlen /* header length */
4879 , atype /* Atheros packet type */
4880 , ni->ni_txpower /* txpower */
4881 , txrate, try0 /* series 0 rate/tries */
4882 , keyix /* key cache index */
4883 , sc->sc_txantenna /* antenna mode */
4885 , ctsrate /* rts/cts rate */
4886 , ctsduration /* rts/cts duration */
4888 bf->bf_txflags = flags;
4890 * Setup the multi-rate retry state only when we're
4891 * going to use it. This assumes ath_hal_setuptxdesc
4892 * initializes the descriptors (so we don't have to)
4893 * when the hardware supports multi-rate retry and
4897 ath_rate_setupxtxdesc(sc, an, ds, shortPreamble, rix);
4899 ath_tx_handoff(sc, txq, bf);
4904 * Process completed xmit descriptors from the specified queue.
4907 ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq)
4909 struct ath_hal *ah = sc->sc_ah;
4910 struct ifnet *ifp = sc->sc_ifp;
4911 struct ieee80211com *ic = ifp->if_l2com;
4912 struct ath_buf *bf, *last;
4913 struct ath_desc *ds, *ds0;
4914 struct ath_tx_status *ts;
4915 struct ieee80211_node *ni;
4916 struct ath_node *an;
4917 int sr, lr, pri, nacked;
4920 DPRINTF(sc, ATH_DEBUG_TX_PROC, "%s: tx queue %u head %p link %p\n",
4921 __func__, txq->axq_qnum,
4922 (caddr_t)(uintptr_t) ath_hal_gettxbuf(sc->sc_ah, txq->axq_qnum),
4927 txq->axq_intrcnt = 0; /* reset periodic desc intr count */
4928 bf = STAILQ_FIRST(&txq->axq_q);
4930 ATH_TXQ_UNLOCK(txq);
4933 ds0 = &bf->bf_desc[0];
4934 ds = &bf->bf_desc[bf->bf_nseg - 1];
4935 ts = &bf->bf_status.ds_txstat;
4936 status = ath_hal_txprocdesc(ah, ds, ts);
4938 if (sc->sc_debug & ATH_DEBUG_XMIT_DESC)
4939 ath_printtxbuf(sc, bf, txq->axq_qnum, 0,
4942 if (status == HAL_EINPROGRESS) {
4943 ATH_TXQ_UNLOCK(txq);
4946 ATH_TXQ_REMOVE_HEAD(txq, bf_list);
4947 #ifdef IEEE80211_SUPPORT_TDMA
4948 if (txq->axq_depth > 0) {
4950 * More frames follow. Mark the buffer busy
4951 * so it's not re-used while the hardware may
4952 * still re-read the link field in the descriptor.
4954 bf->bf_flags |= ATH_BUF_BUSY;
4957 if (txq->axq_depth == 0)
4959 txq->axq_link = NULL;
4960 ATH_TXQ_UNLOCK(txq);
4965 if (ts->ts_status == 0) {
4966 u_int8_t txant = ts->ts_antenna;
4967 sc->sc_stats.ast_ant_tx[txant]++;
4968 sc->sc_ant_tx[txant]++;
4969 if (ts->ts_finaltsi != 0)
4970 sc->sc_stats.ast_tx_altrate++;
4971 pri = M_WME_GETAC(bf->bf_m);
4972 if (pri >= WME_AC_VO)
4973 ic->ic_wme.wme_hipri_traffic++;
4974 if ((bf->bf_txflags & HAL_TXDESC_NOACK) == 0)
4975 ni->ni_inact = ni->ni_inact_reload;
4977 if (ts->ts_status & HAL_TXERR_XRETRY)
4978 sc->sc_stats.ast_tx_xretries++;
4979 if (ts->ts_status & HAL_TXERR_FIFO)
4980 sc->sc_stats.ast_tx_fifoerr++;
4981 if (ts->ts_status & HAL_TXERR_FILT)
4982 sc->sc_stats.ast_tx_filtered++;
4983 if (bf->bf_m->m_flags & M_FF)
4984 sc->sc_stats.ast_ff_txerr++;
4986 sr = ts->ts_shortretry;
4987 lr = ts->ts_longretry;
4988 sc->sc_stats.ast_tx_shortretry += sr;
4989 sc->sc_stats.ast_tx_longretry += lr;
4991 * Hand the descriptor to the rate control algorithm.
4993 if ((ts->ts_status & HAL_TXERR_FILT) == 0 &&
4994 (bf->bf_txflags & HAL_TXDESC_NOACK) == 0) {
4996 * If frame was ack'd update statistics,
4997 * including the last rx time used to
4998 * workaround phantom bmiss interrupts.
5000 if (ts->ts_status == 0) {
5002 sc->sc_stats.ast_tx_rssi = ts->ts_rssi;
5003 ATH_RSSI_LPF(sc->sc_halstats.ns_avgtxrssi,
5006 ath_rate_tx_complete(sc, an, bf);
5009 * Do any tx complete callback. Note this must
5010 * be done before releasing the node reference.
5012 if (bf->bf_m->m_flags & M_TXCB)
5013 ieee80211_process_callback(ni, bf->bf_m,
5014 (bf->bf_txflags & HAL_TXDESC_NOACK) == 0 ?
5015 ts->ts_status : HAL_TXERR_XRETRY);
5016 ieee80211_free_node(ni);
5018 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap,
5019 BUS_DMASYNC_POSTWRITE);
5020 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap);
5027 last = STAILQ_LAST(&sc->sc_txbuf, ath_buf, bf_list);
5029 last->bf_flags &= ~ATH_BUF_BUSY;
5030 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list);
5031 ATH_TXBUF_UNLOCK(sc);
5033 #ifdef IEEE80211_SUPPORT_SUPERG
5035 * Flush fast-frame staging queue when traffic slows.
5037 if (txq->axq_depth <= 1)
5038 ieee80211_ff_flush(ic, txq->axq_ac);
5044 txqactive(struct ath_hal *ah, int qnum)
5046 u_int32_t txqs = 1<<qnum;
5047 ath_hal_gettxintrtxqs(ah, &txqs);
5048 return (txqs & (1<<qnum));
5052 * Deferred processing of transmit interrupt; special-cased
5053 * for a single hardware transmit queue (e.g. 5210 and 5211).
5056 ath_tx_proc_q0(void *arg, int npending)
5058 struct ath_softc *sc = arg;
5059 struct ifnet *ifp = sc->sc_ifp;
5061 if (txqactive(sc->sc_ah, 0) && ath_tx_processq(sc, &sc->sc_txq[0]))
5062 sc->sc_lastrx = ath_hal_gettsf64(sc->sc_ah);
5063 if (txqactive(sc->sc_ah, sc->sc_cabq->axq_qnum))
5064 ath_tx_processq(sc, sc->sc_cabq);
5065 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
5066 sc->sc_wd_timer = 0;
5069 ath_led_event(sc, sc->sc_txrix);
5075 * Deferred processing of transmit interrupt; special-cased
5076 * for four hardware queues, 0-3 (e.g. 5212 w/ WME support).
5079 ath_tx_proc_q0123(void *arg, int npending)
5081 struct ath_softc *sc = arg;
5082 struct ifnet *ifp = sc->sc_ifp;
5086 * Process each active queue.
5089 if (txqactive(sc->sc_ah, 0))
5090 nacked += ath_tx_processq(sc, &sc->sc_txq[0]);
5091 if (txqactive(sc->sc_ah, 1))
5092 nacked += ath_tx_processq(sc, &sc->sc_txq[1]);
5093 if (txqactive(sc->sc_ah, 2))
5094 nacked += ath_tx_processq(sc, &sc->sc_txq[2]);
5095 if (txqactive(sc->sc_ah, 3))
5096 nacked += ath_tx_processq(sc, &sc->sc_txq[3]);
5097 if (txqactive(sc->sc_ah, sc->sc_cabq->axq_qnum))
5098 ath_tx_processq(sc, sc->sc_cabq);
5100 sc->sc_lastrx = ath_hal_gettsf64(sc->sc_ah);
5102 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
5103 sc->sc_wd_timer = 0;
5106 ath_led_event(sc, sc->sc_txrix);
5112 * Deferred processing of transmit interrupt.
5115 ath_tx_proc(void *arg, int npending)
5117 struct ath_softc *sc = arg;
5118 struct ifnet *ifp = sc->sc_ifp;
5122 * Process each active queue.
5125 for (i = 0; i < HAL_NUM_TX_QUEUES; i++)
5126 if (ATH_TXQ_SETUP(sc, i) && txqactive(sc->sc_ah, i))
5127 nacked += ath_tx_processq(sc, &sc->sc_txq[i]);
5129 sc->sc_lastrx = ath_hal_gettsf64(sc->sc_ah);
5131 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
5132 sc->sc_wd_timer = 0;
5135 ath_led_event(sc, sc->sc_txrix);
5141 ath_tx_draintxq(struct ath_softc *sc, struct ath_txq *txq)
5144 struct ath_hal *ah = sc->sc_ah;
5146 struct ieee80211_node *ni;
5151 * NB: this assumes output has been stopped and
5152 * we do not need to block ath_tx_proc
5155 bf = STAILQ_LAST(&sc->sc_txbuf, ath_buf, bf_list);
5157 bf->bf_flags &= ~ATH_BUF_BUSY;
5158 ATH_TXBUF_UNLOCK(sc);
5159 for (ix = 0;; ix++) {
5161 bf = STAILQ_FIRST(&txq->axq_q);
5163 txq->axq_link = NULL;
5164 ATH_TXQ_UNLOCK(txq);
5167 ATH_TXQ_REMOVE_HEAD(txq, bf_list);
5168 ATH_TXQ_UNLOCK(txq);
5170 if (sc->sc_debug & ATH_DEBUG_RESET) {
5171 struct ieee80211com *ic = sc->sc_ifp->if_l2com;
5173 ath_printtxbuf(sc, bf, txq->axq_qnum, ix,
5174 ath_hal_txprocdesc(ah, bf->bf_desc,
5175 &bf->bf_status.ds_txstat) == HAL_OK);
5176 ieee80211_dump_pkt(ic, mtod(bf->bf_m, const uint8_t *),
5177 bf->bf_m->m_len, 0, -1);
5179 #endif /* ATH_DEBUG */
5180 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap);
5185 * Do any callback and reclaim the node reference.
5187 if (bf->bf_m->m_flags & M_TXCB)
5188 ieee80211_process_callback(ni, bf->bf_m, -1);
5189 ieee80211_free_node(ni);
5193 bf->bf_flags &= ~ATH_BUF_BUSY;
5196 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list);
5197 ATH_TXBUF_UNLOCK(sc);
5202 ath_tx_stopdma(struct ath_softc *sc, struct ath_txq *txq)
5204 struct ath_hal *ah = sc->sc_ah;
5206 DPRINTF(sc, ATH_DEBUG_RESET, "%s: tx queue [%u] %p, link %p\n",
5207 __func__, txq->axq_qnum,
5208 (caddr_t)(uintptr_t) ath_hal_gettxbuf(ah, txq->axq_qnum),
5210 (void) ath_hal_stoptxdma(ah, txq->axq_qnum);
5214 * Drain the transmit queues and reclaim resources.
5217 ath_draintxq(struct ath_softc *sc)
5219 struct ath_hal *ah = sc->sc_ah;
5220 struct ifnet *ifp = sc->sc_ifp;
5223 /* XXX return value */
5224 if (!sc->sc_invalid) {
5225 /* don't touch the hardware if marked invalid */
5226 DPRINTF(sc, ATH_DEBUG_RESET, "%s: tx queue [%u] %p, link %p\n",
5227 __func__, sc->sc_bhalq,
5228 (caddr_t)(uintptr_t) ath_hal_gettxbuf(ah, sc->sc_bhalq),
5230 (void) ath_hal_stoptxdma(ah, sc->sc_bhalq);
5231 for (i = 0; i < HAL_NUM_TX_QUEUES; i++)
5232 if (ATH_TXQ_SETUP(sc, i))
5233 ath_tx_stopdma(sc, &sc->sc_txq[i]);
5235 for (i = 0; i < HAL_NUM_TX_QUEUES; i++)
5236 if (ATH_TXQ_SETUP(sc, i))
5237 ath_tx_draintxq(sc, &sc->sc_txq[i]);
5239 if (sc->sc_debug & ATH_DEBUG_RESET) {
5240 struct ath_buf *bf = STAILQ_FIRST(&sc->sc_bbuf);
5241 if (bf != NULL && bf->bf_m != NULL) {
5242 ath_printtxbuf(sc, bf, sc->sc_bhalq, 0,
5243 ath_hal_txprocdesc(ah, bf->bf_desc,
5244 &bf->bf_status.ds_txstat) == HAL_OK);
5245 ieee80211_dump_pkt(ifp->if_l2com,
5246 mtod(bf->bf_m, const uint8_t *), bf->bf_m->m_len,
5250 #endif /* ATH_DEBUG */
5251 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
5252 sc->sc_wd_timer = 0;
5256 * Disable the receive h/w in preparation for a reset.
5259 ath_stoprecv(struct ath_softc *sc)
5261 #define PA2DESC(_sc, _pa) \
5262 ((struct ath_desc *)((caddr_t)(_sc)->sc_rxdma.dd_desc + \
5263 ((_pa) - (_sc)->sc_rxdma.dd_desc_paddr)))
5264 struct ath_hal *ah = sc->sc_ah;
5266 ath_hal_stoppcurecv(ah); /* disable PCU */
5267 ath_hal_setrxfilter(ah, 0); /* clear recv filter */
5268 ath_hal_stopdmarecv(ah); /* disable DMA engine */
5269 DELAY(3000); /* 3ms is long enough for 1 frame */
5271 if (sc->sc_debug & (ATH_DEBUG_RESET | ATH_DEBUG_FATAL)) {
5275 printf("%s: rx queue %p, link %p\n", __func__,
5276 (caddr_t)(uintptr_t) ath_hal_getrxbuf(ah), sc->sc_rxlink);
5278 STAILQ_FOREACH(bf, &sc->sc_rxbuf, bf_list) {
5279 struct ath_desc *ds = bf->bf_desc;
5280 struct ath_rx_status *rs = &bf->bf_status.ds_rxstat;
5281 HAL_STATUS status = ath_hal_rxprocdesc(ah, ds,
5282 bf->bf_daddr, PA2DESC(sc, ds->ds_link), rs);
5283 if (status == HAL_OK || (sc->sc_debug & ATH_DEBUG_FATAL))
5284 ath_printrxbuf(sc, bf, ix, status == HAL_OK);
5289 if (sc->sc_rxpending != NULL) {
5290 m_freem(sc->sc_rxpending);
5291 sc->sc_rxpending = NULL;
5293 sc->sc_rxlink = NULL; /* just in case */
5298 * Enable the receive h/w following a reset.
5301 ath_startrecv(struct ath_softc *sc)
5303 struct ath_hal *ah = sc->sc_ah;
5306 sc->sc_rxlink = NULL;
5307 sc->sc_rxpending = NULL;
5308 STAILQ_FOREACH(bf, &sc->sc_rxbuf, bf_list) {
5309 int error = ath_rxbuf_init(sc, bf);
5311 DPRINTF(sc, ATH_DEBUG_RECV,
5312 "%s: ath_rxbuf_init failed %d\n",
5318 bf = STAILQ_FIRST(&sc->sc_rxbuf);
5319 ath_hal_putrxbuf(ah, bf->bf_daddr);
5320 ath_hal_rxena(ah); /* enable recv descriptors */
5321 ath_mode_init(sc); /* set filters, etc. */
5322 ath_hal_startpcurecv(ah); /* re-enable PCU/DMA engine */
5327 * Update internal state after a channel change.
5330 ath_chan_change(struct ath_softc *sc, struct ieee80211_channel *chan)
5332 enum ieee80211_phymode mode;
5335 * Change channels and update the h/w rate map
5336 * if we're switching; e.g. 11a to 11b/g.
5338 mode = ieee80211_chan2mode(chan);
5339 if (mode != sc->sc_curmode)
5340 ath_setcurmode(sc, mode);
5341 sc->sc_curchan = chan;
5345 * Set/change channels. If the channel is really being changed,
5346 * it's done by reseting the chip. To accomplish this we must
5347 * first cleanup any pending DMA, then restart stuff after a la
5351 ath_chan_set(struct ath_softc *sc, struct ieee80211_channel *chan)
5353 struct ifnet *ifp = sc->sc_ifp;
5354 struct ieee80211com *ic = ifp->if_l2com;
5355 struct ath_hal *ah = sc->sc_ah;
5357 DPRINTF(sc, ATH_DEBUG_RESET, "%s: %u (%u MHz, flags 0x%x)\n",
5358 __func__, ieee80211_chan2ieee(ic, chan),
5359 chan->ic_freq, chan->ic_flags);
5360 if (chan != sc->sc_curchan) {
5363 * To switch channels clear any pending DMA operations;
5364 * wait long enough for the RX fifo to drain, reset the
5365 * hardware at the new frequency, and then re-enable
5366 * the relevant bits of the h/w.
5368 ath_hal_intrset(ah, 0); /* disable interrupts */
5369 ath_draintxq(sc); /* clear pending tx frames */
5370 ath_stoprecv(sc); /* turn off frame recv */
5371 if (!ath_hal_reset(ah, sc->sc_opmode, chan, AH_TRUE, &status)) {
5372 if_printf(ifp, "%s: unable to reset "
5373 "channel %u (%u MHz, flags 0x%x), hal status %u\n",
5374 __func__, ieee80211_chan2ieee(ic, chan),
5375 chan->ic_freq, chan->ic_flags, status);
5378 sc->sc_diversity = ath_hal_getdiversity(ah);
5381 * Re-enable rx framework.
5383 if (ath_startrecv(sc) != 0) {
5384 if_printf(ifp, "%s: unable to restart recv logic\n",
5390 * Change channels and update the h/w rate map
5391 * if we're switching; e.g. 11a to 11b/g.
5393 ath_chan_change(sc, chan);
5396 * Re-enable interrupts.
5398 ath_hal_intrset(ah, sc->sc_imask);
5404 * Periodically recalibrate the PHY to account
5405 * for temperature/environment changes.
5408 ath_calibrate(void *arg)
5410 struct ath_softc *sc = arg;
5411 struct ath_hal *ah = sc->sc_ah;
5412 struct ifnet *ifp = sc->sc_ifp;
5413 struct ieee80211com *ic = ifp->if_l2com;
5414 HAL_BOOL longCal, isCalDone;
5417 if (ic->ic_flags & IEEE80211_F_SCAN) /* defer, off channel */
5419 longCal = (ticks - sc->sc_lastlongcal >= ath_longcalinterval*hz);
5421 sc->sc_stats.ast_per_cal++;
5422 if (ath_hal_getrfgain(ah) == HAL_RFGAIN_NEED_CHANGE) {
5424 * Rfgain is out of bounds, reset the chip
5425 * to load new gain values.
5427 DPRINTF(sc, ATH_DEBUG_CALIBRATE,
5428 "%s: rfgain change\n", __func__);
5429 sc->sc_stats.ast_per_rfgain++;
5433 * If this long cal is after an idle period, then
5434 * reset the data collection state so we start fresh.
5436 if (sc->sc_resetcal) {
5437 (void) ath_hal_calreset(ah, sc->sc_curchan);
5438 sc->sc_lastcalreset = ticks;
5439 sc->sc_resetcal = 0;
5442 if (ath_hal_calibrateN(ah, sc->sc_curchan, longCal, &isCalDone)) {
5445 * Calibrate noise floor data again in case of change.
5447 ath_hal_process_noisefloor(ah);
5450 DPRINTF(sc, ATH_DEBUG_ANY,
5451 "%s: calibration of channel %u failed\n",
5452 __func__, sc->sc_curchan->ic_freq);
5453 sc->sc_stats.ast_per_calfail++;
5458 * Use a shorter interval to potentially collect multiple
5459 * data samples required to complete calibration. Once
5460 * we're told the work is done we drop back to a longer
5461 * interval between requests. We're more aggressive doing
5462 * work when operating as an AP to improve operation right
5465 nextcal = (1000*ath_shortcalinterval)/hz;
5466 if (sc->sc_opmode != HAL_M_HOSTAP)
5469 nextcal = ath_longcalinterval*hz;
5470 sc->sc_lastlongcal = ticks;
5471 if (sc->sc_lastcalreset == 0)
5472 sc->sc_lastcalreset = sc->sc_lastlongcal;
5473 else if (ticks - sc->sc_lastcalreset >= ath_resetcalinterval*hz)
5474 sc->sc_resetcal = 1; /* setup reset next trip */
5478 DPRINTF(sc, ATH_DEBUG_CALIBRATE, "%s: next +%u (%sisCalDone)\n",
5479 __func__, nextcal, isCalDone ? "" : "!");
5480 callout_reset(&sc->sc_cal_ch, nextcal, ath_calibrate, sc);
5482 DPRINTF(sc, ATH_DEBUG_CALIBRATE, "%s: calibration disabled\n",
5484 /* NB: don't rearm timer */
5489 ath_scan_start(struct ieee80211com *ic)
5491 struct ifnet *ifp = ic->ic_ifp;
5492 struct ath_softc *sc = ifp->if_softc;
5493 struct ath_hal *ah = sc->sc_ah;
5496 /* XXX calibration timer? */
5498 sc->sc_scanning = 1;
5499 sc->sc_syncbeacon = 0;
5500 rfilt = ath_calcrxfilter(sc);
5501 ath_hal_setrxfilter(ah, rfilt);
5502 ath_hal_setassocid(ah, ifp->if_broadcastaddr, 0);
5504 DPRINTF(sc, ATH_DEBUG_STATE, "%s: RX filter 0x%x bssid %s aid 0\n",
5505 __func__, rfilt, ether_sprintf(ifp->if_broadcastaddr));
5509 ath_scan_end(struct ieee80211com *ic)
5511 struct ifnet *ifp = ic->ic_ifp;
5512 struct ath_softc *sc = ifp->if_softc;
5513 struct ath_hal *ah = sc->sc_ah;
5516 sc->sc_scanning = 0;
5517 rfilt = ath_calcrxfilter(sc);
5518 ath_hal_setrxfilter(ah, rfilt);
5519 ath_hal_setassocid(ah, sc->sc_curbssid, sc->sc_curaid);
5521 ath_hal_process_noisefloor(ah);
5523 DPRINTF(sc, ATH_DEBUG_STATE, "%s: RX filter 0x%x bssid %s aid 0x%x\n",
5524 __func__, rfilt, ether_sprintf(sc->sc_curbssid),
5529 ath_set_channel(struct ieee80211com *ic)
5531 struct ifnet *ifp = ic->ic_ifp;
5532 struct ath_softc *sc = ifp->if_softc;
5534 (void) ath_chan_set(sc, ic->ic_curchan);
5536 * If we are returning to our bss channel then mark state
5537 * so the next recv'd beacon's tsf will be used to sync the
5538 * beacon timers. Note that since we only hear beacons in
5539 * sta/ibss mode this has no effect in other operating modes.
5541 if (!sc->sc_scanning && ic->ic_curchan == ic->ic_bsschan)
5542 sc->sc_syncbeacon = 1;
5546 * Walk the vap list and check if there any vap's in RUN state.
5549 ath_isanyrunningvaps(struct ieee80211vap *this)
5551 struct ieee80211com *ic = this->iv_ic;
5552 struct ieee80211vap *vap;
5554 IEEE80211_LOCK_ASSERT(ic);
5556 TAILQ_FOREACH(vap, &ic->ic_vaps, iv_next) {
5557 if (vap != this && vap->iv_state >= IEEE80211_S_RUN)
5564 ath_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg)
5566 struct ieee80211com *ic = vap->iv_ic;
5567 struct ath_softc *sc = ic->ic_ifp->if_softc;
5568 struct ath_vap *avp = ATH_VAP(vap);
5569 struct ath_hal *ah = sc->sc_ah;
5570 struct ieee80211_node *ni = NULL;
5571 int i, error, stamode;
5573 static const HAL_LED_STATE leds[] = {
5574 HAL_LED_INIT, /* IEEE80211_S_INIT */
5575 HAL_LED_SCAN, /* IEEE80211_S_SCAN */
5576 HAL_LED_AUTH, /* IEEE80211_S_AUTH */
5577 HAL_LED_ASSOC, /* IEEE80211_S_ASSOC */
5578 HAL_LED_RUN, /* IEEE80211_S_CAC */
5579 HAL_LED_RUN, /* IEEE80211_S_RUN */
5580 HAL_LED_RUN, /* IEEE80211_S_CSA */
5581 HAL_LED_RUN, /* IEEE80211_S_SLEEP */
5584 DPRINTF(sc, ATH_DEBUG_STATE, "%s: %s -> %s\n", __func__,
5585 ieee80211_state_name[vap->iv_state],
5586 ieee80211_state_name[nstate]);
5588 callout_drain(&sc->sc_cal_ch);
5589 ath_hal_setledstate(ah, leds[nstate]); /* set LED */
5591 if (nstate == IEEE80211_S_SCAN) {
5593 * Scanning: turn off beacon miss and don't beacon.
5594 * Mark beacon state so when we reach RUN state we'll
5595 * [re]setup beacons. Unblock the task q thread so
5596 * deferred interrupt processing is done.
5599 sc->sc_imask &~ (HAL_INT_SWBA | HAL_INT_BMISS));
5600 sc->sc_imask &= ~(HAL_INT_SWBA | HAL_INT_BMISS);
5602 taskqueue_unblock(sc->sc_tq);
5606 rfilt = ath_calcrxfilter(sc);
5607 stamode = (vap->iv_opmode == IEEE80211_M_STA ||
5608 vap->iv_opmode == IEEE80211_M_AHDEMO ||
5609 vap->iv_opmode == IEEE80211_M_IBSS);
5610 if (stamode && nstate == IEEE80211_S_RUN) {
5611 sc->sc_curaid = ni->ni_associd;
5612 IEEE80211_ADDR_COPY(sc->sc_curbssid, ni->ni_bssid);
5613 ath_hal_setassocid(ah, sc->sc_curbssid, sc->sc_curaid);
5615 DPRINTF(sc, ATH_DEBUG_STATE, "%s: RX filter 0x%x bssid %s aid 0x%x\n",
5616 __func__, rfilt, ether_sprintf(sc->sc_curbssid), sc->sc_curaid);
5617 ath_hal_setrxfilter(ah, rfilt);
5619 /* XXX is this to restore keycache on resume? */
5620 if (vap->iv_opmode != IEEE80211_M_STA &&
5621 (vap->iv_flags & IEEE80211_F_PRIVACY)) {
5622 for (i = 0; i < IEEE80211_WEP_NKID; i++)
5623 if (ath_hal_keyisvalid(ah, i))
5624 ath_hal_keysetmac(ah, i, ni->ni_bssid);
5628 * Invoke the parent method to do net80211 work.
5630 error = avp->av_newstate(vap, nstate, arg);
5634 if (nstate == IEEE80211_S_RUN) {
5635 /* NB: collect bss node again, it may have changed */
5638 DPRINTF(sc, ATH_DEBUG_STATE,
5639 "%s(RUN): iv_flags 0x%08x bintvl %d bssid %s "
5640 "capinfo 0x%04x chan %d\n", __func__,
5641 vap->iv_flags, ni->ni_intval, ether_sprintf(ni->ni_bssid),
5642 ni->ni_capinfo, ieee80211_chan2ieee(ic, ic->ic_curchan));
5644 switch (vap->iv_opmode) {
5645 #ifdef IEEE80211_SUPPORT_TDMA
5646 case IEEE80211_M_AHDEMO:
5647 if ((vap->iv_caps & IEEE80211_C_TDMA) == 0)
5651 case IEEE80211_M_HOSTAP:
5652 case IEEE80211_M_IBSS:
5653 case IEEE80211_M_MBSS:
5655 * Allocate and setup the beacon frame.
5657 * Stop any previous beacon DMA. This may be
5658 * necessary, for example, when an ibss merge
5659 * causes reconfiguration; there will be a state
5660 * transition from RUN->RUN that means we may
5661 * be called with beacon transmission active.
5663 ath_hal_stoptxdma(ah, sc->sc_bhalq);
5665 error = ath_beacon_alloc(sc, ni);
5669 * If joining an adhoc network defer beacon timer
5670 * configuration to the next beacon frame so we
5671 * have a current TSF to use. Otherwise we're
5672 * starting an ibss/bss so there's no need to delay;
5673 * if this is the first vap moving to RUN state, then
5674 * beacon state needs to be [re]configured.
5676 if (vap->iv_opmode == IEEE80211_M_IBSS &&
5677 ni->ni_tstamp.tsf != 0) {
5678 sc->sc_syncbeacon = 1;
5679 } else if (!sc->sc_beacons) {
5680 #ifdef IEEE80211_SUPPORT_TDMA
5681 if (vap->iv_caps & IEEE80211_C_TDMA)
5682 ath_tdma_config(sc, vap);
5685 ath_beacon_config(sc, vap);
5689 case IEEE80211_M_STA:
5691 * Defer beacon timer configuration to the next
5692 * beacon frame so we have a current TSF to use
5693 * (any TSF collected when scanning is likely old).
5695 sc->sc_syncbeacon = 1;
5697 case IEEE80211_M_MONITOR:
5699 * Monitor mode vaps have only INIT->RUN and RUN->RUN
5700 * transitions so we must re-enable interrupts here to
5701 * handle the case of a single monitor mode vap.
5703 ath_hal_intrset(ah, sc->sc_imask);
5705 case IEEE80211_M_WDS:
5711 * Let the hal process statistics collected during a
5712 * scan so it can provide calibrated noise floor data.
5714 ath_hal_process_noisefloor(ah);
5716 * Reset rssi stats; maybe not the best place...
5718 sc->sc_halstats.ns_avgbrssi = ATH_RSSI_DUMMY_MARKER;
5719 sc->sc_halstats.ns_avgrssi = ATH_RSSI_DUMMY_MARKER;
5720 sc->sc_halstats.ns_avgtxrssi = ATH_RSSI_DUMMY_MARKER;
5722 * Finally, start any timers and the task q thread
5723 * (in case we didn't go through SCAN state).
5725 if (ath_longcalinterval != 0) {
5726 /* start periodic recalibration timer */
5727 callout_reset(&sc->sc_cal_ch, 1, ath_calibrate, sc);
5729 DPRINTF(sc, ATH_DEBUG_CALIBRATE,
5730 "%s: calibration disabled\n", __func__);
5732 taskqueue_unblock(sc->sc_tq);
5733 } else if (nstate == IEEE80211_S_INIT) {
5735 * If there are no vaps left in RUN state then
5736 * shutdown host/driver operation:
5737 * o disable interrupts
5738 * o disable the task queue thread
5739 * o mark beacon processing as stopped
5741 if (!ath_isanyrunningvaps(vap)) {
5742 sc->sc_imask &= ~(HAL_INT_SWBA | HAL_INT_BMISS);
5743 /* disable interrupts */
5744 ath_hal_intrset(ah, sc->sc_imask &~ HAL_INT_GLOBAL);
5745 taskqueue_block(sc->sc_tq);
5748 #ifdef IEEE80211_SUPPORT_TDMA
5749 ath_hal_setcca(ah, AH_TRUE);
5757 * Allocate a key cache slot to the station so we can
5758 * setup a mapping from key index to node. The key cache
5759 * slot is needed for managing antenna state and for
5760 * compression when stations do not use crypto. We do
5761 * it uniliaterally here; if crypto is employed this slot
5762 * will be reassigned.
5765 ath_setup_stationkey(struct ieee80211_node *ni)
5767 struct ieee80211vap *vap = ni->ni_vap;
5768 struct ath_softc *sc = vap->iv_ic->ic_ifp->if_softc;
5769 ieee80211_keyix keyix, rxkeyix;
5771 if (!ath_key_alloc(vap, &ni->ni_ucastkey, &keyix, &rxkeyix)) {
5773 * Key cache is full; we'll fall back to doing
5774 * the more expensive lookup in software. Note
5775 * this also means no h/w compression.
5777 /* XXX msg+statistic */
5780 ni->ni_ucastkey.wk_keyix = keyix;
5781 ni->ni_ucastkey.wk_rxkeyix = rxkeyix;
5782 /* NB: must mark device key to get called back on delete */
5783 ni->ni_ucastkey.wk_flags |= IEEE80211_KEY_DEVKEY;
5784 IEEE80211_ADDR_COPY(ni->ni_ucastkey.wk_macaddr, ni->ni_macaddr);
5785 /* NB: this will create a pass-thru key entry */
5786 ath_keyset(sc, &ni->ni_ucastkey, vap->iv_bss);
5791 * Setup driver-specific state for a newly associated node.
5792 * Note that we're called also on a re-associate, the isnew
5793 * param tells us if this is the first time or not.
5796 ath_newassoc(struct ieee80211_node *ni, int isnew)
5798 struct ath_node *an = ATH_NODE(ni);
5799 struct ieee80211vap *vap = ni->ni_vap;
5800 struct ath_softc *sc = vap->iv_ic->ic_ifp->if_softc;
5801 const struct ieee80211_txparam *tp = ni->ni_txparms;
5803 an->an_mcastrix = ath_tx_findrix(sc, tp->mcastrate);
5804 an->an_mgmtrix = ath_tx_findrix(sc, tp->mgmtrate);
5806 ath_rate_newassoc(sc, an, isnew);
5808 (vap->iv_flags & IEEE80211_F_PRIVACY) == 0 && sc->sc_hasclrkey &&
5809 ni->ni_ucastkey.wk_keyix == IEEE80211_KEYIX_NONE)
5810 ath_setup_stationkey(ni);
5814 ath_setregdomain(struct ieee80211com *ic, struct ieee80211_regdomain *reg,
5815 int nchans, struct ieee80211_channel chans[])
5817 struct ath_softc *sc = ic->ic_ifp->if_softc;
5818 struct ath_hal *ah = sc->sc_ah;
5821 DPRINTF(sc, ATH_DEBUG_REGDOMAIN,
5822 "%s: rd %u cc %u location %c%s\n",
5823 __func__, reg->regdomain, reg->country, reg->location,
5824 reg->ecm ? " ecm" : "");
5826 status = ath_hal_set_channels(ah, chans, nchans,
5827 reg->country, reg->regdomain);
5828 if (status != HAL_OK) {
5829 DPRINTF(sc, ATH_DEBUG_REGDOMAIN, "%s: failed, status %u\n",
5831 return EINVAL; /* XXX */
5837 ath_getradiocaps(struct ieee80211com *ic,
5838 int maxchans, int *nchans, struct ieee80211_channel chans[])
5840 struct ath_softc *sc = ic->ic_ifp->if_softc;
5841 struct ath_hal *ah = sc->sc_ah;
5843 DPRINTF(sc, ATH_DEBUG_REGDOMAIN, "%s: use rd %u cc %d\n",
5844 __func__, SKU_DEBUG, CTRY_DEFAULT);
5846 /* XXX check return */
5847 (void) ath_hal_getchannels(ah, chans, maxchans, nchans,
5848 HAL_MODE_ALL, CTRY_DEFAULT, SKU_DEBUG, AH_TRUE);
5853 ath_getchannels(struct ath_softc *sc)
5855 struct ifnet *ifp = sc->sc_ifp;
5856 struct ieee80211com *ic = ifp->if_l2com;
5857 struct ath_hal *ah = sc->sc_ah;
5861 * Collect channel set based on EEPROM contents.
5863 status = ath_hal_init_channels(ah, ic->ic_channels, IEEE80211_CHAN_MAX,
5864 &ic->ic_nchans, HAL_MODE_ALL, CTRY_DEFAULT, SKU_NONE, AH_TRUE);
5865 if (status != HAL_OK) {
5866 if_printf(ifp, "%s: unable to collect channel list from hal, "
5867 "status %d\n", __func__, status);
5870 (void) ath_hal_getregdomain(ah, &sc->sc_eerd);
5871 ath_hal_getcountrycode(ah, &sc->sc_eecc); /* NB: cannot fail */
5872 /* XXX map Atheros sku's to net80211 SKU's */
5873 /* XXX net80211 types too small */
5874 ic->ic_regdomain.regdomain = (uint16_t) sc->sc_eerd;
5875 ic->ic_regdomain.country = (uint16_t) sc->sc_eecc;
5876 ic->ic_regdomain.isocc[0] = ' '; /* XXX don't know */
5877 ic->ic_regdomain.isocc[1] = ' ';
5879 ic->ic_regdomain.ecm = 1;
5880 ic->ic_regdomain.location = 'I';
5882 DPRINTF(sc, ATH_DEBUG_REGDOMAIN,
5883 "%s: eeprom rd %u cc %u (mapped rd %u cc %u) location %c%s\n",
5884 __func__, sc->sc_eerd, sc->sc_eecc,
5885 ic->ic_regdomain.regdomain, ic->ic_regdomain.country,
5886 ic->ic_regdomain.location, ic->ic_regdomain.ecm ? " ecm" : "");
5891 ath_led_done(void *arg)
5893 struct ath_softc *sc = arg;
5895 sc->sc_blinking = 0;
5899 * Turn the LED off: flip the pin and then set a timer so no
5900 * update will happen for the specified duration.
5903 ath_led_off(void *arg)
5905 struct ath_softc *sc = arg;
5907 ath_hal_gpioset(sc->sc_ah, sc->sc_ledpin, !sc->sc_ledon);
5908 callout_reset(&sc->sc_ledtimer, sc->sc_ledoff, ath_led_done, sc);
5912 * Blink the LED according to the specified on/off times.
5915 ath_led_blink(struct ath_softc *sc, int on, int off)
5917 DPRINTF(sc, ATH_DEBUG_LED, "%s: on %u off %u\n", __func__, on, off);
5918 ath_hal_gpioset(sc->sc_ah, sc->sc_ledpin, sc->sc_ledon);
5919 sc->sc_blinking = 1;
5920 sc->sc_ledoff = off;
5921 callout_reset(&sc->sc_ledtimer, on, ath_led_off, sc);
5925 ath_led_event(struct ath_softc *sc, int rix)
5927 sc->sc_ledevent = ticks; /* time of last event */
5928 if (sc->sc_blinking) /* don't interrupt active blink */
5930 ath_led_blink(sc, sc->sc_hwmap[rix].ledon, sc->sc_hwmap[rix].ledoff);
5934 ath_rate_setup(struct ath_softc *sc, u_int mode)
5936 struct ath_hal *ah = sc->sc_ah;
5937 const HAL_RATE_TABLE *rt;
5940 case IEEE80211_MODE_11A:
5941 rt = ath_hal_getratetable(ah, HAL_MODE_11A);
5943 case IEEE80211_MODE_HALF:
5944 rt = ath_hal_getratetable(ah, HAL_MODE_11A_HALF_RATE);
5946 case IEEE80211_MODE_QUARTER:
5947 rt = ath_hal_getratetable(ah, HAL_MODE_11A_QUARTER_RATE);
5949 case IEEE80211_MODE_11B:
5950 rt = ath_hal_getratetable(ah, HAL_MODE_11B);
5952 case IEEE80211_MODE_11G:
5953 rt = ath_hal_getratetable(ah, HAL_MODE_11G);
5955 case IEEE80211_MODE_TURBO_A:
5956 rt = ath_hal_getratetable(ah, HAL_MODE_108A);
5958 case IEEE80211_MODE_TURBO_G:
5959 rt = ath_hal_getratetable(ah, HAL_MODE_108G);
5961 case IEEE80211_MODE_STURBO_A:
5962 rt = ath_hal_getratetable(ah, HAL_MODE_TURBO);
5964 case IEEE80211_MODE_11NA:
5965 rt = ath_hal_getratetable(ah, HAL_MODE_11NA_HT20);
5967 case IEEE80211_MODE_11NG:
5968 rt = ath_hal_getratetable(ah, HAL_MODE_11NG_HT20);
5971 DPRINTF(sc, ATH_DEBUG_ANY, "%s: invalid mode %u\n",
5975 sc->sc_rates[mode] = rt;
5976 return (rt != NULL);
5980 ath_setcurmode(struct ath_softc *sc, enum ieee80211_phymode mode)
5982 #define N(a) (sizeof(a)/sizeof(a[0]))
5983 /* NB: on/off times from the Atheros NDIS driver, w/ permission */
5984 static const struct {
5985 u_int rate; /* tx/rx 802.11 rate */
5986 u_int16_t timeOn; /* LED on time (ms) */
5987 u_int16_t timeOff; /* LED off time (ms) */
6003 /* XXX half/quarter rates */
6005 const HAL_RATE_TABLE *rt;
6008 memset(sc->sc_rixmap, 0xff, sizeof(sc->sc_rixmap));
6009 rt = sc->sc_rates[mode];
6010 KASSERT(rt != NULL, ("no h/w rate set for phy mode %u", mode));
6011 for (i = 0; i < rt->rateCount; i++) {
6012 uint8_t ieeerate = rt->info[i].dot11Rate & IEEE80211_RATE_VAL;
6013 if (rt->info[i].phy != IEEE80211_T_HT)
6014 sc->sc_rixmap[ieeerate] = i;
6016 sc->sc_rixmap[ieeerate | IEEE80211_RATE_MCS] = i;
6018 memset(sc->sc_hwmap, 0, sizeof(sc->sc_hwmap));
6019 for (i = 0; i < N(sc->sc_hwmap); i++) {
6020 if (i >= rt->rateCount) {
6021 sc->sc_hwmap[i].ledon = (500 * hz) / 1000;
6022 sc->sc_hwmap[i].ledoff = (130 * hz) / 1000;
6025 sc->sc_hwmap[i].ieeerate =
6026 rt->info[i].dot11Rate & IEEE80211_RATE_VAL;
6027 if (rt->info[i].phy == IEEE80211_T_HT)
6028 sc->sc_hwmap[i].ieeerate |= IEEE80211_RATE_MCS;
6029 sc->sc_hwmap[i].txflags = IEEE80211_RADIOTAP_F_DATAPAD;
6030 if (rt->info[i].shortPreamble ||
6031 rt->info[i].phy == IEEE80211_T_OFDM)
6032 sc->sc_hwmap[i].txflags |= IEEE80211_RADIOTAP_F_SHORTPRE;
6033 sc->sc_hwmap[i].rxflags = sc->sc_hwmap[i].txflags;
6034 for (j = 0; j < N(blinkrates)-1; j++)
6035 if (blinkrates[j].rate == sc->sc_hwmap[i].ieeerate)
6037 /* NB: this uses the last entry if the rate isn't found */
6038 /* XXX beware of overlow */
6039 sc->sc_hwmap[i].ledon = (blinkrates[j].timeOn * hz) / 1000;
6040 sc->sc_hwmap[i].ledoff = (blinkrates[j].timeOff * hz) / 1000;
6042 sc->sc_currates = rt;
6043 sc->sc_curmode = mode;
6045 * All protection frames are transmited at 2Mb/s for
6046 * 11g, otherwise at 1Mb/s.
6048 if (mode == IEEE80211_MODE_11G)
6049 sc->sc_protrix = ath_tx_findrix(sc, 2*2);
6051 sc->sc_protrix = ath_tx_findrix(sc, 2*1);
6052 /* NB: caller is responsible for reseting rate control state */
6058 ath_printrxbuf(struct ath_softc *sc, const struct ath_buf *bf,
6061 const struct ath_rx_status *rs = &bf->bf_status.ds_rxstat;
6062 struct ath_hal *ah = sc->sc_ah;
6063 const struct ath_desc *ds;
6066 for (i = 0, ds = bf->bf_desc; i < bf->bf_nseg; i++, ds++) {
6067 printf("R[%2u] (DS.V:%p DS.P:%p) L:%08x D:%08x%s\n"
6068 " %08x %08x %08x %08x\n",
6069 ix, ds, (const struct ath_desc *)bf->bf_daddr + i,
6070 ds->ds_link, ds->ds_data,
6071 !done ? "" : (rs->rs_status == 0) ? " *" : " !",
6072 ds->ds_ctl0, ds->ds_ctl1,
6073 ds->ds_hw[0], ds->ds_hw[1]);
6074 if (ah->ah_magic == 0x20065416) {
6075 printf(" %08x %08x %08x %08x %08x %08x %08x\n",
6076 ds->ds_hw[2], ds->ds_hw[3], ds->ds_hw[4],
6077 ds->ds_hw[5], ds->ds_hw[6], ds->ds_hw[7],
6084 ath_printtxbuf(struct ath_softc *sc, const struct ath_buf *bf,
6085 u_int qnum, u_int ix, int done)
6087 const struct ath_tx_status *ts = &bf->bf_status.ds_txstat;
6088 struct ath_hal *ah = sc->sc_ah;
6089 const struct ath_desc *ds;
6092 printf("Q%u[%3u]", qnum, ix);
6093 for (i = 0, ds = bf->bf_desc; i < bf->bf_nseg; i++, ds++) {
6094 printf(" (DS.V:%p DS.P:%p) L:%08x D:%08x F:04%x%s\n"
6095 " %08x %08x %08x %08x %08x %08x\n",
6096 ds, (const struct ath_desc *)bf->bf_daddr + i,
6097 ds->ds_link, ds->ds_data, bf->bf_txflags,
6098 !done ? "" : (ts->ts_status == 0) ? " *" : " !",
6099 ds->ds_ctl0, ds->ds_ctl1,
6100 ds->ds_hw[0], ds->ds_hw[1], ds->ds_hw[2], ds->ds_hw[3]);
6101 if (ah->ah_magic == 0x20065416) {
6102 printf(" %08x %08x %08x %08x %08x %08x %08x %08x\n",
6103 ds->ds_hw[4], ds->ds_hw[5], ds->ds_hw[6],
6104 ds->ds_hw[7], ds->ds_hw[8], ds->ds_hw[9],
6105 ds->ds_hw[10],ds->ds_hw[11]);
6106 printf(" %08x %08x %08x %08x %08x %08x %08x %08x\n",
6107 ds->ds_hw[12],ds->ds_hw[13],ds->ds_hw[14],
6108 ds->ds_hw[15],ds->ds_hw[16],ds->ds_hw[17],
6109 ds->ds_hw[18], ds->ds_hw[19]);
6113 #endif /* ATH_DEBUG */
6116 ath_watchdog(void *arg)
6118 struct ath_softc *sc = arg;
6120 if (sc->sc_wd_timer != 0 && --sc->sc_wd_timer == 0) {
6121 struct ifnet *ifp = sc->sc_ifp;
6124 if (ath_hal_gethangstate(sc->sc_ah, 0xffff, &hangs) &&
6126 if_printf(ifp, "%s hang detected (0x%x)\n",
6127 hangs & 0xff ? "bb" : "mac", hangs);
6129 if_printf(ifp, "device timeout\n");
6132 sc->sc_stats.ast_watchdog++;
6134 callout_schedule(&sc->sc_wd_ch, hz);
6139 * Diagnostic interface to the HAL. This is used by various
6140 * tools to do things like retrieve register contents for
6141 * debugging. The mechanism is intentionally opaque so that
6142 * it can change frequently w/o concern for compatiblity.
6145 ath_ioctl_diag(struct ath_softc *sc, struct ath_diag *ad)
6147 struct ath_hal *ah = sc->sc_ah;
6148 u_int id = ad->ad_id & ATH_DIAG_ID;
6149 void *indata = NULL;
6150 void *outdata = NULL;
6151 u_int32_t insize = ad->ad_in_size;
6152 u_int32_t outsize = ad->ad_out_size;
6155 if (ad->ad_id & ATH_DIAG_IN) {
6159 indata = malloc(insize, M_TEMP, M_NOWAIT);
6160 if (indata == NULL) {
6164 error = copyin(ad->ad_in_data, indata, insize);
6168 if (ad->ad_id & ATH_DIAG_DYN) {
6170 * Allocate a buffer for the results (otherwise the HAL
6171 * returns a pointer to a buffer where we can read the
6172 * results). Note that we depend on the HAL leaving this
6173 * pointer for us to use below in reclaiming the buffer;
6174 * may want to be more defensive.
6176 outdata = malloc(outsize, M_TEMP, M_NOWAIT);
6177 if (outdata == NULL) {
6182 if (ath_hal_getdiagstate(ah, id, indata, insize, &outdata, &outsize)) {
6183 if (outsize < ad->ad_out_size)
6184 ad->ad_out_size = outsize;
6185 if (outdata != NULL)
6186 error = copyout(outdata, ad->ad_out_data,
6192 if ((ad->ad_id & ATH_DIAG_IN) && indata != NULL)
6193 free(indata, M_TEMP);
6194 if ((ad->ad_id & ATH_DIAG_DYN) && outdata != NULL)
6195 free(outdata, M_TEMP);
6198 #endif /* ATH_DIAGAPI */
6201 ath_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
6203 #define IS_RUNNING(ifp) \
6204 ((ifp->if_flags & IFF_UP) && (ifp->if_drv_flags & IFF_DRV_RUNNING))
6205 struct ath_softc *sc = ifp->if_softc;
6206 struct ieee80211com *ic = ifp->if_l2com;
6207 struct ifreq *ifr = (struct ifreq *)data;
6208 const HAL_RATE_TABLE *rt;
6214 if (IS_RUNNING(ifp)) {
6216 * To avoid rescanning another access point,
6217 * do not call ath_init() here. Instead,
6218 * only reflect promisc mode settings.
6221 } else if (ifp->if_flags & IFF_UP) {
6223 * Beware of being called during attach/detach
6224 * to reset promiscuous mode. In that case we
6225 * will still be marked UP but not RUNNING.
6226 * However trying to re-init the interface
6227 * is the wrong thing to do as we've already
6228 * torn down much of our state. There's
6229 * probably a better way to deal with this.
6231 if (!sc->sc_invalid)
6232 ath_init(sc); /* XXX lose error */
6234 ath_stop_locked(ifp);
6236 /* XXX must wakeup in places like ath_vap_delete */
6237 if (!sc->sc_invalid)
6238 ath_hal_setpower(sc->sc_ah, HAL_PM_FULL_SLEEP);
6245 error = ifmedia_ioctl(ifp, ifr, &ic->ic_media, cmd);
6248 /* NB: embed these numbers to get a consistent view */
6249 sc->sc_stats.ast_tx_packets = ifp->if_opackets;
6250 sc->sc_stats.ast_rx_packets = ifp->if_ipackets;
6251 sc->sc_stats.ast_tx_rssi = ATH_RSSI(sc->sc_halstats.ns_avgtxrssi);
6252 sc->sc_stats.ast_rx_rssi = ATH_RSSI(sc->sc_halstats.ns_avgrssi);
6253 #ifdef IEEE80211_SUPPORT_TDMA
6254 sc->sc_stats.ast_tdma_tsfadjp = TDMA_AVG(sc->sc_avgtsfdeltap);
6255 sc->sc_stats.ast_tdma_tsfadjm = TDMA_AVG(sc->sc_avgtsfdeltam);
6257 rt = sc->sc_currates;
6259 sc->sc_stats.ast_tx_rate =
6260 rt->info[sc->sc_txrix].dot11Rate &~ IEEE80211_RATE_BASIC;
6261 return copyout(&sc->sc_stats,
6262 ifr->ifr_data, sizeof (sc->sc_stats));
6264 error = priv_check(curthread, PRIV_DRIVER);
6266 memset(&sc->sc_stats, 0, sizeof(sc->sc_stats));
6270 error = ath_ioctl_diag(sc, (struct ath_diag *) ifr);
6274 error = ether_ioctl(ifp, cmd, data);
6285 ath_sysctl_slottime(SYSCTL_HANDLER_ARGS)
6287 struct ath_softc *sc = arg1;
6288 u_int slottime = ath_hal_getslottime(sc->sc_ah);
6291 error = sysctl_handle_int(oidp, &slottime, 0, req);
6292 if (error || !req->newptr)
6294 return !ath_hal_setslottime(sc->sc_ah, slottime) ? EINVAL : 0;
6298 ath_sysctl_acktimeout(SYSCTL_HANDLER_ARGS)
6300 struct ath_softc *sc = arg1;
6301 u_int acktimeout = ath_hal_getacktimeout(sc->sc_ah);
6304 error = sysctl_handle_int(oidp, &acktimeout, 0, req);
6305 if (error || !req->newptr)
6307 return !ath_hal_setacktimeout(sc->sc_ah, acktimeout) ? EINVAL : 0;
6311 ath_sysctl_ctstimeout(SYSCTL_HANDLER_ARGS)
6313 struct ath_softc *sc = arg1;
6314 u_int ctstimeout = ath_hal_getctstimeout(sc->sc_ah);
6317 error = sysctl_handle_int(oidp, &ctstimeout, 0, req);
6318 if (error || !req->newptr)
6320 return !ath_hal_setctstimeout(sc->sc_ah, ctstimeout) ? EINVAL : 0;
6324 ath_sysctl_softled(SYSCTL_HANDLER_ARGS)
6326 struct ath_softc *sc = arg1;
6327 int softled = sc->sc_softled;
6330 error = sysctl_handle_int(oidp, &softled, 0, req);
6331 if (error || !req->newptr)
6333 softled = (softled != 0);
6334 if (softled != sc->sc_softled) {
6336 /* NB: handle any sc_ledpin change */
6337 ath_hal_gpioCfgOutput(sc->sc_ah, sc->sc_ledpin,
6338 HAL_GPIO_MUX_MAC_NETWORK_LED);
6339 ath_hal_gpioset(sc->sc_ah, sc->sc_ledpin,
6342 sc->sc_softled = softled;
6348 ath_sysctl_ledpin(SYSCTL_HANDLER_ARGS)
6350 struct ath_softc *sc = arg1;
6351 int ledpin = sc->sc_ledpin;
6354 error = sysctl_handle_int(oidp, &ledpin, 0, req);
6355 if (error || !req->newptr)
6357 if (ledpin != sc->sc_ledpin) {
6358 sc->sc_ledpin = ledpin;
6359 if (sc->sc_softled) {
6360 ath_hal_gpioCfgOutput(sc->sc_ah, sc->sc_ledpin,
6361 HAL_GPIO_MUX_MAC_NETWORK_LED);
6362 ath_hal_gpioset(sc->sc_ah, sc->sc_ledpin,
6370 ath_sysctl_txantenna(SYSCTL_HANDLER_ARGS)
6372 struct ath_softc *sc = arg1;
6373 u_int txantenna = ath_hal_getantennaswitch(sc->sc_ah);
6376 error = sysctl_handle_int(oidp, &txantenna, 0, req);
6377 if (!error && req->newptr) {
6378 /* XXX assumes 2 antenna ports */
6379 if (txantenna < HAL_ANT_VARIABLE || txantenna > HAL_ANT_FIXED_B)
6381 ath_hal_setantennaswitch(sc->sc_ah, txantenna);
6383 * NB: with the switch locked this isn't meaningful,
6384 * but set it anyway so things like radiotap get
6385 * consistent info in their data.
6387 sc->sc_txantenna = txantenna;
6393 ath_sysctl_rxantenna(SYSCTL_HANDLER_ARGS)
6395 struct ath_softc *sc = arg1;
6396 u_int defantenna = ath_hal_getdefantenna(sc->sc_ah);
6399 error = sysctl_handle_int(oidp, &defantenna, 0, req);
6400 if (!error && req->newptr)
6401 ath_hal_setdefantenna(sc->sc_ah, defantenna);
6406 ath_sysctl_diversity(SYSCTL_HANDLER_ARGS)
6408 struct ath_softc *sc = arg1;
6409 u_int diversity = ath_hal_getdiversity(sc->sc_ah);
6412 error = sysctl_handle_int(oidp, &diversity, 0, req);
6413 if (error || !req->newptr)
6415 if (!ath_hal_setdiversity(sc->sc_ah, diversity))
6417 sc->sc_diversity = diversity;
6422 ath_sysctl_diag(SYSCTL_HANDLER_ARGS)
6424 struct ath_softc *sc = arg1;
6428 if (!ath_hal_getdiag(sc->sc_ah, &diag))
6430 error = sysctl_handle_int(oidp, &diag, 0, req);
6431 if (error || !req->newptr)
6433 return !ath_hal_setdiag(sc->sc_ah, diag) ? EINVAL : 0;
6437 ath_sysctl_tpscale(SYSCTL_HANDLER_ARGS)
6439 struct ath_softc *sc = arg1;
6440 struct ifnet *ifp = sc->sc_ifp;
6444 (void) ath_hal_gettpscale(sc->sc_ah, &scale);
6445 error = sysctl_handle_int(oidp, &scale, 0, req);
6446 if (error || !req->newptr)
6448 return !ath_hal_settpscale(sc->sc_ah, scale) ? EINVAL :
6449 (ifp->if_drv_flags & IFF_DRV_RUNNING) ? ath_reset(ifp) : 0;
6453 ath_sysctl_tpc(SYSCTL_HANDLER_ARGS)
6455 struct ath_softc *sc = arg1;
6456 u_int tpc = ath_hal_gettpc(sc->sc_ah);
6459 error = sysctl_handle_int(oidp, &tpc, 0, req);
6460 if (error || !req->newptr)
6462 return !ath_hal_settpc(sc->sc_ah, tpc) ? EINVAL : 0;
6466 ath_sysctl_rfkill(SYSCTL_HANDLER_ARGS)
6468 struct ath_softc *sc = arg1;
6469 struct ifnet *ifp = sc->sc_ifp;
6470 struct ath_hal *ah = sc->sc_ah;
6471 u_int rfkill = ath_hal_getrfkill(ah);
6474 error = sysctl_handle_int(oidp, &rfkill, 0, req);
6475 if (error || !req->newptr)
6477 if (rfkill == ath_hal_getrfkill(ah)) /* unchanged */
6479 if (!ath_hal_setrfkill(ah, rfkill))
6481 return (ifp->if_drv_flags & IFF_DRV_RUNNING) ? ath_reset(ifp) : 0;
6485 ath_sysctl_rfsilent(SYSCTL_HANDLER_ARGS)
6487 struct ath_softc *sc = arg1;
6491 (void) ath_hal_getrfsilent(sc->sc_ah, &rfsilent);
6492 error = sysctl_handle_int(oidp, &rfsilent, 0, req);
6493 if (error || !req->newptr)
6495 if (!ath_hal_setrfsilent(sc->sc_ah, rfsilent))
6497 sc->sc_rfsilentpin = rfsilent & 0x1c;
6498 sc->sc_rfsilentpol = (rfsilent & 0x2) != 0;
6503 ath_sysctl_tpack(SYSCTL_HANDLER_ARGS)
6505 struct ath_softc *sc = arg1;
6509 (void) ath_hal_gettpack(sc->sc_ah, &tpack);
6510 error = sysctl_handle_int(oidp, &tpack, 0, req);
6511 if (error || !req->newptr)
6513 return !ath_hal_settpack(sc->sc_ah, tpack) ? EINVAL : 0;
6517 ath_sysctl_tpcts(SYSCTL_HANDLER_ARGS)
6519 struct ath_softc *sc = arg1;
6523 (void) ath_hal_gettpcts(sc->sc_ah, &tpcts);
6524 error = sysctl_handle_int(oidp, &tpcts, 0, req);
6525 if (error || !req->newptr)
6527 return !ath_hal_settpcts(sc->sc_ah, tpcts) ? EINVAL : 0;
6531 ath_sysctl_intmit(SYSCTL_HANDLER_ARGS)
6533 struct ath_softc *sc = arg1;
6536 intmit = ath_hal_getintmit(sc->sc_ah);
6537 error = sysctl_handle_int(oidp, &intmit, 0, req);
6538 if (error || !req->newptr)
6540 return !ath_hal_setintmit(sc->sc_ah, intmit) ? EINVAL : 0;
6543 #ifdef IEEE80211_SUPPORT_TDMA
6545 ath_sysctl_setcca(SYSCTL_HANDLER_ARGS)
6547 struct ath_softc *sc = arg1;
6550 setcca = sc->sc_setcca;
6551 error = sysctl_handle_int(oidp, &setcca, 0, req);
6552 if (error || !req->newptr)
6554 sc->sc_setcca = (setcca != 0);
6557 #endif /* IEEE80211_SUPPORT_TDMA */
6560 ath_sysctlattach(struct ath_softc *sc)
6562 struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(sc->sc_dev);
6563 struct sysctl_oid *tree = device_get_sysctl_tree(sc->sc_dev);
6564 struct ath_hal *ah = sc->sc_ah;
6566 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
6567 "countrycode", CTLFLAG_RD, &sc->sc_eecc, 0,
6568 "EEPROM country code");
6569 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
6570 "regdomain", CTLFLAG_RD, &sc->sc_eerd, 0,
6571 "EEPROM regdomain code");
6573 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
6574 "debug", CTLFLAG_RW, &sc->sc_debug, 0,
6575 "control debugging printfs");
6577 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
6578 "slottime", CTLTYPE_INT | CTLFLAG_RW, sc, 0,
6579 ath_sysctl_slottime, "I", "802.11 slot time (us)");
6580 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
6581 "acktimeout", CTLTYPE_INT | CTLFLAG_RW, sc, 0,
6582 ath_sysctl_acktimeout, "I", "802.11 ACK timeout (us)");
6583 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
6584 "ctstimeout", CTLTYPE_INT | CTLFLAG_RW, sc, 0,
6585 ath_sysctl_ctstimeout, "I", "802.11 CTS timeout (us)");
6586 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
6587 "softled", CTLTYPE_INT | CTLFLAG_RW, sc, 0,
6588 ath_sysctl_softled, "I", "enable/disable software LED support");
6589 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
6590 "ledpin", CTLTYPE_INT | CTLFLAG_RW, sc, 0,
6591 ath_sysctl_ledpin, "I", "GPIO pin connected to LED");
6592 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
6593 "ledon", CTLFLAG_RW, &sc->sc_ledon, 0,
6594 "setting to turn LED on");
6595 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
6596 "ledidle", CTLFLAG_RW, &sc->sc_ledidle, 0,
6597 "idle time for inactivity LED (ticks)");
6598 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
6599 "txantenna", CTLTYPE_INT | CTLFLAG_RW, sc, 0,
6600 ath_sysctl_txantenna, "I", "antenna switch");
6601 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
6602 "rxantenna", CTLTYPE_INT | CTLFLAG_RW, sc, 0,
6603 ath_sysctl_rxantenna, "I", "default/rx antenna");
6604 if (ath_hal_hasdiversity(ah))
6605 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
6606 "diversity", CTLTYPE_INT | CTLFLAG_RW, sc, 0,
6607 ath_sysctl_diversity, "I", "antenna diversity");
6608 sc->sc_txintrperiod = ATH_TXINTR_PERIOD;
6609 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
6610 "txintrperiod", CTLFLAG_RW, &sc->sc_txintrperiod, 0,
6611 "tx descriptor batching");
6612 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
6613 "diag", CTLTYPE_INT | CTLFLAG_RW, sc, 0,
6614 ath_sysctl_diag, "I", "h/w diagnostic control");
6615 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
6616 "tpscale", CTLTYPE_INT | CTLFLAG_RW, sc, 0,
6617 ath_sysctl_tpscale, "I", "tx power scaling");
6618 if (ath_hal_hastpc(ah)) {
6619 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
6620 "tpc", CTLTYPE_INT | CTLFLAG_RW, sc, 0,
6621 ath_sysctl_tpc, "I", "enable/disable per-packet TPC");
6622 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
6623 "tpack", CTLTYPE_INT | CTLFLAG_RW, sc, 0,
6624 ath_sysctl_tpack, "I", "tx power for ack frames");
6625 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
6626 "tpcts", CTLTYPE_INT | CTLFLAG_RW, sc, 0,
6627 ath_sysctl_tpcts, "I", "tx power for cts frames");
6629 if (ath_hal_hasrfsilent(ah)) {
6630 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
6631 "rfsilent", CTLTYPE_INT | CTLFLAG_RW, sc, 0,
6632 ath_sysctl_rfsilent, "I", "h/w RF silent config");
6633 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
6634 "rfkill", CTLTYPE_INT | CTLFLAG_RW, sc, 0,
6635 ath_sysctl_rfkill, "I", "enable/disable RF kill switch");
6637 if (ath_hal_hasintmit(ah)) {
6638 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
6639 "intmit", CTLTYPE_INT | CTLFLAG_RW, sc, 0,
6640 ath_sysctl_intmit, "I", "interference mitigation");
6642 sc->sc_monpass = HAL_RXERR_DECRYPT | HAL_RXERR_MIC;
6643 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
6644 "monpass", CTLFLAG_RW, &sc->sc_monpass, 0,
6645 "mask of error frames to pass when monitoring");
6646 #ifdef IEEE80211_SUPPORT_TDMA
6647 if (ath_hal_macversion(ah) > 0x78) {
6648 sc->sc_tdmadbaprep = 2;
6649 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
6650 "dbaprep", CTLFLAG_RW, &sc->sc_tdmadbaprep, 0,
6651 "TDMA DBA preparation time");
6652 sc->sc_tdmaswbaprep = 10;
6653 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
6654 "swbaprep", CTLFLAG_RW, &sc->sc_tdmaswbaprep, 0,
6655 "TDMA SWBA preparation time");
6656 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
6657 "guardtime", CTLFLAG_RW, &sc->sc_tdmaguard, 0,
6658 "TDMA slot guard time");
6659 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
6660 "superframe", CTLFLAG_RD, &sc->sc_tdmabintval, 0,
6661 "TDMA calculated super frame");
6662 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
6663 "setcca", CTLTYPE_INT | CTLFLAG_RW, sc, 0,
6664 ath_sysctl_setcca, "I", "enable CCA control");
6670 ath_tx_raw_start(struct ath_softc *sc, struct ieee80211_node *ni,
6671 struct ath_buf *bf, struct mbuf *m0,
6672 const struct ieee80211_bpf_params *params)
6674 struct ifnet *ifp = sc->sc_ifp;
6675 struct ieee80211com *ic = ifp->if_l2com;
6676 struct ath_hal *ah = sc->sc_ah;
6677 struct ieee80211vap *vap = ni->ni_vap;
6678 int error, ismcast, ismrr;
6679 int keyix, hdrlen, pktlen, try0, txantenna;
6680 u_int8_t rix, cix, txrate, ctsrate, rate1, rate2, rate3;
6681 struct ieee80211_frame *wh;
6682 u_int flags, ctsduration;
6684 const HAL_RATE_TABLE *rt;
6685 struct ath_desc *ds;
6688 wh = mtod(m0, struct ieee80211_frame *);
6689 ismcast = IEEE80211_IS_MULTICAST(wh->i_addr1);
6690 hdrlen = ieee80211_anyhdrsize(wh);
6692 * Packet length must not include any
6693 * pad bytes; deduct them here.
6695 /* XXX honor IEEE80211_BPF_DATAPAD */
6696 pktlen = m0->m_pkthdr.len - (hdrlen & 3) + IEEE80211_CRC_LEN;
6698 if (params->ibp_flags & IEEE80211_BPF_CRYPTO) {
6699 const struct ieee80211_cipher *cip;
6700 struct ieee80211_key *k;
6703 * Construct the 802.11 header+trailer for an encrypted
6704 * frame. The only reason this can fail is because of an
6705 * unknown or unsupported cipher/key type.
6707 k = ieee80211_crypto_encap(ni, m0);
6710 * This can happen when the key is yanked after the
6711 * frame was queued. Just discard the frame; the
6712 * 802.11 layer counts failures and provides
6713 * debugging/diagnostics.
6719 * Adjust the packet + header lengths for the crypto
6720 * additions and calculate the h/w key index. When
6721 * a s/w mic is done the frame will have had any mic
6722 * added to it prior to entry so m0->m_pkthdr.len will
6723 * account for it. Otherwise we need to add it to the
6727 hdrlen += cip->ic_header;
6728 pktlen += cip->ic_header + cip->ic_trailer;
6729 /* NB: frags always have any TKIP MIC done in s/w */
6730 if ((k->wk_flags & IEEE80211_KEY_SWMIC) == 0)
6731 pktlen += cip->ic_miclen;
6732 keyix = k->wk_keyix;
6734 /* packet header may have moved, reset our local pointer */
6735 wh = mtod(m0, struct ieee80211_frame *);
6736 } else if (ni->ni_ucastkey.wk_cipher == &ieee80211_cipher_none) {
6738 * Use station key cache slot, if assigned.
6740 keyix = ni->ni_ucastkey.wk_keyix;
6741 if (keyix == IEEE80211_KEYIX_NONE)
6742 keyix = HAL_TXKEYIX_INVALID;
6744 keyix = HAL_TXKEYIX_INVALID;
6746 error = ath_tx_dmasetup(sc, bf, m0);
6749 m0 = bf->bf_m; /* NB: may have changed */
6750 wh = mtod(m0, struct ieee80211_frame *);
6751 bf->bf_node = ni; /* NB: held reference */
6753 flags = HAL_TXDESC_CLRDMASK; /* XXX needed for crypto errs */
6754 flags |= HAL_TXDESC_INTREQ; /* force interrupt */
6755 if (params->ibp_flags & IEEE80211_BPF_RTS)
6756 flags |= HAL_TXDESC_RTSENA;
6757 else if (params->ibp_flags & IEEE80211_BPF_CTS)
6758 flags |= HAL_TXDESC_CTSENA;
6759 /* XXX leave ismcast to injector? */
6760 if ((params->ibp_flags & IEEE80211_BPF_NOACK) || ismcast)
6761 flags |= HAL_TXDESC_NOACK;
6763 rt = sc->sc_currates;
6764 KASSERT(rt != NULL, ("no rate table, mode %u", sc->sc_curmode));
6765 rix = ath_tx_findrix(sc, params->ibp_rate0);
6766 txrate = rt->info[rix].rateCode;
6767 if (params->ibp_flags & IEEE80211_BPF_SHORTPRE)
6768 txrate |= rt->info[rix].shortPreamble;
6770 try0 = params->ibp_try0;
6771 ismrr = (params->ibp_try1 != 0);
6772 txantenna = params->ibp_pri >> 2;
6773 if (txantenna == 0) /* XXX? */
6774 txantenna = sc->sc_txantenna;
6776 if (flags & (HAL_TXDESC_CTSENA | HAL_TXDESC_RTSENA)) {
6777 cix = ath_tx_findrix(sc, params->ibp_ctsrate);
6778 ctsrate = rt->info[cix].rateCode;
6779 if (params->ibp_flags & IEEE80211_BPF_SHORTPRE) {
6780 ctsrate |= rt->info[cix].shortPreamble;
6781 if (flags & HAL_TXDESC_RTSENA) /* SIFS + CTS */
6782 ctsduration += rt->info[cix].spAckDuration;
6783 ctsduration += ath_hal_computetxtime(ah,
6784 rt, pktlen, rix, AH_TRUE);
6785 if ((flags & HAL_TXDESC_NOACK) == 0) /* SIFS + ACK */
6786 ctsduration += rt->info[rix].spAckDuration;
6788 if (flags & HAL_TXDESC_RTSENA) /* SIFS + CTS */
6789 ctsduration += rt->info[cix].lpAckDuration;
6790 ctsduration += ath_hal_computetxtime(ah,
6791 rt, pktlen, rix, AH_FALSE);
6792 if ((flags & HAL_TXDESC_NOACK) == 0) /* SIFS + ACK */
6793 ctsduration += rt->info[rix].lpAckDuration;
6795 ismrr = 0; /* XXX */
6798 pri = params->ibp_pri & 3;
6800 * NB: we mark all packets as type PSPOLL so the h/w won't
6801 * set the sequence number, duration, etc.
6803 atype = HAL_PKT_TYPE_PSPOLL;
6805 if (IFF_DUMPPKTS(sc, ATH_DEBUG_XMIT))
6806 ieee80211_dump_pkt(ic, mtod(m0, caddr_t), m0->m_len,
6807 sc->sc_hwmap[rix].ieeerate, -1);
6809 if (ieee80211_radiotap_active_vap(vap)) {
6810 u_int64_t tsf = ath_hal_gettsf64(ah);
6812 sc->sc_tx_th.wt_tsf = htole64(tsf);
6813 sc->sc_tx_th.wt_flags = sc->sc_hwmap[rix].txflags;
6814 if (wh->i_fc[1] & IEEE80211_FC1_WEP)
6815 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_WEP;
6816 if (m0->m_flags & M_FRAG)
6817 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_FRAG;
6818 sc->sc_tx_th.wt_rate = sc->sc_hwmap[rix].ieeerate;
6819 sc->sc_tx_th.wt_txpower = ni->ni_txpower;
6820 sc->sc_tx_th.wt_antenna = sc->sc_txantenna;
6822 ieee80211_radiotap_tx(vap, m0);
6826 * Formulate first tx descriptor with tx controls.
6829 /* XXX check return value? */
6830 ath_hal_setuptxdesc(ah, ds
6831 , pktlen /* packet length */
6832 , hdrlen /* header length */
6833 , atype /* Atheros packet type */
6834 , params->ibp_power /* txpower */
6835 , txrate, try0 /* series 0 rate/tries */
6836 , keyix /* key cache index */
6837 , txantenna /* antenna mode */
6839 , ctsrate /* rts/cts rate */
6840 , ctsduration /* rts/cts duration */
6842 bf->bf_txflags = flags;
6845 rix = ath_tx_findrix(sc, params->ibp_rate1);
6846 rate1 = rt->info[rix].rateCode;
6847 if (params->ibp_flags & IEEE80211_BPF_SHORTPRE)
6848 rate1 |= rt->info[rix].shortPreamble;
6849 if (params->ibp_try2) {
6850 rix = ath_tx_findrix(sc, params->ibp_rate2);
6851 rate2 = rt->info[rix].rateCode;
6852 if (params->ibp_flags & IEEE80211_BPF_SHORTPRE)
6853 rate2 |= rt->info[rix].shortPreamble;
6856 if (params->ibp_try3) {
6857 rix = ath_tx_findrix(sc, params->ibp_rate3);
6858 rate3 = rt->info[rix].rateCode;
6859 if (params->ibp_flags & IEEE80211_BPF_SHORTPRE)
6860 rate3 |= rt->info[rix].shortPreamble;
6863 ath_hal_setupxtxdesc(ah, ds
6864 , rate1, params->ibp_try1 /* series 1 */
6865 , rate2, params->ibp_try2 /* series 2 */
6866 , rate3, params->ibp_try3 /* series 3 */
6870 /* NB: no buffered multicast in power save support */
6871 ath_tx_handoff(sc, sc->sc_ac2q[pri], bf);
6876 ath_raw_xmit(struct ieee80211_node *ni, struct mbuf *m,
6877 const struct ieee80211_bpf_params *params)
6879 struct ieee80211com *ic = ni->ni_ic;
6880 struct ifnet *ifp = ic->ic_ifp;
6881 struct ath_softc *sc = ifp->if_softc;
6885 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 || sc->sc_invalid) {
6886 DPRINTF(sc, ATH_DEBUG_XMIT, "%s: discard frame, %s", __func__,
6887 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 ?
6888 "!running" : "invalid");
6894 * Grab a TX buffer and associated resources.
6896 bf = ath_getbuf(sc);
6898 sc->sc_stats.ast_tx_nobuf++;
6904 if (params == NULL) {
6906 * Legacy path; interpret frame contents to decide
6907 * precisely how to send the frame.
6909 if (ath_tx_start(sc, ni, bf, m)) {
6910 error = EIO; /* XXX */
6915 * Caller supplied explicit parameters to use in
6916 * sending the frame.
6918 if (ath_tx_raw_start(sc, ni, bf, m, params)) {
6919 error = EIO; /* XXX */
6923 sc->sc_wd_timer = 5;
6925 sc->sc_stats.ast_tx_raw++;
6930 STAILQ_INSERT_HEAD(&sc->sc_txbuf, bf, bf_list);
6931 ATH_TXBUF_UNLOCK(sc);
6934 sc->sc_stats.ast_tx_raw_fail++;
6935 ieee80211_free_node(ni);
6940 * Announce various information on device/driver attach.
6943 ath_announce(struct ath_softc *sc)
6945 struct ifnet *ifp = sc->sc_ifp;
6946 struct ath_hal *ah = sc->sc_ah;
6948 if_printf(ifp, "AR%s mac %d.%d RF%s phy %d.%d\n",
6949 ath_hal_mac_name(ah), ah->ah_macVersion, ah->ah_macRev,
6950 ath_hal_rf_name(ah), ah->ah_phyRev >> 4, ah->ah_phyRev & 0xf);
6953 for (i = 0; i <= WME_AC_VO; i++) {
6954 struct ath_txq *txq = sc->sc_ac2q[i];
6955 if_printf(ifp, "Use hw queue %u for %s traffic\n",
6956 txq->axq_qnum, ieee80211_wme_acnames[i]);
6958 if_printf(ifp, "Use hw queue %u for CAB traffic\n",
6959 sc->sc_cabq->axq_qnum);
6960 if_printf(ifp, "Use hw queue %u for beacons\n", sc->sc_bhalq);
6962 if (ath_rxbuf != ATH_RXBUF)
6963 if_printf(ifp, "using %u rx buffers\n", ath_rxbuf);
6964 if (ath_txbuf != ATH_TXBUF)
6965 if_printf(ifp, "using %u tx buffers\n", ath_txbuf);
6966 if (sc->sc_mcastkey && bootverbose)
6967 if_printf(ifp, "using multicast key search\n");
6970 #ifdef IEEE80211_SUPPORT_TDMA
6971 static __inline uint32_t
6972 ath_hal_getnexttbtt(struct ath_hal *ah)
6974 #define AR_TIMER0 0x8028
6975 return OS_REG_READ(ah, AR_TIMER0);
6978 static __inline void
6979 ath_hal_adjusttsf(struct ath_hal *ah, int32_t tsfdelta)
6981 /* XXX handle wrap/overflow */
6982 OS_REG_WRITE(ah, AR_TSF_L32, OS_REG_READ(ah, AR_TSF_L32) + tsfdelta);
6986 ath_tdma_settimers(struct ath_softc *sc, u_int32_t nexttbtt, u_int32_t bintval)
6988 struct ath_hal *ah = sc->sc_ah;
6989 HAL_BEACON_TIMERS bt;
6991 bt.bt_intval = bintval | HAL_BEACON_ENA;
6992 bt.bt_nexttbtt = nexttbtt;
6993 bt.bt_nextdba = (nexttbtt<<3) - sc->sc_tdmadbaprep;
6994 bt.bt_nextswba = (nexttbtt<<3) - sc->sc_tdmaswbaprep;
6995 bt.bt_nextatim = nexttbtt+1;
6996 ath_hal_beaconsettimers(ah, &bt);
7000 * Calculate the beacon interval. This is periodic in the
7001 * superframe for the bss. We assume each station is configured
7002 * identically wrt transmit rate so the guard time we calculate
7003 * above will be the same on all stations. Note we need to
7004 * factor in the xmit time because the hardware will schedule
7005 * a frame for transmit if the start of the frame is within
7006 * the burst time. When we get hardware that properly kills
7007 * frames in the PCU we can reduce/eliminate the guard time.
7009 * Roundup to 1024 is so we have 1 TU buffer in the guard time
7010 * to deal with the granularity of the nexttbtt timer. 11n MAC's
7011 * with 1us timer granularity should allow us to reduce/eliminate
7015 ath_tdma_bintvalsetup(struct ath_softc *sc,
7016 const struct ieee80211_tdma_state *tdma)
7018 /* copy from vap state (XXX check all vaps have same value?) */
7019 sc->sc_tdmaslotlen = tdma->tdma_slotlen;
7021 sc->sc_tdmabintval = roundup((sc->sc_tdmaslotlen+sc->sc_tdmaguard) *
7022 tdma->tdma_slotcnt, 1024);
7023 sc->sc_tdmabintval >>= 10; /* TSF -> TU */
7024 if (sc->sc_tdmabintval & 1)
7025 sc->sc_tdmabintval++;
7027 if (tdma->tdma_slot == 0) {
7029 * Only slot 0 beacons; other slots respond.
7031 sc->sc_imask |= HAL_INT_SWBA;
7032 sc->sc_tdmaswba = 0; /* beacon immediately */
7034 /* XXX all vaps must be slot 0 or slot !0 */
7035 sc->sc_imask &= ~HAL_INT_SWBA;
7040 * Max 802.11 overhead. This assumes no 4-address frames and
7041 * the encapsulation done by ieee80211_encap (llc). We also
7042 * include potential crypto overhead.
7044 #define IEEE80211_MAXOVERHEAD \
7045 (sizeof(struct ieee80211_qosframe) \
7046 + sizeof(struct llc) \
7047 + IEEE80211_ADDR_LEN \
7048 + IEEE80211_WEP_IVLEN \
7049 + IEEE80211_WEP_KIDLEN \
7050 + IEEE80211_WEP_CRCLEN \
7051 + IEEE80211_WEP_MICLEN \
7052 + IEEE80211_CRC_LEN)
7055 * Setup initially for tdma operation. Start the beacon
7056 * timers and enable SWBA if we are slot 0. Otherwise
7057 * we wait for slot 0 to arrive so we can sync up before
7058 * starting to transmit.
7061 ath_tdma_config(struct ath_softc *sc, struct ieee80211vap *vap)
7063 struct ath_hal *ah = sc->sc_ah;
7064 struct ifnet *ifp = sc->sc_ifp;
7065 struct ieee80211com *ic = ifp->if_l2com;
7066 const struct ieee80211_txparam *tp;
7067 const struct ieee80211_tdma_state *tdma = NULL;
7071 vap = TAILQ_FIRST(&ic->ic_vaps); /* XXX */
7073 if_printf(ifp, "%s: no vaps?\n", __func__);
7077 tp = vap->iv_bss->ni_txparms;
7079 * Calculate the guard time for each slot. This is the
7080 * time to send a maximal-size frame according to the
7081 * fixed/lowest transmit rate. Note that the interface
7082 * mtu does not include the 802.11 overhead so we must
7083 * tack that on (ath_hal_computetxtime includes the
7084 * preamble and plcp in it's calculation).
7086 tdma = vap->iv_tdma;
7087 if (tp->ucastrate != IEEE80211_FIXED_RATE_NONE)
7088 rix = ath_tx_findrix(sc, tp->ucastrate);
7090 rix = ath_tx_findrix(sc, tp->mcastrate);
7091 /* XXX short preamble assumed */
7092 sc->sc_tdmaguard = ath_hal_computetxtime(ah, sc->sc_currates,
7093 ifp->if_mtu + IEEE80211_MAXOVERHEAD, rix, AH_TRUE);
7095 ath_hal_intrset(ah, 0);
7097 ath_beaconq_config(sc); /* setup h/w beacon q */
7099 ath_hal_setcca(ah, AH_FALSE); /* disable CCA */
7100 ath_tdma_bintvalsetup(sc, tdma); /* calculate beacon interval */
7101 ath_tdma_settimers(sc, sc->sc_tdmabintval,
7102 sc->sc_tdmabintval | HAL_BEACON_RESET_TSF);
7103 sc->sc_syncbeacon = 0;
7105 sc->sc_avgtsfdeltap = TDMA_DUMMY_MARKER;
7106 sc->sc_avgtsfdeltam = TDMA_DUMMY_MARKER;
7108 ath_hal_intrset(ah, sc->sc_imask);
7110 DPRINTF(sc, ATH_DEBUG_TDMA, "%s: slot %u len %uus cnt %u "
7111 "bsched %u guard %uus bintval %u TU dba prep %u\n", __func__,
7112 tdma->tdma_slot, tdma->tdma_slotlen, tdma->tdma_slotcnt,
7113 tdma->tdma_bintval, sc->sc_tdmaguard, sc->sc_tdmabintval,
7114 sc->sc_tdmadbaprep);
7118 * Update tdma operation. Called from the 802.11 layer
7119 * when a beacon is received from the TDMA station operating
7120 * in the slot immediately preceding us in the bss. Use
7121 * the rx timestamp for the beacon frame to update our
7122 * beacon timers so we follow their schedule. Note that
7123 * by using the rx timestamp we implicitly include the
7124 * propagation delay in our schedule.
7127 ath_tdma_update(struct ieee80211_node *ni,
7128 const struct ieee80211_tdma_param *tdma, int changed)
7130 #define TSF_TO_TU(_h,_l) \
7131 ((((u_int32_t)(_h)) << 22) | (((u_int32_t)(_l)) >> 10))
7132 #define TU_TO_TSF(_tu) (((u_int64_t)(_tu)) << 10)
7133 struct ieee80211vap *vap = ni->ni_vap;
7134 struct ieee80211com *ic = ni->ni_ic;
7135 struct ath_softc *sc = ic->ic_ifp->if_softc;
7136 struct ath_hal *ah = sc->sc_ah;
7137 const HAL_RATE_TABLE *rt = sc->sc_currates;
7138 u_int64_t tsf, rstamp, nextslot;
7139 u_int32_t txtime, nextslottu, timer0;
7140 int32_t tudelta, tsfdelta;
7141 const struct ath_rx_status *rs;
7144 sc->sc_stats.ast_tdma_update++;
7147 * Check for and adopt configuration changes.
7150 const struct ieee80211_tdma_state *ts = vap->iv_tdma;
7152 ath_tdma_bintvalsetup(sc, ts);
7153 if (changed & TDMA_UPDATE_SLOTLEN)
7156 DPRINTF(sc, ATH_DEBUG_TDMA,
7157 "%s: adopt slot %u slotcnt %u slotlen %u us "
7158 "bintval %u TU\n", __func__,
7159 ts->tdma_slot, ts->tdma_slotcnt, ts->tdma_slotlen,
7160 sc->sc_tdmabintval);
7163 ath_hal_intrset(ah, sc->sc_imask);
7164 /* NB: beacon timers programmed below */
7167 /* extend rx timestamp to 64 bits */
7169 tsf = ath_hal_gettsf64(ah);
7170 rstamp = ath_extend_tsf(rs->rs_tstamp, tsf);
7172 * The rx timestamp is set by the hardware on completing
7173 * reception (at the point where the rx descriptor is DMA'd
7174 * to the host). To find the start of our next slot we
7175 * must adjust this time by the time required to send
7176 * the packet just received.
7178 rix = rt->rateCodeToIndex[rs->rs_rate];
7179 txtime = ath_hal_computetxtime(ah, rt, rs->rs_datalen, rix,
7180 rt->info[rix].shortPreamble);
7181 /* NB: << 9 is to cvt to TU and /2 */
7182 nextslot = (rstamp - txtime) + (sc->sc_tdmabintval << 9);
7183 nextslottu = TSF_TO_TU(nextslot>>32, nextslot) & HAL_BEACON_PERIOD;
7186 * TIMER0 is the h/w's idea of NextTBTT (in TU's). Convert
7187 * to usecs and calculate the difference between what the
7188 * other station thinks and what we have programmed. This
7189 * lets us figure how to adjust our timers to match. The
7190 * adjustments are done by pulling the TSF forward and possibly
7191 * rewriting the beacon timers.
7193 timer0 = ath_hal_getnexttbtt(ah);
7194 tsfdelta = (int32_t)((nextslot % TU_TO_TSF(HAL_BEACON_PERIOD+1)) - TU_TO_TSF(timer0));
7196 DPRINTF(sc, ATH_DEBUG_TDMA_TIMER,
7197 "tsfdelta %d avg +%d/-%d\n", tsfdelta,
7198 TDMA_AVG(sc->sc_avgtsfdeltap), TDMA_AVG(sc->sc_avgtsfdeltam));
7201 TDMA_SAMPLE(sc->sc_avgtsfdeltap, 0);
7202 TDMA_SAMPLE(sc->sc_avgtsfdeltam, -tsfdelta);
7203 tsfdelta = -tsfdelta % 1024;
7205 } else if (tsfdelta > 0) {
7206 TDMA_SAMPLE(sc->sc_avgtsfdeltap, tsfdelta);
7207 TDMA_SAMPLE(sc->sc_avgtsfdeltam, 0);
7208 tsfdelta = 1024 - (tsfdelta % 1024);
7211 TDMA_SAMPLE(sc->sc_avgtsfdeltap, 0);
7212 TDMA_SAMPLE(sc->sc_avgtsfdeltam, 0);
7214 tudelta = nextslottu - timer0;
7217 * Copy sender's timetstamp into tdma ie so they can
7218 * calculate roundtrip time. We submit a beacon frame
7219 * below after any timer adjustment. The frame goes out
7220 * at the next TBTT so the sender can calculate the
7221 * roundtrip by inspecting the tdma ie in our beacon frame.
7223 * NB: This tstamp is subtlely preserved when
7224 * IEEE80211_BEACON_TDMA is marked (e.g. when the
7225 * slot position changes) because ieee80211_add_tdma
7226 * skips over the data.
7228 memcpy(ATH_VAP(vap)->av_boff.bo_tdma +
7229 __offsetof(struct ieee80211_tdma_param, tdma_tstamp),
7230 &ni->ni_tstamp.data, 8);
7232 DPRINTF(sc, ATH_DEBUG_TDMA_TIMER,
7233 "tsf %llu nextslot %llu (%d, %d) nextslottu %u timer0 %u (%d)\n",
7234 (unsigned long long) tsf, (unsigned long long) nextslot,
7235 (int)(nextslot - tsf), tsfdelta,
7236 nextslottu, timer0, tudelta);
7239 * Adjust the beacon timers only when pulling them forward
7240 * or when going back by less than the beacon interval.
7241 * Negative jumps larger than the beacon interval seem to
7242 * cause the timers to stop and generally cause instability.
7243 * This basically filters out jumps due to missed beacons.
7245 if (tudelta != 0 && (tudelta > 0 || -tudelta < sc->sc_tdmabintval)) {
7246 ath_tdma_settimers(sc, nextslottu, sc->sc_tdmabintval);
7247 sc->sc_stats.ast_tdma_timers++;
7250 ath_hal_adjusttsf(ah, tsfdelta);
7251 sc->sc_stats.ast_tdma_tsf++;
7253 ath_tdma_beacon_send(sc, vap); /* prepare response */
7259 * Transmit a beacon frame at SWBA. Dynamic updates
7260 * to the frame contents are done as needed.
7263 ath_tdma_beacon_send(struct ath_softc *sc, struct ieee80211vap *vap)
7265 struct ath_hal *ah = sc->sc_ah;
7270 * Check if the previous beacon has gone out. If
7271 * not don't try to post another, skip this period
7272 * and wait for the next. Missed beacons indicate
7273 * a problem and should not occur. If we miss too
7274 * many consecutive beacons reset the device.
7276 if (ath_hal_numtxpending(ah, sc->sc_bhalq) != 0) {
7277 sc->sc_bmisscount++;
7278 DPRINTF(sc, ATH_DEBUG_BEACON,
7279 "%s: missed %u consecutive beacons\n",
7280 __func__, sc->sc_bmisscount);
7281 if (sc->sc_bmisscount >= ath_bstuck_threshold)
7282 taskqueue_enqueue(sc->sc_tq, &sc->sc_bstucktask);
7285 if (sc->sc_bmisscount != 0) {
7286 DPRINTF(sc, ATH_DEBUG_BEACON,
7287 "%s: resume beacon xmit after %u misses\n",
7288 __func__, sc->sc_bmisscount);
7289 sc->sc_bmisscount = 0;
7293 * Check recent per-antenna transmit statistics and flip
7294 * the default antenna if noticeably more frames went out
7295 * on the non-default antenna.
7296 * XXX assumes 2 anntenae
7298 if (!sc->sc_diversity) {
7299 otherant = sc->sc_defant & 1 ? 2 : 1;
7300 if (sc->sc_ant_tx[otherant] > sc->sc_ant_tx[sc->sc_defant] + 2)
7301 ath_setdefantenna(sc, otherant);
7302 sc->sc_ant_tx[1] = sc->sc_ant_tx[2] = 0;
7305 bf = ath_beacon_generate(sc, vap);
7308 * Stop any current dma and put the new frame on the queue.
7309 * This should never fail since we check above that no frames
7310 * are still pending on the queue.
7312 if (!ath_hal_stoptxdma(ah, sc->sc_bhalq)) {
7313 DPRINTF(sc, ATH_DEBUG_ANY,
7314 "%s: beacon queue %u did not stop?\n",
7315 __func__, sc->sc_bhalq);
7316 /* NB: the HAL still stops DMA, so proceed */
7318 ath_hal_puttxbuf(ah, sc->sc_bhalq, bf->bf_daddr);
7319 ath_hal_txstart(ah, sc->sc_bhalq);
7321 sc->sc_stats.ast_be_xmit++; /* XXX per-vap? */
7324 * Record local TSF for our last send for use
7325 * in arbitrating slot collisions.
7327 vap->iv_bss->ni_tstamp.tsf = ath_hal_gettsf64(ah);
7330 #endif /* IEEE80211_SUPPORT_TDMA */