sys/dev/bge/if_bge.c

   1 /*-
   2  * Copyright (c) 2001 Wind River Systems
   3  * Copyright (c) 1997, 1998, 1999, 2001
   4  *      Bill Paul <wpaul@windriver.com>.  All rights reserved.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions
   8  * are met:
   9  * 1. Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions and the following disclaimer.
  11  * 2. Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the distribution.
  14  * 3. All advertising materials mentioning features or use of this software
  15  *    must display the following acknowledgement:
  16  *      This product includes software developed by Bill Paul.
  17  * 4. Neither the name of the author nor the names of any co-contributors
  18  *    may be used to endorse or promote products derived from this software
  19  *    without specific prior written permission.
  20  *
  21  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
  22  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  23  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  24  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
  25  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  26  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  27  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  28  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  29  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  30  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  31  * THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/cdefs.h>
  35 __FBSDID("$FreeBSD$");
  36
  37 /*
  38  * Broadcom BCM570x family gigabit ethernet driver for FreeBSD.
  39  *
  40  * The Broadcom BCM5700 is based on technology originally developed by
  41  * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet
  42  * MAC chips. The BCM5700, sometimes refered to as the Tigon III, has
  43  * two on-board MIPS R4000 CPUs and can have as much as 16MB of external
  44  * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo
  45  * frames, highly configurable RX filtering, and 16 RX and TX queues
  46  * (which, along with RX filter rules, can be used for QOS applications).
  47  * Other features, such as TCP segmentation, may be available as part
  48  * of value-added firmware updates. Unlike the Tigon I and Tigon II,
  49  * firmware images can be stored in hardware and need not be compiled
  50  * into the driver.
  51  *
  52  * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will
  53  * function in a 32-bit/64-bit 33/66Mhz bus, or a 64-bit/133Mhz bus.
  54  *
  55  * The BCM5701 is a single-chip solution incorporating both the BCM5700
  56  * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701
  57  * does not support external SSRAM.
  58  *
  59  * Broadcom also produces a variation of the BCM5700 under the "Altima"
  60  * brand name, which is functionally similar but lacks PCI-X support.
  61  *
  62  * Without external SSRAM, you can only have at most 4 TX rings,
  63  * and the use of the mini RX ring is disabled. This seems to imply
  64  * that these features are simply not available on the BCM5701. As a
  65  * result, this driver does not implement any support for the mini RX
  66  * ring.
  67  */
  68
  69 #ifdef HAVE_KERNEL_OPTION_HEADERS
  70 #include "opt_device_polling.h"
  71 #endif
  72
  73 #include <sys/param.h>
  74 #include <sys/endian.h>
  75 #include <sys/systm.h>
  76 #include <sys/sockio.h>
  77 #include <sys/mbuf.h>
  78 #include <sys/malloc.h>
  79 #include <sys/kernel.h>
  80 #include <sys/module.h>
  81 #include <sys/socket.h>
  82 #include <sys/sysctl.h>
  83 #include <sys/taskqueue.h>
  84
  85 #include <net/if.h>
  86 #include <net/if_arp.h>
  87 #include <net/ethernet.h>
  88 #include <net/if_dl.h>
  89 #include <net/if_media.h>
  90
  91 #include <net/bpf.h>
  92
  93 #include <net/if_types.h>
  94 #include <net/if_vlan_var.h>
  95
  96 #include <netinet/in_systm.h>
  97 #include <netinet/in.h>
  98 #include <netinet/ip.h>
  99 #include <netinet/tcp.h>
 100
 101 #include <machine/bus.h>
 102 #include <machine/resource.h>
 103 #include <sys/bus.h>
 104 #include <sys/rman.h>
 105
 106 #include <dev/mii/mii.h>
 107 #include <dev/mii/miivar.h>
 108 #include "miidevs.h"
 109 #include <dev/mii/brgphyreg.h>
 110
 111 #ifdef __sparc64__
 112 #include <dev/ofw/ofw_bus.h>
 113 #include <dev/ofw/openfirm.h>
 114 #include <machine/ofw_machdep.h>
 115 #include <machine/ver.h>
 116 #endif
 117
 118 #include <dev/pci/pcireg.h>
 119 #include <dev/pci/pcivar.h>
 120
 121 #include <dev/bge/if_bgereg.h>
 122
 123 #define BGE_CSUM_FEATURES       (CSUM_IP | CSUM_TCP | CSUM_UDP)
 124 #define ETHER_MIN_NOPAD         (ETHER_MIN_LEN - ETHER_CRC_LEN) /* i.e., 60 */
 125
 126 MODULE_DEPEND(bge, pci, 1, 1, 1);
 127 MODULE_DEPEND(bge, ether, 1, 1, 1);
 128 MODULE_DEPEND(bge, miibus, 1, 1, 1);
 129
 130 /* "device miibus" required.  See GENERIC if you get errors here. */
 131 #include "miibus_if.h"
 132
 133 /*
 134  * Various supported device vendors/types and their names. Note: the
 135  * spec seems to indicate that the hardware still has Alteon's vendor
 136  * ID burned into it, though it will always be overriden by the vendor
 137  * ID in the EEPROM. Just to be safe, we cover all possibilities.
 138  */
 139 static const struct bge_type {
 140         uint16_t        bge_vid;
 141         uint16_t        bge_did;
 142 } bge_devs[] = {
 143         { ALTEON_VENDORID,      ALTEON_DEVICEID_BCM5700 },
 144         { ALTEON_VENDORID,      ALTEON_DEVICEID_BCM5701 },
 145
 146         { ALTIMA_VENDORID,      ALTIMA_DEVICE_AC1000 },
 147         { ALTIMA_VENDORID,      ALTIMA_DEVICE_AC1002 },
 148         { ALTIMA_VENDORID,      ALTIMA_DEVICE_AC9100 },
 149
 150         { APPLE_VENDORID,       APPLE_DEVICE_BCM5701 },
 151
 152         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5700 },
 153         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5701 },
 154         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5702 },
 155         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5702_ALT },
 156         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5702X },
 157         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5703 },
 158         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5703_ALT },
 159         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5703X },
 160         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5704C },
 161         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5704S },
 162         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5704S_ALT },
 163         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5705 },
 164         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5705F },
 165         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5705K },
 166         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5705M },
 167         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5705M_ALT },
 168         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5714C },
 169         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5714S },
 170         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5715 },
 171         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5715S },
 172         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5720 },
 173         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5721 },
 174         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5722 },
 175         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5723 },
 176         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5750 },
 177         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5750M },
 178         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5751 },
 179         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5751F },
 180         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5751M },
 181         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5752 },
 182         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5752M },
 183         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5753 },
 184         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5753F },
 185         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5753M },
 186         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5754 },
 187         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5754M },
 188         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5755 },
 189         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5755M },
 190         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5756 },
 191         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5761 },
 192         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5761E },
 193         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5761S },
 194         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5761SE },
 195         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5764 },
 196         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5780 },
 197         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5780S },
 198         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5781 },
 199         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5782 },
 200         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5784 },
 201         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5785F },
 202         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5785G },
 203         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5786 },
 204         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5787 },
 205         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5787F },
 206         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5787M },
 207         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5788 },
 208         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5789 },
 209         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5901 },
 210         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5901A2 },
 211         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5903M },
 212         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5906 },
 213         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5906M },
 214         { BCOM_VENDORID,        BCOM_DEVICEID_BCM57760 },
 215         { BCOM_VENDORID,        BCOM_DEVICEID_BCM57780 },
 216         { BCOM_VENDORID,        BCOM_DEVICEID_BCM57788 },
 217         { BCOM_VENDORID,        BCOM_DEVICEID_BCM57790 },
 218
 219         { SK_VENDORID,          SK_DEVICEID_ALTIMA },
 220
 221         { TC_VENDORID,          TC_DEVICEID_3C996 },
 222
 223         { FJTSU_VENDORID,       FJTSU_DEVICEID_PW008GE4 },
 224         { FJTSU_VENDORID,       FJTSU_DEVICEID_PW008GE5 },
 225         { FJTSU_VENDORID,       FJTSU_DEVICEID_PP250450 },
 226
 227         { 0, 0 }
 228 };
 229
 230 static const struct bge_vendor {
 231         uint16_t        v_id;
 232         const char      *v_name;
 233 } bge_vendors[] = {
 234         { ALTEON_VENDORID,      "Alteon" },
 235         { ALTIMA_VENDORID,      "Altima" },
 236         { APPLE_VENDORID,       "Apple" },
 237         { BCOM_VENDORID,        "Broadcom" },
 238         { SK_VENDORID,          "SysKonnect" },
 239         { TC_VENDORID,          "3Com" },
 240         { FJTSU_VENDORID,       "Fujitsu" },
 241
 242         { 0, NULL }
 243 };
 244
 245 static const struct bge_revision {
 246         uint32_t        br_chipid;
 247         const char      *br_name;
 248 } bge_revisions[] = {
 249         { BGE_CHIPID_BCM5700_A0,        "BCM5700 A0" },
 250         { BGE_CHIPID_BCM5700_A1,        "BCM5700 A1" },
 251         { BGE_CHIPID_BCM5700_B0,        "BCM5700 B0" },
 252         { BGE_CHIPID_BCM5700_B1,        "BCM5700 B1" },
 253         { BGE_CHIPID_BCM5700_B2,        "BCM5700 B2" },
 254         { BGE_CHIPID_BCM5700_B3,        "BCM5700 B3" },
 255         { BGE_CHIPID_BCM5700_ALTIMA,    "BCM5700 Altima" },
 256         { BGE_CHIPID_BCM5700_C0,        "BCM5700 C0" },
 257         { BGE_CHIPID_BCM5701_A0,        "BCM5701 A0" },
 258         { BGE_CHIPID_BCM5701_B0,        "BCM5701 B0" },
 259         { BGE_CHIPID_BCM5701_B2,        "BCM5701 B2" },
 260         { BGE_CHIPID_BCM5701_B5,        "BCM5701 B5" },
 261         { BGE_CHIPID_BCM5703_A0,        "BCM5703 A0" },
 262         { BGE_CHIPID_BCM5703_A1,        "BCM5703 A1" },
 263         { BGE_CHIPID_BCM5703_A2,        "BCM5703 A2" },
 264         { BGE_CHIPID_BCM5703_A3,        "BCM5703 A3" },
 265         { BGE_CHIPID_BCM5703_B0,        "BCM5703 B0" },
 266         { BGE_CHIPID_BCM5704_A0,        "BCM5704 A0" },
 267         { BGE_CHIPID_BCM5704_A1,        "BCM5704 A1" },
 268         { BGE_CHIPID_BCM5704_A2,        "BCM5704 A2" },
 269         { BGE_CHIPID_BCM5704_A3,        "BCM5704 A3" },
 270         { BGE_CHIPID_BCM5704_B0,        "BCM5704 B0" },
 271         { BGE_CHIPID_BCM5705_A0,        "BCM5705 A0" },
 272         { BGE_CHIPID_BCM5705_A1,        "BCM5705 A1" },
 273         { BGE_CHIPID_BCM5705_A2,        "BCM5705 A2" },
 274         { BGE_CHIPID_BCM5705_A3,        "BCM5705 A3" },
 275         { BGE_CHIPID_BCM5750_A0,        "BCM5750 A0" },
 276         { BGE_CHIPID_BCM5750_A1,        "BCM5750 A1" },
 277         { BGE_CHIPID_BCM5750_A3,        "BCM5750 A3" },
 278         { BGE_CHIPID_BCM5750_B0,        "BCM5750 B0" },
 279         { BGE_CHIPID_BCM5750_B1,        "BCM5750 B1" },
 280         { BGE_CHIPID_BCM5750_C0,        "BCM5750 C0" },
 281         { BGE_CHIPID_BCM5750_C1,        "BCM5750 C1" },
 282         { BGE_CHIPID_BCM5750_C2,        "BCM5750 C2" },
 283         { BGE_CHIPID_BCM5714_A0,        "BCM5714 A0" },
 284         { BGE_CHIPID_BCM5752_A0,        "BCM5752 A0" },
 285         { BGE_CHIPID_BCM5752_A1,        "BCM5752 A1" },
 286         { BGE_CHIPID_BCM5752_A2,        "BCM5752 A2" },
 287         { BGE_CHIPID_BCM5714_B0,        "BCM5714 B0" },
 288         { BGE_CHIPID_BCM5714_B3,        "BCM5714 B3" },
 289         { BGE_CHIPID_BCM5715_A0,        "BCM5715 A0" },
 290         { BGE_CHIPID_BCM5715_A1,        "BCM5715 A1" },
 291         { BGE_CHIPID_BCM5715_A3,        "BCM5715 A3" },
 292         { BGE_CHIPID_BCM5755_A0,        "BCM5755 A0" },
 293         { BGE_CHIPID_BCM5755_A1,        "BCM5755 A1" },
 294         { BGE_CHIPID_BCM5755_A2,        "BCM5755 A2" },
 295         { BGE_CHIPID_BCM5722_A0,        "BCM5722 A0" },
 296         { BGE_CHIPID_BCM5761_A0,        "BCM5761 A0" },
 297         { BGE_CHIPID_BCM5761_A1,        "BCM5761 A1" },
 298         { BGE_CHIPID_BCM5784_A0,        "BCM5784 A0" },
 299         { BGE_CHIPID_BCM5784_A1,        "BCM5784 A1" },
 300         /* 5754 and 5787 share the same ASIC ID */
 301         { BGE_CHIPID_BCM5787_A0,        "BCM5754/5787 A0" },
 302         { BGE_CHIPID_BCM5787_A1,        "BCM5754/5787 A1" },
 303         { BGE_CHIPID_BCM5787_A2,        "BCM5754/5787 A2" },
 304         { BGE_CHIPID_BCM5906_A1,        "BCM5906 A1" },
 305         { BGE_CHIPID_BCM5906_A2,        "BCM5906 A2" },
 306         { BGE_CHIPID_BCM57780_A0,       "BCM57780 A0" },
 307         { BGE_CHIPID_BCM57780_A1,       "BCM57780 A1" },
 308
 309         { 0, NULL }
 310 };
 311
 312 /*
 313  * Some defaults for major revisions, so that newer steppings
 314  * that we don't know about have a shot at working.
 315  */
 316 static const struct bge_revision bge_majorrevs[] = {
 317         { BGE_ASICREV_BCM5700,          "unknown BCM5700" },
 318         { BGE_ASICREV_BCM5701,          "unknown BCM5701" },
 319         { BGE_ASICREV_BCM5703,          "unknown BCM5703" },
 320         { BGE_ASICREV_BCM5704,          "unknown BCM5704" },
 321         { BGE_ASICREV_BCM5705,          "unknown BCM5705" },
 322         { BGE_ASICREV_BCM5750,          "unknown BCM5750" },
 323         { BGE_ASICREV_BCM5714_A0,       "unknown BCM5714" },
 324         { BGE_ASICREV_BCM5752,          "unknown BCM5752" },
 325         { BGE_ASICREV_BCM5780,          "unknown BCM5780" },
 326         { BGE_ASICREV_BCM5714,          "unknown BCM5714" },
 327         { BGE_ASICREV_BCM5755,          "unknown BCM5755" },
 328         { BGE_ASICREV_BCM5761,          "unknown BCM5761" },
 329         { BGE_ASICREV_BCM5784,          "unknown BCM5784" },
 330         { BGE_ASICREV_BCM5785,          "unknown BCM5785" },
 331         /* 5754 and 5787 share the same ASIC ID */
 332         { BGE_ASICREV_BCM5787,          "unknown BCM5754/5787" },
 333         { BGE_ASICREV_BCM5906,          "unknown BCM5906" },
 334         { BGE_ASICREV_BCM57780,         "unknown BCM57780" },
 335
 336         { 0, NULL }
 337 };
 338
 339 #define BGE_IS_JUMBO_CAPABLE(sc)        ((sc)->bge_flags & BGE_FLAG_JUMBO)
 340 #define BGE_IS_5700_FAMILY(sc)          ((sc)->bge_flags & BGE_FLAG_5700_FAMILY)
 341 #define BGE_IS_5705_PLUS(sc)            ((sc)->bge_flags & BGE_FLAG_5705_PLUS)
 342 #define BGE_IS_5714_FAMILY(sc)          ((sc)->bge_flags & BGE_FLAG_5714_FAMILY)
 343 #define BGE_IS_575X_PLUS(sc)            ((sc)->bge_flags & BGE_FLAG_575X_PLUS)
 344 #define BGE_IS_5755_PLUS(sc)            ((sc)->bge_flags & BGE_FLAG_5755_PLUS)
 345
 346 const struct bge_revision * bge_lookup_rev(uint32_t);
 347 const struct bge_vendor * bge_lookup_vendor(uint16_t);
 348
 349 typedef int     (*bge_eaddr_fcn_t)(struct bge_softc *, uint8_t[]);
 350
 351 static int bge_probe(device_t);
 352 static int bge_attach(device_t);
 353 static int bge_detach(device_t);
 354 static int bge_suspend(device_t);
 355 static int bge_resume(device_t);
 356 static void bge_release_resources(struct bge_softc *);
 357 static void bge_dma_map_addr(void *, bus_dma_segment_t *, int, int);
 358 static int bge_dma_alloc(device_t);
 359 static void bge_dma_free(struct bge_softc *);
 360
 361 static int bge_get_eaddr_fw(struct bge_softc *sc, uint8_t ether_addr[]);
 362 static int bge_get_eaddr_mem(struct bge_softc *, uint8_t[]);
 363 static int bge_get_eaddr_nvram(struct bge_softc *, uint8_t[]);
 364 static int bge_get_eaddr_eeprom(struct bge_softc *, uint8_t[]);
 365 static int bge_get_eaddr(struct bge_softc *, uint8_t[]);
 366
 367 static void bge_txeof(struct bge_softc *, uint16_t);
 368 static int bge_rxeof(struct bge_softc *, uint16_t, int);
 369
 370 static void bge_asf_driver_up (struct bge_softc *);
 371 static void bge_tick(void *);
 372 static void bge_stats_update(struct bge_softc *);
 373 static void bge_stats_update_regs(struct bge_softc *);
 374 static struct mbuf *bge_setup_tso(struct bge_softc *, struct mbuf *,
 375     uint16_t *);
 376 static int bge_encap(struct bge_softc *, struct mbuf **, uint32_t *);
 377
 378 static void bge_intr(void *);
 379 static int bge_msi_intr(void *);
 380 static void bge_intr_task(void *, int);
 381 static void bge_start_locked(struct ifnet *);
 382 static void bge_start(struct ifnet *);
 383 static int bge_ioctl(struct ifnet *, u_long, caddr_t);
 384 static void bge_init_locked(struct bge_softc *);
 385 static void bge_init(void *);
 386 static void bge_stop(struct bge_softc *);
 387 static void bge_watchdog(struct bge_softc *);
 388 static int bge_shutdown(device_t);
 389 static int bge_ifmedia_upd_locked(struct ifnet *);
 390 static int bge_ifmedia_upd(struct ifnet *);
 391 static void bge_ifmedia_sts(struct ifnet *, struct ifmediareq *);
 392
 393 static uint8_t bge_nvram_getbyte(struct bge_softc *, int, uint8_t *);
 394 static int bge_read_nvram(struct bge_softc *, caddr_t, int, int);
 395
 396 static uint8_t bge_eeprom_getbyte(struct bge_softc *, int, uint8_t *);
 397 static int bge_read_eeprom(struct bge_softc *, caddr_t, int, int);
 398
 399 static void bge_setpromisc(struct bge_softc *);
 400 static void bge_setmulti(struct bge_softc *);
 401 static void bge_setvlan(struct bge_softc *);
 402
 403 static __inline void bge_rxreuse_std(struct bge_softc *, int);
 404 static __inline void bge_rxreuse_jumbo(struct bge_softc *, int);
 405 static int bge_newbuf_std(struct bge_softc *, int);
 406 static int bge_newbuf_jumbo(struct bge_softc *, int);
 407 static int bge_init_rx_ring_std(struct bge_softc *);
 408 static void bge_free_rx_ring_std(struct bge_softc *);
 409 static int bge_init_rx_ring_jumbo(struct bge_softc *);
 410 static void bge_free_rx_ring_jumbo(struct bge_softc *);
 411 static void bge_free_tx_ring(struct bge_softc *);
 412 static int bge_init_tx_ring(struct bge_softc *);
 413
 414 static int bge_chipinit(struct bge_softc *);
 415 static int bge_blockinit(struct bge_softc *);
 416
 417 static int bge_has_eaddr(struct bge_softc *);
 418 static uint32_t bge_readmem_ind(struct bge_softc *, int);
 419 static void bge_writemem_ind(struct bge_softc *, int, int);
 420 static void bge_writembx(struct bge_softc *, int, int);
 421 #ifdef notdef
 422 static uint32_t bge_readreg_ind(struct bge_softc *, int);
 423 #endif
 424 static void bge_writemem_direct(struct bge_softc *, int, int);
 425 static void bge_writereg_ind(struct bge_softc *, int, int);
 426 static void bge_set_max_readrq(struct bge_softc *);
 427
 428 static int bge_miibus_readreg(device_t, int, int);
 429 static int bge_miibus_writereg(device_t, int, int, int);
 430 static void bge_miibus_statchg(device_t);
 431 #ifdef DEVICE_POLLING
 432 static int bge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count);
 433 #endif
 434
 435 #define BGE_RESET_START 1
 436 #define BGE_RESET_STOP  2
 437 static void bge_sig_post_reset(struct bge_softc *, int);
 438 static void bge_sig_legacy(struct bge_softc *, int);
 439 static void bge_sig_pre_reset(struct bge_softc *, int);
 440 static int bge_reset(struct bge_softc *);
 441 static void bge_link_upd(struct bge_softc *);
 442
 443 /*
 444  * The BGE_REGISTER_DEBUG option is only for low-level debugging.  It may
 445  * leak information to untrusted users.  It is also known to cause alignment
 446  * traps on certain architectures.
 447  */
 448 #ifdef BGE_REGISTER_DEBUG
 449 static int bge_sysctl_debug_info(SYSCTL_HANDLER_ARGS);
 450 static int bge_sysctl_reg_read(SYSCTL_HANDLER_ARGS);
 451 static int bge_sysctl_mem_read(SYSCTL_HANDLER_ARGS);
 452 #endif
 453 static void bge_add_sysctls(struct bge_softc *);
 454 static int bge_sysctl_stats(SYSCTL_HANDLER_ARGS);
 455
 456 static device_method_t bge_methods[] = {
 457         /* Device interface */
 458         DEVMETHOD(device_probe,         bge_probe),
 459         DEVMETHOD(device_attach,        bge_attach),
 460         DEVMETHOD(device_detach,        bge_detach),
 461         DEVMETHOD(device_shutdown,      bge_shutdown),
 462         DEVMETHOD(device_suspend,       bge_suspend),
 463         DEVMETHOD(device_resume,        bge_resume),
 464
 465         /* bus interface */
 466         DEVMETHOD(bus_print_child,      bus_generic_print_child),
 467         DEVMETHOD(bus_driver_added,     bus_generic_driver_added),
 468
 469         /* MII interface */
 470         DEVMETHOD(miibus_readreg,       bge_miibus_readreg),
 471         DEVMETHOD(miibus_writereg,      bge_miibus_writereg),
 472         DEVMETHOD(miibus_statchg,       bge_miibus_statchg),
 473
 474         { 0, 0 }
 475 };
 476
 477 static driver_t bge_driver = {
 478         "bge",
 479         bge_methods,
 480         sizeof(struct bge_softc)
 481 };
 482
 483 static devclass_t bge_devclass;
 484
 485 DRIVER_MODULE(bge, pci, bge_driver, bge_devclass, 0, 0);
 486 DRIVER_MODULE(miibus, bge, miibus_driver, miibus_devclass, 0, 0);
 487
 488 static int bge_allow_asf = 0;
 489
 490 TUNABLE_INT("hw.bge.allow_asf", &bge_allow_asf);
 491
 492 SYSCTL_NODE(_hw, OID_AUTO, bge, CTLFLAG_RD, 0, "BGE driver parameters");
 493 SYSCTL_INT(_hw_bge, OID_AUTO, allow_asf, CTLFLAG_RD, &bge_allow_asf, 0,
 494         "Allow ASF mode if available");
 495
 496 #define SPARC64_BLADE_1500_MODEL        "SUNW,Sun-Blade-1500"
 497 #define SPARC64_BLADE_1500_PATH_BGE     "/pci@1f,700000/network@2"
 498 #define SPARC64_BLADE_2500_MODEL        "SUNW,Sun-Blade-2500"
 499 #define SPARC64_BLADE_2500_PATH_BGE     "/pci@1c,600000/network@3"
 500 #define SPARC64_OFW_SUBVENDOR           "subsystem-vendor-id"
 501
 502 static int
 503 bge_has_eaddr(struct bge_softc *sc)
 504 {
 505 #ifdef __sparc64__
 506         char buf[sizeof(SPARC64_BLADE_1500_PATH_BGE)];
 507         device_t dev;
 508         uint32_t subvendor;
 509
 510         dev = sc->bge_dev;
 511
 512         /*
 513          * The on-board BGEs found in sun4u machines aren't fitted with
 514          * an EEPROM which means that we have to obtain the MAC address
 515          * via OFW and that some tests will always fail.  We distinguish
 516          * such BGEs by the subvendor ID, which also has to be obtained
 517          * from OFW instead of the PCI configuration space as the latter
 518          * indicates Broadcom as the subvendor of the netboot interface.
 519          * For early Blade 1500 and 2500 we even have to check the OFW
 520          * device path as the subvendor ID always defaults to Broadcom
 521          * there.
 522          */
 523         if (OF_getprop(ofw_bus_get_node(dev), SPARC64_OFW_SUBVENDOR,
 524             &subvendor, sizeof(subvendor)) == sizeof(subvendor) &&
 525             (subvendor == FJTSU_VENDORID || subvendor == SUN_VENDORID))
 526                 return (0);
 527         memset(buf, 0, sizeof(buf));
 528         if (OF_package_to_path(ofw_bus_get_node(dev), buf, sizeof(buf)) > 0) {
 529                 if (strcmp(sparc64_model, SPARC64_BLADE_1500_MODEL) == 0 &&
 530                     strcmp(buf, SPARC64_BLADE_1500_PATH_BGE) == 0)
 531                         return (0);
 532                 if (strcmp(sparc64_model, SPARC64_BLADE_2500_MODEL) == 0 &&
 533                     strcmp(buf, SPARC64_BLADE_2500_PATH_BGE) == 0)
 534                         return (0);
 535         }
 536 #endif
 537         return (1);
 538 }
 539
 540 static uint32_t
 541 bge_readmem_ind(struct bge_softc *sc, int off)
 542 {
 543         device_t dev;
 544         uint32_t val;
 545
 546         dev = sc->bge_dev;
 547
 548         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
 549         val = pci_read_config(dev, BGE_PCI_MEMWIN_DATA, 4);
 550         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4);
 551         return (val);
 552 }
 553
 554 static void
 555 bge_writemem_ind(struct bge_softc *sc, int off, int val)
 556 {
 557         device_t dev;
 558
 559         dev = sc->bge_dev;
 560
 561         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
 562         pci_write_config(dev, BGE_PCI_MEMWIN_DATA, val, 4);
 563         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4);
 564 }
 565
 566 /*
 567  * PCI Express only
 568  */
 569 static void
 570 bge_set_max_readrq(struct bge_softc *sc)
 571 {
 572         device_t dev;
 573         uint16_t val;
 574
 575         dev = sc->bge_dev;
 576
 577         val = pci_read_config(dev, sc->bge_expcap + PCIR_EXPRESS_DEVICE_CTL, 2);
 578         if ((val & PCIM_EXP_CTL_MAX_READ_REQUEST) !=
 579             BGE_PCIE_DEVCTL_MAX_READRQ_4096) {
 580                 if (bootverbose)
 581                         device_printf(dev, "adjust device control 0x%04x ",
 582                             val);
 583                 val &= ~PCIM_EXP_CTL_MAX_READ_REQUEST;
 584                 val |= BGE_PCIE_DEVCTL_MAX_READRQ_4096;
 585                 pci_write_config(dev, sc->bge_expcap + PCIR_EXPRESS_DEVICE_CTL,
 586                     val, 2);
 587                 if (bootverbose)
 588                         printf("-> 0x%04x\n", val);
 589         }
 590 }
 591
 592 #ifdef notdef
 593 static uint32_t
 594 bge_readreg_ind(struct bge_softc *sc, int off)
 595 {
 596         device_t dev;
 597
 598         dev = sc->bge_dev;
 599
 600         pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4);
 601         return (pci_read_config(dev, BGE_PCI_REG_DATA, 4));
 602 }
 603 #endif
 604
 605 static void
 606 bge_writereg_ind(struct bge_softc *sc, int off, int val)
 607 {
 608         device_t dev;
 609
 610         dev = sc->bge_dev;
 611
 612         pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4);
 613         pci_write_config(dev, BGE_PCI_REG_DATA, val, 4);
 614 }
 615
 616 static void
 617 bge_writemem_direct(struct bge_softc *sc, int off, int val)
 618 {
 619         CSR_WRITE_4(sc, off, val);
 620 }
 621
 622 static void
 623 bge_writembx(struct bge_softc *sc, int off, int val)
 624 {
 625         if (sc->bge_asicrev == BGE_ASICREV_BCM5906)
 626                 off += BGE_LPMBX_IRQ0_HI - BGE_MBX_IRQ0_HI;
 627
 628         CSR_WRITE_4(sc, off, val);
 629 }
 630
 631 /*
 632  * Map a single buffer address.
 633  */
 634
 635 static void
 636 bge_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
 637 {
 638         struct bge_dmamap_arg *ctx;
 639
 640         if (error)
 641                 return;
 642
 643         ctx = arg;
 644
 645         if (nseg > ctx->bge_maxsegs) {
 646                 ctx->bge_maxsegs = 0;
 647                 return;
 648         }
 649
 650         ctx->bge_busaddr = segs->ds_addr;
 651 }
 652
 653 static uint8_t
 654 bge_nvram_getbyte(struct bge_softc *sc, int addr, uint8_t *dest)
 655 {
 656         uint32_t access, byte = 0;
 657         int i;
 658
 659         /* Lock. */
 660         CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1);
 661         for (i = 0; i < 8000; i++) {
 662                 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & BGE_NVRAMSWARB_GNT1)
 663                         break;
 664                 DELAY(20);
 665         }
 666         if (i == 8000)
 667                 return (1);
 668
 669         /* Enable access. */
 670         access = CSR_READ_4(sc, BGE_NVRAM_ACCESS);
 671         CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access | BGE_NVRAMACC_ENABLE);
 672
 673         CSR_WRITE_4(sc, BGE_NVRAM_ADDR, addr & 0xfffffffc);
 674         CSR_WRITE_4(sc, BGE_NVRAM_CMD, BGE_NVRAM_READCMD);
 675         for (i = 0; i < BGE_TIMEOUT * 10; i++) {
 676                 DELAY(10);
 677                 if (CSR_READ_4(sc, BGE_NVRAM_CMD) & BGE_NVRAMCMD_DONE) {
 678                         DELAY(10);
 679                         break;
 680                 }
 681         }
 682
 683         if (i == BGE_TIMEOUT * 10) {
 684                 if_printf(sc->bge_ifp, "nvram read timed out\n");
 685                 return (1);
 686         }
 687
 688         /* Get result. */
 689         byte = CSR_READ_4(sc, BGE_NVRAM_RDDATA);
 690
 691         *dest = (bswap32(byte) >> ((addr % 4) * 8)) & 0xFF;
 692
 693         /* Disable access. */
 694         CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access);
 695
 696         /* Unlock. */
 697         CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_CLR1);
 698         CSR_READ_4(sc, BGE_NVRAM_SWARB);
 699
 700         return (0);
 701 }
 702
 703 /*
 704  * Read a sequence of bytes from NVRAM.
 705  */
 706 static int
 707 bge_read_nvram(struct bge_softc *sc, caddr_t dest, int off, int cnt)
 708 {
 709         int err = 0, i;
 710         uint8_t byte = 0;
 711
 712         if (sc->bge_asicrev != BGE_ASICREV_BCM5906)
 713                 return (1);
 714
 715         for (i = 0; i < cnt; i++) {
 716                 err = bge_nvram_getbyte(sc, off + i, &byte);
 717                 if (err)
 718                         break;
 719                 *(dest + i) = byte;
 720         }
 721
 722         return (err ? 1 : 0);
 723 }
 724
 725 /*
 726  * Read a byte of data stored in the EEPROM at address 'addr.' The
 727  * BCM570x supports both the traditional bitbang interface and an
 728  * auto access interface for reading the EEPROM. We use the auto
 729  * access method.
 730  */
 731 static uint8_t
 732 bge_eeprom_getbyte(struct bge_softc *sc, int addr, uint8_t *dest)
 733 {
 734         int i;
 735         uint32_t byte = 0;
 736
 737         /*
 738          * Enable use of auto EEPROM access so we can avoid
 739          * having to use the bitbang method.
 740          */
 741         BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM);
 742
 743         /* Reset the EEPROM, load the clock period. */
 744         CSR_WRITE_4(sc, BGE_EE_ADDR,
 745             BGE_EEADDR_RESET | BGE_EEHALFCLK(BGE_HALFCLK_384SCL));
 746         DELAY(20);
 747
 748         /* Issue the read EEPROM command. */
 749         CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr);
 750
 751         /* Wait for completion */
 752         for(i = 0; i < BGE_TIMEOUT * 10; i++) {
 753                 DELAY(10);
 754                 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE)
 755                         break;
 756         }
 757
 758         if (i == BGE_TIMEOUT * 10) {
 759                 device_printf(sc->bge_dev, "EEPROM read timed out\n");
 760                 return (1);
 761         }
 762
 763         /* Get result. */
 764         byte = CSR_READ_4(sc, BGE_EE_DATA);
 765
 766         *dest = (byte >> ((addr % 4) * 8)) & 0xFF;
 767
 768         return (0);
 769 }
 770
 771 /*
 772  * Read a sequence of bytes from the EEPROM.
 773  */
 774 static int
 775 bge_read_eeprom(struct bge_softc *sc, caddr_t dest, int off, int cnt)
 776 {
 777         int i, error = 0;
 778         uint8_t byte = 0;
 779
 780         for (i = 0; i < cnt; i++) {
 781                 error = bge_eeprom_getbyte(sc, off + i, &byte);
 782                 if (error)
 783                         break;
 784                 *(dest + i) = byte;
 785         }
 786
 787         return (error ? 1 : 0);
 788 }
 789
 790 static int
 791 bge_miibus_readreg(device_t dev, int phy, int reg)
 792 {
 793         struct bge_softc *sc;
 794         uint32_t val, autopoll;
 795         int i;
 796
 797         sc = device_get_softc(dev);
 798
 799         /*
 800          * Broadcom's own driver always assumes the internal
 801          * PHY is at GMII address 1. On some chips, the PHY responds
 802          * to accesses at all addresses, which could cause us to
 803          * bogusly attach the PHY 32 times at probe type. Always
 804          * restricting the lookup to address 1 is simpler than
 805          * trying to figure out which chips revisions should be
 806          * special-cased.
 807          */
 808         if (phy != 1)
 809                 return (0);
 810
 811         /* Reading with autopolling on may trigger PCI errors */
 812         autopoll = CSR_READ_4(sc, BGE_MI_MODE);
 813         if (autopoll & BGE_MIMODE_AUTOPOLL) {
 814                 BGE_CLRBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
 815                 DELAY(40);
 816         }
 817
 818         CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ | BGE_MICOMM_BUSY |
 819             BGE_MIPHY(phy) | BGE_MIREG(reg));
 820
 821         for (i = 0; i < BGE_TIMEOUT; i++) {
 822                 DELAY(10);
 823                 val = CSR_READ_4(sc, BGE_MI_COMM);
 824                 if (!(val & BGE_MICOMM_BUSY))
 825                         break;
 826         }
 827
 828         if (i == BGE_TIMEOUT) {
 829                 device_printf(sc->bge_dev,
 830                     "PHY read timed out (phy %d, reg %d, val 0x%08x)\n",
 831                     phy, reg, val);
 832                 val = 0;
 833                 goto done;
 834         }
 835
 836         DELAY(5);
 837         val = CSR_READ_4(sc, BGE_MI_COMM);
 838
 839 done:
 840         if (autopoll & BGE_MIMODE_AUTOPOLL) {
 841                 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
 842                 DELAY(40);
 843         }
 844
 845         if (val & BGE_MICOMM_READFAIL)
 846                 return (0);
 847
 848         return (val & 0xFFFF);
 849 }
 850
 851 static int
 852 bge_miibus_writereg(device_t dev, int phy, int reg, int val)
 853 {
 854         struct bge_softc *sc;
 855         uint32_t autopoll;
 856         int i;
 857
 858         sc = device_get_softc(dev);
 859
 860         if (sc->bge_asicrev == BGE_ASICREV_BCM5906 &&
 861             (reg == BRGPHY_MII_1000CTL || reg == BRGPHY_MII_AUXCTL))
 862                 return(0);
 863
 864         /* Reading with autopolling on may trigger PCI errors */
 865         autopoll = CSR_READ_4(sc, BGE_MI_MODE);
 866         if (autopoll & BGE_MIMODE_AUTOPOLL) {
 867                 BGE_CLRBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
 868                 DELAY(40);
 869         }
 870
 871         CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE | BGE_MICOMM_BUSY |
 872             BGE_MIPHY(phy) | BGE_MIREG(reg) | val);
 873
 874         for (i = 0; i < BGE_TIMEOUT; i++) {
 875                 DELAY(10);
 876                 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) {
 877                         DELAY(5);
 878                         CSR_READ_4(sc, BGE_MI_COMM); /* dummy read */
 879                         break;
 880                 }
 881         }
 882
 883         if (i == BGE_TIMEOUT) {
 884                 device_printf(sc->bge_dev,
 885                     "PHY write timed out (phy %d, reg %d, val %d)\n",
 886                     phy, reg, val);
 887                 return (0);
 888         }
 889
 890         if (autopoll & BGE_MIMODE_AUTOPOLL) {
 891                 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
 892                 DELAY(40);
 893         }
 894
 895         return (0);
 896 }
 897
 898 static void
 899 bge_miibus_statchg(device_t dev)
 900 {
 901         struct bge_softc *sc;
 902         struct mii_data *mii;
 903         sc = device_get_softc(dev);
 904         mii = device_get_softc(sc->bge_miibus);
 905
 906         BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_PORTMODE);
 907         if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T ||
 908             IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX)
 909                 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_GMII);
 910         else
 911                 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_MII);
 912
 913         if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX)
 914                 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX);
 915         else
 916                 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX);
 917 }
 918
 919 /*
 920  * Intialize a standard receive ring descriptor.
 921  */
 922 static int
 923 bge_newbuf_std(struct bge_softc *sc, int i)
 924 {
 925         struct mbuf *m;
 926         struct bge_rx_bd *r;
 927         bus_dma_segment_t segs[1];
 928         bus_dmamap_t map;
 929         int error, nsegs;
 930
 931         m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
 932         if (m == NULL)
 933                 return (ENOBUFS);
 934         m->m_len = m->m_pkthdr.len = MCLBYTES;
 935         if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0)
 936                 m_adj(m, ETHER_ALIGN);
 937
 938         error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_rx_mtag,
 939             sc->bge_cdata.bge_rx_std_sparemap, m, segs, &nsegs, 0);
 940         if (error != 0) {
 941                 m_freem(m);
 942                 return (error);
 943         }
 944         if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) {
 945                 bus_dmamap_sync(sc->bge_cdata.bge_rx_mtag,
 946                     sc->bge_cdata.bge_rx_std_dmamap[i], BUS_DMASYNC_POSTREAD);
 947                 bus_dmamap_unload(sc->bge_cdata.bge_rx_mtag,
 948                     sc->bge_cdata.bge_rx_std_dmamap[i]);
 949         }
 950         map = sc->bge_cdata.bge_rx_std_dmamap[i];
 951         sc->bge_cdata.bge_rx_std_dmamap[i] = sc->bge_cdata.bge_rx_std_sparemap;
 952         sc->bge_cdata.bge_rx_std_sparemap = map;
 953         sc->bge_cdata.bge_rx_std_chain[i] = m;
 954         sc->bge_cdata.bge_rx_std_seglen[i] = segs[0].ds_len;
 955         r = &sc->bge_ldata.bge_rx_std_ring[sc->bge_std];
 956         r->bge_addr.bge_addr_lo = BGE_ADDR_LO(segs[0].ds_addr);
 957         r->bge_addr.bge_addr_hi = BGE_ADDR_HI(segs[0].ds_addr);
 958         r->bge_flags = BGE_RXBDFLAG_END;
 959         r->bge_len = segs[0].ds_len;
 960         r->bge_idx = i;
 961
 962         bus_dmamap_sync(sc->bge_cdata.bge_rx_mtag,
 963             sc->bge_cdata.bge_rx_std_dmamap[i], BUS_DMASYNC_PREREAD);
 964
 965         return (0);
 966 }
 967
 968 /*
 969  * Initialize a jumbo receive ring descriptor. This allocates
 970  * a jumbo buffer from the pool managed internally by the driver.
 971  */
 972 static int
 973 bge_newbuf_jumbo(struct bge_softc *sc, int i)
 974 {
 975         bus_dma_segment_t segs[BGE_NSEG_JUMBO];
 976         bus_dmamap_t map;
 977         struct bge_extrx_bd *r;
 978         struct mbuf *m;
 979         int error, nsegs;
 980
 981         MGETHDR(m, M_DONTWAIT, MT_DATA);
 982         if (m == NULL)
 983                 return (ENOBUFS);
 984
 985         m_cljget(m, M_DONTWAIT, MJUM9BYTES);
 986         if (!(m->m_flags & M_EXT)) {
 987                 m_freem(m);
 988                 return (ENOBUFS);
 989         }
 990         m->m_len = m->m_pkthdr.len = MJUM9BYTES;
 991         if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0)
 992                 m_adj(m, ETHER_ALIGN);
 993
 994         error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_mtag_jumbo,
 995             sc->bge_cdata.bge_rx_jumbo_sparemap, m, segs, &nsegs, 0);
 996         if (error != 0) {
 997                 m_freem(m);
 998                 return (error);
 999         }
1000
1001         if (sc->bge_cdata.bge_rx_jumbo_chain[i] == NULL) {
1002                 bus_dmamap_sync(sc->bge_cdata.bge_mtag_jumbo,
1003                     sc->bge_cdata.bge_rx_jumbo_dmamap[i], BUS_DMASYNC_POSTREAD);
1004                 bus_dmamap_unload(sc->bge_cdata.bge_mtag_jumbo,
1005                     sc->bge_cdata.bge_rx_jumbo_dmamap[i]);
1006         }
1007         map = sc->bge_cdata.bge_rx_jumbo_dmamap[i];
1008         sc->bge_cdata.bge_rx_jumbo_dmamap[i] =
1009             sc->bge_cdata.bge_rx_jumbo_sparemap;
1010         sc->bge_cdata.bge_rx_jumbo_sparemap = map;
1011         sc->bge_cdata.bge_rx_jumbo_chain[i] = m;
1012         sc->bge_cdata.bge_rx_jumbo_seglen[i][0] = 0;
1013         sc->bge_cdata.bge_rx_jumbo_seglen[i][1] = 0;
1014         sc->bge_cdata.bge_rx_jumbo_seglen[i][2] = 0;
1015         sc->bge_cdata.bge_rx_jumbo_seglen[i][3] = 0;
1016
1017         /*
1018          * Fill in the extended RX buffer descriptor.
1019          */
1020         r = &sc->bge_ldata.bge_rx_jumbo_ring[sc->bge_jumbo];
1021         r->bge_flags = BGE_RXBDFLAG_JUMBO_RING | BGE_RXBDFLAG_END;
1022         r->bge_idx = i;
1023         r->bge_len3 = r->bge_len2 = r->bge_len1 = 0;
1024         switch (nsegs) {
1025         case 4:
1026                 r->bge_addr3.bge_addr_lo = BGE_ADDR_LO(segs[3].ds_addr);
1027                 r->bge_addr3.bge_addr_hi = BGE_ADDR_HI(segs[3].ds_addr);
1028                 r->bge_len3 = segs[3].ds_len;
1029                 sc->bge_cdata.bge_rx_jumbo_seglen[i][3] = segs[3].ds_len;
1030         case 3:
1031                 r->bge_addr2.bge_addr_lo = BGE_ADDR_LO(segs[2].ds_addr);
1032                 r->bge_addr2.bge_addr_hi = BGE_ADDR_HI(segs[2].ds_addr);
1033                 r->bge_len2 = segs[2].ds_len;
1034                 sc->bge_cdata.bge_rx_jumbo_seglen[i][2] = segs[2].ds_len;
1035         case 2:
1036                 r->bge_addr1.bge_addr_lo = BGE_ADDR_LO(segs[1].ds_addr);
1037                 r->bge_addr1.bge_addr_hi = BGE_ADDR_HI(segs[1].ds_addr);
1038                 r->bge_len1 = segs[1].ds_len;
1039                 sc->bge_cdata.bge_rx_jumbo_seglen[i][1] = segs[1].ds_len;
1040         case 1:
1041                 r->bge_addr0.bge_addr_lo = BGE_ADDR_LO(segs[0].ds_addr);
1042                 r->bge_addr0.bge_addr_hi = BGE_ADDR_HI(segs[0].ds_addr);
1043                 r->bge_len0 = segs[0].ds_len;
1044                 sc->bge_cdata.bge_rx_jumbo_seglen[i][0] = segs[0].ds_len;
1045                 break;
1046         default:
1047                 panic("%s: %d segments\n", __func__, nsegs);
1048         }
1049
1050         bus_dmamap_sync(sc->bge_cdata.bge_mtag_jumbo,
1051             sc->bge_cdata.bge_rx_jumbo_dmamap[i], BUS_DMASYNC_PREREAD);
1052
1053         return (0);
1054 }
1055
1056 static int
1057 bge_init_rx_ring_std(struct bge_softc *sc)
1058 {
1059         int error, i;
1060
1061         bzero(sc->bge_ldata.bge_rx_std_ring, BGE_STD_RX_RING_SZ);
1062         sc->bge_std = 0;
1063         for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
1064                 if ((error = bge_newbuf_std(sc, i)) != 0)
1065                         return (error);
1066                 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT);
1067         };
1068
1069         bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
1070             sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREWRITE);
1071
1072         sc->bge_std = 0;
1073         bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, BGE_STD_RX_RING_CNT - 1);
1074
1075         return (0);
1076 }
1077
1078 static void
1079 bge_free_rx_ring_std(struct bge_softc *sc)
1080 {
1081         int i;
1082
1083         for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
1084                 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) {
1085                         bus_dmamap_sync(sc->bge_cdata.bge_rx_mtag,
1086                             sc->bge_cdata.bge_rx_std_dmamap[i],
1087                             BUS_DMASYNC_POSTREAD);
1088                         bus_dmamap_unload(sc->bge_cdata.bge_rx_mtag,
1089                             sc->bge_cdata.bge_rx_std_dmamap[i]);
1090                         m_freem(sc->bge_cdata.bge_rx_std_chain[i]);
1091                         sc->bge_cdata.bge_rx_std_chain[i] = NULL;
1092                 }
1093                 bzero((char *)&sc->bge_ldata.bge_rx_std_ring[i],
1094                     sizeof(struct bge_rx_bd));
1095         }
1096 }
1097
1098 static int
1099 bge_init_rx_ring_jumbo(struct bge_softc *sc)
1100 {
1101         struct bge_rcb *rcb;
1102         int error, i;
1103
1104         bzero(sc->bge_ldata.bge_rx_jumbo_ring, BGE_JUMBO_RX_RING_SZ);
1105         sc->bge_jumbo = 0;
1106         for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
1107                 if ((error = bge_newbuf_jumbo(sc, i)) != 0)
1108                         return (error);
1109                 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT);
1110         };
1111
1112         bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
1113             sc->bge_cdata.bge_rx_jumbo_ring_map, BUS_DMASYNC_PREWRITE);
1114
1115         sc->bge_jumbo = 0;
1116
1117         rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb;
1118         rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0,
1119                                     BGE_RCB_FLAG_USE_EXT_RX_BD);
1120         CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
1121
1122         bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, BGE_JUMBO_RX_RING_CNT - 1);
1123
1124         return (0);
1125 }
1126
1127 static void
1128 bge_free_rx_ring_jumbo(struct bge_softc *sc)
1129 {
1130         int i;
1131
1132         for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
1133                 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) {
1134                         bus_dmamap_sync(sc->bge_cdata.bge_mtag_jumbo,
1135                             sc->bge_cdata.bge_rx_jumbo_dmamap[i],
1136                             BUS_DMASYNC_POSTREAD);
1137                         bus_dmamap_unload(sc->bge_cdata.bge_mtag_jumbo,
1138                             sc->bge_cdata.bge_rx_jumbo_dmamap[i]);
1139                         m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]);
1140                         sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL;
1141                 }
1142                 bzero((char *)&sc->bge_ldata.bge_rx_jumbo_ring[i],
1143                     sizeof(struct bge_extrx_bd));
1144         }
1145 }
1146
1147 static void
1148 bge_free_tx_ring(struct bge_softc *sc)
1149 {
1150         int i;
1151
1152         if (sc->bge_ldata.bge_tx_ring == NULL)
1153                 return;
1154
1155         for (i = 0; i < BGE_TX_RING_CNT; i++) {
1156                 if (sc->bge_cdata.bge_tx_chain[i] != NULL) {
1157                         bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag,
1158                             sc->bge_cdata.bge_tx_dmamap[i],
1159                             BUS_DMASYNC_POSTWRITE);
1160                         bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag,
1161                             sc->bge_cdata.bge_tx_dmamap[i]);
1162                         m_freem(sc->bge_cdata.bge_tx_chain[i]);
1163                         sc->bge_cdata.bge_tx_chain[i] = NULL;
1164                 }
1165                 bzero((char *)&sc->bge_ldata.bge_tx_ring[i],
1166                     sizeof(struct bge_tx_bd));
1167         }
1168 }
1169
1170 static int
1171 bge_init_tx_ring(struct bge_softc *sc)
1172 {
1173         sc->bge_txcnt = 0;
1174         sc->bge_tx_saved_considx = 0;
1175
1176         bzero(sc->bge_ldata.bge_tx_ring, BGE_TX_RING_SZ);
1177         bus_dmamap_sync(sc->bge_cdata.bge_tx_ring_tag,
1178             sc->bge_cdata.bge_tx_ring_map, BUS_DMASYNC_PREWRITE);
1179
1180         /* Initialize transmit producer index for host-memory send ring. */
1181         sc->bge_tx_prodidx = 0;
1182         bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx);
1183
1184         /* 5700 b2 errata */
1185         if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
1186                 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx);
1187
1188         /* NIC-memory send ring not used; initialize to zero. */
1189         bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);
1190         /* 5700 b2 errata */
1191         if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
1192                 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);
1193
1194         return (0);
1195 }
1196
1197 static void
1198 bge_setpromisc(struct bge_softc *sc)
1199 {
1200         struct ifnet *ifp;
1201
1202         BGE_LOCK_ASSERT(sc);
1203
1204         ifp = sc->bge_ifp;
1205
1206         /* Enable or disable promiscuous mode as needed. */
1207         if (ifp->if_flags & IFF_PROMISC)
1208                 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
1209         else
1210                 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
1211 }
1212
1213 static void
1214 bge_setmulti(struct bge_softc *sc)
1215 {
1216         struct ifnet *ifp;
1217         struct ifmultiaddr *ifma;
1218         uint32_t hashes[4] = { 0, 0, 0, 0 };
1219         int h, i;
1220
1221         BGE_LOCK_ASSERT(sc);
1222
1223         ifp = sc->bge_ifp;
1224
1225         if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
1226                 for (i = 0; i < 4; i++)
1227                         CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0xFFFFFFFF);
1228                 return;
1229         }
1230
1231         /* First, zot all the existing filters. */
1232         for (i = 0; i < 4; i++)
1233                 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0);
1234
1235         /* Now program new ones. */
1236         if_maddr_rlock(ifp);
1237         TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1238                 if (ifma->ifma_addr->sa_family != AF_LINK)
1239                         continue;
1240                 h = ether_crc32_le(LLADDR((struct sockaddr_dl *)
1241                     ifma->ifma_addr), ETHER_ADDR_LEN) & 0x7F;
1242                 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F);
1243         }
1244         if_maddr_runlock(ifp);
1245
1246         for (i = 0; i < 4; i++)
1247                 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]);
1248 }
1249
1250 static void
1251 bge_setvlan(struct bge_softc *sc)
1252 {
1253         struct ifnet *ifp;
1254
1255         BGE_LOCK_ASSERT(sc);
1256
1257         ifp = sc->bge_ifp;
1258
1259         /* Enable or disable VLAN tag stripping as needed. */
1260         if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING)
1261                 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_KEEP_VLAN_DIAG);
1262         else
1263                 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_KEEP_VLAN_DIAG);
1264 }
1265
1266 static void
1267 bge_sig_pre_reset(sc, type)
1268         struct bge_softc *sc;
1269         int type;
1270 {
1271         /*
1272          * Some chips don't like this so only do this if ASF is enabled
1273          */
1274         if (sc->bge_asf_mode)
1275                 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER);
1276
1277         if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) {
1278                 switch (type) {
1279                 case BGE_RESET_START:
1280                         bge_writemem_ind(sc, BGE_SDI_STATUS, 0x1); /* START */
1281                         break;
1282                 case BGE_RESET_STOP:
1283                         bge_writemem_ind(sc, BGE_SDI_STATUS, 0x2); /* UNLOAD */
1284                         break;
1285                 }
1286         }
1287 }
1288
1289 static void
1290 bge_sig_post_reset(sc, type)
1291         struct bge_softc *sc;
1292         int type;
1293 {
1294         if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) {
1295                 switch (type) {
1296                 case BGE_RESET_START:
1297                         bge_writemem_ind(sc, BGE_SDI_STATUS, 0x80000001);
1298                         /* START DONE */
1299                         break;
1300                 case BGE_RESET_STOP:
1301                         bge_writemem_ind(sc, BGE_SDI_STATUS, 0x80000002);
1302                         break;
1303                 }
1304         }
1305 }
1306
1307 static void
1308 bge_sig_legacy(sc, type)
1309         struct bge_softc *sc;
1310         int type;
1311 {
1312         if (sc->bge_asf_mode) {
1313                 switch (type) {
1314                 case BGE_RESET_START:
1315                         bge_writemem_ind(sc, BGE_SDI_STATUS, 0x1); /* START */
1316                         break;
1317                 case BGE_RESET_STOP:
1318                         bge_writemem_ind(sc, BGE_SDI_STATUS, 0x2); /* UNLOAD */
1319                         break;
1320                 }
1321         }
1322 }
1323
1324 void bge_stop_fw(struct bge_softc *);
1325 void
1326 bge_stop_fw(sc)
1327         struct bge_softc *sc;
1328 {
1329         int i;
1330
1331         if (sc->bge_asf_mode) {
1332                 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM_FW, BGE_FW_PAUSE);
1333                 CSR_WRITE_4(sc, BGE_CPU_EVENT,
1334                     CSR_READ_4(sc, BGE_CPU_EVENT) | (1 << 14));
1335
1336                 for (i = 0; i < 100; i++ ) {
1337                         if (!(CSR_READ_4(sc, BGE_CPU_EVENT) & (1 << 14)))
1338                                 break;
1339                         DELAY(10);
1340                 }
1341         }
1342 }
1343
1344 /*
1345  * Do endian, PCI and DMA initialization.
1346  */
1347 static int
1348 bge_chipinit(struct bge_softc *sc)
1349 {
1350         uint32_t dma_rw_ctl;
1351         uint16_t val;
1352         int i;
1353
1354         /* Set endianness before we access any non-PCI registers. */
1355         pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL, BGE_INIT, 4);
1356
1357         /* Clear the MAC control register */
1358         CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
1359
1360         /*
1361          * Clear the MAC statistics block in the NIC's
1362          * internal memory.
1363          */
1364         for (i = BGE_STATS_BLOCK;
1365             i < BGE_STATS_BLOCK_END + 1; i += sizeof(uint32_t))
1366                 BGE_MEMWIN_WRITE(sc, i, 0);
1367
1368         for (i = BGE_STATUS_BLOCK;
1369             i < BGE_STATUS_BLOCK_END + 1; i += sizeof(uint32_t))
1370                 BGE_MEMWIN_WRITE(sc, i, 0);
1371
1372         if (sc->bge_chiprev == BGE_CHIPREV_5704_BX) {
1373                 /*
1374                  *  Fix data corruption caused by non-qword write with WB.
1375                  *  Fix master abort in PCI mode.
1376                  *  Fix PCI latency timer.
1377                  */
1378                 val = pci_read_config(sc->bge_dev, BGE_PCI_MSI_DATA + 2, 2);
1379                 val |= (1 << 10) | (1 << 12) | (1 << 13);
1380                 pci_write_config(sc->bge_dev, BGE_PCI_MSI_DATA + 2, val, 2);
1381         }
1382
1383         /*
1384          * Set up the PCI DMA control register.
1385          */
1386         dma_rw_ctl = BGE_PCIDMARWCTL_RD_CMD_SHIFT(6) |
1387             BGE_PCIDMARWCTL_WR_CMD_SHIFT(7);
1388         if (sc->bge_flags & BGE_FLAG_PCIE) {
1389                 /* Read watermark not used, 128 bytes for write. */
1390                 dma_rw_ctl |= BGE_PCIDMARWCTL_WR_WAT_SHIFT(3);
1391         } else if (sc->bge_flags & BGE_FLAG_PCIX) {
1392                 if (BGE_IS_5714_FAMILY(sc)) {
1393                         /* 256 bytes for read and write. */
1394                         dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(2) |
1395                             BGE_PCIDMARWCTL_WR_WAT_SHIFT(2);
1396                         dma_rw_ctl |= (sc->bge_asicrev == BGE_ASICREV_BCM5780) ?
1397                             BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL :
1398                             BGE_PCIDMARWCTL_ONEDMA_ATONCE_LOCAL;
1399                 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5703) {
1400                         /*
1401                          * In the BCM5703, the DMA read watermark should
1402                          * be set to less than or equal to the maximum
1403                          * memory read byte count of the PCI-X command
1404                          * register.
1405                          */
1406                         dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(4) |
1407                             BGE_PCIDMARWCTL_WR_WAT_SHIFT(3);
1408                 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
1409                         /* 1536 bytes for read, 384 bytes for write. */
1410                         dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) |
1411                             BGE_PCIDMARWCTL_WR_WAT_SHIFT(3);
1412                 } else {
1413                         /* 384 bytes for read and write. */
1414                         dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(3) |
1415                             BGE_PCIDMARWCTL_WR_WAT_SHIFT(3) |
1416                             0x0F;
1417                 }
1418                 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 ||
1419                     sc->bge_asicrev == BGE_ASICREV_BCM5704) {
1420                         uint32_t tmp;
1421
1422                         /* Set ONE_DMA_AT_ONCE for hardware workaround. */
1423                         tmp = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1F;
1424                         if (tmp == 6 || tmp == 7)
1425                                 dma_rw_ctl |=
1426                                     BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL;
1427
1428                         /* Set PCI-X DMA write workaround. */
1429                         dma_rw_ctl |= BGE_PCIDMARWCTL_ASRT_ALL_BE;
1430                 }
1431         } else {
1432                 /* Conventional PCI bus: 256 bytes for read and write. */
1433                 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) |
1434                     BGE_PCIDMARWCTL_WR_WAT_SHIFT(7);
1435
1436                 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
1437                     sc->bge_asicrev != BGE_ASICREV_BCM5750)
1438                         dma_rw_ctl |= 0x0F;
1439         }
1440         if (sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
1441             sc->bge_asicrev == BGE_ASICREV_BCM5701)
1442                 dma_rw_ctl |= BGE_PCIDMARWCTL_USE_MRM |
1443                     BGE_PCIDMARWCTL_ASRT_ALL_BE;
1444         if (sc->bge_asicrev == BGE_ASICREV_BCM5703 ||
1445             sc->bge_asicrev == BGE_ASICREV_BCM5704)
1446                 dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA;
1447         pci_write_config(sc->bge_dev, BGE_PCI_DMA_RW_CTL, dma_rw_ctl, 4);
1448
1449         /*
1450          * Set up general mode register.
1451          */
1452         CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS |
1453             BGE_MODECTL_MAC_ATTN_INTR | BGE_MODECTL_HOST_SEND_BDS |
1454             BGE_MODECTL_TX_NO_PHDR_CSUM);
1455
1456         /*
1457          * BCM5701 B5 have a bug causing data corruption when using
1458          * 64-bit DMA reads, which can be terminated early and then
1459          * completed later as 32-bit accesses, in combination with
1460          * certain bridges.
1461          */
1462         if (sc->bge_asicrev == BGE_ASICREV_BCM5701 &&
1463             sc->bge_chipid == BGE_CHIPID_BCM5701_B5)
1464                 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_FORCE_PCI32);
1465
1466         /*
1467          * Tell the firmware the driver is running
1468          */
1469         if (sc->bge_asf_mode & ASF_STACKUP)
1470                 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
1471
1472         /*
1473          * Disable memory write invalidate.  Apparently it is not supported
1474          * properly by these devices.  Also ensure that INTx isn't disabled,
1475          * as these chips need it even when using MSI.
1476          */
1477         PCI_CLRBIT(sc->bge_dev, BGE_PCI_CMD,
1478             PCIM_CMD_INTxDIS | PCIM_CMD_MWIEN, 4);
1479
1480         /* Set the timer prescaler (always 66Mhz) */
1481         CSR_WRITE_4(sc, BGE_MISC_CFG, BGE_32BITTIME_66MHZ);
1482
1483         /* XXX: The Linux tg3 driver does this at the start of brgphy_reset. */
1484         if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
1485                 DELAY(40);      /* XXX */
1486
1487                 /* Put PHY into ready state */
1488                 BGE_CLRBIT(sc, BGE_MISC_CFG, BGE_MISCCFG_EPHY_IDDQ);
1489                 CSR_READ_4(sc, BGE_MISC_CFG); /* Flush */
1490                 DELAY(40);
1491         }
1492
1493         return (0);
1494 }
1495
1496 static int
1497 bge_blockinit(struct bge_softc *sc)
1498 {
1499         struct bge_rcb *rcb;
1500         bus_size_t vrcb;
1501         bge_hostaddr taddr;
1502         uint32_t val;
1503         int i;
1504
1505         /*
1506          * Initialize the memory window pointer register so that
1507          * we can access the first 32K of internal NIC RAM. This will
1508          * allow us to set up the TX send ring RCBs and the RX return
1509          * ring RCBs, plus other things which live in NIC memory.
1510          */
1511         CSR_WRITE_4(sc, BGE_PCI_MEMWIN_BASEADDR, 0);
1512
1513         /* Note: the BCM5704 has a smaller mbuf space than other chips. */
1514
1515         if (!(BGE_IS_5705_PLUS(sc))) {
1516                 /* Configure mbuf memory pool */
1517                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, BGE_BUFFPOOL_1);
1518                 if (sc->bge_asicrev == BGE_ASICREV_BCM5704)
1519                         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000);
1520                 else
1521                         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000);
1522
1523                 /* Configure DMA resource pool */
1524                 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR,
1525                     BGE_DMA_DESCRIPTORS);
1526                 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000);
1527         }
1528
1529         /* Configure mbuf pool watermarks */
1530         if (!BGE_IS_5705_PLUS(sc)) {
1531                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50);
1532                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20);
1533                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60);
1534         } else if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
1535                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
1536                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x04);
1537                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x10);
1538         } else {
1539                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
1540                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10);
1541                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60);
1542         }
1543
1544         /* Configure DMA resource watermarks */
1545         CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5);
1546         CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10);
1547
1548         /* Enable buffer manager */
1549         if (!(BGE_IS_5705_PLUS(sc))) {
1550                 CSR_WRITE_4(sc, BGE_BMAN_MODE,
1551                     BGE_BMANMODE_ENABLE | BGE_BMANMODE_LOMBUF_ATTN);
1552
1553                 /* Poll for buffer manager start indication */
1554                 for (i = 0; i < BGE_TIMEOUT; i++) {
1555                         DELAY(10);
1556                         if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE)
1557                                 break;
1558                 }
1559
1560                 if (i == BGE_TIMEOUT) {
1561                         device_printf(sc->bge_dev,
1562                             "buffer manager failed to start\n");
1563                         return (ENXIO);
1564                 }
1565         }
1566
1567         /* Enable flow-through queues */
1568         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
1569         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
1570
1571         /* Wait until queue initialization is complete */
1572         for (i = 0; i < BGE_TIMEOUT; i++) {
1573                 DELAY(10);
1574                 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0)
1575                         break;
1576         }
1577
1578         if (i == BGE_TIMEOUT) {
1579                 device_printf(sc->bge_dev, "flow-through queue init failed\n");
1580                 return (ENXIO);
1581         }
1582
1583         /* Initialize the standard RX ring control block */
1584         rcb = &sc->bge_ldata.bge_info.bge_std_rx_rcb;
1585         rcb->bge_hostaddr.bge_addr_lo =
1586             BGE_ADDR_LO(sc->bge_ldata.bge_rx_std_ring_paddr);
1587         rcb->bge_hostaddr.bge_addr_hi =
1588             BGE_ADDR_HI(sc->bge_ldata.bge_rx_std_ring_paddr);
1589         bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
1590             sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREREAD);
1591         if (BGE_IS_5705_PLUS(sc))
1592                 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0);
1593         else
1594                 rcb->bge_maxlen_flags =
1595                     BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0);
1596         rcb->bge_nicaddr = BGE_STD_RX_RINGS;
1597         CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi);
1598         CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo);
1599
1600         CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
1601         CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr);
1602
1603         /*
1604          * Initialize the jumbo RX ring control block
1605          * We set the 'ring disabled' bit in the flags
1606          * field until we're actually ready to start
1607          * using this ring (i.e. once we set the MTU
1608          * high enough to require it).
1609          */
1610         if (BGE_IS_JUMBO_CAPABLE(sc)) {
1611                 rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb;
1612
1613                 rcb->bge_hostaddr.bge_addr_lo =
1614                     BGE_ADDR_LO(sc->bge_ldata.bge_rx_jumbo_ring_paddr);
1615                 rcb->bge_hostaddr.bge_addr_hi =
1616                     BGE_ADDR_HI(sc->bge_ldata.bge_rx_jumbo_ring_paddr);
1617                 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
1618                     sc->bge_cdata.bge_rx_jumbo_ring_map,
1619                     BUS_DMASYNC_PREREAD);
1620                 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0,
1621                     BGE_RCB_FLAG_USE_EXT_RX_BD | BGE_RCB_FLAG_RING_DISABLED);
1622                 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS;
1623                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI,
1624                     rcb->bge_hostaddr.bge_addr_hi);
1625                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO,
1626                     rcb->bge_hostaddr.bge_addr_lo);
1627
1628                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS,
1629                     rcb->bge_maxlen_flags);
1630                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr);
1631
1632                 /* Set up dummy disabled mini ring RCB */
1633                 rcb = &sc->bge_ldata.bge_info.bge_mini_rx_rcb;
1634                 rcb->bge_maxlen_flags =
1635                     BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED);
1636                 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS,
1637                     rcb->bge_maxlen_flags);
1638         }
1639
1640         /*
1641          * Set the BD ring replentish thresholds. The recommended
1642          * values are 1/8th the number of descriptors allocated to
1643          * each ring.
1644          * XXX The 5754 requires a lower threshold, so it might be a
1645          * requirement of all 575x family chips.  The Linux driver sets
1646          * the lower threshold for all 5705 family chips as well, but there
1647          * are reports that it might not need to be so strict.
1648          *
1649          * XXX Linux does some extra fiddling here for the 5906 parts as
1650          * well.
1651          */
1652         if (BGE_IS_5705_PLUS(sc))
1653                 val = 8;
1654         else
1655                 val = BGE_STD_RX_RING_CNT / 8;
1656         CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, val);
1657         if (BGE_IS_JUMBO_CAPABLE(sc))
1658                 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH,
1659                     BGE_JUMBO_RX_RING_CNT/8);
1660
1661         /*
1662          * Disable all unused send rings by setting the 'ring disabled'
1663          * bit in the flags field of all the TX send ring control blocks.
1664          * These are located in NIC memory.
1665          */
1666         vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
1667         for (i = 0; i < BGE_TX_RINGS_EXTSSRAM_MAX; i++) {
1668                 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1669                     BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED));
1670                 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
1671                 vrcb += sizeof(struct bge_rcb);
1672         }
1673
1674         /* Configure TX RCB 0 (we use only the first ring) */
1675         vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
1676         BGE_HOSTADDR(taddr, sc->bge_ldata.bge_tx_ring_paddr);
1677         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
1678         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
1679         RCB_WRITE_4(sc, vrcb, bge_nicaddr,
1680             BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT));
1681         if (!(BGE_IS_5705_PLUS(sc)))
1682                 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1683                     BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0));
1684
1685         /* Disable all unused RX return rings */
1686         vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
1687         for (i = 0; i < BGE_RX_RINGS_MAX; i++) {
1688                 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, 0);
1689                 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, 0);
1690                 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1691                     BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt,
1692                     BGE_RCB_FLAG_RING_DISABLED));
1693                 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
1694                 bge_writembx(sc, BGE_MBX_RX_CONS0_LO +
1695                     (i * (sizeof(uint64_t))), 0);
1696                 vrcb += sizeof(struct bge_rcb);
1697         }
1698
1699         /* Initialize RX ring indexes */
1700         bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, 0);
1701         if (BGE_IS_JUMBO_CAPABLE(sc))
1702                 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0);
1703         if (sc->bge_asicrev == BGE_ASICREV_BCM5700)
1704                 bge_writembx(sc, BGE_MBX_RX_MINI_PROD_LO, 0);
1705
1706         /*
1707          * Set up RX return ring 0
1708          * Note that the NIC address for RX return rings is 0x00000000.
1709          * The return rings live entirely within the host, so the
1710          * nicaddr field in the RCB isn't used.
1711          */
1712         vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
1713         BGE_HOSTADDR(taddr, sc->bge_ldata.bge_rx_return_ring_paddr);
1714         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
1715         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
1716         RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0x00000000);
1717         RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1718             BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0));
1719
1720         /* Set random backoff seed for TX */
1721         CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF,
1722             IF_LLADDR(sc->bge_ifp)[0] + IF_LLADDR(sc->bge_ifp)[1] +
1723             IF_LLADDR(sc->bge_ifp)[2] + IF_LLADDR(sc->bge_ifp)[3] +
1724             IF_LLADDR(sc->bge_ifp)[4] + IF_LLADDR(sc->bge_ifp)[5] +
1725             BGE_TX_BACKOFF_SEED_MASK);
1726
1727         /* Set inter-packet gap */
1728         CSR_WRITE_4(sc, BGE_TX_LENGTHS, 0x2620);
1729
1730         /*
1731          * Specify which ring to use for packets that don't match
1732          * any RX rules.
1733          */
1734         CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08);
1735
1736         /*
1737          * Configure number of RX lists. One interrupt distribution
1738          * list, sixteen active lists, one bad frames class.
1739          */
1740         CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181);
1741
1742         /* Inialize RX list placement stats mask. */
1743         CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF);
1744         CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1);
1745
1746         /* Disable host coalescing until we get it set up */
1747         CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000);
1748
1749         /* Poll to make sure it's shut down. */
1750         for (i = 0; i < BGE_TIMEOUT; i++) {
1751                 DELAY(10);
1752                 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE))
1753                         break;
1754         }
1755
1756         if (i == BGE_TIMEOUT) {
1757                 device_printf(sc->bge_dev,
1758                     "host coalescing engine failed to idle\n");
1759                 return (ENXIO);
1760         }
1761
1762         /* Set up host coalescing defaults */
1763         CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks);
1764         CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks);
1765         CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds);
1766         CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds);
1767         if (!(BGE_IS_5705_PLUS(sc))) {
1768                 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0);
1769                 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0);
1770         }
1771         CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 1);
1772         CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 1);
1773
1774         /* Set up address of statistics block */
1775         if (!(BGE_IS_5705_PLUS(sc))) {
1776                 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI,
1777                     BGE_ADDR_HI(sc->bge_ldata.bge_stats_paddr));
1778                 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO,
1779                     BGE_ADDR_LO(sc->bge_ldata.bge_stats_paddr));
1780                 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK);
1781                 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK);
1782                 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks);
1783         }
1784
1785         /* Set up address of status block */
1786         CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI,
1787             BGE_ADDR_HI(sc->bge_ldata.bge_status_block_paddr));
1788         CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO,
1789             BGE_ADDR_LO(sc->bge_ldata.bge_status_block_paddr));
1790         sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx = 0;
1791         sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx = 0;
1792
1793         /* Set up status block size. */
1794         if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
1795             sc->bge_chipid != BGE_CHIPID_BCM5700_C0)
1796                 val = BGE_STATBLKSZ_FULL;
1797         else
1798                 val = BGE_STATBLKSZ_32BYTE;
1799
1800         /* Turn on host coalescing state machine */
1801         CSR_WRITE_4(sc, BGE_HCC_MODE, val | BGE_HCCMODE_ENABLE);
1802
1803         /* Turn on RX BD completion state machine and enable attentions */
1804         CSR_WRITE_4(sc, BGE_RBDC_MODE,
1805             BGE_RBDCMODE_ENABLE | BGE_RBDCMODE_ATTN);
1806
1807         /* Turn on RX list placement state machine */
1808         CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
1809
1810         /* Turn on RX list selector state machine. */
1811         if (!(BGE_IS_5705_PLUS(sc)))
1812                 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
1813
1814         val = BGE_MACMODE_TXDMA_ENB | BGE_MACMODE_RXDMA_ENB |
1815             BGE_MACMODE_RX_STATS_CLEAR | BGE_MACMODE_TX_STATS_CLEAR |
1816             BGE_MACMODE_RX_STATS_ENB | BGE_MACMODE_TX_STATS_ENB |
1817             BGE_MACMODE_FRMHDR_DMA_ENB;
1818
1819         if (sc->bge_flags & BGE_FLAG_TBI)
1820                 val |= BGE_PORTMODE_TBI;
1821         else if (sc->bge_flags & BGE_FLAG_MII_SERDES)
1822                 val |= BGE_PORTMODE_GMII;
1823         else
1824                 val |= BGE_PORTMODE_MII;
1825
1826         /* Turn on DMA, clear stats */
1827         CSR_WRITE_4(sc, BGE_MAC_MODE, val);
1828
1829         /* Set misc. local control, enable interrupts on attentions */
1830         CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN);
1831
1832 #ifdef notdef
1833         /* Assert GPIO pins for PHY reset */
1834         BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0 |
1835             BGE_MLC_MISCIO_OUT1 | BGE_MLC_MISCIO_OUT2);
1836         BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0 |
1837             BGE_MLC_MISCIO_OUTEN1 | BGE_MLC_MISCIO_OUTEN2);
1838 #endif
1839
1840         /* Turn on DMA completion state machine */
1841         if (!(BGE_IS_5705_PLUS(sc)))
1842                 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
1843
1844         val = BGE_WDMAMODE_ENABLE | BGE_WDMAMODE_ALL_ATTNS;
1845
1846         /* Enable host coalescing bug fix. */
1847         if (BGE_IS_5755_PLUS(sc))
1848                 val |= BGE_WDMAMODE_STATUS_TAG_FIX;
1849
1850         /* Turn on write DMA state machine */
1851         CSR_WRITE_4(sc, BGE_WDMA_MODE, val);
1852         DELAY(40);
1853
1854         /* Turn on read DMA state machine */
1855         val = BGE_RDMAMODE_ENABLE | BGE_RDMAMODE_ALL_ATTNS;
1856         if (sc->bge_asicrev == BGE_ASICREV_BCM5784 ||
1857             sc->bge_asicrev == BGE_ASICREV_BCM5785 ||
1858             sc->bge_asicrev == BGE_ASICREV_BCM57780)
1859                 val |= BGE_RDMAMODE_BD_SBD_CRPT_ATTN |
1860                     BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN |
1861                     BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN;
1862         if (sc->bge_flags & BGE_FLAG_PCIE)
1863                 val |= BGE_RDMAMODE_FIFO_LONG_BURST;
1864         if (sc->bge_flags & BGE_FLAG_TSO)
1865                 val |= BGE_RDMAMODE_TSO4_ENABLE;
1866         CSR_WRITE_4(sc, BGE_RDMA_MODE, val);
1867         DELAY(40);
1868
1869         /* Turn on RX data completion state machine */
1870         CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
1871
1872         /* Turn on RX BD initiator state machine */
1873         CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
1874
1875         /* Turn on RX data and RX BD initiator state machine */
1876         CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE);
1877
1878         /* Turn on Mbuf cluster free state machine */
1879         if (!(BGE_IS_5705_PLUS(sc)))
1880                 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
1881
1882         /* Turn on send BD completion state machine */
1883         CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
1884
1885         /* Turn on send data completion state machine */
1886         val = BGE_SDCMODE_ENABLE;
1887         if (sc->bge_asicrev == BGE_ASICREV_BCM5761)
1888                 val |= BGE_SDCMODE_CDELAY;
1889         CSR_WRITE_4(sc, BGE_SDC_MODE, val);
1890
1891         /* Turn on send data initiator state machine */
1892         if (sc->bge_flags & BGE_FLAG_TSO)
1893                 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE | 0x08);
1894         else
1895                 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
1896
1897         /* Turn on send BD initiator state machine */
1898         CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
1899
1900         /* Turn on send BD selector state machine */
1901         CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
1902
1903         CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF);
1904         CSR_WRITE_4(sc, BGE_SDI_STATS_CTL,
1905             BGE_SDISTATSCTL_ENABLE | BGE_SDISTATSCTL_FASTER);
1906
1907         /* ack/clear link change events */
1908         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
1909             BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
1910             BGE_MACSTAT_LINK_CHANGED);
1911         CSR_WRITE_4(sc, BGE_MI_STS, 0);
1912
1913         /* Enable PHY auto polling (for MII/GMII only) */
1914         if (sc->bge_flags & BGE_FLAG_TBI) {
1915                 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK);
1916         } else {
1917                 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL | (10 << 16));
1918                 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
1919                     sc->bge_chipid != BGE_CHIPID_BCM5700_B2)
1920                         CSR_WRITE_4(sc, BGE_MAC_EVT_ENB,
1921                             BGE_EVTENB_MI_INTERRUPT);
1922         }
1923
1924         /*
1925          * Clear any pending link state attention.
1926          * Otherwise some link state change events may be lost until attention
1927          * is cleared by bge_intr() -> bge_link_upd() sequence.
1928          * It's not necessary on newer BCM chips - perhaps enabling link
1929          * state change attentions implies clearing pending attention.
1930          */
1931         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
1932             BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
1933             BGE_MACSTAT_LINK_CHANGED);
1934
1935         /* Enable link state change attentions. */
1936         BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED);
1937
1938         return (0);
1939 }
1940
1941 const struct bge_revision *
1942 bge_lookup_rev(uint32_t chipid)
1943 {
1944         const struct bge_revision *br;
1945
1946         for (br = bge_revisions; br->br_name != NULL; br++) {
1947                 if (br->br_chipid == chipid)
1948                         return (br);
1949         }
1950
1951         for (br = bge_majorrevs; br->br_name != NULL; br++) {
1952                 if (br->br_chipid == BGE_ASICREV(chipid))
1953                         return (br);
1954         }
1955
1956         return (NULL);
1957 }
1958
1959 const struct bge_vendor *
1960 bge_lookup_vendor(uint16_t vid)
1961 {
1962         const struct bge_vendor *v;
1963
1964         for (v = bge_vendors; v->v_name != NULL; v++)
1965                 if (v->v_id == vid)
1966                         return (v);
1967
1968         panic("%s: unknown vendor %d", __func__, vid);
1969         return (NULL);
1970 }
1971
1972 /*
1973  * Probe for a Broadcom chip. Check the PCI vendor and device IDs
1974  * against our list and return its name if we find a match.
1975  *
1976  * Note that since the Broadcom controller contains VPD support, we
1977  * try to get the device name string from the controller itself instead
1978  * of the compiled-in string. It guarantees we'll always announce the
1979  * right product name. We fall back to the compiled-in string when
1980  * VPD is unavailable or corrupt.
1981  */
1982 static int
1983 bge_probe(device_t dev)
1984 {
1985         const struct bge_type *t = bge_devs;
1986         struct bge_softc *sc = device_get_softc(dev);
1987         uint16_t vid, did;
1988
1989         sc->bge_dev = dev;
1990         vid = pci_get_vendor(dev);
1991         did = pci_get_device(dev);
1992         while(t->bge_vid != 0) {
1993                 if ((vid == t->bge_vid) && (did == t->bge_did)) {
1994                         char model[64], buf[96];
1995                         const struct bge_revision *br;
1996                         const struct bge_vendor *v;
1997                         uint32_t id;
1998
1999                         id = pci_read_config(dev, BGE_PCI_MISC_CTL, 4) >>
2000                             BGE_PCIMISCCTL_ASICREV_SHIFT;
2001                         if (BGE_ASICREV(id) == BGE_ASICREV_USE_PRODID_REG)
2002                                 id = pci_read_config(dev,
2003                                     BGE_PCI_PRODID_ASICREV, 4);
2004                         br = bge_lookup_rev(id);
2005                         v = bge_lookup_vendor(vid);
2006                         {
2007 #if __FreeBSD_version > 700024
2008                                 const char *pname;
2009
2010                                 if (bge_has_eaddr(sc) &&
2011                                     pci_get_vpd_ident(dev, &pname) == 0)
2012                                         snprintf(model, 64, "%s", pname);
2013                                 else
2014 #endif
2015                                         snprintf(model, 64, "%s %s",
2016                                             v->v_name,
2017                                             br != NULL ? br->br_name :
2018                                             "NetXtreme Ethernet Controller");
2019                         }
2020                         snprintf(buf, 96, "%s, %sASIC rev. %#08x", model,
2021                             br != NULL ? "" : "unknown ", id);
2022                         device_set_desc_copy(dev, buf);
2023                         return (0);
2024                 }
2025                 t++;
2026         }
2027
2028         return (ENXIO);
2029 }
2030
2031 static void
2032 bge_dma_free(struct bge_softc *sc)
2033 {
2034         int i;
2035
2036         /* Destroy DMA maps for RX buffers. */
2037         for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
2038                 if (sc->bge_cdata.bge_rx_std_dmamap[i])
2039                         bus_dmamap_destroy(sc->bge_cdata.bge_rx_mtag,
2040                             sc->bge_cdata.bge_rx_std_dmamap[i]);
2041         }
2042         if (sc->bge_cdata.bge_rx_std_sparemap)
2043                 bus_dmamap_destroy(sc->bge_cdata.bge_rx_mtag,
2044                     sc->bge_cdata.bge_rx_std_sparemap);
2045
2046         /* Destroy DMA maps for jumbo RX buffers. */
2047         for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
2048                 if (sc->bge_cdata.bge_rx_jumbo_dmamap[i])
2049                         bus_dmamap_destroy(sc->bge_cdata.bge_mtag_jumbo,
2050                             sc->bge_cdata.bge_rx_jumbo_dmamap[i]);
2051         }
2052         if (sc->bge_cdata.bge_rx_jumbo_sparemap)
2053                 bus_dmamap_destroy(sc->bge_cdata.bge_mtag_jumbo,
2054                     sc->bge_cdata.bge_rx_jumbo_sparemap);
2055
2056         /* Destroy DMA maps for TX buffers. */
2057         for (i = 0; i < BGE_TX_RING_CNT; i++) {
2058                 if (sc->bge_cdata.bge_tx_dmamap[i])
2059                         bus_dmamap_destroy(sc->bge_cdata.bge_tx_mtag,
2060                             sc->bge_cdata.bge_tx_dmamap[i]);
2061         }
2062
2063         if (sc->bge_cdata.bge_rx_mtag)
2064                 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_mtag);
2065         if (sc->bge_cdata.bge_tx_mtag)
2066                 bus_dma_tag_destroy(sc->bge_cdata.bge_tx_mtag);
2067
2068
2069         /* Destroy standard RX ring. */
2070         if (sc->bge_cdata.bge_rx_std_ring_map)
2071                 bus_dmamap_unload(sc->bge_cdata.bge_rx_std_ring_tag,
2072                     sc->bge_cdata.bge_rx_std_ring_map);
2073         if (sc->bge_cdata.bge_rx_std_ring_map && sc->bge_ldata.bge_rx_std_ring)
2074                 bus_dmamem_free(sc->bge_cdata.bge_rx_std_ring_tag,
2075                     sc->bge_ldata.bge_rx_std_ring,
2076                     sc->bge_cdata.bge_rx_std_ring_map);
2077
2078         if (sc->bge_cdata.bge_rx_std_ring_tag)
2079                 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_std_ring_tag);
2080
2081         /* Destroy jumbo RX ring. */
2082         if (sc->bge_cdata.bge_rx_jumbo_ring_map)
2083                 bus_dmamap_unload(sc->bge_cdata.bge_rx_jumbo_ring_tag,
2084                     sc->bge_cdata.bge_rx_jumbo_ring_map);
2085
2086         if (sc->bge_cdata.bge_rx_jumbo_ring_map &&
2087             sc->bge_ldata.bge_rx_jumbo_ring)
2088                 bus_dmamem_free(sc->bge_cdata.bge_rx_jumbo_ring_tag,
2089                     sc->bge_ldata.bge_rx_jumbo_ring,
2090                     sc->bge_cdata.bge_rx_jumbo_ring_map);
2091
2092         if (sc->bge_cdata.bge_rx_jumbo_ring_tag)
2093                 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_jumbo_ring_tag);
2094
2095         /* Destroy RX return ring. */
2096         if (sc->bge_cdata.bge_rx_return_ring_map)
2097                 bus_dmamap_unload(sc->bge_cdata.bge_rx_return_ring_tag,
2098                     sc->bge_cdata.bge_rx_return_ring_map);
2099
2100         if (sc->bge_cdata.bge_rx_return_ring_map &&
2101             sc->bge_ldata.bge_rx_return_ring)
2102                 bus_dmamem_free(sc->bge_cdata.bge_rx_return_ring_tag,
2103                     sc->bge_ldata.bge_rx_return_ring,
2104                     sc->bge_cdata.bge_rx_return_ring_map);
2105
2106         if (sc->bge_cdata.bge_rx_return_ring_tag)
2107                 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_return_ring_tag);
2108
2109         /* Destroy TX ring. */
2110         if (sc->bge_cdata.bge_tx_ring_map)
2111                 bus_dmamap_unload(sc->bge_cdata.bge_tx_ring_tag,
2112                     sc->bge_cdata.bge_tx_ring_map);
2113
2114         if (sc->bge_cdata.bge_tx_ring_map && sc->bge_ldata.bge_tx_ring)
2115                 bus_dmamem_free(sc->bge_cdata.bge_tx_ring_tag,
2116                     sc->bge_ldata.bge_tx_ring,
2117                     sc->bge_cdata.bge_tx_ring_map);
2118
2119         if (sc->bge_cdata.bge_tx_ring_tag)
2120                 bus_dma_tag_destroy(sc->bge_cdata.bge_tx_ring_tag);
2121
2122         /* Destroy status block. */
2123         if (sc->bge_cdata.bge_status_map)
2124                 bus_dmamap_unload(sc->bge_cdata.bge_status_tag,
2125                     sc->bge_cdata.bge_status_map);
2126
2127         if (sc->bge_cdata.bge_status_map && sc->bge_ldata.bge_status_block)
2128                 bus_dmamem_free(sc->bge_cdata.bge_status_tag,
2129                     sc->bge_ldata.bge_status_block,
2130                     sc->bge_cdata.bge_status_map);
2131
2132         if (sc->bge_cdata.bge_status_tag)
2133                 bus_dma_tag_destroy(sc->bge_cdata.bge_status_tag);
2134
2135         /* Destroy statistics block. */
2136         if (sc->bge_cdata.bge_stats_map)
2137                 bus_dmamap_unload(sc->bge_cdata.bge_stats_tag,
2138                     sc->bge_cdata.bge_stats_map);
2139
2140         if (sc->bge_cdata.bge_stats_map && sc->bge_ldata.bge_stats)
2141                 bus_dmamem_free(sc->bge_cdata.bge_stats_tag,
2142                     sc->bge_ldata.bge_stats,
2143                     sc->bge_cdata.bge_stats_map);
2144
2145         if (sc->bge_cdata.bge_stats_tag)
2146                 bus_dma_tag_destroy(sc->bge_cdata.bge_stats_tag);
2147
2148         /* Destroy the parent tag. */
2149         if (sc->bge_cdata.bge_parent_tag)
2150                 bus_dma_tag_destroy(sc->bge_cdata.bge_parent_tag);
2151 }
2152
2153 static int
2154 bge_dma_alloc(device_t dev)
2155 {
2156         struct bge_dmamap_arg ctx;
2157         struct bge_softc *sc;
2158         bus_addr_t lowaddr;
2159         bus_size_t sbsz, txsegsz, txmaxsegsz;
2160         int i, error;
2161
2162         sc = device_get_softc(dev);
2163
2164         lowaddr = BUS_SPACE_MAXADDR;
2165         if ((sc->bge_flags & BGE_FLAG_40BIT_BUG) != 0)
2166                 lowaddr = BGE_DMA_MAXADDR;
2167         if ((sc->bge_flags & BGE_FLAG_4G_BNDRY_BUG) != 0)
2168                 lowaddr = BUS_SPACE_MAXADDR_32BIT;
2169         /*
2170          * Allocate the parent bus DMA tag appropriate for PCI.
2171          */
2172         error = bus_dma_tag_create(bus_get_dma_tag(sc->bge_dev),
2173             1, 0, lowaddr, BUS_SPACE_MAXADDR, NULL,
2174             NULL, BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT,
2175             0, NULL, NULL, &sc->bge_cdata.bge_parent_tag);
2176
2177         if (error != 0) {
2178                 device_printf(sc->bge_dev,
2179                     "could not allocate parent dma tag\n");
2180                 return (ENOMEM);
2181         }
2182
2183         /*
2184          * Create tag for Tx mbufs.
2185          */
2186         if (sc->bge_flags & BGE_FLAG_TSO) {
2187                 txsegsz = BGE_TSOSEG_SZ;
2188                 txmaxsegsz = 65535 + sizeof(struct ether_vlan_header);
2189         } else {
2190                 txsegsz = MCLBYTES;
2191                 txmaxsegsz = MCLBYTES * BGE_NSEG_NEW;
2192         }
2193         error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 1,
2194             0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
2195             txmaxsegsz, BGE_NSEG_NEW, txsegsz, 0, NULL, NULL,
2196             &sc->bge_cdata.bge_tx_mtag);
2197
2198         if (error) {
2199                 device_printf(sc->bge_dev, "could not allocate TX dma tag\n");
2200                 return (ENOMEM);
2201         }
2202
2203         /*
2204          * Create tag for Rx mbufs.
2205          */
2206         error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 1, 0,
2207             BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 1,
2208             MCLBYTES, 0, NULL, NULL, &sc->bge_cdata.bge_rx_mtag);
2209
2210         if (error) {
2211                 device_printf(sc->bge_dev, "could not allocate RX dma tag\n");
2212                 return (ENOMEM);
2213         }
2214
2215         /* Create DMA maps for RX buffers. */
2216         error = bus_dmamap_create(sc->bge_cdata.bge_rx_mtag, 0,
2217             &sc->bge_cdata.bge_rx_std_sparemap);
2218         if (error) {
2219                 device_printf(sc->bge_dev,
2220                     "can't create spare DMA map for RX\n");
2221                 return (ENOMEM);
2222         }
2223         for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
2224                 error = bus_dmamap_create(sc->bge_cdata.bge_rx_mtag, 0,
2225                             &sc->bge_cdata.bge_rx_std_dmamap[i]);
2226                 if (error) {
2227                         device_printf(sc->bge_dev,
2228                             "can't create DMA map for RX\n");
2229                         return (ENOMEM);
2230                 }
2231         }
2232
2233         /* Create DMA maps for TX buffers. */
2234         for (i = 0; i < BGE_TX_RING_CNT; i++) {
2235                 error = bus_dmamap_create(sc->bge_cdata.bge_tx_mtag, 0,
2236                             &sc->bge_cdata.bge_tx_dmamap[i]);
2237                 if (error) {
2238                         device_printf(sc->bge_dev,
2239                             "can't create DMA map for TX\n");
2240                         return (ENOMEM);
2241                 }
2242         }
2243
2244         /* Create tag for standard RX ring. */
2245         error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag,
2246             PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL,
2247             NULL, BGE_STD_RX_RING_SZ, 1, BGE_STD_RX_RING_SZ, 0,
2248             NULL, NULL, &sc->bge_cdata.bge_rx_std_ring_tag);
2249
2250         if (error) {
2251                 device_printf(sc->bge_dev, "could not allocate dma tag\n");
2252                 return (ENOMEM);
2253         }
2254
2255         /* Allocate DMA'able memory for standard RX ring. */
2256         error = bus_dmamem_alloc(sc->bge_cdata.bge_rx_std_ring_tag,
2257             (void **)&sc->bge_ldata.bge_rx_std_ring, BUS_DMA_NOWAIT,
2258             &sc->bge_cdata.bge_rx_std_ring_map);
2259         if (error)
2260                 return (ENOMEM);
2261
2262         bzero((char *)sc->bge_ldata.bge_rx_std_ring, BGE_STD_RX_RING_SZ);
2263
2264         /* Load the address of the standard RX ring. */
2265         ctx.bge_maxsegs = 1;
2266         ctx.sc = sc;
2267
2268         error = bus_dmamap_load(sc->bge_cdata.bge_rx_std_ring_tag,
2269             sc->bge_cdata.bge_rx_std_ring_map, sc->bge_ldata.bge_rx_std_ring,
2270             BGE_STD_RX_RING_SZ, bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT);
2271
2272         if (error)
2273                 return (ENOMEM);
2274
2275         sc->bge_ldata.bge_rx_std_ring_paddr = ctx.bge_busaddr;
2276
2277         /* Create tags for jumbo mbufs. */
2278         if (BGE_IS_JUMBO_CAPABLE(sc)) {
2279                 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag,
2280                     1, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL,
2281                     NULL, MJUM9BYTES, BGE_NSEG_JUMBO, PAGE_SIZE,
2282                     0, NULL, NULL, &sc->bge_cdata.bge_mtag_jumbo);
2283                 if (error) {
2284                         device_printf(sc->bge_dev,
2285                             "could not allocate jumbo dma tag\n");
2286                         return (ENOMEM);
2287                 }
2288
2289                 /* Create tag for jumbo RX ring. */
2290                 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag,
2291                     PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL,
2292                     NULL, BGE_JUMBO_RX_RING_SZ, 1, BGE_JUMBO_RX_RING_SZ, 0,
2293                     NULL, NULL, &sc->bge_cdata.bge_rx_jumbo_ring_tag);
2294
2295                 if (error) {
2296                         device_printf(sc->bge_dev,
2297                             "could not allocate jumbo ring dma tag\n");
2298                         return (ENOMEM);
2299                 }
2300
2301                 /* Allocate DMA'able memory for jumbo RX ring. */
2302                 error = bus_dmamem_alloc(sc->bge_cdata.bge_rx_jumbo_ring_tag,
2303                     (void **)&sc->bge_ldata.bge_rx_jumbo_ring,
2304                     BUS_DMA_NOWAIT | BUS_DMA_ZERO,
2305                     &sc->bge_cdata.bge_rx_jumbo_ring_map);
2306                 if (error)
2307                         return (ENOMEM);
2308
2309                 /* Load the address of the jumbo RX ring. */
2310                 ctx.bge_maxsegs = 1;
2311                 ctx.sc = sc;
2312
2313                 error = bus_dmamap_load(sc->bge_cdata.bge_rx_jumbo_ring_tag,
2314                     sc->bge_cdata.bge_rx_jumbo_ring_map,
2315                     sc->bge_ldata.bge_rx_jumbo_ring, BGE_JUMBO_RX_RING_SZ,
2316                     bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT);
2317
2318                 if (error)
2319                         return (ENOMEM);
2320
2321                 sc->bge_ldata.bge_rx_jumbo_ring_paddr = ctx.bge_busaddr;
2322
2323                 /* Create DMA maps for jumbo RX buffers. */
2324                 error = bus_dmamap_create(sc->bge_cdata.bge_mtag_jumbo,
2325                     0, &sc->bge_cdata.bge_rx_jumbo_sparemap);
2326                 if (error) {
2327                         device_printf(sc->bge_dev,
2328                             "can't create spare DMA map for jumbo RX\n");
2329                         return (ENOMEM);
2330                 }
2331                 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
2332                         error = bus_dmamap_create(sc->bge_cdata.bge_mtag_jumbo,
2333                                     0, &sc->bge_cdata.bge_rx_jumbo_dmamap[i]);
2334                         if (error) {
2335                                 device_printf(sc->bge_dev,
2336                                     "can't create DMA map for jumbo RX\n");
2337                                 return (ENOMEM);
2338                         }
2339                 }
2340
2341         }
2342
2343         /* Create tag for RX return ring. */
2344         error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag,
2345             PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL,
2346             NULL, BGE_RX_RTN_RING_SZ(sc), 1, BGE_RX_RTN_RING_SZ(sc), 0,
2347             NULL, NULL, &sc->bge_cdata.bge_rx_return_ring_tag);
2348
2349         if (error) {
2350                 device_printf(sc->bge_dev, "could not allocate dma tag\n");
2351                 return (ENOMEM);
2352         }
2353
2354         /* Allocate DMA'able memory for RX return ring. */
2355         error = bus_dmamem_alloc(sc->bge_cdata.bge_rx_return_ring_tag,
2356             (void **)&sc->bge_ldata.bge_rx_return_ring, BUS_DMA_NOWAIT,
2357             &sc->bge_cdata.bge_rx_return_ring_map);
2358         if (error)
2359                 return (ENOMEM);
2360
2361         bzero((char *)sc->bge_ldata.bge_rx_return_ring,
2362             BGE_RX_RTN_RING_SZ(sc));
2363
2364         /* Load the address of the RX return ring. */
2365         ctx.bge_maxsegs = 1;
2366         ctx.sc = sc;
2367
2368         error = bus_dmamap_load(sc->bge_cdata.bge_rx_return_ring_tag,
2369             sc->bge_cdata.bge_rx_return_ring_map,
2370             sc->bge_ldata.bge_rx_return_ring, BGE_RX_RTN_RING_SZ(sc),
2371             bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT);
2372
2373         if (error)
2374                 return (ENOMEM);
2375
2376         sc->bge_ldata.bge_rx_return_ring_paddr = ctx.bge_busaddr;
2377
2378         /* Create tag for TX ring. */
2379         error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag,
2380             PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL,
2381             NULL, BGE_TX_RING_SZ, 1, BGE_TX_RING_SZ, 0, NULL, NULL,
2382             &sc->bge_cdata.bge_tx_ring_tag);
2383
2384         if (error) {
2385                 device_printf(sc->bge_dev, "could not allocate dma tag\n");
2386                 return (ENOMEM);
2387         }
2388
2389         /* Allocate DMA'able memory for TX ring. */
2390         error = bus_dmamem_alloc(sc->bge_cdata.bge_tx_ring_tag,
2391             (void **)&sc->bge_ldata.bge_tx_ring, BUS_DMA_NOWAIT,
2392             &sc->bge_cdata.bge_tx_ring_map);
2393         if (error)
2394                 return (ENOMEM);
2395
2396         bzero((char *)sc->bge_ldata.bge_tx_ring, BGE_TX_RING_SZ);
2397
2398         /* Load the address of the TX ring. */
2399         ctx.bge_maxsegs = 1;
2400         ctx.sc = sc;
2401
2402         error = bus_dmamap_load(sc->bge_cdata.bge_tx_ring_tag,
2403             sc->bge_cdata.bge_tx_ring_map, sc->bge_ldata.bge_tx_ring,
2404             BGE_TX_RING_SZ, bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT);
2405
2406         if (error)
2407                 return (ENOMEM);
2408
2409         sc->bge_ldata.bge_tx_ring_paddr = ctx.bge_busaddr;
2410
2411         /*
2412          * Create tag for status block.
2413          * Because we only use single Tx/Rx/Rx return ring, use
2414          * minimum status block size except BCM5700 AX/BX which
2415          * seems to want to see full status block size regardless
2416          * of configured number of ring.
2417          */
2418         if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
2419             sc->bge_chipid != BGE_CHIPID_BCM5700_C0)
2420                 sbsz = BGE_STATUS_BLK_SZ;
2421         else
2422                 sbsz = 32;
2423         error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag,
2424             PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL,
2425             NULL, sbsz, 1, sbsz, 0, NULL, NULL, &sc->bge_cdata.bge_status_tag);
2426
2427         if (error) {
2428                 device_printf(sc->bge_dev,
2429                     "could not allocate status dma tag\n");
2430                 return (ENOMEM);
2431         }
2432
2433         /* Allocate DMA'able memory for status block. */
2434         error = bus_dmamem_alloc(sc->bge_cdata.bge_status_tag,
2435             (void **)&sc->bge_ldata.bge_status_block, BUS_DMA_NOWAIT,
2436             &sc->bge_cdata.bge_status_map);
2437         if (error)
2438                 return (ENOMEM);
2439
2440         bzero((char *)sc->bge_ldata.bge_status_block, sbsz);
2441
2442         /* Load the address of the status block. */
2443         ctx.sc = sc;
2444         ctx.bge_maxsegs = 1;
2445
2446         error = bus_dmamap_load(sc->bge_cdata.bge_status_tag,
2447             sc->bge_cdata.bge_status_map, sc->bge_ldata.bge_status_block,
2448             sbsz, bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT);
2449
2450         if (error)
2451                 return (ENOMEM);
2452
2453         sc->bge_ldata.bge_status_block_paddr = ctx.bge_busaddr;
2454
2455         /* Create tag for statistics block. */
2456         error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag,
2457             PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL,
2458             NULL, BGE_STATS_SZ, 1, BGE_STATS_SZ, 0, NULL, NULL,
2459             &sc->bge_cdata.bge_stats_tag);
2460
2461         if (error) {
2462                 device_printf(sc->bge_dev, "could not allocate dma tag\n");
2463                 return (ENOMEM);
2464         }
2465
2466         /* Allocate DMA'able memory for statistics block. */
2467         error = bus_dmamem_alloc(sc->bge_cdata.bge_stats_tag,
2468             (void **)&sc->bge_ldata.bge_stats, BUS_DMA_NOWAIT,
2469             &sc->bge_cdata.bge_stats_map);
2470         if (error)
2471                 return (ENOMEM);
2472
2473         bzero((char *)sc->bge_ldata.bge_stats, BGE_STATS_SZ);
2474
2475         /* Load the address of the statstics block. */
2476         ctx.sc = sc;
2477         ctx.bge_maxsegs = 1;
2478
2479         error = bus_dmamap_load(sc->bge_cdata.bge_stats_tag,
2480             sc->bge_cdata.bge_stats_map, sc->bge_ldata.bge_stats,
2481             BGE_STATS_SZ, bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT);
2482
2483         if (error)
2484                 return (ENOMEM);
2485
2486         sc->bge_ldata.bge_stats_paddr = ctx.bge_busaddr;
2487
2488         return (0);
2489 }
2490
2491 /*
2492  * Return true if this device has more than one port.
2493  */
2494 static int
2495 bge_has_multiple_ports(struct bge_softc *sc)
2496 {
2497         device_t dev = sc->bge_dev;
2498         u_int b, d, f, fscan, s;
2499
2500         d = pci_get_domain(dev);
2501         b = pci_get_bus(dev);
2502         s = pci_get_slot(dev);
2503         f = pci_get_function(dev);
2504         for (fscan = 0; fscan <= PCI_FUNCMAX; fscan++)
2505                 if (fscan != f && pci_find_dbsf(d, b, s, fscan) != NULL)
2506                         return (1);
2507         return (0);
2508 }
2509
2510 /*
2511  * Return true if MSI can be used with this device.
2512  */
2513 static int
2514 bge_can_use_msi(struct bge_softc *sc)
2515 {
2516         int can_use_msi = 0;
2517
2518         switch (sc->bge_asicrev) {
2519         case BGE_ASICREV_BCM5714_A0:
2520         case BGE_ASICREV_BCM5714:
2521                 /*
2522                  * Apparently, MSI doesn't work when these chips are
2523                  * configured in single-port mode.
2524                  */
2525                 if (bge_has_multiple_ports(sc))
2526                         can_use_msi = 1;
2527                 break;
2528         case BGE_ASICREV_BCM5750:
2529                 if (sc->bge_chiprev != BGE_CHIPREV_5750_AX &&
2530                     sc->bge_chiprev != BGE_CHIPREV_5750_BX)
2531                         can_use_msi = 1;
2532                 break;
2533         default:
2534                 if (BGE_IS_575X_PLUS(sc))
2535                         can_use_msi = 1;
2536         }
2537         return (can_use_msi);
2538 }
2539
2540 static int
2541 bge_attach(device_t dev)
2542 {
2543         struct ifnet *ifp;
2544         struct bge_softc *sc;
2545         uint32_t hwcfg = 0, misccfg;
2546         u_char eaddr[ETHER_ADDR_LEN];
2547         int error, msicount, reg, rid, trys;
2548
2549         sc = device_get_softc(dev);
2550         sc->bge_dev = dev;
2551
2552         TASK_INIT(&sc->bge_intr_task, 0, bge_intr_task, sc);
2553
2554         /*
2555          * Map control/status registers.
2556          */
2557         pci_enable_busmaster(dev);
2558
2559         rid = BGE_PCI_BAR0;
2560         sc->bge_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
2561             RF_ACTIVE);
2562
2563         if (sc->bge_res == NULL) {
2564                 device_printf (sc->bge_dev, "couldn't map memory\n");
2565                 error = ENXIO;
2566                 goto fail;
2567         }
2568
2569         /* Save various chip information. */
2570         sc->bge_chipid =
2571             pci_read_config(dev, BGE_PCI_MISC_CTL, 4) >>
2572             BGE_PCIMISCCTL_ASICREV_SHIFT;
2573         if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_USE_PRODID_REG)
2574                 sc->bge_chipid = pci_read_config(dev, BGE_PCI_PRODID_ASICREV,
2575                     4);
2576         sc->bge_asicrev = BGE_ASICREV(sc->bge_chipid);
2577         sc->bge_chiprev = BGE_CHIPREV(sc->bge_chipid);
2578
2579         /*
2580          * Don't enable Ethernet@WireSpeed for the 5700, 5906, or the
2581          * 5705 A0 and A1 chips.
2582          */
2583         if (sc->bge_asicrev != BGE_ASICREV_BCM5700 &&
2584             sc->bge_asicrev != BGE_ASICREV_BCM5906 &&
2585             sc->bge_chipid != BGE_CHIPID_BCM5705_A0 &&
2586             sc->bge_chipid != BGE_CHIPID_BCM5705_A1)
2587                 sc->bge_flags |= BGE_FLAG_WIRESPEED;
2588
2589         if (bge_has_eaddr(sc))
2590                 sc->bge_flags |= BGE_FLAG_EADDR;
2591
2592         /* Save chipset family. */
2593         switch (sc->bge_asicrev) {
2594         case BGE_ASICREV_BCM5755:
2595         case BGE_ASICREV_BCM5761:
2596         case BGE_ASICREV_BCM5784:
2597         case BGE_ASICREV_BCM5785:
2598         case BGE_ASICREV_BCM5787:
2599         case BGE_ASICREV_BCM57780:
2600                 sc->bge_flags |= BGE_FLAG_5755_PLUS | BGE_FLAG_575X_PLUS |
2601                     BGE_FLAG_5705_PLUS;
2602                 break;
2603         case BGE_ASICREV_BCM5700:
2604         case BGE_ASICREV_BCM5701:
2605         case BGE_ASICREV_BCM5703:
2606         case BGE_ASICREV_BCM5704:
2607                 sc->bge_flags |= BGE_FLAG_5700_FAMILY | BGE_FLAG_JUMBO;
2608                 break;
2609         case BGE_ASICREV_BCM5714_A0:
2610         case BGE_ASICREV_BCM5780:
2611         case BGE_ASICREV_BCM5714:
2612                 sc->bge_flags |= BGE_FLAG_5714_FAMILY /* | BGE_FLAG_JUMBO */;
2613                 /* FALLTHROUGH */
2614         case BGE_ASICREV_BCM5750:
2615         case BGE_ASICREV_BCM5752:
2616         case BGE_ASICREV_BCM5906:
2617                 sc->bge_flags |= BGE_FLAG_575X_PLUS;
2618                 /* FALLTHROUGH */
2619         case BGE_ASICREV_BCM5705:
2620                 sc->bge_flags |= BGE_FLAG_5705_PLUS;
2621                 break;
2622         }
2623
2624         /* Set various bug flags. */
2625         if (sc->bge_chipid == BGE_CHIPID_BCM5701_A0 ||
2626             sc->bge_chipid == BGE_CHIPID_BCM5701_B0)
2627                 sc->bge_flags |= BGE_FLAG_CRC_BUG;
2628         if (sc->bge_chiprev == BGE_CHIPREV_5703_AX ||
2629             sc->bge_chiprev == BGE_CHIPREV_5704_AX)
2630                 sc->bge_flags |= BGE_FLAG_ADC_BUG;
2631         if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0)
2632                 sc->bge_flags |= BGE_FLAG_5704_A0_BUG;
2633         if (pci_get_subvendor(dev) == DELL_VENDORID)
2634                 sc->bge_flags |= BGE_FLAG_NO_3LED;
2635         if (pci_get_device(dev) == BCOM_DEVICEID_BCM5755M)
2636                 sc->bge_flags |= BGE_FLAG_ADJUST_TRIM;
2637         if (BGE_IS_5705_PLUS(sc) &&
2638             !(sc->bge_flags & BGE_FLAG_ADJUST_TRIM)) {
2639                 if (sc->bge_asicrev == BGE_ASICREV_BCM5755 ||
2640                     sc->bge_asicrev == BGE_ASICREV_BCM5761 ||
2641                     sc->bge_asicrev == BGE_ASICREV_BCM5784 ||
2642                     sc->bge_asicrev == BGE_ASICREV_BCM5787) {
2643                         if (pci_get_device(dev) != BCOM_DEVICEID_BCM5722 &&
2644                             pci_get_device(dev) != BCOM_DEVICEID_BCM5756)
2645                                 sc->bge_flags |= BGE_FLAG_JITTER_BUG;
2646                 } else if (sc->bge_asicrev != BGE_ASICREV_BCM5906)
2647                         sc->bge_flags |= BGE_FLAG_BER_BUG;
2648         }
2649
2650         /*
2651          * All controllers that are not 5755 or higher have 4GB
2652          * boundary DMA bug.
2653          * Whenever an address crosses a multiple of the 4GB boundary
2654          * (including 4GB, 8Gb, 12Gb, etc.) and makes the transition
2655          * from 0xX_FFFF_FFFF to 0x(X+1)_0000_0000 an internal DMA
2656          * state machine will lockup and cause the device to hang.
2657          */
2658         if (BGE_IS_5755_PLUS(sc) == 0)
2659                 sc->bge_flags |= BGE_FLAG_4G_BNDRY_BUG;
2660
2661         /*
2662          * We could possibly check for BCOM_DEVICEID_BCM5788 in bge_probe()
2663          * but I do not know the DEVICEID for the 5788M.
2664          */
2665         misccfg = CSR_READ_4(sc, BGE_MISC_CFG) & BGE_MISCCFG_BOARD_ID;
2666         if (misccfg == BGE_MISCCFG_BOARD_ID_5788 ||
2667             misccfg == BGE_MISCCFG_BOARD_ID_5788M)
2668                 sc->bge_flags |= BGE_FLAG_5788;
2669
2670         /*
2671          * Some controllers seem to require a special firmware to use
2672          * TSO. But the firmware is not available to FreeBSD and Linux
2673          * claims that the TSO performed by the firmware is slower than
2674          * hardware based TSO. Moreover the firmware based TSO has one
2675          * known bug which can't handle TSO if ethernet header + IP/TCP
2676          * header is greater than 80 bytes. The workaround for the TSO
2677          * bug exist but it seems it's too expensive than not using
2678          * TSO at all. Some hardwares also have the TSO bug so limit
2679          * the TSO to the controllers that are not affected TSO issues
2680          * (e.g. 5755 or higher).
2681          */
2682         if (BGE_IS_5755_PLUS(sc)) {
2683                 /*
2684                  * BCM5754 and BCM5787 shares the same ASIC id so
2685                  * explicit device id check is required.
2686                  * Due to unknown reason TSO does not work on BCM5755M.
2687                  */
2688                 if (pci_get_device(dev) != BCOM_DEVICEID_BCM5754 &&
2689                     pci_get_device(dev) != BCOM_DEVICEID_BCM5754M &&
2690                     pci_get_device(dev) != BCOM_DEVICEID_BCM5755M)
2691                         sc->bge_flags |= BGE_FLAG_TSO;
2692         }
2693
2694         /*
2695          * Check if this is a PCI-X or PCI Express device.
2696          */
2697         if (pci_find_extcap(dev, PCIY_EXPRESS, &reg) == 0) {
2698                 /*
2699                  * Found a PCI Express capabilities register, this
2700                  * must be a PCI Express device.
2701                  */
2702                 sc->bge_flags |= BGE_FLAG_PCIE;
2703                 sc->bge_expcap = reg;
2704                 bge_set_max_readrq(sc);
2705         } else {
2706                 /*
2707                  * Check if the device is in PCI-X Mode.
2708                  * (This bit is not valid on PCI Express controllers.)
2709                  */
2710                 if (pci_find_extcap(dev, PCIY_PCIX, &reg) == 0)
2711                         sc->bge_pcixcap = reg;
2712                 if ((pci_read_config(dev, BGE_PCI_PCISTATE, 4) &
2713                     BGE_PCISTATE_PCI_BUSMODE) == 0)
2714                         sc->bge_flags |= BGE_FLAG_PCIX;
2715         }
2716
2717         /*
2718          * The 40bit DMA bug applies to the 5714/5715 controllers and is
2719          * not actually a MAC controller bug but an issue with the embedded
2720          * PCIe to PCI-X bridge in the device. Use 40bit DMA workaround.
2721          */
2722         if (BGE_IS_5714_FAMILY(sc) && (sc->bge_flags & BGE_FLAG_PCIX))
2723                 sc->bge_flags |= BGE_FLAG_40BIT_BUG;
2724         /*
2725          * Allocate the interrupt, using MSI if possible.  These devices
2726          * support 8 MSI messages, but only the first one is used in
2727          * normal operation.
2728          */
2729         rid = 0;
2730         if (pci_find_extcap(sc->bge_dev, PCIY_MSI, &reg) == 0) {
2731                 sc->bge_msicap = reg;
2732                 if (bge_can_use_msi(sc)) {
2733                         msicount = pci_msi_count(dev);
2734                         if (msicount > 1)
2735                                 msicount = 1;
2736                 } else
2737                         msicount = 0;
2738                 if (msicount == 1 && pci_alloc_msi(dev, &msicount) == 0) {
2739                         rid = 1;
2740                         sc->bge_flags |= BGE_FLAG_MSI;
2741                 }
2742         }
2743
2744         sc->bge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
2745             RF_SHAREABLE | RF_ACTIVE);
2746
2747         if (sc->bge_irq == NULL) {
2748                 device_printf(sc->bge_dev, "couldn't map interrupt\n");
2749                 error = ENXIO;
2750                 goto fail;
2751         }
2752
2753         if (bootverbose)
2754                 device_printf(dev,
2755                     "CHIP ID 0x%08x; ASIC REV 0x%02x; CHIP REV 0x%02x; %s\n",
2756                     sc->bge_chipid, sc->bge_asicrev, sc->bge_chiprev,
2757                     (sc->bge_flags & BGE_FLAG_PCIX) ? "PCI-X" :
2758                     ((sc->bge_flags & BGE_FLAG_PCIE) ? "PCI-E" : "PCI"));
2759
2760         BGE_LOCK_INIT(sc, device_get_nameunit(dev));
2761
2762         /* Try to reset the chip. */
2763         if (bge_reset(sc)) {
2764                 device_printf(sc->bge_dev, "chip reset failed\n");
2765                 error = ENXIO;
2766                 goto fail;
2767         }
2768
2769         sc->bge_asf_mode = 0;
2770         if (bge_allow_asf && (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG)
2771             == BGE_MAGIC_NUMBER)) {
2772                 if (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG)
2773                     & BGE_HWCFG_ASF) {
2774                         sc->bge_asf_mode |= ASF_ENABLE;
2775                         sc->bge_asf_mode |= ASF_STACKUP;
2776                         if (BGE_IS_575X_PLUS(sc))
2777                                 sc->bge_asf_mode |= ASF_NEW_HANDSHAKE;
2778                 }
2779         }
2780
2781         /* Try to reset the chip again the nice way. */
2782         bge_stop_fw(sc);
2783         bge_sig_pre_reset(sc, BGE_RESET_STOP);
2784         if (bge_reset(sc)) {
2785                 device_printf(sc->bge_dev, "chip reset failed\n");
2786                 error = ENXIO;
2787                 goto fail;
2788         }
2789
2790         bge_sig_legacy(sc, BGE_RESET_STOP);
2791         bge_sig_post_reset(sc, BGE_RESET_STOP);
2792
2793         if (bge_chipinit(sc)) {
2794                 device_printf(sc->bge_dev, "chip initialization failed\n");
2795                 error = ENXIO;
2796                 goto fail;
2797         }
2798
2799         error = bge_get_eaddr(sc, eaddr);
2800         if (error) {
2801                 device_printf(sc->bge_dev,
2802                     "failed to read station address\n");
2803                 error = ENXIO;
2804                 goto fail;
2805         }
2806
2807         /* 5705 limits RX return ring to 512 entries. */
2808         if (BGE_IS_5705_PLUS(sc))
2809                 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705;
2810         else
2811                 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT;
2812
2813         if (bge_dma_alloc(dev)) {
2814                 device_printf(sc->bge_dev,
2815                     "failed to allocate DMA resources\n");
2816                 error = ENXIO;
2817                 goto fail;
2818         }
2819
2820         /* Set default tuneable values. */
2821         sc->bge_stat_ticks = BGE_TICKS_PER_SEC;
2822         sc->bge_rx_coal_ticks = 150;
2823         sc->bge_tx_coal_ticks = 150;
2824         sc->bge_rx_max_coal_bds = 10;
2825         sc->bge_tx_max_coal_bds = 10;
2826
2827         /* Set up ifnet structure */
2828         ifp = sc->bge_ifp = if_alloc(IFT_ETHER);
2829         if (ifp == NULL) {
2830                 device_printf(sc->bge_dev, "failed to if_alloc()\n");
2831                 error = ENXIO;
2832                 goto fail;
2833         }
2834         ifp->if_softc = sc;
2835         if_initname(ifp, device_get_name(dev), device_get_unit(dev));
2836         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
2837         ifp->if_ioctl = bge_ioctl;
2838         ifp->if_start = bge_start;
2839         ifp->if_init = bge_init;
2840         ifp->if_snd.ifq_drv_maxlen = BGE_TX_RING_CNT - 1;
2841         IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen);
2842         IFQ_SET_READY(&ifp->if_snd);
2843         ifp->if_hwassist = BGE_CSUM_FEATURES;
2844         ifp->if_capabilities = IFCAP_HWCSUM | IFCAP_VLAN_HWTAGGING |
2845             IFCAP_VLAN_MTU;
2846         if ((sc->bge_flags & BGE_FLAG_TSO) != 0) {
2847                 ifp->if_hwassist |= CSUM_TSO;
2848                 ifp->if_capabilities |= IFCAP_TSO4 | IFCAP_VLAN_HWTSO;
2849         }
2850 #ifdef IFCAP_VLAN_HWCSUM
2851         ifp->if_capabilities |= IFCAP_VLAN_HWCSUM;
2852 #endif
2853         ifp->if_capenable = ifp->if_capabilities;
2854 #ifdef DEVICE_POLLING
2855         ifp->if_capabilities |= IFCAP_POLLING;
2856 #endif
2857
2858         /*
2859          * 5700 B0 chips do not support checksumming correctly due
2860          * to hardware bugs.
2861          */
2862         if (sc->bge_chipid == BGE_CHIPID_BCM5700_B0) {
2863                 ifp->if_capabilities &= ~IFCAP_HWCSUM;
2864                 ifp->if_capenable &= ~IFCAP_HWCSUM;
2865                 ifp->if_hwassist = 0;
2866         }
2867
2868         /*
2869          * Figure out what sort of media we have by checking the
2870          * hardware config word in the first 32k of NIC internal memory,
2871          * or fall back to examining the EEPROM if necessary.
2872          * Note: on some BCM5700 cards, this value appears to be unset.
2873          * If that's the case, we have to rely on identifying the NIC
2874          * by its PCI subsystem ID, as we do below for the SysKonnect
2875          * SK-9D41.
2876          */
2877         if (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG) == BGE_MAGIC_NUMBER)
2878                 hwcfg = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG);
2879         else if ((sc->bge_flags & BGE_FLAG_EADDR) &&
2880             (sc->bge_asicrev != BGE_ASICREV_BCM5906)) {
2881                 if (bge_read_eeprom(sc, (caddr_t)&hwcfg, BGE_EE_HWCFG_OFFSET,
2882                     sizeof(hwcfg))) {
2883                         device_printf(sc->bge_dev, "failed to read EEPROM\n");
2884                         error = ENXIO;
2885                         goto fail;
2886                 }
2887                 hwcfg = ntohl(hwcfg);
2888         }
2889
2890         /* The SysKonnect SK-9D41 is a 1000baseSX card. */
2891         if ((pci_read_config(dev, BGE_PCI_SUBSYS, 4) >> 16) ==
2892             SK_SUBSYSID_9D41 || (hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER) {
2893                 if (BGE_IS_5714_FAMILY(sc))
2894                         sc->bge_flags |= BGE_FLAG_MII_SERDES;
2895                 else
2896                         sc->bge_flags |= BGE_FLAG_TBI;
2897         }
2898
2899         if (sc->bge_flags & BGE_FLAG_TBI) {
2900                 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK, bge_ifmedia_upd,
2901                     bge_ifmedia_sts);
2902                 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_1000_SX, 0, NULL);
2903                 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_1000_SX | IFM_FDX,
2904                     0, NULL);
2905                 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL);
2906                 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO);
2907                 sc->bge_ifmedia.ifm_media = sc->bge_ifmedia.ifm_cur->ifm_media;
2908         } else {
2909                 /*
2910                  * Do transceiver setup and tell the firmware the
2911                  * driver is down so we can try to get access the
2912                  * probe if ASF is running.  Retry a couple of times
2913                  * if we get a conflict with the ASF firmware accessing
2914                  * the PHY.
2915                  */
2916                 trys = 0;
2917                 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
2918 again:
2919                 bge_asf_driver_up(sc);
2920
2921                 if (mii_phy_probe(dev, &sc->bge_miibus,
2922                     bge_ifmedia_upd, bge_ifmedia_sts)) {
2923                         if (trys++ < 4) {
2924                                 device_printf(sc->bge_dev, "Try again\n");
2925                                 bge_miibus_writereg(sc->bge_dev, 1, MII_BMCR,
2926                                     BMCR_RESET);
2927                                 goto again;
2928                         }
2929
2930                         device_printf(sc->bge_dev, "MII without any PHY!\n");
2931                         error = ENXIO;
2932                         goto fail;
2933                 }
2934
2935                 /*
2936                  * Now tell the firmware we are going up after probing the PHY
2937                  */
2938                 if (sc->bge_asf_mode & ASF_STACKUP)
2939                         BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
2940         }
2941
2942         /*
2943          * When using the BCM5701 in PCI-X mode, data corruption has
2944          * been observed in the first few bytes of some received packets.
2945          * Aligning the packet buffer in memory eliminates the corruption.
2946          * Unfortunately, this misaligns the packet payloads.  On platforms
2947          * which do not support unaligned accesses, we will realign the
2948          * payloads by copying the received packets.
2949          */
2950         if (sc->bge_asicrev == BGE_ASICREV_BCM5701 &&
2951             sc->bge_flags & BGE_FLAG_PCIX)
2952                 sc->bge_flags |= BGE_FLAG_RX_ALIGNBUG;
2953
2954         /*
2955          * Call MI attach routine.
2956          */
2957         ether_ifattach(ifp, eaddr);
2958         callout_init_mtx(&sc->bge_stat_ch, &sc->bge_mtx, 0);
2959
2960         /* Tell upper layer we support long frames. */
2961         ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
2962
2963         /*
2964          * Hookup IRQ last.
2965          */
2966 #if __FreeBSD_version > 700030
2967         if (BGE_IS_5755_PLUS(sc) && sc->bge_flags & BGE_FLAG_MSI) {
2968                 /* Take advantage of single-shot MSI. */
2969                 CSR_WRITE_4(sc, BGE_MSI_MODE, CSR_READ_4(sc, BGE_MSI_MODE) &
2970                     ~BGE_MSIMODE_ONE_SHOT_DISABLE);
2971                 sc->bge_tq = taskqueue_create_fast("bge_taskq", M_WAITOK,
2972                     taskqueue_thread_enqueue, &sc->bge_tq);
2973                 if (sc->bge_tq == NULL) {
2974                         device_printf(dev, "could not create taskqueue.\n");
2975                         ether_ifdetach(ifp);
2976                         error = ENXIO;
2977                         goto fail;
2978                 }
2979                 taskqueue_start_threads(&sc->bge_tq, 1, PI_NET, "%s taskq",
2980                     device_get_nameunit(sc->bge_dev));
2981                 error = bus_setup_intr(dev, sc->bge_irq,
2982                     INTR_TYPE_NET | INTR_MPSAFE, bge_msi_intr, NULL, sc,
2983                     &sc->bge_intrhand);
2984                 if (error)
2985                         ether_ifdetach(ifp);
2986         } else
2987                 error = bus_setup_intr(dev, sc->bge_irq,
2988                     INTR_TYPE_NET | INTR_MPSAFE, NULL, bge_intr, sc,
2989                     &sc->bge_intrhand);
2990 #else
2991         error = bus_setup_intr(dev, sc->bge_irq, INTR_TYPE_NET | INTR_MPSAFE,
2992            bge_intr, sc, &sc->bge_intrhand);
2993 #endif
2994
2995         if (error) {
2996                 bge_detach(dev);
2997                 device_printf(sc->bge_dev, "couldn't set up irq\n");
2998         }
2999
3000         bge_add_sysctls(sc);
3001
3002         return (0);
3003
3004 fail:
3005         bge_release_resources(sc);
3006
3007         return (error);
3008 }
3009
3010 static int
3011 bge_detach(device_t dev)
3012 {
3013         struct bge_softc *sc;
3014         struct ifnet *ifp;
3015
3016         sc = device_get_softc(dev);
3017         ifp = sc->bge_ifp;
3018
3019 #ifdef DEVICE_POLLING
3020         if (ifp->if_capenable & IFCAP_POLLING)
3021                 ether_poll_deregister(ifp);
3022 #endif
3023
3024         BGE_LOCK(sc);
3025         bge_stop(sc);
3026         bge_reset(sc);
3027         BGE_UNLOCK(sc);
3028
3029         callout_drain(&sc->bge_stat_ch);
3030
3031         if (sc->bge_tq)
3032                 taskqueue_drain(sc->bge_tq, &sc->bge_intr_task);
3033         ether_ifdetach(ifp);
3034
3035         if (sc->bge_flags & BGE_FLAG_TBI) {
3036                 ifmedia_removeall(&sc->bge_ifmedia);
3037         } else {
3038                 bus_generic_detach(dev);
3039                 device_delete_child(dev, sc->bge_miibus);
3040         }
3041
3042         bge_release_resources(sc);
3043
3044         return (0);
3045 }
3046
3047 static void
3048 bge_release_resources(struct bge_softc *sc)
3049 {
3050         device_t dev;
3051
3052         dev = sc->bge_dev;
3053
3054         if (sc->bge_tq != NULL)
3055                 taskqueue_free(sc->bge_tq);
3056
3057         if (sc->bge_intrhand != NULL)
3058                 bus_teardown_intr(dev, sc->bge_irq, sc->bge_intrhand);
3059
3060         if (sc->bge_irq != NULL)
3061                 bus_release_resource(dev, SYS_RES_IRQ,
3062                     sc->bge_flags & BGE_FLAG_MSI ? 1 : 0, sc->bge_irq);
3063
3064         if (sc->bge_flags & BGE_FLAG_MSI)
3065                 pci_release_msi(dev);
3066
3067         if (sc->bge_res != NULL)
3068                 bus_release_resource(dev, SYS_RES_MEMORY,
3069                     BGE_PCI_BAR0, sc->bge_res);
3070
3071         if (sc->bge_ifp != NULL)
3072                 if_free(sc->bge_ifp);
3073
3074         bge_dma_free(sc);
3075
3076         if (mtx_initialized(&sc->bge_mtx))      /* XXX */
3077                 BGE_LOCK_DESTROY(sc);
3078 }
3079
3080 static int
3081 bge_reset(struct bge_softc *sc)
3082 {
3083         device_t dev;
3084         uint32_t cachesize, command, pcistate, reset, val;
3085         void (*write_op)(struct bge_softc *, int, int);
3086         uint16_t devctl;
3087         int i;
3088
3089         dev = sc->bge_dev;
3090
3091         if (BGE_IS_575X_PLUS(sc) && !BGE_IS_5714_FAMILY(sc) &&
3092             (sc->bge_asicrev != BGE_ASICREV_BCM5906)) {
3093                 if (sc->bge_flags & BGE_FLAG_PCIE)
3094                         write_op = bge_writemem_direct;
3095                 else
3096                         write_op = bge_writemem_ind;
3097         } else
3098                 write_op = bge_writereg_ind;
3099
3100         /* Save some important PCI state. */
3101         cachesize = pci_read_config(dev, BGE_PCI_CACHESZ, 4);
3102         command = pci_read_config(dev, BGE_PCI_CMD, 4);
3103         pcistate = pci_read_config(dev, BGE_PCI_PCISTATE, 4);
3104
3105         pci_write_config(dev, BGE_PCI_MISC_CTL,
3106             BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR |
3107             BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW, 4);
3108
3109         /* Disable fastboot on controllers that support it. */
3110         if (sc->bge_asicrev == BGE_ASICREV_BCM5752 ||
3111             BGE_IS_5755_PLUS(sc)) {
3112                 if (bootverbose)
3113                         device_printf(sc->bge_dev, "Disabling fastboot\n");
3114                 CSR_WRITE_4(sc, BGE_FASTBOOT_PC, 0x0);
3115         }
3116
3117         /*
3118          * Write the magic number to SRAM at offset 0xB50.
3119          * When firmware finishes its initialization it will
3120          * write ~BGE_MAGIC_NUMBER to the same location.
3121          */
3122         bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER);
3123
3124         reset = BGE_MISCCFG_RESET_CORE_CLOCKS | BGE_32BITTIME_66MHZ;
3125
3126         /* XXX: Broadcom Linux driver. */
3127         if (sc->bge_flags & BGE_FLAG_PCIE) {
3128                 if (CSR_READ_4(sc, 0x7E2C) == 0x60)     /* PCIE 1.0 */
3129                         CSR_WRITE_4(sc, 0x7E2C, 0x20);
3130                 if (sc->bge_chipid != BGE_CHIPID_BCM5750_A0) {
3131                         /* Prevent PCIE link training during global reset */
3132                         CSR_WRITE_4(sc, BGE_MISC_CFG, 1 << 29);
3133                         reset |= 1 << 29;
3134                 }
3135         }
3136
3137         /*
3138          * Set GPHY Power Down Override to leave GPHY
3139          * powered up in D0 uninitialized.
3140          */
3141         if (BGE_IS_5705_PLUS(sc))
3142                 reset |= 0x04000000;
3143
3144         /* Issue global reset */
3145         write_op(sc, BGE_MISC_CFG, reset);
3146
3147         if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
3148                 val = CSR_READ_4(sc, BGE_VCPU_STATUS);
3149                 CSR_WRITE_4(sc, BGE_VCPU_STATUS,
3150                     val | BGE_VCPU_STATUS_DRV_RESET);
3151                 val = CSR_READ_4(sc, BGE_VCPU_EXT_CTRL);
3152                 CSR_WRITE_4(sc, BGE_VCPU_EXT_CTRL,
3153                     val & ~BGE_VCPU_EXT_CTRL_HALT_CPU);
3154         }
3155
3156         DELAY(1000);
3157
3158         /* XXX: Broadcom Linux driver. */
3159         if (sc->bge_flags & BGE_FLAG_PCIE) {
3160                 if (sc->bge_chipid == BGE_CHIPID_BCM5750_A0) {
3161                         DELAY(500000); /* wait for link training to complete */
3162                         val = pci_read_config(dev, 0xC4, 4);
3163                         pci_write_config(dev, 0xC4, val | (1 << 15), 4);
3164                 }
3165                 devctl = pci_read_config(dev,
3166                     sc->bge_expcap + PCIR_EXPRESS_DEVICE_CTL, 2);
3167                 /* Clear enable no snoop and disable relaxed ordering. */
3168                 devctl &= ~(PCIM_EXP_CTL_RELAXED_ORD_ENABLE |
3169                     PCIM_EXP_CTL_NOSNOOP_ENABLE);
3170                 /* Set PCIE max payload size to 128. */
3171                 devctl &= ~PCIM_EXP_CTL_MAX_PAYLOAD;
3172                 pci_write_config(dev, sc->bge_expcap + PCIR_EXPRESS_DEVICE_CTL,
3173                     devctl, 2);
3174                 /* Clear error status. */
3175                 pci_write_config(dev, sc->bge_expcap + PCIR_EXPRESS_DEVICE_STA,
3176                     PCIM_EXP_STA_CORRECTABLE_ERROR |
3177                     PCIM_EXP_STA_NON_FATAL_ERROR | PCIM_EXP_STA_FATAL_ERROR |
3178                     PCIM_EXP_STA_UNSUPPORTED_REQ, 2);
3179         }
3180
3181         /* Reset some of the PCI state that got zapped by reset. */
3182         pci_write_config(dev, BGE_PCI_MISC_CTL,
3183             BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR |
3184             BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW, 4);
3185         pci_write_config(dev, BGE_PCI_CACHESZ, cachesize, 4);
3186         pci_write_config(dev, BGE_PCI_CMD, command, 4);
3187         write_op(sc, BGE_MISC_CFG, BGE_32BITTIME_66MHZ);
3188         /*
3189          * Disable PCI-X relaxed ordering to ensure status block update
3190          * comes first then packet buffer DMA. Otherwise driver may
3191          * read stale status block.
3192          */
3193         if (sc->bge_flags & BGE_FLAG_PCIX) {
3194                 devctl = pci_read_config(dev,
3195                     sc->bge_pcixcap + PCIXR_COMMAND, 2);
3196                 devctl &= ~PCIXM_COMMAND_ERO;
3197                 if (sc->bge_asicrev == BGE_ASICREV_BCM5703) {
3198                         devctl &= ~PCIXM_COMMAND_MAX_READ;
3199                         devctl |= PCIXM_COMMAND_MAX_READ_2048;
3200                 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
3201                         devctl &= ~(PCIXM_COMMAND_MAX_SPLITS |
3202                             PCIXM_COMMAND_MAX_READ);
3203                         devctl |= PCIXM_COMMAND_MAX_READ_2048;
3204                 }
3205                 pci_write_config(dev, sc->bge_pcixcap + PCIXR_COMMAND,
3206                     devctl, 2);
3207         }
3208         /* Re-enable MSI, if neccesary, and enable the memory arbiter. */
3209         if (BGE_IS_5714_FAMILY(sc)) {
3210                 /* This chip disables MSI on reset. */
3211                 if (sc->bge_flags & BGE_FLAG_MSI) {
3212                         val = pci_read_config(dev,
3213                             sc->bge_msicap + PCIR_MSI_CTRL, 2);
3214                         pci_write_config(dev,
3215                             sc->bge_msicap + PCIR_MSI_CTRL,
3216                             val | PCIM_MSICTRL_MSI_ENABLE, 2);
3217                         val = CSR_READ_4(sc, BGE_MSI_MODE);
3218                         CSR_WRITE_4(sc, BGE_MSI_MODE,
3219                             val | BGE_MSIMODE_ENABLE);
3220                 }
3221                 val = CSR_READ_4(sc, BGE_MARB_MODE);
3222                 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | val);
3223         } else
3224                 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
3225
3226         if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
3227                 for (i = 0; i < BGE_TIMEOUT; i++) {
3228                         val = CSR_READ_4(sc, BGE_VCPU_STATUS);
3229                         if (val & BGE_VCPU_STATUS_INIT_DONE)
3230                                 break;
3231                         DELAY(100);
3232                 }
3233                 if (i == BGE_TIMEOUT) {
3234                         device_printf(sc->bge_dev, "reset timed out\n");
3235                         return (1);
3236                 }
3237         } else {
3238                 /*
3239                  * Poll until we see the 1's complement of the magic number.
3240                  * This indicates that the firmware initialization is complete.
3241                  * We expect this to fail if no chip containing the Ethernet
3242                  * address is fitted though.
3243                  */
3244                 for (i = 0; i < BGE_TIMEOUT; i++) {
3245                         DELAY(10);
3246                         val = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM);
3247                         if (val == ~BGE_MAGIC_NUMBER)
3248                                 break;
3249                 }
3250
3251                 if ((sc->bge_flags & BGE_FLAG_EADDR) && i == BGE_TIMEOUT)
3252                         device_printf(sc->bge_dev, "firmware handshake timed out, "
3253                             "found 0x%08x\n", val);
3254         }
3255
3256         /*
3257          * XXX Wait for the value of the PCISTATE register to
3258          * return to its original pre-reset state. This is a
3259          * fairly good indicator of reset completion. If we don't
3260          * wait for the reset to fully complete, trying to read
3261          * from the device's non-PCI registers may yield garbage
3262          * results.
3263          */
3264         for (i = 0; i < BGE_TIMEOUT; i++) {
3265                 if (pci_read_config(dev, BGE_PCI_PCISTATE, 4) == pcistate)
3266                         break;
3267                 DELAY(10);
3268         }
3269
3270         if (sc->bge_flags & BGE_FLAG_PCIE) {
3271                 reset = bge_readmem_ind(sc, 0x7C00);
3272                 bge_writemem_ind(sc, 0x7C00, reset | (1 << 25));
3273         }
3274
3275         /* Fix up byte swapping. */
3276         CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS |
3277             BGE_MODECTL_BYTESWAP_DATA);
3278
3279         /* Tell the ASF firmware we are up */
3280         if (sc->bge_asf_mode & ASF_STACKUP)
3281                 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
3282
3283         CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
3284
3285         /*
3286          * The 5704 in TBI mode apparently needs some special
3287          * adjustment to insure the SERDES drive level is set
3288          * to 1.2V.
3289          */
3290         if (sc->bge_asicrev == BGE_ASICREV_BCM5704 &&
3291             sc->bge_flags & BGE_FLAG_TBI) {
3292                 val = CSR_READ_4(sc, BGE_SERDES_CFG);
3293                 val = (val & ~0xFFF) | 0x880;
3294                 CSR_WRITE_4(sc, BGE_SERDES_CFG, val);
3295         }
3296
3297         /* XXX: Broadcom Linux driver. */
3298         if (sc->bge_flags & BGE_FLAG_PCIE &&
3299             sc->bge_chipid != BGE_CHIPID_BCM5750_A0) {
3300                 val = CSR_READ_4(sc, 0x7C00);
3301                 CSR_WRITE_4(sc, 0x7C00, val | (1 << 25));
3302         }
3303         DELAY(10000);
3304
3305         return(0);
3306 }
3307
3308 static __inline void
3309 bge_rxreuse_std(struct bge_softc *sc, int i)
3310 {
3311         struct bge_rx_bd *r;
3312
3313         r = &sc->bge_ldata.bge_rx_std_ring[sc->bge_std];
3314         r->bge_flags = BGE_RXBDFLAG_END;
3315         r->bge_len = sc->bge_cdata.bge_rx_std_seglen[i];
3316         r->bge_idx = i;
3317         BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT);
3318 }
3319
3320 static __inline void
3321 bge_rxreuse_jumbo(struct bge_softc *sc, int i)
3322 {
3323         struct bge_extrx_bd *r;
3324
3325         r = &sc->bge_ldata.bge_rx_jumbo_ring[sc->bge_jumbo];
3326         r->bge_flags = BGE_RXBDFLAG_JUMBO_RING | BGE_RXBDFLAG_END;
3327         r->bge_len0 = sc->bge_cdata.bge_rx_jumbo_seglen[i][0];
3328         r->bge_len1 = sc->bge_cdata.bge_rx_jumbo_seglen[i][1];
3329         r->bge_len2 = sc->bge_cdata.bge_rx_jumbo_seglen[i][2];
3330         r->bge_len3 = sc->bge_cdata.bge_rx_jumbo_seglen[i][3];
3331         r->bge_idx = i;
3332         BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT);
3333 }
3334
3335 /*
3336  * Frame reception handling. This is called if there's a frame
3337  * on the receive return list.
3338  *
3339  * Note: we have to be able to handle two possibilities here:
3340  * 1) the frame is from the jumbo receive ring
3341  * 2) the frame is from the standard receive ring
3342  */
3343
3344 static int
3345 bge_rxeof(struct bge_softc *sc, uint16_t rx_prod, int holdlck)
3346 {
3347         struct ifnet *ifp;
3348         int rx_npkts = 0, stdcnt = 0, jumbocnt = 0;
3349         uint16_t rx_cons;
3350
3351         rx_cons = sc->bge_rx_saved_considx;
3352
3353         /* Nothing to do. */
3354         if (rx_cons == rx_prod)
3355                 return (rx_npkts);
3356
3357         ifp = sc->bge_ifp;
3358
3359         bus_dmamap_sync(sc->bge_cdata.bge_rx_return_ring_tag,
3360             sc->bge_cdata.bge_rx_return_ring_map, BUS_DMASYNC_POSTREAD);
3361         bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
3362             sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_POSTWRITE);
3363         if (ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN >
3364             (MCLBYTES - ETHER_ALIGN))
3365                 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
3366                     sc->bge_cdata.bge_rx_jumbo_ring_map, BUS_DMASYNC_POSTWRITE);
3367
3368         while (rx_cons != rx_prod) {
3369                 struct bge_rx_bd        *cur_rx;
3370                 uint32_t                rxidx;
3371                 struct mbuf             *m = NULL;
3372                 uint16_t                vlan_tag = 0;
3373                 int                     have_tag = 0;
3374
3375 #ifdef DEVICE_POLLING
3376                 if (ifp->if_capenable & IFCAP_POLLING) {
3377                         if (sc->rxcycles <= 0)
3378                                 break;
3379                         sc->rxcycles--;
3380                 }
3381 #endif
3382
3383                 cur_rx = &sc->bge_ldata.bge_rx_return_ring[rx_cons];
3384
3385                 rxidx = cur_rx->bge_idx;
3386                 BGE_INC(rx_cons, sc->bge_return_ring_cnt);
3387
3388                 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING &&
3389                     cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) {
3390                         have_tag = 1;
3391                         vlan_tag = cur_rx->bge_vlan_tag;
3392                 }
3393
3394                 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) {
3395                         jumbocnt++;
3396                         m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx];
3397                         if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
3398                                 bge_rxreuse_jumbo(sc, rxidx);
3399                                 continue;
3400                         }
3401                         if (bge_newbuf_jumbo(sc, rxidx) != 0) {
3402                                 bge_rxreuse_jumbo(sc, rxidx);
3403                                 ifp->if_iqdrops++;
3404                                 continue;
3405                         }
3406                         BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT);
3407                 } else {
3408                         stdcnt++;
3409                         m = sc->bge_cdata.bge_rx_std_chain[rxidx];
3410                         if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
3411                                 bge_rxreuse_std(sc, rxidx);
3412                                 continue;
3413                         }
3414                         if (bge_newbuf_std(sc, rxidx) != 0) {
3415                                 bge_rxreuse_std(sc, rxidx);
3416                                 ifp->if_iqdrops++;
3417                                 continue;
3418                         }
3419                         BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT);
3420                 }
3421
3422                 ifp->if_ipackets++;
3423 #ifndef __NO_STRICT_ALIGNMENT
3424                 /*
3425                  * For architectures with strict alignment we must make sure
3426                  * the payload is aligned.
3427                  */
3428                 if (sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) {
3429                         bcopy(m->m_data, m->m_data + ETHER_ALIGN,
3430                             cur_rx->bge_len);
3431                         m->m_data += ETHER_ALIGN;
3432                 }
3433 #endif
3434                 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN;
3435                 m->m_pkthdr.rcvif = ifp;
3436
3437                 if (ifp->if_capenable & IFCAP_RXCSUM) {
3438                         if (cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) {
3439                                 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
3440                                 if ((cur_rx->bge_ip_csum ^ 0xFFFF) == 0)
3441                                         m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
3442                         }
3443                         if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM &&
3444                             m->m_pkthdr.len >= ETHER_MIN_NOPAD) {
3445                                 m->m_pkthdr.csum_data =
3446                                     cur_rx->bge_tcp_udp_csum;
3447                                 m->m_pkthdr.csum_flags |=
3448                                     CSUM_DATA_VALID | CSUM_PSEUDO_HDR;
3449                         }
3450                 }
3451
3452                 /*
3453                  * If we received a packet with a vlan tag,
3454                  * attach that information to the packet.
3455                  */
3456                 if (have_tag) {
3457 #if __FreeBSD_version > 700022
3458                         m->m_pkthdr.ether_vtag = vlan_tag;
3459                         m->m_flags |= M_VLANTAG;
3460 #else
3461                         VLAN_INPUT_TAG_NEW(ifp, m, vlan_tag);
3462                         if (m == NULL)
3463                                 continue;
3464 #endif
3465                 }
3466
3467                 if (holdlck != 0) {
3468                         BGE_UNLOCK(sc);
3469                         (*ifp->if_input)(ifp, m);
3470                         BGE_LOCK(sc);
3471                 } else
3472                         (*ifp->if_input)(ifp, m);
3473                 rx_npkts++;
3474
3475                 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING))
3476                         return (rx_npkts);
3477         }
3478
3479         bus_dmamap_sync(sc->bge_cdata.bge_rx_return_ring_tag,
3480             sc->bge_cdata.bge_rx_return_ring_map, BUS_DMASYNC_PREREAD);
3481         if (stdcnt > 0)
3482                 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
3483                     sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREWRITE);
3484
3485         if (jumbocnt > 0)
3486                 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
3487                     sc->bge_cdata.bge_rx_jumbo_ring_map, BUS_DMASYNC_PREWRITE);
3488
3489         sc->bge_rx_saved_considx = rx_cons;
3490         bge_writembx(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx);
3491         if (stdcnt)
3492                 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std);
3493         if (jumbocnt)
3494                 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo);
3495 #ifdef notyet
3496         /*
3497          * This register wraps very quickly under heavy packet drops.
3498          * If you need correct statistics, you can enable this check.
3499          */
3500         if (BGE_IS_5705_PLUS(sc))
3501                 ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS);
3502 #endif
3503         return (rx_npkts);
3504 }
3505
3506 static void
3507 bge_txeof(struct bge_softc *sc, uint16_t tx_cons)
3508 {
3509         struct bge_tx_bd *cur_tx = NULL;
3510         struct ifnet *ifp;
3511
3512         BGE_LOCK_ASSERT(sc);
3513
3514         /* Nothing to do. */
3515         if (sc->bge_tx_saved_considx == tx_cons)
3516                 return;
3517
3518         ifp = sc->bge_ifp;
3519
3520         bus_dmamap_sync(sc->bge_cdata.bge_tx_ring_tag,
3521             sc->bge_cdata.bge_tx_ring_map, BUS_DMASYNC_POSTWRITE);
3522         /*
3523          * Go through our tx ring and free mbufs for those
3524          * frames that have been sent.
3525          */
3526         while (sc->bge_tx_saved_considx != tx_cons) {
3527                 uint32_t                idx = 0;
3528
3529                 idx = sc->bge_tx_saved_considx;
3530                 cur_tx = &sc->bge_ldata.bge_tx_ring[idx];
3531                 if (cur_tx->bge_flags & BGE_TXBDFLAG_END)
3532                         ifp->if_opackets++;
3533                 if (sc->bge_cdata.bge_tx_chain[idx] != NULL) {
3534                         bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag,
3535                             sc->bge_cdata.bge_tx_dmamap[idx],
3536                             BUS_DMASYNC_POSTWRITE);
3537                         bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag,
3538                             sc->bge_cdata.bge_tx_dmamap[idx]);
3539                         m_freem(sc->bge_cdata.bge_tx_chain[idx]);
3540                         sc->bge_cdata.bge_tx_chain[idx] = NULL;
3541                 }
3542                 sc->bge_txcnt--;
3543                 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT);
3544         }
3545
3546         if (cur_tx != NULL)
3547                 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
3548         if (sc->bge_txcnt == 0)
3549                 sc->bge_timer = 0;
3550 }
3551
3552 #ifdef DEVICE_POLLING
3553 static int
3554 bge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
3555 {
3556         struct bge_softc *sc = ifp->if_softc;
3557         uint16_t rx_prod, tx_cons;
3558         uint32_t statusword;
3559         int rx_npkts = 0;
3560
3561         BGE_LOCK(sc);
3562         if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) {
3563                 BGE_UNLOCK(sc);
3564                 return (rx_npkts);
3565         }
3566
3567         bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
3568             sc->bge_cdata.bge_status_map,
3569             BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
3570         rx_prod = sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx;
3571         tx_cons = sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx;
3572
3573         statusword = atomic_readandclear_32(
3574             &sc->bge_ldata.bge_status_block->bge_status);
3575
3576         bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
3577             sc->bge_cdata.bge_status_map,
3578             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3579
3580         /* Note link event. It will be processed by POLL_AND_CHECK_STATUS. */
3581         if (statusword & BGE_STATFLAG_LINKSTATE_CHANGED)
3582                 sc->bge_link_evt++;
3583
3584         if (cmd == POLL_AND_CHECK_STATUS)
3585                 if ((sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
3586                     sc->bge_chipid != BGE_CHIPID_BCM5700_B2) ||
3587                     sc->bge_link_evt || (sc->bge_flags & BGE_FLAG_TBI))
3588                         bge_link_upd(sc);
3589
3590         sc->rxcycles = count;
3591         rx_npkts = bge_rxeof(sc, rx_prod, 1);
3592         if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) {
3593                 BGE_UNLOCK(sc);
3594                 return (rx_npkts);
3595         }
3596         bge_txeof(sc, tx_cons);
3597         if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
3598                 bge_start_locked(ifp);
3599
3600         BGE_UNLOCK(sc);
3601         return (rx_npkts);
3602 }
3603 #endif /* DEVICE_POLLING */
3604
3605 static int
3606 bge_msi_intr(void *arg)
3607 {
3608         struct bge_softc *sc;
3609
3610         sc = (struct bge_softc *)arg;
3611         /*
3612          * This interrupt is not shared and controller already
3613          * disabled further interrupt.
3614          */
3615         taskqueue_enqueue(sc->bge_tq, &sc->bge_intr_task);
3616         return (FILTER_HANDLED);
3617 }
3618
3619 static void
3620 bge_intr_task(void *arg, int pending)
3621 {
3622         struct bge_softc *sc;
3623         struct ifnet *ifp;
3624         uint32_t status;
3625         uint16_t rx_prod, tx_cons;
3626
3627         sc = (struct bge_softc *)arg;
3628         ifp = sc->bge_ifp;
3629
3630         if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
3631                 return;
3632
3633         /* Get updated status block. */
3634         bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
3635             sc->bge_cdata.bge_status_map,
3636             BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
3637
3638         /* Save producer/consumer indexess. */
3639         rx_prod = sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx;
3640         tx_cons = sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx;
3641         status = sc->bge_ldata.bge_status_block->bge_status;
3642         sc->bge_ldata.bge_status_block->bge_status = 0;
3643         bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
3644             sc->bge_cdata.bge_status_map,
3645             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3646         /* Let controller work. */
3647         bge_writembx(sc, BGE_MBX_IRQ0_LO, 0);
3648
3649         if ((status & BGE_STATFLAG_LINKSTATE_CHANGED) != 0) {
3650                 BGE_LOCK(sc);
3651                 bge_link_upd(sc);
3652                 BGE_UNLOCK(sc);
3653         }
3654         if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
3655                 /* Check RX return ring producer/consumer. */
3656                 bge_rxeof(sc, rx_prod, 0);
3657         }
3658         if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
3659                 BGE_LOCK(sc);
3660                 /* Check TX ring producer/consumer. */
3661                 bge_txeof(sc, tx_cons);
3662                 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
3663                         bge_start_locked(ifp);
3664                 BGE_UNLOCK(sc);
3665         }
3666 }
3667
3668 static void
3669 bge_intr(void *xsc)
3670 {
3671         struct bge_softc *sc;
3672         struct ifnet *ifp;
3673         uint32_t statusword;
3674         uint16_t rx_prod, tx_cons;
3675
3676         sc = xsc;
3677
3678         BGE_LOCK(sc);
3679
3680         ifp = sc->bge_ifp;
3681
3682 #ifdef DEVICE_POLLING
3683         if (ifp->if_capenable & IFCAP_POLLING) {
3684                 BGE_UNLOCK(sc);
3685                 return;
3686         }
3687 #endif
3688
3689         /*
3690          * Ack the interrupt by writing something to BGE_MBX_IRQ0_LO.  Don't
3691          * disable interrupts by writing nonzero like we used to, since with
3692          * our current organization this just gives complications and
3693          * pessimizations for re-enabling interrupts.  We used to have races
3694          * instead of the necessary complications.  Disabling interrupts
3695          * would just reduce the chance of a status update while we are
3696          * running (by switching to the interrupt-mode coalescence
3697          * parameters), but this chance is already very low so it is more
3698          * efficient to get another interrupt than prevent it.
3699          *
3700          * We do the ack first to ensure another interrupt if there is a
3701          * status update after the ack.  We don't check for the status
3702          * changing later because it is more efficient to get another
3703          * interrupt than prevent it, not quite as above (not checking is
3704          * a smaller optimization than not toggling the interrupt enable,
3705          * since checking doesn't involve PCI accesses and toggling require
3706          * the status check).  So toggling would probably be a pessimization
3707          * even with MSI.  It would only be needed for using a task queue.
3708          */
3709         bge_writembx(sc, BGE_MBX_IRQ0_LO, 0);
3710
3711         /*
3712          * Do the mandatory PCI flush as well as get the link status.
3713          */
3714         statusword = CSR_READ_4(sc, BGE_MAC_STS) & BGE_MACSTAT_LINK_CHANGED;
3715
3716         /* Make sure the descriptor ring indexes are coherent. */
3717         bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
3718             sc->bge_cdata.bge_status_map,
3719             BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
3720         rx_prod = sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx;
3721         tx_cons = sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx;
3722         sc->bge_ldata.bge_status_block->bge_status = 0;
3723         bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
3724             sc->bge_cdata.bge_status_map,
3725             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3726
3727         if ((sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
3728             sc->bge_chipid != BGE_CHIPID_BCM5700_B2) ||
3729             statusword || sc->bge_link_evt)
3730                 bge_link_upd(sc);
3731
3732         if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
3733                 /* Check RX return ring producer/consumer. */
3734                 bge_rxeof(sc, rx_prod, 1);
3735         }
3736
3737         if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
3738                 /* Check TX ring producer/consumer. */
3739                 bge_txeof(sc, tx_cons);
3740         }
3741
3742         if (ifp->if_drv_flags & IFF_DRV_RUNNING &&
3743             !IFQ_DRV_IS_EMPTY(&ifp->if_snd))
3744                 bge_start_locked(ifp);
3745
3746         BGE_UNLOCK(sc);
3747 }
3748
3749 static void
3750 bge_asf_driver_up(struct bge_softc *sc)
3751 {
3752         if (sc->bge_asf_mode & ASF_STACKUP) {
3753                 /* Send ASF heartbeat aprox. every 2s */
3754                 if (sc->bge_asf_count)
3755                         sc->bge_asf_count --;
3756                 else {
3757                         sc->bge_asf_count = 2;
3758                         bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM_FW,
3759                             BGE_FW_DRV_ALIVE);
3760                         bge_writemem_ind(sc, BGE_SOFTWARE_GENNCOMM_FW_LEN, 4);
3761                         bge_writemem_ind(sc, BGE_SOFTWARE_GENNCOMM_FW_DATA, 3);
3762                         CSR_WRITE_4(sc, BGE_CPU_EVENT,
3763                             CSR_READ_4(sc, BGE_CPU_EVENT) | (1 << 14));
3764                 }
3765         }
3766 }
3767
3768 static void
3769 bge_tick(void *xsc)
3770 {
3771         struct bge_softc *sc = xsc;
3772         struct mii_data *mii = NULL;
3773
3774         BGE_LOCK_ASSERT(sc);
3775
3776         /* Synchronize with possible callout reset/stop. */
3777         if (callout_pending(&sc->bge_stat_ch) ||
3778             !callout_active(&sc->bge_stat_ch))
3779                 return;
3780
3781         if (BGE_IS_5705_PLUS(sc))
3782                 bge_stats_update_regs(sc);
3783         else
3784                 bge_stats_update(sc);
3785
3786         if ((sc->bge_flags & BGE_FLAG_TBI) == 0) {
3787                 mii = device_get_softc(sc->bge_miibus);
3788                 /*
3789                  * Do not touch PHY if we have link up. This could break
3790                  * IPMI/ASF mode or produce extra input errors
3791                  * (extra errors was reported for bcm5701 & bcm5704).
3792                  */
3793                 if (!sc->bge_link)
3794                         mii_tick(mii);
3795         } else {
3796                 /*
3797                  * Since in TBI mode auto-polling can't be used we should poll
3798                  * link status manually. Here we register pending link event
3799                  * and trigger interrupt.
3800                  */
3801 #ifdef DEVICE_POLLING
3802                 /* In polling mode we poll link state in bge_poll(). */
3803                 if (!(sc->bge_ifp->if_capenable & IFCAP_POLLING))
3804 #endif
3805                 {
3806                 sc->bge_link_evt++;
3807                 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
3808                     sc->bge_flags & BGE_FLAG_5788)
3809                         BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET);
3810                 else
3811                         BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW);
3812                 }
3813         }
3814
3815         bge_asf_driver_up(sc);
3816         bge_watchdog(sc);
3817
3818         callout_reset(&sc->bge_stat_ch, hz, bge_tick, sc);
3819 }
3820
3821 static void
3822 bge_stats_update_regs(struct bge_softc *sc)
3823 {
3824         struct ifnet *ifp;
3825
3826         ifp = sc->bge_ifp;
3827
3828         ifp->if_collisions += CSR_READ_4(sc, BGE_MAC_STATS +
3829             offsetof(struct bge_mac_stats_regs, etherStatsCollisions));
3830
3831         ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_OUT_OF_BDS);
3832         ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS);
3833         ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_ERRORS);
3834 }
3835
3836 static void
3837 bge_stats_update(struct bge_softc *sc)
3838 {
3839         struct ifnet *ifp;
3840         bus_size_t stats;
3841         uint32_t cnt;   /* current register value */
3842
3843         ifp = sc->bge_ifp;
3844
3845         stats = BGE_MEMWIN_START + BGE_STATS_BLOCK;
3846
3847 #define READ_STAT(sc, stats, stat) \
3848         CSR_READ_4(sc, stats + offsetof(struct bge_stats, stat))
3849
3850         cnt = READ_STAT(sc, stats, txstats.etherStatsCollisions.bge_addr_lo);
3851         ifp->if_collisions += (uint32_t)(cnt - sc->bge_tx_collisions);
3852         sc->bge_tx_collisions = cnt;
3853
3854         cnt = READ_STAT(sc, stats, ifInDiscards.bge_addr_lo);
3855         ifp->if_ierrors += (uint32_t)(cnt - sc->bge_rx_discards);
3856         sc->bge_rx_discards = cnt;
3857
3858         cnt = READ_STAT(sc, stats, txstats.ifOutDiscards.bge_addr_lo);
3859         ifp->if_oerrors += (uint32_t)(cnt - sc->bge_tx_discards);
3860         sc->bge_tx_discards = cnt;
3861
3862 #undef  READ_STAT
3863 }
3864
3865 /*
3866  * Pad outbound frame to ETHER_MIN_NOPAD for an unusual reason.
3867  * The bge hardware will pad out Tx runts to ETHER_MIN_NOPAD,
3868  * but when such padded frames employ the bge IP/TCP checksum offload,
3869  * the hardware checksum assist gives incorrect results (possibly
3870  * from incorporating its own padding into the UDP/TCP checksum; who knows).
3871  * If we pad such runts with zeros, the onboard checksum comes out correct.
3872  */
3873 static __inline int
3874 bge_cksum_pad(struct mbuf *m)
3875 {
3876         int padlen = ETHER_MIN_NOPAD - m->m_pkthdr.len;
3877         struct mbuf *last;
3878
3879         /* If there's only the packet-header and we can pad there, use it. */
3880         if (m->m_pkthdr.len == m->m_len && M_WRITABLE(m) &&
3881             M_TRAILINGSPACE(m) >= padlen) {
3882                 last = m;
3883         } else {
3884                 /*
3885                  * Walk packet chain to find last mbuf. We will either
3886                  * pad there, or append a new mbuf and pad it.
3887                  */
3888                 for (last = m; last->m_next != NULL; last = last->m_next);
3889                 if (!(M_WRITABLE(last) && M_TRAILINGSPACE(last) >= padlen)) {
3890                         /* Allocate new empty mbuf, pad it. Compact later. */
3891                         struct mbuf *n;
3892
3893                         MGET(n, M_DONTWAIT, MT_DATA);
3894                         if (n == NULL)
3895                                 return (ENOBUFS);
3896                         n->m_len = 0;
3897                         last->m_next = n;
3898                         last = n;
3899                 }
3900         }
3901
3902         /* Now zero the pad area, to avoid the bge cksum-assist bug. */
3903         memset(mtod(last, caddr_t) + last->m_len, 0, padlen);
3904         last->m_len += padlen;
3905         m->m_pkthdr.len += padlen;
3906
3907         return (0);
3908 }
3909
3910 static struct mbuf *
3911 bge_setup_tso(struct bge_softc *sc, struct mbuf *m, uint16_t *mss)
3912 {
3913         struct ip *ip;
3914         struct tcphdr *tcp;
3915         struct mbuf *n;
3916         uint16_t hlen;
3917         uint32_t poff;
3918
3919         if (M_WRITABLE(m) == 0) {
3920                 /* Get a writable copy. */
3921                 n = m_dup(m, M_DONTWAIT);
3922                 m_freem(m);
3923                 if (n == NULL)
3924                         return (NULL);
3925                 m = n;
3926         }
3927         m = m_pullup(m, sizeof(struct ether_header) + sizeof(struct ip));
3928         if (m == NULL)
3929                 return (NULL);
3930         ip = (struct ip *)(mtod(m, char *) + sizeof(struct ether_header));
3931         poff = sizeof(struct ether_header) + (ip->ip_hl << 2);
3932         m = m_pullup(m, poff + sizeof(struct tcphdr));
3933         if (m == NULL)
3934                 return (NULL);
3935         tcp = (struct tcphdr *)(mtod(m, char *) + poff);
3936         m = m_pullup(m, poff + (tcp->th_off << 2));
3937         if (m == NULL)
3938                 return (NULL);
3939         /*
3940          * It seems controller doesn't modify IP length and TCP pseudo
3941          * checksum. These checksum computed by upper stack should be 0.
3942          */
3943         *mss = m->m_pkthdr.tso_segsz;
3944         ip->ip_sum = 0;
3945         ip->ip_len = htons(*mss + (ip->ip_hl << 2) + (tcp->th_off << 2));
3946         /* Clear pseudo checksum computed by TCP stack. */
3947         tcp->th_sum = 0;
3948         /*
3949          * Broadcom controllers uses different descriptor format for
3950          * TSO depending on ASIC revision. Due to TSO-capable firmware
3951          * license issue and lower performance of firmware based TSO
3952          * we only support hardware based TSO which is applicable for
3953          * BCM5755 or newer controllers. Hardware based TSO uses 11
3954          * bits to store MSS and upper 5 bits are used to store IP/TCP
3955          * header length(including IP/TCP options). The header length
3956          * is expressed as 32 bits unit.
3957          */
3958         hlen = ((ip->ip_hl << 2) + (tcp->th_off << 2)) >> 2;
3959         *mss |= (hlen << 11);
3960         return (m);
3961 }
3962
3963 /*
3964  * Encapsulate an mbuf chain in the tx ring  by coupling the mbuf data
3965  * pointers to descriptors.
3966  */
3967 static int
3968 bge_encap(struct bge_softc *sc, struct mbuf **m_head, uint32_t *txidx)
3969 {
3970         bus_dma_segment_t       segs[BGE_NSEG_NEW];
3971         bus_dmamap_t            map;
3972         struct bge_tx_bd        *d;
3973         struct mbuf             *m = *m_head;
3974         uint32_t                idx = *txidx;
3975         uint16_t                csum_flags, mss, vlan_tag;
3976         int                     nsegs, i, error;
3977
3978         csum_flags = 0;
3979         mss = 0;
3980         vlan_tag = 0;
3981         if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) {
3982                 *m_head = m = bge_setup_tso(sc, m, &mss);
3983                 if (*m_head == NULL)
3984                         return (ENOBUFS);
3985                 csum_flags |= BGE_TXBDFLAG_CPU_PRE_DMA |
3986                     BGE_TXBDFLAG_CPU_POST_DMA;
3987         } else if ((m->m_pkthdr.csum_flags & BGE_CSUM_FEATURES) != 0) {
3988                 if (m->m_pkthdr.csum_flags & CSUM_IP)
3989                         csum_flags |= BGE_TXBDFLAG_IP_CSUM;
3990                 if (m->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP)) {
3991                         csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM;
3992                         if (m->m_pkthdr.len < ETHER_MIN_NOPAD &&
3993                             (error = bge_cksum_pad(m)) != 0) {
3994                                 m_freem(m);
3995                                 *m_head = NULL;
3996                                 return (error);
3997                         }
3998                 }
3999                 if (m->m_flags & M_LASTFRAG)
4000                         csum_flags |= BGE_TXBDFLAG_IP_FRAG_END;
4001                 else if (m->m_flags & M_FRAG)
4002                         csum_flags |= BGE_TXBDFLAG_IP_FRAG;
4003         }
4004
4005         if ((m->m_pkthdr.csum_flags & CSUM_TSO) == 0 &&
4006             sc->bge_forced_collapse > 0 &&
4007             (sc->bge_flags & BGE_FLAG_PCIE) != 0 && m->m_next != NULL) {
4008                 /*
4009                  * Forcedly collapse mbuf chains to overcome hardware
4010                  * limitation which only support a single outstanding
4011                  * DMA read operation.
4012                  */
4013                 if (sc->bge_forced_collapse == 1)
4014                         m = m_defrag(m, M_DONTWAIT);
4015                 else
4016                         m = m_collapse(m, M_DONTWAIT, sc->bge_forced_collapse);
4017                 if (m == NULL)
4018                         m = *m_head;
4019                 *m_head = m;
4020         }
4021
4022         map = sc->bge_cdata.bge_tx_dmamap[idx];
4023         error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_tx_mtag, map, m, segs,
4024             &nsegs, BUS_DMA_NOWAIT);
4025         if (error == EFBIG) {
4026                 m = m_collapse(m, M_DONTWAIT, BGE_NSEG_NEW);
4027                 if (m == NULL) {
4028                         m_freem(*m_head);
4029                         *m_head = NULL;
4030                         return (ENOBUFS);
4031                 }
4032                 *m_head = m;
4033                 error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_tx_mtag, map,
4034                     m, segs, &nsegs, BUS_DMA_NOWAIT);
4035                 if (error) {
4036                         m_freem(m);
4037                         *m_head = NULL;
4038                         return (error);
4039                 }
4040         } else if (error != 0)
4041                 return (error);
4042
4043         /* Check if we have enough free send BDs. */
4044         if (sc->bge_txcnt + nsegs >= BGE_TX_RING_CNT) {
4045                 bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag, map);
4046                 return (ENOBUFS);
4047         }
4048
4049         bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag, map, BUS_DMASYNC_PREWRITE);
4050
4051 #if __FreeBSD_version > 700022
4052         if (m->m_flags & M_VLANTAG) {
4053                 csum_flags |= BGE_TXBDFLAG_VLAN_TAG;
4054                 vlan_tag = m->m_pkthdr.ether_vtag;
4055         }
4056 #else
4057         {
4058                 struct m_tag            *mtag;
4059
4060                 if ((mtag = VLAN_OUTPUT_TAG(sc->bge_ifp, m)) != NULL) {
4061                         csum_flags |= BGE_TXBDFLAG_VLAN_TAG;
4062                         vlan_tag = VLAN_TAG_VALUE(mtag);
4063                 }
4064         }
4065 #endif
4066         for (i = 0; ; i++) {
4067                 d = &sc->bge_ldata.bge_tx_ring[idx];
4068                 d->bge_addr.bge_addr_lo = BGE_ADDR_LO(segs[i].ds_addr);
4069                 d->bge_addr.bge_addr_hi = BGE_ADDR_HI(segs[i].ds_addr);
4070                 d->bge_len = segs[i].ds_len;
4071                 d->bge_flags = csum_flags;
4072                 d->bge_vlan_tag = vlan_tag;
4073                 d->bge_mss = mss;
4074                 if (i == nsegs - 1)
4075                         break;
4076                 BGE_INC(idx, BGE_TX_RING_CNT);
4077         }
4078
4079         /* Mark the last segment as end of packet... */
4080         d->bge_flags |= BGE_TXBDFLAG_END;
4081
4082         /*
4083          * Insure that the map for this transmission
4084          * is placed at the array index of the last descriptor
4085          * in this chain.
4086          */
4087         sc->bge_cdata.bge_tx_dmamap[*txidx] = sc->bge_cdata.bge_tx_dmamap[idx];
4088         sc->bge_cdata.bge_tx_dmamap[idx] = map;
4089         sc->bge_cdata.bge_tx_chain[idx] = m;
4090         sc->bge_txcnt += nsegs;
4091
4092         BGE_INC(idx, BGE_TX_RING_CNT);
4093         *txidx = idx;
4094
4095         return (0);
4096 }
4097
4098 /*
4099  * Main transmit routine. To avoid having to do mbuf copies, we put pointers
4100  * to the mbuf data regions directly in the transmit descriptors.
4101  */
4102 static void
4103 bge_start_locked(struct ifnet *ifp)
4104 {
4105         struct bge_softc *sc;
4106         struct mbuf *m_head;
4107         uint32_t prodidx;
4108         int count;
4109
4110         sc = ifp->if_softc;
4111         BGE_LOCK_ASSERT(sc);
4112
4113         if (!sc->bge_link ||
4114             (ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
4115             IFF_DRV_RUNNING)
4116                 return;
4117
4118         prodidx = sc->bge_tx_prodidx;
4119
4120         for (count = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd);) {
4121                 if (sc->bge_txcnt > BGE_TX_RING_CNT - 16) {
4122                         ifp->if_drv_flags |= IFF_DRV_OACTIVE;
4123                         break;
4124                 }
4125                 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
4126                 if (m_head == NULL)
4127                         break;
4128
4129                 /*
4130                  * XXX
4131                  * The code inside the if() block is never reached since we
4132                  * must mark CSUM_IP_FRAGS in our if_hwassist to start getting
4133                  * requests to checksum TCP/UDP in a fragmented packet.
4134                  *
4135                  * XXX
4136                  * safety overkill.  If this is a fragmented packet chain
4137                  * with delayed TCP/UDP checksums, then only encapsulate
4138                  * it if we have enough descriptors to handle the entire
4139                  * chain at once.
4140                  * (paranoia -- may not actually be needed)
4141                  */
4142                 if (m_head->m_flags & M_FIRSTFRAG &&
4143                     m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) {
4144                         if ((BGE_TX_RING_CNT - sc->bge_txcnt) <
4145                             m_head->m_pkthdr.csum_data + 16) {
4146                                 IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
4147                                 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
4148                                 break;
4149                         }
4150                 }
4151
4152                 /*
4153                  * Pack the data into the transmit ring. If we
4154                  * don't have room, set the OACTIVE flag and wait
4155                  * for the NIC to drain the ring.
4156                  */
4157                 if (bge_encap(sc, &m_head, &prodidx)) {
4158                         if (m_head == NULL)
4159                                 break;
4160                         IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
4161                         ifp->if_drv_flags |= IFF_DRV_OACTIVE;
4162                         break;
4163                 }
4164                 ++count;
4165
4166                 /*
4167                  * If there's a BPF listener, bounce a copy of this frame
4168                  * to him.
4169                  */
4170 #ifdef ETHER_BPF_MTAP
4171                 ETHER_BPF_MTAP(ifp, m_head);
4172 #else
4173                 BPF_MTAP(ifp, m_head);
4174 #endif
4175         }
4176
4177         if (count > 0) {
4178                 bus_dmamap_sync(sc->bge_cdata.bge_tx_ring_tag,
4179                     sc->bge_cdata.bge_tx_ring_map, BUS_DMASYNC_PREWRITE);
4180                 /* Transmit. */
4181                 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
4182                 /* 5700 b2 errata */
4183                 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
4184                         bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
4185
4186                 sc->bge_tx_prodidx = prodidx;
4187
4188                 /*
4189                  * Set a timeout in case the chip goes out to lunch.
4190                  */
4191                 sc->bge_timer = 5;
4192         }
4193 }
4194
4195 /*
4196  * Main transmit routine. To avoid having to do mbuf copies, we put pointers
4197  * to the mbuf data regions directly in the transmit descriptors.
4198  */
4199 static void
4200 bge_start(struct ifnet *ifp)
4201 {
4202         struct bge_softc *sc;
4203
4204         sc = ifp->if_softc;
4205         BGE_LOCK(sc);
4206         bge_start_locked(ifp);
4207         BGE_UNLOCK(sc);
4208 }
4209
4210 static void
4211 bge_init_locked(struct bge_softc *sc)
4212 {
4213         struct ifnet *ifp;
4214         uint16_t *m;
4215
4216         BGE_LOCK_ASSERT(sc);
4217
4218         ifp = sc->bge_ifp;
4219
4220         if (ifp->if_drv_flags & IFF_DRV_RUNNING)
4221                 return;
4222
4223         /* Cancel pending I/O and flush buffers. */
4224         bge_stop(sc);
4225
4226         bge_stop_fw(sc);
4227         bge_sig_pre_reset(sc, BGE_RESET_START);
4228         bge_reset(sc);
4229         bge_sig_legacy(sc, BGE_RESET_START);
4230         bge_sig_post_reset(sc, BGE_RESET_START);
4231
4232         bge_chipinit(sc);
4233
4234         /*
4235          * Init the various state machines, ring
4236          * control blocks and firmware.
4237          */
4238         if (bge_blockinit(sc)) {
4239                 device_printf(sc->bge_dev, "initialization failure\n");
4240                 return;
4241         }
4242
4243         ifp = sc->bge_ifp;
4244
4245         /* Specify MTU. */
4246         CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu +
4247             ETHER_HDR_LEN + ETHER_CRC_LEN +
4248             (ifp->if_capenable & IFCAP_VLAN_MTU ? ETHER_VLAN_ENCAP_LEN : 0));
4249
4250         /* Load our MAC address. */
4251         m = (uint16_t *)IF_LLADDR(sc->bge_ifp);
4252         CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0]));
4253         CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2]));
4254
4255         /* Program promiscuous mode. */
4256         bge_setpromisc(sc);
4257
4258         /* Program multicast filter. */
4259         bge_setmulti(sc);
4260
4261         /* Program VLAN tag stripping. */
4262         bge_setvlan(sc);
4263
4264         /* Init RX ring. */
4265         if (bge_init_rx_ring_std(sc) != 0) {
4266                 device_printf(sc->bge_dev, "no memory for std Rx buffers.\n");
4267                 bge_stop(sc);
4268                 return;
4269         }
4270
4271         /*
4272          * Workaround for a bug in 5705 ASIC rev A0. Poll the NIC's
4273          * memory to insure that the chip has in fact read the first
4274          * entry of the ring.
4275          */
4276         if (sc->bge_chipid == BGE_CHIPID_BCM5705_A0) {
4277                 uint32_t                v, i;
4278                 for (i = 0; i < 10; i++) {
4279                         DELAY(20);
4280                         v = bge_readmem_ind(sc, BGE_STD_RX_RINGS + 8);
4281                         if (v == (MCLBYTES - ETHER_ALIGN))
4282                                 break;
4283                 }
4284                 if (i == 10)
4285                         device_printf (sc->bge_dev,
4286                             "5705 A0 chip failed to load RX ring\n");
4287         }
4288
4289         /* Init jumbo RX ring. */
4290         if (ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN >
4291             (MCLBYTES - ETHER_ALIGN)) {
4292                 if (bge_init_rx_ring_jumbo(sc) != 0) {
4293                         device_printf(sc->bge_dev, "no memory for std Rx buffers.\n");
4294                         bge_stop(sc);
4295                         return;
4296                 }
4297         }
4298
4299         /* Init our RX return ring index. */
4300         sc->bge_rx_saved_considx = 0;
4301
4302         /* Init our RX/TX stat counters. */
4303         sc->bge_rx_discards = sc->bge_tx_discards = sc->bge_tx_collisions = 0;
4304
4305         /* Init TX ring. */
4306         bge_init_tx_ring(sc);
4307
4308         /* Turn on transmitter. */
4309         BGE_SETBIT(sc, BGE_TX_MODE, BGE_TXMODE_ENABLE);
4310
4311         /* Turn on receiver. */
4312         BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
4313
4314         /* Tell firmware we're alive. */
4315         BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
4316
4317 #ifdef DEVICE_POLLING
4318         /* Disable interrupts if we are polling. */
4319         if (ifp->if_capenable & IFCAP_POLLING) {
4320                 BGE_SETBIT(sc, BGE_PCI_MISC_CTL,
4321                     BGE_PCIMISCCTL_MASK_PCI_INTR);
4322                 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1);
4323         } else
4324 #endif
4325
4326         /* Enable host interrupts. */
4327         {
4328         BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA);
4329         BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR);
4330         bge_writembx(sc, BGE_MBX_IRQ0_LO, 0);
4331         }
4332
4333         bge_ifmedia_upd_locked(ifp);
4334
4335         ifp->if_drv_flags |= IFF_DRV_RUNNING;
4336         ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
4337
4338         callout_reset(&sc->bge_stat_ch, hz, bge_tick, sc);
4339 }
4340
4341 static void
4342 bge_init(void *xsc)
4343 {
4344         struct bge_softc *sc = xsc;
4345
4346         BGE_LOCK(sc);
4347         bge_init_locked(sc);
4348         BGE_UNLOCK(sc);
4349 }
4350
4351 /*
4352  * Set media options.
4353  */
4354 static int
4355 bge_ifmedia_upd(struct ifnet *ifp)
4356 {
4357         struct bge_softc *sc = ifp->if_softc;
4358         int res;
4359
4360         BGE_LOCK(sc);
4361         res = bge_ifmedia_upd_locked(ifp);
4362         BGE_UNLOCK(sc);
4363
4364         return (res);
4365 }
4366
4367 static int
4368 bge_ifmedia_upd_locked(struct ifnet *ifp)
4369 {
4370         struct bge_softc *sc = ifp->if_softc;
4371         struct mii_data *mii;
4372         struct mii_softc *miisc;
4373         struct ifmedia *ifm;
4374
4375         BGE_LOCK_ASSERT(sc);
4376
4377         ifm = &sc->bge_ifmedia;
4378
4379         /* If this is a 1000baseX NIC, enable the TBI port. */
4380         if (sc->bge_flags & BGE_FLAG_TBI) {
4381                 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
4382                         return (EINVAL);
4383                 switch(IFM_SUBTYPE(ifm->ifm_media)) {
4384                 case IFM_AUTO:
4385                         /*
4386                          * The BCM5704 ASIC appears to have a special
4387                          * mechanism for programming the autoneg
4388                          * advertisement registers in TBI mode.
4389                          */
4390                         if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
4391                                 uint32_t sgdig;
4392                                 sgdig = CSR_READ_4(sc, BGE_SGDIG_STS);
4393                                 if (sgdig & BGE_SGDIGSTS_DONE) {
4394                                         CSR_WRITE_4(sc, BGE_TX_TBI_AUTONEG, 0);
4395                                         sgdig = CSR_READ_4(sc, BGE_SGDIG_CFG);
4396                                         sgdig |= BGE_SGDIGCFG_AUTO |
4397                                             BGE_SGDIGCFG_PAUSE_CAP |
4398                                             BGE_SGDIGCFG_ASYM_PAUSE;
4399                                         CSR_WRITE_4(sc, BGE_SGDIG_CFG,
4400                                             sgdig | BGE_SGDIGCFG_SEND);
4401                                         DELAY(5);
4402                                         CSR_WRITE_4(sc, BGE_SGDIG_CFG, sgdig);
4403                                 }
4404                         }
4405                         break;
4406                 case IFM_1000_SX:
4407                         if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) {
4408                                 BGE_CLRBIT(sc, BGE_MAC_MODE,
4409                                     BGE_MACMODE_HALF_DUPLEX);
4410                         } else {
4411                                 BGE_SETBIT(sc, BGE_MAC_MODE,
4412                                     BGE_MACMODE_HALF_DUPLEX);
4413                         }
4414                         break;
4415                 default:
4416                         return (EINVAL);
4417                 }
4418                 return (0);
4419         }
4420
4421         sc->bge_link_evt++;
4422         mii = device_get_softc(sc->bge_miibus);
4423         if (mii->mii_instance)
4424                 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
4425                         mii_phy_reset(miisc);
4426         mii_mediachg(mii);
4427
4428         /*
4429          * Force an interrupt so that we will call bge_link_upd
4430          * if needed and clear any pending link state attention.
4431          * Without this we are not getting any further interrupts
4432          * for link state changes and thus will not UP the link and
4433          * not be able to send in bge_start_locked. The only
4434          * way to get things working was to receive a packet and
4435          * get an RX intr.
4436          * bge_tick should help for fiber cards and we might not
4437          * need to do this here if BGE_FLAG_TBI is set but as
4438          * we poll for fiber anyway it should not harm.
4439          */
4440         if (sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
4441             sc->bge_flags & BGE_FLAG_5788)
4442                 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET);
4443         else
4444                 BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW);
4445
4446         return (0);
4447 }
4448
4449 /*
4450  * Report current media status.
4451  */
4452 static void
4453 bge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
4454 {
4455         struct bge_softc *sc = ifp->if_softc;
4456         struct mii_data *mii;
4457
4458         BGE_LOCK(sc);
4459
4460         if (sc->bge_flags & BGE_FLAG_TBI) {
4461                 ifmr->ifm_status = IFM_AVALID;
4462                 ifmr->ifm_active = IFM_ETHER;
4463                 if (CSR_READ_4(sc, BGE_MAC_STS) &
4464                     BGE_MACSTAT_TBI_PCS_SYNCHED)
4465                         ifmr->ifm_status |= IFM_ACTIVE;
4466                 else {
4467                         ifmr->ifm_active |= IFM_NONE;
4468                         BGE_UNLOCK(sc);
4469                         return;
4470                 }
4471                 ifmr->ifm_active |= IFM_1000_SX;
4472                 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX)
4473                         ifmr->ifm_active |= IFM_HDX;
4474                 else
4475                         ifmr->ifm_active |= IFM_FDX;
4476                 BGE_UNLOCK(sc);
4477                 return;
4478         }
4479
4480         mii = device_get_softc(sc->bge_miibus);
4481         mii_pollstat(mii);
4482         ifmr->ifm_active = mii->mii_media_active;
4483         ifmr->ifm_status = mii->mii_media_status;
4484
4485         BGE_UNLOCK(sc);
4486 }
4487
4488 static int
4489 bge_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
4490 {
4491         struct bge_softc *sc = ifp->if_softc;
4492         struct ifreq *ifr = (struct ifreq *) data;
4493         struct mii_data *mii;
4494         int flags, mask, error = 0;
4495
4496         switch (command) {
4497         case SIOCSIFMTU:
4498                 if (ifr->ifr_mtu < ETHERMIN ||
4499                     ((BGE_IS_JUMBO_CAPABLE(sc)) &&
4500                     ifr->ifr_mtu > BGE_JUMBO_MTU) ||
4501                     ((!BGE_IS_JUMBO_CAPABLE(sc)) &&
4502                     ifr->ifr_mtu > ETHERMTU))
4503                         error = EINVAL;
4504                 else if (ifp->if_mtu != ifr->ifr_mtu) {
4505                         ifp->if_mtu = ifr->ifr_mtu;
4506                         ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
4507                         bge_init(sc);
4508                 }
4509                 break;
4510         case SIOCSIFFLAGS:
4511                 BGE_LOCK(sc);
4512                 if (ifp->if_flags & IFF_UP) {
4513                         /*
4514                          * If only the state of the PROMISC flag changed,
4515                          * then just use the 'set promisc mode' command
4516                          * instead of reinitializing the entire NIC. Doing
4517                          * a full re-init means reloading the firmware and
4518                          * waiting for it to start up, which may take a
4519                          * second or two.  Similarly for ALLMULTI.
4520                          */
4521                         if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
4522                                 flags = ifp->if_flags ^ sc->bge_if_flags;
4523                                 if (flags & IFF_PROMISC)
4524                                         bge_setpromisc(sc);
4525                                 if (flags & IFF_ALLMULTI)
4526                                         bge_setmulti(sc);
4527                         } else
4528                                 bge_init_locked(sc);
4529                 } else {
4530                         if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
4531                                 bge_stop(sc);
4532                         }
4533                 }
4534                 sc->bge_if_flags = ifp->if_flags;
4535                 BGE_UNLOCK(sc);
4536                 error = 0;
4537                 break;
4538         case SIOCADDMULTI:
4539         case SIOCDELMULTI:
4540                 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
4541                         BGE_LOCK(sc);
4542                         bge_setmulti(sc);
4543                         BGE_UNLOCK(sc);
4544                         error = 0;
4545                 }
4546                 break;
4547         case SIOCSIFMEDIA:
4548         case SIOCGIFMEDIA:
4549                 if (sc->bge_flags & BGE_FLAG_TBI) {
4550                         error = ifmedia_ioctl(ifp, ifr,
4551                             &sc->bge_ifmedia, command);
4552                 } else {
4553                         mii = device_get_softc(sc->bge_miibus);
4554                         error = ifmedia_ioctl(ifp, ifr,
4555                             &mii->mii_media, command);
4556                 }
4557                 break;
4558         case SIOCSIFCAP:
4559                 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
4560 #ifdef DEVICE_POLLING
4561                 if (mask & IFCAP_POLLING) {
4562                         if (ifr->ifr_reqcap & IFCAP_POLLING) {
4563                                 error = ether_poll_register(bge_poll, ifp);
4564                                 if (error)
4565                                         return (error);
4566                                 BGE_LOCK(sc);
4567                                 BGE_SETBIT(sc, BGE_PCI_MISC_CTL,
4568                                     BGE_PCIMISCCTL_MASK_PCI_INTR);
4569                                 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1);
4570                                 ifp->if_capenable |= IFCAP_POLLING;
4571                                 BGE_UNLOCK(sc);
4572                         } else {
4573                                 error = ether_poll_deregister(ifp);
4574                                 /* Enable interrupt even in error case */
4575                                 BGE_LOCK(sc);
4576                                 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL,
4577                                     BGE_PCIMISCCTL_MASK_PCI_INTR);
4578                                 bge_writembx(sc, BGE_MBX_IRQ0_LO, 0);
4579                                 ifp->if_capenable &= ~IFCAP_POLLING;
4580                                 BGE_UNLOCK(sc);
4581                         }
4582                 }
4583 #endif
4584                 if (mask & IFCAP_HWCSUM) {
4585                         ifp->if_capenable ^= IFCAP_HWCSUM;
4586                         if (IFCAP_HWCSUM & ifp->if_capenable &&
4587                             IFCAP_HWCSUM & ifp->if_capabilities)
4588                                 ifp->if_hwassist |= BGE_CSUM_FEATURES;
4589                         else
4590                                 ifp->if_hwassist &= ~BGE_CSUM_FEATURES;
4591                 }
4592
4593                 if ((mask & IFCAP_TSO4) != 0 &&
4594                     (ifp->if_capabilities & IFCAP_TSO4) != 0) {
4595                         ifp->if_capenable ^= IFCAP_TSO4;
4596                         if ((ifp->if_capenable & IFCAP_TSO4) != 0)
4597                                 ifp->if_hwassist |= CSUM_TSO;
4598                         else
4599                                 ifp->if_hwassist &= ~CSUM_TSO;
4600                 }
4601
4602                 if (mask & IFCAP_VLAN_MTU) {
4603                         ifp->if_capenable ^= IFCAP_VLAN_MTU;
4604                         ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
4605                         bge_init(sc);
4606                 }
4607
4608                 if ((mask & IFCAP_VLAN_HWTSO) != 0 &&
4609                     (ifp->if_capabilities & IFCAP_VLAN_HWTSO) != 0)
4610                         ifp->if_capenable ^= IFCAP_VLAN_HWTSO;
4611                 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 &&
4612                     (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) != 0) {
4613                         ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
4614                         if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) == 0)
4615                                 ifp->if_capenable &= ~IFCAP_VLAN_HWTSO;
4616                         BGE_LOCK(sc);
4617                         bge_setvlan(sc);
4618                         BGE_UNLOCK(sc);
4619                 }
4620 #ifdef VLAN_CAPABILITIES
4621                 VLAN_CAPABILITIES(ifp);
4622 #endif
4623                 break;
4624         default:
4625                 error = ether_ioctl(ifp, command, data);
4626                 break;
4627         }
4628
4629         return (error);
4630 }
4631
4632 static void
4633 bge_watchdog(struct bge_softc *sc)
4634 {
4635         struct ifnet *ifp;
4636
4637         BGE_LOCK_ASSERT(sc);
4638
4639         if (sc->bge_timer == 0 || --sc->bge_timer)
4640                 return;
4641
4642         ifp = sc->bge_ifp;
4643
4644         if_printf(ifp, "watchdog timeout -- resetting\n");
4645
4646         ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
4647         bge_init_locked(sc);
4648
4649         ifp->if_oerrors++;
4650 }
4651
4652 /*
4653  * Stop the adapter and free any mbufs allocated to the
4654  * RX and TX lists.
4655  */
4656 static void
4657 bge_stop(struct bge_softc *sc)
4658 {
4659         struct ifnet *ifp;
4660
4661         BGE_LOCK_ASSERT(sc);
4662
4663         ifp = sc->bge_ifp;
4664
4665         callout_stop(&sc->bge_stat_ch);
4666
4667         /* Disable host interrupts. */
4668         BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR);
4669         bge_writembx(sc, BGE_MBX_IRQ0_LO, 1);
4670
4671         /*
4672          * Tell firmware we're shutting down.
4673          */
4674         bge_stop_fw(sc);
4675         bge_sig_pre_reset(sc, BGE_RESET_STOP);
4676
4677         /*
4678          * Disable all of the receiver blocks.
4679          */
4680         BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
4681         BGE_CLRBIT(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
4682         BGE_CLRBIT(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
4683         if (!(BGE_IS_5705_PLUS(sc)))
4684                 BGE_CLRBIT(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
4685         BGE_CLRBIT(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE);
4686         BGE_CLRBIT(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
4687         BGE_CLRBIT(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE);
4688
4689         /*
4690          * Disable all of the transmit blocks.
4691          */
4692         BGE_CLRBIT(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
4693         BGE_CLRBIT(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
4694         BGE_CLRBIT(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
4695         BGE_CLRBIT(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE);
4696         BGE_CLRBIT(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE);
4697         if (!(BGE_IS_5705_PLUS(sc)))
4698                 BGE_CLRBIT(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
4699         BGE_CLRBIT(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
4700
4701         /*
4702          * Shut down all of the memory managers and related
4703          * state machines.
4704          */
4705         BGE_CLRBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE);
4706         BGE_CLRBIT(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE);
4707         if (!(BGE_IS_5705_PLUS(sc)))
4708                 BGE_CLRBIT(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
4709         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
4710         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
4711         if (!(BGE_IS_5705_PLUS(sc))) {
4712                 BGE_CLRBIT(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE);
4713                 BGE_CLRBIT(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
4714         }
4715
4716         bge_reset(sc);
4717         bge_sig_legacy(sc, BGE_RESET_STOP);
4718         bge_sig_post_reset(sc, BGE_RESET_STOP);
4719
4720         /*
4721          * Keep the ASF firmware running if up.
4722          */
4723         if (sc->bge_asf_mode & ASF_STACKUP)
4724                 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
4725         else
4726                 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
4727
4728         /* Free the RX lists. */
4729         bge_free_rx_ring_std(sc);
4730
4731         /* Free jumbo RX list. */
4732         if (BGE_IS_JUMBO_CAPABLE(sc))
4733                 bge_free_rx_ring_jumbo(sc);
4734
4735         /* Free TX buffers. */
4736         bge_free_tx_ring(sc);
4737
4738         sc->bge_tx_saved_considx = BGE_TXCONS_UNSET;
4739
4740         /* Clear MAC's link state (PHY may still have link UP). */
4741         if (bootverbose && sc->bge_link)
4742                 if_printf(sc->bge_ifp, "link DOWN\n");
4743         sc->bge_link = 0;
4744
4745         ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
4746 }
4747
4748 /*
4749  * Stop all chip I/O so that the kernel's probe routines don't
4750  * get confused by errant DMAs when rebooting.
4751  */
4752 static int
4753 bge_shutdown(device_t dev)
4754 {
4755         struct bge_softc *sc;
4756
4757         sc = device_get_softc(dev);
4758         BGE_LOCK(sc);
4759         bge_stop(sc);
4760         bge_reset(sc);
4761         BGE_UNLOCK(sc);
4762
4763         return (0);
4764 }
4765
4766 static int
4767 bge_suspend(device_t dev)
4768 {
4769         struct bge_softc *sc;
4770
4771         sc = device_get_softc(dev);
4772         BGE_LOCK(sc);
4773         bge_stop(sc);
4774         BGE_UNLOCK(sc);
4775
4776         return (0);
4777 }
4778
4779 static int
4780 bge_resume(device_t dev)
4781 {
4782         struct bge_softc *sc;
4783         struct ifnet *ifp;
4784
4785         sc = device_get_softc(dev);
4786         BGE_LOCK(sc);
4787         ifp = sc->bge_ifp;
4788         if (ifp->if_flags & IFF_UP) {
4789                 bge_init_locked(sc);
4790                 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
4791                         bge_start_locked(ifp);
4792         }
4793         BGE_UNLOCK(sc);
4794
4795         return (0);
4796 }
4797
4798 static void
4799 bge_link_upd(struct bge_softc *sc)
4800 {
4801         struct mii_data *mii;
4802         uint32_t link, status;
4803
4804         BGE_LOCK_ASSERT(sc);
4805
4806         /* Clear 'pending link event' flag. */
4807         sc->bge_link_evt = 0;
4808
4809         /*
4810          * Process link state changes.
4811          * Grrr. The link status word in the status block does
4812          * not work correctly on the BCM5700 rev AX and BX chips,
4813          * according to all available information. Hence, we have
4814          * to enable MII interrupts in order to properly obtain
4815          * async link changes. Unfortunately, this also means that
4816          * we have to read the MAC status register to detect link
4817          * changes, thereby adding an additional register access to
4818          * the interrupt handler.
4819          *
4820          * XXX: perhaps link state detection procedure used for
4821          * BGE_CHIPID_BCM5700_B2 can be used for others BCM5700 revisions.
4822          */
4823
4824         if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
4825             sc->bge_chipid != BGE_CHIPID_BCM5700_B2) {
4826                 status = CSR_READ_4(sc, BGE_MAC_STS);
4827                 if (status & BGE_MACSTAT_MI_INTERRUPT) {
4828                         mii = device_get_softc(sc->bge_miibus);
4829                         mii_pollstat(mii);
4830                         if (!sc->bge_link &&
4831                             mii->mii_media_status & IFM_ACTIVE &&
4832                             IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
4833                                 sc->bge_link++;
4834                                 if (bootverbose)
4835                                         if_printf(sc->bge_ifp, "link UP\n");
4836                         } else if (sc->bge_link &&
4837                             (!(mii->mii_media_status & IFM_ACTIVE) ||
4838                             IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) {
4839                                 sc->bge_link = 0;
4840                                 if (bootverbose)
4841                                         if_printf(sc->bge_ifp, "link DOWN\n");
4842                         }
4843
4844                         /* Clear the interrupt. */
4845                         CSR_WRITE_4(sc, BGE_MAC_EVT_ENB,
4846                             BGE_EVTENB_MI_INTERRUPT);
4847                         bge_miibus_readreg(sc->bge_dev, 1, BRGPHY_MII_ISR);
4848                         bge_miibus_writereg(sc->bge_dev, 1, BRGPHY_MII_IMR,
4849                             BRGPHY_INTRS);
4850                 }
4851                 return;
4852         }
4853
4854         if (sc->bge_flags & BGE_FLAG_TBI) {
4855                 status = CSR_READ_4(sc, BGE_MAC_STS);
4856                 if (status & BGE_MACSTAT_TBI_PCS_SYNCHED) {
4857                         if (!sc->bge_link) {
4858                                 sc->bge_link++;
4859                                 if (sc->bge_asicrev == BGE_ASICREV_BCM5704)
4860                                         BGE_CLRBIT(sc, BGE_MAC_MODE,
4861                                             BGE_MACMODE_TBI_SEND_CFGS);
4862                                 CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF);
4863                                 if (bootverbose)
4864                                         if_printf(sc->bge_ifp, "link UP\n");
4865                                 if_link_state_change(sc->bge_ifp,
4866                                     LINK_STATE_UP);
4867                         }
4868                 } else if (sc->bge_link) {
4869                         sc->bge_link = 0;
4870                         if (bootverbose)
4871                                 if_printf(sc->bge_ifp, "link DOWN\n");
4872                         if_link_state_change(sc->bge_ifp, LINK_STATE_DOWN);
4873                 }
4874         } else if (CSR_READ_4(sc, BGE_MI_MODE) & BGE_MIMODE_AUTOPOLL) {
4875                 /*
4876                  * Some broken BCM chips have BGE_STATFLAG_LINKSTATE_CHANGED bit
4877                  * in status word always set. Workaround this bug by reading
4878                  * PHY link status directly.
4879                  */
4880                 link = (CSR_READ_4(sc, BGE_MI_STS) & BGE_MISTS_LINK) ? 1 : 0;
4881
4882                 if (link != sc->bge_link ||
4883                     sc->bge_asicrev == BGE_ASICREV_BCM5700) {
4884                         mii = device_get_softc(sc->bge_miibus);
4885                         mii_pollstat(mii);
4886                         if (!sc->bge_link &&
4887                             mii->mii_media_status & IFM_ACTIVE &&
4888                             IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
4889                                 sc->bge_link++;
4890                                 if (bootverbose)
4891                                         if_printf(sc->bge_ifp, "link UP\n");
4892                         } else if (sc->bge_link &&
4893                             (!(mii->mii_media_status & IFM_ACTIVE) ||
4894                             IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) {
4895                                 sc->bge_link = 0;
4896                                 if (bootverbose)
4897                                         if_printf(sc->bge_ifp, "link DOWN\n");
4898                         }
4899                 }
4900         } else {
4901                 /*
4902                  * Discard link events for MII/GMII controllers
4903                  * if MI auto-polling is disabled.
4904                  */
4905         }
4906
4907         /* Clear the attention. */
4908         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
4909             BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
4910             BGE_MACSTAT_LINK_CHANGED);
4911 }
4912
4913 #define BGE_SYSCTL_STAT(sc, ctx, desc, parent, node, oid) \
4914         SYSCTL_ADD_PROC(ctx, parent, OID_AUTO, oid, CTLTYPE_UINT|CTLFLAG_RD, \
4915             sc, offsetof(struct bge_stats, node), bge_sysctl_stats, "IU", \
4916             desc)
4917
4918 static void
4919 bge_add_sysctls(struct bge_softc *sc)
4920 {
4921         struct sysctl_ctx_list *ctx;
4922         struct sysctl_oid_list *children, *schildren;
4923         struct sysctl_oid *tree;
4924
4925         ctx = device_get_sysctl_ctx(sc->bge_dev);
4926         children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->bge_dev));
4927
4928 #ifdef BGE_REGISTER_DEBUG
4929         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "debug_info",
4930             CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_debug_info, "I",
4931             "Debug Information");
4932
4933         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "reg_read",
4934             CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_reg_read, "I",
4935             "Register Read");
4936
4937         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "mem_read",
4938             CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_mem_read, "I",
4939             "Memory Read");
4940
4941 #endif
4942
4943         /*
4944          * A common design characteristic for many Broadcom client controllers
4945          * is that they only support a single outstanding DMA read operation
4946          * on the PCIe bus. This means that it will take twice as long to fetch
4947          * a TX frame that is split into header and payload buffers as it does
4948          * to fetch a single, contiguous TX frame (2 reads vs. 1 read). For
4949          * these controllers, coalescing buffers to reduce the number of memory
4950          * reads is effective way to get maximum performance(about 940Mbps).
4951          * Without collapsing TX buffers the maximum TCP bulk transfer
4952          * performance is about 850Mbps. However forcing coalescing mbufs
4953          * consumes a lot of CPU cycles, so leave it off by default.
4954          */
4955         SYSCTL_ADD_INT(ctx, children, OID_AUTO, "forced_collapse",
4956             CTLFLAG_RW, &sc->bge_forced_collapse, 0,
4957             "Number of fragmented TX buffers of a frame allowed before "
4958             "forced collapsing");
4959         resource_int_value(device_get_name(sc->bge_dev),
4960             device_get_unit(sc->bge_dev), "forced_collapse",
4961             &sc->bge_forced_collapse);
4962
4963         if (BGE_IS_5705_PLUS(sc))
4964                 return;
4965
4966         tree = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "stats", CTLFLAG_RD,
4967             NULL, "BGE Statistics");
4968         schildren = children = SYSCTL_CHILDREN(tree);
4969         BGE_SYSCTL_STAT(sc, ctx, "Frames Dropped Due To Filters",
4970             children, COSFramesDroppedDueToFilters,
4971             "FramesDroppedDueToFilters");
4972         BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Write Queue Full",
4973             children, nicDmaWriteQueueFull, "DmaWriteQueueFull");
4974         BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Write High Priority Queue Full",
4975             children, nicDmaWriteHighPriQueueFull, "DmaWriteHighPriQueueFull");
4976         BGE_SYSCTL_STAT(sc, ctx, "NIC No More RX Buffer Descriptors",
4977             children, nicNoMoreRxBDs, "NoMoreRxBDs");
4978         BGE_SYSCTL_STAT(sc, ctx, "Discarded Input Frames",
4979             children, ifInDiscards, "InputDiscards");
4980         BGE_SYSCTL_STAT(sc, ctx, "Input Errors",
4981             children, ifInErrors, "InputErrors");
4982         BGE_SYSCTL_STAT(sc, ctx, "NIC Recv Threshold Hit",
4983             children, nicRecvThresholdHit, "RecvThresholdHit");
4984         BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Read Queue Full",
4985             children, nicDmaReadQueueFull, "DmaReadQueueFull");
4986         BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Read High Priority Queue Full",
4987             children, nicDmaReadHighPriQueueFull, "DmaReadHighPriQueueFull");
4988         BGE_SYSCTL_STAT(sc, ctx, "NIC Send Data Complete Queue Full",
4989             children, nicSendDataCompQueueFull, "SendDataCompQueueFull");
4990         BGE_SYSCTL_STAT(sc, ctx, "NIC Ring Set Send Producer Index",
4991             children, nicRingSetSendProdIndex, "RingSetSendProdIndex");
4992         BGE_SYSCTL_STAT(sc, ctx, "NIC Ring Status Update",
4993             children, nicRingStatusUpdate, "RingStatusUpdate");
4994         BGE_SYSCTL_STAT(sc, ctx, "NIC Interrupts",
4995             children, nicInterrupts, "Interrupts");
4996         BGE_SYSCTL_STAT(sc, ctx, "NIC Avoided Interrupts",
4997             children, nicAvoidedInterrupts, "AvoidedInterrupts");
4998         BGE_SYSCTL_STAT(sc, ctx, "NIC Send Threshold Hit",
4999             children, nicSendThresholdHit, "SendThresholdHit");
5000
5001         tree = SYSCTL_ADD_NODE(ctx, schildren, OID_AUTO, "rx", CTLFLAG_RD,
5002             NULL, "BGE RX Statistics");
5003         children = SYSCTL_CHILDREN(tree);
5004         BGE_SYSCTL_STAT(sc, ctx, "Inbound Octets",
5005             children, rxstats.ifHCInOctets, "Octets");
5006         BGE_SYSCTL_STAT(sc, ctx, "Fragments",
5007             children, rxstats.etherStatsFragments, "Fragments");
5008         BGE_SYSCTL_STAT(sc, ctx, "Inbound Unicast Packets",
5009             children, rxstats.ifHCInUcastPkts, "UcastPkts");
5010         BGE_SYSCTL_STAT(sc, ctx, "Inbound Multicast Packets",
5011             children, rxstats.ifHCInMulticastPkts, "MulticastPkts");
5012         BGE_SYSCTL_STAT(sc, ctx, "FCS Errors",
5013             children, rxstats.dot3StatsFCSErrors, "FCSErrors");
5014         BGE_SYSCTL_STAT(sc, ctx, "Alignment Errors",
5015             children, rxstats.dot3StatsAlignmentErrors, "AlignmentErrors");
5016         BGE_SYSCTL_STAT(sc, ctx, "XON Pause Frames Received",
5017             children, rxstats.xonPauseFramesReceived, "xonPauseFramesReceived");
5018         BGE_SYSCTL_STAT(sc, ctx, "XOFF Pause Frames Received",
5019             children, rxstats.xoffPauseFramesReceived,
5020             "xoffPauseFramesReceived");
5021         BGE_SYSCTL_STAT(sc, ctx, "MAC Control Frames Received",
5022             children, rxstats.macControlFramesReceived,
5023             "ControlFramesReceived");
5024         BGE_SYSCTL_STAT(sc, ctx, "XOFF State Entered",
5025             children, rxstats.xoffStateEntered, "xoffStateEntered");
5026         BGE_SYSCTL_STAT(sc, ctx, "Frames Too Long",
5027             children, rxstats.dot3StatsFramesTooLong, "FramesTooLong");
5028         BGE_SYSCTL_STAT(sc, ctx, "Jabbers",
5029             children, rxstats.etherStatsJabbers, "Jabbers");
5030         BGE_SYSCTL_STAT(sc, ctx, "Undersized Packets",
5031             children, rxstats.etherStatsUndersizePkts, "UndersizePkts");
5032         BGE_SYSCTL_STAT(sc, ctx, "Inbound Range Length Errors",
5033             children, rxstats.inRangeLengthError, "inRangeLengthError");
5034         BGE_SYSCTL_STAT(sc, ctx, "Outbound Range Length Errors",
5035             children, rxstats.outRangeLengthError, "outRangeLengthError");
5036
5037         tree = SYSCTL_ADD_NODE(ctx, schildren, OID_AUTO, "tx", CTLFLAG_RD,
5038             NULL, "BGE TX Statistics");
5039         children = SYSCTL_CHILDREN(tree);
5040         BGE_SYSCTL_STAT(sc, ctx, "Outbound Octets",
5041             children, txstats.ifHCOutOctets, "Octets");
5042         BGE_SYSCTL_STAT(sc, ctx, "TX Collisions",
5043             children, txstats.etherStatsCollisions, "Collisions");
5044         BGE_SYSCTL_STAT(sc, ctx, "XON Sent",
5045             children, txstats.outXonSent, "XonSent");
5046         BGE_SYSCTL_STAT(sc, ctx, "XOFF Sent",
5047             children, txstats.outXoffSent, "XoffSent");
5048         BGE_SYSCTL_STAT(sc, ctx, "Flow Control Done",
5049             children, txstats.flowControlDone, "flowControlDone");
5050         BGE_SYSCTL_STAT(sc, ctx, "Internal MAC TX errors",
5051             children, txstats.dot3StatsInternalMacTransmitErrors,
5052             "InternalMacTransmitErrors");
5053         BGE_SYSCTL_STAT(sc, ctx, "Single Collision Frames",
5054             children, txstats.dot3StatsSingleCollisionFrames,
5055             "SingleCollisionFrames");
5056         BGE_SYSCTL_STAT(sc, ctx, "Multiple Collision Frames",
5057             children, txstats.dot3StatsMultipleCollisionFrames,
5058             "MultipleCollisionFrames");
5059         BGE_SYSCTL_STAT(sc, ctx, "Deferred Transmissions",
5060             children, txstats.dot3StatsDeferredTransmissions,
5061             "DeferredTransmissions");
5062         BGE_SYSCTL_STAT(sc, ctx, "Excessive Collisions",
5063             children, txstats.dot3StatsExcessiveCollisions,
5064             "ExcessiveCollisions");
5065         BGE_SYSCTL_STAT(sc, ctx, "Late Collisions",
5066             children, txstats.dot3StatsLateCollisions,
5067             "LateCollisions");
5068         BGE_SYSCTL_STAT(sc, ctx, "Outbound Unicast Packets",
5069             children, txstats.ifHCOutUcastPkts, "UcastPkts");
5070         BGE_SYSCTL_STAT(sc, ctx, "Outbound Multicast Packets",
5071             children, txstats.ifHCOutMulticastPkts, "MulticastPkts");
5072         BGE_SYSCTL_STAT(sc, ctx, "Outbound Broadcast Packets",
5073             children, txstats.ifHCOutBroadcastPkts, "BroadcastPkts");
5074         BGE_SYSCTL_STAT(sc, ctx, "Carrier Sense Errors",
5075             children, txstats.dot3StatsCarrierSenseErrors,
5076             "CarrierSenseErrors");
5077         BGE_SYSCTL_STAT(sc, ctx, "Outbound Discards",
5078             children, txstats.ifOutDiscards, "Discards");
5079         BGE_SYSCTL_STAT(sc, ctx, "Outbound Errors",
5080             children, txstats.ifOutErrors, "Errors");
5081 }
5082
5083 static int
5084 bge_sysctl_stats(SYSCTL_HANDLER_ARGS)
5085 {
5086         struct bge_softc *sc;
5087         uint32_t result;
5088         int offset;
5089
5090         sc = (struct bge_softc *)arg1;
5091         offset = arg2;
5092         result = CSR_READ_4(sc, BGE_MEMWIN_START + BGE_STATS_BLOCK + offset +
5093             offsetof(bge_hostaddr, bge_addr_lo));
5094         return (sysctl_handle_int(oidp, &result, 0, req));
5095 }
5096
5097 #ifdef BGE_REGISTER_DEBUG
5098 static int
5099 bge_sysctl_debug_info(SYSCTL_HANDLER_ARGS)
5100 {
5101         struct bge_softc *sc;
5102         uint16_t *sbdata;
5103         int error;
5104         int result;
5105         int i, j;
5106
5107         result = -1;
5108         error = sysctl_handle_int(oidp, &result, 0, req);
5109         if (error || (req->newptr == NULL))
5110                 return (error);
5111
5112         if (result == 1) {
5113                 sc = (struct bge_softc *)arg1;
5114
5115                 sbdata = (uint16_t *)sc->bge_ldata.bge_status_block;
5116                 printf("Status Block:\n");
5117                 for (i = 0x0; i < (BGE_STATUS_BLK_SZ / 4); ) {
5118                         printf("%06x:", i);
5119                         for (j = 0; j < 8; j++) {
5120                                 printf(" %04x", sbdata[i]);
5121                                 i += 4;
5122                         }
5123                         printf("\n");
5124                 }
5125
5126                 printf("Registers:\n");
5127                 for (i = 0x800; i < 0xA00; ) {
5128                         printf("%06x:", i);
5129                         for (j = 0; j < 8; j++) {
5130                                 printf(" %08x", CSR_READ_4(sc, i));
5131                                 i += 4;
5132                         }
5133                         printf("\n");
5134                 }
5135
5136                 printf("Hardware Flags:\n");
5137                 if (BGE_IS_5755_PLUS(sc))
5138                         printf(" - 5755 Plus\n");
5139                 if (BGE_IS_575X_PLUS(sc))
5140                         printf(" - 575X Plus\n");
5141                 if (BGE_IS_5705_PLUS(sc))
5142                         printf(" - 5705 Plus\n");
5143                 if (BGE_IS_5714_FAMILY(sc))
5144                         printf(" - 5714 Family\n");
5145                 if (BGE_IS_5700_FAMILY(sc))
5146                         printf(" - 5700 Family\n");
5147                 if (sc->bge_flags & BGE_FLAG_JUMBO)
5148                         printf(" - Supports Jumbo Frames\n");
5149                 if (sc->bge_flags & BGE_FLAG_PCIX)
5150                         printf(" - PCI-X Bus\n");
5151                 if (sc->bge_flags & BGE_FLAG_PCIE)
5152                         printf(" - PCI Express Bus\n");
5153                 if (sc->bge_flags & BGE_FLAG_NO_3LED)
5154                         printf(" - No 3 LEDs\n");
5155                 if (sc->bge_flags & BGE_FLAG_RX_ALIGNBUG)
5156                         printf(" - RX Alignment Bug\n");
5157         }
5158
5159         return (error);
5160 }
5161
5162 static int
5163 bge_sysctl_reg_read(SYSCTL_HANDLER_ARGS)
5164 {
5165         struct bge_softc *sc;
5166         int error;
5167         uint16_t result;
5168         uint32_t val;
5169
5170         result = -1;
5171         error = sysctl_handle_int(oidp, &result, 0, req);
5172         if (error || (req->newptr == NULL))
5173                 return (error);
5174
5175         if (result < 0x8000) {
5176                 sc = (struct bge_softc *)arg1;
5177                 val = CSR_READ_4(sc, result);
5178                 printf("reg 0x%06X = 0x%08X\n", result, val);
5179         }
5180
5181         return (error);
5182 }
5183
5184 static int
5185 bge_sysctl_mem_read(SYSCTL_HANDLER_ARGS)
5186 {
5187         struct bge_softc *sc;
5188         int error;
5189         uint16_t result;
5190         uint32_t val;
5191
5192         result = -1;
5193         error = sysctl_handle_int(oidp, &result, 0, req);
5194         if (error || (req->newptr == NULL))
5195                 return (error);
5196
5197         if (result < 0x8000) {
5198                 sc = (struct bge_softc *)arg1;
5199                 val = bge_readmem_ind(sc, result);
5200                 printf("mem 0x%06X = 0x%08X\n", result, val);
5201         }
5202
5203         return (error);
5204 }
5205 #endif
5206
5207 static int
5208 bge_get_eaddr_fw(struct bge_softc *sc, uint8_t ether_addr[])
5209 {
5210
5211         if (sc->bge_flags & BGE_FLAG_EADDR)
5212                 return (1);
5213
5214 #ifdef __sparc64__
5215         OF_getetheraddr(sc->bge_dev, ether_addr);
5216         return (0);
5217 #endif
5218         return (1);
5219 }
5220
5221 static int
5222 bge_get_eaddr_mem(struct bge_softc *sc, uint8_t ether_addr[])
5223 {
5224         uint32_t mac_addr;
5225
5226         mac_addr = bge_readmem_ind(sc, 0x0c14);
5227         if ((mac_addr >> 16) == 0x484b) {
5228                 ether_addr[0] = (uint8_t)(mac_addr >> 8);
5229                 ether_addr[1] = (uint8_t)mac_addr;
5230                 mac_addr = bge_readmem_ind(sc, 0x0c18);
5231                 ether_addr[2] = (uint8_t)(mac_addr >> 24);
5232                 ether_addr[3] = (uint8_t)(mac_addr >> 16);
5233                 ether_addr[4] = (uint8_t)(mac_addr >> 8);
5234                 ether_addr[5] = (uint8_t)mac_addr;
5235                 return (0);
5236         }
5237         return (1);
5238 }
5239
5240 static int
5241 bge_get_eaddr_nvram(struct bge_softc *sc, uint8_t ether_addr[])
5242 {
5243         int mac_offset = BGE_EE_MAC_OFFSET;
5244
5245         if (sc->bge_asicrev == BGE_ASICREV_BCM5906)
5246                 mac_offset = BGE_EE_MAC_OFFSET_5906;
5247
5248         return (bge_read_nvram(sc, ether_addr, mac_offset + 2,
5249             ETHER_ADDR_LEN));
5250 }
5251
5252 static int
5253 bge_get_eaddr_eeprom(struct bge_softc *sc, uint8_t ether_addr[])
5254 {
5255
5256         if (sc->bge_asicrev == BGE_ASICREV_BCM5906)
5257                 return (1);
5258
5259         return (bge_read_eeprom(sc, ether_addr, BGE_EE_MAC_OFFSET + 2,
5260            ETHER_ADDR_LEN));
5261 }
5262
5263 static int
5264 bge_get_eaddr(struct bge_softc *sc, uint8_t eaddr[])
5265 {
5266         static const bge_eaddr_fcn_t bge_eaddr_funcs[] = {
5267                 /* NOTE: Order is critical */
5268                 bge_get_eaddr_fw,
5269                 bge_get_eaddr_mem,
5270                 bge_get_eaddr_nvram,
5271                 bge_get_eaddr_eeprom,
5272                 NULL
5273         };
5274         const bge_eaddr_fcn_t *func;
5275
5276         for (func = bge_eaddr_funcs; *func != NULL; ++func) {
5277                 if ((*func)(sc, eaddr) == 0)
5278                         break;
5279         }
5280         return (*func == NULL ? ENXIO : 0);
5281 }