1 /**************************************************************************
3 Copyright (c) 2007, Chelsio Inc.
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Neither the name of the Chelsio Corporation nor the names of its
13 contributors may be used to endorse or promote products derived from
14 this software without specific prior written permission.
16 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
17 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
20 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
21 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
23 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
24 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
25 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
26 POSSIBILITY OF SUCH DAMAGE.
31 ***************************************************************************/
33 #include <sys/param.h>
34 #include <sys/systm.h>
35 #include <sys/ctype.h>
36 #include <sys/endian.h>
40 #include <sys/mutex.h>
42 #include <dev/mii/mii.h>
44 #ifndef _CXGB_OSDEP_H_
45 #define _CXGB_OSDEP_H_
47 typedef struct adapter adapter_t;
48 typedef struct port_info pinfo_t;
52 TP_TMR_RES = 200, /* TP timer resolution in usec */
53 MAX_NPORTS = 4, /* max # of ports */
54 TP_SRAM_OFFSET = 4096, /* TP SRAM content offset in eeprom */
55 TP_SRAM_LEN = 2112, /* TP SRAM content offset in eeprom */
64 #define PANIC_IF(exp) do { \
66 panic("BUG: %s", #exp); \
70 #define m_get_priority(m) ((uintptr_t)(m)->m_pkthdr.rcvif)
71 #define m_set_priority(m, pri) ((m)->m_pkthdr.rcvif = (struct ifnet *)((uintptr_t)pri))
72 #define m_set_sgl(m, sgl) ((m)->m_pkthdr.header = (sgl))
73 #define m_get_sgl(m) ((bus_dma_segment_t *)(m)->m_pkthdr.header)
74 #define m_set_sgllen(m, len) ((m)->m_pkthdr.ether_vtag = len)
75 #define m_get_sgllen(m) ((m)->m_pkthdr.ether_vtag)
80 #define m_set_toep(m, a) ((m)->m_pkthdr.header = (a))
81 #define m_get_toep(m) ((m)->m_pkthdr.header)
82 #define m_set_handler(m, handler) ((m)->m_pkthdr.header = (handler))
84 #define m_set_socket(m, a) ((m)->m_pkthdr.header = (a))
85 #define m_get_socket(m) ((m)->m_pkthdr.header)
87 #define KTR_CXGB KTR_SPARE2
89 #define MT_DONTFREE 128
91 #if __FreeBSD_version < 800054
92 #if defined (__GNUC__)
93 #if #cpu(i386) || defined __i386 || defined i386 || defined __i386__ || #cpu(x86_64) || defined __x86_64__
94 #define mb() __asm__ __volatile__ ("mfence;": : :"memory")
95 #define wmb() __asm__ __volatile__ ("sfence;": : :"memory")
96 #define rmb() __asm__ __volatile__ ("lfence;": : :"memory")
97 #elif #cpu(sparc64) || defined sparc64 || defined __sparcv9
98 #define mb() __asm__ __volatile__ ("membar #MemIssue": : :"memory")
101 #elif #cpu(sparc) || defined sparc || defined __sparc__
102 #define mb() __asm__ __volatile__ ("stbar;": : :"memory")
108 #define mb() /* XXX just to make this compile */
111 #error "unknown compiler"
115 #define __read_mostly __attribute__((__section__(".data.read_mostly")))
118 * Workaround for weird Chelsio issue
120 #if __FreeBSD_version > 700029
121 #define PRIV_SUPPORTED
124 #define CXGB_TX_CLEANUP_THRESHOLD 32
128 #define DPRINTF printf
133 #define TX_MAX_SIZE (1 << 16) /* 64KB */
134 #define TX_MAX_SEGS 36 /* maximum supported by card */
136 #define TX_MAX_DESC 4 /* max descriptors per packet */
139 #define TX_START_MAX_DESC (TX_MAX_DESC << 2) /* maximum number of descriptors
140 * call to start used per */
142 #define TX_CLEAN_MAX_DESC (TX_MAX_DESC << 4) /* maximum tx descriptors
143 * to clean per iteration */
144 #define TX_WR_SIZE_MAX 11*1024 /* the maximum total size of packets aggregated into a single
147 #define TX_WR_COUNT_MAX 7 /* the maximum total number of packets that can be
148 * aggregated into a single TX WR
150 #if defined(__i386__) || defined(__amd64__)
153 void prefetch(void *x)
155 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x));
158 #define smp_mb() mb()
160 #define L1_CACHE_BYTES 128
161 extern void kdb_backtrace(void);
163 #define WARN_ON(condition) do { \
164 if (__predict_false((condition)!=0)) { \
165 log(LOG_WARNING, "BUG: warning at %s:%d/%s()\n", __FILE__, __LINE__, __FUNCTION__); \
173 #define L1_CACHE_BYTES 32
176 #define DBG_RX (1 << 0)
177 static const int debug_flags = DBG_RX;
180 #define DBG(flag, msg) do { \
181 if ((flag & debug_flags)) \
188 #include <sys/syslog.h>
190 #define promisc_rx_mode(rm) ((rm)->port->ifp->if_flags & IFF_PROMISC)
191 #define allmulti_rx_mode(rm) ((rm)->port->ifp->if_flags & IFF_ALLMULTI)
193 #define CH_ERR(adap, fmt, ...) log(LOG_ERR, fmt, ##__VA_ARGS__)
194 #define CH_WARN(adap, fmt, ...) log(LOG_WARNING, fmt, ##__VA_ARGS__)
195 #define CH_ALERT(adap, fmt, ...) log(LOG_ALERT, fmt, ##__VA_ARGS__)
197 #define t3_os_sleep(x) DELAY((x) * 1000)
199 #define test_and_clear_bit(bit, p) atomic_cmpset_int((p), ((*(p)) | (1<<bit)), ((*(p)) & ~(1<<bit)))
201 #define max_t(type, a, b) (type)max((a), (b))
202 #define net_device ifnet
203 #define cpu_to_be32 htobe32
205 /* Standard PHY definitions */
206 #define BMCR_LOOPBACK BMCR_LOOP
207 #define BMCR_ISOLATE BMCR_ISO
208 #define BMCR_ANENABLE BMCR_AUTOEN
209 #define BMCR_SPEED1000 BMCR_SPEED1
210 #define BMCR_SPEED100 BMCR_SPEED0
211 #define BMCR_ANRESTART BMCR_STARTNEG
212 #define BMCR_FULLDPLX BMCR_FDX
213 #define BMSR_LSTATUS BMSR_LINK
214 #define BMSR_ANEGCOMPLETE BMSR_ACOMP
216 #define MII_LPA MII_ANLPAR
217 #define MII_ADVERTISE MII_ANAR
218 #define MII_CTRL1000 MII_100T2CR
220 #define ADVERTISE_PAUSE_CAP ANAR_FC
221 #define ADVERTISE_PAUSE_ASYM 0x800
222 #define ADVERTISE_PAUSE ANAR_FC
223 #define ADVERTISE_1000HALF 0x100
224 #define ADVERTISE_1000FULL 0x200
225 #define ADVERTISE_10FULL ANAR_10_FD
226 #define ADVERTISE_10HALF ANAR_10
227 #define ADVERTISE_100FULL ANAR_TX_FD
228 #define ADVERTISE_100HALF ANAR_TX
231 #define ADVERTISE_1000XHALF ANAR_X_HD
232 #define ADVERTISE_1000XFULL ANAR_X_FD
233 #define ADVERTISE_1000XPSE_ASYM ANAR_X_PAUSE_ASYM
234 #define ADVERTISE_1000XPAUSE ANAR_X_PAUSE_SYM
236 #define ADVERTISE_CSMA ANAR_CSMA
237 #define ADVERTISE_NPAGE ANAR_NP
240 /* Standard PCI Extended Capabilities definitions */
241 #define PCI_CAP_ID_VPD PCIY_VPD
242 #define PCI_VPD_ADDR PCIR_VPD_ADDR
243 #define PCI_VPD_ADDR_F 0x8000
244 #define PCI_VPD_DATA PCIR_VPD_DATA
246 #define PCI_CAP_ID_EXP PCIY_EXPRESS
247 #define PCI_EXP_DEVCTL PCIR_EXPRESS_DEVICE_CTL
248 #define PCI_EXP_DEVCTL_PAYLOAD PCIM_EXP_CTL_MAX_PAYLOAD
249 #define PCI_EXP_DEVCTL_READRQ PCIM_EXP_CTL_MAX_READ_REQUEST
250 #define PCI_EXP_LNKCTL PCIR_EXPRESS_LINK_CTL
251 #define PCI_EXP_LNKSTA PCIR_EXPRESS_LINK_STA
254 * Linux compatibility macros
257 /* Some simple translations */
259 #define udelay(x) DELAY(x)
260 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
261 #define le32_to_cpu(x) le32toh(x)
262 #define le16_to_cpu(x) le16toh(x)
263 #define cpu_to_le32(x) htole32(x)
264 #define swab32(x) bswap32(x)
265 #define simple_strtoul strtoul
268 #ifndef LINUX_TYPES_DEFINED
270 typedef uint16_t u16;
271 typedef uint32_t u32;
272 typedef uint64_t u64;
274 typedef uint8_t __u8;
275 typedef uint16_t __u16;
276 typedef uint32_t __u32;
277 typedef uint8_t __be8;
278 typedef uint16_t __be16;
279 typedef uint32_t __be32;
280 typedef uint64_t __be64;
284 #if BYTE_ORDER == BIG_ENDIAN
285 #define __BIG_ENDIAN_BITFIELD
286 #elif BYTE_ORDER == LITTLE_ENDIAN
287 #define __LITTLE_ENDIAN_BITFIELD
289 #error "Must set BYTE_ORDER"
292 /* Indicates what features are supported by the interface. */
293 #define SUPPORTED_10baseT_Half (1 << 0)
294 #define SUPPORTED_10baseT_Full (1 << 1)
295 #define SUPPORTED_100baseT_Half (1 << 2)
296 #define SUPPORTED_100baseT_Full (1 << 3)
297 #define SUPPORTED_1000baseT_Half (1 << 4)
298 #define SUPPORTED_1000baseT_Full (1 << 5)
299 #define SUPPORTED_Autoneg (1 << 6)
300 #define SUPPORTED_TP (1 << 7)
301 #define SUPPORTED_AUI (1 << 8)
302 #define SUPPORTED_MII (1 << 9)
303 #define SUPPORTED_FIBRE (1 << 10)
304 #define SUPPORTED_BNC (1 << 11)
305 #define SUPPORTED_10000baseT_Full (1 << 12)
306 #define SUPPORTED_Pause (1 << 13)
307 #define SUPPORTED_Asym_Pause (1 << 14)
309 /* Indicates what features are advertised by the interface. */
310 #define ADVERTISED_10baseT_Half (1 << 0)
311 #define ADVERTISED_10baseT_Full (1 << 1)
312 #define ADVERTISED_100baseT_Half (1 << 2)
313 #define ADVERTISED_100baseT_Full (1 << 3)
314 #define ADVERTISED_1000baseT_Half (1 << 4)
315 #define ADVERTISED_1000baseT_Full (1 << 5)
316 #define ADVERTISED_Autoneg (1 << 6)
317 #define ADVERTISED_TP (1 << 7)
318 #define ADVERTISED_AUI (1 << 8)
319 #define ADVERTISED_MII (1 << 9)
320 #define ADVERTISED_FIBRE (1 << 10)
321 #define ADVERTISED_BNC (1 << 11)
322 #define ADVERTISED_10000baseT_Full (1 << 12)
323 #define ADVERTISED_Pause (1 << 13)
324 #define ADVERTISED_Asym_Pause (1 << 14)
326 /* Enable or disable autonegotiation. If this is set to enable,
327 * the forced link modes above are completely ignored.
329 #define AUTONEG_DISABLE 0x00
330 #define AUTONEG_ENABLE 0x01
333 #define SPEED_100 100
334 #define SPEED_1000 1000
335 #define SPEED_10000 10000
336 #define DUPLEX_HALF 0
337 #define DUPLEX_FULL 1