2 * Copyright (c) 1997, 1998, 1999
3 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
33 #include <sys/cdefs.h>
34 __FBSDID("$FreeBSD$");
37 * DEC "tulip" clone ethernet driver. Supports the DEC/Intel 21143
38 * series chips and several workalikes including the following:
40 * Macronix 98713/98715/98725/98727/98732 PMAC (www.macronix.com)
41 * Macronix/Lite-On 82c115 PNIC II (www.macronix.com)
42 * Lite-On 82c168/82c169 PNIC (www.litecom.com)
43 * ASIX Electronics AX88140A (www.asix.com.tw)
44 * ASIX Electronics AX88141 (www.asix.com.tw)
45 * ADMtek AL981 (www.admtek.com.tw)
46 * ADMtek AN985 (www.admtek.com.tw)
47 * Netgear FA511 (www.netgear.com) Appears to be rebadged ADMTek AN985
48 * Davicom DM9100, DM9102, DM9102A (www.davicom8.com)
49 * Accton EN1217 (www.accton.com)
50 * Xircom X3201 (www.xircom.com)
52 * Conexant LANfinity (www.conexant.com)
53 * 3Com OfficeConnect 10/100B 3CSOHO100B (www.3com.com)
55 * Datasheets for the 21143 are available at developer.intel.com.
56 * Datasheets for the clone parts can be found at their respective sites.
57 * (Except for the PNIC; see www.freebsd.org/~wpaul/PNIC/pnic.ps.gz.)
58 * The PNIC II is essentially a Macronix 98715A chip; the only difference
59 * worth noting is that its multicast hash table is only 128 bits wide
62 * Written by Bill Paul <wpaul@ee.columbia.edu>
63 * Electrical Engineering Department
64 * Columbia University, New York City
67 * The Intel 21143 is the successor to the DEC 21140. It is basically
68 * the same as the 21140 but with a few new features. The 21143 supports
69 * three kinds of media attachments:
71 * o MII port, for 10Mbps and 100Mbps support and NWAY
72 * autonegotiation provided by an external PHY.
73 * o SYM port, for symbol mode 100Mbps support.
77 * The 100Mbps SYM port and 10baseT port can be used together in
78 * combination with the internal NWAY support to create a 10/100
79 * autosensing configuration.
81 * Note that not all tulip workalikes are handled in this driver: we only
82 * deal with those which are relatively well behaved. The Winbond is
83 * handled separately due to its different register offsets and the
84 * special handling needed for its various bugs. The PNIC is handled
85 * here, but I'm not thrilled about it.
87 * All of the workalike chips use some form of MII transceiver support
88 * with the exception of the Macronix chips, which also have a SYM port.
89 * The ASIX AX88140A is also documented to have a SYM port, but all
90 * the cards I've seen use an MII transceiver, probably because the
91 * AX88140A doesn't support internal NWAY.
94 #ifdef HAVE_KERNEL_OPTION_HEADERS
95 #include "opt_device_polling.h"
98 #include <sys/param.h>
99 #include <sys/endian.h>
100 #include <sys/systm.h>
101 #include <sys/sockio.h>
102 #include <sys/mbuf.h>
103 #include <sys/malloc.h>
104 #include <sys/kernel.h>
105 #include <sys/module.h>
106 #include <sys/socket.h>
109 #include <net/if_arp.h>
110 #include <net/ethernet.h>
111 #include <net/if_dl.h>
112 #include <net/if_media.h>
113 #include <net/if_types.h>
114 #include <net/if_vlan_var.h>
118 #include <machine/bus.h>
119 #include <machine/resource.h>
121 #include <sys/rman.h>
123 #include <dev/mii/mii.h>
124 #include <dev/mii/miivar.h>
126 #include <dev/pci/pcireg.h>
127 #include <dev/pci/pcivar.h>
129 #define DC_USEIOSPACE
131 #include <dev/dc/if_dcreg.h>
134 #include <dev/ofw/openfirm.h>
135 #include <machine/ofw_machdep.h>
138 MODULE_DEPEND(dc, pci, 1, 1, 1);
139 MODULE_DEPEND(dc, ether, 1, 1, 1);
140 MODULE_DEPEND(dc, miibus, 1, 1, 1);
143 * "device miibus" is required in kernel config. See GENERIC if you get
146 #include "miibus_if.h"
149 * Various supported device vendors/types and their names.
151 static const struct dc_type dc_devs[] = {
152 { DC_DEVID(DC_VENDORID_DEC, DC_DEVICEID_21143), 0,
153 "Intel 21143 10/100BaseTX" },
154 { DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9009), 0,
155 "Davicom DM9009 10/100BaseTX" },
156 { DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9100), 0,
157 "Davicom DM9100 10/100BaseTX" },
158 { DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102), DC_REVISION_DM9102A,
159 "Davicom DM9102A 10/100BaseTX" },
160 { DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102), 0,
161 "Davicom DM9102 10/100BaseTX" },
162 { DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_AL981), 0,
163 "ADMtek AL981 10/100BaseTX" },
164 { DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_AN985), 0,
165 "ADMtek AN985 10/100BaseTX" },
166 { DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9511), 0,
167 "ADMtek ADM9511 10/100BaseTX" },
168 { DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9513), 0,
169 "ADMtek ADM9513 10/100BaseTX" },
170 { DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_FA511), 0,
171 "Netgear FA511 10/100BaseTX" },
172 { DC_DEVID(DC_VENDORID_ASIX, DC_DEVICEID_AX88140A), DC_REVISION_88141,
173 "ASIX AX88141 10/100BaseTX" },
174 { DC_DEVID(DC_VENDORID_ASIX, DC_DEVICEID_AX88140A), 0,
175 "ASIX AX88140A 10/100BaseTX" },
176 { DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_98713), DC_REVISION_98713A,
177 "Macronix 98713A 10/100BaseTX" },
178 { DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_98713), 0,
179 "Macronix 98713 10/100BaseTX" },
180 { DC_DEVID(DC_VENDORID_CP, DC_DEVICEID_98713_CP), DC_REVISION_98713A,
181 "Compex RL100-TX 10/100BaseTX" },
182 { DC_DEVID(DC_VENDORID_CP, DC_DEVICEID_98713_CP), 0,
183 "Compex RL100-TX 10/100BaseTX" },
184 { DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_987x5), DC_REVISION_98725,
185 "Macronix 98725 10/100BaseTX" },
186 { DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_987x5), DC_REVISION_98715AEC_C,
187 "Macronix 98715AEC-C 10/100BaseTX" },
188 { DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_987x5), 0,
189 "Macronix 98715/98715A 10/100BaseTX" },
190 { DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_98727), 0,
191 "Macronix 98727/98732 10/100BaseTX" },
192 { DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C115), 0,
193 "LC82C115 PNIC II 10/100BaseTX" },
194 { DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C168), DC_REVISION_82C169,
195 "82c169 PNIC 10/100BaseTX" },
196 { DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C168), 0,
197 "82c168 PNIC 10/100BaseTX" },
198 { DC_DEVID(DC_VENDORID_ACCTON, DC_DEVICEID_EN1217), 0,
199 "Accton EN1217 10/100BaseTX" },
200 { DC_DEVID(DC_VENDORID_ACCTON, DC_DEVICEID_EN2242), 0,
201 "Accton EN2242 MiniPCI 10/100BaseTX" },
202 { DC_DEVID(DC_VENDORID_XIRCOM, DC_DEVICEID_X3201), 0,
203 "Xircom X3201 10/100BaseTX" },
204 { DC_DEVID(DC_VENDORID_DLINK, DC_DEVICEID_DRP32TXD), 0,
205 "Neteasy DRP-32TXD Cardbus 10/100" },
206 { DC_DEVID(DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500), 0,
207 "Abocom FE2500 10/100BaseTX" },
208 { DC_DEVID(DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500MX), 0,
209 "Abocom FE2500MX 10/100BaseTX" },
210 { DC_DEVID(DC_VENDORID_CONEXANT, DC_DEVICEID_RS7112), 0,
211 "Conexant LANfinity MiniPCI 10/100BaseTX" },
212 { DC_DEVID(DC_VENDORID_HAWKING, DC_DEVICEID_HAWKING_PN672TX), 0,
213 "Hawking CB102 CardBus 10/100" },
214 { DC_DEVID(DC_VENDORID_PLANEX, DC_DEVICEID_FNW3602T), 0,
215 "PlaneX FNW-3602-T CardBus 10/100" },
216 { DC_DEVID(DC_VENDORID_3COM, DC_DEVICEID_3CSOHOB), 0,
217 "3Com OfficeConnect 10/100B" },
218 { DC_DEVID(DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN120), 0,
219 "Microsoft MN-120 CardBus 10/100" },
220 { DC_DEVID(DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN130), 0,
221 "Microsoft MN-130 10/100" },
222 { DC_DEVID(DC_VENDORID_LINKSYS, DC_DEVICEID_PCMPC200_AB08), 0,
223 "Linksys PCMPC200 CardBus 10/100" },
224 { DC_DEVID(DC_VENDORID_LINKSYS, DC_DEVICEID_PCMPC200_AB09), 0,
225 "Linksys PCMPC200 CardBus 10/100" },
229 static int dc_probe(device_t);
230 static int dc_attach(device_t);
231 static int dc_detach(device_t);
232 static int dc_suspend(device_t);
233 static int dc_resume(device_t);
234 static const struct dc_type *dc_devtype(device_t);
235 static int dc_newbuf(struct dc_softc *, int, int);
236 static int dc_encap(struct dc_softc *, struct mbuf **);
237 static void dc_pnic_rx_bug_war(struct dc_softc *, int);
238 static int dc_rx_resync(struct dc_softc *);
239 static int dc_rxeof(struct dc_softc *);
240 static void dc_txeof(struct dc_softc *);
241 static void dc_tick(void *);
242 static void dc_tx_underrun(struct dc_softc *);
243 static void dc_intr(void *);
244 static void dc_start(struct ifnet *);
245 static void dc_start_locked(struct ifnet *);
246 static int dc_ioctl(struct ifnet *, u_long, caddr_t);
247 static void dc_init(void *);
248 static void dc_init_locked(struct dc_softc *);
249 static void dc_stop(struct dc_softc *);
250 static void dc_watchdog(void *);
251 static int dc_shutdown(device_t);
252 static int dc_ifmedia_upd(struct ifnet *);
253 static void dc_ifmedia_sts(struct ifnet *, struct ifmediareq *);
255 static void dc_delay(struct dc_softc *);
256 static void dc_eeprom_idle(struct dc_softc *);
257 static void dc_eeprom_putbyte(struct dc_softc *, int);
258 static void dc_eeprom_getword(struct dc_softc *, int, u_int16_t *);
259 static void dc_eeprom_getword_pnic(struct dc_softc *, int, u_int16_t *);
260 static void dc_eeprom_getword_xircom(struct dc_softc *, int, u_int16_t *);
261 static void dc_eeprom_width(struct dc_softc *);
262 static void dc_read_eeprom(struct dc_softc *, caddr_t, int, int, int);
264 static void dc_mii_writebit(struct dc_softc *, int);
265 static int dc_mii_readbit(struct dc_softc *);
266 static void dc_mii_sync(struct dc_softc *);
267 static void dc_mii_send(struct dc_softc *, u_int32_t, int);
268 static int dc_mii_readreg(struct dc_softc *, struct dc_mii_frame *);
269 static int dc_mii_writereg(struct dc_softc *, struct dc_mii_frame *);
270 static int dc_miibus_readreg(device_t, int, int);
271 static int dc_miibus_writereg(device_t, int, int, int);
272 static void dc_miibus_statchg(device_t);
273 static void dc_miibus_mediainit(device_t);
275 static void dc_setcfg(struct dc_softc *, int);
276 static uint32_t dc_mchash_le(struct dc_softc *, const uint8_t *);
277 static uint32_t dc_mchash_be(const uint8_t *);
278 static void dc_setfilt_21143(struct dc_softc *);
279 static void dc_setfilt_asix(struct dc_softc *);
280 static void dc_setfilt_admtek(struct dc_softc *);
281 static void dc_setfilt_xircom(struct dc_softc *);
283 static void dc_setfilt(struct dc_softc *);
285 static void dc_reset(struct dc_softc *);
286 static int dc_list_rx_init(struct dc_softc *);
287 static int dc_list_tx_init(struct dc_softc *);
289 static void dc_read_srom(struct dc_softc *, int);
290 static void dc_parse_21143_srom(struct dc_softc *);
291 static void dc_decode_leaf_sia(struct dc_softc *, struct dc_eblock_sia *);
292 static void dc_decode_leaf_mii(struct dc_softc *, struct dc_eblock_mii *);
293 static void dc_decode_leaf_sym(struct dc_softc *, struct dc_eblock_sym *);
294 static void dc_apply_fixup(struct dc_softc *, int);
297 #define DC_RES SYS_RES_IOPORT
298 #define DC_RID DC_PCI_CFBIO
300 #define DC_RES SYS_RES_MEMORY
301 #define DC_RID DC_PCI_CFBMA
304 static device_method_t dc_methods[] = {
305 /* Device interface */
306 DEVMETHOD(device_probe, dc_probe),
307 DEVMETHOD(device_attach, dc_attach),
308 DEVMETHOD(device_detach, dc_detach),
309 DEVMETHOD(device_suspend, dc_suspend),
310 DEVMETHOD(device_resume, dc_resume),
311 DEVMETHOD(device_shutdown, dc_shutdown),
314 DEVMETHOD(bus_print_child, bus_generic_print_child),
315 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
318 DEVMETHOD(miibus_readreg, dc_miibus_readreg),
319 DEVMETHOD(miibus_writereg, dc_miibus_writereg),
320 DEVMETHOD(miibus_statchg, dc_miibus_statchg),
321 DEVMETHOD(miibus_mediainit, dc_miibus_mediainit),
326 static driver_t dc_driver = {
329 sizeof(struct dc_softc)
332 static devclass_t dc_devclass;
334 DRIVER_MODULE(dc, pci, dc_driver, dc_devclass, 0, 0);
335 DRIVER_MODULE(miibus, dc, miibus_driver, miibus_devclass, 0, 0);
337 #define DC_SETBIT(sc, reg, x) \
338 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x))
340 #define DC_CLRBIT(sc, reg, x) \
341 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x))
343 #define SIO_SET(x) DC_SETBIT(sc, DC_SIO, (x))
344 #define SIO_CLR(x) DC_CLRBIT(sc, DC_SIO, (x))
347 dc_delay(struct dc_softc *sc)
351 for (idx = (300 / 33) + 1; idx > 0; idx--)
352 CSR_READ_4(sc, DC_BUSCTL);
356 dc_eeprom_width(struct dc_softc *sc)
360 /* Force EEPROM to idle state. */
363 /* Enter EEPROM access mode. */
364 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL);
366 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ);
368 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
370 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS);
375 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN);
377 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN);
379 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK);
381 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
385 for (i = 1; i <= 12; i++) {
386 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK);
388 if (!(CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT)) {
389 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
393 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
397 /* Turn off EEPROM access mode. */
405 /* Enter EEPROM access mode. */
406 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL);
408 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ);
410 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
412 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS);
415 /* Turn off EEPROM access mode. */
420 dc_eeprom_idle(struct dc_softc *sc)
424 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL);
426 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ);
428 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
430 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS);
433 for (i = 0; i < 25; i++) {
434 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
436 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK);
440 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
442 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CS);
444 CSR_WRITE_4(sc, DC_SIO, 0x00000000);
448 * Send a read command and address to the EEPROM, check for ACK.
451 dc_eeprom_putbyte(struct dc_softc *sc, int addr)
455 d = DC_EECMD_READ >> 6;
458 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN);
460 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN);
462 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK);
464 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
469 * Feed in each bit and strobe the clock.
471 for (i = sc->dc_romwidth; i--;) {
472 if (addr & (1 << i)) {
473 SIO_SET(DC_SIO_EE_DATAIN);
475 SIO_CLR(DC_SIO_EE_DATAIN);
478 SIO_SET(DC_SIO_EE_CLK);
480 SIO_CLR(DC_SIO_EE_CLK);
486 * Read a word of data stored in the EEPROM at address 'addr.'
487 * The PNIC 82c168/82c169 has its own non-standard way to read
491 dc_eeprom_getword_pnic(struct dc_softc *sc, int addr, u_int16_t *dest)
496 CSR_WRITE_4(sc, DC_PN_SIOCTL, DC_PN_EEOPCODE_READ | addr);
498 for (i = 0; i < DC_TIMEOUT; i++) {
500 r = CSR_READ_4(sc, DC_SIO);
501 if (!(r & DC_PN_SIOCTL_BUSY)) {
502 *dest = (u_int16_t)(r & 0xFFFF);
509 * Read a word of data stored in the EEPROM at address 'addr.'
510 * The Xircom X3201 has its own non-standard way to read
514 dc_eeprom_getword_xircom(struct dc_softc *sc, int addr, u_int16_t *dest)
517 SIO_SET(DC_SIO_ROMSEL | DC_SIO_ROMCTL_READ);
520 CSR_WRITE_4(sc, DC_ROM, addr | 0x160);
521 *dest = (u_int16_t)CSR_READ_4(sc, DC_SIO) & 0xff;
523 CSR_WRITE_4(sc, DC_ROM, addr | 0x160);
524 *dest |= ((u_int16_t)CSR_READ_4(sc, DC_SIO) & 0xff) << 8;
526 SIO_CLR(DC_SIO_ROMSEL | DC_SIO_ROMCTL_READ);
530 * Read a word of data stored in the EEPROM at address 'addr.'
533 dc_eeprom_getword(struct dc_softc *sc, int addr, u_int16_t *dest)
538 /* Force EEPROM to idle state. */
541 /* Enter EEPROM access mode. */
542 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL);
544 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ);
546 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
548 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS);
552 * Send address of word we want to read.
554 dc_eeprom_putbyte(sc, addr);
557 * Start reading bits from EEPROM.
559 for (i = 0x8000; i; i >>= 1) {
560 SIO_SET(DC_SIO_EE_CLK);
562 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT)
565 SIO_CLR(DC_SIO_EE_CLK);
569 /* Turn off EEPROM access mode. */
576 * Read a sequence of words from the EEPROM.
579 dc_read_eeprom(struct dc_softc *sc, caddr_t dest, int off, int cnt, int be)
582 u_int16_t word = 0, *ptr;
584 for (i = 0; i < cnt; i++) {
586 dc_eeprom_getword_pnic(sc, off + i, &word);
587 else if (DC_IS_XIRCOM(sc))
588 dc_eeprom_getword_xircom(sc, off + i, &word);
590 dc_eeprom_getword(sc, off + i, &word);
591 ptr = (u_int16_t *)(dest + (i * 2));
593 *ptr = be16toh(word);
595 *ptr = le16toh(word);
600 * The following two routines are taken from the Macronix 98713
601 * Application Notes pp.19-21.
604 * Write a bit to the MII bus.
607 dc_mii_writebit(struct dc_softc *sc, int bit)
611 reg = DC_SIO_ROMCTL_WRITE | (bit != 0 ? DC_SIO_MII_DATAOUT : 0);
612 CSR_WRITE_4(sc, DC_SIO, reg);
613 CSR_BARRIER_4(sc, DC_SIO,
614 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
617 CSR_WRITE_4(sc, DC_SIO, reg | DC_SIO_MII_CLK);
618 CSR_BARRIER_4(sc, DC_SIO,
619 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
621 CSR_WRITE_4(sc, DC_SIO, reg);
622 CSR_BARRIER_4(sc, DC_SIO,
623 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
628 * Read a bit from the MII bus.
631 dc_mii_readbit(struct dc_softc *sc)
635 reg = DC_SIO_ROMCTL_READ | DC_SIO_MII_DIR;
636 CSR_WRITE_4(sc, DC_SIO, reg);
637 CSR_BARRIER_4(sc, DC_SIO,
638 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
640 (void)CSR_READ_4(sc, DC_SIO);
641 CSR_WRITE_4(sc, DC_SIO, reg | DC_SIO_MII_CLK);
642 CSR_BARRIER_4(sc, DC_SIO,
643 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
645 CSR_WRITE_4(sc, DC_SIO, reg);
646 CSR_BARRIER_4(sc, DC_SIO,
647 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
649 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_MII_DATAIN)
656 * Sync the PHYs by setting data bit and strobing the clock 32 times.
659 dc_mii_sync(struct dc_softc *sc)
663 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE);
664 CSR_BARRIER_4(sc, DC_SIO,
665 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
668 for (i = 0; i < 32; i++)
669 dc_mii_writebit(sc, 1);
673 * Clock a series of bits through the MII.
676 dc_mii_send(struct dc_softc *sc, u_int32_t bits, int cnt)
680 for (i = (0x1 << (cnt - 1)); i; i >>= 1)
681 dc_mii_writebit(sc, bits & i);
685 * Read an PHY register through the MII.
688 dc_mii_readreg(struct dc_softc *sc, struct dc_mii_frame *frame)
693 * Set up frame for RX.
695 frame->mii_stdelim = DC_MII_STARTDELIM;
696 frame->mii_opcode = DC_MII_READOP;
704 * Send command/address info.
706 dc_mii_send(sc, frame->mii_stdelim, 2);
707 dc_mii_send(sc, frame->mii_opcode, 2);
708 dc_mii_send(sc, frame->mii_phyaddr, 5);
709 dc_mii_send(sc, frame->mii_regaddr, 5);
712 * Now try reading data bits. If the turnaround failed, we still
713 * need to clock through 16 cycles to keep the PHY(s) in sync.
715 frame->mii_turnaround = dc_mii_readbit(sc);
716 if (frame->mii_turnaround != 0) {
717 for (i = 0; i < 16; i++)
721 for (i = 0x8000; i; i >>= 1) {
722 if (dc_mii_readbit(sc))
723 frame->mii_data |= i;
728 /* Clock the idle bits. */
729 dc_mii_writebit(sc, 0);
730 dc_mii_writebit(sc, 0);
732 if (frame->mii_turnaround != 0)
738 * Write to a PHY register through the MII.
741 dc_mii_writereg(struct dc_softc *sc, struct dc_mii_frame *frame)
745 * Set up frame for TX.
747 frame->mii_stdelim = DC_MII_STARTDELIM;
748 frame->mii_opcode = DC_MII_WRITEOP;
749 frame->mii_turnaround = DC_MII_TURNAROUND;
756 dc_mii_send(sc, frame->mii_stdelim, 2);
757 dc_mii_send(sc, frame->mii_opcode, 2);
758 dc_mii_send(sc, frame->mii_phyaddr, 5);
759 dc_mii_send(sc, frame->mii_regaddr, 5);
760 dc_mii_send(sc, frame->mii_turnaround, 2);
761 dc_mii_send(sc, frame->mii_data, 16);
763 /* Clock the idle bits. */
764 dc_mii_writebit(sc, 0);
765 dc_mii_writebit(sc, 0);
771 dc_miibus_readreg(device_t dev, int phy, int reg)
773 struct dc_mii_frame frame;
775 int i, rval, phy_reg = 0;
777 sc = device_get_softc(dev);
778 bzero(&frame, sizeof(frame));
781 * Note: both the AL981 and AN985 have internal PHYs,
782 * however the AL981 provides direct access to the PHY
783 * registers while the AN985 uses a serial MII interface.
784 * The AN985's MII interface is also buggy in that you
785 * can read from any MII address (0 to 31), but only address 1
786 * behaves normally. To deal with both cases, we pretend
787 * that the PHY is at MII address 1.
789 if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR)
793 * Note: the ukphy probes of the RS7112 report a PHY at
794 * MII address 0 (possibly HomePNA?) and 1 (ethernet)
795 * so we only respond to correct one.
797 if (DC_IS_CONEXANT(sc) && phy != DC_CONEXANT_PHYADDR)
800 if (sc->dc_pmode != DC_PMODE_MII) {
801 if (phy == (MII_NPHY - 1)) {
805 * Fake something to make the probe
806 * code think there's a PHY here.
808 return (BMSR_MEDIAMASK);
812 return (DC_VENDORID_LO);
813 return (DC_VENDORID_DEC);
817 return (DC_DEVICEID_82C168);
818 return (DC_DEVICEID_21143);
828 if (DC_IS_PNIC(sc)) {
829 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_READ |
830 (phy << 23) | (reg << 18));
831 for (i = 0; i < DC_TIMEOUT; i++) {
833 rval = CSR_READ_4(sc, DC_PN_MII);
834 if (!(rval & DC_PN_MII_BUSY)) {
836 return (rval == 0xFFFF ? 0 : rval);
842 if (DC_IS_COMET(sc)) {
845 phy_reg = DC_AL_BMCR;
848 phy_reg = DC_AL_BMSR;
851 phy_reg = DC_AL_VENID;
854 phy_reg = DC_AL_DEVID;
857 phy_reg = DC_AL_ANAR;
860 phy_reg = DC_AL_LPAR;
863 phy_reg = DC_AL_ANER;
866 device_printf(dev, "phy_read: bad phy register %x\n",
872 rval = CSR_READ_4(sc, phy_reg) & 0x0000FFFF;
879 frame.mii_phyaddr = phy;
880 frame.mii_regaddr = reg;
881 if (sc->dc_type == DC_TYPE_98713) {
882 phy_reg = CSR_READ_4(sc, DC_NETCFG);
883 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL);
885 dc_mii_readreg(sc, &frame);
886 if (sc->dc_type == DC_TYPE_98713)
887 CSR_WRITE_4(sc, DC_NETCFG, phy_reg);
889 return (frame.mii_data);
893 dc_miibus_writereg(device_t dev, int phy, int reg, int data)
896 struct dc_mii_frame frame;
899 sc = device_get_softc(dev);
900 bzero(&frame, sizeof(frame));
902 if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR)
905 if (DC_IS_CONEXANT(sc) && phy != DC_CONEXANT_PHYADDR)
908 if (DC_IS_PNIC(sc)) {
909 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_WRITE |
910 (phy << 23) | (reg << 10) | data);
911 for (i = 0; i < DC_TIMEOUT; i++) {
912 if (!(CSR_READ_4(sc, DC_PN_MII) & DC_PN_MII_BUSY))
918 if (DC_IS_COMET(sc)) {
921 phy_reg = DC_AL_BMCR;
924 phy_reg = DC_AL_BMSR;
927 phy_reg = DC_AL_VENID;
930 phy_reg = DC_AL_DEVID;
933 phy_reg = DC_AL_ANAR;
936 phy_reg = DC_AL_LPAR;
939 phy_reg = DC_AL_ANER;
942 device_printf(dev, "phy_write: bad phy register %x\n",
948 CSR_WRITE_4(sc, phy_reg, data);
952 frame.mii_phyaddr = phy;
953 frame.mii_regaddr = reg;
954 frame.mii_data = data;
956 if (sc->dc_type == DC_TYPE_98713) {
957 phy_reg = CSR_READ_4(sc, DC_NETCFG);
958 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL);
960 dc_mii_writereg(sc, &frame);
961 if (sc->dc_type == DC_TYPE_98713)
962 CSR_WRITE_4(sc, DC_NETCFG, phy_reg);
968 dc_miibus_statchg(device_t dev)
971 struct mii_data *mii;
974 sc = device_get_softc(dev);
975 if (DC_IS_ADMTEK(sc))
978 mii = device_get_softc(sc->dc_miibus);
979 ifm = &mii->mii_media;
980 if (DC_IS_DAVICOM(sc) &&
981 IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) {
982 dc_setcfg(sc, ifm->ifm_media);
983 sc->dc_if_media = ifm->ifm_media;
985 dc_setcfg(sc, mii->mii_media_active);
986 sc->dc_if_media = mii->mii_media_active;
991 * Special support for DM9102A cards with HomePNA PHYs. Note:
992 * with the Davicom DM9102A/DM9801 eval board that I have, it seems
993 * to be impossible to talk to the management interface of the DM9801
994 * PHY (its MDIO pin is not connected to anything). Consequently,
995 * the driver has to just 'know' about the additional mode and deal
996 * with it itself. *sigh*
999 dc_miibus_mediainit(device_t dev)
1001 struct dc_softc *sc;
1002 struct mii_data *mii;
1003 struct ifmedia *ifm;
1006 rev = pci_get_revid(dev);
1008 sc = device_get_softc(dev);
1009 mii = device_get_softc(sc->dc_miibus);
1010 ifm = &mii->mii_media;
1012 if (DC_IS_DAVICOM(sc) && rev >= DC_REVISION_DM9102A)
1013 ifmedia_add(ifm, IFM_ETHER | IFM_HPNA_1, 0, NULL);
1016 #define DC_BITS_512 9
1017 #define DC_BITS_128 7
1018 #define DC_BITS_64 6
1021 dc_mchash_le(struct dc_softc *sc, const uint8_t *addr)
1025 /* Compute CRC for the address value. */
1026 crc = ether_crc32_le(addr, ETHER_ADDR_LEN);
1029 * The hash table on the PNIC II and the MX98715AEC-C/D/E
1030 * chips is only 128 bits wide.
1032 if (sc->dc_flags & DC_128BIT_HASH)
1033 return (crc & ((1 << DC_BITS_128) - 1));
1035 /* The hash table on the MX98715BEC is only 64 bits wide. */
1036 if (sc->dc_flags & DC_64BIT_HASH)
1037 return (crc & ((1 << DC_BITS_64) - 1));
1039 /* Xircom's hash filtering table is different (read: weird) */
1040 /* Xircom uses the LEAST significant bits */
1041 if (DC_IS_XIRCOM(sc)) {
1042 if ((crc & 0x180) == 0x180)
1043 return ((crc & 0x0F) + (crc & 0x70) * 3 + (14 << 4));
1045 return ((crc & 0x1F) + ((crc >> 1) & 0xF0) * 3 +
1049 return (crc & ((1 << DC_BITS_512) - 1));
1053 * Calculate CRC of a multicast group address, return the lower 6 bits.
1056 dc_mchash_be(const uint8_t *addr)
1060 /* Compute CRC for the address value. */
1061 crc = ether_crc32_be(addr, ETHER_ADDR_LEN);
1063 /* Return the filter bit position. */
1064 return ((crc >> 26) & 0x0000003F);
1068 * 21143-style RX filter setup routine. Filter programming is done by
1069 * downloading a special setup frame into the TX engine. 21143, Macronix,
1070 * PNIC, PNIC II and Davicom chips are programmed this way.
1072 * We always program the chip using 'hash perfect' mode, i.e. one perfect
1073 * address (our node address) and a 512-bit hash filter for multicast
1074 * frames. We also sneak the broadcast address into the hash filter since
1078 dc_setfilt_21143(struct dc_softc *sc)
1080 uint16_t eaddr[(ETHER_ADDR_LEN+1)/2];
1081 struct dc_desc *sframe;
1083 struct ifmultiaddr *ifma;
1089 i = sc->dc_cdata.dc_tx_prod;
1090 DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT);
1091 sc->dc_cdata.dc_tx_cnt++;
1092 sframe = &sc->dc_ldata->dc_tx_list[i];
1093 sp = sc->dc_cdata.dc_sbuf;
1094 bzero(sp, DC_SFRAME_LEN);
1096 sframe->dc_data = htole32(sc->dc_saddr);
1097 sframe->dc_ctl = htole32(DC_SFRAME_LEN | DC_TXCTL_SETUP |
1098 DC_TXCTL_TLINK | DC_FILTER_HASHPERF | DC_TXCTL_FINT);
1100 sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)sc->dc_cdata.dc_sbuf;
1102 /* If we want promiscuous mode, set the allframes bit. */
1103 if (ifp->if_flags & IFF_PROMISC)
1104 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1106 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1108 if (ifp->if_flags & IFF_ALLMULTI)
1109 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1111 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1113 if_maddr_rlock(ifp);
1114 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1115 if (ifma->ifma_addr->sa_family != AF_LINK)
1117 h = dc_mchash_le(sc,
1118 LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
1119 sp[h >> 4] |= htole32(1 << (h & 0xF));
1121 if_maddr_runlock(ifp);
1123 if (ifp->if_flags & IFF_BROADCAST) {
1124 h = dc_mchash_le(sc, ifp->if_broadcastaddr);
1125 sp[h >> 4] |= htole32(1 << (h & 0xF));
1128 /* Set our MAC address. */
1129 bcopy(IF_LLADDR(sc->dc_ifp), eaddr, ETHER_ADDR_LEN);
1130 sp[39] = DC_SP_MAC(eaddr[0]);
1131 sp[40] = DC_SP_MAC(eaddr[1]);
1132 sp[41] = DC_SP_MAC(eaddr[2]);
1134 sframe->dc_status = htole32(DC_TXSTAT_OWN);
1135 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF);
1138 * The PNIC takes an exceedingly long time to process its
1139 * setup frame; wait 10ms after posting the setup frame
1140 * before proceeding, just so it has time to swallow its
1145 sc->dc_wdog_timer = 5;
1149 dc_setfilt_admtek(struct dc_softc *sc)
1151 uint8_t eaddr[ETHER_ADDR_LEN];
1153 struct ifmultiaddr *ifma;
1155 u_int32_t hashes[2] = { 0, 0 };
1159 /* Init our MAC address. */
1160 bcopy(IF_LLADDR(sc->dc_ifp), eaddr, ETHER_ADDR_LEN);
1161 CSR_WRITE_4(sc, DC_AL_PAR0, eaddr[3] << 24 | eaddr[2] << 16 |
1162 eaddr[1] << 8 | eaddr[0]);
1163 CSR_WRITE_4(sc, DC_AL_PAR1, eaddr[5] << 8 | eaddr[4]);
1165 /* If we want promiscuous mode, set the allframes bit. */
1166 if (ifp->if_flags & IFF_PROMISC)
1167 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1169 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1171 if (ifp->if_flags & IFF_ALLMULTI)
1172 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1174 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1176 /* First, zot all the existing hash bits. */
1177 CSR_WRITE_4(sc, DC_AL_MAR0, 0);
1178 CSR_WRITE_4(sc, DC_AL_MAR1, 0);
1181 * If we're already in promisc or allmulti mode, we
1182 * don't have to bother programming the multicast filter.
1184 if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI))
1187 /* Now program new ones. */
1188 if_maddr_rlock(ifp);
1189 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1190 if (ifma->ifma_addr->sa_family != AF_LINK)
1192 if (DC_IS_CENTAUR(sc))
1193 h = dc_mchash_le(sc,
1194 LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
1197 LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
1199 hashes[0] |= (1 << h);
1201 hashes[1] |= (1 << (h - 32));
1203 if_maddr_runlock(ifp);
1205 CSR_WRITE_4(sc, DC_AL_MAR0, hashes[0]);
1206 CSR_WRITE_4(sc, DC_AL_MAR1, hashes[1]);
1210 dc_setfilt_asix(struct dc_softc *sc)
1212 uint32_t eaddr[(ETHER_ADDR_LEN+3)/4];
1214 struct ifmultiaddr *ifma;
1216 u_int32_t hashes[2] = { 0, 0 };
1220 /* Init our MAC address. */
1221 bcopy(IF_LLADDR(sc->dc_ifp), eaddr, ETHER_ADDR_LEN);
1222 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR0);
1223 CSR_WRITE_4(sc, DC_AX_FILTDATA, eaddr[0]);
1224 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR1);
1225 CSR_WRITE_4(sc, DC_AX_FILTDATA, eaddr[1]);
1227 /* If we want promiscuous mode, set the allframes bit. */
1228 if (ifp->if_flags & IFF_PROMISC)
1229 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1231 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1233 if (ifp->if_flags & IFF_ALLMULTI)
1234 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1236 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1239 * The ASIX chip has a special bit to enable reception
1240 * of broadcast frames.
1242 if (ifp->if_flags & IFF_BROADCAST)
1243 DC_SETBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD);
1245 DC_CLRBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD);
1247 /* first, zot all the existing hash bits */
1248 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0);
1249 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0);
1250 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1);
1251 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0);
1254 * If we're already in promisc or allmulti mode, we
1255 * don't have to bother programming the multicast filter.
1257 if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI))
1260 /* now program new ones */
1261 if_maddr_rlock(ifp);
1262 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1263 if (ifma->ifma_addr->sa_family != AF_LINK)
1265 h = dc_mchash_be(LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
1267 hashes[0] |= (1 << h);
1269 hashes[1] |= (1 << (h - 32));
1271 if_maddr_runlock(ifp);
1273 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0);
1274 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[0]);
1275 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1);
1276 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[1]);
1280 dc_setfilt_xircom(struct dc_softc *sc)
1282 uint16_t eaddr[(ETHER_ADDR_LEN+1)/2];
1284 struct ifmultiaddr *ifma;
1285 struct dc_desc *sframe;
1290 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON));
1292 i = sc->dc_cdata.dc_tx_prod;
1293 DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT);
1294 sc->dc_cdata.dc_tx_cnt++;
1295 sframe = &sc->dc_ldata->dc_tx_list[i];
1296 sp = sc->dc_cdata.dc_sbuf;
1297 bzero(sp, DC_SFRAME_LEN);
1299 sframe->dc_data = htole32(sc->dc_saddr);
1300 sframe->dc_ctl = htole32(DC_SFRAME_LEN | DC_TXCTL_SETUP |
1301 DC_TXCTL_TLINK | DC_FILTER_HASHPERF | DC_TXCTL_FINT);
1303 sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)sc->dc_cdata.dc_sbuf;
1305 /* If we want promiscuous mode, set the allframes bit. */
1306 if (ifp->if_flags & IFF_PROMISC)
1307 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1309 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1311 if (ifp->if_flags & IFF_ALLMULTI)
1312 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1314 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1316 if_maddr_rlock(ifp);
1317 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1318 if (ifma->ifma_addr->sa_family != AF_LINK)
1320 h = dc_mchash_le(sc,
1321 LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
1322 sp[h >> 4] |= htole32(1 << (h & 0xF));
1324 if_maddr_runlock(ifp);
1326 if (ifp->if_flags & IFF_BROADCAST) {
1327 h = dc_mchash_le(sc, ifp->if_broadcastaddr);
1328 sp[h >> 4] |= htole32(1 << (h & 0xF));
1331 /* Set our MAC address. */
1332 bcopy(IF_LLADDR(sc->dc_ifp), eaddr, ETHER_ADDR_LEN);
1333 sp[0] = DC_SP_MAC(eaddr[0]);
1334 sp[1] = DC_SP_MAC(eaddr[1]);
1335 sp[2] = DC_SP_MAC(eaddr[2]);
1337 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON);
1338 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON);
1339 ifp->if_drv_flags |= IFF_DRV_RUNNING;
1340 sframe->dc_status = htole32(DC_TXSTAT_OWN);
1341 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF);
1348 sc->dc_wdog_timer = 5;
1352 dc_setfilt(struct dc_softc *sc)
1355 if (DC_IS_INTEL(sc) || DC_IS_MACRONIX(sc) || DC_IS_PNIC(sc) ||
1356 DC_IS_PNICII(sc) || DC_IS_DAVICOM(sc) || DC_IS_CONEXANT(sc))
1357 dc_setfilt_21143(sc);
1360 dc_setfilt_asix(sc);
1362 if (DC_IS_ADMTEK(sc))
1363 dc_setfilt_admtek(sc);
1365 if (DC_IS_XIRCOM(sc))
1366 dc_setfilt_xircom(sc);
1370 * In order to fiddle with the 'full-duplex' and '100Mbps' bits in
1371 * the netconfig register, we first have to put the transmit and/or
1372 * receive logic in the idle state.
1375 dc_setcfg(struct dc_softc *sc, int media)
1377 int i, restart = 0, watchdogreg;
1380 if (IFM_SUBTYPE(media) == IFM_NONE)
1383 if (CSR_READ_4(sc, DC_NETCFG) & (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON)) {
1385 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON));
1387 for (i = 0; i < DC_TIMEOUT; i++) {
1388 isr = CSR_READ_4(sc, DC_ISR);
1389 if (isr & DC_ISR_TX_IDLE &&
1390 ((isr & DC_ISR_RX_STATE) == DC_RXSTATE_STOPPED ||
1391 (isr & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT))
1396 if (i == DC_TIMEOUT) {
1397 if (!(isr & DC_ISR_TX_IDLE) && !DC_IS_ASIX(sc))
1398 device_printf(sc->dc_dev,
1399 "%s: failed to force tx to idle state\n",
1401 if (!((isr & DC_ISR_RX_STATE) == DC_RXSTATE_STOPPED ||
1402 (isr & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT) &&
1403 !DC_HAS_BROKEN_RXSTATE(sc))
1404 device_printf(sc->dc_dev,
1405 "%s: failed to force rx to idle state\n",
1410 if (IFM_SUBTYPE(media) == IFM_100_TX) {
1411 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL);
1412 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT);
1413 if (sc->dc_pmode == DC_PMODE_MII) {
1414 if (DC_IS_INTEL(sc)) {
1415 /* There's a write enable bit here that reads as 1. */
1416 watchdogreg = CSR_READ_4(sc, DC_WATCHDOG);
1417 watchdogreg &= ~DC_WDOG_CTLWREN;
1418 watchdogreg |= DC_WDOG_JABBERDIS;
1419 CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg);
1421 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS);
1423 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS |
1424 DC_NETCFG_PORTSEL | DC_NETCFG_SCRAMBLER));
1425 if (sc->dc_type == DC_TYPE_98713)
1426 DC_SETBIT(sc, DC_NETCFG, (DC_NETCFG_PCS |
1427 DC_NETCFG_SCRAMBLER));
1428 if (!DC_IS_DAVICOM(sc))
1429 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
1430 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF);
1431 if (DC_IS_INTEL(sc))
1432 dc_apply_fixup(sc, IFM_AUTO);
1434 if (DC_IS_PNIC(sc)) {
1435 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_SPEEDSEL);
1436 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP);
1437 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL);
1439 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
1440 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS);
1441 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER);
1442 if (DC_IS_INTEL(sc))
1444 (media & IFM_GMASK) == IFM_FDX ?
1445 IFM_100_TX | IFM_FDX : IFM_100_TX);
1449 if (IFM_SUBTYPE(media) == IFM_10_T) {
1450 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL);
1451 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT);
1452 if (sc->dc_pmode == DC_PMODE_MII) {
1453 /* There's a write enable bit here that reads as 1. */
1454 if (DC_IS_INTEL(sc)) {
1455 watchdogreg = CSR_READ_4(sc, DC_WATCHDOG);
1456 watchdogreg &= ~DC_WDOG_CTLWREN;
1457 watchdogreg |= DC_WDOG_JABBERDIS;
1458 CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg);
1460 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS);
1462 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS |
1463 DC_NETCFG_PORTSEL | DC_NETCFG_SCRAMBLER));
1464 if (sc->dc_type == DC_TYPE_98713)
1465 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS);
1466 if (!DC_IS_DAVICOM(sc))
1467 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
1468 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF);
1469 if (DC_IS_INTEL(sc))
1470 dc_apply_fixup(sc, IFM_AUTO);
1472 if (DC_IS_PNIC(sc)) {
1473 DC_PN_GPIO_CLRBIT(sc, DC_PN_GPIO_SPEEDSEL);
1474 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP);
1475 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL);
1477 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
1478 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PCS);
1479 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER);
1480 if (DC_IS_INTEL(sc)) {
1481 DC_CLRBIT(sc, DC_SIARESET, DC_SIA_RESET);
1482 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF);
1483 if ((media & IFM_GMASK) == IFM_FDX)
1484 DC_SETBIT(sc, DC_10BTCTRL, 0x7F3D);
1486 DC_SETBIT(sc, DC_10BTCTRL, 0x7F3F);
1487 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET);
1488 DC_CLRBIT(sc, DC_10BTCTRL,
1489 DC_TCTL_AUTONEGENBL);
1491 (media & IFM_GMASK) == IFM_FDX ?
1492 IFM_10_T | IFM_FDX : IFM_10_T);
1499 * If this is a Davicom DM9102A card with a DM9801 HomePNA
1500 * PHY and we want HomePNA mode, set the portsel bit to turn
1501 * on the external MII port.
1503 if (DC_IS_DAVICOM(sc)) {
1504 if (IFM_SUBTYPE(media) == IFM_HPNA_1) {
1505 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
1508 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
1512 if ((media & IFM_GMASK) == IFM_FDX) {
1513 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX);
1514 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc))
1515 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX);
1517 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX);
1518 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc))
1519 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX);
1523 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON | DC_NETCFG_RX_ON);
1527 dc_reset(struct dc_softc *sc)
1531 DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET);
1533 for (i = 0; i < DC_TIMEOUT; i++) {
1535 if (!(CSR_READ_4(sc, DC_BUSCTL) & DC_BUSCTL_RESET))
1539 if (DC_IS_ASIX(sc) || DC_IS_ADMTEK(sc) || DC_IS_CONEXANT(sc) ||
1540 DC_IS_XIRCOM(sc) || DC_IS_INTEL(sc)) {
1542 DC_CLRBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET);
1546 if (i == DC_TIMEOUT)
1547 device_printf(sc->dc_dev, "reset never completed!\n");
1549 /* Wait a little while for the chip to get its brains in order. */
1552 CSR_WRITE_4(sc, DC_IMR, 0x00000000);
1553 CSR_WRITE_4(sc, DC_BUSCTL, 0x00000000);
1554 CSR_WRITE_4(sc, DC_NETCFG, 0x00000000);
1557 * Bring the SIA out of reset. In some cases, it looks
1558 * like failing to unreset the SIA soon enough gets it
1559 * into a state where it will never come out of reset
1560 * until we reset the whole chip again.
1562 if (DC_IS_INTEL(sc)) {
1563 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET);
1564 CSR_WRITE_4(sc, DC_10BTCTRL, 0);
1565 CSR_WRITE_4(sc, DC_WATCHDOG, 0);
1569 static const struct dc_type *
1570 dc_devtype(device_t dev)
1572 const struct dc_type *t;
1577 devid = pci_get_devid(dev);
1578 rev = pci_get_revid(dev);
1580 while (t->dc_name != NULL) {
1581 if (devid == t->dc_devid && rev >= t->dc_minrev)
1590 * Probe for a 21143 or clone chip. Check the PCI vendor and device
1591 * IDs against our list and return a device name if we find a match.
1592 * We do a little bit of extra work to identify the exact type of
1593 * chip. The MX98713 and MX98713A have the same PCI vendor/device ID,
1594 * but different revision IDs. The same is true for 98715/98715A
1595 * chips and the 98725, as well as the ASIX and ADMtek chips. In some
1596 * cases, the exact chip revision affects driver behavior.
1599 dc_probe(device_t dev)
1601 const struct dc_type *t;
1603 t = dc_devtype(dev);
1606 device_set_desc(dev, t->dc_name);
1607 return (BUS_PROBE_DEFAULT);
1614 dc_apply_fixup(struct dc_softc *sc, int media)
1616 struct dc_mediainfo *m;
1624 if (m->dc_media == media)
1632 for (i = 0, p = m->dc_reset_ptr; i < m->dc_reset_len; i++, p += 2) {
1633 reg = (p[0] | (p[1] << 8)) << 16;
1634 CSR_WRITE_4(sc, DC_WATCHDOG, reg);
1637 for (i = 0, p = m->dc_gp_ptr; i < m->dc_gp_len; i++, p += 2) {
1638 reg = (p[0] | (p[1] << 8)) << 16;
1639 CSR_WRITE_4(sc, DC_WATCHDOG, reg);
1644 dc_decode_leaf_sia(struct dc_softc *sc, struct dc_eblock_sia *l)
1646 struct dc_mediainfo *m;
1648 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT | M_ZERO);
1649 switch (l->dc_sia_code & ~DC_SIA_CODE_EXT) {
1650 case DC_SIA_CODE_10BT:
1651 m->dc_media = IFM_10_T;
1653 case DC_SIA_CODE_10BT_FDX:
1654 m->dc_media = IFM_10_T | IFM_FDX;
1656 case DC_SIA_CODE_10B2:
1657 m->dc_media = IFM_10_2;
1659 case DC_SIA_CODE_10B5:
1660 m->dc_media = IFM_10_5;
1667 * We need to ignore CSR13, CSR14, CSR15 for SIA mode.
1668 * Things apparently already work for cards that do
1669 * supply Media Specific Data.
1671 if (l->dc_sia_code & DC_SIA_CODE_EXT) {
1674 (u_int8_t *)&l->dc_un.dc_sia_ext.dc_sia_gpio_ctl;
1678 (u_int8_t *)&l->dc_un.dc_sia_noext.dc_sia_gpio_ctl;
1681 m->dc_next = sc->dc_mi;
1684 sc->dc_pmode = DC_PMODE_SIA;
1688 dc_decode_leaf_sym(struct dc_softc *sc, struct dc_eblock_sym *l)
1690 struct dc_mediainfo *m;
1692 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT | M_ZERO);
1693 if (l->dc_sym_code == DC_SYM_CODE_100BT)
1694 m->dc_media = IFM_100_TX;
1696 if (l->dc_sym_code == DC_SYM_CODE_100BT_FDX)
1697 m->dc_media = IFM_100_TX | IFM_FDX;
1700 m->dc_gp_ptr = (u_int8_t *)&l->dc_sym_gpio_ctl;
1702 m->dc_next = sc->dc_mi;
1705 sc->dc_pmode = DC_PMODE_SYM;
1709 dc_decode_leaf_mii(struct dc_softc *sc, struct dc_eblock_mii *l)
1711 struct dc_mediainfo *m;
1714 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT | M_ZERO);
1715 /* We abuse IFM_AUTO to represent MII. */
1716 m->dc_media = IFM_AUTO;
1717 m->dc_gp_len = l->dc_gpr_len;
1720 p += sizeof(struct dc_eblock_mii);
1722 p += 2 * l->dc_gpr_len;
1723 m->dc_reset_len = *p;
1725 m->dc_reset_ptr = p;
1727 m->dc_next = sc->dc_mi;
1732 dc_read_srom(struct dc_softc *sc, int bits)
1737 sc->dc_srom = malloc(size, M_DEVBUF, M_NOWAIT);
1738 dc_read_eeprom(sc, (caddr_t)sc->dc_srom, 0, (size / 2), 0);
1742 dc_parse_21143_srom(struct dc_softc *sc)
1744 struct dc_leaf_hdr *lhdr;
1745 struct dc_eblock_hdr *hdr;
1746 int have_mii, i, loff;
1750 loff = sc->dc_srom[27];
1751 lhdr = (struct dc_leaf_hdr *)&(sc->dc_srom[loff]);
1754 ptr += sizeof(struct dc_leaf_hdr) - 1;
1756 * Look if we got a MII media block.
1758 for (i = 0; i < lhdr->dc_mcnt; i++) {
1759 hdr = (struct dc_eblock_hdr *)ptr;
1760 if (hdr->dc_type == DC_EBLOCK_MII)
1763 ptr += (hdr->dc_len & 0x7F);
1768 * Do the same thing again. Only use SIA and SYM media
1769 * blocks if no MII media block is available.
1772 ptr += sizeof(struct dc_leaf_hdr) - 1;
1773 for (i = 0; i < lhdr->dc_mcnt; i++) {
1774 hdr = (struct dc_eblock_hdr *)ptr;
1775 switch (hdr->dc_type) {
1777 dc_decode_leaf_mii(sc, (struct dc_eblock_mii *)hdr);
1781 dc_decode_leaf_sia(sc,
1782 (struct dc_eblock_sia *)hdr);
1786 dc_decode_leaf_sym(sc,
1787 (struct dc_eblock_sym *)hdr);
1790 /* Don't care. Yet. */
1793 ptr += (hdr->dc_len & 0x7F);
1799 dc_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
1804 ("%s: wrong number of segments (%d)", __func__, nseg));
1806 *paddr = segs->ds_addr;
1810 * Attach the interface. Allocate softc structures, do ifmedia
1811 * setup and ethernet/BPF attach.
1814 dc_attach(device_t dev)
1817 uint32_t eaddr[(ETHER_ADDR_LEN+3)/4];
1819 struct dc_softc *sc;
1821 u_int32_t reg, revision;
1822 int error = 0, rid, mac_offset;
1826 sc = device_get_softc(dev);
1829 mtx_init(&sc->dc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
1833 * Map control/status registers.
1835 pci_enable_busmaster(dev);
1838 sc->dc_res = bus_alloc_resource_any(dev, DC_RES, &rid, RF_ACTIVE);
1840 if (sc->dc_res == NULL) {
1841 device_printf(dev, "couldn't map ports/memory\n");
1846 sc->dc_btag = rman_get_bustag(sc->dc_res);
1847 sc->dc_bhandle = rman_get_bushandle(sc->dc_res);
1849 /* Allocate interrupt. */
1851 sc->dc_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
1852 RF_SHAREABLE | RF_ACTIVE);
1854 if (sc->dc_irq == NULL) {
1855 device_printf(dev, "couldn't map interrupt\n");
1860 /* Need this info to decide on a chip type. */
1861 sc->dc_info = dc_devtype(dev);
1862 revision = pci_get_revid(dev);
1864 /* Get the eeprom width, but PNIC and XIRCOM have diff eeprom */
1865 if (sc->dc_info->dc_devid !=
1866 DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C168) &&
1867 sc->dc_info->dc_devid !=
1868 DC_DEVID(DC_VENDORID_XIRCOM, DC_DEVICEID_X3201))
1869 dc_eeprom_width(sc);
1871 switch (sc->dc_info->dc_devid) {
1872 case DC_DEVID(DC_VENDORID_DEC, DC_DEVICEID_21143):
1873 sc->dc_type = DC_TYPE_21143;
1874 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR;
1875 sc->dc_flags |= DC_REDUCED_MII_POLL;
1876 /* Save EEPROM contents so we can parse them later. */
1877 dc_read_srom(sc, sc->dc_romwidth);
1879 case DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9009):
1880 case DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9100):
1881 case DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102):
1882 sc->dc_type = DC_TYPE_DM9102;
1883 sc->dc_flags |= DC_TX_COALESCE | DC_TX_INTR_ALWAYS;
1884 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_TX_STORENFWD;
1885 sc->dc_flags |= DC_TX_ALIGN;
1886 sc->dc_pmode = DC_PMODE_MII;
1888 /* Increase the latency timer value. */
1889 pci_write_config(dev, PCIR_LATTIMER, 0x80, 1);
1891 case DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_AL981):
1892 sc->dc_type = DC_TYPE_AL981;
1893 sc->dc_flags |= DC_TX_USE_TX_INTR;
1894 sc->dc_flags |= DC_TX_ADMTEK_WAR;
1895 sc->dc_pmode = DC_PMODE_MII;
1896 dc_read_srom(sc, sc->dc_romwidth);
1898 case DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_AN985):
1899 case DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9511):
1900 case DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9513):
1901 case DC_DEVID(DC_VENDORID_DLINK, DC_DEVICEID_DRP32TXD):
1902 case DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_FA511):
1903 case DC_DEVID(DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500):
1904 case DC_DEVID(DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500MX):
1905 case DC_DEVID(DC_VENDORID_ACCTON, DC_DEVICEID_EN2242):
1906 case DC_DEVID(DC_VENDORID_HAWKING, DC_DEVICEID_HAWKING_PN672TX):
1907 case DC_DEVID(DC_VENDORID_PLANEX, DC_DEVICEID_FNW3602T):
1908 case DC_DEVID(DC_VENDORID_3COM, DC_DEVICEID_3CSOHOB):
1909 case DC_DEVID(DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN120):
1910 case DC_DEVID(DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN130):
1911 case DC_DEVID(DC_VENDORID_LINKSYS, DC_DEVICEID_PCMPC200_AB08):
1912 case DC_DEVID(DC_VENDORID_LINKSYS, DC_DEVICEID_PCMPC200_AB09):
1913 sc->dc_type = DC_TYPE_AN985;
1914 sc->dc_flags |= DC_64BIT_HASH;
1915 sc->dc_flags |= DC_TX_USE_TX_INTR;
1916 sc->dc_flags |= DC_TX_ADMTEK_WAR;
1917 sc->dc_pmode = DC_PMODE_MII;
1918 /* Don't read SROM for - auto-loaded on reset */
1920 case DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_98713):
1921 case DC_DEVID(DC_VENDORID_CP, DC_DEVICEID_98713_CP):
1922 if (revision < DC_REVISION_98713A) {
1923 sc->dc_type = DC_TYPE_98713;
1925 if (revision >= DC_REVISION_98713A) {
1926 sc->dc_type = DC_TYPE_98713A;
1927 sc->dc_flags |= DC_21143_NWAY;
1929 sc->dc_flags |= DC_REDUCED_MII_POLL;
1930 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR;
1932 case DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_987x5):
1933 case DC_DEVID(DC_VENDORID_ACCTON, DC_DEVICEID_EN1217):
1935 * Macronix MX98715AEC-C/D/E parts have only a
1936 * 128-bit hash table. We need to deal with these
1937 * in the same manner as the PNIC II so that we
1938 * get the right number of bits out of the
1941 if (revision >= DC_REVISION_98715AEC_C &&
1942 revision < DC_REVISION_98725)
1943 sc->dc_flags |= DC_128BIT_HASH;
1944 sc->dc_type = DC_TYPE_987x5;
1945 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR;
1946 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_21143_NWAY;
1948 case DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_98727):
1949 sc->dc_type = DC_TYPE_987x5;
1950 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR;
1951 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_21143_NWAY;
1953 case DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C115):
1954 sc->dc_type = DC_TYPE_PNICII;
1955 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR | DC_128BIT_HASH;
1956 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_21143_NWAY;
1958 case DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C168):
1959 sc->dc_type = DC_TYPE_PNIC;
1960 sc->dc_flags |= DC_TX_STORENFWD | DC_TX_INTR_ALWAYS;
1961 sc->dc_flags |= DC_PNIC_RX_BUG_WAR;
1962 sc->dc_pnic_rx_buf = malloc(DC_RXLEN * 5, M_DEVBUF, M_NOWAIT);
1963 if (revision < DC_REVISION_82C169)
1964 sc->dc_pmode = DC_PMODE_SYM;
1966 case DC_DEVID(DC_VENDORID_ASIX, DC_DEVICEID_AX88140A):
1967 sc->dc_type = DC_TYPE_ASIX;
1968 sc->dc_flags |= DC_TX_USE_TX_INTR | DC_TX_INTR_FIRSTFRAG;
1969 sc->dc_flags |= DC_REDUCED_MII_POLL;
1970 sc->dc_pmode = DC_PMODE_MII;
1972 case DC_DEVID(DC_VENDORID_XIRCOM, DC_DEVICEID_X3201):
1973 sc->dc_type = DC_TYPE_XIRCOM;
1974 sc->dc_flags |= DC_TX_INTR_ALWAYS | DC_TX_COALESCE |
1977 * We don't actually need to coalesce, but we're doing
1978 * it to obtain a double word aligned buffer.
1979 * The DC_TX_COALESCE flag is required.
1981 sc->dc_pmode = DC_PMODE_MII;
1983 case DC_DEVID(DC_VENDORID_CONEXANT, DC_DEVICEID_RS7112):
1984 sc->dc_type = DC_TYPE_CONEXANT;
1985 sc->dc_flags |= DC_TX_INTR_ALWAYS;
1986 sc->dc_flags |= DC_REDUCED_MII_POLL;
1987 sc->dc_pmode = DC_PMODE_MII;
1988 dc_read_srom(sc, sc->dc_romwidth);
1991 device_printf(dev, "unknown device: %x\n",
1992 sc->dc_info->dc_devid);
1996 /* Save the cache line size. */
1997 if (DC_IS_DAVICOM(sc))
1998 sc->dc_cachesize = 0;
2000 sc->dc_cachesize = pci_get_cachelnsz(dev);
2002 /* Reset the adapter. */
2005 /* Take 21143 out of snooze mode */
2006 if (DC_IS_INTEL(sc) || DC_IS_XIRCOM(sc)) {
2007 command = pci_read_config(dev, DC_PCI_CFDD, 4);
2008 command &= ~(DC_CFDD_SNOOZE_MODE | DC_CFDD_SLEEP_MODE);
2009 pci_write_config(dev, DC_PCI_CFDD, command, 4);
2013 * Try to learn something about the supported media.
2014 * We know that ASIX and ADMtek and Davicom devices
2015 * will *always* be using MII media, so that's a no-brainer.
2016 * The tricky ones are the Macronix/PNIC II and the
2019 if (DC_IS_INTEL(sc))
2020 dc_parse_21143_srom(sc);
2021 else if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) {
2022 if (sc->dc_type == DC_TYPE_98713)
2023 sc->dc_pmode = DC_PMODE_MII;
2025 sc->dc_pmode = DC_PMODE_SYM;
2026 } else if (!sc->dc_pmode)
2027 sc->dc_pmode = DC_PMODE_MII;
2030 * Get station address from the EEPROM.
2032 switch(sc->dc_type) {
2034 case DC_TYPE_98713A:
2036 case DC_TYPE_PNICII:
2037 dc_read_eeprom(sc, (caddr_t)&mac_offset,
2038 (DC_EE_NODEADDR_OFFSET / 2), 1, 0);
2039 dc_read_eeprom(sc, (caddr_t)&eaddr, (mac_offset / 2), 3, 0);
2042 dc_read_eeprom(sc, (caddr_t)&eaddr, 0, 3, 1);
2044 case DC_TYPE_DM9102:
2045 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0);
2048 * If this is an onboard dc(4) the station address read from
2049 * the EEPROM is all zero and we have to get it from the FCode.
2051 if (eaddr[0] == 0 && (eaddr[1] & ~0xffff) == 0)
2052 OF_getetheraddr(dev, (caddr_t)&eaddr);
2057 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0);
2061 reg = CSR_READ_4(sc, DC_AL_PAR0);
2062 mac = (uint8_t *)&eaddr[0];
2063 mac[0] = (reg >> 0) & 0xff;
2064 mac[1] = (reg >> 8) & 0xff;
2065 mac[2] = (reg >> 16) & 0xff;
2066 mac[3] = (reg >> 24) & 0xff;
2067 reg = CSR_READ_4(sc, DC_AL_PAR1);
2068 mac[4] = (reg >> 0) & 0xff;
2069 mac[5] = (reg >> 8) & 0xff;
2071 case DC_TYPE_CONEXANT:
2072 bcopy(sc->dc_srom + DC_CONEXANT_EE_NODEADDR, &eaddr,
2075 case DC_TYPE_XIRCOM:
2076 /* The MAC comes from the CIS. */
2077 mac = pci_get_ether(dev);
2079 device_printf(dev, "No station address in CIS!\n");
2083 bcopy(mac, eaddr, ETHER_ADDR_LEN);
2086 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0);
2090 /* Allocate a busdma tag and DMA safe memory for TX/RX descriptors. */
2091 error = bus_dma_tag_create(bus_get_dma_tag(dev), PAGE_SIZE, 0,
2092 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
2093 sizeof(struct dc_list_data), 1, sizeof(struct dc_list_data),
2094 0, NULL, NULL, &sc->dc_ltag);
2096 device_printf(dev, "failed to allocate busdma tag\n");
2100 error = bus_dmamem_alloc(sc->dc_ltag, (void **)&sc->dc_ldata,
2101 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->dc_lmap);
2103 device_printf(dev, "failed to allocate DMA safe memory\n");
2107 error = bus_dmamap_load(sc->dc_ltag, sc->dc_lmap, sc->dc_ldata,
2108 sizeof(struct dc_list_data), dc_dma_map_addr, &sc->dc_laddr,
2111 device_printf(dev, "cannot get address of the descriptors\n");
2117 * Allocate a busdma tag and DMA safe memory for the multicast
2120 error = bus_dma_tag_create(bus_get_dma_tag(dev), PAGE_SIZE, 0,
2121 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
2122 DC_SFRAME_LEN + DC_MIN_FRAMELEN, 1, DC_SFRAME_LEN + DC_MIN_FRAMELEN,
2123 0, NULL, NULL, &sc->dc_stag);
2125 device_printf(dev, "failed to allocate busdma tag\n");
2129 error = bus_dmamem_alloc(sc->dc_stag, (void **)&sc->dc_cdata.dc_sbuf,
2130 BUS_DMA_NOWAIT, &sc->dc_smap);
2132 device_printf(dev, "failed to allocate DMA safe memory\n");
2136 error = bus_dmamap_load(sc->dc_stag, sc->dc_smap, sc->dc_cdata.dc_sbuf,
2137 DC_SFRAME_LEN, dc_dma_map_addr, &sc->dc_saddr, BUS_DMA_NOWAIT);
2139 device_printf(dev, "cannot get address of the descriptors\n");
2144 /* Allocate a busdma tag for mbufs. */
2145 error = bus_dma_tag_create(bus_get_dma_tag(dev), 1, 0,
2146 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
2147 MCLBYTES * DC_MAXFRAGS, DC_MAXFRAGS, MCLBYTES,
2148 0, NULL, NULL, &sc->dc_mtag);
2150 device_printf(dev, "failed to allocate busdma tag\n");
2155 /* Create the TX/RX busdma maps. */
2156 for (i = 0; i < DC_TX_LIST_CNT; i++) {
2157 error = bus_dmamap_create(sc->dc_mtag, 0,
2158 &sc->dc_cdata.dc_tx_map[i]);
2160 device_printf(dev, "failed to init TX ring\n");
2165 for (i = 0; i < DC_RX_LIST_CNT; i++) {
2166 error = bus_dmamap_create(sc->dc_mtag, 0,
2167 &sc->dc_cdata.dc_rx_map[i]);
2169 device_printf(dev, "failed to init RX ring\n");
2174 error = bus_dmamap_create(sc->dc_mtag, 0, &sc->dc_sparemap);
2176 device_printf(dev, "failed to init RX ring\n");
2181 ifp = sc->dc_ifp = if_alloc(IFT_ETHER);
2183 device_printf(dev, "can not if_alloc()\n");
2188 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
2189 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
2190 ifp->if_ioctl = dc_ioctl;
2191 ifp->if_start = dc_start;
2192 ifp->if_init = dc_init;
2193 IFQ_SET_MAXLEN(&ifp->if_snd, DC_TX_LIST_CNT - 1);
2194 ifp->if_snd.ifq_drv_maxlen = DC_TX_LIST_CNT - 1;
2195 IFQ_SET_READY(&ifp->if_snd);
2198 * Do MII setup. If this is a 21143, check for a PHY on the
2199 * MII bus after applying any necessary fixups to twiddle the
2200 * GPIO bits. If we don't end up finding a PHY, restore the
2201 * old selection (SIA only or SIA/SYM) and attach the dcphy
2204 if (DC_IS_INTEL(sc)) {
2205 dc_apply_fixup(sc, IFM_AUTO);
2207 sc->dc_pmode = DC_PMODE_MII;
2211 * Setup General Purpose port mode and data so the tulip can talk
2212 * to the MII. This needs to be done before mii_phy_probe so that
2213 * we can actually see them.
2215 if (DC_IS_XIRCOM(sc)) {
2216 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_WRITE_EN | DC_SIAGP_INT1_EN |
2217 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT);
2219 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_INT1_EN |
2220 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT);
2224 error = mii_phy_probe(dev, &sc->dc_miibus,
2225 dc_ifmedia_upd, dc_ifmedia_sts);
2227 if (error && DC_IS_INTEL(sc)) {
2229 if (sc->dc_pmode != DC_PMODE_SIA)
2230 sc->dc_pmode = DC_PMODE_SYM;
2231 sc->dc_flags |= DC_21143_NWAY;
2232 mii_phy_probe(dev, &sc->dc_miibus,
2233 dc_ifmedia_upd, dc_ifmedia_sts);
2235 * For non-MII cards, we need to have the 21143
2236 * drive the LEDs. Except there are some systems
2237 * like the NEC VersaPro NoteBook PC which have no
2238 * LEDs, and twiddling these bits has adverse effects
2239 * on them. (I.e. you suddenly can't get a link.)
2241 if (!(pci_get_subvendor(dev) == 0x1033 &&
2242 pci_get_subdevice(dev) == 0x8028))
2243 sc->dc_flags |= DC_TULIP_LEDS;
2248 device_printf(dev, "MII without any PHY!\n");
2252 if (DC_IS_ADMTEK(sc)) {
2254 * Set automatic TX underrun recovery for the ADMtek chips
2256 DC_SETBIT(sc, DC_AL_CR, DC_AL_CR_ATUR);
2260 * Tell the upper layer(s) we support long frames.
2262 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
2263 ifp->if_capabilities |= IFCAP_VLAN_MTU;
2264 ifp->if_capenable = ifp->if_capabilities;
2265 #ifdef DEVICE_POLLING
2266 ifp->if_capabilities |= IFCAP_POLLING;
2269 callout_init_mtx(&sc->dc_stat_ch, &sc->dc_mtx, 0);
2270 callout_init_mtx(&sc->dc_wdog_ch, &sc->dc_mtx, 0);
2273 * Call MI attach routine.
2275 ether_ifattach(ifp, (caddr_t)eaddr);
2277 /* Hook interrupt last to avoid having to lock softc */
2278 error = bus_setup_intr(dev, sc->dc_irq, INTR_TYPE_NET | INTR_MPSAFE,
2279 NULL, dc_intr, sc, &sc->dc_intrhand);
2282 device_printf(dev, "couldn't set up irq\n");
2283 ether_ifdetach(ifp);
2294 * Shutdown hardware and free up resources. This can be called any
2295 * time after the mutex has been initialized. It is called in both
2296 * the error case in attach and the normal detach case so it needs
2297 * to be careful about only freeing resources that have actually been
2301 dc_detach(device_t dev)
2303 struct dc_softc *sc;
2305 struct dc_mediainfo *m;
2308 sc = device_get_softc(dev);
2309 KASSERT(mtx_initialized(&sc->dc_mtx), ("dc mutex not initialized"));
2313 #ifdef DEVICE_POLLING
2314 if (ifp->if_capenable & IFCAP_POLLING)
2315 ether_poll_deregister(ifp);
2318 /* These should only be active if attach succeeded */
2319 if (device_is_attached(dev)) {
2323 callout_drain(&sc->dc_stat_ch);
2324 callout_drain(&sc->dc_wdog_ch);
2325 ether_ifdetach(ifp);
2328 device_delete_child(dev, sc->dc_miibus);
2329 bus_generic_detach(dev);
2331 if (sc->dc_intrhand)
2332 bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand);
2334 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq);
2336 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res);
2341 if (sc->dc_cdata.dc_sbuf != NULL)
2342 bus_dmamem_free(sc->dc_stag, sc->dc_cdata.dc_sbuf, sc->dc_smap);
2343 if (sc->dc_ldata != NULL)
2344 bus_dmamem_free(sc->dc_ltag, sc->dc_ldata, sc->dc_lmap);
2346 for (i = 0; i < DC_TX_LIST_CNT; i++)
2347 if (sc->dc_cdata.dc_tx_map[i] != NULL)
2348 bus_dmamap_destroy(sc->dc_mtag,
2349 sc->dc_cdata.dc_tx_map[i]);
2350 for (i = 0; i < DC_RX_LIST_CNT; i++)
2351 if (sc->dc_cdata.dc_rx_map[i] != NULL)
2352 bus_dmamap_destroy(sc->dc_mtag,
2353 sc->dc_cdata.dc_rx_map[i]);
2354 bus_dmamap_destroy(sc->dc_mtag, sc->dc_sparemap);
2357 bus_dma_tag_destroy(sc->dc_stag);
2359 bus_dma_tag_destroy(sc->dc_mtag);
2361 bus_dma_tag_destroy(sc->dc_ltag);
2363 free(sc->dc_pnic_rx_buf, M_DEVBUF);
2365 while (sc->dc_mi != NULL) {
2366 m = sc->dc_mi->dc_next;
2367 free(sc->dc_mi, M_DEVBUF);
2370 free(sc->dc_srom, M_DEVBUF);
2372 mtx_destroy(&sc->dc_mtx);
2378 * Initialize the transmit descriptors.
2381 dc_list_tx_init(struct dc_softc *sc)
2383 struct dc_chain_data *cd;
2384 struct dc_list_data *ld;
2389 for (i = 0; i < DC_TX_LIST_CNT; i++) {
2390 if (i == DC_TX_LIST_CNT - 1)
2394 ld->dc_tx_list[i].dc_next = htole32(DC_TXDESC(sc, nexti));
2395 cd->dc_tx_chain[i] = NULL;
2396 ld->dc_tx_list[i].dc_data = 0;
2397 ld->dc_tx_list[i].dc_ctl = 0;
2400 cd->dc_tx_prod = cd->dc_tx_cons = cd->dc_tx_cnt = 0;
2401 bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap,
2402 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2408 * Initialize the RX descriptors and allocate mbufs for them. Note that
2409 * we arrange the descriptors in a closed ring, so that the last descriptor
2410 * points back to the first.
2413 dc_list_rx_init(struct dc_softc *sc)
2415 struct dc_chain_data *cd;
2416 struct dc_list_data *ld;
2422 for (i = 0; i < DC_RX_LIST_CNT; i++) {
2423 if (dc_newbuf(sc, i, 1) != 0)
2425 if (i == DC_RX_LIST_CNT - 1)
2429 ld->dc_rx_list[i].dc_next = htole32(DC_RXDESC(sc, nexti));
2433 bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap,
2434 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2439 * Initialize an RX descriptor and attach an MBUF cluster.
2442 dc_newbuf(struct dc_softc *sc, int i, int alloc)
2446 bus_dma_segment_t segs[1];
2450 m_new = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
2454 m_new = sc->dc_cdata.dc_rx_chain[i];
2455 m_new->m_data = m_new->m_ext.ext_buf;
2457 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
2458 m_adj(m_new, sizeof(u_int64_t));
2461 * If this is a PNIC chip, zero the buffer. This is part
2462 * of the workaround for the receive bug in the 82c168 and
2465 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR)
2466 bzero(mtod(m_new, char *), m_new->m_len);
2468 /* No need to remap the mbuf if we're reusing it. */
2470 error = bus_dmamap_load_mbuf_sg(sc->dc_mtag, sc->dc_sparemap,
2471 m_new, segs, &nseg, 0);
2477 ("%s: wrong number of segments (%d)", __func__, nseg));
2478 sc->dc_ldata->dc_rx_list[i].dc_data = htole32(segs->ds_addr);
2479 bus_dmamap_unload(sc->dc_mtag, sc->dc_cdata.dc_rx_map[i]);
2480 tmp = sc->dc_cdata.dc_rx_map[i];
2481 sc->dc_cdata.dc_rx_map[i] = sc->dc_sparemap;
2482 sc->dc_sparemap = tmp;
2483 sc->dc_cdata.dc_rx_chain[i] = m_new;
2486 sc->dc_ldata->dc_rx_list[i].dc_ctl = htole32(DC_RXCTL_RLINK | DC_RXLEN);
2487 sc->dc_ldata->dc_rx_list[i].dc_status = htole32(DC_RXSTAT_OWN);
2488 bus_dmamap_sync(sc->dc_mtag, sc->dc_cdata.dc_rx_map[i],
2489 BUS_DMASYNC_PREREAD);
2490 bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap,
2491 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2497 * The PNIC chip has a terrible bug in it that manifests itself during
2498 * periods of heavy activity. The exact mode of failure if difficult to
2499 * pinpoint: sometimes it only happens in promiscuous mode, sometimes it
2500 * will happen on slow machines. The bug is that sometimes instead of
2501 * uploading one complete frame during reception, it uploads what looks
2502 * like the entire contents of its FIFO memory. The frame we want is at
2503 * the end of the whole mess, but we never know exactly how much data has
2504 * been uploaded, so salvaging the frame is hard.
2506 * There is only one way to do it reliably, and it's disgusting.
2507 * Here's what we know:
2509 * - We know there will always be somewhere between one and three extra
2510 * descriptors uploaded.
2512 * - We know the desired received frame will always be at the end of the
2513 * total data upload.
2515 * - We know the size of the desired received frame because it will be
2516 * provided in the length field of the status word in the last descriptor.
2518 * Here's what we do:
2520 * - When we allocate buffers for the receive ring, we bzero() them.
2521 * This means that we know that the buffer contents should be all
2522 * zeros, except for data uploaded by the chip.
2524 * - We also force the PNIC chip to upload frames that include the
2525 * ethernet CRC at the end.
2527 * - We gather all of the bogus frame data into a single buffer.
2529 * - We then position a pointer at the end of this buffer and scan
2530 * backwards until we encounter the first non-zero byte of data.
2531 * This is the end of the received frame. We know we will encounter
2532 * some data at the end of the frame because the CRC will always be
2533 * there, so even if the sender transmits a packet of all zeros,
2534 * we won't be fooled.
2536 * - We know the size of the actual received frame, so we subtract
2537 * that value from the current pointer location. This brings us
2538 * to the start of the actual received packet.
2540 * - We copy this into an mbuf and pass it on, along with the actual
2543 * The performance hit is tremendous, but it beats dropping frames all
2547 #define DC_WHOLEFRAME (DC_RXSTAT_FIRSTFRAG | DC_RXSTAT_LASTFRAG)
2549 dc_pnic_rx_bug_war(struct dc_softc *sc, int idx)
2551 struct dc_desc *cur_rx;
2552 struct dc_desc *c = NULL;
2553 struct mbuf *m = NULL;
2556 u_int32_t rxstat = 0;
2558 i = sc->dc_pnic_rx_bug_save;
2559 cur_rx = &sc->dc_ldata->dc_rx_list[idx];
2560 ptr = sc->dc_pnic_rx_buf;
2561 bzero(ptr, DC_RXLEN * 5);
2563 /* Copy all the bytes from the bogus buffers. */
2565 c = &sc->dc_ldata->dc_rx_list[i];
2566 rxstat = le32toh(c->dc_status);
2567 m = sc->dc_cdata.dc_rx_chain[i];
2568 bcopy(mtod(m, char *), ptr, DC_RXLEN);
2570 /* If this is the last buffer, break out. */
2571 if (i == idx || rxstat & DC_RXSTAT_LASTFRAG)
2573 dc_newbuf(sc, i, 0);
2574 DC_INC(i, DC_RX_LIST_CNT);
2577 /* Find the length of the actual receive frame. */
2578 total_len = DC_RXBYTES(rxstat);
2580 /* Scan backwards until we hit a non-zero byte. */
2581 while (*ptr == 0x00)
2585 if ((uintptr_t)(ptr) & 0x3)
2588 /* Now find the start of the frame. */
2590 if (ptr < sc->dc_pnic_rx_buf)
2591 ptr = sc->dc_pnic_rx_buf;
2594 * Now copy the salvaged frame to the last mbuf and fake up
2595 * the status word to make it look like a successful
2598 dc_newbuf(sc, i, 0);
2599 bcopy(ptr, mtod(m, char *), total_len);
2600 cur_rx->dc_status = htole32(rxstat | DC_RXSTAT_FIRSTFRAG);
2604 * This routine searches the RX ring for dirty descriptors in the
2605 * event that the rxeof routine falls out of sync with the chip's
2606 * current descriptor pointer. This may happen sometimes as a result
2607 * of a "no RX buffer available" condition that happens when the chip
2608 * consumes all of the RX buffers before the driver has a chance to
2609 * process the RX ring. This routine may need to be called more than
2610 * once to bring the driver back in sync with the chip, however we
2611 * should still be getting RX DONE interrupts to drive the search
2612 * for new packets in the RX ring, so we should catch up eventually.
2615 dc_rx_resync(struct dc_softc *sc)
2617 struct dc_desc *cur_rx;
2620 pos = sc->dc_cdata.dc_rx_prod;
2622 for (i = 0; i < DC_RX_LIST_CNT; i++) {
2623 cur_rx = &sc->dc_ldata->dc_rx_list[pos];
2624 if (!(le32toh(cur_rx->dc_status) & DC_RXSTAT_OWN))
2626 DC_INC(pos, DC_RX_LIST_CNT);
2629 /* If the ring really is empty, then just return. */
2630 if (i == DC_RX_LIST_CNT)
2633 /* We've fallen behing the chip: catch it. */
2634 sc->dc_cdata.dc_rx_prod = pos;
2640 * A frame has been uploaded: pass the resulting mbuf chain up to
2641 * the higher level protocols.
2644 dc_rxeof(struct dc_softc *sc)
2646 struct mbuf *m, *m0;
2648 struct dc_desc *cur_rx;
2649 int i, total_len, rx_npkts;
2655 i = sc->dc_cdata.dc_rx_prod;
2659 bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, BUS_DMASYNC_POSTREAD);
2660 while (!(le32toh(sc->dc_ldata->dc_rx_list[i].dc_status) &
2662 #ifdef DEVICE_POLLING
2663 if (ifp->if_capenable & IFCAP_POLLING) {
2664 if (sc->rxcycles <= 0)
2669 cur_rx = &sc->dc_ldata->dc_rx_list[i];
2670 rxstat = le32toh(cur_rx->dc_status);
2671 m = sc->dc_cdata.dc_rx_chain[i];
2672 bus_dmamap_sync(sc->dc_mtag, sc->dc_cdata.dc_rx_map[i],
2673 BUS_DMASYNC_POSTREAD);
2674 total_len = DC_RXBYTES(rxstat);
2676 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) {
2677 if ((rxstat & DC_WHOLEFRAME) != DC_WHOLEFRAME) {
2678 if (rxstat & DC_RXSTAT_FIRSTFRAG)
2679 sc->dc_pnic_rx_bug_save = i;
2680 if ((rxstat & DC_RXSTAT_LASTFRAG) == 0) {
2681 DC_INC(i, DC_RX_LIST_CNT);
2684 dc_pnic_rx_bug_war(sc, i);
2685 rxstat = le32toh(cur_rx->dc_status);
2686 total_len = DC_RXBYTES(rxstat);
2691 * If an error occurs, update stats, clear the
2692 * status word and leave the mbuf cluster in place:
2693 * it should simply get re-used next time this descriptor
2694 * comes up in the ring. However, don't report long
2695 * frames as errors since they could be vlans.
2697 if ((rxstat & DC_RXSTAT_RXERR)) {
2698 if (!(rxstat & DC_RXSTAT_GIANT) ||
2699 (rxstat & (DC_RXSTAT_CRCERR | DC_RXSTAT_DRIBBLE |
2700 DC_RXSTAT_MIIERE | DC_RXSTAT_COLLSEEN |
2701 DC_RXSTAT_RUNT | DC_RXSTAT_DE))) {
2703 if (rxstat & DC_RXSTAT_COLLSEEN)
2704 ifp->if_collisions++;
2705 dc_newbuf(sc, i, 0);
2706 if (rxstat & DC_RXSTAT_CRCERR) {
2707 DC_INC(i, DC_RX_LIST_CNT);
2716 /* No errors; receive the packet. */
2717 total_len -= ETHER_CRC_LEN;
2718 #ifdef __NO_STRICT_ALIGNMENT
2720 * On architectures without alignment problems we try to
2721 * allocate a new buffer for the receive ring, and pass up
2722 * the one where the packet is already, saving the expensive
2723 * copy done in m_devget().
2724 * If we are on an architecture with alignment problems, or
2725 * if the allocation fails, then use m_devget and leave the
2726 * existing buffer in the receive ring.
2728 if (dc_newbuf(sc, i, 1) == 0) {
2729 m->m_pkthdr.rcvif = ifp;
2730 m->m_pkthdr.len = m->m_len = total_len;
2731 DC_INC(i, DC_RX_LIST_CNT);
2735 m0 = m_devget(mtod(m, char *), total_len,
2736 ETHER_ALIGN, ifp, NULL);
2737 dc_newbuf(sc, i, 0);
2738 DC_INC(i, DC_RX_LIST_CNT);
2748 (*ifp->if_input)(ifp, m);
2753 sc->dc_cdata.dc_rx_prod = i;
2758 * A frame was downloaded to the chip. It's safe for us to clean up
2762 dc_txeof(struct dc_softc *sc)
2764 struct dc_desc *cur_tx = NULL;
2767 u_int32_t ctl, txstat;
2772 * Go through our tx list and free mbufs for those
2773 * frames that have been transmitted.
2775 bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, BUS_DMASYNC_POSTREAD);
2776 idx = sc->dc_cdata.dc_tx_cons;
2777 while (idx != sc->dc_cdata.dc_tx_prod) {
2779 cur_tx = &sc->dc_ldata->dc_tx_list[idx];
2780 txstat = le32toh(cur_tx->dc_status);
2781 ctl = le32toh(cur_tx->dc_ctl);
2783 if (txstat & DC_TXSTAT_OWN)
2786 if (!(ctl & DC_TXCTL_LASTFRAG) || ctl & DC_TXCTL_SETUP) {
2787 if (ctl & DC_TXCTL_SETUP) {
2789 * Yes, the PNIC is so brain damaged
2790 * that it will sometimes generate a TX
2791 * underrun error while DMAing the RX
2792 * filter setup frame. If we detect this,
2793 * we have to send the setup frame again,
2794 * or else the filter won't be programmed
2797 if (DC_IS_PNIC(sc)) {
2798 if (txstat & DC_TXSTAT_ERRSUM)
2801 sc->dc_cdata.dc_tx_chain[idx] = NULL;
2803 sc->dc_cdata.dc_tx_cnt--;
2804 DC_INC(idx, DC_TX_LIST_CNT);
2808 if (DC_IS_XIRCOM(sc) || DC_IS_CONEXANT(sc)) {
2810 * XXX: Why does my Xircom taunt me so?
2811 * For some reason it likes setting the CARRLOST flag
2812 * even when the carrier is there. wtf?!?
2813 * Who knows, but Conexant chips have the
2814 * same problem. Maybe they took lessons
2817 if (/*sc->dc_type == DC_TYPE_21143 &&*/
2818 sc->dc_pmode == DC_PMODE_MII &&
2819 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM |
2820 DC_TXSTAT_NOCARRIER)))
2821 txstat &= ~DC_TXSTAT_ERRSUM;
2823 if (/*sc->dc_type == DC_TYPE_21143 &&*/
2824 sc->dc_pmode == DC_PMODE_MII &&
2825 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM |
2826 DC_TXSTAT_NOCARRIER | DC_TXSTAT_CARRLOST)))
2827 txstat &= ~DC_TXSTAT_ERRSUM;
2830 if (txstat & DC_TXSTAT_ERRSUM) {
2832 if (txstat & DC_TXSTAT_EXCESSCOLL)
2833 ifp->if_collisions++;
2834 if (txstat & DC_TXSTAT_LATECOLL)
2835 ifp->if_collisions++;
2836 if (!(txstat & DC_TXSTAT_UNDERRUN)) {
2842 ifp->if_collisions += (txstat & DC_TXSTAT_COLLCNT) >> 3;
2845 if (sc->dc_cdata.dc_tx_chain[idx] != NULL) {
2846 bus_dmamap_sync(sc->dc_mtag,
2847 sc->dc_cdata.dc_tx_map[idx],
2848 BUS_DMASYNC_POSTWRITE);
2849 bus_dmamap_unload(sc->dc_mtag,
2850 sc->dc_cdata.dc_tx_map[idx]);
2851 m_freem(sc->dc_cdata.dc_tx_chain[idx]);
2852 sc->dc_cdata.dc_tx_chain[idx] = NULL;
2855 sc->dc_cdata.dc_tx_cnt--;
2856 DC_INC(idx, DC_TX_LIST_CNT);
2858 sc->dc_cdata.dc_tx_cons = idx;
2860 if (DC_TX_LIST_CNT - sc->dc_cdata.dc_tx_cnt > DC_TX_LIST_RSVD)
2861 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2863 if (sc->dc_cdata.dc_tx_cnt == 0)
2864 sc->dc_wdog_timer = 0;
2870 struct dc_softc *sc;
2871 struct mii_data *mii;
2878 mii = device_get_softc(sc->dc_miibus);
2880 if (sc->dc_flags & DC_REDUCED_MII_POLL) {
2881 if (sc->dc_flags & DC_21143_NWAY) {
2882 r = CSR_READ_4(sc, DC_10BTSTAT);
2883 if (IFM_SUBTYPE(mii->mii_media_active) ==
2884 IFM_100_TX && (r & DC_TSTAT_LS100)) {
2888 if (IFM_SUBTYPE(mii->mii_media_active) ==
2889 IFM_10_T && (r & DC_TSTAT_LS10)) {
2893 if (sc->dc_link == 0)
2897 * For NICs which never report DC_RXSTATE_WAIT, we
2898 * have to bite the bullet...
2900 if ((DC_HAS_BROKEN_RXSTATE(sc) || (CSR_READ_4(sc,
2901 DC_ISR) & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT) &&
2902 sc->dc_cdata.dc_tx_cnt == 0) {
2904 if (!(mii->mii_media_status & IFM_ACTIVE))
2912 * When the init routine completes, we expect to be able to send
2913 * packets right away, and in fact the network code will send a
2914 * gratuitous ARP the moment the init routine marks the interface
2915 * as running. However, even though the MAC may have been initialized,
2916 * there may be a delay of a few seconds before the PHY completes
2917 * autonegotiation and the link is brought up. Any transmissions
2918 * made during that delay will be lost. Dealing with this is tricky:
2919 * we can't just pause in the init routine while waiting for the
2920 * PHY to come ready since that would bring the whole system to
2921 * a screeching halt for several seconds.
2923 * What we do here is prevent the TX start routine from sending
2924 * any packets until a link has been established. After the
2925 * interface has been initialized, the tick routine will poll
2926 * the state of the PHY until the IFM_ACTIVE flag is set. Until
2927 * that time, packets will stay in the send queue, and once the
2928 * link comes up, they will be flushed out to the wire.
2930 if (!sc->dc_link && mii->mii_media_status & IFM_ACTIVE &&
2931 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
2933 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
2934 dc_start_locked(ifp);
2937 if (sc->dc_flags & DC_21143_NWAY && !sc->dc_link)
2938 callout_reset(&sc->dc_stat_ch, hz/10, dc_tick, sc);
2940 callout_reset(&sc->dc_stat_ch, hz, dc_tick, sc);
2944 * A transmit underrun has occurred. Back off the transmit threshold,
2945 * or switch to store and forward mode if we have to.
2948 dc_tx_underrun(struct dc_softc *sc)
2953 if (DC_IS_DAVICOM(sc))
2956 if (DC_IS_INTEL(sc)) {
2958 * The real 21143 requires that the transmitter be idle
2959 * in order to change the transmit threshold or store
2960 * and forward state.
2962 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON);
2964 for (i = 0; i < DC_TIMEOUT; i++) {
2965 isr = CSR_READ_4(sc, DC_ISR);
2966 if (isr & DC_ISR_TX_IDLE)
2970 if (i == DC_TIMEOUT) {
2971 device_printf(sc->dc_dev,
2972 "%s: failed to force tx to idle state\n",
2978 device_printf(sc->dc_dev, "TX underrun -- ");
2979 sc->dc_txthresh += DC_TXTHRESH_INC;
2980 if (sc->dc_txthresh > DC_TXTHRESH_MAX) {
2981 printf("using store and forward mode\n");
2982 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD);
2984 printf("increasing TX threshold\n");
2985 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH);
2986 DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh);
2989 if (DC_IS_INTEL(sc))
2990 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON);
2993 #ifdef DEVICE_POLLING
2994 static poll_handler_t dc_poll;
2997 dc_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
2999 struct dc_softc *sc = ifp->if_softc;
3004 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) {
3009 sc->rxcycles = count;
3010 rx_npkts = dc_rxeof(sc);
3012 if (!IFQ_IS_EMPTY(&ifp->if_snd) &&
3013 !(ifp->if_drv_flags & IFF_DRV_OACTIVE))
3014 dc_start_locked(ifp);
3016 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */
3019 status = CSR_READ_4(sc, DC_ISR);
3020 status &= (DC_ISR_RX_WATDOGTIMEO | DC_ISR_RX_NOBUF |
3021 DC_ISR_TX_NOBUF | DC_ISR_TX_IDLE | DC_ISR_TX_UNDERRUN |
3027 /* ack what we have */
3028 CSR_WRITE_4(sc, DC_ISR, status);
3030 if (status & (DC_ISR_RX_WATDOGTIMEO | DC_ISR_RX_NOBUF)) {
3031 u_int32_t r = CSR_READ_4(sc, DC_FRAMESDISCARDED);
3032 ifp->if_ierrors += (r & 0xffff) + ((r >> 17) & 0x7ff);
3034 if (dc_rx_resync(sc))
3037 /* restart transmit unit if necessary */
3038 if (status & DC_ISR_TX_IDLE && sc->dc_cdata.dc_tx_cnt)
3039 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF);
3041 if (status & DC_ISR_TX_UNDERRUN)
3044 if (status & DC_ISR_BUS_ERR) {
3045 if_printf(ifp, "%s: bus error\n", __func__);
3053 #endif /* DEVICE_POLLING */
3058 struct dc_softc *sc;
3067 if ((CSR_READ_4(sc, DC_ISR) & DC_INTRS) == 0)
3072 #ifdef DEVICE_POLLING
3073 if (ifp->if_capenable & IFCAP_POLLING) {
3079 /* Suppress unwanted interrupts */
3080 if (!(ifp->if_flags & IFF_UP)) {
3081 if (CSR_READ_4(sc, DC_ISR) & DC_INTRS)
3087 /* Disable interrupts. */
3088 CSR_WRITE_4(sc, DC_IMR, 0x00000000);
3090 while (((status = CSR_READ_4(sc, DC_ISR)) & DC_INTRS) &&
3091 status != 0xFFFFFFFF &&
3092 (ifp->if_drv_flags & IFF_DRV_RUNNING)) {
3094 CSR_WRITE_4(sc, DC_ISR, status);
3096 if (status & DC_ISR_RX_OK) {
3098 curpkts = ifp->if_ipackets;
3100 if (curpkts == ifp->if_ipackets) {
3101 while (dc_rx_resync(sc))
3106 if (status & (DC_ISR_TX_OK | DC_ISR_TX_NOBUF))
3109 if (status & DC_ISR_TX_IDLE) {
3111 if (sc->dc_cdata.dc_tx_cnt) {
3112 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON);
3113 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF);
3117 if (status & DC_ISR_TX_UNDERRUN)
3120 if ((status & DC_ISR_RX_WATDOGTIMEO)
3121 || (status & DC_ISR_RX_NOBUF)) {
3123 curpkts = ifp->if_ipackets;
3125 if (curpkts == ifp->if_ipackets) {
3126 while (dc_rx_resync(sc))
3131 if (status & DC_ISR_BUS_ERR) {
3137 /* Re-enable interrupts. */
3138 CSR_WRITE_4(sc, DC_IMR, DC_INTRS);
3140 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
3141 dc_start_locked(ifp);
3147 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
3148 * pointers to the fragment pointers.
3151 dc_encap(struct dc_softc *sc, struct mbuf **m_head)
3153 bus_dma_segment_t segs[DC_MAXFRAGS];
3156 int cur, defragged, error, first, frag, i, idx, nseg;
3159 * If there's no way we can send any packets, return now.
3161 if (DC_TX_LIST_CNT - sc->dc_cdata.dc_tx_cnt <= DC_TX_LIST_RSVD)
3166 if (sc->dc_flags & DC_TX_COALESCE &&
3167 ((*m_head)->m_next != NULL || sc->dc_flags & DC_TX_ALIGN)) {
3168 m = m_defrag(*m_head, M_DONTWAIT);
3172 * Count the number of frags in this chain to see if we
3173 * need to m_collapse. Since the descriptor list is shared
3174 * by all packets, we'll m_collapse long chains so that they
3175 * do not use up the entire list, even if they would fit.
3178 for (m = *m_head; m != NULL; m = m->m_next)
3180 if (i > DC_TX_LIST_CNT / 4 ||
3181 DC_TX_LIST_CNT - i + sc->dc_cdata.dc_tx_cnt <=
3183 m = m_collapse(*m_head, M_DONTWAIT, DC_MAXFRAGS);
3187 if (defragged != 0) {
3196 idx = sc->dc_cdata.dc_tx_prod;
3197 error = bus_dmamap_load_mbuf_sg(sc->dc_mtag,
3198 sc->dc_cdata.dc_tx_map[idx], *m_head, segs, &nseg, 0);
3199 if (error == EFBIG) {
3200 if (defragged != 0 || (m = m_collapse(*m_head, M_DONTWAIT,
3201 DC_MAXFRAGS)) == NULL) {
3204 return (defragged != 0 ? error : ENOBUFS);
3207 error = bus_dmamap_load_mbuf_sg(sc->dc_mtag,
3208 sc->dc_cdata.dc_tx_map[idx], *m_head, segs, &nseg, 0);
3214 } else if (error != 0)
3216 KASSERT(nseg <= DC_MAXFRAGS,
3217 ("%s: wrong number of segments (%d)", __func__, nseg));
3224 first = cur = frag = sc->dc_cdata.dc_tx_prod;
3225 for (i = 0; i < nseg; i++) {
3226 if ((sc->dc_flags & DC_TX_ADMTEK_WAR) &&
3227 (frag == (DC_TX_LIST_CNT - 1)) &&
3228 (first != sc->dc_cdata.dc_tx_first)) {
3229 bus_dmamap_unload(sc->dc_mtag,
3230 sc->dc_cdata.dc_tx_map[first]);
3236 f = &sc->dc_ldata->dc_tx_list[frag];
3237 f->dc_ctl = htole32(DC_TXCTL_TLINK | segs[i].ds_len);
3240 f->dc_ctl |= htole32(DC_TXCTL_FIRSTFRAG);
3242 f->dc_status = htole32(DC_TXSTAT_OWN);
3243 f->dc_data = htole32(segs[i].ds_addr);
3245 DC_INC(frag, DC_TX_LIST_CNT);
3248 sc->dc_cdata.dc_tx_prod = frag;
3249 sc->dc_cdata.dc_tx_cnt += nseg;
3250 sc->dc_cdata.dc_tx_chain[cur] = *m_head;
3251 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= htole32(DC_TXCTL_LASTFRAG);
3252 if (sc->dc_flags & DC_TX_INTR_FIRSTFRAG)
3253 sc->dc_ldata->dc_tx_list[first].dc_ctl |=
3254 htole32(DC_TXCTL_FINT);
3255 if (sc->dc_flags & DC_TX_INTR_ALWAYS)
3256 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= htole32(DC_TXCTL_FINT);
3257 if (sc->dc_flags & DC_TX_USE_TX_INTR && sc->dc_cdata.dc_tx_cnt > 64)
3258 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= htole32(DC_TXCTL_FINT);
3259 sc->dc_ldata->dc_tx_list[first].dc_status = htole32(DC_TXSTAT_OWN);
3261 bus_dmamap_sync(sc->dc_mtag, sc->dc_cdata.dc_tx_map[idx],
3262 BUS_DMASYNC_PREWRITE);
3263 bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap,
3264 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
3269 dc_start(struct ifnet *ifp)
3271 struct dc_softc *sc;
3275 dc_start_locked(ifp);
3280 * Main transmit routine
3281 * To avoid having to do mbuf copies, we put pointers to the mbuf data
3282 * regions directly in the transmit lists. We also save a copy of the
3283 * pointers since the transmit list fragment pointers are physical
3287 dc_start_locked(struct ifnet *ifp)
3289 struct dc_softc *sc;
3290 struct mbuf *m_head = NULL;
3291 unsigned int queued = 0;
3298 if (!sc->dc_link && ifp->if_snd.ifq_len < 10)
3301 if (ifp->if_drv_flags & IFF_DRV_OACTIVE)
3304 idx = sc->dc_cdata.dc_tx_first = sc->dc_cdata.dc_tx_prod;
3306 while (sc->dc_cdata.dc_tx_chain[idx] == NULL) {
3307 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
3311 if (dc_encap(sc, &m_head)) {
3314 IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
3315 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
3318 idx = sc->dc_cdata.dc_tx_prod;
3322 * If there's a BPF listener, bounce a copy of this frame
3325 BPF_MTAP(ifp, m_head);
3327 if (sc->dc_flags & DC_TX_ONE) {
3328 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
3335 if (!(sc->dc_flags & DC_TX_POLL))
3336 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF);
3339 * Set a timeout in case the chip goes out to lunch.
3341 sc->dc_wdog_timer = 5;
3348 struct dc_softc *sc = xsc;
3356 dc_init_locked(struct dc_softc *sc)
3358 struct ifnet *ifp = sc->dc_ifp;
3359 struct mii_data *mii;
3363 mii = device_get_softc(sc->dc_miibus);
3366 * Cancel pending I/O and free all RX/TX buffers.
3372 * Set cache alignment and burst length.
3374 if (DC_IS_ASIX(sc) || DC_IS_DAVICOM(sc))
3375 CSR_WRITE_4(sc, DC_BUSCTL, 0);
3377 CSR_WRITE_4(sc, DC_BUSCTL, DC_BUSCTL_MRME | DC_BUSCTL_MRLE);
3379 * Evenly share the bus between receive and transmit process.
3381 if (DC_IS_INTEL(sc))
3382 DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_ARBITRATION);
3383 if (DC_IS_DAVICOM(sc) || DC_IS_INTEL(sc)) {
3384 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_USECA);
3386 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_16LONG);
3388 if (sc->dc_flags & DC_TX_POLL)
3389 DC_SETBIT(sc, DC_BUSCTL, DC_TXPOLL_1);
3390 switch(sc->dc_cachesize) {
3392 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_32LONG);
3395 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_16LONG);
3398 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_8LONG);
3402 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_NONE);
3406 if (sc->dc_flags & DC_TX_STORENFWD)
3407 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD);
3409 if (sc->dc_txthresh > DC_TXTHRESH_MAX) {
3410 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD);
3412 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD);
3413 DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh);
3417 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_NO_RXCRC);
3418 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_BACKOFF);
3420 if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) {
3422 * The app notes for the 98713 and 98715A say that
3423 * in order to have the chips operate properly, a magic
3424 * number must be written to CSR16. Macronix does not
3425 * document the meaning of these bits so there's no way
3426 * to know exactly what they do. The 98713 has a magic
3427 * number all its own; the rest all use a different one.
3429 DC_CLRBIT(sc, DC_MX_MAGICPACKET, 0xFFFF0000);
3430 if (sc->dc_type == DC_TYPE_98713)
3431 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98713);
3433 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98715);
3436 if (DC_IS_XIRCOM(sc)) {
3438 * setup General Purpose Port mode and data so the tulip
3439 * can talk to the MII.
3441 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_WRITE_EN | DC_SIAGP_INT1_EN |
3442 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT);
3444 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_INT1_EN |
3445 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT);
3449 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH);
3450 DC_SETBIT(sc, DC_NETCFG, DC_TXTHRESH_MIN);
3452 /* Init circular RX list. */
3453 if (dc_list_rx_init(sc) == ENOBUFS) {
3454 device_printf(sc->dc_dev,
3455 "initialization failed: no memory for rx buffers\n");
3461 * Init TX descriptors.
3463 dc_list_tx_init(sc);
3466 * Load the address of the RX list.
3468 CSR_WRITE_4(sc, DC_RXADDR, DC_RXDESC(sc, 0));
3469 CSR_WRITE_4(sc, DC_TXADDR, DC_TXDESC(sc, 0));
3472 * Enable interrupts.
3474 #ifdef DEVICE_POLLING
3476 * ... but only if we are not polling, and make sure they are off in
3477 * the case of polling. Some cards (e.g. fxp) turn interrupts on
3480 if (ifp->if_capenable & IFCAP_POLLING)
3481 CSR_WRITE_4(sc, DC_IMR, 0x00000000);
3484 CSR_WRITE_4(sc, DC_IMR, DC_INTRS);
3485 CSR_WRITE_4(sc, DC_ISR, 0xFFFFFFFF);
3487 /* Enable transmitter. */
3488 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON);
3491 * If this is an Intel 21143 and we're not using the
3492 * MII port, program the LED control pins so we get
3493 * link and activity indications.
3495 if (sc->dc_flags & DC_TULIP_LEDS) {
3496 CSR_WRITE_4(sc, DC_WATCHDOG,
3497 DC_WDOG_CTLWREN | DC_WDOG_LINK | DC_WDOG_ACTIVITY);
3498 CSR_WRITE_4(sc, DC_WATCHDOG, 0);
3502 * Load the RX/multicast filter. We do this sort of late
3503 * because the filter programming scheme on the 21143 and
3504 * some clones requires DMAing a setup frame via the TX
3505 * engine, and we need the transmitter enabled for that.
3509 /* Enable receiver. */
3510 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON);
3511 CSR_WRITE_4(sc, DC_RXSTART, 0xFFFFFFFF);
3514 dc_setcfg(sc, sc->dc_if_media);
3516 ifp->if_drv_flags |= IFF_DRV_RUNNING;
3517 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
3519 /* Don't start the ticker if this is a homePNA link. */
3520 if (IFM_SUBTYPE(mii->mii_media.ifm_media) == IFM_HPNA_1)
3523 if (sc->dc_flags & DC_21143_NWAY)
3524 callout_reset(&sc->dc_stat_ch, hz/10, dc_tick, sc);
3526 callout_reset(&sc->dc_stat_ch, hz, dc_tick, sc);
3529 sc->dc_wdog_timer = 0;
3530 callout_reset(&sc->dc_wdog_ch, hz, dc_watchdog, sc);
3534 * Set media options.
3537 dc_ifmedia_upd(struct ifnet *ifp)
3539 struct dc_softc *sc;
3540 struct mii_data *mii;
3541 struct ifmedia *ifm;
3544 mii = device_get_softc(sc->dc_miibus);
3547 ifm = &mii->mii_media;
3549 if (DC_IS_DAVICOM(sc) &&
3550 IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1)
3551 dc_setcfg(sc, ifm->ifm_media);
3560 * Report current media status.
3563 dc_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
3565 struct dc_softc *sc;
3566 struct mii_data *mii;
3567 struct ifmedia *ifm;
3570 mii = device_get_softc(sc->dc_miibus);
3573 ifm = &mii->mii_media;
3574 if (DC_IS_DAVICOM(sc)) {
3575 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) {
3576 ifmr->ifm_active = ifm->ifm_media;
3577 ifmr->ifm_status = 0;
3582 ifmr->ifm_active = mii->mii_media_active;
3583 ifmr->ifm_status = mii->mii_media_status;
3588 dc_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
3590 struct dc_softc *sc = ifp->if_softc;
3591 struct ifreq *ifr = (struct ifreq *)data;
3592 struct mii_data *mii;
3598 if (ifp->if_flags & IFF_UP) {
3599 int need_setfilt = (ifp->if_flags ^ sc->dc_if_flags) &
3600 (IFF_PROMISC | IFF_ALLMULTI);
3602 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
3606 sc->dc_txthresh = 0;
3610 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
3613 sc->dc_if_flags = ifp->if_flags;
3626 mii = device_get_softc(sc->dc_miibus);
3627 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
3630 #ifdef DEVICE_POLLING
3631 if (ifr->ifr_reqcap & IFCAP_POLLING &&
3632 !(ifp->if_capenable & IFCAP_POLLING)) {
3633 error = ether_poll_register(dc_poll, ifp);
3637 /* Disable interrupts */
3638 CSR_WRITE_4(sc, DC_IMR, 0x00000000);
3639 ifp->if_capenable |= IFCAP_POLLING;
3643 if (!(ifr->ifr_reqcap & IFCAP_POLLING) &&
3644 ifp->if_capenable & IFCAP_POLLING) {
3645 error = ether_poll_deregister(ifp);
3646 /* Enable interrupts. */
3648 CSR_WRITE_4(sc, DC_IMR, DC_INTRS);
3649 ifp->if_capenable &= ~IFCAP_POLLING;
3653 #endif /* DEVICE_POLLING */
3656 error = ether_ioctl(ifp, command, data);
3664 dc_watchdog(void *xsc)
3666 struct dc_softc *sc = xsc;
3671 if (sc->dc_wdog_timer == 0 || --sc->dc_wdog_timer != 0) {
3672 callout_reset(&sc->dc_wdog_ch, hz, dc_watchdog, sc);
3678 device_printf(sc->dc_dev, "watchdog timeout\n");
3684 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
3685 dc_start_locked(ifp);
3689 * Stop the adapter and free any mbufs allocated to the
3693 dc_stop(struct dc_softc *sc)
3696 struct dc_list_data *ld;
3697 struct dc_chain_data *cd;
3707 callout_stop(&sc->dc_stat_ch);
3708 callout_stop(&sc->dc_wdog_ch);
3709 sc->dc_wdog_timer = 0;
3711 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
3713 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_RX_ON | DC_NETCFG_TX_ON));
3714 CSR_WRITE_4(sc, DC_IMR, 0x00000000);
3715 CSR_WRITE_4(sc, DC_TXADDR, 0x00000000);
3716 CSR_WRITE_4(sc, DC_RXADDR, 0x00000000);
3720 * Free data in the RX lists.
3722 for (i = 0; i < DC_RX_LIST_CNT; i++) {
3723 if (cd->dc_rx_chain[i] != NULL) {
3724 m_freem(cd->dc_rx_chain[i]);
3725 cd->dc_rx_chain[i] = NULL;
3728 bzero(&ld->dc_rx_list, sizeof(ld->dc_rx_list));
3731 * Free the TX list buffers.
3733 for (i = 0; i < DC_TX_LIST_CNT; i++) {
3734 if (cd->dc_tx_chain[i] != NULL) {
3735 ctl = le32toh(ld->dc_tx_list[i].dc_ctl);
3736 if ((ctl & DC_TXCTL_SETUP) ||
3737 !(ctl & DC_TXCTL_LASTFRAG)) {
3738 cd->dc_tx_chain[i] = NULL;
3741 bus_dmamap_unload(sc->dc_mtag, cd->dc_tx_map[i]);
3742 m_freem(cd->dc_tx_chain[i]);
3743 cd->dc_tx_chain[i] = NULL;
3746 bzero(&ld->dc_tx_list, sizeof(ld->dc_tx_list));
3750 * Device suspend routine. Stop the interface and save some PCI
3751 * settings in case the BIOS doesn't restore them properly on
3755 dc_suspend(device_t dev)
3757 struct dc_softc *sc;
3759 sc = device_get_softc(dev);
3769 * Device resume routine. Restore some PCI settings in case the BIOS
3770 * doesn't, re-enable busmastering, and restart the interface if
3774 dc_resume(device_t dev)
3776 struct dc_softc *sc;
3779 sc = device_get_softc(dev);
3782 /* reinitialize interface if necessary */
3784 if (ifp->if_flags & IFF_UP)
3794 * Stop all chip I/O so that the kernel's probe routines don't
3795 * get confused by errant DMAs when rebooting.
3798 dc_shutdown(device_t dev)
3800 struct dc_softc *sc;
3802 sc = device_get_softc(dev);
projects / FreeBSD / releng / 8.1.git / blob