sys/dev/drm/r600_cp.c

   1 /*-
   2  * Copyright 2008-2009 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22  * DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *     Dave Airlie <airlied@redhat.com>
  26  *     Alex Deucher <alexander.deucher@amd.com>
  27  */
  28
  29 #include <sys/cdefs.h>
  30 __FBSDID("$FreeBSD$");
  31
  32 #include "dev/drm/drmP.h"
  33 #include "dev/drm/drm.h"
  34 #include "dev/drm/radeon_drm.h"
  35 #include "dev/drm/radeon_drv.h"
  36
  37 #include "dev/drm/r600_microcode.h"
  38
  39 # define ATI_PCIGART_PAGE_SIZE          4096    /**< PCI GART page size */
  40 # define ATI_PCIGART_PAGE_MASK          (~(ATI_PCIGART_PAGE_SIZE-1))
  41
  42 #define R600_PTE_VALID     (1 << 0)
  43 #define R600_PTE_SYSTEM    (1 << 1)
  44 #define R600_PTE_SNOOPED   (1 << 2)
  45 #define R600_PTE_READABLE  (1 << 5)
  46 #define R600_PTE_WRITEABLE (1 << 6)
  47
  48 /* MAX values used for gfx init */
  49 #define R6XX_MAX_SH_GPRS           256
  50 #define R6XX_MAX_TEMP_GPRS         16
  51 #define R6XX_MAX_SH_THREADS        256
  52 #define R6XX_MAX_SH_STACK_ENTRIES  4096
  53 #define R6XX_MAX_BACKENDS          8
  54 #define R6XX_MAX_BACKENDS_MASK     0xff
  55 #define R6XX_MAX_SIMDS             8
  56 #define R6XX_MAX_SIMDS_MASK        0xff
  57 #define R6XX_MAX_PIPES             8
  58 #define R6XX_MAX_PIPES_MASK        0xff
  59
  60 #define R7XX_MAX_SH_GPRS           256
  61 #define R7XX_MAX_TEMP_GPRS         16
  62 #define R7XX_MAX_SH_THREADS        256
  63 #define R7XX_MAX_SH_STACK_ENTRIES  4096
  64 #define R7XX_MAX_BACKENDS          8
  65 #define R7XX_MAX_BACKENDS_MASK     0xff
  66 #define R7XX_MAX_SIMDS             16
  67 #define R7XX_MAX_SIMDS_MASK        0xffff
  68 #define R7XX_MAX_PIPES             8
  69 #define R7XX_MAX_PIPES_MASK        0xff
  70
  71 static int r600_do_wait_for_fifo(drm_radeon_private_t *dev_priv, int entries)
  72 {
  73         int i;
  74
  75         dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
  76
  77         for (i = 0; i < dev_priv->usec_timeout; i++) {
  78                 int slots;
  79                 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)
  80                         slots = (RADEON_READ(R600_GRBM_STATUS)
  81                                  & R700_CMDFIFO_AVAIL_MASK);
  82                 else
  83                         slots = (RADEON_READ(R600_GRBM_STATUS)
  84                                  & R600_CMDFIFO_AVAIL_MASK);
  85                 if (slots >= entries)
  86                         return 0;
  87                 DRM_UDELAY(1);
  88         }
  89         DRM_INFO("wait for fifo failed status : 0x%08X 0x%08X\n",
  90                  RADEON_READ(R600_GRBM_STATUS),
  91                  RADEON_READ(R600_GRBM_STATUS2));
  92
  93         return -EBUSY;
  94 }
  95
  96 static int r600_do_wait_for_idle(drm_radeon_private_t *dev_priv)
  97 {
  98         int i, ret;
  99
 100         dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
 101
 102         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)
 103                 ret = r600_do_wait_for_fifo(dev_priv, 8);
 104         else
 105                 ret = r600_do_wait_for_fifo(dev_priv, 16);
 106         if (ret)
 107                 return ret;
 108         for (i = 0; i < dev_priv->usec_timeout; i++) {
 109                 if (!(RADEON_READ(R600_GRBM_STATUS) & R600_GUI_ACTIVE))
 110                         return 0;
 111                 DRM_UDELAY(1);
 112         }
 113         DRM_INFO("wait idle failed status : 0x%08X 0x%08X\n",
 114                  RADEON_READ(R600_GRBM_STATUS),
 115                  RADEON_READ(R600_GRBM_STATUS2));
 116
 117         return -EBUSY;
 118 }
 119
 120 void r600_page_table_cleanup(struct drm_device *dev, struct drm_ati_pcigart_info *gart_info)
 121 {
 122 #ifdef __linux__
 123         struct drm_sg_mem *entry = dev->sg;
 124         int max_pages;
 125         int pages;
 126         int i;
 127 #endif
 128         if (gart_info->bus_addr) {
 129 #ifdef __linux__
 130                 max_pages = (gart_info->table_size / sizeof(u32));
 131                 pages = (entry->pages <= max_pages)
 132                   ? entry->pages : max_pages;
 133
 134                 for (i = 0; i < pages; i++) {
 135                         if (!entry->busaddr[i])
 136                                 break;
 137                         pci_unmap_single(dev->pdev, entry->busaddr[i],
 138                                          PAGE_SIZE, PCI_DMA_TODEVICE);
 139                 }
 140 #endif
 141                 if (gart_info->gart_table_location == DRM_ATI_GART_MAIN)
 142                         gart_info->bus_addr = 0;
 143         }
 144 }
 145
 146 /* R600 has page table setup */
 147 int r600_page_table_init(struct drm_device *dev)
 148 {
 149         drm_radeon_private_t *dev_priv = dev->dev_private;
 150         struct drm_ati_pcigart_info *gart_info = &dev_priv->gart_info;
 151         struct drm_sg_mem *entry = dev->sg;
 152         int ret = 0;
 153         int i, j;
 154         int max_pages, pages;
 155         u64 *pci_gart, page_base;
 156         dma_addr_t entry_addr;
 157
 158         /* okay page table is available - lets rock */
 159
 160         /* PTEs are 64-bits */
 161         pci_gart = (u64 *)gart_info->addr;
 162
 163         max_pages = (gart_info->table_size / sizeof(u64));
 164         pages = (entry->pages <= max_pages) ? entry->pages : max_pages;
 165
 166         memset(pci_gart, 0, max_pages * sizeof(u64));
 167
 168         for (i = 0; i < pages; i++) {
 169 #ifdef __linux__
 170                 entry->busaddr[i] = pci_map_single(dev->pdev,
 171                                                    page_address(entry->
 172                                                                 pagelist[i]),
 173                                                    PAGE_SIZE, PCI_DMA_TODEVICE);
 174                 if (entry->busaddr[i] == 0) {
 175                         DRM_ERROR("unable to map PCIGART pages!\n");
 176                         r600_page_table_cleanup(dev, gart_info);
 177                         goto done;
 178                 }
 179 #endif
 180                 entry_addr = entry->busaddr[i];
 181                 for (j = 0; j < (PAGE_SIZE / ATI_PCIGART_PAGE_SIZE); j++) {
 182                         page_base = (u64) entry_addr & ATI_PCIGART_PAGE_MASK;
 183                         page_base |= R600_PTE_VALID | R600_PTE_SYSTEM | R600_PTE_SNOOPED;
 184                         page_base |= R600_PTE_READABLE | R600_PTE_WRITEABLE;
 185
 186                         *pci_gart = page_base;
 187
 188                         if ((i % 128) == 0)
 189                                 DRM_DEBUG("page entry %d: 0x%016llx\n",
 190                                     i, (unsigned long long)page_base);
 191                         pci_gart++;
 192                         entry_addr += ATI_PCIGART_PAGE_SIZE;
 193                 }
 194         }
 195         ret = 1;
 196 #ifdef __linux__
 197 done:
 198 #endif
 199         return ret;
 200 }
 201
 202 static void r600_vm_flush_gart_range(struct drm_device *dev)
 203 {
 204         drm_radeon_private_t *dev_priv = dev->dev_private;
 205         u32 resp, countdown = 1000;
 206         RADEON_WRITE(R600_VM_CONTEXT0_INVALIDATION_LOW_ADDR, dev_priv->gart_vm_start >> 12);
 207         RADEON_WRITE(R600_VM_CONTEXT0_INVALIDATION_HIGH_ADDR, (dev_priv->gart_vm_start + dev_priv->gart_size - 1) >> 12);
 208         RADEON_WRITE(R600_VM_CONTEXT0_REQUEST_RESPONSE, 2);
 209
 210         do {
 211                 resp = RADEON_READ(R600_VM_CONTEXT0_REQUEST_RESPONSE);
 212                 countdown--;
 213                 DRM_UDELAY(1);
 214         } while (((resp & 0xf0) == 0) && countdown);
 215 }
 216
 217 static void r600_vm_init(struct drm_device *dev)
 218 {
 219         drm_radeon_private_t *dev_priv = dev->dev_private;
 220         /* initialise the VM to use the page table we constructed up there */
 221         u32 vm_c0, i;
 222         u32 mc_rd_a;
 223         u32 vm_l2_cntl, vm_l2_cntl3;
 224         /* okay set up the PCIE aperture type thingo */
 225         RADEON_WRITE(R600_MC_VM_SYSTEM_APERTURE_LOW_ADDR, dev_priv->gart_vm_start >> 12);
 226         RADEON_WRITE(R600_MC_VM_SYSTEM_APERTURE_HIGH_ADDR, (dev_priv->gart_vm_start + dev_priv->gart_size - 1) >> 12);
 227         RADEON_WRITE(R600_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0);
 228
 229         /* setup MC RD a */
 230         mc_rd_a = R600_MCD_L1_TLB | R600_MCD_L1_FRAG_PROC | R600_MCD_SYSTEM_ACCESS_MODE_IN_SYS |
 231                 R600_MCD_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU | R600_MCD_EFFECTIVE_L1_TLB_SIZE(5) |
 232                 R600_MCD_EFFECTIVE_L1_QUEUE_SIZE(5) | R600_MCD_WAIT_L2_QUERY;
 233
 234         RADEON_WRITE(R600_MCD_RD_A_CNTL, mc_rd_a);
 235         RADEON_WRITE(R600_MCD_RD_B_CNTL, mc_rd_a);
 236
 237         RADEON_WRITE(R600_MCD_WR_A_CNTL, mc_rd_a);
 238         RADEON_WRITE(R600_MCD_WR_B_CNTL, mc_rd_a);
 239
 240         RADEON_WRITE(R600_MCD_RD_GFX_CNTL, mc_rd_a);
 241         RADEON_WRITE(R600_MCD_WR_GFX_CNTL, mc_rd_a);
 242
 243         RADEON_WRITE(R600_MCD_RD_SYS_CNTL, mc_rd_a);
 244         RADEON_WRITE(R600_MCD_WR_SYS_CNTL, mc_rd_a);
 245
 246         RADEON_WRITE(R600_MCD_RD_HDP_CNTL, mc_rd_a | R600_MCD_L1_STRICT_ORDERING);
 247         RADEON_WRITE(R600_MCD_WR_HDP_CNTL, mc_rd_a /*| R600_MCD_L1_STRICT_ORDERING*/);
 248
 249         RADEON_WRITE(R600_MCD_RD_PDMA_CNTL, mc_rd_a);
 250         RADEON_WRITE(R600_MCD_WR_PDMA_CNTL, mc_rd_a);
 251
 252         RADEON_WRITE(R600_MCD_RD_SEM_CNTL, mc_rd_a | R600_MCD_SEMAPHORE_MODE);
 253         RADEON_WRITE(R600_MCD_WR_SEM_CNTL, mc_rd_a);
 254
 255         vm_l2_cntl = R600_VM_L2_CACHE_EN | R600_VM_L2_FRAG_PROC | R600_VM_ENABLE_PTE_CACHE_LRU_W;
 256         vm_l2_cntl |= R600_VM_L2_CNTL_QUEUE_SIZE(7);
 257         RADEON_WRITE(R600_VM_L2_CNTL, vm_l2_cntl);
 258
 259         RADEON_WRITE(R600_VM_L2_CNTL2, 0);
 260         vm_l2_cntl3 = (R600_VM_L2_CNTL3_BANK_SELECT_0(0) |
 261                        R600_VM_L2_CNTL3_BANK_SELECT_1(1) |
 262                        R600_VM_L2_CNTL3_CACHE_UPDATE_MODE(2));
 263         RADEON_WRITE(R600_VM_L2_CNTL3, vm_l2_cntl3);
 264
 265         vm_c0 = R600_VM_ENABLE_CONTEXT | R600_VM_PAGE_TABLE_DEPTH_FLAT;
 266
 267         RADEON_WRITE(R600_VM_CONTEXT0_CNTL, vm_c0);
 268
 269         vm_c0 &= ~R600_VM_ENABLE_CONTEXT;
 270
 271         /* disable all other contexts */
 272         for (i = 1; i < 8; i++)
 273                 RADEON_WRITE(R600_VM_CONTEXT0_CNTL + (i * 4), vm_c0);
 274
 275         RADEON_WRITE(R600_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, dev_priv->gart_info.bus_addr >> 12);
 276         RADEON_WRITE(R600_VM_CONTEXT0_PAGE_TABLE_START_ADDR, dev_priv->gart_vm_start >> 12);
 277         RADEON_WRITE(R600_VM_CONTEXT0_PAGE_TABLE_END_ADDR, (dev_priv->gart_vm_start + dev_priv->gart_size - 1) >> 12);
 278
 279         r600_vm_flush_gart_range(dev);
 280 }
 281
 282 /* load r600 microcode */
 283 static void r600_cp_load_microcode(drm_radeon_private_t *dev_priv)
 284 {
 285         const u32 (*cp)[3];
 286         const u32 *pfp;
 287         int i;
 288
 289         switch (dev_priv->flags & RADEON_FAMILY_MASK) {
 290         case CHIP_R600:
 291                 DRM_INFO("Loading R600 Microcode\n");
 292                 cp  = R600_cp_microcode;
 293                 pfp = R600_pfp_microcode;
 294                 break;
 295         case CHIP_RV610:
 296                 DRM_INFO("Loading RV610 Microcode\n");
 297                 cp  = RV610_cp_microcode;
 298                 pfp = RV610_pfp_microcode;
 299                 break;
 300         case CHIP_RV630:
 301                 DRM_INFO("Loading RV630 Microcode\n");
 302                 cp  = RV630_cp_microcode;
 303                 pfp = RV630_pfp_microcode;
 304                 break;
 305         case CHIP_RV620:
 306                 DRM_INFO("Loading RV620 Microcode\n");
 307                 cp  = RV620_cp_microcode;
 308                 pfp = RV620_pfp_microcode;
 309                 break;
 310         case CHIP_RV635:
 311                 DRM_INFO("Loading RV635 Microcode\n");
 312                 cp  = RV635_cp_microcode;
 313                 pfp = RV635_pfp_microcode;
 314                 break;
 315         case CHIP_RV670:
 316                 DRM_INFO("Loading RV670 Microcode\n");
 317                 cp  = RV670_cp_microcode;
 318                 pfp = RV670_pfp_microcode;
 319                 break;
 320         case CHIP_RS780:
 321         case CHIP_RS880:
 322                 DRM_INFO("Loading RS780/RS880 Microcode\n");
 323                 cp  = RS780_cp_microcode;
 324                 pfp = RS780_pfp_microcode;
 325                 break;
 326         default:
 327                 return;
 328         }
 329
 330         r600_do_cp_stop(dev_priv);
 331
 332         RADEON_WRITE(R600_CP_RB_CNTL,
 333                      R600_RB_NO_UPDATE |
 334                      R600_RB_BLKSZ(15) |
 335                      R600_RB_BUFSZ(3));
 336
 337         RADEON_WRITE(R600_GRBM_SOFT_RESET, R600_SOFT_RESET_CP);
 338         RADEON_READ(R600_GRBM_SOFT_RESET);
 339         DRM_UDELAY(15000);
 340         RADEON_WRITE(R600_GRBM_SOFT_RESET, 0);
 341
 342         RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0);
 343
 344         for (i = 0; i < PM4_UCODE_SIZE; i++) {
 345                 RADEON_WRITE(R600_CP_ME_RAM_DATA, cp[i][0]);
 346                 RADEON_WRITE(R600_CP_ME_RAM_DATA, cp[i][1]);
 347                 RADEON_WRITE(R600_CP_ME_RAM_DATA, cp[i][2]);
 348         }
 349
 350         RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
 351         for (i = 0; i < PFP_UCODE_SIZE; i++)
 352                 RADEON_WRITE(R600_CP_PFP_UCODE_DATA, pfp[i]);
 353
 354         RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
 355         RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0);
 356         RADEON_WRITE(R600_CP_ME_RAM_RADDR, 0);
 357 }
 358
 359 static void r700_vm_init(struct drm_device *dev)
 360 {
 361         drm_radeon_private_t *dev_priv = dev->dev_private;
 362         /* initialise the VM to use the page table we constructed up there */
 363         u32 vm_c0, i;
 364         u32 mc_vm_md_l1;
 365         u32 vm_l2_cntl, vm_l2_cntl3;
 366         /* okay set up the PCIE aperture type thingo */
 367         RADEON_WRITE(R700_MC_VM_SYSTEM_APERTURE_LOW_ADDR, dev_priv->gart_vm_start >> 12);
 368         RADEON_WRITE(R700_MC_VM_SYSTEM_APERTURE_HIGH_ADDR, (dev_priv->gart_vm_start + dev_priv->gart_size - 1) >> 12);
 369         RADEON_WRITE(R700_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0);
 370
 371         mc_vm_md_l1 = R700_ENABLE_L1_TLB |
 372             R700_ENABLE_L1_FRAGMENT_PROCESSING |
 373             R700_SYSTEM_ACCESS_MODE_IN_SYS |
 374             R700_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
 375             R700_EFFECTIVE_L1_TLB_SIZE(5) |
 376             R700_EFFECTIVE_L1_QUEUE_SIZE(5);
 377
 378         RADEON_WRITE(R700_MC_VM_MD_L1_TLB0_CNTL, mc_vm_md_l1);
 379         RADEON_WRITE(R700_MC_VM_MD_L1_TLB1_CNTL, mc_vm_md_l1);
 380         RADEON_WRITE(R700_MC_VM_MD_L1_TLB2_CNTL, mc_vm_md_l1);
 381         RADEON_WRITE(R700_MC_VM_MB_L1_TLB0_CNTL, mc_vm_md_l1);
 382         RADEON_WRITE(R700_MC_VM_MB_L1_TLB1_CNTL, mc_vm_md_l1);
 383         RADEON_WRITE(R700_MC_VM_MB_L1_TLB2_CNTL, mc_vm_md_l1);
 384         RADEON_WRITE(R700_MC_VM_MB_L1_TLB3_CNTL, mc_vm_md_l1);
 385
 386         vm_l2_cntl = R600_VM_L2_CACHE_EN | R600_VM_L2_FRAG_PROC | R600_VM_ENABLE_PTE_CACHE_LRU_W;
 387         vm_l2_cntl |= R700_VM_L2_CNTL_QUEUE_SIZE(7);
 388         RADEON_WRITE(R600_VM_L2_CNTL, vm_l2_cntl);
 389
 390         RADEON_WRITE(R600_VM_L2_CNTL2, 0);
 391         vm_l2_cntl3 = R700_VM_L2_CNTL3_BANK_SELECT(0) | R700_VM_L2_CNTL3_CACHE_UPDATE_MODE(2);
 392         RADEON_WRITE(R600_VM_L2_CNTL3, vm_l2_cntl3);
 393
 394         vm_c0 = R600_VM_ENABLE_CONTEXT | R600_VM_PAGE_TABLE_DEPTH_FLAT;
 395
 396         RADEON_WRITE(R600_VM_CONTEXT0_CNTL, vm_c0);
 397
 398         vm_c0 &= ~R600_VM_ENABLE_CONTEXT;
 399
 400         /* disable all other contexts */
 401         for (i = 1; i < 8; i++)
 402                 RADEON_WRITE(R600_VM_CONTEXT0_CNTL + (i * 4), vm_c0);
 403
 404         RADEON_WRITE(R700_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, dev_priv->gart_info.bus_addr >> 12);
 405         RADEON_WRITE(R700_VM_CONTEXT0_PAGE_TABLE_START_ADDR, dev_priv->gart_vm_start >> 12);
 406         RADEON_WRITE(R700_VM_CONTEXT0_PAGE_TABLE_END_ADDR, (dev_priv->gart_vm_start + dev_priv->gart_size - 1) >> 12);
 407
 408         r600_vm_flush_gart_range(dev);
 409 }
 410
 411 /* load r600 microcode */
 412 static void r700_cp_load_microcode(drm_radeon_private_t *dev_priv)
 413 {
 414         const u32 *pfp;
 415         const u32 *cp;
 416         int i;
 417
 418         switch (dev_priv->flags & RADEON_FAMILY_MASK) {
 419         case CHIP_RV770:
 420                 DRM_INFO("Loading RV770/RV790 Microcode\n");
 421                 pfp = RV770_pfp_microcode;
 422                 cp  = RV770_cp_microcode;
 423                 break;
 424         case CHIP_RV730:
 425         case CHIP_RV740:
 426                 DRM_INFO("Loading RV730/RV740 Microcode\n");
 427                 pfp = RV730_pfp_microcode;
 428                 cp  = RV730_cp_microcode;
 429                 break;
 430         case CHIP_RV710:
 431                 DRM_INFO("Loading RV710 Microcode\n");
 432                 pfp = RV710_pfp_microcode;
 433                 cp  = RV710_cp_microcode;
 434                 break;
 435         default:
 436                 return;
 437         }
 438
 439         r600_do_cp_stop(dev_priv);
 440
 441         RADEON_WRITE(R600_CP_RB_CNTL,
 442                      R600_RB_NO_UPDATE |
 443                      (15 << 8) |
 444                      (3 << 0));
 445
 446         RADEON_WRITE(R600_GRBM_SOFT_RESET, R600_SOFT_RESET_CP);
 447         RADEON_READ(R600_GRBM_SOFT_RESET);
 448         DRM_UDELAY(15000);
 449         RADEON_WRITE(R600_GRBM_SOFT_RESET, 0);
 450
 451         RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
 452         for (i = 0; i < R700_PFP_UCODE_SIZE; i++)
 453                 RADEON_WRITE(R600_CP_PFP_UCODE_DATA, pfp[i]);
 454         RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
 455
 456         RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0);
 457         for (i = 0; i < R700_PM4_UCODE_SIZE; i++)
 458                 RADEON_WRITE(R600_CP_ME_RAM_DATA, cp[i]);
 459         RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0);
 460
 461         RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
 462         RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0);
 463         RADEON_WRITE(R600_CP_ME_RAM_RADDR, 0);
 464 }
 465
 466 static void r600_test_writeback(drm_radeon_private_t *dev_priv)
 467 {
 468         u32 tmp;
 469
 470         /* Start with assuming that writeback doesn't work */
 471         dev_priv->writeback_works = 0;
 472
 473         /* Writeback doesn't seem to work everywhere, test it here and possibly
 474          * enable it if it appears to work
 475          */
 476         radeon_write_ring_rptr(dev_priv, R600_SCRATCHOFF(1), 0);
 477
 478         RADEON_WRITE(R600_SCRATCH_REG1, 0xdeadbeef);
 479
 480         for (tmp = 0; tmp < dev_priv->usec_timeout; tmp++) {
 481                 u32 val;
 482
 483                 val = radeon_read_ring_rptr(dev_priv, R600_SCRATCHOFF(1));
 484                 if (val == 0xdeadbeef)
 485                         break;
 486                 DRM_UDELAY(1);
 487         }
 488
 489         if (tmp < dev_priv->usec_timeout) {
 490                 dev_priv->writeback_works = 1;
 491                 DRM_INFO("writeback test succeeded in %d usecs\n", tmp);
 492         } else {
 493                 dev_priv->writeback_works = 0;
 494                 DRM_INFO("writeback test failed\n");
 495         }
 496         if (radeon_no_wb == 1) {
 497                 dev_priv->writeback_works = 0;
 498                 DRM_INFO("writeback forced off\n");
 499         }
 500
 501         if (!dev_priv->writeback_works) {
 502                 /* Disable writeback to avoid unnecessary bus master transfer */
 503                 RADEON_WRITE(R600_CP_RB_CNTL, RADEON_READ(R600_CP_RB_CNTL) |
 504                              RADEON_RB_NO_UPDATE);
 505                 RADEON_WRITE(R600_SCRATCH_UMSK, 0);
 506         }
 507 }
 508
 509 int r600_do_engine_reset(struct drm_device *dev)
 510 {
 511         drm_radeon_private_t *dev_priv = dev->dev_private;
 512         u32 cp_ptr, cp_me_cntl, cp_rb_cntl;
 513
 514         DRM_INFO("Resetting GPU\n");
 515
 516         cp_ptr = RADEON_READ(R600_CP_RB_WPTR);
 517         cp_me_cntl = RADEON_READ(R600_CP_ME_CNTL);
 518         RADEON_WRITE(R600_CP_ME_CNTL, R600_CP_ME_HALT);
 519
 520         RADEON_WRITE(R600_GRBM_SOFT_RESET, 0x7fff);
 521         RADEON_READ(R600_GRBM_SOFT_RESET);
 522         DRM_UDELAY(50);
 523         RADEON_WRITE(R600_GRBM_SOFT_RESET, 0);
 524         RADEON_READ(R600_GRBM_SOFT_RESET);
 525
 526         RADEON_WRITE(R600_CP_RB_WPTR_DELAY, 0);
 527         cp_rb_cntl = RADEON_READ(R600_CP_RB_CNTL);
 528         RADEON_WRITE(R600_CP_RB_CNTL, R600_RB_RPTR_WR_ENA);
 529
 530         RADEON_WRITE(R600_CP_RB_RPTR_WR, cp_ptr);
 531         RADEON_WRITE(R600_CP_RB_WPTR, cp_ptr);
 532         RADEON_WRITE(R600_CP_RB_CNTL, cp_rb_cntl);
 533         RADEON_WRITE(R600_CP_ME_CNTL, cp_me_cntl);
 534
 535         /* Reset the CP ring */
 536         r600_do_cp_reset(dev_priv);
 537
 538         /* The CP is no longer running after an engine reset */
 539         dev_priv->cp_running = 0;
 540
 541         /* Reset any pending vertex, indirect buffers */
 542         radeon_freelist_reset(dev);
 543
 544         return 0;
 545
 546 }
 547
 548 static u32 r600_get_tile_pipe_to_backend_map(u32 num_tile_pipes,
 549                                              u32 num_backends,
 550                                              u32 backend_disable_mask)
 551 {
 552         u32 backend_map = 0;
 553         u32 enabled_backends_mask;
 554         u32 enabled_backends_count;
 555         u32 cur_pipe;
 556         u32 swizzle_pipe[R6XX_MAX_PIPES];
 557         u32 cur_backend;
 558         u32 i;
 559
 560         if (num_tile_pipes > R6XX_MAX_PIPES)
 561                 num_tile_pipes = R6XX_MAX_PIPES;
 562         if (num_tile_pipes < 1)
 563                 num_tile_pipes = 1;
 564         if (num_backends > R6XX_MAX_BACKENDS)
 565                 num_backends = R6XX_MAX_BACKENDS;
 566         if (num_backends < 1)
 567                 num_backends = 1;
 568
 569         enabled_backends_mask = 0;
 570         enabled_backends_count = 0;
 571         for (i = 0; i < R6XX_MAX_BACKENDS; ++i) {
 572                 if (((backend_disable_mask >> i) & 1) == 0) {
 573                         enabled_backends_mask |= (1 << i);
 574                         ++enabled_backends_count;
 575                 }
 576                 if (enabled_backends_count == num_backends)
 577                         break;
 578         }
 579
 580         if (enabled_backends_count == 0) {
 581                 enabled_backends_mask = 1;
 582                 enabled_backends_count = 1;
 583         }
 584
 585         if (enabled_backends_count != num_backends)
 586                 num_backends = enabled_backends_count;
 587
 588         memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * R6XX_MAX_PIPES);
 589         switch (num_tile_pipes) {
 590         case 1:
 591                 swizzle_pipe[0] = 0;
 592                 break;
 593         case 2:
 594                 swizzle_pipe[0] = 0;
 595                 swizzle_pipe[1] = 1;
 596                 break;
 597         case 3:
 598                 swizzle_pipe[0] = 0;
 599                 swizzle_pipe[1] = 1;
 600                 swizzle_pipe[2] = 2;
 601                 break;
 602         case 4:
 603                 swizzle_pipe[0] = 0;
 604                 swizzle_pipe[1] = 1;
 605                 swizzle_pipe[2] = 2;
 606                 swizzle_pipe[3] = 3;
 607                 break;
 608         case 5:
 609                 swizzle_pipe[0] = 0;
 610                 swizzle_pipe[1] = 1;
 611                 swizzle_pipe[2] = 2;
 612                 swizzle_pipe[3] = 3;
 613                 swizzle_pipe[4] = 4;
 614                 break;
 615         case 6:
 616                 swizzle_pipe[0] = 0;
 617                 swizzle_pipe[1] = 2;
 618                 swizzle_pipe[2] = 4;
 619                 swizzle_pipe[3] = 5;
 620                 swizzle_pipe[4] = 1;
 621                 swizzle_pipe[5] = 3;
 622                 break;
 623         case 7:
 624                 swizzle_pipe[0] = 0;
 625                 swizzle_pipe[1] = 2;
 626                 swizzle_pipe[2] = 4;
 627                 swizzle_pipe[3] = 6;
 628                 swizzle_pipe[4] = 1;
 629                 swizzle_pipe[5] = 3;
 630                 swizzle_pipe[6] = 5;
 631                 break;
 632         case 8:
 633                 swizzle_pipe[0] = 0;
 634                 swizzle_pipe[1] = 2;
 635                 swizzle_pipe[2] = 4;
 636                 swizzle_pipe[3] = 6;
 637                 swizzle_pipe[4] = 1;
 638                 swizzle_pipe[5] = 3;
 639                 swizzle_pipe[6] = 5;
 640                 swizzle_pipe[7] = 7;
 641                 break;
 642         }
 643
 644         cur_backend = 0;
 645         for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) {
 646                 while (((1 << cur_backend) & enabled_backends_mask) == 0)
 647                         cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS;
 648
 649                 backend_map |= (u32)(((cur_backend & 3) << (swizzle_pipe[cur_pipe] * 2)));
 650
 651                 cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS;
 652         }
 653
 654         return backend_map;
 655 }
 656
 657 static int r600_count_pipe_bits(uint32_t val)
 658 {
 659         int i, ret = 0;
 660         for (i = 0; i < 32; i++) {
 661                 ret += val & 1;
 662                 val >>= 1;
 663         }
 664         return ret;
 665 }
 666
 667 static void r600_gfx_init(struct drm_device *dev,
 668                           drm_radeon_private_t *dev_priv)
 669 {
 670         int i, j, num_qd_pipes;
 671         u32 sx_debug_1;
 672         u32 tc_cntl;
 673         u32 arb_pop;
 674         u32 num_gs_verts_per_thread;
 675         u32 vgt_gs_per_es;
 676         u32 gs_prim_buffer_depth = 0;
 677         u32 sq_ms_fifo_sizes;
 678         u32 sq_config;
 679         u32 sq_gpr_resource_mgmt_1 = 0;
 680         u32 sq_gpr_resource_mgmt_2 = 0;
 681         u32 sq_thread_resource_mgmt = 0;
 682         u32 sq_stack_resource_mgmt_1 = 0;
 683         u32 sq_stack_resource_mgmt_2 = 0;
 684         u32 hdp_host_path_cntl;
 685         u32 backend_map;
 686         u32 gb_tiling_config = 0;
 687         u32 cc_rb_backend_disable = 0;
 688         u32 cc_gc_shader_pipe_config = 0;
 689         u32 ramcfg;
 690
 691         /* setup chip specs */
 692         switch (dev_priv->flags & RADEON_FAMILY_MASK) {
 693         case CHIP_R600:
 694                 dev_priv->r600_max_pipes = 4;
 695                 dev_priv->r600_max_tile_pipes = 8;
 696                 dev_priv->r600_max_simds = 4;
 697                 dev_priv->r600_max_backends = 4;
 698                 dev_priv->r600_max_gprs = 256;
 699                 dev_priv->r600_max_threads = 192;
 700                 dev_priv->r600_max_stack_entries = 256;
 701                 dev_priv->r600_max_hw_contexts = 8;
 702                 dev_priv->r600_max_gs_threads = 16;
 703                 dev_priv->r600_sx_max_export_size = 128;
 704                 dev_priv->r600_sx_max_export_pos_size = 16;
 705                 dev_priv->r600_sx_max_export_smx_size = 128;
 706                 dev_priv->r600_sq_num_cf_insts = 2;
 707                 break;
 708         case CHIP_RV630:
 709         case CHIP_RV635:
 710                 dev_priv->r600_max_pipes = 2;
 711                 dev_priv->r600_max_tile_pipes = 2;
 712                 dev_priv->r600_max_simds = 3;
 713                 dev_priv->r600_max_backends = 1;
 714                 dev_priv->r600_max_gprs = 128;
 715                 dev_priv->r600_max_threads = 192;
 716                 dev_priv->r600_max_stack_entries = 128;
 717                 dev_priv->r600_max_hw_contexts = 8;
 718                 dev_priv->r600_max_gs_threads = 4;
 719                 dev_priv->r600_sx_max_export_size = 128;
 720                 dev_priv->r600_sx_max_export_pos_size = 16;
 721                 dev_priv->r600_sx_max_export_smx_size = 128;
 722                 dev_priv->r600_sq_num_cf_insts = 2;
 723                 break;
 724         case CHIP_RV610:
 725         case CHIP_RS780:
 726         case CHIP_RS880:
 727         case CHIP_RV620:
 728                 dev_priv->r600_max_pipes = 1;
 729                 dev_priv->r600_max_tile_pipes = 1;
 730                 dev_priv->r600_max_simds = 2;
 731                 dev_priv->r600_max_backends = 1;
 732                 dev_priv->r600_max_gprs = 128;
 733                 dev_priv->r600_max_threads = 192;
 734                 dev_priv->r600_max_stack_entries = 128;
 735                 dev_priv->r600_max_hw_contexts = 4;
 736                 dev_priv->r600_max_gs_threads = 4;
 737                 dev_priv->r600_sx_max_export_size = 128;
 738                 dev_priv->r600_sx_max_export_pos_size = 16;
 739                 dev_priv->r600_sx_max_export_smx_size = 128;
 740                 dev_priv->r600_sq_num_cf_insts = 1;
 741                 break;
 742         case CHIP_RV670:
 743                 dev_priv->r600_max_pipes = 4;
 744                 dev_priv->r600_max_tile_pipes = 4;
 745                 dev_priv->r600_max_simds = 4;
 746                 dev_priv->r600_max_backends = 4;
 747                 dev_priv->r600_max_gprs = 192;
 748                 dev_priv->r600_max_threads = 192;
 749                 dev_priv->r600_max_stack_entries = 256;
 750                 dev_priv->r600_max_hw_contexts = 8;
 751                 dev_priv->r600_max_gs_threads = 16;
 752                 dev_priv->r600_sx_max_export_size = 128;
 753                 dev_priv->r600_sx_max_export_pos_size = 16;
 754                 dev_priv->r600_sx_max_export_smx_size = 128;
 755                 dev_priv->r600_sq_num_cf_insts = 2;
 756                 break;
 757         default:
 758                 break;
 759         }
 760
 761         /* Initialize HDP */
 762         j = 0;
 763         for (i = 0; i < 32; i++) {
 764                 RADEON_WRITE((0x2c14 + j), 0x00000000);
 765                 RADEON_WRITE((0x2c18 + j), 0x00000000);
 766                 RADEON_WRITE((0x2c1c + j), 0x00000000);
 767                 RADEON_WRITE((0x2c20 + j), 0x00000000);
 768                 RADEON_WRITE((0x2c24 + j), 0x00000000);
 769                 j += 0x18;
 770         }
 771
 772         RADEON_WRITE(R600_GRBM_CNTL, R600_GRBM_READ_TIMEOUT(0xff));
 773
 774         /* setup tiling, simd, pipe config */
 775         ramcfg = RADEON_READ(R600_RAMCFG);
 776
 777         switch (dev_priv->r600_max_tile_pipes) {
 778         case 1:
 779                 gb_tiling_config |= R600_PIPE_TILING(0);
 780                 break;
 781         case 2:
 782                 gb_tiling_config |= R600_PIPE_TILING(1);
 783                 break;
 784         case 4:
 785                 gb_tiling_config |= R600_PIPE_TILING(2);
 786                 break;
 787         case 8:
 788                 gb_tiling_config |= R600_PIPE_TILING(3);
 789                 break;
 790         default:
 791                 break;
 792         }
 793
 794         gb_tiling_config |= R600_BANK_TILING((ramcfg >> R600_NOOFBANK_SHIFT) & R600_NOOFBANK_MASK);
 795
 796         gb_tiling_config |= R600_GROUP_SIZE(0);
 797
 798         if (((ramcfg >> R600_NOOFROWS_SHIFT) & R600_NOOFROWS_MASK) > 3) {
 799                 gb_tiling_config |= R600_ROW_TILING(3);
 800                 gb_tiling_config |= R600_SAMPLE_SPLIT(3);
 801         } else {
 802                 gb_tiling_config |=
 803                         R600_ROW_TILING(((ramcfg >> R600_NOOFROWS_SHIFT) & R600_NOOFROWS_MASK));
 804                 gb_tiling_config |=
 805                         R600_SAMPLE_SPLIT(((ramcfg >> R600_NOOFROWS_SHIFT) & R600_NOOFROWS_MASK));
 806         }
 807
 808         gb_tiling_config |= R600_BANK_SWAPS(1);
 809
 810         backend_map = r600_get_tile_pipe_to_backend_map(dev_priv->r600_max_tile_pipes,
 811                                                         dev_priv->r600_max_backends,
 812                                                         (0xff << dev_priv->r600_max_backends) & 0xff);
 813         gb_tiling_config |= R600_BACKEND_MAP(backend_map);
 814
 815         cc_gc_shader_pipe_config =
 816                 R600_INACTIVE_QD_PIPES((R6XX_MAX_PIPES_MASK << dev_priv->r600_max_pipes) & R6XX_MAX_PIPES_MASK);
 817         cc_gc_shader_pipe_config |=
 818                 R600_INACTIVE_SIMDS((R6XX_MAX_SIMDS_MASK << dev_priv->r600_max_simds) & R6XX_MAX_SIMDS_MASK);
 819
 820         cc_rb_backend_disable =
 821                 R600_BACKEND_DISABLE((R6XX_MAX_BACKENDS_MASK << dev_priv->r600_max_backends) & R6XX_MAX_BACKENDS_MASK);
 822
 823         RADEON_WRITE(R600_GB_TILING_CONFIG,      gb_tiling_config);
 824         RADEON_WRITE(R600_DCP_TILING_CONFIG,    (gb_tiling_config & 0xffff));
 825         RADEON_WRITE(R600_HDP_TILING_CONFIG,    (gb_tiling_config & 0xffff));
 826
 827         RADEON_WRITE(R600_CC_RB_BACKEND_DISABLE,      cc_rb_backend_disable);
 828         RADEON_WRITE(R600_CC_GC_SHADER_PIPE_CONFIG,   cc_gc_shader_pipe_config);
 829         RADEON_WRITE(R600_GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
 830
 831         num_qd_pipes =
 832                 R6XX_MAX_BACKENDS - r600_count_pipe_bits(cc_gc_shader_pipe_config & R600_INACTIVE_QD_PIPES_MASK);
 833         RADEON_WRITE(R600_VGT_OUT_DEALLOC_CNTL, (num_qd_pipes * 4) & R600_DEALLOC_DIST_MASK);
 834         RADEON_WRITE(R600_VGT_VERTEX_REUSE_BLOCK_CNTL, ((num_qd_pipes * 4) - 2) & R600_VTX_REUSE_DEPTH_MASK);
 835
 836         /* set HW defaults for 3D engine */
 837         RADEON_WRITE(R600_CP_QUEUE_THRESHOLDS, (R600_ROQ_IB1_START(0x16) |
 838                                                 R600_ROQ_IB2_START(0x2b)));
 839
 840         RADEON_WRITE(R600_CP_MEQ_THRESHOLDS, (R600_MEQ_END(0x40) |
 841                                               R600_ROQ_END(0x40)));
 842
 843         RADEON_WRITE(R600_TA_CNTL_AUX, (R600_DISABLE_CUBE_ANISO |
 844                                         R600_SYNC_GRADIENT |
 845                                         R600_SYNC_WALKER |
 846                                         R600_SYNC_ALIGNER));
 847
 848         if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV670)
 849                 RADEON_WRITE(R600_ARB_GDEC_RD_CNTL, 0x00000021);
 850
 851         sx_debug_1 = RADEON_READ(R600_SX_DEBUG_1);
 852         sx_debug_1 |= R600_SMX_EVENT_RELEASE;
 853         if (((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_R600))
 854                 sx_debug_1 |= R600_ENABLE_NEW_SMX_ADDRESS;
 855         RADEON_WRITE(R600_SX_DEBUG_1, sx_debug_1);
 856
 857         if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R600) ||
 858             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV630) ||
 859             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610) ||
 860             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620) ||
 861             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780) ||
 862             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS880))
 863                 RADEON_WRITE(R600_DB_DEBUG, R600_PREZ_MUST_WAIT_FOR_POSTZ_DONE);
 864         else
 865                 RADEON_WRITE(R600_DB_DEBUG, 0);
 866
 867         RADEON_WRITE(R600_DB_WATERMARKS, (R600_DEPTH_FREE(4) |
 868                                           R600_DEPTH_FLUSH(16) |
 869                                           R600_DEPTH_PENDING_FREE(4) |
 870                                           R600_DEPTH_CACHELINE_FREE(16)));
 871         RADEON_WRITE(R600_PA_SC_MULTI_CHIP_CNTL, 0);
 872         RADEON_WRITE(R600_VGT_NUM_INSTANCES, 0);
 873
 874         RADEON_WRITE(R600_SPI_CONFIG_CNTL, R600_GPR_WRITE_PRIORITY(0));
 875         RADEON_WRITE(R600_SPI_CONFIG_CNTL_1, R600_VTX_DONE_DELAY(0));
 876
 877         sq_ms_fifo_sizes = RADEON_READ(R600_SQ_MS_FIFO_SIZES);
 878         if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610) ||
 879             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620) ||
 880             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780) ||
 881             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS880)) {
 882                 sq_ms_fifo_sizes = (R600_CACHE_FIFO_SIZE(0xa) |
 883                                     R600_FETCH_FIFO_HIWATER(0xa) |
 884                                     R600_DONE_FIFO_HIWATER(0xe0) |
 885                                     R600_ALU_UPDATE_FIFO_HIWATER(0x8));
 886         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R600) ||
 887                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV630)) {
 888                 sq_ms_fifo_sizes &= ~R600_DONE_FIFO_HIWATER(0xff);
 889                 sq_ms_fifo_sizes |= R600_DONE_FIFO_HIWATER(0x4);
 890         }
 891         RADEON_WRITE(R600_SQ_MS_FIFO_SIZES, sq_ms_fifo_sizes);
 892
 893         /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT
 894          * should be adjusted as needed by the 2D/3D drivers.  This just sets default values
 895          */
 896         sq_config = RADEON_READ(R600_SQ_CONFIG);
 897         sq_config &= ~(R600_PS_PRIO(3) |
 898                        R600_VS_PRIO(3) |
 899                        R600_GS_PRIO(3) |
 900                        R600_ES_PRIO(3));
 901         sq_config |= (R600_DX9_CONSTS |
 902                       R600_VC_ENABLE |
 903                       R600_PS_PRIO(0) |
 904                       R600_VS_PRIO(1) |
 905                       R600_GS_PRIO(2) |
 906                       R600_ES_PRIO(3));
 907
 908         if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R600) {
 909                 sq_gpr_resource_mgmt_1 = (R600_NUM_PS_GPRS(124) |
 910                                           R600_NUM_VS_GPRS(124) |
 911                                           R600_NUM_CLAUSE_TEMP_GPRS(4));
 912                 sq_gpr_resource_mgmt_2 = (R600_NUM_GS_GPRS(0) |
 913                                           R600_NUM_ES_GPRS(0));
 914                 sq_thread_resource_mgmt = (R600_NUM_PS_THREADS(136) |
 915                                            R600_NUM_VS_THREADS(48) |
 916                                            R600_NUM_GS_THREADS(4) |
 917                                            R600_NUM_ES_THREADS(4));
 918                 sq_stack_resource_mgmt_1 = (R600_NUM_PS_STACK_ENTRIES(128) |
 919                                             R600_NUM_VS_STACK_ENTRIES(128));
 920                 sq_stack_resource_mgmt_2 = (R600_NUM_GS_STACK_ENTRIES(0) |
 921                                             R600_NUM_ES_STACK_ENTRIES(0));
 922         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610) ||
 923                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620) ||
 924                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780) ||
 925                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS880)) {
 926                 /* no vertex cache */
 927                 sq_config &= ~R600_VC_ENABLE;
 928
 929                 sq_gpr_resource_mgmt_1 = (R600_NUM_PS_GPRS(44) |
 930                                           R600_NUM_VS_GPRS(44) |
 931                                           R600_NUM_CLAUSE_TEMP_GPRS(2));
 932                 sq_gpr_resource_mgmt_2 = (R600_NUM_GS_GPRS(17) |
 933                                           R600_NUM_ES_GPRS(17));
 934                 sq_thread_resource_mgmt = (R600_NUM_PS_THREADS(79) |
 935                                            R600_NUM_VS_THREADS(78) |
 936                                            R600_NUM_GS_THREADS(4) |
 937                                            R600_NUM_ES_THREADS(31));
 938                 sq_stack_resource_mgmt_1 = (R600_NUM_PS_STACK_ENTRIES(40) |
 939                                             R600_NUM_VS_STACK_ENTRIES(40));
 940                 sq_stack_resource_mgmt_2 = (R600_NUM_GS_STACK_ENTRIES(32) |
 941                                             R600_NUM_ES_STACK_ENTRIES(16));
 942         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV630) ||
 943                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV635)) {
 944                 sq_gpr_resource_mgmt_1 = (R600_NUM_PS_GPRS(44) |
 945                                           R600_NUM_VS_GPRS(44) |
 946                                           R600_NUM_CLAUSE_TEMP_GPRS(2));
 947                 sq_gpr_resource_mgmt_2 = (R600_NUM_GS_GPRS(18) |
 948                                           R600_NUM_ES_GPRS(18));
 949                 sq_thread_resource_mgmt = (R600_NUM_PS_THREADS(79) |
 950                                            R600_NUM_VS_THREADS(78) |
 951                                            R600_NUM_GS_THREADS(4) |
 952                                            R600_NUM_ES_THREADS(31));
 953                 sq_stack_resource_mgmt_1 = (R600_NUM_PS_STACK_ENTRIES(40) |
 954                                             R600_NUM_VS_STACK_ENTRIES(40));
 955                 sq_stack_resource_mgmt_2 = (R600_NUM_GS_STACK_ENTRIES(32) |
 956                                             R600_NUM_ES_STACK_ENTRIES(16));
 957         } else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV670) {
 958                 sq_gpr_resource_mgmt_1 = (R600_NUM_PS_GPRS(44) |
 959                                           R600_NUM_VS_GPRS(44) |
 960                                           R600_NUM_CLAUSE_TEMP_GPRS(2));
 961                 sq_gpr_resource_mgmt_2 = (R600_NUM_GS_GPRS(17) |
 962                                           R600_NUM_ES_GPRS(17));
 963                 sq_thread_resource_mgmt = (R600_NUM_PS_THREADS(79) |
 964                                            R600_NUM_VS_THREADS(78) |
 965                                            R600_NUM_GS_THREADS(4) |
 966                                            R600_NUM_ES_THREADS(31));
 967                 sq_stack_resource_mgmt_1 = (R600_NUM_PS_STACK_ENTRIES(64) |
 968                                             R600_NUM_VS_STACK_ENTRIES(64));
 969                 sq_stack_resource_mgmt_2 = (R600_NUM_GS_STACK_ENTRIES(64) |
 970                                             R600_NUM_ES_STACK_ENTRIES(64));
 971         }
 972
 973         RADEON_WRITE(R600_SQ_CONFIG, sq_config);
 974         RADEON_WRITE(R600_SQ_GPR_RESOURCE_MGMT_1,  sq_gpr_resource_mgmt_1);
 975         RADEON_WRITE(R600_SQ_GPR_RESOURCE_MGMT_2,  sq_gpr_resource_mgmt_2);
 976         RADEON_WRITE(R600_SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
 977         RADEON_WRITE(R600_SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1);
 978         RADEON_WRITE(R600_SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2);
 979
 980         if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610) ||
 981             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620) ||
 982             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780) ||
 983             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS880))
 984                 RADEON_WRITE(R600_VGT_CACHE_INVALIDATION, R600_CACHE_INVALIDATION(R600_TC_ONLY));
 985         else
 986                 RADEON_WRITE(R600_VGT_CACHE_INVALIDATION, R600_CACHE_INVALIDATION(R600_VC_AND_TC));
 987
 988         RADEON_WRITE(R600_PA_SC_AA_SAMPLE_LOCS_2S, (R600_S0_X(0xc) |
 989                                                     R600_S0_Y(0x4) |
 990                                                     R600_S1_X(0x4) |
 991                                                     R600_S1_Y(0xc)));
 992         RADEON_WRITE(R600_PA_SC_AA_SAMPLE_LOCS_4S, (R600_S0_X(0xe) |
 993                                                     R600_S0_Y(0xe) |
 994                                                     R600_S1_X(0x2) |
 995                                                     R600_S1_Y(0x2) |
 996                                                     R600_S2_X(0xa) |
 997                                                     R600_S2_Y(0x6) |
 998                                                     R600_S3_X(0x6) |
 999                                                     R600_S3_Y(0xa)));
1000         RADEON_WRITE(R600_PA_SC_AA_SAMPLE_LOCS_8S_WD0, (R600_S0_X(0xe) |
1001                                                         R600_S0_Y(0xb) |
1002                                                         R600_S1_X(0x4) |
1003                                                         R600_S1_Y(0xc) |
1004                                                         R600_S2_X(0x1) |
1005                                                         R600_S2_Y(0x6) |
1006                                                         R600_S3_X(0xa) |
1007                                                         R600_S3_Y(0xe)));
1008         RADEON_WRITE(R600_PA_SC_AA_SAMPLE_LOCS_8S_WD1, (R600_S4_X(0x6) |
1009                                                         R600_S4_Y(0x1) |
1010                                                         R600_S5_X(0x0) |
1011                                                         R600_S5_Y(0x0) |
1012                                                         R600_S6_X(0xb) |
1013                                                         R600_S6_Y(0x4) |
1014                                                         R600_S7_X(0x7) |
1015                                                         R600_S7_Y(0x8)));
1016
1017
1018         switch (dev_priv->flags & RADEON_FAMILY_MASK) {
1019         case CHIP_R600:
1020         case CHIP_RV630:
1021         case CHIP_RV635:
1022                 gs_prim_buffer_depth = 0;
1023                 break;
1024         case CHIP_RV610:
1025         case CHIP_RS780:
1026         case CHIP_RS880:
1027         case CHIP_RV620:
1028                 gs_prim_buffer_depth = 32;
1029                 break;
1030         case CHIP_RV670:
1031                 gs_prim_buffer_depth = 128;
1032                 break;
1033         default:
1034                 break;
1035         }
1036
1037         num_gs_verts_per_thread = dev_priv->r600_max_pipes * 16;
1038         vgt_gs_per_es = gs_prim_buffer_depth + num_gs_verts_per_thread;
1039         /* Max value for this is 256 */
1040         if (vgt_gs_per_es > 256)
1041                 vgt_gs_per_es = 256;
1042
1043         RADEON_WRITE(R600_VGT_ES_PER_GS, 128);
1044         RADEON_WRITE(R600_VGT_GS_PER_ES, vgt_gs_per_es);
1045         RADEON_WRITE(R600_VGT_GS_PER_VS, 2);
1046         RADEON_WRITE(R600_VGT_GS_VERTEX_REUSE, 16);
1047
1048         /* more default values. 2D/3D driver should adjust as needed */
1049         RADEON_WRITE(R600_PA_SC_LINE_STIPPLE_STATE, 0);
1050         RADEON_WRITE(R600_VGT_STRMOUT_EN, 0);
1051         RADEON_WRITE(R600_SX_MISC, 0);
1052         RADEON_WRITE(R600_PA_SC_MODE_CNTL, 0);
1053         RADEON_WRITE(R600_PA_SC_AA_CONFIG, 0);
1054         RADEON_WRITE(R600_PA_SC_LINE_STIPPLE, 0);
1055         RADEON_WRITE(R600_SPI_INPUT_Z, 0);
1056         RADEON_WRITE(R600_SPI_PS_IN_CONTROL_0, R600_NUM_INTERP(2));
1057         RADEON_WRITE(R600_CB_COLOR7_FRAG, 0);
1058
1059         /* clear render buffer base addresses */
1060         RADEON_WRITE(R600_CB_COLOR0_BASE, 0);
1061         RADEON_WRITE(R600_CB_COLOR1_BASE, 0);
1062         RADEON_WRITE(R600_CB_COLOR2_BASE, 0);
1063         RADEON_WRITE(R600_CB_COLOR3_BASE, 0);
1064         RADEON_WRITE(R600_CB_COLOR4_BASE, 0);
1065         RADEON_WRITE(R600_CB_COLOR5_BASE, 0);
1066         RADEON_WRITE(R600_CB_COLOR6_BASE, 0);
1067         RADEON_WRITE(R600_CB_COLOR7_BASE, 0);
1068
1069         switch (dev_priv->flags & RADEON_FAMILY_MASK) {
1070         case CHIP_RV610:
1071         case CHIP_RS780:
1072         case CHIP_RS880:
1073         case CHIP_RV620:
1074                 tc_cntl = R600_TC_L2_SIZE(8);
1075                 break;
1076         case CHIP_RV630:
1077         case CHIP_RV635:
1078                 tc_cntl = R600_TC_L2_SIZE(4);
1079                 break;
1080         case CHIP_R600:
1081                 tc_cntl = R600_TC_L2_SIZE(0) | R600_L2_DISABLE_LATE_HIT;
1082                 break;
1083         default:
1084                 tc_cntl = R600_TC_L2_SIZE(0);
1085                 break;
1086         }
1087
1088         RADEON_WRITE(R600_TC_CNTL, tc_cntl);
1089
1090         hdp_host_path_cntl = RADEON_READ(R600_HDP_HOST_PATH_CNTL);
1091         RADEON_WRITE(R600_HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
1092
1093         arb_pop = RADEON_READ(R600_ARB_POP);
1094         arb_pop |= R600_ENABLE_TC128;
1095         RADEON_WRITE(R600_ARB_POP, arb_pop);
1096
1097         RADEON_WRITE(R600_PA_SC_MULTI_CHIP_CNTL, 0);
1098         RADEON_WRITE(R600_PA_CL_ENHANCE, (R600_CLIP_VTX_REORDER_ENA |
1099                                           R600_NUM_CLIP_SEQ(3)));
1100         RADEON_WRITE(R600_PA_SC_ENHANCE, R600_FORCE_EOV_MAX_CLK_CNT(4095));
1101
1102 }
1103
1104 static u32 r700_get_tile_pipe_to_backend_map(u32 num_tile_pipes,
1105                                              u32 num_backends,
1106                                              u32 backend_disable_mask)
1107 {
1108         u32 backend_map = 0;
1109         u32 enabled_backends_mask;
1110         u32 enabled_backends_count;
1111         u32 cur_pipe;
1112         u32 swizzle_pipe[R7XX_MAX_PIPES];
1113         u32 cur_backend;
1114         u32 i;
1115
1116         if (num_tile_pipes > R7XX_MAX_PIPES)
1117                 num_tile_pipes = R7XX_MAX_PIPES;
1118         if (num_tile_pipes < 1)
1119                 num_tile_pipes = 1;
1120         if (num_backends > R7XX_MAX_BACKENDS)
1121                 num_backends = R7XX_MAX_BACKENDS;
1122         if (num_backends < 1)
1123                 num_backends = 1;
1124
1125         enabled_backends_mask = 0;
1126         enabled_backends_count = 0;
1127         for (i = 0; i < R7XX_MAX_BACKENDS; ++i) {
1128                 if (((backend_disable_mask >> i) & 1) == 0) {
1129                         enabled_backends_mask |= (1 << i);
1130                         ++enabled_backends_count;
1131                 }
1132                 if (enabled_backends_count == num_backends)
1133                         break;
1134         }
1135
1136         if (enabled_backends_count == 0) {
1137                 enabled_backends_mask = 1;
1138                 enabled_backends_count = 1;
1139         }
1140
1141         if (enabled_backends_count != num_backends)
1142                 num_backends = enabled_backends_count;
1143
1144         memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * R7XX_MAX_PIPES);
1145         switch (num_tile_pipes) {
1146         case 1:
1147                 swizzle_pipe[0] = 0;
1148                 break;
1149         case 2:
1150                 swizzle_pipe[0] = 0;
1151                 swizzle_pipe[1] = 1;
1152                 break;
1153         case 3:
1154                 swizzle_pipe[0] = 0;
1155                 swizzle_pipe[1] = 2;
1156                 swizzle_pipe[2] = 1;
1157                 break;
1158         case 4:
1159                 swizzle_pipe[0] = 0;
1160                 swizzle_pipe[1] = 2;
1161                 swizzle_pipe[2] = 3;
1162                 swizzle_pipe[3] = 1;
1163                 break;
1164         case 5:
1165                 swizzle_pipe[0] = 0;
1166                 swizzle_pipe[1] = 2;
1167                 swizzle_pipe[2] = 4;
1168                 swizzle_pipe[3] = 1;
1169                 swizzle_pipe[4] = 3;
1170                 break;
1171         case 6:
1172                 swizzle_pipe[0] = 0;
1173                 swizzle_pipe[1] = 2;
1174                 swizzle_pipe[2] = 4;
1175                 swizzle_pipe[3] = 5;
1176                 swizzle_pipe[4] = 3;
1177                 swizzle_pipe[5] = 1;
1178                 break;
1179         case 7:
1180                 swizzle_pipe[0] = 0;
1181                 swizzle_pipe[1] = 2;
1182                 swizzle_pipe[2] = 4;
1183                 swizzle_pipe[3] = 6;
1184                 swizzle_pipe[4] = 3;
1185                 swizzle_pipe[5] = 1;
1186                 swizzle_pipe[6] = 5;
1187                 break;
1188         case 8:
1189                 swizzle_pipe[0] = 0;
1190                 swizzle_pipe[1] = 2;
1191                 swizzle_pipe[2] = 4;
1192                 swizzle_pipe[3] = 6;
1193                 swizzle_pipe[4] = 3;
1194                 swizzle_pipe[5] = 1;
1195                 swizzle_pipe[6] = 7;
1196                 swizzle_pipe[7] = 5;
1197                 break;
1198         }
1199
1200         cur_backend = 0;
1201         for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) {
1202                 while (((1 << cur_backend) & enabled_backends_mask) == 0)
1203                         cur_backend = (cur_backend + 1) % R7XX_MAX_BACKENDS;
1204
1205                 backend_map |= (u32)(((cur_backend & 3) << (swizzle_pipe[cur_pipe] * 2)));
1206
1207                 cur_backend = (cur_backend + 1) % R7XX_MAX_BACKENDS;
1208         }
1209
1210         return backend_map;
1211 }
1212
1213 static void r700_gfx_init(struct drm_device *dev,
1214                           drm_radeon_private_t *dev_priv)
1215 {
1216         int i, j, num_qd_pipes;
1217         u32 sx_debug_1;
1218         u32 smx_dc_ctl0;
1219         u32 num_gs_verts_per_thread;
1220         u32 vgt_gs_per_es;
1221         u32 gs_prim_buffer_depth = 0;
1222         u32 sq_ms_fifo_sizes;
1223         u32 sq_config;
1224         u32 sq_thread_resource_mgmt;
1225         u32 hdp_host_path_cntl;
1226         u32 sq_dyn_gpr_size_simd_ab_0;
1227         u32 backend_map;
1228         u32 gb_tiling_config = 0;
1229         u32 cc_rb_backend_disable = 0;
1230         u32 cc_gc_shader_pipe_config = 0;
1231         u32 mc_arb_ramcfg;
1232         u32 db_debug4;
1233
1234         /* setup chip specs */
1235         switch (dev_priv->flags & RADEON_FAMILY_MASK) {
1236         case CHIP_RV770:
1237                 dev_priv->r600_max_pipes = 4;
1238                 dev_priv->r600_max_tile_pipes = 8;
1239                 dev_priv->r600_max_simds = 10;
1240                 dev_priv->r600_max_backends = 4;
1241                 dev_priv->r600_max_gprs = 256;
1242                 dev_priv->r600_max_threads = 248;
1243                 dev_priv->r600_max_stack_entries = 512;
1244                 dev_priv->r600_max_hw_contexts = 8;
1245                 dev_priv->r600_max_gs_threads = 16 * 2;
1246                 dev_priv->r600_sx_max_export_size = 128;
1247                 dev_priv->r600_sx_max_export_pos_size = 16;
1248                 dev_priv->r600_sx_max_export_smx_size = 112;
1249                 dev_priv->r600_sq_num_cf_insts = 2;
1250
1251                 dev_priv->r700_sx_num_of_sets = 7;
1252                 dev_priv->r700_sc_prim_fifo_size = 0xF9;
1253                 dev_priv->r700_sc_hiz_tile_fifo_size = 0x30;
1254                 dev_priv->r700_sc_earlyz_tile_fifo_fize = 0x130;
1255                 break;
1256         case CHIP_RV740:
1257                 dev_priv->r600_max_pipes = 4;
1258                 dev_priv->r600_max_tile_pipes = 4;
1259                 dev_priv->r600_max_simds = 8;
1260                 dev_priv->r600_max_backends = 4;
1261                 dev_priv->r600_max_gprs = 256;
1262                 dev_priv->r600_max_threads = 248;
1263                 dev_priv->r600_max_stack_entries = 512;
1264                 dev_priv->r600_max_hw_contexts = 8;
1265                 dev_priv->r600_max_gs_threads = 16 * 2;
1266                 dev_priv->r600_sx_max_export_size = 256;
1267                 dev_priv->r600_sx_max_export_pos_size = 32;
1268                 dev_priv->r600_sx_max_export_smx_size = 224;
1269                 dev_priv->r600_sq_num_cf_insts = 2;
1270
1271                 dev_priv->r700_sx_num_of_sets = 7;
1272                 dev_priv->r700_sc_prim_fifo_size = 0x100;
1273                 dev_priv->r700_sc_hiz_tile_fifo_size = 0x30;
1274                 dev_priv->r700_sc_earlyz_tile_fifo_fize = 0x130;
1275
1276                 if (dev_priv->r600_sx_max_export_pos_size > 16) {
1277                         dev_priv->r600_sx_max_export_pos_size -= 16;
1278                         dev_priv->r600_sx_max_export_smx_size += 16;
1279                 }
1280                 break;
1281         case CHIP_RV730:
1282                 dev_priv->r600_max_pipes = 2;
1283                 dev_priv->r600_max_tile_pipes = 4;
1284                 dev_priv->r600_max_simds = 8;
1285                 dev_priv->r600_max_backends = 2;
1286                 dev_priv->r600_max_gprs = 128;
1287                 dev_priv->r600_max_threads = 248;
1288                 dev_priv->r600_max_stack_entries = 256;
1289                 dev_priv->r600_max_hw_contexts = 8;
1290                 dev_priv->r600_max_gs_threads = 16 * 2;
1291                 dev_priv->r600_sx_max_export_size = 256;
1292                 dev_priv->r600_sx_max_export_pos_size = 32;
1293                 dev_priv->r600_sx_max_export_smx_size = 224;
1294                 dev_priv->r600_sq_num_cf_insts = 2;
1295
1296                 dev_priv->r700_sx_num_of_sets = 7;
1297                 dev_priv->r700_sc_prim_fifo_size = 0xf9;
1298                 dev_priv->r700_sc_hiz_tile_fifo_size = 0x30;
1299                 dev_priv->r700_sc_earlyz_tile_fifo_fize = 0x130;
1300
1301                 if (dev_priv->r600_sx_max_export_pos_size > 16) {
1302                         dev_priv->r600_sx_max_export_pos_size -= 16;
1303                         dev_priv->r600_sx_max_export_smx_size += 16;
1304                 }
1305                 break;
1306         case CHIP_RV710:
1307                 dev_priv->r600_max_pipes = 2;
1308                 dev_priv->r600_max_tile_pipes = 2;
1309                 dev_priv->r600_max_simds = 2;
1310                 dev_priv->r600_max_backends = 1;
1311                 dev_priv->r600_max_gprs = 256;
1312                 dev_priv->r600_max_threads = 192;
1313                 dev_priv->r600_max_stack_entries = 256;
1314                 dev_priv->r600_max_hw_contexts = 4;
1315                 dev_priv->r600_max_gs_threads = 8 * 2;
1316                 dev_priv->r600_sx_max_export_size = 128;
1317                 dev_priv->r600_sx_max_export_pos_size = 16;
1318                 dev_priv->r600_sx_max_export_smx_size = 112;
1319                 dev_priv->r600_sq_num_cf_insts = 1;
1320
1321                 dev_priv->r700_sx_num_of_sets = 7;
1322                 dev_priv->r700_sc_prim_fifo_size = 0x40;
1323                 dev_priv->r700_sc_hiz_tile_fifo_size = 0x30;
1324                 dev_priv->r700_sc_earlyz_tile_fifo_fize = 0x130;
1325                 break;
1326         default:
1327                 break;
1328         }
1329
1330         /* Initialize HDP */
1331         j = 0;
1332         for (i = 0; i < 32; i++) {
1333                 RADEON_WRITE((0x2c14 + j), 0x00000000);
1334                 RADEON_WRITE((0x2c18 + j), 0x00000000);
1335                 RADEON_WRITE((0x2c1c + j), 0x00000000);
1336                 RADEON_WRITE((0x2c20 + j), 0x00000000);
1337                 RADEON_WRITE((0x2c24 + j), 0x00000000);
1338                 j += 0x18;
1339         }
1340
1341         RADEON_WRITE(R600_GRBM_CNTL, R600_GRBM_READ_TIMEOUT(0xff));
1342
1343         /* setup tiling, simd, pipe config */
1344         mc_arb_ramcfg = RADEON_READ(R700_MC_ARB_RAMCFG);
1345
1346         switch (dev_priv->r600_max_tile_pipes) {
1347         case 1:
1348                 gb_tiling_config |= R600_PIPE_TILING(0);
1349                 break;
1350         case 2:
1351                 gb_tiling_config |= R600_PIPE_TILING(1);
1352                 break;
1353         case 4:
1354                 gb_tiling_config |= R600_PIPE_TILING(2);
1355                 break;
1356         case 8:
1357                 gb_tiling_config |= R600_PIPE_TILING(3);
1358                 break;
1359         default:
1360                 break;
1361         }
1362
1363         if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV770)
1364                 gb_tiling_config |= R600_BANK_TILING(1);
1365         else
1366                 gb_tiling_config |= R600_BANK_TILING((mc_arb_ramcfg >> R700_NOOFBANK_SHIFT) & R700_NOOFBANK_MASK);
1367
1368         gb_tiling_config |= R600_GROUP_SIZE(0);
1369
1370         if (((mc_arb_ramcfg >> R700_NOOFROWS_SHIFT) & R700_NOOFROWS_MASK) > 3) {
1371                 gb_tiling_config |= R600_ROW_TILING(3);
1372                 gb_tiling_config |= R600_SAMPLE_SPLIT(3);
1373         } else {
1374                 gb_tiling_config |=
1375                         R600_ROW_TILING(((mc_arb_ramcfg >> R700_NOOFROWS_SHIFT) & R700_NOOFROWS_MASK));
1376                 gb_tiling_config |=
1377                         R600_SAMPLE_SPLIT(((mc_arb_ramcfg >> R700_NOOFROWS_SHIFT) & R700_NOOFROWS_MASK));
1378         }
1379
1380         gb_tiling_config |= R600_BANK_SWAPS(1);
1381
1382         backend_map = r700_get_tile_pipe_to_backend_map(dev_priv->r600_max_tile_pipes,
1383                                                         dev_priv->r600_max_backends,
1384                                                         (0xff << dev_priv->r600_max_backends) & 0xff);
1385         gb_tiling_config |= R600_BACKEND_MAP(backend_map);
1386
1387         cc_gc_shader_pipe_config =
1388                 R600_INACTIVE_QD_PIPES((R7XX_MAX_PIPES_MASK << dev_priv->r600_max_pipes) & R7XX_MAX_PIPES_MASK);
1389         cc_gc_shader_pipe_config |=
1390                 R600_INACTIVE_SIMDS((R7XX_MAX_SIMDS_MASK << dev_priv->r600_max_simds) & R7XX_MAX_SIMDS_MASK);
1391
1392         cc_rb_backend_disable =
1393                 R600_BACKEND_DISABLE((R7XX_MAX_BACKENDS_MASK << dev_priv->r600_max_backends) & R7XX_MAX_BACKENDS_MASK);
1394
1395         RADEON_WRITE(R600_GB_TILING_CONFIG,      gb_tiling_config);
1396         RADEON_WRITE(R600_DCP_TILING_CONFIG,    (gb_tiling_config & 0xffff));
1397         RADEON_WRITE(R600_HDP_TILING_CONFIG,    (gb_tiling_config & 0xffff));
1398
1399         RADEON_WRITE(R600_CC_RB_BACKEND_DISABLE,      cc_rb_backend_disable);
1400         RADEON_WRITE(R600_CC_GC_SHADER_PIPE_CONFIG,   cc_gc_shader_pipe_config);
1401         RADEON_WRITE(R600_GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
1402
1403         RADEON_WRITE(R700_CC_SYS_RB_BACKEND_DISABLE, cc_rb_backend_disable);
1404         RADEON_WRITE(R700_CGTS_SYS_TCC_DISABLE, 0);
1405         RADEON_WRITE(R700_CGTS_TCC_DISABLE, 0);
1406         RADEON_WRITE(R700_CGTS_USER_SYS_TCC_DISABLE, 0);
1407         RADEON_WRITE(R700_CGTS_USER_TCC_DISABLE, 0);
1408
1409         num_qd_pipes =
1410                 R7XX_MAX_BACKENDS - r600_count_pipe_bits(cc_gc_shader_pipe_config & R600_INACTIVE_QD_PIPES_MASK);
1411         RADEON_WRITE(R600_VGT_OUT_DEALLOC_CNTL, (num_qd_pipes * 4) & R600_DEALLOC_DIST_MASK);
1412         RADEON_WRITE(R600_VGT_VERTEX_REUSE_BLOCK_CNTL, ((num_qd_pipes * 4) - 2) & R600_VTX_REUSE_DEPTH_MASK);
1413
1414         /* set HW defaults for 3D engine */
1415         RADEON_WRITE(R600_CP_QUEUE_THRESHOLDS, (R600_ROQ_IB1_START(0x16) |
1416                                                 R600_ROQ_IB2_START(0x2b)));
1417
1418         RADEON_WRITE(R600_CP_MEQ_THRESHOLDS, R700_STQ_SPLIT(0x30));
1419
1420         RADEON_WRITE(R600_TA_CNTL_AUX, (R600_DISABLE_CUBE_ANISO |
1421                                         R600_SYNC_GRADIENT |
1422                                         R600_SYNC_WALKER |
1423                                         R600_SYNC_ALIGNER));
1424
1425         sx_debug_1 = RADEON_READ(R700_SX_DEBUG_1);
1426         sx_debug_1 |= R700_ENABLE_NEW_SMX_ADDRESS;
1427         RADEON_WRITE(R700_SX_DEBUG_1, sx_debug_1);
1428
1429         smx_dc_ctl0 = RADEON_READ(R600_SMX_DC_CTL0);
1430         smx_dc_ctl0 &= ~R700_CACHE_DEPTH(0x1ff);
1431         smx_dc_ctl0 |= R700_CACHE_DEPTH((dev_priv->r700_sx_num_of_sets * 64) - 1);
1432         RADEON_WRITE(R600_SMX_DC_CTL0, smx_dc_ctl0);
1433
1434         RADEON_WRITE(R700_SMX_EVENT_CTL, (R700_ES_FLUSH_CTL(4) |
1435                                           R700_GS_FLUSH_CTL(4) |
1436                                           R700_ACK_FLUSH_CTL(3) |
1437                                           R700_SYNC_FLUSH_CTL));
1438
1439         if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV770)
1440                 RADEON_WRITE(R700_DB_DEBUG3, R700_DB_CLK_OFF_DELAY(0x1f));
1441         else {
1442                 db_debug4 = RADEON_READ(RV700_DB_DEBUG4);
1443                 db_debug4 |= RV700_DISABLE_TILE_COVERED_FOR_PS_ITER;
1444                 RADEON_WRITE(RV700_DB_DEBUG4, db_debug4);
1445         }
1446
1447         RADEON_WRITE(R600_SX_EXPORT_BUFFER_SIZES, (R600_COLOR_BUFFER_SIZE((dev_priv->r600_sx_max_export_size / 4) - 1) |
1448                                                    R600_POSITION_BUFFER_SIZE((dev_priv->r600_sx_max_export_pos_size / 4) - 1) |
1449                                                    R600_SMX_BUFFER_SIZE((dev_priv->r600_sx_max_export_smx_size / 4) - 1)));
1450
1451         RADEON_WRITE(R700_PA_SC_FIFO_SIZE_R7XX, (R700_SC_PRIM_FIFO_SIZE(dev_priv->r700_sc_prim_fifo_size) |
1452                                                  R700_SC_HIZ_TILE_FIFO_SIZE(dev_priv->r700_sc_hiz_tile_fifo_size) |
1453                                                  R700_SC_EARLYZ_TILE_FIFO_SIZE(dev_priv->r700_sc_earlyz_tile_fifo_fize)));
1454
1455         RADEON_WRITE(R600_PA_SC_MULTI_CHIP_CNTL, 0);
1456
1457         RADEON_WRITE(R600_VGT_NUM_INSTANCES, 1);
1458
1459         RADEON_WRITE(R600_SPI_CONFIG_CNTL, R600_GPR_WRITE_PRIORITY(0));
1460
1461         RADEON_WRITE(R600_SPI_CONFIG_CNTL_1, R600_VTX_DONE_DELAY(4));
1462
1463         RADEON_WRITE(R600_CP_PERFMON_CNTL, 0);
1464
1465         sq_ms_fifo_sizes = (R600_CACHE_FIFO_SIZE(16 * dev_priv->r600_sq_num_cf_insts) |
1466                             R600_DONE_FIFO_HIWATER(0xe0) |
1467                             R600_ALU_UPDATE_FIFO_HIWATER(0x8));
1468         switch (dev_priv->flags & RADEON_FAMILY_MASK) {
1469         case CHIP_RV770:
1470                 sq_ms_fifo_sizes |= R600_FETCH_FIFO_HIWATER(0x1);
1471                 break;
1472         case CHIP_RV740:
1473         case CHIP_RV730:
1474         case CHIP_RV710:
1475         default:
1476                 sq_ms_fifo_sizes |= R600_FETCH_FIFO_HIWATER(0x4);
1477                 break;
1478         }
1479         RADEON_WRITE(R600_SQ_MS_FIFO_SIZES, sq_ms_fifo_sizes);
1480
1481         /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT
1482          * should be adjusted as needed by the 2D/3D drivers.  This just sets default values
1483          */
1484         sq_config = RADEON_READ(R600_SQ_CONFIG);
1485         sq_config &= ~(R600_PS_PRIO(3) |
1486                        R600_VS_PRIO(3) |
1487                        R600_GS_PRIO(3) |
1488                        R600_ES_PRIO(3));
1489         sq_config |= (R600_DX9_CONSTS |
1490                       R600_VC_ENABLE |
1491                       R600_EXPORT_SRC_C |
1492                       R600_PS_PRIO(0) |
1493                       R600_VS_PRIO(1) |
1494                       R600_GS_PRIO(2) |
1495                       R600_ES_PRIO(3));
1496         if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV710)
1497                 /* no vertex cache */
1498                 sq_config &= ~R600_VC_ENABLE;
1499
1500         RADEON_WRITE(R600_SQ_CONFIG, sq_config);
1501
1502         RADEON_WRITE(R600_SQ_GPR_RESOURCE_MGMT_1,  (R600_NUM_PS_GPRS((dev_priv->r600_max_gprs * 24)/64) |
1503                                                     R600_NUM_VS_GPRS((dev_priv->r600_max_gprs * 24)/64) |
1504                                                     R600_NUM_CLAUSE_TEMP_GPRS(((dev_priv->r600_max_gprs * 24)/64)/2)));
1505
1506         RADEON_WRITE(R600_SQ_GPR_RESOURCE_MGMT_2,  (R600_NUM_GS_GPRS((dev_priv->r600_max_gprs * 7)/64) |
1507                                                     R600_NUM_ES_GPRS((dev_priv->r600_max_gprs * 7)/64)));
1508
1509         sq_thread_resource_mgmt = (R600_NUM_PS_THREADS((dev_priv->r600_max_threads * 4)/8) |
1510                                    R600_NUM_VS_THREADS((dev_priv->r600_max_threads * 2)/8) |
1511                                    R600_NUM_ES_THREADS((dev_priv->r600_max_threads * 1)/8));
1512         if (((dev_priv->r600_max_threads * 1) / 8) > dev_priv->r600_max_gs_threads)
1513                 sq_thread_resource_mgmt |= R600_NUM_GS_THREADS(dev_priv->r600_max_gs_threads);
1514         else
1515                 sq_thread_resource_mgmt |= R600_NUM_GS_THREADS((dev_priv->r600_max_gs_threads * 1)/8);
1516         RADEON_WRITE(R600_SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
1517
1518         RADEON_WRITE(R600_SQ_STACK_RESOURCE_MGMT_1, (R600_NUM_PS_STACK_ENTRIES((dev_priv->r600_max_stack_entries * 1)/4) |
1519                                                      R600_NUM_VS_STACK_ENTRIES((dev_priv->r600_max_stack_entries * 1)/4)));
1520
1521         RADEON_WRITE(R600_SQ_STACK_RESOURCE_MGMT_2, (R600_NUM_GS_STACK_ENTRIES((dev_priv->r600_max_stack_entries * 1)/4) |
1522                                                      R600_NUM_ES_STACK_ENTRIES((dev_priv->r600_max_stack_entries * 1)/4)));
1523
1524         sq_dyn_gpr_size_simd_ab_0 = (R700_SIMDA_RING0((dev_priv->r600_max_gprs * 38)/64) |
1525                                      R700_SIMDA_RING1((dev_priv->r600_max_gprs * 38)/64) |
1526                                      R700_SIMDB_RING0((dev_priv->r600_max_gprs * 38)/64) |
1527                                      R700_SIMDB_RING1((dev_priv->r600_max_gprs * 38)/64));
1528
1529         RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_0, sq_dyn_gpr_size_simd_ab_0);
1530         RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_1, sq_dyn_gpr_size_simd_ab_0);
1531         RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_2, sq_dyn_gpr_size_simd_ab_0);
1532         RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_3, sq_dyn_gpr_size_simd_ab_0);
1533         RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_4, sq_dyn_gpr_size_simd_ab_0);
1534         RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_5, sq_dyn_gpr_size_simd_ab_0);
1535         RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_6, sq_dyn_gpr_size_simd_ab_0);
1536         RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_7, sq_dyn_gpr_size_simd_ab_0);
1537
1538         RADEON_WRITE(R700_PA_SC_FORCE_EOV_MAX_CNTS, (R700_FORCE_EOV_MAX_CLK_CNT(4095) |
1539                                                      R700_FORCE_EOV_MAX_REZ_CNT(255)));
1540
1541         if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV710)
1542                 RADEON_WRITE(R600_VGT_CACHE_INVALIDATION, (R600_CACHE_INVALIDATION(R600_TC_ONLY) |
1543                                                            R700_AUTO_INVLD_EN(R700_ES_AND_GS_AUTO)));
1544         else
1545                 RADEON_WRITE(R600_VGT_CACHE_INVALIDATION, (R600_CACHE_INVALIDATION(R600_VC_AND_TC) |
1546                                                            R700_AUTO_INVLD_EN(R700_ES_AND_GS_AUTO)));
1547
1548         switch (dev_priv->flags & RADEON_FAMILY_MASK) {
1549         case CHIP_RV770:
1550         case CHIP_RV740:
1551         case CHIP_RV730:
1552                 gs_prim_buffer_depth = 384;
1553                 break;
1554         case CHIP_RV710:
1555                 gs_prim_buffer_depth = 128;
1556                 break;
1557         default:
1558                 break;
1559         }
1560
1561         num_gs_verts_per_thread = dev_priv->r600_max_pipes * 16;
1562         vgt_gs_per_es = gs_prim_buffer_depth + num_gs_verts_per_thread;
1563         /* Max value for this is 256 */
1564         if (vgt_gs_per_es > 256)
1565                 vgt_gs_per_es = 256;
1566
1567         RADEON_WRITE(R600_VGT_ES_PER_GS, 128);
1568         RADEON_WRITE(R600_VGT_GS_PER_ES, vgt_gs_per_es);
1569         RADEON_WRITE(R600_VGT_GS_PER_VS, 2);
1570
1571         /* more default values. 2D/3D driver should adjust as needed */
1572         RADEON_WRITE(R600_VGT_GS_VERTEX_REUSE, 16);
1573         RADEON_WRITE(R600_PA_SC_LINE_STIPPLE_STATE, 0);
1574         RADEON_WRITE(R600_VGT_STRMOUT_EN, 0);
1575         RADEON_WRITE(R600_SX_MISC, 0);
1576         RADEON_WRITE(R600_PA_SC_MODE_CNTL, 0);
1577         RADEON_WRITE(R700_PA_SC_EDGERULE, 0xaaaaaaaa);
1578         RADEON_WRITE(R600_PA_SC_AA_CONFIG, 0);
1579         RADEON_WRITE(R600_PA_SC_CLIPRECT_RULE, 0xffff);
1580         RADEON_WRITE(R600_PA_SC_LINE_STIPPLE, 0);
1581         RADEON_WRITE(R600_SPI_INPUT_Z, 0);
1582         RADEON_WRITE(R600_SPI_PS_IN_CONTROL_0, R600_NUM_INTERP(2));
1583         RADEON_WRITE(R600_CB_COLOR7_FRAG, 0);
1584
1585         /* clear render buffer base addresses */
1586         RADEON_WRITE(R600_CB_COLOR0_BASE, 0);
1587         RADEON_WRITE(R600_CB_COLOR1_BASE, 0);
1588         RADEON_WRITE(R600_CB_COLOR2_BASE, 0);
1589         RADEON_WRITE(R600_CB_COLOR3_BASE, 0);
1590         RADEON_WRITE(R600_CB_COLOR4_BASE, 0);
1591         RADEON_WRITE(R600_CB_COLOR5_BASE, 0);
1592         RADEON_WRITE(R600_CB_COLOR6_BASE, 0);
1593         RADEON_WRITE(R600_CB_COLOR7_BASE, 0);
1594
1595         RADEON_WRITE(R700_TCP_CNTL, 0);
1596
1597         hdp_host_path_cntl = RADEON_READ(R600_HDP_HOST_PATH_CNTL);
1598         RADEON_WRITE(R600_HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
1599
1600         RADEON_WRITE(R600_PA_SC_MULTI_CHIP_CNTL, 0);
1601
1602         RADEON_WRITE(R600_PA_CL_ENHANCE, (R600_CLIP_VTX_REORDER_ENA |
1603                                           R600_NUM_CLIP_SEQ(3)));
1604
1605 }
1606
1607 static void r600_cp_init_ring_buffer(struct drm_device *dev,
1608                                        drm_radeon_private_t *dev_priv,
1609                                        struct drm_file *file_priv)
1610 {
1611         u32 ring_start;
1612         u64 rptr_addr;
1613
1614         if (((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770))
1615                 r700_gfx_init(dev, dev_priv);
1616         else
1617                 r600_gfx_init(dev, dev_priv);
1618
1619         RADEON_WRITE(R600_GRBM_SOFT_RESET, R600_SOFT_RESET_CP);
1620         RADEON_READ(R600_GRBM_SOFT_RESET);
1621         DRM_UDELAY(15000);
1622         RADEON_WRITE(R600_GRBM_SOFT_RESET, 0);
1623
1624
1625         /* Set ring buffer size */
1626 #ifdef __BIG_ENDIAN
1627         RADEON_WRITE(R600_CP_RB_CNTL,
1628                      RADEON_BUF_SWAP_32BIT |
1629                      RADEON_RB_NO_UPDATE |
1630                      (dev_priv->ring.rptr_update_l2qw << 8) |
1631                      dev_priv->ring.size_l2qw);
1632 #else
1633         RADEON_WRITE(R600_CP_RB_CNTL,
1634                      RADEON_RB_NO_UPDATE |
1635                      (dev_priv->ring.rptr_update_l2qw << 8) |
1636                      dev_priv->ring.size_l2qw);
1637 #endif
1638
1639         RADEON_WRITE(R600_CP_SEM_WAIT_TIMER, 0x4);
1640
1641         /* Set the write pointer delay */
1642         RADEON_WRITE(R600_CP_RB_WPTR_DELAY, 0);
1643
1644 #ifdef __BIG_ENDIAN
1645         RADEON_WRITE(R600_CP_RB_CNTL,
1646                      RADEON_BUF_SWAP_32BIT |
1647                      RADEON_RB_NO_UPDATE |
1648                      RADEON_RB_RPTR_WR_ENA |
1649                      (dev_priv->ring.rptr_update_l2qw << 8) |
1650                      dev_priv->ring.size_l2qw);
1651 #else
1652         RADEON_WRITE(R600_CP_RB_CNTL,
1653                      RADEON_RB_NO_UPDATE |
1654                      RADEON_RB_RPTR_WR_ENA |
1655                      (dev_priv->ring.rptr_update_l2qw << 8) |
1656                      dev_priv->ring.size_l2qw);
1657 #endif
1658
1659         /* Initialize the ring buffer's read and write pointers */
1660         RADEON_WRITE(R600_CP_RB_RPTR_WR, 0);
1661         RADEON_WRITE(R600_CP_RB_WPTR, 0);
1662         SET_RING_HEAD(dev_priv, 0);
1663         dev_priv->ring.tail = 0;
1664
1665 #if __OS_HAS_AGP
1666         if (dev_priv->flags & RADEON_IS_AGP) {
1667                 rptr_addr = dev_priv->ring_rptr->offset
1668                         - dev->agp->base +
1669                         dev_priv->gart_vm_start;
1670         } else
1671 #endif
1672         {
1673                 rptr_addr = dev_priv->ring_rptr->offset
1674                         - ((unsigned long) dev->sg->virtual)
1675                         + dev_priv->gart_vm_start;
1676         }
1677         RADEON_WRITE(R600_CP_RB_RPTR_ADDR,
1678                      rptr_addr & 0xffffffff);
1679         RADEON_WRITE(R600_CP_RB_RPTR_ADDR_HI,
1680                      upper_32_bits(rptr_addr));
1681
1682 #ifdef __BIG_ENDIAN
1683         RADEON_WRITE(R600_CP_RB_CNTL,
1684                      RADEON_BUF_SWAP_32BIT |
1685                      (dev_priv->ring.rptr_update_l2qw << 8) |
1686                      dev_priv->ring.size_l2qw);
1687 #else
1688         RADEON_WRITE(R600_CP_RB_CNTL,
1689                      (dev_priv->ring.rptr_update_l2qw << 8) |
1690                      dev_priv->ring.size_l2qw);
1691 #endif
1692
1693 #if __OS_HAS_AGP
1694         if (dev_priv->flags & RADEON_IS_AGP) {
1695                 /* XXX */
1696                 radeon_write_agp_base(dev_priv, dev->agp->base);
1697
1698                 /* XXX */
1699                 radeon_write_agp_location(dev_priv,
1700                              (((dev_priv->gart_vm_start - 1 +
1701                                 dev_priv->gart_size) & 0xffff0000) |
1702                               (dev_priv->gart_vm_start >> 16)));
1703
1704                 ring_start = (dev_priv->cp_ring->offset
1705                               - dev->agp->base
1706                               + dev_priv->gart_vm_start);
1707         } else
1708 #endif
1709                 ring_start = (dev_priv->cp_ring->offset
1710                               - (unsigned long)dev->sg->virtual
1711                               + dev_priv->gart_vm_start);
1712
1713         RADEON_WRITE(R600_CP_RB_BASE, ring_start >> 8);
1714
1715         RADEON_WRITE(R600_CP_ME_CNTL, 0xff);
1716
1717         RADEON_WRITE(R600_CP_DEBUG, (1 << 27) | (1 << 28));
1718
1719         /* Initialize the scratch register pointer.  This will cause
1720          * the scratch register values to be written out to memory
1721          * whenever they are updated.
1722          *
1723          * We simply put this behind the ring read pointer, this works
1724          * with PCI GART as well as (whatever kind of) AGP GART
1725          */
1726         {
1727                 u64 scratch_addr;
1728
1729                 scratch_addr = RADEON_READ(R600_CP_RB_RPTR_ADDR);
1730                 scratch_addr |= ((u64)RADEON_READ(R600_CP_RB_RPTR_ADDR_HI)) << 32;
1731                 scratch_addr += R600_SCRATCH_REG_OFFSET;
1732                 scratch_addr >>= 8;
1733                 scratch_addr &= 0xffffffff;
1734
1735                 RADEON_WRITE(R600_SCRATCH_ADDR, (uint32_t)scratch_addr);
1736         }
1737
1738         RADEON_WRITE(R600_SCRATCH_UMSK, 0x7);
1739
1740         /* Turn on bus mastering */
1741         radeon_enable_bm(dev_priv);
1742
1743         radeon_write_ring_rptr(dev_priv, R600_SCRATCHOFF(0), 0);
1744         RADEON_WRITE(R600_LAST_FRAME_REG, 0);
1745
1746         radeon_write_ring_rptr(dev_priv, R600_SCRATCHOFF(1), 0);
1747         RADEON_WRITE(R600_LAST_DISPATCH_REG, 0);
1748
1749         radeon_write_ring_rptr(dev_priv, R600_SCRATCHOFF(2), 0);
1750         RADEON_WRITE(R600_LAST_CLEAR_REG, 0);
1751
1752         /* reset sarea copies of these */
1753         if (dev_priv->sarea_priv) {
1754                 dev_priv->sarea_priv->last_frame = 0;
1755                 dev_priv->sarea_priv->last_dispatch = 0;
1756                 dev_priv->sarea_priv->last_clear = 0;
1757         }
1758
1759         r600_do_wait_for_idle(dev_priv);
1760
1761 }
1762
1763 int r600_do_cleanup_cp(struct drm_device *dev)
1764 {
1765         drm_radeon_private_t *dev_priv = dev->dev_private;
1766         DRM_DEBUG("\n");
1767
1768         /* Make sure interrupts are disabled here because the uninstall ioctl
1769          * may not have been called from userspace and after dev_private
1770          * is freed, it's too late.
1771          */
1772         if (dev->irq_enabled)
1773                 drm_irq_uninstall(dev);
1774
1775 #if __OS_HAS_AGP
1776         if (dev_priv->flags & RADEON_IS_AGP) {
1777                 if (dev_priv->cp_ring != NULL) {
1778                         drm_core_ioremapfree(dev_priv->cp_ring, dev);
1779                         dev_priv->cp_ring = NULL;
1780                 }
1781                 if (dev_priv->ring_rptr != NULL) {
1782                         drm_core_ioremapfree(dev_priv->ring_rptr, dev);
1783                         dev_priv->ring_rptr = NULL;
1784                 }
1785                 if (dev->agp_buffer_map != NULL) {
1786                         drm_core_ioremapfree(dev->agp_buffer_map, dev);
1787                         dev->agp_buffer_map = NULL;
1788                 }
1789         } else
1790 #endif
1791         {
1792
1793                 if (dev_priv->gart_info.bus_addr)
1794                         r600_page_table_cleanup(dev, &dev_priv->gart_info);
1795
1796                 if (dev_priv->gart_info.gart_table_location == DRM_ATI_GART_FB) {
1797                         drm_core_ioremapfree(&dev_priv->gart_info.mapping, dev);
1798                         dev_priv->gart_info.addr = 0;
1799                 }
1800         }
1801         /* only clear to the start of flags */
1802         memset(dev_priv, 0, offsetof(drm_radeon_private_t, flags));
1803
1804         return 0;
1805 }
1806
1807 int r600_do_init_cp(struct drm_device *dev, drm_radeon_init_t *init,
1808                     struct drm_file *file_priv)
1809 {
1810         drm_radeon_private_t *dev_priv = dev->dev_private;
1811
1812         DRM_DEBUG("\n");
1813
1814         /* if we require new memory map but we don't have it fail */
1815         if ((dev_priv->flags & RADEON_NEW_MEMMAP) && !dev_priv->new_memmap) {
1816                 DRM_ERROR("Cannot initialise DRM on this card\nThis card requires a new X.org DDX for 3D\n");
1817                 r600_do_cleanup_cp(dev);
1818                 return -EINVAL;
1819         }
1820
1821         if (init->is_pci && (dev_priv->flags & RADEON_IS_AGP)) {
1822                 DRM_DEBUG("Forcing AGP card to PCI mode\n");
1823                 dev_priv->flags &= ~RADEON_IS_AGP;
1824                 /* The writeback test succeeds, but when writeback is enabled,
1825                  * the ring buffer read ptr update fails after first 128 bytes.
1826                  */
1827                 radeon_no_wb = 1;
1828         } else if (!(dev_priv->flags & (RADEON_IS_AGP | RADEON_IS_PCI | RADEON_IS_PCIE))
1829                  && !init->is_pci) {
1830                 DRM_DEBUG("Restoring AGP flag\n");
1831                 dev_priv->flags |= RADEON_IS_AGP;
1832         }
1833
1834         dev_priv->usec_timeout = init->usec_timeout;
1835         if (dev_priv->usec_timeout < 1 ||
1836             dev_priv->usec_timeout > RADEON_MAX_USEC_TIMEOUT) {
1837                 DRM_DEBUG("TIMEOUT problem!\n");
1838                 r600_do_cleanup_cp(dev);
1839                 return -EINVAL;
1840         }
1841
1842         /* Enable vblank on CRTC1 for older X servers
1843          */
1844         dev_priv->vblank_crtc = DRM_RADEON_VBLANK_CRTC1;
1845
1846         dev_priv->do_boxes = 0;
1847         dev_priv->cp_mode = init->cp_mode;
1848
1849         /* We don't support anything other than bus-mastering ring mode,
1850          * but the ring can be in either AGP or PCI space for the ring
1851          * read pointer.
1852          */
1853         if ((init->cp_mode != RADEON_CSQ_PRIBM_INDDIS) &&
1854             (init->cp_mode != RADEON_CSQ_PRIBM_INDBM)) {
1855                 DRM_DEBUG("BAD cp_mode (%x)!\n", init->cp_mode);
1856                 r600_do_cleanup_cp(dev);
1857                 return -EINVAL;
1858         }
1859
1860         switch (init->fb_bpp) {
1861         case 16:
1862                 dev_priv->color_fmt = RADEON_COLOR_FORMAT_RGB565;
1863                 break;
1864         case 32:
1865         default:
1866                 dev_priv->color_fmt = RADEON_COLOR_FORMAT_ARGB8888;
1867                 break;
1868         }
1869         dev_priv->front_offset = init->front_offset;
1870         dev_priv->front_pitch = init->front_pitch;
1871         dev_priv->back_offset = init->back_offset;
1872         dev_priv->back_pitch = init->back_pitch;
1873
1874         dev_priv->ring_offset = init->ring_offset;
1875         dev_priv->ring_rptr_offset = init->ring_rptr_offset;
1876         dev_priv->buffers_offset = init->buffers_offset;
1877         dev_priv->gart_textures_offset = init->gart_textures_offset;
1878
1879         dev_priv->sarea = drm_getsarea(dev);
1880         if (!dev_priv->sarea) {
1881                 DRM_ERROR("could not find sarea!\n");
1882                 r600_do_cleanup_cp(dev);
1883                 return -EINVAL;
1884         }
1885
1886         dev_priv->cp_ring = drm_core_findmap(dev, init->ring_offset);
1887         if (!dev_priv->cp_ring) {
1888                 DRM_ERROR("could not find cp ring region!\n");
1889                 r600_do_cleanup_cp(dev);
1890                 return -EINVAL;
1891         }
1892         dev_priv->ring_rptr = drm_core_findmap(dev, init->ring_rptr_offset);
1893         if (!dev_priv->ring_rptr) {
1894                 DRM_ERROR("could not find ring read pointer!\n");
1895                 r600_do_cleanup_cp(dev);
1896                 return -EINVAL;
1897         }
1898         dev->agp_buffer_token = init->buffers_offset;
1899         dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset);
1900         if (!dev->agp_buffer_map) {
1901                 DRM_ERROR("could not find dma buffer region!\n");
1902                 r600_do_cleanup_cp(dev);
1903                 return -EINVAL;
1904         }
1905
1906         if (init->gart_textures_offset) {
1907                 dev_priv->gart_textures =
1908                     drm_core_findmap(dev, init->gart_textures_offset);
1909                 if (!dev_priv->gart_textures) {
1910                         DRM_ERROR("could not find GART texture region!\n");
1911                         r600_do_cleanup_cp(dev);
1912                         return -EINVAL;
1913                 }
1914         }
1915
1916         dev_priv->sarea_priv =
1917             (drm_radeon_sarea_t *) ((u8 *) dev_priv->sarea->handle +
1918                                     init->sarea_priv_offset);
1919
1920 #if __OS_HAS_AGP
1921         /* XXX */
1922         if (dev_priv->flags & RADEON_IS_AGP) {
1923                 drm_core_ioremap_wc(dev_priv->cp_ring, dev);
1924                 drm_core_ioremap_wc(dev_priv->ring_rptr, dev);
1925                 drm_core_ioremap_wc(dev->agp_buffer_map, dev);
1926                 if (!dev_priv->cp_ring->handle ||
1927                     !dev_priv->ring_rptr->handle ||
1928                     !dev->agp_buffer_map->handle) {
1929                         DRM_ERROR("could not find ioremap agp regions!\n");
1930                         r600_do_cleanup_cp(dev);
1931                         return -EINVAL;
1932                 }
1933         } else
1934 #endif
1935         {
1936                 dev_priv->cp_ring->handle = (void *)dev_priv->cp_ring->offset;
1937                 dev_priv->ring_rptr->handle =
1938                     (void *)dev_priv->ring_rptr->offset;
1939                 dev->agp_buffer_map->handle =
1940                     (void *)dev->agp_buffer_map->offset;
1941
1942                 DRM_DEBUG("dev_priv->cp_ring->handle %p\n",
1943                           dev_priv->cp_ring->handle);
1944                 DRM_DEBUG("dev_priv->ring_rptr->handle %p\n",
1945                           dev_priv->ring_rptr->handle);
1946                 DRM_DEBUG("dev->agp_buffer_map->handle %p\n",
1947                           dev->agp_buffer_map->handle);
1948         }
1949
1950         dev_priv->fb_location = (radeon_read_fb_location(dev_priv) & 0xffff) << 24;
1951         dev_priv->fb_size =
1952                 (((radeon_read_fb_location(dev_priv) & 0xffff0000u) << 8) + 0x1000000)
1953                 - dev_priv->fb_location;
1954
1955         dev_priv->front_pitch_offset = (((dev_priv->front_pitch / 64) << 22) |
1956                                         ((dev_priv->front_offset
1957                                           + dev_priv->fb_location) >> 10));
1958
1959         dev_priv->back_pitch_offset = (((dev_priv->back_pitch / 64) << 22) |
1960                                        ((dev_priv->back_offset
1961                                          + dev_priv->fb_location) >> 10));
1962
1963         dev_priv->depth_pitch_offset = (((dev_priv->depth_pitch / 64) << 22) |
1964                                         ((dev_priv->depth_offset
1965                                           + dev_priv->fb_location) >> 10));
1966
1967         dev_priv->gart_size = init->gart_size;
1968
1969         /* New let's set the memory map ... */
1970         if (dev_priv->new_memmap) {
1971                 u32 base = 0;
1972
1973                 DRM_INFO("Setting GART location based on new memory map\n");
1974
1975                 /* If using AGP, try to locate the AGP aperture at the same
1976                  * location in the card and on the bus, though we have to
1977                  * align it down.
1978                  */
1979 #if __OS_HAS_AGP
1980                 /* XXX */
1981                 if (dev_priv->flags & RADEON_IS_AGP) {
1982                         base = dev->agp->base;
1983                         /* Check if valid */
1984                         if ((base + dev_priv->gart_size - 1) >= dev_priv->fb_location &&
1985                             base < (dev_priv->fb_location + dev_priv->fb_size - 1)) {
1986                                 DRM_INFO("Can't use AGP base @0x%08lx, won't fit\n",
1987                                          dev->agp->base);
1988                                 base = 0;
1989                         }
1990                 }
1991 #endif
1992                 /* If not or if AGP is at 0 (Macs), try to put it elsewhere */
1993                 if (base == 0) {
1994                         base = dev_priv->fb_location + dev_priv->fb_size;
1995                         if (base < dev_priv->fb_location ||
1996                             ((base + dev_priv->gart_size) & 0xfffffffful) < base)
1997                                 base = dev_priv->fb_location
1998                                         - dev_priv->gart_size;
1999                 }
2000                 dev_priv->gart_vm_start = base & 0xffc00000u;
2001                 if (dev_priv->gart_vm_start != base)
2002                         DRM_INFO("GART aligned down from 0x%08x to 0x%08x\n",
2003                                  base, dev_priv->gart_vm_start);
2004         }
2005
2006 #if __OS_HAS_AGP
2007         /* XXX */
2008         if (dev_priv->flags & RADEON_IS_AGP)
2009                 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
2010                                                  - dev->agp->base
2011                                                  + dev_priv->gart_vm_start);
2012         else
2013 #endif
2014                 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
2015                                                  - (unsigned long)dev->sg->virtual
2016                                                  + dev_priv->gart_vm_start);
2017
2018         DRM_DEBUG("fb 0x%08x size %d\n",
2019                   (unsigned int) dev_priv->fb_location,
2020                   (unsigned int) dev_priv->fb_size);
2021         DRM_DEBUG("dev_priv->gart_size %d\n", dev_priv->gart_size);
2022         DRM_DEBUG("dev_priv->gart_vm_start 0x%08x\n",
2023                   (unsigned int) dev_priv->gart_vm_start);
2024         DRM_DEBUG("dev_priv->gart_buffers_offset 0x%08lx\n",
2025                   dev_priv->gart_buffers_offset);
2026
2027         dev_priv->ring.start = (u32 *) dev_priv->cp_ring->handle;
2028         dev_priv->ring.end = ((u32 *) dev_priv->cp_ring->handle
2029                               + init->ring_size / sizeof(u32));
2030         dev_priv->ring.size = init->ring_size;
2031         dev_priv->ring.size_l2qw = drm_order(init->ring_size / 8);
2032
2033         dev_priv->ring.rptr_update = /* init->rptr_update */ 4096;
2034         dev_priv->ring.rptr_update_l2qw = drm_order(/* init->rptr_update */ 4096 / 8);
2035
2036         dev_priv->ring.fetch_size = /* init->fetch_size */ 32;
2037         dev_priv->ring.fetch_size_l2ow = drm_order(/* init->fetch_size */ 32 / 16);
2038
2039         dev_priv->ring.tail_mask = (dev_priv->ring.size / sizeof(u32)) - 1;
2040
2041         dev_priv->ring.high_mark = RADEON_RING_HIGH_MARK;
2042
2043 #if __OS_HAS_AGP
2044         if (dev_priv->flags & RADEON_IS_AGP) {
2045                 /* XXX turn off pcie gart */
2046         } else
2047 #endif
2048         {
2049                 dev_priv->gart_info.table_mask = DMA_BIT_MASK(32);
2050                 /* if we have an offset set from userspace */
2051                 if (!dev_priv->pcigart_offset_set) {
2052                         DRM_ERROR("Need gart offset from userspace\n");
2053                         r600_do_cleanup_cp(dev);
2054                         return -EINVAL;
2055                 }
2056
2057                 DRM_DEBUG("Using gart offset 0x%08lx\n", dev_priv->pcigart_offset);
2058
2059                 dev_priv->gart_info.bus_addr =
2060                         dev_priv->pcigart_offset + dev_priv->fb_location;
2061                 dev_priv->gart_info.mapping.offset =
2062                         dev_priv->pcigart_offset + dev_priv->fb_aper_offset;
2063                 dev_priv->gart_info.mapping.size =
2064                         dev_priv->gart_info.table_size;
2065
2066                 drm_core_ioremap_wc(&dev_priv->gart_info.mapping, dev);
2067                 if (!dev_priv->gart_info.mapping.handle) {
2068                         DRM_ERROR("ioremap failed.\n");
2069                         r600_do_cleanup_cp(dev);
2070                         return -EINVAL;
2071                 }
2072
2073                 dev_priv->gart_info.addr =
2074                         dev_priv->gart_info.mapping.handle;
2075
2076                 DRM_DEBUG("Setting phys_pci_gart to %p %08lX\n",
2077                           dev_priv->gart_info.addr,
2078                           dev_priv->pcigart_offset);
2079
2080                 if (!r600_page_table_init(dev)) {
2081                         DRM_ERROR("Failed to init GART table\n");
2082                         r600_do_cleanup_cp(dev);
2083                         return -EINVAL;
2084                 }
2085
2086                 if (((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770))
2087                         r700_vm_init(dev);
2088                 else
2089                         r600_vm_init(dev);
2090         }
2091
2092         if (((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770))
2093                 r700_cp_load_microcode(dev_priv);
2094         else
2095                 r600_cp_load_microcode(dev_priv);
2096
2097         r600_cp_init_ring_buffer(dev, dev_priv, file_priv);
2098
2099         dev_priv->last_buf = 0;
2100
2101         r600_do_engine_reset(dev);
2102         r600_test_writeback(dev_priv);
2103
2104         r600_cs_init(dev);
2105
2106         return 0;
2107 }
2108
2109 int r600_do_resume_cp(struct drm_device *dev, struct drm_file *file_priv)
2110 {
2111         drm_radeon_private_t *dev_priv = dev->dev_private;
2112
2113         DRM_DEBUG("\n");
2114         if (((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)) {
2115                 r700_vm_init(dev);
2116                 r700_cp_load_microcode(dev_priv);
2117         } else {
2118                 r600_vm_init(dev);
2119                 r600_cp_load_microcode(dev_priv);
2120         }
2121         r600_cp_init_ring_buffer(dev, dev_priv, file_priv);
2122         r600_do_engine_reset(dev);
2123
2124         return 0;
2125 }
2126
2127 /* Wait for the CP to go idle.
2128  */
2129 int r600_do_cp_idle(drm_radeon_private_t *dev_priv)
2130 {
2131         RING_LOCALS;
2132         DRM_DEBUG("\n");
2133
2134         BEGIN_RING(5);
2135         OUT_RING(CP_PACKET3(R600_IT_EVENT_WRITE, 0));
2136         OUT_RING(R600_CACHE_FLUSH_AND_INV_EVENT);
2137         /* wait for 3D idle clean */
2138         OUT_RING(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1));
2139         OUT_RING((R600_WAIT_UNTIL - R600_SET_CONFIG_REG_OFFSET) >> 2);
2140         OUT_RING(RADEON_WAIT_3D_IDLE | RADEON_WAIT_3D_IDLECLEAN);
2141
2142         ADVANCE_RING();
2143         COMMIT_RING();
2144
2145         return r600_do_wait_for_idle(dev_priv);
2146 }
2147
2148 /* Start the Command Processor.
2149  */
2150 void r600_do_cp_start(drm_radeon_private_t *dev_priv)
2151 {
2152         u32 cp_me;
2153         RING_LOCALS;
2154         DRM_DEBUG("\n");
2155
2156         BEGIN_RING(7);
2157         OUT_RING(CP_PACKET3(R600_IT_ME_INITIALIZE, 5));
2158         OUT_RING(0x00000001);
2159         if (((dev_priv->flags & RADEON_FAMILY_MASK) < CHIP_RV770))
2160                 OUT_RING(0x00000003);
2161         else
2162                 OUT_RING(0x00000000);
2163         OUT_RING((dev_priv->r600_max_hw_contexts - 1));
2164         OUT_RING(R600_ME_INITIALIZE_DEVICE_ID(1));
2165         OUT_RING(0x00000000);
2166         OUT_RING(0x00000000);
2167         ADVANCE_RING();
2168         COMMIT_RING();
2169
2170         /* set the mux and reset the halt bit */
2171         cp_me = 0xff;
2172         RADEON_WRITE(R600_CP_ME_CNTL, cp_me);
2173
2174         dev_priv->cp_running = 1;
2175
2176 }
2177
2178 void r600_do_cp_reset(drm_radeon_private_t *dev_priv)
2179 {
2180         u32 cur_read_ptr;
2181         DRM_DEBUG("\n");
2182
2183         cur_read_ptr = RADEON_READ(R600_CP_RB_RPTR);
2184         RADEON_WRITE(R600_CP_RB_WPTR, cur_read_ptr);
2185         SET_RING_HEAD(dev_priv, cur_read_ptr);
2186         dev_priv->ring.tail = cur_read_ptr;
2187 }
2188
2189 void r600_do_cp_stop(drm_radeon_private_t *dev_priv)
2190 {
2191         uint32_t cp_me;
2192
2193         DRM_DEBUG("\n");
2194
2195         cp_me = 0xff | R600_CP_ME_HALT;
2196
2197         RADEON_WRITE(R600_CP_ME_CNTL, cp_me);
2198
2199         dev_priv->cp_running = 0;
2200 }
2201
2202 int r600_cp_dispatch_indirect(struct drm_device *dev,
2203                               struct drm_buf *buf, int start, int end)
2204 {
2205         drm_radeon_private_t *dev_priv = dev->dev_private;
2206         RING_LOCALS;
2207
2208         if (start != end) {
2209                 unsigned long offset = (dev_priv->gart_buffers_offset
2210                                         + buf->offset + start);
2211                 int dwords = (end - start + 3) / sizeof(u32);
2212
2213                 DRM_DEBUG("dwords:%d\n", dwords);
2214                 DRM_DEBUG("offset 0x%lx\n", offset);
2215
2216
2217                 /* Indirect buffer data must be a multiple of 16 dwords.
2218                  * pad the data with a Type-2 CP packet.
2219                  */
2220                 while (dwords & 0xf) {
2221                         u32 *data = (u32 *)
2222                             ((char *)dev->agp_buffer_map->handle
2223                              + buf->offset + start);
2224                         data[dwords++] = RADEON_CP_PACKET2;
2225                 }
2226
2227                 /* Fire off the indirect buffer */
2228                 BEGIN_RING(4);
2229                 OUT_RING(CP_PACKET3(R600_IT_INDIRECT_BUFFER, 2));
2230                 OUT_RING((offset & 0xfffffffc));
2231                 OUT_RING((upper_32_bits(offset) & 0xff));
2232                 OUT_RING(dwords);
2233                 ADVANCE_RING();
2234         }
2235
2236         return 0;
2237 }
2238
2239 void r600_cp_dispatch_swap(struct drm_device * dev)
2240 {
2241         drm_radeon_private_t *dev_priv = dev->dev_private;
2242         drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
2243         int nbox = sarea_priv->nbox;
2244         struct drm_clip_rect *pbox = sarea_priv->boxes;
2245         int i, cpp, src_pitch, dst_pitch;
2246         uint64_t src, dst;
2247         RING_LOCALS;
2248         DRM_DEBUG("\n");
2249
2250         if (dev_priv->color_fmt == RADEON_COLOR_FORMAT_ARGB8888)
2251                 cpp = 4;
2252         else
2253                 cpp = 2;
2254
2255         if (dev_priv->sarea_priv->pfCurrentPage == 0) {
2256                 src_pitch = dev_priv->back_pitch;
2257                 dst_pitch = dev_priv->front_pitch;
2258                 src = dev_priv->back_offset + dev_priv->fb_location;
2259                 dst = dev_priv->front_offset + dev_priv->fb_location;
2260         } else {
2261                 src_pitch = dev_priv->front_pitch;
2262                 dst_pitch = dev_priv->back_pitch;
2263                 src = dev_priv->front_offset + dev_priv->fb_location;
2264                 dst = dev_priv->back_offset + dev_priv->fb_location;
2265         }
2266
2267         if (r600_prepare_blit_copy(dev)) {
2268                 DRM_ERROR("unable to allocate vertex buffer for swap buffer\n");
2269                 return;
2270         }
2271         for (i = 0; i < nbox; i++) {
2272                 int x = pbox[i].x1;
2273                 int y = pbox[i].y1;
2274                 int w = pbox[i].x2 - x;
2275                 int h = pbox[i].y2 - y;
2276
2277                 DRM_DEBUG("%d,%d-%d,%d\n", x, y, w, h);
2278
2279                 r600_blit_swap(dev,
2280                                src, dst,
2281                                x, y, x, y, w, h,
2282                                src_pitch, dst_pitch, cpp);
2283         }
2284         r600_done_blit_copy(dev);
2285
2286         /* Increment the frame counter.  The client-side 3D driver must
2287          * throttle the framerate by waiting for this value before
2288          * performing the swapbuffer ioctl.
2289          */
2290         dev_priv->sarea_priv->last_frame++;
2291
2292         BEGIN_RING(3);
2293         R600_FRAME_AGE(dev_priv->sarea_priv->last_frame);
2294         ADVANCE_RING();
2295 }
2296
2297 int r600_cp_dispatch_texture(struct drm_device * dev,
2298                              struct drm_file *file_priv,
2299                              drm_radeon_texture_t * tex,
2300                              drm_radeon_tex_image_t * image)
2301 {
2302         drm_radeon_private_t *dev_priv = dev->dev_private;
2303         struct drm_buf *buf;
2304         u32 *buffer;
2305         const u8 __user *data;
2306         int size, pass_size;
2307         u64 src_offset, dst_offset;
2308
2309         if (!radeon_check_offset(dev_priv, tex->offset)) {
2310                 DRM_ERROR("Invalid destination offset\n");
2311                 return -EINVAL;
2312         }
2313
2314         /* this might fail for zero-sized uploads - are those illegal? */
2315         if (!radeon_check_offset(dev_priv, tex->offset + tex->height * tex->pitch - 1)) {
2316                 DRM_ERROR("Invalid final destination offset\n");
2317                 return -EINVAL;
2318         }
2319
2320         size = tex->height * tex->pitch;
2321
2322         if (size == 0)
2323                 return 0;
2324
2325         dst_offset = tex->offset;
2326
2327         r600_prepare_blit_copy(dev);
2328         do {
2329                 data = (const u8 __user *)image->data;
2330                 pass_size = size;
2331
2332                 buf = radeon_freelist_get(dev);
2333                 if (!buf) {
2334                         DRM_DEBUG("EAGAIN\n");
2335                         if (DRM_COPY_TO_USER(tex->image, image, sizeof(*image)))
2336                                 return -EFAULT;
2337                         return -EAGAIN;
2338                 }
2339
2340                 if (pass_size > buf->total)
2341                         pass_size = buf->total;
2342
2343                 /* Dispatch the indirect buffer.
2344                  */
2345                 buffer =
2346                     (u32 *) ((char *)dev->agp_buffer_map->handle + buf->offset);
2347
2348                 if (DRM_COPY_FROM_USER(buffer, data, pass_size)) {
2349                         DRM_ERROR("EFAULT on pad, %d bytes\n", pass_size);
2350                         return -EFAULT;
2351                 }
2352
2353                 buf->file_priv = file_priv;
2354                 buf->used = pass_size;
2355                 src_offset = dev_priv->gart_buffers_offset + buf->offset;
2356
2357                 r600_blit_copy(dev, src_offset, dst_offset, pass_size);
2358
2359                 radeon_cp_discard_buffer(dev, buf);
2360
2361                 /* Update the input parameters for next time */
2362                 image->data = (const u8 __user *)image->data + pass_size;
2363                 dst_offset += pass_size;
2364                 size -= pass_size;
2365         } while (size > 0);
2366         r600_done_blit_copy(dev);
2367
2368         return 0;
2369 }