sys/dev/drm/radeon_cp.c

   1 /*-
   2  * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
   3  * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
   4  * Copyright 2007 Advanced Micro Devices, Inc.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the "Software"),
   9  * to deal in the Software without restriction, including without limitation
  10  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  11  * and/or sell copies of the Software, and to permit persons to whom the
  12  * Software is furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the next
  15  * paragraph) shall be included in all copies or substantial portions of the
  16  * Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  19  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  20  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  21  * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  22  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  23  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  24  * DEALINGS IN THE SOFTWARE.
  25  *
  26  * Authors:
  27  *    Kevin E. Martin <martin@valinux.com>
  28  *    Gareth Hughes <gareth@valinux.com>
  29  */
  30
  31 #include <sys/cdefs.h>
  32 __FBSDID("$FreeBSD$");
  33
  34 #include "dev/drm/drmP.h"
  35 #include "dev/drm/drm.h"
  36 #include "dev/drm/drm_sarea.h"
  37 #include "dev/drm/radeon_drm.h"
  38 #include "dev/drm/radeon_drv.h"
  39 #include "dev/drm/r300_reg.h"
  40
  41 #include "dev/drm/radeon_microcode.h"
  42
  43 #define RADEON_FIFO_DEBUG       0
  44
  45 static int radeon_do_cleanup_cp(struct drm_device * dev);
  46 static void radeon_do_cp_start(drm_radeon_private_t * dev_priv);
  47
  48 u32 radeon_read_ring_rptr(drm_radeon_private_t *dev_priv, u32 off)
  49 {
  50         u32 val;
  51
  52         if (dev_priv->flags & RADEON_IS_AGP) {
  53                 val = DRM_READ32(dev_priv->ring_rptr, off);
  54         } else {
  55                 val = *(((volatile u32 *)
  56                          dev_priv->ring_rptr->handle) +
  57                         (off / sizeof(u32)));
  58                 val = le32_to_cpu(val);
  59         }
  60         return val;
  61 }
  62
  63 u32 radeon_get_ring_head(drm_radeon_private_t *dev_priv)
  64 {
  65         if (dev_priv->writeback_works)
  66                 return radeon_read_ring_rptr(dev_priv, 0);
  67         else {
  68                 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
  69                         return RADEON_READ(R600_CP_RB_RPTR);
  70                 else
  71                         return RADEON_READ(RADEON_CP_RB_RPTR);
  72         }
  73 }
  74
  75 void radeon_write_ring_rptr(drm_radeon_private_t *dev_priv, u32 off, u32 val)
  76 {
  77         if (dev_priv->flags & RADEON_IS_AGP)
  78                 DRM_WRITE32(dev_priv->ring_rptr, off, val);
  79         else
  80                 *(((volatile u32 *) dev_priv->ring_rptr->handle) +
  81                   (off / sizeof(u32))) = cpu_to_le32(val);
  82 }
  83
  84 void radeon_set_ring_head(drm_radeon_private_t *dev_priv, u32 val)
  85 {
  86         radeon_write_ring_rptr(dev_priv, 0, val);
  87 }
  88
  89 u32 radeon_get_scratch(drm_radeon_private_t *dev_priv, int index)
  90 {
  91         if (dev_priv->writeback_works) {
  92                 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
  93                         return radeon_read_ring_rptr(dev_priv,
  94                                                      R600_SCRATCHOFF(index));
  95                 else
  96                         return radeon_read_ring_rptr(dev_priv,
  97                                                      RADEON_SCRATCHOFF(index));
  98         } else {
  99                 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
 100                         return RADEON_READ(R600_SCRATCH_REG0 + 4*index);
 101                 else
 102                         return RADEON_READ(RADEON_SCRATCH_REG0 + 4*index);
 103         }
 104 }
 105
 106 u32 RADEON_READ_MM(drm_radeon_private_t *dev_priv, int addr)
 107 {
 108         u32 ret;
 109
 110         if (addr < 0x10000)
 111                 ret = DRM_READ32(dev_priv->mmio, addr);
 112         else {
 113                 DRM_WRITE32(dev_priv->mmio, RADEON_MM_INDEX, addr);
 114                 ret = DRM_READ32(dev_priv->mmio, RADEON_MM_DATA);
 115         }
 116
 117         return ret;
 118 }
 119
 120 static u32 R500_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
 121 {
 122         u32 ret;
 123         RADEON_WRITE(R520_MC_IND_INDEX, 0x7f0000 | (addr & 0xff));
 124         ret = RADEON_READ(R520_MC_IND_DATA);
 125         RADEON_WRITE(R520_MC_IND_INDEX, 0);
 126         return ret;
 127 }
 128
 129 static u32 RS480_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
 130 {
 131         u32 ret;
 132         RADEON_WRITE(RS480_NB_MC_INDEX, addr & 0xff);
 133         ret = RADEON_READ(RS480_NB_MC_DATA);
 134         RADEON_WRITE(RS480_NB_MC_INDEX, 0xff);
 135         return ret;
 136 }
 137
 138 static u32 RS690_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
 139 {
 140         u32 ret;
 141         RADEON_WRITE(RS690_MC_INDEX, (addr & RS690_MC_INDEX_MASK));
 142         ret = RADEON_READ(RS690_MC_DATA);
 143         RADEON_WRITE(RS690_MC_INDEX, RS690_MC_INDEX_MASK);
 144         return ret;
 145 }
 146
 147 static u32 RS600_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
 148 {
 149         u32 ret;
 150         RADEON_WRITE(RS600_MC_INDEX, ((addr & RS600_MC_ADDR_MASK) |
 151                                       RS600_MC_IND_CITF_ARB0));
 152         ret = RADEON_READ(RS600_MC_DATA);
 153         return ret;
 154 }
 155
 156 static u32 IGP_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
 157 {
 158         if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
 159             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
 160                 return RS690_READ_MCIND(dev_priv, addr);
 161         else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600)
 162                 return RS600_READ_MCIND(dev_priv, addr);
 163         else
 164                 return RS480_READ_MCIND(dev_priv, addr);
 165 }
 166
 167 u32 radeon_read_fb_location(drm_radeon_private_t *dev_priv)
 168 {
 169
 170         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)
 171                 return RADEON_READ(R700_MC_VM_FB_LOCATION);
 172         else if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
 173                 return RADEON_READ(R600_MC_VM_FB_LOCATION);
 174         else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
 175                 return R500_READ_MCIND(dev_priv, RV515_MC_FB_LOCATION);
 176         else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
 177                  ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
 178                 return RS690_READ_MCIND(dev_priv, RS690_MC_FB_LOCATION);
 179         else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600)
 180                 return RS600_READ_MCIND(dev_priv, RS600_MC_FB_LOCATION);
 181         else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
 182                 return R500_READ_MCIND(dev_priv, R520_MC_FB_LOCATION);
 183         else
 184                 return RADEON_READ(RADEON_MC_FB_LOCATION);
 185 }
 186
 187 static void radeon_write_fb_location(drm_radeon_private_t *dev_priv, u32 fb_loc)
 188 {
 189         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)
 190                 RADEON_WRITE(R700_MC_VM_FB_LOCATION, fb_loc);
 191         else if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
 192                 RADEON_WRITE(R600_MC_VM_FB_LOCATION, fb_loc);
 193         else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
 194                 R500_WRITE_MCIND(RV515_MC_FB_LOCATION, fb_loc);
 195         else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
 196                  ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
 197                 RS690_WRITE_MCIND(RS690_MC_FB_LOCATION, fb_loc);
 198         else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600)
 199                 RS600_WRITE_MCIND(RS600_MC_FB_LOCATION, fb_loc);
 200         else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
 201                 R500_WRITE_MCIND(R520_MC_FB_LOCATION, fb_loc);
 202         else
 203                 RADEON_WRITE(RADEON_MC_FB_LOCATION, fb_loc);
 204 }
 205
 206 void radeon_write_agp_location(drm_radeon_private_t *dev_priv, u32 agp_loc)
 207 {
 208         /*R6xx/R7xx: AGP_TOP and BOT are actually 18 bits each */
 209         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770) {
 210                 RADEON_WRITE(R700_MC_VM_AGP_BOT, agp_loc & 0xffff); /* FIX ME */
 211                 RADEON_WRITE(R700_MC_VM_AGP_TOP, (agp_loc >> 16) & 0xffff);
 212         } else if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) {
 213                 RADEON_WRITE(R600_MC_VM_AGP_BOT, agp_loc & 0xffff); /* FIX ME */
 214                 RADEON_WRITE(R600_MC_VM_AGP_TOP, (agp_loc >> 16) & 0xffff);
 215         } else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
 216                 R500_WRITE_MCIND(RV515_MC_AGP_LOCATION, agp_loc);
 217         else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
 218                  ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
 219                 RS690_WRITE_MCIND(RS690_MC_AGP_LOCATION, agp_loc);
 220         else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600)
 221                 RS600_WRITE_MCIND(RS600_MC_AGP_LOCATION, agp_loc);
 222         else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
 223                 R500_WRITE_MCIND(R520_MC_AGP_LOCATION, agp_loc);
 224         else
 225                 RADEON_WRITE(RADEON_MC_AGP_LOCATION, agp_loc);
 226 }
 227
 228 void radeon_write_agp_base(drm_radeon_private_t *dev_priv, u64 agp_base)
 229 {
 230         u32 agp_base_hi = upper_32_bits(agp_base);
 231         u32 agp_base_lo = agp_base & 0xffffffff;
 232         u32 r6xx_agp_base = (agp_base >> 22) & 0x3ffff;
 233
 234         /* R6xx/R7xx must be aligned to a 4MB boundry */
 235         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)
 236                 RADEON_WRITE(R700_MC_VM_AGP_BASE, r6xx_agp_base);
 237         else if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
 238                 RADEON_WRITE(R600_MC_VM_AGP_BASE, r6xx_agp_base);
 239         else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) {
 240                 R500_WRITE_MCIND(RV515_MC_AGP_BASE, agp_base_lo);
 241                 R500_WRITE_MCIND(RV515_MC_AGP_BASE_2, agp_base_hi);
 242         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
 243                  ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) {
 244                 RS690_WRITE_MCIND(RS690_MC_AGP_BASE, agp_base_lo);
 245                 RS690_WRITE_MCIND(RS690_MC_AGP_BASE_2, agp_base_hi);
 246         } else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600) {
 247                 RS600_WRITE_MCIND(RS600_AGP_BASE, agp_base_lo);
 248                 RS600_WRITE_MCIND(RS600_AGP_BASE_2, agp_base_hi);
 249         } else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515) {
 250                 R500_WRITE_MCIND(R520_MC_AGP_BASE, agp_base_lo);
 251                 R500_WRITE_MCIND(R520_MC_AGP_BASE_2, agp_base_hi);
 252         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS400) ||
 253                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480)) {
 254                 RADEON_WRITE(RADEON_AGP_BASE, agp_base_lo);
 255                 RADEON_WRITE(RS480_AGP_BASE_2, agp_base_hi);
 256         } else {
 257                 RADEON_WRITE(RADEON_AGP_BASE, agp_base_lo);
 258                 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R200)
 259                         RADEON_WRITE(RADEON_AGP_BASE_2, agp_base_hi);
 260         }
 261 }
 262
 263 void radeon_enable_bm(struct drm_radeon_private *dev_priv)
 264 {
 265         u32 tmp;
 266         /* Turn on bus mastering */
 267         if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
 268             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) {
 269                 /* rs600/rs690/rs740 */
 270                 tmp = RADEON_READ(RADEON_BUS_CNTL) & ~RS600_BUS_MASTER_DIS;
 271                 RADEON_WRITE(RADEON_BUS_CNTL, tmp);
 272         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV350) ||
 273                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R420) ||
 274                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS400) ||
 275                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480)) {
 276                 /* r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */
 277                 tmp = RADEON_READ(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
 278                 RADEON_WRITE(RADEON_BUS_CNTL, tmp);
 279         } /* PCIE cards appears to not need this */
 280 }
 281
 282 static int RADEON_READ_PLL(struct drm_device * dev, int addr)
 283 {
 284         drm_radeon_private_t *dev_priv = dev->dev_private;
 285
 286         RADEON_WRITE8(RADEON_CLOCK_CNTL_INDEX, addr & 0x1f);
 287         return RADEON_READ(RADEON_CLOCK_CNTL_DATA);
 288 }
 289
 290 static u32 RADEON_READ_PCIE(drm_radeon_private_t *dev_priv, int addr)
 291 {
 292         RADEON_WRITE8(RADEON_PCIE_INDEX, addr & 0xff);
 293         return RADEON_READ(RADEON_PCIE_DATA);
 294 }
 295
 296 #if RADEON_FIFO_DEBUG
 297 static void radeon_status(drm_radeon_private_t * dev_priv)
 298 {
 299         printk("%s:\n", __func__);
 300         printk("RBBM_STATUS = 0x%08x\n",
 301                (unsigned int)RADEON_READ(RADEON_RBBM_STATUS));
 302         printk("CP_RB_RTPR = 0x%08x\n",
 303                (unsigned int)RADEON_READ(RADEON_CP_RB_RPTR));
 304         printk("CP_RB_WTPR = 0x%08x\n",
 305                (unsigned int)RADEON_READ(RADEON_CP_RB_WPTR));
 306         printk("AIC_CNTL = 0x%08x\n",
 307                (unsigned int)RADEON_READ(RADEON_AIC_CNTL));
 308         printk("AIC_STAT = 0x%08x\n",
 309                (unsigned int)RADEON_READ(RADEON_AIC_STAT));
 310         printk("AIC_PT_BASE = 0x%08x\n",
 311                (unsigned int)RADEON_READ(RADEON_AIC_PT_BASE));
 312         printk("TLB_ADDR = 0x%08x\n",
 313                (unsigned int)RADEON_READ(RADEON_AIC_TLB_ADDR));
 314         printk("TLB_DATA = 0x%08x\n",
 315                (unsigned int)RADEON_READ(RADEON_AIC_TLB_DATA));
 316 }
 317 #endif
 318
 319 /* ================================================================
 320  * Engine, FIFO control
 321  */
 322
 323 static int radeon_do_pixcache_flush(drm_radeon_private_t * dev_priv)
 324 {
 325         u32 tmp;
 326         int i;
 327
 328         dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
 329
 330         if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) {
 331                 tmp = RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT);
 332                 tmp |= RADEON_RB3D_DC_FLUSH_ALL;
 333                 RADEON_WRITE(RADEON_RB3D_DSTCACHE_CTLSTAT, tmp);
 334
 335                 for (i = 0; i < dev_priv->usec_timeout; i++) {
 336                         if (!(RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT)
 337                               & RADEON_RB3D_DC_BUSY)) {
 338                                 return 0;
 339                         }
 340                         DRM_UDELAY(1);
 341                 }
 342         } else {
 343                 /* don't flush or purge cache here or lockup */
 344                 return 0;
 345         }
 346
 347 #if RADEON_FIFO_DEBUG
 348         DRM_ERROR("failed!\n");
 349         radeon_status(dev_priv);
 350 #endif
 351         return -EBUSY;
 352 }
 353
 354 static int radeon_do_wait_for_fifo(drm_radeon_private_t * dev_priv, int entries)
 355 {
 356         int i;
 357
 358         dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
 359
 360         for (i = 0; i < dev_priv->usec_timeout; i++) {
 361                 int slots = (RADEON_READ(RADEON_RBBM_STATUS)
 362                              & RADEON_RBBM_FIFOCNT_MASK);
 363                 if (slots >= entries)
 364                         return 0;
 365                 DRM_UDELAY(1);
 366         }
 367         DRM_DEBUG("wait for fifo failed status : 0x%08X 0x%08X\n",
 368                  RADEON_READ(RADEON_RBBM_STATUS),
 369                  RADEON_READ(R300_VAP_CNTL_STATUS));
 370
 371 #if RADEON_FIFO_DEBUG
 372         DRM_ERROR("failed!\n");
 373         radeon_status(dev_priv);
 374 #endif
 375         return -EBUSY;
 376 }
 377
 378 static int radeon_do_wait_for_idle(drm_radeon_private_t * dev_priv)
 379 {
 380         int i, ret;
 381
 382         dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
 383
 384         ret = radeon_do_wait_for_fifo(dev_priv, 64);
 385         if (ret)
 386                 return ret;
 387
 388         for (i = 0; i < dev_priv->usec_timeout; i++) {
 389                 if (!(RADEON_READ(RADEON_RBBM_STATUS)
 390                       & RADEON_RBBM_ACTIVE)) {
 391                         radeon_do_pixcache_flush(dev_priv);
 392                         return 0;
 393                 }
 394                 DRM_UDELAY(1);
 395         }
 396         DRM_DEBUG("wait idle failed status : 0x%08X 0x%08X\n",
 397                  RADEON_READ(RADEON_RBBM_STATUS),
 398                  RADEON_READ(R300_VAP_CNTL_STATUS));
 399
 400 #if RADEON_FIFO_DEBUG
 401         DRM_ERROR("failed!\n");
 402         radeon_status(dev_priv);
 403 #endif
 404         return -EBUSY;
 405 }
 406
 407 static void radeon_init_pipes(drm_radeon_private_t *dev_priv)
 408 {
 409         uint32_t gb_tile_config, gb_pipe_sel = 0;
 410
 411         if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV530) {
 412                 uint32_t z_pipe_sel = RADEON_READ(RV530_GB_PIPE_SELECT2);
 413                 if ((z_pipe_sel & 3) == 3)
 414                         dev_priv->num_z_pipes = 2;
 415                 else
 416                         dev_priv->num_z_pipes = 1;
 417         } else
 418                 dev_priv->num_z_pipes = 1;
 419
 420         /* RS4xx/RS6xx/R4xx/R5xx */
 421         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R420) {
 422                 gb_pipe_sel = RADEON_READ(R400_GB_PIPE_SELECT);
 423                 dev_priv->num_gb_pipes = ((gb_pipe_sel >> 12) & 0x3) + 1;
 424         } else {
 425                 /* R3xx */
 426                 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R300) ||
 427                     ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R350)) {
 428                         dev_priv->num_gb_pipes = 2;
 429                 } else {
 430                         /* R3Vxx */
 431                         dev_priv->num_gb_pipes = 1;
 432                 }
 433         }
 434         DRM_INFO("Num pipes: %d\n", dev_priv->num_gb_pipes);
 435
 436         gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16 /*| R300_SUBPIXEL_1_16*/);
 437
 438         switch (dev_priv->num_gb_pipes) {
 439         case 2: gb_tile_config |= R300_PIPE_COUNT_R300; break;
 440         case 3: gb_tile_config |= R300_PIPE_COUNT_R420_3P; break;
 441         case 4: gb_tile_config |= R300_PIPE_COUNT_R420; break;
 442         default:
 443         case 1: gb_tile_config |= R300_PIPE_COUNT_RV350; break;
 444         }
 445
 446         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV515) {
 447                 RADEON_WRITE_PLL(R500_DYN_SCLK_PWMEM_PIPE, (1 | ((gb_pipe_sel >> 8) & 0xf) << 4));
 448                 RADEON_WRITE(R300_SU_REG_DEST, ((1 << dev_priv->num_gb_pipes) - 1));
 449         }
 450         RADEON_WRITE(R300_GB_TILE_CONFIG, gb_tile_config);
 451         radeon_do_wait_for_idle(dev_priv);
 452         RADEON_WRITE(R300_DST_PIPE_CONFIG, RADEON_READ(R300_DST_PIPE_CONFIG) | R300_PIPE_AUTO_CONFIG);
 453         RADEON_WRITE(R300_RB2D_DSTCACHE_MODE, (RADEON_READ(R300_RB2D_DSTCACHE_MODE) |
 454                                                R300_DC_AUTOFLUSH_ENABLE |
 455                                                R300_DC_DC_DISABLE_IGNORE_PE));
 456
 457
 458 }
 459
 460 /* ================================================================
 461  * CP control, initialization
 462  */
 463
 464 /* Load the microcode for the CP */
 465 static void radeon_cp_load_microcode(drm_radeon_private_t * dev_priv)
 466 {
 467         const u32 (*cp)[2];
 468         int i;
 469
 470         DRM_DEBUG("\n");
 471
 472         switch (dev_priv->flags & RADEON_FAMILY_MASK) {
 473         case CHIP_R100:
 474         case CHIP_RV100:
 475         case CHIP_RV200:
 476         case CHIP_RS100:
 477         case CHIP_RS200:
 478                 DRM_INFO("Loading R100 Microcode\n");
 479                 cp = R100_cp_microcode;
 480                 break;
 481         case CHIP_R200:
 482         case CHIP_RV250:
 483         case CHIP_RV280:
 484         case CHIP_RS300:
 485                 DRM_INFO("Loading R200 Microcode\n");
 486                 cp = R200_cp_microcode;
 487                 break;
 488         case CHIP_R300:
 489         case CHIP_R350:
 490         case CHIP_RV350:
 491         case CHIP_RV380:
 492         case CHIP_RS400:
 493         case CHIP_RS480:
 494                 DRM_INFO("Loading R300 Microcode\n");
 495                 cp = R300_cp_microcode;
 496                 break;
 497         case CHIP_R420:
 498         case CHIP_R423:
 499         case CHIP_RV410:
 500                 DRM_INFO("Loading R400 Microcode\n");
 501                 cp = R420_cp_microcode;
 502                 break;
 503         case CHIP_RS690:
 504         case CHIP_RS740:
 505                 DRM_INFO("Loading RS690/RS740 Microcode\n");
 506                 cp = RS690_cp_microcode;
 507                 break;
 508         case CHIP_RS600:
 509                 DRM_INFO("Loading RS600 Microcode\n");
 510                 cp = RS600_cp_microcode;
 511                 break;
 512         case CHIP_RV515:
 513         case CHIP_R520:
 514         case CHIP_RV530:
 515         case CHIP_R580:
 516         case CHIP_RV560:
 517         case CHIP_RV570:
 518                 DRM_INFO("Loading R500 Microcode\n");
 519                 cp = R520_cp_microcode;
 520                 break;
 521         default:
 522                 return;
 523         }
 524
 525         radeon_do_wait_for_idle(dev_priv);
 526
 527         RADEON_WRITE(RADEON_CP_ME_RAM_ADDR, 0);
 528
 529         for (i = 0; i != 256; i++) {
 530                 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH, cp[i][1]);
 531                 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL, cp[i][0]);
 532         }
 533 }
 534
 535 /* Flush any pending commands to the CP.  This should only be used just
 536  * prior to a wait for idle, as it informs the engine that the command
 537  * stream is ending.
 538  */
 539 static void radeon_do_cp_flush(drm_radeon_private_t * dev_priv)
 540 {
 541         DRM_DEBUG("\n");
 542 #if 0
 543         u32 tmp;
 544
 545         tmp = RADEON_READ(RADEON_CP_RB_WPTR) | (1 << 31);
 546         RADEON_WRITE(RADEON_CP_RB_WPTR, tmp);
 547 #endif
 548 }
 549
 550 /* Wait for the CP to go idle.
 551  */
 552 int radeon_do_cp_idle(drm_radeon_private_t * dev_priv)
 553 {
 554         RING_LOCALS;
 555         DRM_DEBUG("\n");
 556
 557         BEGIN_RING(6);
 558
 559         RADEON_PURGE_CACHE();
 560         RADEON_PURGE_ZCACHE();
 561         RADEON_WAIT_UNTIL_IDLE();
 562
 563         ADVANCE_RING();
 564         COMMIT_RING();
 565
 566         return radeon_do_wait_for_idle(dev_priv);
 567 }
 568
 569 /* Start the Command Processor.
 570  */
 571 static void radeon_do_cp_start(drm_radeon_private_t * dev_priv)
 572 {
 573         RING_LOCALS;
 574         DRM_DEBUG("\n");
 575
 576         radeon_do_wait_for_idle(dev_priv);
 577
 578         RADEON_WRITE(RADEON_CP_CSQ_CNTL, dev_priv->cp_mode);
 579
 580         dev_priv->cp_running = 1;
 581
 582         BEGIN_RING(8);
 583         /* isync can only be written through cp on r5xx write it here */
 584         OUT_RING(CP_PACKET0(RADEON_ISYNC_CNTL, 0));
 585         OUT_RING(RADEON_ISYNC_ANY2D_IDLE3D |
 586                  RADEON_ISYNC_ANY3D_IDLE2D |
 587                  RADEON_ISYNC_WAIT_IDLEGUI |
 588                  RADEON_ISYNC_CPSCRATCH_IDLEGUI);
 589         RADEON_PURGE_CACHE();
 590         RADEON_PURGE_ZCACHE();
 591         RADEON_WAIT_UNTIL_IDLE();
 592         ADVANCE_RING();
 593         COMMIT_RING();
 594
 595         dev_priv->track_flush |= RADEON_FLUSH_EMITED | RADEON_PURGE_EMITED;
 596 }
 597
 598 /* Reset the Command Processor.  This will not flush any pending
 599  * commands, so you must wait for the CP command stream to complete
 600  * before calling this routine.
 601  */
 602 static void radeon_do_cp_reset(drm_radeon_private_t * dev_priv)
 603 {
 604         u32 cur_read_ptr;
 605         DRM_DEBUG("\n");
 606
 607         cur_read_ptr = RADEON_READ(RADEON_CP_RB_RPTR);
 608         RADEON_WRITE(RADEON_CP_RB_WPTR, cur_read_ptr);
 609         SET_RING_HEAD(dev_priv, cur_read_ptr);
 610         dev_priv->ring.tail = cur_read_ptr;
 611 }
 612
 613 /* Stop the Command Processor.  This will not flush any pending
 614  * commands, so you must flush the command stream and wait for the CP
 615  * to go idle before calling this routine.
 616  */
 617 static void radeon_do_cp_stop(drm_radeon_private_t * dev_priv)
 618 {
 619         DRM_DEBUG("\n");
 620
 621         RADEON_WRITE(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIDIS_INDDIS);
 622
 623         dev_priv->cp_running = 0;
 624 }
 625
 626 /* Reset the engine.  This will stop the CP if it is running.
 627  */
 628 static int radeon_do_engine_reset(struct drm_device * dev)
 629 {
 630         drm_radeon_private_t *dev_priv = dev->dev_private;
 631         u32 clock_cntl_index = 0, mclk_cntl = 0, rbbm_soft_reset;
 632         DRM_DEBUG("\n");
 633
 634         radeon_do_pixcache_flush(dev_priv);
 635
 636         if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV410) {
 637                 /* may need something similar for newer chips */
 638                 clock_cntl_index = RADEON_READ(RADEON_CLOCK_CNTL_INDEX);
 639                 mclk_cntl = RADEON_READ_PLL(dev, RADEON_MCLK_CNTL);
 640
 641                 RADEON_WRITE_PLL(RADEON_MCLK_CNTL, (mclk_cntl |
 642                                                     RADEON_FORCEON_MCLKA |
 643                                                     RADEON_FORCEON_MCLKB |
 644                                                     RADEON_FORCEON_YCLKA |
 645                                                     RADEON_FORCEON_YCLKB |
 646                                                     RADEON_FORCEON_MC |
 647                                                     RADEON_FORCEON_AIC));
 648         }
 649
 650         rbbm_soft_reset = RADEON_READ(RADEON_RBBM_SOFT_RESET);
 651
 652         RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset |
 653                                               RADEON_SOFT_RESET_CP |
 654                                               RADEON_SOFT_RESET_HI |
 655                                               RADEON_SOFT_RESET_SE |
 656                                               RADEON_SOFT_RESET_RE |
 657                                               RADEON_SOFT_RESET_PP |
 658                                               RADEON_SOFT_RESET_E2 |
 659                                               RADEON_SOFT_RESET_RB));
 660         RADEON_READ(RADEON_RBBM_SOFT_RESET);
 661         RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset &
 662                                               ~(RADEON_SOFT_RESET_CP |
 663                                                 RADEON_SOFT_RESET_HI |
 664                                                 RADEON_SOFT_RESET_SE |
 665                                                 RADEON_SOFT_RESET_RE |
 666                                                 RADEON_SOFT_RESET_PP |
 667                                                 RADEON_SOFT_RESET_E2 |
 668                                                 RADEON_SOFT_RESET_RB)));
 669         RADEON_READ(RADEON_RBBM_SOFT_RESET);
 670
 671         if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV410) {
 672                 RADEON_WRITE_PLL(RADEON_MCLK_CNTL, mclk_cntl);
 673                 RADEON_WRITE(RADEON_CLOCK_CNTL_INDEX, clock_cntl_index);
 674                 RADEON_WRITE(RADEON_RBBM_SOFT_RESET, rbbm_soft_reset);
 675         }
 676
 677         /* setup the raster pipes */
 678         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R300)
 679             radeon_init_pipes(dev_priv);
 680
 681         /* Reset the CP ring */
 682         radeon_do_cp_reset(dev_priv);
 683
 684         /* The CP is no longer running after an engine reset */
 685         dev_priv->cp_running = 0;
 686
 687         /* Reset any pending vertex, indirect buffers */
 688         radeon_freelist_reset(dev);
 689
 690         return 0;
 691 }
 692
 693 static void radeon_cp_init_ring_buffer(struct drm_device * dev,
 694                                        drm_radeon_private_t *dev_priv,
 695                                        struct drm_file *file_priv)
 696 {
 697         u32 ring_start, cur_read_ptr;
 698
 699         /* Initialize the memory controller. With new memory map, the fb location
 700          * is not changed, it should have been properly initialized already. Part
 701          * of the problem is that the code below is bogus, assuming the GART is
 702          * always appended to the fb which is not necessarily the case
 703          */
 704         if (!dev_priv->new_memmap)
 705                 radeon_write_fb_location(dev_priv,
 706                              ((dev_priv->gart_vm_start - 1) & 0xffff0000)
 707                              | (dev_priv->fb_location >> 16));
 708
 709 #if __OS_HAS_AGP
 710         if (dev_priv->flags & RADEON_IS_AGP) {
 711                 radeon_write_agp_base(dev_priv, dev->agp->base);
 712
 713                 radeon_write_agp_location(dev_priv,
 714                              (((dev_priv->gart_vm_start - 1 +
 715                                 dev_priv->gart_size) & 0xffff0000) |
 716                               (dev_priv->gart_vm_start >> 16)));
 717
 718                 ring_start = (dev_priv->cp_ring->offset
 719                               - dev->agp->base
 720                               + dev_priv->gart_vm_start);
 721         } else
 722 #endif
 723                 ring_start = (dev_priv->cp_ring->offset
 724                               - (unsigned long)dev->sg->virtual
 725                               + dev_priv->gart_vm_start);
 726
 727         RADEON_WRITE(RADEON_CP_RB_BASE, ring_start);
 728
 729         /* Set the write pointer delay */
 730         RADEON_WRITE(RADEON_CP_RB_WPTR_DELAY, 0);
 731
 732         /* Initialize the ring buffer's read and write pointers */
 733         cur_read_ptr = RADEON_READ(RADEON_CP_RB_RPTR);
 734         RADEON_WRITE(RADEON_CP_RB_WPTR, cur_read_ptr);
 735         SET_RING_HEAD(dev_priv, cur_read_ptr);
 736         dev_priv->ring.tail = cur_read_ptr;
 737
 738 #if __OS_HAS_AGP
 739         if (dev_priv->flags & RADEON_IS_AGP) {
 740                 RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR,
 741                              dev_priv->ring_rptr->offset
 742                              - dev->agp->base + dev_priv->gart_vm_start);
 743         } else
 744 #endif
 745         {
 746                 RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR,
 747                              dev_priv->ring_rptr->offset
 748                              - ((unsigned long) dev->sg->virtual)
 749                              + dev_priv->gart_vm_start);
 750         }
 751
 752         /* Set ring buffer size */
 753 #ifdef __BIG_ENDIAN
 754         RADEON_WRITE(RADEON_CP_RB_CNTL,
 755                      RADEON_BUF_SWAP_32BIT |
 756                      (dev_priv->ring.fetch_size_l2ow << 18) |
 757                      (dev_priv->ring.rptr_update_l2qw << 8) |
 758                      dev_priv->ring.size_l2qw);
 759 #else
 760         RADEON_WRITE(RADEON_CP_RB_CNTL,
 761                      (dev_priv->ring.fetch_size_l2ow << 18) |
 762                      (dev_priv->ring.rptr_update_l2qw << 8) |
 763                      dev_priv->ring.size_l2qw);
 764 #endif
 765
 766
 767         /* Initialize the scratch register pointer.  This will cause
 768          * the scratch register values to be written out to memory
 769          * whenever they are updated.
 770          *
 771          * We simply put this behind the ring read pointer, this works
 772          * with PCI GART as well as (whatever kind of) AGP GART
 773          */
 774         RADEON_WRITE(RADEON_SCRATCH_ADDR, RADEON_READ(RADEON_CP_RB_RPTR_ADDR)
 775                      + RADEON_SCRATCH_REG_OFFSET);
 776
 777         RADEON_WRITE(RADEON_SCRATCH_UMSK, 0x7);
 778
 779         radeon_enable_bm(dev_priv);
 780
 781         radeon_write_ring_rptr(dev_priv, RADEON_SCRATCHOFF(0), 0);
 782         RADEON_WRITE(RADEON_LAST_FRAME_REG, 0);
 783
 784         radeon_write_ring_rptr(dev_priv, RADEON_SCRATCHOFF(1), 0);
 785         RADEON_WRITE(RADEON_LAST_DISPATCH_REG, 0);
 786
 787         radeon_write_ring_rptr(dev_priv, RADEON_SCRATCHOFF(2), 0);
 788         RADEON_WRITE(RADEON_LAST_CLEAR_REG, 0);
 789
 790         /* reset sarea copies of these */
 791         if (dev_priv->sarea_priv) {
 792                 dev_priv->sarea_priv->last_frame = 0;
 793                 dev_priv->sarea_priv->last_dispatch = 0;
 794                 dev_priv->sarea_priv->last_clear = 0;
 795         }
 796
 797         radeon_do_wait_for_idle(dev_priv);
 798
 799         /* Sync everything up */
 800         RADEON_WRITE(RADEON_ISYNC_CNTL,
 801                      (RADEON_ISYNC_ANY2D_IDLE3D |
 802                       RADEON_ISYNC_ANY3D_IDLE2D |
 803                       RADEON_ISYNC_WAIT_IDLEGUI |
 804                       RADEON_ISYNC_CPSCRATCH_IDLEGUI));
 805
 806 }
 807
 808 static void radeon_test_writeback(drm_radeon_private_t * dev_priv)
 809 {
 810         u32 tmp;
 811
 812         /* Start with assuming that writeback doesn't work */
 813         dev_priv->writeback_works = 0;
 814
 815         /* Writeback doesn't seem to work everywhere, test it here and possibly
 816          * enable it if it appears to work
 817          */
 818         radeon_write_ring_rptr(dev_priv, RADEON_SCRATCHOFF(1), 0);
 819
 820         RADEON_WRITE(RADEON_SCRATCH_REG1, 0xdeadbeef);
 821
 822         for (tmp = 0; tmp < dev_priv->usec_timeout; tmp++) {
 823                 u32 val;
 824
 825                 val = radeon_read_ring_rptr(dev_priv, RADEON_SCRATCHOFF(1));
 826                 if (val == 0xdeadbeef)
 827                         break;
 828                 DRM_UDELAY(1);
 829         }
 830
 831         if (tmp < dev_priv->usec_timeout) {
 832                 dev_priv->writeback_works = 1;
 833                 DRM_INFO("writeback test succeeded in %d usecs\n", tmp);
 834         } else {
 835                 dev_priv->writeback_works = 0;
 836                 DRM_INFO("writeback test failed\n");
 837         }
 838         if (radeon_no_wb == 1) {
 839                 dev_priv->writeback_works = 0;
 840                 DRM_INFO("writeback forced off\n");
 841         }
 842
 843         if (!dev_priv->writeback_works) {
 844                 /* Disable writeback to avoid unnecessary bus master transfer */
 845                 RADEON_WRITE(RADEON_CP_RB_CNTL, RADEON_READ(RADEON_CP_RB_CNTL) |
 846                              RADEON_RB_NO_UPDATE);
 847                 RADEON_WRITE(RADEON_SCRATCH_UMSK, 0);
 848         }
 849 }
 850
 851 /* Enable or disable IGP GART on the chip */
 852 static void radeon_set_igpgart(drm_radeon_private_t * dev_priv, int on)
 853 {
 854         u32 temp;
 855
 856         if (on) {
 857                 DRM_DEBUG("programming igp gart %08X %08lX %08X\n",
 858                           dev_priv->gart_vm_start,
 859                           (long)dev_priv->gart_info.bus_addr,
 860                           dev_priv->gart_size);
 861
 862                 temp = IGP_READ_MCIND(dev_priv, RS480_MC_MISC_CNTL);
 863                 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
 864                     ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
 865                         IGP_WRITE_MCIND(RS480_MC_MISC_CNTL, (RS480_GART_INDEX_REG_EN |
 866                                                              RS690_BLOCK_GFX_D3_EN));
 867                 else
 868                         IGP_WRITE_MCIND(RS480_MC_MISC_CNTL, RS480_GART_INDEX_REG_EN);
 869
 870                 IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN |
 871                                                                RS480_VA_SIZE_32MB));
 872
 873                 temp = IGP_READ_MCIND(dev_priv, RS480_GART_FEATURE_ID);
 874                 IGP_WRITE_MCIND(RS480_GART_FEATURE_ID, (RS480_HANG_EN |
 875                                                         RS480_TLB_ENABLE |
 876                                                         RS480_GTW_LAC_EN |
 877                                                         RS480_1LEVEL_GART));
 878
 879                 temp = dev_priv->gart_info.bus_addr & 0xfffff000;
 880                 temp |= (upper_32_bits(dev_priv->gart_info.bus_addr) & 0xff) << 4;
 881                 IGP_WRITE_MCIND(RS480_GART_BASE, temp);
 882
 883                 temp = IGP_READ_MCIND(dev_priv, RS480_AGP_MODE_CNTL);
 884                 IGP_WRITE_MCIND(RS480_AGP_MODE_CNTL, ((1 << RS480_REQ_TYPE_SNOOP_SHIFT) |
 885                                                       RS480_REQ_TYPE_SNOOP_DIS));
 886
 887                 radeon_write_agp_base(dev_priv, dev_priv->gart_vm_start);
 888
 889                 dev_priv->gart_size = 32*1024*1024;
 890                 temp = (((dev_priv->gart_vm_start - 1 + dev_priv->gart_size) &
 891                          0xffff0000) | (dev_priv->gart_vm_start >> 16));
 892
 893                 radeon_write_agp_location(dev_priv, temp);
 894
 895                 temp = IGP_READ_MCIND(dev_priv, RS480_AGP_ADDRESS_SPACE_SIZE);
 896                 IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN |
 897                                                                RS480_VA_SIZE_32MB));
 898
 899                 do {
 900                         temp = IGP_READ_MCIND(dev_priv, RS480_GART_CACHE_CNTRL);
 901                         if ((temp & RS480_GART_CACHE_INVALIDATE) == 0)
 902                                 break;
 903                         DRM_UDELAY(1);
 904                 } while (1);
 905
 906                 IGP_WRITE_MCIND(RS480_GART_CACHE_CNTRL,
 907                                 RS480_GART_CACHE_INVALIDATE);
 908
 909                 do {
 910                         temp = IGP_READ_MCIND(dev_priv, RS480_GART_CACHE_CNTRL);
 911                         if ((temp & RS480_GART_CACHE_INVALIDATE) == 0)
 912                                 break;
 913                         DRM_UDELAY(1);
 914                 } while (1);
 915
 916                 IGP_WRITE_MCIND(RS480_GART_CACHE_CNTRL, 0);
 917         } else {
 918                 IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, 0);
 919         }
 920 }
 921
 922 /* Enable or disable IGP GART on the chip */
 923 static void rs600_set_igpgart(drm_radeon_private_t *dev_priv, int on)
 924 {
 925         u32 temp;
 926         int i;
 927
 928         if (on) {
 929                 DRM_DEBUG("programming igp gart %08X %08lX %08X\n",
 930                          dev_priv->gart_vm_start,
 931                          (long)dev_priv->gart_info.bus_addr,
 932                          dev_priv->gart_size);
 933
 934                 IGP_WRITE_MCIND(RS600_MC_PT0_CNTL, (RS600_EFFECTIVE_L2_CACHE_SIZE(6) |
 935                                                     RS600_EFFECTIVE_L2_QUEUE_SIZE(6)));
 936
 937                 for (i = 0; i < 19; i++)
 938                         IGP_WRITE_MCIND(RS600_MC_PT0_CLIENT0_CNTL + i,
 939                                         (RS600_ENABLE_TRANSLATION_MODE_OVERRIDE |
 940                                          RS600_SYSTEM_ACCESS_MODE_IN_SYS |
 941                                          RS600_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASSTHROUGH |
 942                                          RS600_EFFECTIVE_L1_CACHE_SIZE(3) |
 943                                          RS600_ENABLE_FRAGMENT_PROCESSING |
 944                                          RS600_EFFECTIVE_L1_QUEUE_SIZE(3)));
 945
 946                 IGP_WRITE_MCIND(RS600_MC_PT0_CONTEXT0_CNTL, (RS600_ENABLE_PAGE_TABLE |
 947                                                              RS600_PAGE_TABLE_TYPE_FLAT));
 948
 949                 /* disable all other contexts */
 950                 for (i = 1; i < 8; i++)
 951                         IGP_WRITE_MCIND(RS600_MC_PT0_CONTEXT0_CNTL + i, 0);
 952
 953                 /* setup the page table aperture */
 954                 IGP_WRITE_MCIND(RS600_MC_PT0_CONTEXT0_FLAT_BASE_ADDR,
 955                                 dev_priv->gart_info.bus_addr);
 956                 IGP_WRITE_MCIND(RS600_MC_PT0_CONTEXT0_FLAT_START_ADDR,
 957                                 dev_priv->gart_vm_start);
 958                 IGP_WRITE_MCIND(RS600_MC_PT0_CONTEXT0_FLAT_END_ADDR,
 959                                 (dev_priv->gart_vm_start + dev_priv->gart_size - 1));
 960                 IGP_WRITE_MCIND(RS600_MC_PT0_CONTEXT0_DEFAULT_READ_ADDR, 0);
 961
 962                 /* setup the system aperture */
 963                 IGP_WRITE_MCIND(RS600_MC_PT0_SYSTEM_APERTURE_LOW_ADDR,
 964                                 dev_priv->gart_vm_start);
 965                 IGP_WRITE_MCIND(RS600_MC_PT0_SYSTEM_APERTURE_HIGH_ADDR,
 966                                 (dev_priv->gart_vm_start + dev_priv->gart_size - 1));
 967
 968                 /* enable page tables */
 969                 temp = IGP_READ_MCIND(dev_priv, RS600_MC_PT0_CNTL);
 970                 IGP_WRITE_MCIND(RS600_MC_PT0_CNTL, (temp | RS600_ENABLE_PT));
 971
 972                 temp = IGP_READ_MCIND(dev_priv, RS600_MC_CNTL1);
 973                 IGP_WRITE_MCIND(RS600_MC_CNTL1, (temp | RS600_ENABLE_PAGE_TABLES));
 974
 975                 /* invalidate the cache */
 976                 temp = IGP_READ_MCIND(dev_priv, RS600_MC_PT0_CNTL);
 977
 978                 temp &= ~(RS600_INVALIDATE_ALL_L1_TLBS | RS600_INVALIDATE_L2_CACHE);
 979                 IGP_WRITE_MCIND(RS600_MC_PT0_CNTL, temp);
 980                 temp = IGP_READ_MCIND(dev_priv, RS600_MC_PT0_CNTL);
 981
 982                 temp |= RS600_INVALIDATE_ALL_L1_TLBS | RS600_INVALIDATE_L2_CACHE;
 983                 IGP_WRITE_MCIND(RS600_MC_PT0_CNTL, temp);
 984                 temp = IGP_READ_MCIND(dev_priv, RS600_MC_PT0_CNTL);
 985
 986                 temp &= ~(RS600_INVALIDATE_ALL_L1_TLBS | RS600_INVALIDATE_L2_CACHE);
 987                 IGP_WRITE_MCIND(RS600_MC_PT0_CNTL, temp);
 988                 temp = IGP_READ_MCIND(dev_priv, RS600_MC_PT0_CNTL);
 989
 990         } else {
 991                 IGP_WRITE_MCIND(RS600_MC_PT0_CNTL, 0);
 992                 temp = IGP_READ_MCIND(dev_priv, RS600_MC_CNTL1);
 993                 temp &= ~RS600_ENABLE_PAGE_TABLES;
 994                 IGP_WRITE_MCIND(RS600_MC_CNTL1, temp);
 995         }
 996 }
 997
 998 static void radeon_set_pciegart(drm_radeon_private_t * dev_priv, int on)
 999 {
1000         u32 tmp = RADEON_READ_PCIE(dev_priv, RADEON_PCIE_TX_GART_CNTL);
1001         if (on) {
1002
1003                 DRM_DEBUG("programming pcie %08X %08lX %08X\n",
1004                           dev_priv->gart_vm_start,
1005                           (long)dev_priv->gart_info.bus_addr,
1006                           dev_priv->gart_size);
1007                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO,
1008                                   dev_priv->gart_vm_start);
1009                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_BASE,
1010                                   dev_priv->gart_info.bus_addr);
1011                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_START_LO,
1012                                   dev_priv->gart_vm_start);
1013                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_END_LO,
1014                                   dev_priv->gart_vm_start +
1015                                   dev_priv->gart_size - 1);
1016
1017                 radeon_write_agp_location(dev_priv, 0xffffffc0); /* ?? */
1018
1019                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL,
1020                                   RADEON_PCIE_TX_GART_EN);
1021         } else {
1022                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL,
1023                                   tmp & ~RADEON_PCIE_TX_GART_EN);
1024         }
1025 }
1026
1027 /* Enable or disable PCI GART on the chip */
1028 static void radeon_set_pcigart(drm_radeon_private_t * dev_priv, int on)
1029 {
1030         u32 tmp;
1031
1032         if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
1033             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740) ||
1034             (dev_priv->flags & RADEON_IS_IGPGART)) {
1035                 radeon_set_igpgart(dev_priv, on);
1036                 return;
1037         }
1038
1039         if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600) {
1040                 rs600_set_igpgart(dev_priv, on);
1041                 return;
1042         }
1043
1044         if (dev_priv->flags & RADEON_IS_PCIE) {
1045                 radeon_set_pciegart(dev_priv, on);
1046                 return;
1047         }
1048
1049         tmp = RADEON_READ(RADEON_AIC_CNTL);
1050
1051         if (on) {
1052                 RADEON_WRITE(RADEON_AIC_CNTL,
1053                              tmp | RADEON_PCIGART_TRANSLATE_EN);
1054
1055                 /* set PCI GART page-table base address
1056                  */
1057                 RADEON_WRITE(RADEON_AIC_PT_BASE, dev_priv->gart_info.bus_addr);
1058
1059                 /* set address range for PCI address translate
1060                  */
1061                 RADEON_WRITE(RADEON_AIC_LO_ADDR, dev_priv->gart_vm_start);
1062                 RADEON_WRITE(RADEON_AIC_HI_ADDR, dev_priv->gart_vm_start
1063                              + dev_priv->gart_size - 1);
1064
1065                 /* Turn off AGP aperture -- is this required for PCI GART?
1066                  */
1067                 radeon_write_agp_location(dev_priv, 0xffffffc0);
1068                 RADEON_WRITE(RADEON_AGP_COMMAND, 0);    /* clear AGP_COMMAND */
1069         } else {
1070                 RADEON_WRITE(RADEON_AIC_CNTL,
1071                              tmp & ~RADEON_PCIGART_TRANSLATE_EN);
1072         }
1073 }
1074
1075 static int radeon_setup_pcigart_surface(drm_radeon_private_t *dev_priv)
1076 {
1077         struct drm_ati_pcigart_info *gart_info = &dev_priv->gart_info;
1078         struct radeon_virt_surface *vp;
1079         int i;
1080
1081         for (i = 0; i < RADEON_MAX_SURFACES * 2; i++) {
1082                 if (!dev_priv->virt_surfaces[i].file_priv ||
1083                     dev_priv->virt_surfaces[i].file_priv == PCIGART_FILE_PRIV)
1084                         break;
1085         }
1086         if (i >= 2 * RADEON_MAX_SURFACES)
1087                 return -ENOMEM;
1088         vp = &dev_priv->virt_surfaces[i];
1089
1090         for (i = 0; i < RADEON_MAX_SURFACES; i++) {
1091                 struct radeon_surface *sp = &dev_priv->surfaces[i];
1092                 if (sp->refcount)
1093                         continue;
1094
1095                 vp->surface_index = i;
1096                 vp->lower = gart_info->bus_addr;
1097                 vp->upper = vp->lower + gart_info->table_size;
1098                 vp->flags = 0;
1099                 vp->file_priv = PCIGART_FILE_PRIV;
1100
1101                 sp->refcount = 1;
1102                 sp->lower = vp->lower;
1103                 sp->upper = vp->upper;
1104                 sp->flags = 0;
1105
1106                 RADEON_WRITE(RADEON_SURFACE0_INFO + 16 * i, sp->flags);
1107                 RADEON_WRITE(RADEON_SURFACE0_LOWER_BOUND + 16 * i, sp->lower);
1108                 RADEON_WRITE(RADEON_SURFACE0_UPPER_BOUND + 16 * i, sp->upper);
1109                 return 0;
1110         }
1111
1112         return -ENOMEM;
1113 }
1114
1115 static int radeon_do_init_cp(struct drm_device *dev, drm_radeon_init_t *init,
1116                              struct drm_file *file_priv)
1117 {
1118         drm_radeon_private_t *dev_priv = dev->dev_private;
1119
1120         DRM_DEBUG("\n");
1121
1122         /* if we require new memory map but we don't have it fail */
1123         if ((dev_priv->flags & RADEON_NEW_MEMMAP) && !dev_priv->new_memmap) {
1124                 DRM_ERROR("Cannot initialise DRM on this card\nThis card requires a new X.org DDX for 3D\n");
1125                 radeon_do_cleanup_cp(dev);
1126                 return -EINVAL;
1127         }
1128
1129         if (init->is_pci && (dev_priv->flags & RADEON_IS_AGP)) {
1130                 DRM_DEBUG("Forcing AGP card to PCI mode\n");
1131                 dev_priv->flags &= ~RADEON_IS_AGP;
1132         } else if (!(dev_priv->flags & (RADEON_IS_AGP | RADEON_IS_PCI | RADEON_IS_PCIE))
1133                    && !init->is_pci) {
1134                 DRM_DEBUG("Restoring AGP flag\n");
1135                 dev_priv->flags |= RADEON_IS_AGP;
1136         }
1137
1138         if ((!(dev_priv->flags & RADEON_IS_AGP)) && !dev->sg) {
1139                 DRM_ERROR("PCI GART memory not allocated!\n");
1140                 radeon_do_cleanup_cp(dev);
1141                 return -EINVAL;
1142         }
1143
1144         dev_priv->usec_timeout = init->usec_timeout;
1145         if (dev_priv->usec_timeout < 1 ||
1146             dev_priv->usec_timeout > RADEON_MAX_USEC_TIMEOUT) {
1147                 DRM_DEBUG("TIMEOUT problem!\n");
1148                 radeon_do_cleanup_cp(dev);
1149                 return -EINVAL;
1150         }
1151
1152         /* Enable vblank on CRTC1 for older X servers
1153          */
1154         dev_priv->vblank_crtc = DRM_RADEON_VBLANK_CRTC1;
1155
1156         switch(init->func) {
1157         case RADEON_INIT_R200_CP:
1158                 dev_priv->microcode_version = UCODE_R200;
1159                 break;
1160         case RADEON_INIT_R300_CP:
1161                 dev_priv->microcode_version = UCODE_R300;
1162                 break;
1163         default:
1164                 dev_priv->microcode_version = UCODE_R100;
1165         }
1166
1167         dev_priv->do_boxes = 0;
1168         dev_priv->cp_mode = init->cp_mode;
1169
1170         /* We don't support anything other than bus-mastering ring mode,
1171          * but the ring can be in either AGP or PCI space for the ring
1172          * read pointer.
1173          */
1174         if ((init->cp_mode != RADEON_CSQ_PRIBM_INDDIS) &&
1175             (init->cp_mode != RADEON_CSQ_PRIBM_INDBM)) {
1176                 DRM_DEBUG("BAD cp_mode (%x)!\n", init->cp_mode);
1177                 radeon_do_cleanup_cp(dev);
1178                 return -EINVAL;
1179         }
1180
1181         switch (init->fb_bpp) {
1182         case 16:
1183                 dev_priv->color_fmt = RADEON_COLOR_FORMAT_RGB565;
1184                 break;
1185         case 32:
1186         default:
1187                 dev_priv->color_fmt = RADEON_COLOR_FORMAT_ARGB8888;
1188                 break;
1189         }
1190         dev_priv->front_offset = init->front_offset;
1191         dev_priv->front_pitch = init->front_pitch;
1192         dev_priv->back_offset = init->back_offset;
1193         dev_priv->back_pitch = init->back_pitch;
1194
1195         switch (init->depth_bpp) {
1196         case 16:
1197                 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_16BIT_INT_Z;
1198                 break;
1199         case 32:
1200         default:
1201                 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_24BIT_INT_Z;
1202                 break;
1203         }
1204         dev_priv->depth_offset = init->depth_offset;
1205         dev_priv->depth_pitch = init->depth_pitch;
1206
1207         /* Hardware state for depth clears.  Remove this if/when we no
1208          * longer clear the depth buffer with a 3D rectangle.  Hard-code
1209          * all values to prevent unwanted 3D state from slipping through
1210          * and screwing with the clear operation.
1211          */
1212         dev_priv->depth_clear.rb3d_cntl = (RADEON_PLANE_MASK_ENABLE |
1213                                            (dev_priv->color_fmt << 10) |
1214                                            (dev_priv->microcode_version ==
1215                                             UCODE_R100 ? RADEON_ZBLOCK16 : 0));
1216
1217         dev_priv->depth_clear.rb3d_zstencilcntl =
1218             (dev_priv->depth_fmt |
1219              RADEON_Z_TEST_ALWAYS |
1220              RADEON_STENCIL_TEST_ALWAYS |
1221              RADEON_STENCIL_S_FAIL_REPLACE |
1222              RADEON_STENCIL_ZPASS_REPLACE |
1223              RADEON_STENCIL_ZFAIL_REPLACE | RADEON_Z_WRITE_ENABLE);
1224
1225         dev_priv->depth_clear.se_cntl = (RADEON_FFACE_CULL_CW |
1226                                          RADEON_BFACE_SOLID |
1227                                          RADEON_FFACE_SOLID |
1228                                          RADEON_FLAT_SHADE_VTX_LAST |
1229                                          RADEON_DIFFUSE_SHADE_FLAT |
1230                                          RADEON_ALPHA_SHADE_FLAT |
1231                                          RADEON_SPECULAR_SHADE_FLAT |
1232                                          RADEON_FOG_SHADE_FLAT |
1233                                          RADEON_VTX_PIX_CENTER_OGL |
1234                                          RADEON_ROUND_MODE_TRUNC |
1235                                          RADEON_ROUND_PREC_8TH_PIX);
1236
1237
1238         dev_priv->ring_offset = init->ring_offset;
1239         dev_priv->ring_rptr_offset = init->ring_rptr_offset;
1240         dev_priv->buffers_offset = init->buffers_offset;
1241         dev_priv->gart_textures_offset = init->gart_textures_offset;
1242
1243         dev_priv->sarea = drm_getsarea(dev);
1244         if (!dev_priv->sarea) {
1245                 DRM_ERROR("could not find sarea!\n");
1246                 radeon_do_cleanup_cp(dev);
1247                 return -EINVAL;
1248         }
1249
1250         dev_priv->cp_ring = drm_core_findmap(dev, init->ring_offset);
1251         if (!dev_priv->cp_ring) {
1252                 DRM_ERROR("could not find cp ring region!\n");
1253                 radeon_do_cleanup_cp(dev);
1254                 return -EINVAL;
1255         }
1256         dev_priv->ring_rptr = drm_core_findmap(dev, init->ring_rptr_offset);
1257         if (!dev_priv->ring_rptr) {
1258                 DRM_ERROR("could not find ring read pointer!\n");
1259                 radeon_do_cleanup_cp(dev);
1260                 return -EINVAL;
1261         }
1262         dev->agp_buffer_token = init->buffers_offset;
1263         dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset);
1264         if (!dev->agp_buffer_map) {
1265                 DRM_ERROR("could not find dma buffer region!\n");
1266                 radeon_do_cleanup_cp(dev);
1267                 return -EINVAL;
1268         }
1269
1270         if (init->gart_textures_offset) {
1271                 dev_priv->gart_textures =
1272                     drm_core_findmap(dev, init->gart_textures_offset);
1273                 if (!dev_priv->gart_textures) {
1274                         DRM_ERROR("could not find GART texture region!\n");
1275                         radeon_do_cleanup_cp(dev);
1276                         return -EINVAL;
1277                 }
1278         }
1279
1280         dev_priv->sarea_priv =
1281             (drm_radeon_sarea_t *) ((u8 *) dev_priv->sarea->handle +
1282                                     init->sarea_priv_offset);
1283
1284 #if __OS_HAS_AGP
1285         if (dev_priv->flags & RADEON_IS_AGP) {
1286                 drm_core_ioremap_wc(dev_priv->cp_ring, dev);
1287                 drm_core_ioremap_wc(dev_priv->ring_rptr, dev);
1288                 drm_core_ioremap_wc(dev->agp_buffer_map, dev);
1289                 if (!dev_priv->cp_ring->handle ||
1290                     !dev_priv->ring_rptr->handle ||
1291                     !dev->agp_buffer_map->handle) {
1292                         DRM_ERROR("could not find ioremap agp regions!\n");
1293                         radeon_do_cleanup_cp(dev);
1294                         return -EINVAL;
1295                 }
1296         } else
1297 #endif
1298         {
1299                 dev_priv->cp_ring->handle =
1300                         (void *)(unsigned long)dev_priv->cp_ring->offset;
1301                 dev_priv->ring_rptr->handle =
1302                         (void *)(unsigned long)dev_priv->ring_rptr->offset;
1303                 dev->agp_buffer_map->handle =
1304                         (void *)(unsigned long)dev->agp_buffer_map->offset;
1305
1306                 DRM_DEBUG("dev_priv->cp_ring->handle %p\n",
1307                           dev_priv->cp_ring->handle);
1308                 DRM_DEBUG("dev_priv->ring_rptr->handle %p\n",
1309                           dev_priv->ring_rptr->handle);
1310                 DRM_DEBUG("dev->agp_buffer_map->handle %p\n",
1311                           dev->agp_buffer_map->handle);
1312         }
1313
1314         dev_priv->fb_location = (radeon_read_fb_location(dev_priv) & 0xffff) << 16;
1315         dev_priv->fb_size =
1316                 ((radeon_read_fb_location(dev_priv) & 0xffff0000u) + 0x10000)
1317                 - dev_priv->fb_location;
1318
1319         dev_priv->front_pitch_offset = (((dev_priv->front_pitch / 64) << 22) |
1320                                         ((dev_priv->front_offset
1321                                           + dev_priv->fb_location) >> 10));
1322
1323         dev_priv->back_pitch_offset = (((dev_priv->back_pitch / 64) << 22) |
1324                                        ((dev_priv->back_offset
1325                                          + dev_priv->fb_location) >> 10));
1326
1327         dev_priv->depth_pitch_offset = (((dev_priv->depth_pitch / 64) << 22) |
1328                                         ((dev_priv->depth_offset
1329                                           + dev_priv->fb_location) >> 10));
1330
1331         dev_priv->gart_size = init->gart_size;
1332
1333         /* New let's set the memory map ... */
1334         if (dev_priv->new_memmap) {
1335                 u32 base = 0;
1336
1337                 DRM_INFO("Setting GART location based on new memory map\n");
1338
1339                 /* If using AGP, try to locate the AGP aperture at the same
1340                  * location in the card and on the bus, though we have to
1341                  * align it down.
1342                  */
1343 #if __OS_HAS_AGP
1344                 if (dev_priv->flags & RADEON_IS_AGP) {
1345                         base = dev->agp->base;
1346                         /* Check if valid */
1347                         if ((base + dev_priv->gart_size - 1) >= dev_priv->fb_location &&
1348                             base < (dev_priv->fb_location + dev_priv->fb_size - 1)) {
1349                                 DRM_INFO("Can't use AGP base @0x%08lx, won't fit\n",
1350                                          dev->agp->base);
1351                                 base = 0;
1352                         }
1353                 }
1354 #endif
1355                 /* If not or if AGP is at 0 (Macs), try to put it elsewhere */
1356                 if (base == 0) {
1357                         base = dev_priv->fb_location + dev_priv->fb_size;
1358                         if (base < dev_priv->fb_location ||
1359                             ((base + dev_priv->gart_size) & 0xfffffffful) < base)
1360                                 base = dev_priv->fb_location
1361                                         - dev_priv->gart_size;
1362                 }
1363                 dev_priv->gart_vm_start = base & 0xffc00000u;
1364                 if (dev_priv->gart_vm_start != base)
1365                         DRM_INFO("GART aligned down from 0x%08x to 0x%08x\n",
1366                                  base, dev_priv->gart_vm_start);
1367         } else {
1368                 DRM_INFO("Setting GART location based on old memory map\n");
1369                 dev_priv->gart_vm_start = dev_priv->fb_location +
1370                         RADEON_READ(RADEON_CONFIG_APER_SIZE);
1371         }
1372
1373 #if __OS_HAS_AGP
1374         if (dev_priv->flags & RADEON_IS_AGP)
1375                 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
1376                                                  - dev->agp->base
1377                                                  + dev_priv->gart_vm_start);
1378         else
1379 #endif
1380                 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
1381                                         - (unsigned long)dev->sg->virtual
1382                                         + dev_priv->gart_vm_start);
1383
1384         DRM_DEBUG("dev_priv->gart_size %d\n", dev_priv->gart_size);
1385         DRM_DEBUG("dev_priv->gart_vm_start 0x%x\n", dev_priv->gart_vm_start);
1386         DRM_DEBUG("dev_priv->gart_buffers_offset 0x%lx\n",
1387                   dev_priv->gart_buffers_offset);
1388
1389         dev_priv->ring.start = (u32 *) dev_priv->cp_ring->handle;
1390         dev_priv->ring.end = ((u32 *) dev_priv->cp_ring->handle
1391                               + init->ring_size / sizeof(u32));
1392         dev_priv->ring.size = init->ring_size;
1393         dev_priv->ring.size_l2qw = drm_order(init->ring_size / 8);
1394
1395         dev_priv->ring.rptr_update = /* init->rptr_update */ 4096;
1396         dev_priv->ring.rptr_update_l2qw = drm_order( /* init->rptr_update */ 4096 / 8);
1397
1398         dev_priv->ring.fetch_size = /* init->fetch_size */ 32;
1399         dev_priv->ring.fetch_size_l2ow = drm_order( /* init->fetch_size */ 32 / 16);
1400         dev_priv->ring.tail_mask = (dev_priv->ring.size / sizeof(u32)) - 1;
1401
1402         dev_priv->ring.high_mark = RADEON_RING_HIGH_MARK;
1403
1404 #if __OS_HAS_AGP
1405         if (dev_priv->flags & RADEON_IS_AGP) {
1406                 /* Turn off PCI GART */
1407                 radeon_set_pcigart(dev_priv, 0);
1408         } else
1409 #endif
1410         {
1411                 u32 sctrl;
1412                 int ret;
1413
1414                 dev_priv->gart_info.table_mask = DMA_BIT_MASK(32);
1415                 /* if we have an offset set from userspace */
1416                 if (dev_priv->pcigart_offset_set) {
1417                         dev_priv->gart_info.bus_addr =
1418                             dev_priv->pcigart_offset + dev_priv->fb_location;
1419                         dev_priv->gart_info.mapping.offset =
1420                             dev_priv->pcigart_offset + dev_priv->fb_aper_offset;
1421                         dev_priv->gart_info.mapping.size =
1422                             dev_priv->gart_info.table_size;
1423
1424                         drm_core_ioremap_wc(&dev_priv->gart_info.mapping, dev);
1425                         dev_priv->gart_info.addr =
1426                             dev_priv->gart_info.mapping.handle;
1427
1428                         if (dev_priv->flags & RADEON_IS_PCIE)
1429                                 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCIE;
1430                         else
1431                                 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCI;
1432                         dev_priv->gart_info.gart_table_location =
1433                             DRM_ATI_GART_FB;
1434
1435                         DRM_DEBUG("Setting phys_pci_gart to %p %08lX\n",
1436                                   dev_priv->gart_info.addr,
1437                                   dev_priv->pcigart_offset);
1438                 } else {
1439                         if (dev_priv->flags & RADEON_IS_IGPGART)
1440                                 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_IGP;
1441                         else
1442                                 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCI;
1443                         dev_priv->gart_info.gart_table_location =
1444                             DRM_ATI_GART_MAIN;
1445                         dev_priv->gart_info.addr = NULL;
1446                         dev_priv->gart_info.bus_addr = 0;
1447                         if (dev_priv->flags & RADEON_IS_PCIE) {
1448                                 DRM_ERROR
1449                                     ("Cannot use PCI Express without GART in FB memory\n");
1450                                 radeon_do_cleanup_cp(dev);
1451                                 return -EINVAL;
1452                         }
1453                 }
1454
1455                 sctrl = RADEON_READ(RADEON_SURFACE_CNTL);
1456                 RADEON_WRITE(RADEON_SURFACE_CNTL, 0);
1457                 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600)
1458                         ret = r600_page_table_init(dev);
1459                 else
1460                         ret = drm_ati_pcigart_init(dev, &dev_priv->gart_info);
1461                 RADEON_WRITE(RADEON_SURFACE_CNTL, sctrl);
1462
1463                 if (!ret) {
1464                         DRM_ERROR("failed to init PCI GART!\n");
1465                         radeon_do_cleanup_cp(dev);
1466                         return -ENOMEM;
1467                 }
1468
1469                 ret = radeon_setup_pcigart_surface(dev_priv);
1470                 if (ret) {
1471                         DRM_ERROR("failed to setup GART surface!\n");
1472                         if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600)
1473                                 r600_page_table_cleanup(dev, &dev_priv->gart_info);
1474                         else
1475                                 drm_ati_pcigart_cleanup(dev, &dev_priv->gart_info);
1476                         radeon_do_cleanup_cp(dev);
1477                         return ret;
1478                 }
1479
1480                 /* Turn on PCI GART */
1481                 radeon_set_pcigart(dev_priv, 1);
1482         }
1483
1484         radeon_cp_load_microcode(dev_priv);
1485         radeon_cp_init_ring_buffer(dev, dev_priv, file_priv);
1486
1487         dev_priv->last_buf = 0;
1488
1489         radeon_do_engine_reset(dev);
1490         radeon_test_writeback(dev_priv);
1491
1492         return 0;
1493 }
1494
1495 static int radeon_do_cleanup_cp(struct drm_device * dev)
1496 {
1497         drm_radeon_private_t *dev_priv = dev->dev_private;
1498         DRM_DEBUG("\n");
1499
1500         /* Make sure interrupts are disabled here because the uninstall ioctl
1501          * may not have been called from userspace and after dev_private
1502          * is freed, it's too late.
1503          */
1504         if (dev->irq_enabled)
1505                 drm_irq_uninstall(dev);
1506
1507 #if __OS_HAS_AGP
1508         if (dev_priv->flags & RADEON_IS_AGP) {
1509                 if (dev_priv->cp_ring != NULL) {
1510                         drm_core_ioremapfree(dev_priv->cp_ring, dev);
1511                         dev_priv->cp_ring = NULL;
1512                 }
1513                 if (dev_priv->ring_rptr != NULL) {
1514                         drm_core_ioremapfree(dev_priv->ring_rptr, dev);
1515                         dev_priv->ring_rptr = NULL;
1516                 }
1517                 if (dev->agp_buffer_map != NULL) {
1518                         drm_core_ioremapfree(dev->agp_buffer_map, dev);
1519                         dev->agp_buffer_map = NULL;
1520                 }
1521         } else
1522 #endif
1523         {
1524
1525                 if (dev_priv->gart_info.bus_addr) {
1526                         /* Turn off PCI GART */
1527                         radeon_set_pcigart(dev_priv, 0);
1528                         if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600)
1529                                 r600_page_table_cleanup(dev, &dev_priv->gart_info);
1530                         else {
1531                                 if (!drm_ati_pcigart_cleanup(dev, &dev_priv->gart_info))
1532                                         DRM_ERROR("failed to cleanup PCI GART!\n");
1533                         }
1534                 }
1535
1536                 if (dev_priv->gart_info.gart_table_location == DRM_ATI_GART_FB)
1537                 {
1538                         drm_core_ioremapfree(&dev_priv->gart_info.mapping, dev);
1539                         dev_priv->gart_info.addr = 0;
1540                 }
1541         }
1542         /* only clear to the start of flags */
1543         memset(dev_priv, 0, offsetof(drm_radeon_private_t, flags));
1544
1545         return 0;
1546 }
1547
1548 /* This code will reinit the Radeon CP hardware after a resume from disc.
1549  * AFAIK, it would be very difficult to pickle the state at suspend time, so
1550  * here we make sure that all Radeon hardware initialisation is re-done without
1551  * affecting running applications.
1552  *
1553  * Charl P. Botha <http://cpbotha.net>
1554  */
1555 static int radeon_do_resume_cp(struct drm_device *dev, struct drm_file *file_priv)
1556 {
1557         drm_radeon_private_t *dev_priv = dev->dev_private;
1558
1559         if (!dev_priv) {
1560                 DRM_ERROR("Called with no initialization\n");
1561                 return -EINVAL;
1562         }
1563
1564         DRM_DEBUG("Starting radeon_do_resume_cp()\n");
1565
1566 #if __OS_HAS_AGP
1567         if (dev_priv->flags & RADEON_IS_AGP) {
1568                 /* Turn off PCI GART */
1569                 radeon_set_pcigart(dev_priv, 0);
1570         } else
1571 #endif
1572         {
1573                 /* Turn on PCI GART */
1574                 radeon_set_pcigart(dev_priv, 1);
1575         }
1576
1577         radeon_cp_load_microcode(dev_priv);
1578         radeon_cp_init_ring_buffer(dev, dev_priv, file_priv);
1579
1580         radeon_do_engine_reset(dev);
1581         radeon_irq_set_state(dev, RADEON_SW_INT_ENABLE, 1);
1582
1583         DRM_DEBUG("radeon_do_resume_cp() complete\n");
1584
1585         return 0;
1586 }
1587
1588 int radeon_cp_init(struct drm_device *dev, void *data, struct drm_file *file_priv)
1589 {
1590         drm_radeon_private_t *dev_priv = dev->dev_private;
1591         drm_radeon_init_t *init = data;
1592
1593         LOCK_TEST_WITH_RETURN(dev, file_priv);
1594
1595         if (init->func == RADEON_INIT_R300_CP)
1596                 r300_init_reg_flags(dev);
1597
1598         switch (init->func) {
1599         case RADEON_INIT_CP:
1600         case RADEON_INIT_R200_CP:
1601         case RADEON_INIT_R300_CP:
1602                 return radeon_do_init_cp(dev, init, file_priv);
1603         case RADEON_INIT_R600_CP:
1604                 return r600_do_init_cp(dev, init, file_priv);
1605         case RADEON_CLEANUP_CP:
1606                 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1607                         return r600_do_cleanup_cp(dev);
1608                 else
1609                         return radeon_do_cleanup_cp(dev);
1610         }
1611
1612         return -EINVAL;
1613 }
1614
1615 int radeon_cp_start(struct drm_device *dev, void *data, struct drm_file *file_priv)
1616 {
1617         drm_radeon_private_t *dev_priv = dev->dev_private;
1618         DRM_DEBUG("\n");
1619
1620         LOCK_TEST_WITH_RETURN(dev, file_priv);
1621
1622         if (dev_priv->cp_running) {
1623                 DRM_DEBUG("while CP running\n");
1624                 return 0;
1625         }
1626         if (dev_priv->cp_mode == RADEON_CSQ_PRIDIS_INDDIS) {
1627                 DRM_DEBUG("called with bogus CP mode (%d)\n",
1628                           dev_priv->cp_mode);
1629                 return 0;
1630         }
1631
1632         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1633                 r600_do_cp_start(dev_priv);
1634         else
1635                 radeon_do_cp_start(dev_priv);
1636
1637         return 0;
1638 }
1639
1640 /* Stop the CP.  The engine must have been idled before calling this
1641  * routine.
1642  */
1643 int radeon_cp_stop(struct drm_device *dev, void *data, struct drm_file *file_priv)
1644 {
1645         drm_radeon_private_t *dev_priv = dev->dev_private;
1646         drm_radeon_cp_stop_t *stop = data;
1647         int ret;
1648         DRM_DEBUG("\n");
1649
1650         LOCK_TEST_WITH_RETURN(dev, file_priv);
1651
1652         if (!dev_priv->cp_running)
1653                 return 0;
1654
1655         /* Flush any pending CP commands.  This ensures any outstanding
1656          * commands are exectuted by the engine before we turn it off.
1657          */
1658         if (stop->flush) {
1659                 radeon_do_cp_flush(dev_priv);
1660         }
1661
1662         /* If we fail to make the engine go idle, we return an error
1663          * code so that the DRM ioctl wrapper can try again.
1664          */
1665         if (stop->idle) {
1666                 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1667                         ret = r600_do_cp_idle(dev_priv);
1668                 else
1669                         ret = radeon_do_cp_idle(dev_priv);
1670                 if (ret)
1671                         return ret;
1672         }
1673
1674         /* Finally, we can turn off the CP.  If the engine isn't idle,
1675          * we will get some dropped triangles as they won't be fully
1676          * rendered before the CP is shut down.
1677          */
1678         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1679                 r600_do_cp_stop(dev_priv);
1680         else
1681                 radeon_do_cp_stop(dev_priv);
1682
1683         /* Reset the engine */
1684         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1685                 r600_do_engine_reset(dev);
1686         else
1687                 radeon_do_engine_reset(dev);
1688
1689         return 0;
1690 }
1691
1692 void radeon_do_release(struct drm_device * dev)
1693 {
1694         drm_radeon_private_t *dev_priv = dev->dev_private;
1695         int i, ret;
1696
1697         if (dev_priv) {
1698                 if (dev_priv->cp_running) {
1699                         /* Stop the cp */
1700                         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) {
1701                                 while ((ret = r600_do_cp_idle(dev_priv)) != 0) {
1702                                         DRM_DEBUG("radeon_do_cp_idle %d\n", ret);
1703                                         mtx_sleep(&ret, &dev->dev_lock, 0,
1704                                             "rdnrel", 1);
1705                                 }
1706                         } else {
1707                                 while ((ret = radeon_do_cp_idle(dev_priv)) != 0) {
1708                                         DRM_DEBUG("radeon_do_cp_idle %d\n", ret);
1709                                         mtx_sleep(&ret, &dev->dev_lock, 0,
1710                                             "rdnrel", 1);
1711                                 }
1712                         }
1713                         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) {
1714                                 r600_do_cp_stop(dev_priv);
1715                                 r600_do_engine_reset(dev);
1716                         } else {
1717                                 radeon_do_cp_stop(dev_priv);
1718                                 radeon_do_engine_reset(dev);
1719                         }
1720                 }
1721
1722                 if ((dev_priv->flags & RADEON_FAMILY_MASK) < CHIP_R600) {
1723                         /* Disable *all* interrupts */
1724                         if (dev_priv->mmio)     /* remove this after permanent addmaps */
1725                                 RADEON_WRITE(RADEON_GEN_INT_CNTL, 0);
1726
1727                         if (dev_priv->mmio) {   /* remove all surfaces */
1728                                 for (i = 0; i < RADEON_MAX_SURFACES; i++) {
1729                                         RADEON_WRITE(RADEON_SURFACE0_INFO + 16 * i, 0);
1730                                         RADEON_WRITE(RADEON_SURFACE0_LOWER_BOUND +
1731                                                      16 * i, 0);
1732                                         RADEON_WRITE(RADEON_SURFACE0_UPPER_BOUND +
1733                                                      16 * i, 0);
1734                                 }
1735                         }
1736                 }
1737
1738                 /* Free memory heap structures */
1739                 radeon_mem_takedown(&(dev_priv->gart_heap));
1740                 radeon_mem_takedown(&(dev_priv->fb_heap));
1741
1742                 /* deallocate kernel resources */
1743                 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1744                         r600_do_cleanup_cp(dev);
1745                 else
1746                         radeon_do_cleanup_cp(dev);
1747         }
1748 }
1749
1750 /* Just reset the CP ring.  Called as part of an X Server engine reset.
1751  */
1752 int radeon_cp_reset(struct drm_device *dev, void *data, struct drm_file *file_priv)
1753 {
1754         drm_radeon_private_t *dev_priv = dev->dev_private;
1755         DRM_DEBUG("\n");
1756
1757         LOCK_TEST_WITH_RETURN(dev, file_priv);
1758
1759         if (!dev_priv) {
1760                 DRM_DEBUG("called before init done\n");
1761                 return -EINVAL;
1762         }
1763
1764         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1765                 r600_do_cp_reset(dev_priv);
1766         else
1767                 radeon_do_cp_reset(dev_priv);
1768
1769         /* The CP is no longer running after an engine reset */
1770         dev_priv->cp_running = 0;
1771
1772         return 0;
1773 }
1774
1775 int radeon_cp_idle(struct drm_device *dev, void *data, struct drm_file *file_priv)
1776 {
1777         drm_radeon_private_t *dev_priv = dev->dev_private;
1778         DRM_DEBUG("\n");
1779
1780         LOCK_TEST_WITH_RETURN(dev, file_priv);
1781
1782         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1783                 return r600_do_cp_idle(dev_priv);
1784         else
1785                 return radeon_do_cp_idle(dev_priv);
1786 }
1787
1788 /* Added by Charl P. Botha to call radeon_do_resume_cp().
1789  */
1790 int radeon_cp_resume(struct drm_device *dev, void *data, struct drm_file *file_priv)
1791 {
1792         drm_radeon_private_t *dev_priv = dev->dev_private;
1793         DRM_DEBUG("\n");
1794
1795         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1796                 return r600_do_resume_cp(dev, file_priv);
1797         else
1798                 return radeon_do_resume_cp(dev, file_priv);
1799 }
1800
1801 int radeon_engine_reset(struct drm_device *dev, void *data, struct drm_file *file_priv)
1802 {
1803         drm_radeon_private_t *dev_priv = dev->dev_private;
1804         DRM_DEBUG("\n");
1805
1806         LOCK_TEST_WITH_RETURN(dev, file_priv);
1807
1808         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1809                 return r600_do_engine_reset(dev);
1810         else
1811                 return radeon_do_engine_reset(dev);
1812 }
1813
1814 /* ================================================================
1815  * Fullscreen mode
1816  */
1817
1818 /* KW: Deprecated to say the least:
1819  */
1820 int radeon_fullscreen(struct drm_device *dev, void *data, struct drm_file *file_priv)
1821 {
1822         return 0;
1823 }
1824
1825 /* ================================================================
1826  * Freelist management
1827  */
1828
1829 /* Original comment: FIXME: ROTATE_BUFS is a hack to cycle through
1830  *   bufs until freelist code is used.  Note this hides a problem with
1831  *   the scratch register * (used to keep track of last buffer
1832  *   completed) being written to before * the last buffer has actually
1833  *   completed rendering.
1834  *
1835  * KW:  It's also a good way to find free buffers quickly.
1836  *
1837  * KW: Ideally this loop wouldn't exist, and freelist_get wouldn't
1838  * sleep.  However, bugs in older versions of radeon_accel.c mean that
1839  * we essentially have to do this, else old clients will break.
1840  *
1841  * However, it does leave open a potential deadlock where all the
1842  * buffers are held by other clients, which can't release them because
1843  * they can't get the lock.
1844  */
1845
1846 struct drm_buf *radeon_freelist_get(struct drm_device * dev)
1847 {
1848         struct drm_device_dma *dma = dev->dma;
1849         drm_radeon_private_t *dev_priv = dev->dev_private;
1850         drm_radeon_buf_priv_t *buf_priv;
1851         struct drm_buf *buf;
1852         int i, t;
1853         int start;
1854
1855         if (++dev_priv->last_buf >= dma->buf_count)
1856                 dev_priv->last_buf = 0;
1857
1858         start = dev_priv->last_buf;
1859
1860         for (t = 0; t < dev_priv->usec_timeout; t++) {
1861                 u32 done_age = GET_SCRATCH(dev_priv, 1);
1862                 DRM_DEBUG("done_age = %d\n", done_age);
1863                 for (i = 0; i < dma->buf_count; i++) {
1864                         buf = dma->buflist[start];
1865                         buf_priv = buf->dev_private;
1866                         if (buf->file_priv == NULL || (buf->pending &&
1867                                                        buf_priv->age <=
1868                                                        done_age)) {
1869                                 dev_priv->stats.requested_bufs++;
1870                                 buf->pending = 0;
1871                                 return buf;
1872                         }
1873                         if (++start >= dma->buf_count)
1874                                 start = 0;
1875                 }
1876
1877                 if (t) {
1878                         DRM_UDELAY(1);
1879                         dev_priv->stats.freelist_loops++;
1880                 }
1881         }
1882
1883         return NULL;
1884 }
1885
1886 void radeon_freelist_reset(struct drm_device * dev)
1887 {
1888         struct drm_device_dma *dma = dev->dma;
1889         drm_radeon_private_t *dev_priv = dev->dev_private;
1890         int i;
1891
1892         dev_priv->last_buf = 0;
1893         for (i = 0; i < dma->buf_count; i++) {
1894                 struct drm_buf *buf = dma->buflist[i];
1895                 drm_radeon_buf_priv_t *buf_priv = buf->dev_private;
1896                 buf_priv->age = 0;
1897         }
1898 }
1899
1900 /* ================================================================
1901  * CP command submission
1902  */
1903
1904 int radeon_wait_ring(drm_radeon_private_t * dev_priv, int n)
1905 {
1906         drm_radeon_ring_buffer_t *ring = &dev_priv->ring;
1907         int i;
1908         u32 last_head = GET_RING_HEAD(dev_priv);
1909
1910         for (i = 0; i < dev_priv->usec_timeout; i++) {
1911                 u32 head = GET_RING_HEAD(dev_priv);
1912
1913                 ring->space = (head - ring->tail) * sizeof(u32);
1914                 if (ring->space <= 0)
1915                         ring->space += ring->size;
1916                 if (ring->space > n)
1917                         return 0;
1918
1919                 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
1920
1921                 if (head != last_head)
1922                         i = 0;
1923                 last_head = head;
1924
1925                 DRM_UDELAY(1);
1926         }
1927
1928         /* FIXME: This return value is ignored in the BEGIN_RING macro! */
1929 #if RADEON_FIFO_DEBUG
1930         radeon_status(dev_priv);
1931         DRM_ERROR("failed!\n");
1932 #endif
1933         return -EBUSY;
1934 }
1935
1936 static int radeon_cp_get_buffers(struct drm_device *dev,
1937                                  struct drm_file *file_priv,
1938                                  struct drm_dma * d)
1939 {
1940         int i;
1941         struct drm_buf *buf;
1942
1943         for (i = d->granted_count; i < d->request_count; i++) {
1944                 buf = radeon_freelist_get(dev);
1945                 if (!buf)
1946                         return -EBUSY;  /* NOTE: broken client */
1947
1948                 buf->file_priv = file_priv;
1949
1950                 if (DRM_COPY_TO_USER(&d->request_indices[i], &buf->idx,
1951                                      sizeof(buf->idx)))
1952                         return -EFAULT;
1953                 if (DRM_COPY_TO_USER(&d->request_sizes[i], &buf->total,
1954                                      sizeof(buf->total)))
1955                         return -EFAULT;
1956
1957                 d->granted_count++;
1958         }
1959         return 0;
1960 }
1961
1962 int radeon_cp_buffers(struct drm_device *dev, void *data, struct drm_file *file_priv)
1963 {
1964         struct drm_device_dma *dma = dev->dma;
1965         int ret = 0;
1966         struct drm_dma *d = data;
1967
1968         LOCK_TEST_WITH_RETURN(dev, file_priv);
1969
1970         /* Please don't send us buffers.
1971          */
1972         if (d->send_count != 0) {
1973                 DRM_ERROR("Process %d trying to send %d buffers via drmDMA\n",
1974                           DRM_CURRENTPID, d->send_count);
1975                 return -EINVAL;
1976         }
1977
1978         /* We'll send you buffers.
1979          */
1980         if (d->request_count < 0 || d->request_count > dma->buf_count) {
1981                 DRM_ERROR("Process %d trying to get %d buffers (of %d max)\n",
1982                           DRM_CURRENTPID, d->request_count, dma->buf_count);
1983                 return -EINVAL;
1984         }
1985
1986         d->granted_count = 0;
1987
1988         if (d->request_count) {
1989                 ret = radeon_cp_get_buffers(dev, file_priv, d);
1990         }
1991
1992         return ret;
1993 }
1994
1995 int radeon_driver_load(struct drm_device *dev, unsigned long flags)
1996 {
1997         drm_radeon_private_t *dev_priv;
1998         int ret = 0;
1999
2000         dev_priv = drm_alloc(sizeof(drm_radeon_private_t), DRM_MEM_DRIVER);
2001         if (dev_priv == NULL)
2002                 return -ENOMEM;
2003
2004         memset(dev_priv, 0, sizeof(drm_radeon_private_t));
2005         dev->dev_private = (void *)dev_priv;
2006         dev_priv->flags = flags;
2007
2008         switch (flags & RADEON_FAMILY_MASK) {
2009         case CHIP_R100:
2010         case CHIP_RV200:
2011         case CHIP_R200:
2012         case CHIP_R300:
2013         case CHIP_R350:
2014         case CHIP_R420:
2015         case CHIP_R423:
2016         case CHIP_RV410:
2017         case CHIP_RV515:
2018         case CHIP_R520:
2019         case CHIP_RV570:
2020         case CHIP_R580:
2021                 dev_priv->flags |= RADEON_HAS_HIERZ;
2022                 break;
2023         default:
2024                 /* all other chips have no hierarchical z buffer */
2025                 break;
2026         }
2027
2028         if (drm_device_is_agp(dev))
2029                 dev_priv->flags |= RADEON_IS_AGP;
2030         else if (drm_device_is_pcie(dev))
2031                 dev_priv->flags |= RADEON_IS_PCIE;
2032         else
2033                 dev_priv->flags |= RADEON_IS_PCI;
2034
2035         mtx_init(&dev_priv->cs.cs_mutex, "cs_mtx", NULL, MTX_DEF);
2036
2037         ret = drm_addmap(dev, drm_get_resource_start(dev, 2),
2038                          drm_get_resource_len(dev, 2), _DRM_REGISTERS,
2039                          _DRM_READ_ONLY | _DRM_DRIVER, &dev_priv->mmio);
2040         if (ret != 0)
2041                 goto error;
2042
2043         ret = drm_vblank_init(dev, 2);
2044         if (ret != 0)
2045                 goto error;
2046
2047         dev->max_vblank_count = 0x001fffff;
2048
2049         DRM_DEBUG("%s card detected\n",
2050                   ((dev_priv->flags & RADEON_IS_AGP) ? "AGP" :
2051                     (((dev_priv->flags & RADEON_IS_PCIE) ? "PCIE" : "PCI"))));
2052
2053         return ret;
2054
2055 error:
2056         radeon_driver_unload(dev);
2057         return ret;
2058 }
2059
2060 /* Create mappings for registers and framebuffer so userland doesn't necessarily
2061  * have to find them.
2062  */
2063 int radeon_driver_firstopen(struct drm_device *dev)
2064 {
2065         int ret;
2066         drm_local_map_t *map;
2067         drm_radeon_private_t *dev_priv = dev->dev_private;
2068
2069         dev_priv->gart_info.table_size = RADEON_PCIGART_TABLE_SIZE;
2070
2071         dev_priv->fb_aper_offset = drm_get_resource_start(dev, 0);
2072         ret = drm_addmap(dev, dev_priv->fb_aper_offset,
2073                          drm_get_resource_len(dev, 0), _DRM_FRAME_BUFFER,
2074                          _DRM_WRITE_COMBINING, &map);
2075         if (ret != 0)
2076                 return ret;
2077
2078         return 0;
2079 }
2080
2081 int radeon_driver_unload(struct drm_device *dev)
2082 {
2083         drm_radeon_private_t *dev_priv = dev->dev_private;
2084
2085         DRM_DEBUG("\n");
2086
2087         drm_rmmap(dev, dev_priv->mmio);
2088
2089         mtx_destroy(&dev_priv->cs.cs_mutex);
2090
2091         drm_free(dev_priv, sizeof(*dev_priv), DRM_MEM_DRIVER);
2092
2093         dev->dev_private = NULL;
2094         return 0;
2095 }
2096
2097 void radeon_commit_ring(drm_radeon_private_t *dev_priv)
2098 {
2099         int i;
2100         u32 *ring;
2101         int tail_aligned;
2102
2103         /* check if the ring is padded out to 16-dword alignment */
2104
2105         tail_aligned = dev_priv->ring.tail & (RADEON_RING_ALIGN - 1);
2106         if (tail_aligned) {
2107                 int num_p2 = RADEON_RING_ALIGN - tail_aligned;
2108
2109                 ring = dev_priv->ring.start;
2110                 /* pad with some CP_PACKET2 */
2111                 for (i = 0; i < num_p2; i++)
2112                         ring[dev_priv->ring.tail + i] = CP_PACKET2();
2113
2114                 dev_priv->ring.tail += i;
2115
2116                 dev_priv->ring.space -= num_p2 * sizeof(u32);
2117         }
2118
2119         dev_priv->ring.tail &= dev_priv->ring.tail_mask;
2120
2121         DRM_MEMORYBARRIER();
2122         GET_RING_HEAD( dev_priv );
2123
2124         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) {
2125                 RADEON_WRITE(R600_CP_RB_WPTR, dev_priv->ring.tail);
2126                 /* read from PCI bus to ensure correct posting */
2127                 RADEON_READ(R600_CP_RB_RPTR);
2128         } else {
2129                 RADEON_WRITE(RADEON_CP_RB_WPTR, dev_priv->ring.tail);
2130                 /* read from PCI bus to ensure correct posting */
2131                 RADEON_READ(RADEON_CP_RB_RPTR);
2132         }
2133 }