sys/dev/e1000/e1000_82571.c

   1 /******************************************************************************
   2
   3   Copyright (c) 2001-2010, Intel Corporation
   4   All rights reserved.
   5
   6   Redistribution and use in source and binary forms, with or without
   7   modification, are permitted provided that the following conditions are met:
   8
   9    1. Redistributions of source code must retain the above copyright notice,
  10       this list of conditions and the following disclaimer.
  11
  12    2. Redistributions in binary form must reproduce the above copyright
  13       notice, this list of conditions and the following disclaimer in the
  14       documentation and/or other materials provided with the distribution.
  15
  16    3. Neither the name of the Intel Corporation nor the names of its
  17       contributors may be used to endorse or promote products derived from
  18       this software without specific prior written permission.
  19
  20   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23   ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30   POSSIBILITY OF SUCH DAMAGE.
  31
  32 ******************************************************************************/
  33 /*$FreeBSD$*/
  34
  35 /*
  36  * 82571EB Gigabit Ethernet Controller
  37  * 82571EB Gigabit Ethernet Controller (Copper)
  38  * 82571EB Gigabit Ethernet Controller (Fiber)
  39  * 82571EB Dual Port Gigabit Mezzanine Adapter
  40  * 82571EB Quad Port Gigabit Mezzanine Adapter
  41  * 82571PT Gigabit PT Quad Port Server ExpressModule
  42  * 82572EI Gigabit Ethernet Controller (Copper)
  43  * 82572EI Gigabit Ethernet Controller (Fiber)
  44  * 82572EI Gigabit Ethernet Controller
  45  * 82573V Gigabit Ethernet Controller (Copper)
  46  * 82573E Gigabit Ethernet Controller (Copper)
  47  * 82573L Gigabit Ethernet Controller
  48  * 82574L Gigabit Network Connection
  49  * 82583V Gigabit Network Connection
  50  */
  51
  52 #include "e1000_api.h"
  53
  54 static s32  e1000_init_phy_params_82571(struct e1000_hw *hw);
  55 static s32  e1000_init_nvm_params_82571(struct e1000_hw *hw);
  56 static s32  e1000_init_mac_params_82571(struct e1000_hw *hw);
  57 static s32  e1000_acquire_nvm_82571(struct e1000_hw *hw);
  58 static void e1000_release_nvm_82571(struct e1000_hw *hw);
  59 static s32  e1000_write_nvm_82571(struct e1000_hw *hw, u16 offset,
  60                                   u16 words, u16 *data);
  61 static s32  e1000_update_nvm_checksum_82571(struct e1000_hw *hw);
  62 static s32  e1000_validate_nvm_checksum_82571(struct e1000_hw *hw);
  63 static s32  e1000_get_cfg_done_82571(struct e1000_hw *hw);
  64 static s32  e1000_set_d0_lplu_state_82571(struct e1000_hw *hw,
  65                                           bool active);
  66 static s32  e1000_reset_hw_82571(struct e1000_hw *hw);
  67 static s32  e1000_init_hw_82571(struct e1000_hw *hw);
  68 static void e1000_clear_vfta_82571(struct e1000_hw *hw);
  69 static bool e1000_check_mng_mode_82574(struct e1000_hw *hw);
  70 static s32 e1000_led_on_82574(struct e1000_hw *hw);
  71 static s32  e1000_setup_link_82571(struct e1000_hw *hw);
  72 static s32  e1000_setup_copper_link_82571(struct e1000_hw *hw);
  73 static s32  e1000_check_for_serdes_link_82571(struct e1000_hw *hw);
  74 static s32  e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw);
  75 static s32  e1000_valid_led_default_82571(struct e1000_hw *hw, u16 *data);
  76 static void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw);
  77 static s32  e1000_get_hw_semaphore_82571(struct e1000_hw *hw);
  78 static s32  e1000_fix_nvm_checksum_82571(struct e1000_hw *hw);
  79 static s32  e1000_get_phy_id_82571(struct e1000_hw *hw);
  80 static void e1000_put_hw_semaphore_82571(struct e1000_hw *hw);
  81 static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw);
  82 static s32  e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset,
  83                                        u16 words, u16 *data);
  84 static s32  e1000_read_mac_addr_82571(struct e1000_hw *hw);
  85 static void e1000_power_down_phy_copper_82571(struct e1000_hw *hw);
  86
  87 /**
  88  *  e1000_init_phy_params_82571 - Init PHY func ptrs.
  89  *  @hw: pointer to the HW structure
  90  **/
  91 static s32 e1000_init_phy_params_82571(struct e1000_hw *hw)
  92 {
  93         struct e1000_phy_info *phy = &hw->phy;
  94         s32 ret_val = E1000_SUCCESS;
  95
  96         DEBUGFUNC("e1000_init_phy_params_82571");
  97
  98         if (hw->phy.media_type != e1000_media_type_copper) {
  99                 phy->type = e1000_phy_none;
 100                 goto out;
 101         }
 102
 103         phy->addr                        = 1;
 104         phy->autoneg_mask                = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 105         phy->reset_delay_us              = 100;
 106
 107         phy->ops.acquire                 = e1000_get_hw_semaphore_82571;
 108         phy->ops.check_reset_block       = e1000_check_reset_block_generic;
 109         phy->ops.release                 = e1000_put_hw_semaphore_82571;
 110         phy->ops.reset                   = e1000_phy_hw_reset_generic;
 111         phy->ops.set_d0_lplu_state       = e1000_set_d0_lplu_state_82571;
 112         phy->ops.set_d3_lplu_state       = e1000_set_d3_lplu_state_generic;
 113         phy->ops.power_up                = e1000_power_up_phy_copper;
 114         phy->ops.power_down              = e1000_power_down_phy_copper_82571;
 115
 116         switch (hw->mac.type) {
 117         case e1000_82571:
 118         case e1000_82572:
 119                 phy->type                   = e1000_phy_igp_2;
 120                 phy->ops.get_cfg_done       = e1000_get_cfg_done_82571;
 121                 phy->ops.get_info           = e1000_get_phy_info_igp;
 122                 phy->ops.check_polarity     = e1000_check_polarity_igp;
 123                 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp;
 124                 phy->ops.get_cable_length   = e1000_get_cable_length_igp_2;
 125                 phy->ops.read_reg           = e1000_read_phy_reg_igp;
 126                 phy->ops.write_reg          = e1000_write_phy_reg_igp;
 127
 128                 /* This uses above function pointers */
 129                 ret_val = e1000_get_phy_id_82571(hw);
 130
 131                 /* Verify PHY ID */
 132                 if (phy->id != IGP01E1000_I_PHY_ID) {
 133                         ret_val = -E1000_ERR_PHY;
 134                         DEBUGOUT1("PHY ID unknown: type = 0x%08x\n", phy->id);
 135                         goto out;
 136                 }
 137                 break;
 138         case e1000_82573:
 139                 phy->type                   = e1000_phy_m88;
 140                 phy->ops.get_cfg_done       = e1000_get_cfg_done_generic;
 141                 phy->ops.get_info           = e1000_get_phy_info_m88;
 142                 phy->ops.check_polarity     = e1000_check_polarity_m88;
 143                 phy->ops.commit             = e1000_phy_sw_reset_generic;
 144                 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
 145                 phy->ops.get_cable_length   = e1000_get_cable_length_m88;
 146                 phy->ops.read_reg           = e1000_read_phy_reg_m88;
 147                 phy->ops.write_reg          = e1000_write_phy_reg_m88;
 148
 149                 /* This uses above function pointers */
 150                 ret_val = e1000_get_phy_id_82571(hw);
 151
 152                 /* Verify PHY ID */
 153                 if (phy->id != M88E1111_I_PHY_ID) {
 154                         ret_val = -E1000_ERR_PHY;
 155                         DEBUGOUT1("PHY ID unknown: type = 0x%08x\n", phy->id);
 156                         goto out;
 157                 }
 158                 break;
 159         case e1000_82574:
 160         case e1000_82583:
 161                 phy->type                   = e1000_phy_bm;
 162                 phy->ops.get_cfg_done       = e1000_get_cfg_done_generic;
 163                 phy->ops.get_info           = e1000_get_phy_info_m88;
 164                 phy->ops.check_polarity     = e1000_check_polarity_m88;
 165                 phy->ops.commit             = e1000_phy_sw_reset_generic;
 166                 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
 167                 phy->ops.get_cable_length   = e1000_get_cable_length_m88;
 168                 phy->ops.read_reg           = e1000_read_phy_reg_bm2;
 169                 phy->ops.write_reg          = e1000_write_phy_reg_bm2;
 170
 171                 /* This uses above function pointers */
 172                 ret_val = e1000_get_phy_id_82571(hw);
 173                 /* Verify PHY ID */
 174                 if (phy->id != BME1000_E_PHY_ID_R2) {
 175                         ret_val = -E1000_ERR_PHY;
 176                         DEBUGOUT1("PHY ID unknown: type = 0x%08x\n", phy->id);
 177                         goto out;
 178                 }
 179                 break;
 180         default:
 181                 ret_val = -E1000_ERR_PHY;
 182                 goto out;
 183                 break;
 184         }
 185
 186 out:
 187         return ret_val;
 188 }
 189
 190 /**
 191  *  e1000_init_nvm_params_82571 - Init NVM func ptrs.
 192  *  @hw: pointer to the HW structure
 193  **/
 194 static s32 e1000_init_nvm_params_82571(struct e1000_hw *hw)
 195 {
 196         struct e1000_nvm_info *nvm = &hw->nvm;
 197         u32 eecd = E1000_READ_REG(hw, E1000_EECD);
 198         u16 size;
 199
 200         DEBUGFUNC("e1000_init_nvm_params_82571");
 201
 202         nvm->opcode_bits = 8;
 203         nvm->delay_usec = 1;
 204         switch (nvm->override) {
 205         case e1000_nvm_override_spi_large:
 206                 nvm->page_size = 32;
 207                 nvm->address_bits = 16;
 208                 break;
 209         case e1000_nvm_override_spi_small:
 210                 nvm->page_size = 8;
 211                 nvm->address_bits = 8;
 212                 break;
 213         default:
 214                 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
 215                 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8;
 216                 break;
 217         }
 218
 219         switch (hw->mac.type) {
 220         case e1000_82573:
 221         case e1000_82574:
 222         case e1000_82583:
 223                 if (((eecd >> 15) & 0x3) == 0x3) {
 224                         nvm->type = e1000_nvm_flash_hw;
 225                         nvm->word_size = 2048;
 226                         /*
 227                          * Autonomous Flash update bit must be cleared due
 228                          * to Flash update issue.
 229                          */
 230                         eecd &= ~E1000_EECD_AUPDEN;
 231                         E1000_WRITE_REG(hw, E1000_EECD, eecd);
 232                         break;
 233                 }
 234                 /* Fall Through */
 235         default:
 236                 nvm->type = e1000_nvm_eeprom_spi;
 237                 size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
 238                                   E1000_EECD_SIZE_EX_SHIFT);
 239                 /*
 240                  * Added to a constant, "size" becomes the left-shift value
 241                  * for setting word_size.
 242                  */
 243                 size += NVM_WORD_SIZE_BASE_SHIFT;
 244
 245                 /* EEPROM access above 16k is unsupported */
 246                 if (size > 14)
 247                         size = 14;
 248                 nvm->word_size  = 1 << size;
 249                 break;
 250         }
 251
 252         /* Function Pointers */
 253         nvm->ops.acquire       = e1000_acquire_nvm_82571;
 254         nvm->ops.read          = e1000_read_nvm_eerd;
 255         nvm->ops.release       = e1000_release_nvm_82571;
 256         nvm->ops.update        = e1000_update_nvm_checksum_82571;
 257         nvm->ops.validate      = e1000_validate_nvm_checksum_82571;
 258         nvm->ops.valid_led_default = e1000_valid_led_default_82571;
 259         nvm->ops.write         = e1000_write_nvm_82571;
 260
 261         return E1000_SUCCESS;
 262 }
 263
 264 /**
 265  *  e1000_init_mac_params_82571 - Init MAC func ptrs.
 266  *  @hw: pointer to the HW structure
 267  **/
 268 static s32 e1000_init_mac_params_82571(struct e1000_hw *hw)
 269 {
 270         struct e1000_mac_info *mac = &hw->mac;
 271         u32 swsm = 0;
 272         u32 swsm2 = 0;
 273         bool force_clear_smbi = FALSE;
 274
 275         DEBUGFUNC("e1000_init_mac_params_82571");
 276
 277         /* Set media type and media-dependent function pointers */
 278         switch (hw->device_id) {
 279         case E1000_DEV_ID_82571EB_FIBER:
 280         case E1000_DEV_ID_82572EI_FIBER:
 281         case E1000_DEV_ID_82571EB_QUAD_FIBER:
 282                 hw->phy.media_type = e1000_media_type_fiber;
 283                 mac->ops.setup_physical_interface =
 284                         e1000_setup_fiber_serdes_link_82571;
 285                 mac->ops.check_for_link = e1000_check_for_fiber_link_generic;
 286                 mac->ops.get_link_up_info =
 287                         e1000_get_speed_and_duplex_fiber_serdes_generic;
 288                 break;
 289         case E1000_DEV_ID_82571EB_SERDES:
 290         case E1000_DEV_ID_82571EB_SERDES_DUAL:
 291         case E1000_DEV_ID_82571EB_SERDES_QUAD:
 292         case E1000_DEV_ID_82572EI_SERDES:
 293                 hw->phy.media_type = e1000_media_type_internal_serdes;
 294                 mac->ops.setup_physical_interface =
 295                         e1000_setup_fiber_serdes_link_82571;
 296                 mac->ops.check_for_link = e1000_check_for_serdes_link_82571;
 297                 mac->ops.get_link_up_info =
 298                         e1000_get_speed_and_duplex_fiber_serdes_generic;
 299                 break;
 300         default:
 301                 hw->phy.media_type = e1000_media_type_copper;
 302                 mac->ops.setup_physical_interface =
 303                         e1000_setup_copper_link_82571;
 304                 mac->ops.check_for_link = e1000_check_for_copper_link_generic;
 305                 mac->ops.get_link_up_info =
 306                         e1000_get_speed_and_duplex_copper_generic;
 307                 break;
 308         }
 309
 310         /* Set mta register count */
 311         mac->mta_reg_count = 128;
 312         /* Set rar entry count */
 313         mac->rar_entry_count = E1000_RAR_ENTRIES;
 314         /* Set if part includes ASF firmware */
 315         mac->asf_firmware_present = TRUE;
 316         /* Adaptive IFS supported */
 317         mac->adaptive_ifs = TRUE;
 318
 319         /* Function pointers */
 320
 321         /* bus type/speed/width */
 322         mac->ops.get_bus_info = e1000_get_bus_info_pcie_generic;
 323         /* reset */
 324         mac->ops.reset_hw = e1000_reset_hw_82571;
 325         /* hw initialization */
 326         mac->ops.init_hw = e1000_init_hw_82571;
 327         /* link setup */
 328         mac->ops.setup_link = e1000_setup_link_82571;
 329         /* multicast address update */
 330         mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;
 331         /* writing VFTA */
 332         mac->ops.write_vfta = e1000_write_vfta_generic;
 333         /* clearing VFTA */
 334         mac->ops.clear_vfta = e1000_clear_vfta_82571;
 335         /* read mac address */
 336         mac->ops.read_mac_addr = e1000_read_mac_addr_82571;
 337         /* ID LED init */
 338         mac->ops.id_led_init = e1000_id_led_init_generic;
 339         /* blink LED */
 340         mac->ops.blink_led = e1000_blink_led_generic;
 341         /* setup LED */
 342         mac->ops.setup_led = e1000_setup_led_generic;
 343         /* cleanup LED */
 344         mac->ops.cleanup_led = e1000_cleanup_led_generic;
 345         /* turn off LED */
 346         mac->ops.led_off = e1000_led_off_generic;
 347         /* clear hardware counters */
 348         mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82571;
 349
 350         /* MAC-specific function pointers */
 351         switch (hw->mac.type) {
 352         case e1000_82573:
 353                 mac->ops.set_lan_id = e1000_set_lan_id_single_port;
 354                 mac->ops.check_mng_mode = e1000_check_mng_mode_generic;
 355                 mac->ops.led_on = e1000_led_on_generic;
 356
 357                 /* FWSM register */
 358                 mac->has_fwsm = TRUE;
 359                 /*
 360                  * ARC supported; valid only if manageability features are
 361                  * enabled.
 362                  */
 363                 mac->arc_subsystem_valid =
 364                         (E1000_READ_REG(hw, E1000_FWSM) & E1000_FWSM_MODE_MASK)
 365                         ? TRUE : FALSE;
 366                 break;
 367         case e1000_82574:
 368         case e1000_82583:
 369                 mac->ops.set_lan_id = e1000_set_lan_id_single_port;
 370                 mac->ops.check_mng_mode = e1000_check_mng_mode_82574;
 371                 mac->ops.led_on = e1000_led_on_82574;
 372                 break;
 373         default:
 374                 mac->ops.check_mng_mode = e1000_check_mng_mode_generic;
 375                 mac->ops.led_on = e1000_led_on_generic;
 376
 377                 /* FWSM register */
 378                 mac->has_fwsm = TRUE;
 379                 break;
 380         }
 381
 382         /*
 383          * Ensure that the inter-port SWSM.SMBI lock bit is clear before
 384          * first NVM or PHY acess. This should be done for single-port
 385          * devices, and for one port only on dual-port devices so that
 386          * for those devices we can still use the SMBI lock to synchronize
 387          * inter-port accesses to the PHY & NVM.
 388          */
 389         switch (hw->mac.type) {
 390         case e1000_82571:
 391         case e1000_82572:
 392                 swsm2 = E1000_READ_REG(hw, E1000_SWSM2);
 393
 394                 if (!(swsm2 & E1000_SWSM2_LOCK)) {
 395                         /* Only do this for the first interface on this card */
 396                         E1000_WRITE_REG(hw, E1000_SWSM2,
 397                             swsm2 | E1000_SWSM2_LOCK);
 398                         force_clear_smbi = TRUE;
 399                 } else
 400                         force_clear_smbi = FALSE;
 401                 break;
 402         default:
 403                 force_clear_smbi = TRUE;
 404                 break;
 405         }
 406
 407         if (force_clear_smbi) {
 408                 /* Make sure SWSM.SMBI is clear */
 409                 swsm = E1000_READ_REG(hw, E1000_SWSM);
 410                 if (swsm & E1000_SWSM_SMBI) {
 411                         /* This bit should not be set on a first interface, and
 412                          * indicates that the bootagent or EFI code has
 413                          * improperly left this bit enabled
 414                          */
 415                         DEBUGOUT("Please update your 82571 Bootagent\n");
 416                 }
 417                 E1000_WRITE_REG(hw, E1000_SWSM, swsm & ~E1000_SWSM_SMBI);
 418         }
 419
 420         /*
 421          * Initialze device specific counter of SMBI acquisition
 422          * timeouts.
 423          */
 424          hw->dev_spec._82571.smb_counter = 0;
 425
 426         return E1000_SUCCESS;
 427 }
 428
 429 /**
 430  *  e1000_init_function_pointers_82571 - Init func ptrs.
 431  *  @hw: pointer to the HW structure
 432  *
 433  *  Called to initialize all function pointers and parameters.
 434  **/
 435 void e1000_init_function_pointers_82571(struct e1000_hw *hw)
 436 {
 437         DEBUGFUNC("e1000_init_function_pointers_82571");
 438
 439         hw->mac.ops.init_params = e1000_init_mac_params_82571;
 440         hw->nvm.ops.init_params = e1000_init_nvm_params_82571;
 441         hw->phy.ops.init_params = e1000_init_phy_params_82571;
 442 }
 443
 444 /**
 445  *  e1000_get_phy_id_82571 - Retrieve the PHY ID and revision
 446  *  @hw: pointer to the HW structure
 447  *
 448  *  Reads the PHY registers and stores the PHY ID and possibly the PHY
 449  *  revision in the hardware structure.
 450  **/
 451 static s32 e1000_get_phy_id_82571(struct e1000_hw *hw)
 452 {
 453         struct e1000_phy_info *phy = &hw->phy;
 454         s32 ret_val = E1000_SUCCESS;
 455         u16 phy_id = 0;
 456
 457         DEBUGFUNC("e1000_get_phy_id_82571");
 458
 459         switch (hw->mac.type) {
 460         case e1000_82571:
 461         case e1000_82572:
 462                 /*
 463                  * The 82571 firmware may still be configuring the PHY.
 464                  * In this case, we cannot access the PHY until the
 465                  * configuration is done.  So we explicitly set the
 466                  * PHY ID.
 467                  */
 468                 phy->id = IGP01E1000_I_PHY_ID;
 469                 break;
 470         case e1000_82573:
 471                 ret_val = e1000_get_phy_id(hw);
 472                 break;
 473         case e1000_82574:
 474         case e1000_82583:
 475                 ret_val = phy->ops.read_reg(hw, PHY_ID1, &phy_id);
 476                 if (ret_val)
 477                         goto out;
 478
 479                 phy->id = (u32)(phy_id << 16);
 480                 usec_delay(20);
 481                 ret_val = phy->ops.read_reg(hw, PHY_ID2, &phy_id);
 482                 if (ret_val)
 483                         goto out;
 484
 485                 phy->id |= (u32)(phy_id);
 486                 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK);
 487                 break;
 488         default:
 489                 ret_val = -E1000_ERR_PHY;
 490                 break;
 491         }
 492 out:
 493         return ret_val;
 494 }
 495
 496 /**
 497  *  e1000_get_hw_semaphore_82571 - Acquire hardware semaphore
 498  *  @hw: pointer to the HW structure
 499  *
 500  *  Acquire the HW semaphore to access the PHY or NVM
 501  **/
 502 static s32 e1000_get_hw_semaphore_82571(struct e1000_hw *hw)
 503 {
 504         u32 swsm;
 505         s32 ret_val = E1000_SUCCESS;
 506         s32 sw_timeout = hw->nvm.word_size + 1;
 507         s32 fw_timeout = hw->nvm.word_size + 1;
 508         s32 i = 0;
 509
 510         DEBUGFUNC("e1000_get_hw_semaphore_82571");
 511
 512         /*
 513          * If we have timedout 3 times on trying to acquire
 514          * the inter-port SMBI semaphore, there is old code
 515          * operating on the other port, and it is not
 516          * releasing SMBI. Modify the number of times that
 517          * we try for the semaphore to interwork with this
 518          * older code.
 519          */
 520         if (hw->dev_spec._82571.smb_counter > 2)
 521                 sw_timeout = 1;
 522
 523         /* Get the SW semaphore */
 524         while (i < sw_timeout) {
 525                 swsm = E1000_READ_REG(hw, E1000_SWSM);
 526                 if (!(swsm & E1000_SWSM_SMBI))
 527                         break;
 528
 529                 usec_delay(50);
 530                 i++;
 531         }
 532
 533         if (i == sw_timeout) {
 534                 DEBUGOUT("Driver can't access device - SMBI bit is set.\n");
 535                 hw->dev_spec._82571.smb_counter++;
 536         }
 537         /* Get the FW semaphore. */
 538         for (i = 0; i < fw_timeout; i++) {
 539                 swsm = E1000_READ_REG(hw, E1000_SWSM);
 540                 E1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_SWESMBI);
 541
 542                 /* Semaphore acquired if bit latched */
 543                 if (E1000_READ_REG(hw, E1000_SWSM) & E1000_SWSM_SWESMBI)
 544                         break;
 545
 546                 usec_delay(50);
 547         }
 548
 549         if (i == fw_timeout) {
 550                 /* Release semaphores */
 551                 e1000_put_hw_semaphore_82571(hw);
 552                 DEBUGOUT("Driver can't access the NVM\n");
 553                 ret_val = -E1000_ERR_NVM;
 554                 goto out;
 555         }
 556
 557 out:
 558         return ret_val;
 559 }
 560
 561 /**
 562  *  e1000_put_hw_semaphore_82571 - Release hardware semaphore
 563  *  @hw: pointer to the HW structure
 564  *
 565  *  Release hardware semaphore used to access the PHY or NVM
 566  **/
 567 static void e1000_put_hw_semaphore_82571(struct e1000_hw *hw)
 568 {
 569         u32 swsm;
 570
 571         DEBUGFUNC("e1000_put_hw_semaphore_generic");
 572
 573         swsm = E1000_READ_REG(hw, E1000_SWSM);
 574
 575         swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI);
 576
 577         E1000_WRITE_REG(hw, E1000_SWSM, swsm);
 578 }
 579
 580 /**
 581  *  e1000_acquire_nvm_82571 - Request for access to the EEPROM
 582  *  @hw: pointer to the HW structure
 583  *
 584  *  To gain access to the EEPROM, first we must obtain a hardware semaphore.
 585  *  Then for non-82573 hardware, set the EEPROM access request bit and wait
 586  *  for EEPROM access grant bit.  If the access grant bit is not set, release
 587  *  hardware semaphore.
 588  **/
 589 static s32 e1000_acquire_nvm_82571(struct e1000_hw *hw)
 590 {
 591         s32 ret_val;
 592
 593         DEBUGFUNC("e1000_acquire_nvm_82571");
 594
 595         ret_val = e1000_get_hw_semaphore_82571(hw);
 596         if (ret_val)
 597                 goto out;
 598
 599         switch (hw->mac.type) {
 600         case e1000_82573:
 601         case e1000_82574:
 602         case e1000_82583:
 603                 break;
 604         default:
 605                 ret_val = e1000_acquire_nvm_generic(hw);
 606                 break;
 607         }
 608
 609         if (ret_val)
 610                 e1000_put_hw_semaphore_82571(hw);
 611
 612 out:
 613         return ret_val;
 614 }
 615
 616 /**
 617  *  e1000_release_nvm_82571 - Release exclusive access to EEPROM
 618  *  @hw: pointer to the HW structure
 619  *
 620  *  Stop any current commands to the EEPROM and clear the EEPROM request bit.
 621  **/
 622 static void e1000_release_nvm_82571(struct e1000_hw *hw)
 623 {
 624         DEBUGFUNC("e1000_release_nvm_82571");
 625
 626         e1000_release_nvm_generic(hw);
 627         e1000_put_hw_semaphore_82571(hw);
 628 }
 629
 630 /**
 631  *  e1000_write_nvm_82571 - Write to EEPROM using appropriate interface
 632  *  @hw: pointer to the HW structure
 633  *  @offset: offset within the EEPROM to be written to
 634  *  @words: number of words to write
 635  *  @data: 16 bit word(s) to be written to the EEPROM
 636  *
 637  *  For non-82573 silicon, write data to EEPROM at offset using SPI interface.
 638  *
 639  *  If e1000_update_nvm_checksum is not called after this function, the
 640  *  EEPROM will most likely contain an invalid checksum.
 641  **/
 642 static s32 e1000_write_nvm_82571(struct e1000_hw *hw, u16 offset, u16 words,
 643                                  u16 *data)
 644 {
 645         s32 ret_val = E1000_SUCCESS;
 646
 647         DEBUGFUNC("e1000_write_nvm_82571");
 648
 649         switch (hw->mac.type) {
 650         case e1000_82573:
 651         case e1000_82574:
 652         case e1000_82583:
 653                 ret_val = e1000_write_nvm_eewr_82571(hw, offset, words, data);
 654                 break;
 655         case e1000_82571:
 656         case e1000_82572:
 657                 ret_val = e1000_write_nvm_spi(hw, offset, words, data);
 658                 break;
 659         default:
 660                 ret_val = -E1000_ERR_NVM;
 661                 break;
 662         }
 663
 664         return ret_val;
 665 }
 666
 667 /**
 668  *  e1000_update_nvm_checksum_82571 - Update EEPROM checksum
 669  *  @hw: pointer to the HW structure
 670  *
 671  *  Updates the EEPROM checksum by reading/adding each word of the EEPROM
 672  *  up to the checksum.  Then calculates the EEPROM checksum and writes the
 673  *  value to the EEPROM.
 674  **/
 675 static s32 e1000_update_nvm_checksum_82571(struct e1000_hw *hw)
 676 {
 677         u32 eecd;
 678         s32 ret_val;
 679         u16 i;
 680
 681         DEBUGFUNC("e1000_update_nvm_checksum_82571");
 682
 683         ret_val = e1000_update_nvm_checksum_generic(hw);
 684         if (ret_val)
 685                 goto out;
 686
 687         /*
 688          * If our nvm is an EEPROM, then we're done
 689          * otherwise, commit the checksum to the flash NVM.
 690          */
 691         if (hw->nvm.type != e1000_nvm_flash_hw)
 692                 goto out;
 693
 694         /* Check for pending operations. */
 695         for (i = 0; i < E1000_FLASH_UPDATES; i++) {
 696                 msec_delay(1);
 697                 if ((E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_FLUPD) == 0)
 698                         break;
 699         }
 700
 701         if (i == E1000_FLASH_UPDATES) {
 702                 ret_val = -E1000_ERR_NVM;
 703                 goto out;
 704         }
 705
 706         /* Reset the firmware if using STM opcode. */
 707         if ((E1000_READ_REG(hw, E1000_FLOP) & 0xFF00) == E1000_STM_OPCODE) {
 708                 /*
 709                  * The enabling of and the actual reset must be done
 710                  * in two write cycles.
 711                  */
 712                 E1000_WRITE_REG(hw, E1000_HICR, E1000_HICR_FW_RESET_ENABLE);
 713                 E1000_WRITE_FLUSH(hw);
 714                 E1000_WRITE_REG(hw, E1000_HICR, E1000_HICR_FW_RESET);
 715         }
 716
 717         /* Commit the write to flash */
 718         eecd = E1000_READ_REG(hw, E1000_EECD) | E1000_EECD_FLUPD;
 719         E1000_WRITE_REG(hw, E1000_EECD, eecd);
 720
 721         for (i = 0; i < E1000_FLASH_UPDATES; i++) {
 722                 msec_delay(1);
 723                 if ((E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_FLUPD) == 0)
 724                         break;
 725         }
 726
 727         if (i == E1000_FLASH_UPDATES) {
 728                 ret_val = -E1000_ERR_NVM;
 729                 goto out;
 730         }
 731
 732 out:
 733         return ret_val;
 734 }
 735
 736 /**
 737  *  e1000_validate_nvm_checksum_82571 - Validate EEPROM checksum
 738  *  @hw: pointer to the HW structure
 739  *
 740  *  Calculates the EEPROM checksum by reading/adding each word of the EEPROM
 741  *  and then verifies that the sum of the EEPROM is equal to 0xBABA.
 742  **/
 743 static s32 e1000_validate_nvm_checksum_82571(struct e1000_hw *hw)
 744 {
 745         DEBUGFUNC("e1000_validate_nvm_checksum_82571");
 746
 747         if (hw->nvm.type == e1000_nvm_flash_hw)
 748                 e1000_fix_nvm_checksum_82571(hw);
 749
 750         return e1000_validate_nvm_checksum_generic(hw);
 751 }
 752
 753 /**
 754  *  e1000_write_nvm_eewr_82571 - Write to EEPROM for 82573 silicon
 755  *  @hw: pointer to the HW structure
 756  *  @offset: offset within the EEPROM to be written to
 757  *  @words: number of words to write
 758  *  @data: 16 bit word(s) to be written to the EEPROM
 759  *
 760  *  After checking for invalid values, poll the EEPROM to ensure the previous
 761  *  command has completed before trying to write the next word.  After write
 762  *  poll for completion.
 763  *
 764  *  If e1000_update_nvm_checksum is not called after this function, the
 765  *  EEPROM will most likely contain an invalid checksum.
 766  **/
 767 static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset,
 768                                       u16 words, u16 *data)
 769 {
 770         struct e1000_nvm_info *nvm = &hw->nvm;
 771         u32 i, eewr = 0;
 772         s32 ret_val = 0;
 773
 774         DEBUGFUNC("e1000_write_nvm_eewr_82571");
 775
 776         /*
 777          * A check for invalid values:  offset too large, too many words,
 778          * and not enough words.
 779          */
 780         if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
 781             (words == 0)) {
 782                 DEBUGOUT("nvm parameter(s) out of bounds\n");
 783                 ret_val = -E1000_ERR_NVM;
 784                 goto out;
 785         }
 786
 787         for (i = 0; i < words; i++) {
 788                 eewr = (data[i] << E1000_NVM_RW_REG_DATA) |
 789                        ((offset+i) << E1000_NVM_RW_ADDR_SHIFT) |
 790                        E1000_NVM_RW_REG_START;
 791
 792                 ret_val = e1000_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE);
 793                 if (ret_val)
 794                         break;
 795
 796                 E1000_WRITE_REG(hw, E1000_EEWR, eewr);
 797
 798                 ret_val = e1000_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE);
 799                 if (ret_val)
 800                         break;
 801         }
 802
 803 out:
 804         return ret_val;
 805 }
 806
 807 /**
 808  *  e1000_get_cfg_done_82571 - Poll for configuration done
 809  *  @hw: pointer to the HW structure
 810  *
 811  *  Reads the management control register for the config done bit to be set.
 812  **/
 813 static s32 e1000_get_cfg_done_82571(struct e1000_hw *hw)
 814 {
 815         s32 timeout = PHY_CFG_TIMEOUT;
 816         s32 ret_val = E1000_SUCCESS;
 817
 818         DEBUGFUNC("e1000_get_cfg_done_82571");
 819
 820         while (timeout) {
 821                 if (E1000_READ_REG(hw, E1000_EEMNGCTL) &
 822                     E1000_NVM_CFG_DONE_PORT_0)
 823                         break;
 824                 msec_delay(1);
 825                 timeout--;
 826         }
 827         if (!timeout) {
 828                 DEBUGOUT("MNG configuration cycle has not completed.\n");
 829                 ret_val = -E1000_ERR_RESET;
 830                 goto out;
 831         }
 832
 833 out:
 834         return ret_val;
 835 }
 836
 837 /**
 838  *  e1000_set_d0_lplu_state_82571 - Set Low Power Linkup D0 state
 839  *  @hw: pointer to the HW structure
 840  *  @active: TRUE to enable LPLU, FALSE to disable
 841  *
 842  *  Sets the LPLU D0 state according to the active flag.  When activating LPLU
 843  *  this function also disables smart speed and vice versa.  LPLU will not be
 844  *  activated unless the device autonegotiation advertisement meets standards
 845  *  of either 10 or 10/100 or 10/100/1000 at all duplexes.  This is a function
 846  *  pointer entry point only called by PHY setup routines.
 847  **/
 848 static s32 e1000_set_d0_lplu_state_82571(struct e1000_hw *hw, bool active)
 849 {
 850         struct e1000_phy_info *phy = &hw->phy;
 851         s32 ret_val = E1000_SUCCESS;
 852         u16 data;
 853
 854         DEBUGFUNC("e1000_set_d0_lplu_state_82571");
 855
 856         if (!(phy->ops.read_reg))
 857                 goto out;
 858
 859         ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);
 860         if (ret_val)
 861                 goto out;
 862
 863         if (active) {
 864                 data |= IGP02E1000_PM_D0_LPLU;
 865                 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
 866                                              data);
 867                 if (ret_val)
 868                         goto out;
 869
 870                 /* When LPLU is enabled, we should disable SmartSpeed */
 871                 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
 872                                             &data);
 873                 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
 874                 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
 875                                              data);
 876                 if (ret_val)
 877                         goto out;
 878         } else {
 879                 data &= ~IGP02E1000_PM_D0_LPLU;
 880                 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
 881                                              data);
 882                 /*
 883                  * LPLU and SmartSpeed are mutually exclusive.  LPLU is used
 884                  * during Dx states where the power conservation is most
 885                  * important.  During driver activity we should enable
 886                  * SmartSpeed, so performance is maintained.
 887                  */
 888                 if (phy->smart_speed == e1000_smart_speed_on) {
 889                         ret_val = phy->ops.read_reg(hw,
 890                                                     IGP01E1000_PHY_PORT_CONFIG,
 891                                                     &data);
 892                         if (ret_val)
 893                                 goto out;
 894
 895                         data |= IGP01E1000_PSCFR_SMART_SPEED;
 896                         ret_val = phy->ops.write_reg(hw,
 897                                                      IGP01E1000_PHY_PORT_CONFIG,
 898                                                      data);
 899                         if (ret_val)
 900                                 goto out;
 901                 } else if (phy->smart_speed == e1000_smart_speed_off) {
 902                         ret_val = phy->ops.read_reg(hw,
 903                                                     IGP01E1000_PHY_PORT_CONFIG,
 904                                                     &data);
 905                         if (ret_val)
 906                                 goto out;
 907
 908                         data &= ~IGP01E1000_PSCFR_SMART_SPEED;
 909                         ret_val = phy->ops.write_reg(hw,
 910                                                      IGP01E1000_PHY_PORT_CONFIG,
 911                                                      data);
 912                         if (ret_val)
 913                                 goto out;
 914                 }
 915         }
 916
 917 out:
 918         return ret_val;
 919 }
 920
 921 /**
 922  *  e1000_reset_hw_82571 - Reset hardware
 923  *  @hw: pointer to the HW structure
 924  *
 925  *  This resets the hardware into a known state.
 926  **/
 927 static s32 e1000_reset_hw_82571(struct e1000_hw *hw)
 928 {
 929         u32 ctrl, extcnf_ctrl, ctrl_ext, icr;
 930         s32 ret_val;
 931         u16 i = 0;
 932
 933         DEBUGFUNC("e1000_reset_hw_82571");
 934
 935         /*
 936          * Prevent the PCI-E bus from sticking if there is no TLP connection
 937          * on the last TLP read/write transaction when MAC is reset.
 938          */
 939         ret_val = e1000_disable_pcie_master_generic(hw);
 940         if (ret_val)
 941                 DEBUGOUT("PCI-E Master disable polling has failed.\n");
 942
 943         DEBUGOUT("Masking off all interrupts\n");
 944         E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
 945
 946         E1000_WRITE_REG(hw, E1000_RCTL, 0);
 947         E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
 948         E1000_WRITE_FLUSH(hw);
 949
 950         msec_delay(10);
 951
 952         /*
 953          * Must acquire the MDIO ownership before MAC reset.
 954          * Ownership defaults to firmware after a reset.
 955          */
 956         switch (hw->mac.type) {
 957         case e1000_82573:
 958         case e1000_82574:
 959         case e1000_82583:
 960                 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
 961                 extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
 962
 963                 do {
 964                         E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
 965                         extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
 966
 967                         if (extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP)
 968                                 break;
 969
 970                         extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
 971
 972                         msec_delay(2);
 973                         i++;
 974                 } while (i < MDIO_OWNERSHIP_TIMEOUT);
 975                 break;
 976         default:
 977                 break;
 978         }
 979
 980         ctrl = E1000_READ_REG(hw, E1000_CTRL);
 981
 982         DEBUGOUT("Issuing a global reset to MAC\n");
 983         E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);
 984
 985         if (hw->nvm.type == e1000_nvm_flash_hw) {
 986                 usec_delay(10);
 987                 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 988                 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
 989                 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 990                 E1000_WRITE_FLUSH(hw);
 991         }
 992
 993         ret_val = e1000_get_auto_rd_done_generic(hw);
 994         if (ret_val)
 995                 /* We don't want to continue accessing MAC registers. */
 996                 goto out;
 997
 998         /*
 999          * Phy configuration from NVM just starts after EECD_AUTO_RD is set.
1000          * Need to wait for Phy configuration completion before accessing
1001          * NVM and Phy.
1002          */
1003
1004         switch (hw->mac.type) {
1005         case e1000_82573:
1006         case e1000_82574:
1007         case e1000_82583:
1008                 msec_delay(25);
1009                 break;
1010         default:
1011                 break;
1012         }
1013
1014         /* Clear any pending interrupt events. */
1015         E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
1016         icr = E1000_READ_REG(hw, E1000_ICR);
1017
1018         /* Install any alternate MAC address into RAR0 */
1019         ret_val = e1000_check_alt_mac_addr_generic(hw);
1020         if (ret_val)
1021                 goto out;
1022
1023         e1000_set_laa_state_82571(hw, TRUE);
1024
1025         /* Reinitialize the 82571 serdes link state machine */
1026         if (hw->phy.media_type == e1000_media_type_internal_serdes)
1027                 hw->mac.serdes_link_state = e1000_serdes_link_down;
1028
1029 out:
1030         return ret_val;
1031 }
1032
1033 /**
1034  *  e1000_init_hw_82571 - Initialize hardware
1035  *  @hw: pointer to the HW structure
1036  *
1037  *  This inits the hardware readying it for operation.
1038  **/
1039 static s32 e1000_init_hw_82571(struct e1000_hw *hw)
1040 {
1041         struct e1000_mac_info *mac = &hw->mac;
1042         u32 reg_data;
1043         s32 ret_val;
1044         u16 i, rar_count = mac->rar_entry_count;
1045
1046         DEBUGFUNC("e1000_init_hw_82571");
1047
1048         e1000_initialize_hw_bits_82571(hw);
1049
1050         /* Initialize identification LED */
1051         ret_val = mac->ops.id_led_init(hw);
1052         if (ret_val)
1053                 DEBUGOUT("Error initializing identification LED\n");
1054                 /* This is not fatal and we should not stop init due to this */
1055
1056         /* Disabling VLAN filtering */
1057         DEBUGOUT("Initializing the IEEE VLAN\n");
1058         mac->ops.clear_vfta(hw);
1059
1060         /* Setup the receive address. */
1061         /*
1062          * If, however, a locally administered address was assigned to the
1063          * 82571, we must reserve a RAR for it to work around an issue where
1064          * resetting one port will reload the MAC on the other port.
1065          */
1066         if (e1000_get_laa_state_82571(hw))
1067                 rar_count--;
1068         e1000_init_rx_addrs_generic(hw, rar_count);
1069
1070         /* Zero out the Multicast HASH table */
1071         DEBUGOUT("Zeroing the MTA\n");
1072         for (i = 0; i < mac->mta_reg_count; i++)
1073                 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
1074
1075         /* Setup link and flow control */
1076         ret_val = mac->ops.setup_link(hw);
1077
1078         /* Set the transmit descriptor write-back policy */
1079         reg_data = E1000_READ_REG(hw, E1000_TXDCTL(0));
1080         reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) |
1081                    E1000_TXDCTL_FULL_TX_DESC_WB |
1082                    E1000_TXDCTL_COUNT_DESC;
1083         E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg_data);
1084
1085         /* ...for both queues. */
1086         switch (mac->type) {
1087         case e1000_82573:
1088                 e1000_enable_tx_pkt_filtering_generic(hw);
1089                 /* fall through */
1090         case e1000_82574:
1091         case e1000_82583:
1092                 reg_data = E1000_READ_REG(hw, E1000_GCR);
1093                 reg_data |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX;
1094                 E1000_WRITE_REG(hw, E1000_GCR, reg_data);
1095                 break;
1096         default:
1097                 reg_data = E1000_READ_REG(hw, E1000_TXDCTL(1));
1098                 reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) |
1099                            E1000_TXDCTL_FULL_TX_DESC_WB |
1100                            E1000_TXDCTL_COUNT_DESC;
1101                 E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg_data);
1102                 break;
1103         }
1104
1105         /*
1106          * Clear all of the statistics registers (clear on read).  It is
1107          * important that we do this after we have tried to establish link
1108          * because the symbol error count will increment wildly if there
1109          * is no link.
1110          */
1111         e1000_clear_hw_cntrs_82571(hw);
1112
1113         return ret_val;
1114 }
1115
1116 /**
1117  *  e1000_initialize_hw_bits_82571 - Initialize hardware-dependent bits
1118  *  @hw: pointer to the HW structure
1119  *
1120  *  Initializes required hardware-dependent bits needed for normal operation.
1121  **/
1122 static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw)
1123 {
1124         u32 reg;
1125
1126         DEBUGFUNC("e1000_initialize_hw_bits_82571");
1127
1128         /* Transmit Descriptor Control 0 */
1129         reg = E1000_READ_REG(hw, E1000_TXDCTL(0));
1130         reg |= (1 << 22);
1131         E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg);
1132
1133         /* Transmit Descriptor Control 1 */
1134         reg = E1000_READ_REG(hw, E1000_TXDCTL(1));
1135         reg |= (1 << 22);
1136         E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg);
1137
1138         /* Transmit Arbitration Control 0 */
1139         reg = E1000_READ_REG(hw, E1000_TARC(0));
1140         reg &= ~(0xF << 27); /* 30:27 */
1141         switch (hw->mac.type) {
1142         case e1000_82571:
1143         case e1000_82572:
1144                 reg |= (1 << 23) | (1 << 24) | (1 << 25) | (1 << 26);
1145                 break;
1146         default:
1147                 break;
1148         }
1149         E1000_WRITE_REG(hw, E1000_TARC(0), reg);
1150
1151         /* Transmit Arbitration Control 1 */
1152         reg = E1000_READ_REG(hw, E1000_TARC(1));
1153         switch (hw->mac.type) {
1154         case e1000_82571:
1155         case e1000_82572:
1156                 reg &= ~((1 << 29) | (1 << 30));
1157                 reg |= (1 << 22) | (1 << 24) | (1 << 25) | (1 << 26);
1158                 if (E1000_READ_REG(hw, E1000_TCTL) & E1000_TCTL_MULR)
1159                         reg &= ~(1 << 28);
1160                 else
1161                         reg |= (1 << 28);
1162                 E1000_WRITE_REG(hw, E1000_TARC(1), reg);
1163                 break;
1164         default:
1165                 break;
1166         }
1167
1168         /* Device Control */
1169         switch (hw->mac.type) {
1170         case e1000_82573:
1171         case e1000_82574:
1172         case e1000_82583:
1173                 reg = E1000_READ_REG(hw, E1000_CTRL);
1174                 reg &= ~(1 << 29);
1175                 E1000_WRITE_REG(hw, E1000_CTRL, reg);
1176                 break;
1177         default:
1178                 break;
1179         }
1180
1181         /* Extended Device Control */
1182         switch (hw->mac.type) {
1183         case e1000_82573:
1184         case e1000_82574:
1185         case e1000_82583:
1186                 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1187                 reg &= ~(1 << 23);
1188                 reg |= (1 << 22);
1189                 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1190                 break;
1191         default:
1192                 break;
1193         }
1194
1195         if (hw->mac.type == e1000_82571) {
1196                 reg = E1000_READ_REG(hw, E1000_PBA_ECC);
1197                 reg |= E1000_PBA_ECC_CORR_EN;
1198                 E1000_WRITE_REG(hw, E1000_PBA_ECC, reg);
1199         }
1200
1201         /*
1202          * Workaround for hardware errata.
1203          * Ensure that DMA Dynamic Clock gating is disabled on 82571 and 82572
1204          */
1205         if ((hw->mac.type == e1000_82571) ||
1206            (hw->mac.type == e1000_82572)) {
1207                 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1208                 reg &= ~E1000_CTRL_EXT_DMA_DYN_CLK_EN;
1209                 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1210         }
1211
1212         /* PCI-Ex Control Registers */
1213         switch (hw->mac.type) {
1214         case e1000_82574:
1215         case e1000_82583:
1216                 reg = E1000_READ_REG(hw, E1000_GCR);
1217                 reg |= (1 << 22);
1218                 E1000_WRITE_REG(hw, E1000_GCR, reg);
1219
1220                 /*
1221                  * Workaround for hardware errata.
1222                  * apply workaround for hardware errata documented in errata
1223                  * docs Fixes issue where some error prone or unreliable PCIe
1224                  * completions are occurring, particularly with ASPM enabled.
1225                  * Without fix, issue can cause tx timeouts.
1226                  */
1227                 reg = E1000_READ_REG(hw, E1000_GCR2);
1228                 reg |= 1;
1229                 E1000_WRITE_REG(hw, E1000_GCR2, reg);
1230                 break;
1231         default:
1232                 break;
1233         }
1234
1235         return;
1236 }
1237
1238 /**
1239  *  e1000_clear_vfta_82571 - Clear VLAN filter table
1240  *  @hw: pointer to the HW structure
1241  *
1242  *  Clears the register array which contains the VLAN filter table by
1243  *  setting all the values to 0.
1244  **/
1245 static void e1000_clear_vfta_82571(struct e1000_hw *hw)
1246 {
1247         u32 offset;
1248         u32 vfta_value = 0;
1249         u32 vfta_offset = 0;
1250         u32 vfta_bit_in_reg = 0;
1251
1252         DEBUGFUNC("e1000_clear_vfta_82571");
1253
1254         switch (hw->mac.type) {
1255         case e1000_82573:
1256         case e1000_82574:
1257         case e1000_82583:
1258                 if (hw->mng_cookie.vlan_id != 0) {
1259                         /*
1260                          * The VFTA is a 4096b bit-field, each identifying
1261                          * a single VLAN ID.  The following operations
1262                          * determine which 32b entry (i.e. offset) into the
1263                          * array we want to set the VLAN ID (i.e. bit) of
1264                          * the manageability unit.
1265                          */
1266                         vfta_offset = (hw->mng_cookie.vlan_id >>
1267                                 E1000_VFTA_ENTRY_SHIFT) & E1000_VFTA_ENTRY_MASK;
1268                         vfta_bit_in_reg = 1 << (hw->mng_cookie.vlan_id &
1269                                 E1000_VFTA_ENTRY_BIT_SHIFT_MASK);
1270                 }
1271                 break;
1272         default:
1273                 break;
1274         }
1275         for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
1276                 /*
1277                  * If the offset we want to clear is the same offset of the
1278                  * manageability VLAN ID, then clear all bits except that of
1279                  * the manageability unit.
1280                  */
1281                 vfta_value = (offset == vfta_offset) ? vfta_bit_in_reg : 0;
1282                 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, vfta_value);
1283                 E1000_WRITE_FLUSH(hw);
1284         }
1285 }
1286
1287 /**
1288  *  e1000_check_mng_mode_82574 - Check manageability is enabled
1289  *  @hw: pointer to the HW structure
1290  *
1291  *  Reads the NVM Initialization Control Word 2 and returns TRUE
1292  *  (>0) if any manageability is enabled, else FALSE (0).
1293  **/
1294 static bool e1000_check_mng_mode_82574(struct e1000_hw *hw)
1295 {
1296         u16 data;
1297
1298         DEBUGFUNC("e1000_check_mng_mode_82574");
1299
1300         hw->nvm.ops.read(hw, NVM_INIT_CONTROL2_REG, 1, &data);
1301         return (data & E1000_NVM_INIT_CTRL2_MNGM) != 0;
1302 }
1303
1304 /**
1305  *  e1000_led_on_82574 - Turn LED on
1306  *  @hw: pointer to the HW structure
1307  *
1308  *  Turn LED on.
1309  **/
1310 static s32 e1000_led_on_82574(struct e1000_hw *hw)
1311 {
1312         u32 ctrl;
1313         u32 i;
1314
1315         DEBUGFUNC("e1000_led_on_82574");
1316
1317         ctrl = hw->mac.ledctl_mode2;
1318         if (!(E1000_STATUS_LU & E1000_READ_REG(hw, E1000_STATUS))) {
1319                 /*
1320                  * If no link, then turn LED on by setting the invert bit
1321                  * for each LED that's "on" (0x0E) in ledctl_mode2.
1322                  */
1323                 for (i = 0; i < 4; i++)
1324                         if (((hw->mac.ledctl_mode2 >> (i * 8)) & 0xFF) ==
1325                             E1000_LEDCTL_MODE_LED_ON)
1326                                 ctrl |= (E1000_LEDCTL_LED0_IVRT << (i * 8));
1327         }
1328         E1000_WRITE_REG(hw, E1000_LEDCTL, ctrl);
1329
1330         return E1000_SUCCESS;
1331 }
1332
1333
1334 /**
1335  *  e1000_setup_link_82571 - Setup flow control and link settings
1336  *  @hw: pointer to the HW structure
1337  *
1338  *  Determines which flow control settings to use, then configures flow
1339  *  control.  Calls the appropriate media-specific link configuration
1340  *  function.  Assuming the adapter has a valid link partner, a valid link
1341  *  should be established.  Assumes the hardware has previously been reset
1342  *  and the transmitter and receiver are not enabled.
1343  **/
1344 static s32 e1000_setup_link_82571(struct e1000_hw *hw)
1345 {
1346         DEBUGFUNC("e1000_setup_link_82571");
1347
1348         /*
1349          * 82573 does not have a word in the NVM to determine
1350          * the default flow control setting, so we explicitly
1351          * set it to full.
1352          */
1353         switch (hw->mac.type) {
1354         case e1000_82573:
1355         case e1000_82574:
1356         case e1000_82583:
1357                 if (hw->fc.requested_mode == e1000_fc_default)
1358                         hw->fc.requested_mode = e1000_fc_full;
1359                 break;
1360         default:
1361                 break;
1362         }
1363         return e1000_setup_link_generic(hw);
1364 }
1365
1366 /**
1367  *  e1000_setup_copper_link_82571 - Configure copper link settings
1368  *  @hw: pointer to the HW structure
1369  *
1370  *  Configures the link for auto-neg or forced speed and duplex.  Then we check
1371  *  for link, once link is established calls to configure collision distance
1372  *  and flow control are called.
1373  **/
1374 static s32 e1000_setup_copper_link_82571(struct e1000_hw *hw)
1375 {
1376         u32 ctrl;
1377         s32 ret_val;
1378
1379         DEBUGFUNC("e1000_setup_copper_link_82571");
1380
1381         ctrl = E1000_READ_REG(hw, E1000_CTRL);
1382         ctrl |= E1000_CTRL_SLU;
1383         ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1384         E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1385
1386         switch (hw->phy.type) {
1387         case e1000_phy_m88:
1388         case e1000_phy_bm:
1389                 ret_val = e1000_copper_link_setup_m88(hw);
1390                 break;
1391         case e1000_phy_igp_2:
1392                 ret_val = e1000_copper_link_setup_igp(hw);
1393                 break;
1394         default:
1395                 ret_val = -E1000_ERR_PHY;
1396                 break;
1397         }
1398
1399         if (ret_val)
1400                 goto out;
1401
1402         ret_val = e1000_setup_copper_link_generic(hw);
1403
1404 out:
1405         return ret_val;
1406 }
1407
1408 /**
1409  *  e1000_setup_fiber_serdes_link_82571 - Setup link for fiber/serdes
1410  *  @hw: pointer to the HW structure
1411  *
1412  *  Configures collision distance and flow control for fiber and serdes links.
1413  *  Upon successful setup, poll for link.
1414  **/
1415 static s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw)
1416 {
1417         DEBUGFUNC("e1000_setup_fiber_serdes_link_82571");
1418
1419         switch (hw->mac.type) {
1420         case e1000_82571:
1421         case e1000_82572:
1422                 /*
1423                  * If SerDes loopback mode is entered, there is no form
1424                  * of reset to take the adapter out of that mode.  So we
1425                  * have to explicitly take the adapter out of loopback
1426                  * mode.  This prevents drivers from twiddling their thumbs
1427                  * if another tool failed to take it out of loopback mode.
1428                  */
1429                 E1000_WRITE_REG(hw, E1000_SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK);
1430                 break;
1431         default:
1432                 break;
1433         }
1434
1435         return e1000_setup_fiber_serdes_link_generic(hw);
1436 }
1437
1438 /**
1439  *  e1000_check_for_serdes_link_82571 - Check for link (Serdes)
1440  *  @hw: pointer to the HW structure
1441  *
1442  *  Reports the link state as up or down.
1443  *
1444  *  If autonegotiation is supported by the link partner, the link state is
1445  *  determined by the result of autonegotiation. This is the most likely case.
1446  *  If autonegotiation is not supported by the link partner, and the link
1447  *  has a valid signal, force the link up.
1448  *
1449  *  The link state is represented internally here by 4 states:
1450  *
1451  *  1) down
1452  *  2) autoneg_progress
1453  *  3) autoneg_complete (the link sucessfully autonegotiated)
1454  *  4) forced_up (the link has been forced up, it did not autonegotiate)
1455  *
1456  **/
1457 static s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw)
1458 {
1459         struct e1000_mac_info *mac = &hw->mac;
1460         u32 rxcw;
1461         u32 ctrl;
1462         u32 status;
1463         s32 ret_val = E1000_SUCCESS;
1464
1465         DEBUGFUNC("e1000_check_for_serdes_link_82571");
1466
1467         ctrl = E1000_READ_REG(hw, E1000_CTRL);
1468         status = E1000_READ_REG(hw, E1000_STATUS);
1469         rxcw = E1000_READ_REG(hw, E1000_RXCW);
1470
1471         if ((rxcw & E1000_RXCW_SYNCH) && !(rxcw & E1000_RXCW_IV)) {
1472
1473                 /* Receiver is synchronized with no invalid bits.  */
1474                 switch (mac->serdes_link_state) {
1475                 case e1000_serdes_link_autoneg_complete:
1476                         if (!(status & E1000_STATUS_LU)) {
1477                                 /*
1478                                  * We have lost link, retry autoneg before
1479                                  * reporting link failure
1480                                  */
1481                                 mac->serdes_link_state =
1482                                     e1000_serdes_link_autoneg_progress;
1483                                 mac->serdes_has_link = FALSE;
1484                                 DEBUGOUT("AN_UP     -> AN_PROG\n");
1485                         }
1486                 break;
1487
1488                 case e1000_serdes_link_forced_up:
1489                         /*
1490                          * If we are receiving /C/ ordered sets, re-enable
1491                          * auto-negotiation in the TXCW register and disable
1492                          * forced link in the Device Control register in an
1493                          * attempt to auto-negotiate with our link partner.
1494                          */
1495                         if (rxcw & E1000_RXCW_C) {
1496                                 /* Enable autoneg, and unforce link up */
1497                                 E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw);
1498                                 E1000_WRITE_REG(hw, E1000_CTRL,
1499                                     (ctrl & ~E1000_CTRL_SLU));
1500                                 mac->serdes_link_state =
1501                                     e1000_serdes_link_autoneg_progress;
1502                                 mac->serdes_has_link = FALSE;
1503                                 DEBUGOUT("FORCED_UP -> AN_PROG\n");
1504                         }
1505                         break;
1506
1507                 case e1000_serdes_link_autoneg_progress:
1508                         if (rxcw & E1000_RXCW_C) {
1509                                 /*
1510                                  * We received /C/ ordered sets, meaning the
1511                                  * link partner has autonegotiated, and we can
1512                                  * trust the Link Up (LU) status bit.
1513                                  */
1514                                 if (status & E1000_STATUS_LU) {
1515                                         mac->serdes_link_state =
1516                                             e1000_serdes_link_autoneg_complete;
1517                                         DEBUGOUT("AN_PROG   -> AN_UP\n");
1518                                         mac->serdes_has_link = TRUE;
1519                                 } else {
1520                                         /* Autoneg completed, but failed. */
1521                                         mac->serdes_link_state =
1522                                             e1000_serdes_link_down;
1523                                         DEBUGOUT("AN_PROG   -> DOWN\n");
1524                                 }
1525                         } else {
1526                                 /*
1527                                  * The link partner did not autoneg.
1528                                  * Force link up and full duplex, and change
1529                                  * state to forced.
1530                                  */
1531                                 E1000_WRITE_REG(hw, E1000_TXCW,
1532                                 (mac->txcw & ~E1000_TXCW_ANE));
1533                                 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
1534                                 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1535
1536                                 /* Configure Flow Control after link up. */
1537                                 ret_val =
1538                                     e1000_config_fc_after_link_up_generic(hw);
1539                                 if (ret_val) {
1540                                         DEBUGOUT("Error config flow control\n");
1541                                         break;
1542                                 }
1543                                 mac->serdes_link_state =
1544                                 e1000_serdes_link_forced_up;
1545                                 mac->serdes_has_link = TRUE;
1546                                 DEBUGOUT("AN_PROG   -> FORCED_UP\n");
1547                         }
1548                         break;
1549
1550                 case e1000_serdes_link_down:
1551                 default:
1552                         /*
1553                          * The link was down but the receiver has now gained
1554                          * valid sync, so lets see if we can bring the link
1555                          * up.
1556                          */
1557                         E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw);
1558                         E1000_WRITE_REG(hw, E1000_CTRL,
1559                             (ctrl & ~E1000_CTRL_SLU));
1560                         mac->serdes_link_state =
1561                             e1000_serdes_link_autoneg_progress;
1562                         DEBUGOUT("DOWN      -> AN_PROG\n");
1563                         break;
1564                 }
1565         } else {
1566                 if (!(rxcw & E1000_RXCW_SYNCH)) {
1567                         mac->serdes_has_link = FALSE;
1568                         mac->serdes_link_state = e1000_serdes_link_down;
1569                         DEBUGOUT("ANYSTATE  -> DOWN\n");
1570                 } else {
1571                         /*
1572                          * We have sync, and can tolerate one invalid (IV)
1573                          * codeword before declaring link down, so reread
1574                          * to look again.
1575                          */
1576                         usec_delay(10);
1577                         rxcw = E1000_READ_REG(hw, E1000_RXCW);
1578                         if (rxcw & E1000_RXCW_IV) {
1579                                 mac->serdes_link_state = e1000_serdes_link_down;
1580                                 mac->serdes_has_link = FALSE;
1581                                 DEBUGOUT("ANYSTATE  -> DOWN\n");
1582                         }
1583                 }
1584         }
1585
1586         return ret_val;
1587 }
1588
1589 /**
1590  *  e1000_valid_led_default_82571 - Verify a valid default LED config
1591  *  @hw: pointer to the HW structure
1592  *  @data: pointer to the NVM (EEPROM)
1593  *
1594  *  Read the EEPROM for the current default LED configuration.  If the
1595  *  LED configuration is not valid, set to a valid LED configuration.
1596  **/
1597 static s32 e1000_valid_led_default_82571(struct e1000_hw *hw, u16 *data)
1598 {
1599         s32 ret_val;
1600
1601         DEBUGFUNC("e1000_valid_led_default_82571");
1602
1603         ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data);
1604         if (ret_val) {
1605                 DEBUGOUT("NVM Read Error\n");
1606                 goto out;
1607         }
1608
1609         switch (hw->mac.type) {
1610         case e1000_82573:
1611         case e1000_82574:
1612         case e1000_82583:
1613                 if (*data == ID_LED_RESERVED_F746)
1614                         *data = ID_LED_DEFAULT_82573;
1615                 break;
1616         default:
1617                 if (*data == ID_LED_RESERVED_0000 ||
1618                     *data == ID_LED_RESERVED_FFFF)
1619                         *data = ID_LED_DEFAULT;
1620                 break;
1621         }
1622
1623 out:
1624         return ret_val;
1625 }
1626
1627 /**
1628  *  e1000_get_laa_state_82571 - Get locally administered address state
1629  *  @hw: pointer to the HW structure
1630  *
1631  *  Retrieve and return the current locally administered address state.
1632  **/
1633 bool e1000_get_laa_state_82571(struct e1000_hw *hw)
1634 {
1635         DEBUGFUNC("e1000_get_laa_state_82571");
1636
1637         if (hw->mac.type != e1000_82571)
1638                 return FALSE;
1639
1640         return hw->dev_spec._82571.laa_is_present;
1641 }
1642
1643 /**
1644  *  e1000_set_laa_state_82571 - Set locally administered address state
1645  *  @hw: pointer to the HW structure
1646  *  @state: enable/disable locally administered address
1647  *
1648  *  Enable/Disable the current locally administered address state.
1649  **/
1650 void e1000_set_laa_state_82571(struct e1000_hw *hw, bool state)
1651 {
1652         DEBUGFUNC("e1000_set_laa_state_82571");
1653
1654         if (hw->mac.type != e1000_82571)
1655                 return;
1656
1657         hw->dev_spec._82571.laa_is_present = state;
1658
1659         /* If workaround is activated... */
1660         if (state)
1661                 /*
1662                  * Hold a copy of the LAA in RAR[14] This is done so that
1663                  * between the time RAR[0] gets clobbered and the time it
1664                  * gets fixed, the actual LAA is in one of the RARs and no
1665                  * incoming packets directed to this port are dropped.
1666                  * Eventually the LAA will be in RAR[0] and RAR[14].
1667                  */
1668                 e1000_rar_set_generic(hw, hw->mac.addr,
1669                                       hw->mac.rar_entry_count - 1);
1670         return;
1671 }
1672
1673 /**
1674  *  e1000_fix_nvm_checksum_82571 - Fix EEPROM checksum
1675  *  @hw: pointer to the HW structure
1676  *
1677  *  Verifies that the EEPROM has completed the update.  After updating the
1678  *  EEPROM, we need to check bit 15 in work 0x23 for the checksum fix.  If
1679  *  the checksum fix is not implemented, we need to set the bit and update
1680  *  the checksum.  Otherwise, if bit 15 is set and the checksum is incorrect,
1681  *  we need to return bad checksum.
1682  **/
1683 static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw)
1684 {
1685         struct e1000_nvm_info *nvm = &hw->nvm;
1686         s32 ret_val = E1000_SUCCESS;
1687         u16 data;
1688
1689         DEBUGFUNC("e1000_fix_nvm_checksum_82571");
1690
1691         if (nvm->type != e1000_nvm_flash_hw)
1692                 goto out;
1693
1694         /*
1695          * Check bit 4 of word 10h.  If it is 0, firmware is done updating
1696          * 10h-12h.  Checksum may need to be fixed.
1697          */
1698         ret_val = nvm->ops.read(hw, 0x10, 1, &data);
1699         if (ret_val)
1700                 goto out;
1701
1702         if (!(data & 0x10)) {
1703                 /*
1704                  * Read 0x23 and check bit 15.  This bit is a 1
1705                  * when the checksum has already been fixed.  If
1706                  * the checksum is still wrong and this bit is a
1707                  * 1, we need to return bad checksum.  Otherwise,
1708                  * we need to set this bit to a 1 and update the
1709                  * checksum.
1710                  */
1711                 ret_val = nvm->ops.read(hw, 0x23, 1, &data);
1712                 if (ret_val)
1713                         goto out;
1714
1715                 if (!(data & 0x8000)) {
1716                         data |= 0x8000;
1717                         ret_val = nvm->ops.write(hw, 0x23, 1, &data);
1718                         if (ret_val)
1719                                 goto out;
1720                         ret_val = nvm->ops.update(hw);
1721                 }
1722         }
1723
1724 out:
1725         return ret_val;
1726 }
1727
1728
1729 /**
1730  *  e1000_read_mac_addr_82571 - Read device MAC address
1731  *  @hw: pointer to the HW structure
1732  **/
1733 static s32 e1000_read_mac_addr_82571(struct e1000_hw *hw)
1734 {
1735         s32 ret_val = E1000_SUCCESS;
1736
1737         DEBUGFUNC("e1000_read_mac_addr_82571");
1738
1739         /*
1740          * If there's an alternate MAC address place it in RAR0
1741          * so that it will override the Si installed default perm
1742          * address.
1743          */
1744         ret_val = e1000_check_alt_mac_addr_generic(hw);
1745         if (ret_val)
1746                 goto out;
1747
1748         ret_val = e1000_read_mac_addr_generic(hw);
1749
1750 out:
1751         return ret_val;
1752 }
1753
1754 /**
1755  * e1000_power_down_phy_copper_82571 - Remove link during PHY power down
1756  * @hw: pointer to the HW structure
1757  *
1758  * In the case of a PHY power down to save power, or to turn off link during a
1759  * driver unload, or wake on lan is not enabled, remove the link.
1760  **/
1761 static void e1000_power_down_phy_copper_82571(struct e1000_hw *hw)
1762 {
1763         struct e1000_phy_info *phy = &hw->phy;
1764         struct e1000_mac_info *mac = &hw->mac;
1765
1766         if (!(phy->ops.check_reset_block))
1767                 return;
1768
1769         /* If the management interface is not enabled, then power down */
1770         if (!(mac->ops.check_mng_mode(hw) || phy->ops.check_reset_block(hw)))
1771                 e1000_power_down_phy_copper(hw);
1772
1773         return;
1774 }
1775
1776 /**
1777  *  e1000_clear_hw_cntrs_82571 - Clear device specific hardware counters
1778  *  @hw: pointer to the HW structure
1779  *
1780  *  Clears the hardware counters by reading the counter registers.
1781  **/
1782 static void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw)
1783 {
1784         DEBUGFUNC("e1000_clear_hw_cntrs_82571");
1785
1786         e1000_clear_hw_cntrs_base_generic(hw);
1787
1788         E1000_READ_REG(hw, E1000_PRC64);
1789         E1000_READ_REG(hw, E1000_PRC127);
1790         E1000_READ_REG(hw, E1000_PRC255);
1791         E1000_READ_REG(hw, E1000_PRC511);
1792         E1000_READ_REG(hw, E1000_PRC1023);
1793         E1000_READ_REG(hw, E1000_PRC1522);
1794         E1000_READ_REG(hw, E1000_PTC64);
1795         E1000_READ_REG(hw, E1000_PTC127);
1796         E1000_READ_REG(hw, E1000_PTC255);
1797         E1000_READ_REG(hw, E1000_PTC511);
1798         E1000_READ_REG(hw, E1000_PTC1023);
1799         E1000_READ_REG(hw, E1000_PTC1522);
1800
1801         E1000_READ_REG(hw, E1000_ALGNERRC);
1802         E1000_READ_REG(hw, E1000_RXERRC);
1803         E1000_READ_REG(hw, E1000_TNCRS);
1804         E1000_READ_REG(hw, E1000_CEXTERR);
1805         E1000_READ_REG(hw, E1000_TSCTC);
1806         E1000_READ_REG(hw, E1000_TSCTFC);
1807
1808         E1000_READ_REG(hw, E1000_MGTPRC);
1809         E1000_READ_REG(hw, E1000_MGTPDC);
1810         E1000_READ_REG(hw, E1000_MGTPTC);
1811
1812         E1000_READ_REG(hw, E1000_IAC);
1813         E1000_READ_REG(hw, E1000_ICRXOC);
1814
1815         E1000_READ_REG(hw, E1000_ICRXPTC);
1816         E1000_READ_REG(hw, E1000_ICRXATC);
1817         E1000_READ_REG(hw, E1000_ICTXPTC);
1818         E1000_READ_REG(hw, E1000_ICTXATC);
1819         E1000_READ_REG(hw, E1000_ICTXQEC);
1820         E1000_READ_REG(hw, E1000_ICTXQMTC);
1821         E1000_READ_REG(hw, E1000_ICRXDMTC);
1822 }