1 /******************************************************************************
3 Copyright (c) 2001-2010, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
32 ******************************************************************************/
38 #include "e1000_osdep.h"
39 #include "e1000_regs.h"
40 #include "e1000_defines.h"
44 #define E1000_DEV_ID_82542 0x1000
45 #define E1000_DEV_ID_82543GC_FIBER 0x1001
46 #define E1000_DEV_ID_82543GC_COPPER 0x1004
47 #define E1000_DEV_ID_82544EI_COPPER 0x1008
48 #define E1000_DEV_ID_82544EI_FIBER 0x1009
49 #define E1000_DEV_ID_82544GC_COPPER 0x100C
50 #define E1000_DEV_ID_82544GC_LOM 0x100D
51 #define E1000_DEV_ID_82540EM 0x100E
52 #define E1000_DEV_ID_82540EM_LOM 0x1015
53 #define E1000_DEV_ID_82540EP_LOM 0x1016
54 #define E1000_DEV_ID_82540EP 0x1017
55 #define E1000_DEV_ID_82540EP_LP 0x101E
56 #define E1000_DEV_ID_82545EM_COPPER 0x100F
57 #define E1000_DEV_ID_82545EM_FIBER 0x1011
58 #define E1000_DEV_ID_82545GM_COPPER 0x1026
59 #define E1000_DEV_ID_82545GM_FIBER 0x1027
60 #define E1000_DEV_ID_82545GM_SERDES 0x1028
61 #define E1000_DEV_ID_82546EB_COPPER 0x1010
62 #define E1000_DEV_ID_82546EB_FIBER 0x1012
63 #define E1000_DEV_ID_82546EB_QUAD_COPPER 0x101D
64 #define E1000_DEV_ID_82546GB_COPPER 0x1079
65 #define E1000_DEV_ID_82546GB_FIBER 0x107A
66 #define E1000_DEV_ID_82546GB_SERDES 0x107B
67 #define E1000_DEV_ID_82546GB_PCIE 0x108A
68 #define E1000_DEV_ID_82546GB_QUAD_COPPER 0x1099
69 #define E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3 0x10B5
70 #define E1000_DEV_ID_82541EI 0x1013
71 #define E1000_DEV_ID_82541EI_MOBILE 0x1018
72 #define E1000_DEV_ID_82541ER_LOM 0x1014
73 #define E1000_DEV_ID_82541ER 0x1078
74 #define E1000_DEV_ID_82541GI 0x1076
75 #define E1000_DEV_ID_82541GI_LF 0x107C
76 #define E1000_DEV_ID_82541GI_MOBILE 0x1077
77 #define E1000_DEV_ID_82547EI 0x1019
78 #define E1000_DEV_ID_82547EI_MOBILE 0x101A
79 #define E1000_DEV_ID_82547GI 0x1075
80 #define E1000_DEV_ID_82571EB_COPPER 0x105E
81 #define E1000_DEV_ID_82571EB_FIBER 0x105F
82 #define E1000_DEV_ID_82571EB_SERDES 0x1060
83 #define E1000_DEV_ID_82571EB_SERDES_DUAL 0x10D9
84 #define E1000_DEV_ID_82571EB_SERDES_QUAD 0x10DA
85 #define E1000_DEV_ID_82571EB_QUAD_COPPER 0x10A4
86 #define E1000_DEV_ID_82571PT_QUAD_COPPER 0x10D5
87 #define E1000_DEV_ID_82571EB_QUAD_FIBER 0x10A5
88 #define E1000_DEV_ID_82571EB_QUAD_COPPER_LP 0x10BC
89 #define E1000_DEV_ID_82572EI_COPPER 0x107D
90 #define E1000_DEV_ID_82572EI_FIBER 0x107E
91 #define E1000_DEV_ID_82572EI_SERDES 0x107F
92 #define E1000_DEV_ID_82572EI 0x10B9
93 #define E1000_DEV_ID_82573E 0x108B
94 #define E1000_DEV_ID_82573E_IAMT 0x108C
95 #define E1000_DEV_ID_82573L 0x109A
96 #define E1000_DEV_ID_82574L 0x10D3
97 #define E1000_DEV_ID_82574LA 0x10F6
98 #define E1000_DEV_ID_82583V 0x150C
99 #define E1000_DEV_ID_80003ES2LAN_COPPER_DPT 0x1096
100 #define E1000_DEV_ID_80003ES2LAN_SERDES_DPT 0x1098
101 #define E1000_DEV_ID_80003ES2LAN_COPPER_SPT 0x10BA
102 #define E1000_DEV_ID_80003ES2LAN_SERDES_SPT 0x10BB
103 #define E1000_DEV_ID_ICH8_82567V_3 0x1501
104 #define E1000_DEV_ID_ICH8_IGP_M_AMT 0x1049
105 #define E1000_DEV_ID_ICH8_IGP_AMT 0x104A
106 #define E1000_DEV_ID_ICH8_IGP_C 0x104B
107 #define E1000_DEV_ID_ICH8_IFE 0x104C
108 #define E1000_DEV_ID_ICH8_IFE_GT 0x10C4
109 #define E1000_DEV_ID_ICH8_IFE_G 0x10C5
110 #define E1000_DEV_ID_ICH8_IGP_M 0x104D
111 #define E1000_DEV_ID_ICH9_IGP_M 0x10BF
112 #define E1000_DEV_ID_ICH9_IGP_M_AMT 0x10F5
113 #define E1000_DEV_ID_ICH9_IGP_M_V 0x10CB
114 #define E1000_DEV_ID_ICH9_IGP_AMT 0x10BD
115 #define E1000_DEV_ID_ICH9_BM 0x10E5
116 #define E1000_DEV_ID_ICH9_IGP_C 0x294C
117 #define E1000_DEV_ID_ICH9_IFE 0x10C0
118 #define E1000_DEV_ID_ICH9_IFE_GT 0x10C3
119 #define E1000_DEV_ID_ICH9_IFE_G 0x10C2
120 #define E1000_DEV_ID_ICH10_R_BM_LM 0x10CC
121 #define E1000_DEV_ID_ICH10_R_BM_LF 0x10CD
122 #define E1000_DEV_ID_ICH10_R_BM_V 0x10CE
123 #define E1000_DEV_ID_ICH10_D_BM_LM 0x10DE
124 #define E1000_DEV_ID_ICH10_D_BM_LF 0x10DF
126 #define E1000_DEV_ID_PCH_M_HV_LM 0x10EA
127 #define E1000_DEV_ID_PCH_M_HV_LC 0x10EB
128 #define E1000_DEV_ID_PCH_D_HV_DM 0x10EF
129 #define E1000_DEV_ID_PCH_D_HV_DC 0x10F0
130 #define E1000_DEV_ID_82576 0x10C9
131 #define E1000_DEV_ID_82576_FIBER 0x10E6
132 #define E1000_DEV_ID_82576_SERDES 0x10E7
133 #define E1000_DEV_ID_82576_QUAD_COPPER 0x10E8
134 #define E1000_DEV_ID_82576_NS 0x150A
135 #define E1000_DEV_ID_82576_NS_SERDES 0x1518
136 #define E1000_DEV_ID_82576_SERDES_QUAD 0x150D
137 #define E1000_DEV_ID_82575EB_COPPER 0x10A7
138 #define E1000_DEV_ID_82575EB_FIBER_SERDES 0x10A9
139 #define E1000_DEV_ID_82575GB_QUAD_COPPER 0x10D6
140 #define E1000_DEV_ID_82575GB_QUAD_COPPER_PM 0x10E2
141 #define E1000_DEV_ID_82580_COPPER 0x150E
142 #define E1000_DEV_ID_82580_FIBER 0x150F
143 #define E1000_DEV_ID_82580_SERDES 0x1510
144 #define E1000_DEV_ID_82580_SGMII 0x1511
145 #define E1000_DEV_ID_82580_COPPER_DUAL 0x1516
146 #define E1000_REVISION_0 0
147 #define E1000_REVISION_1 1
148 #define E1000_REVISION_2 2
149 #define E1000_REVISION_3 3
150 #define E1000_REVISION_4 4
152 #define E1000_FUNC_0 0
153 #define E1000_FUNC_1 1
154 #define E1000_FUNC_2 2
155 #define E1000_FUNC_3 3
157 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN0 0
158 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN1 3
159 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN2 6
160 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN3 9
162 enum e1000_mac_type {
189 e1000_num_macs /* List is 1-based, so subtract 1 for TRUE count. */
192 enum e1000_media_type {
193 e1000_media_type_unknown = 0,
194 e1000_media_type_copper = 1,
195 e1000_media_type_fiber = 2,
196 e1000_media_type_internal_serdes = 3,
197 e1000_num_media_types
200 enum e1000_nvm_type {
201 e1000_nvm_unknown = 0,
203 e1000_nvm_eeprom_spi,
204 e1000_nvm_eeprom_microwire,
209 enum e1000_nvm_override {
210 e1000_nvm_override_none = 0,
211 e1000_nvm_override_spi_small,
212 e1000_nvm_override_spi_large,
213 e1000_nvm_override_microwire_small,
214 e1000_nvm_override_microwire_large
217 enum e1000_phy_type {
218 e1000_phy_unknown = 0,
233 enum e1000_bus_type {
234 e1000_bus_type_unknown = 0,
237 e1000_bus_type_pci_express,
238 e1000_bus_type_reserved
241 enum e1000_bus_speed {
242 e1000_bus_speed_unknown = 0,
248 e1000_bus_speed_2500,
249 e1000_bus_speed_5000,
250 e1000_bus_speed_reserved
253 enum e1000_bus_width {
254 e1000_bus_width_unknown = 0,
255 e1000_bus_width_pcie_x1,
256 e1000_bus_width_pcie_x2,
257 e1000_bus_width_pcie_x4 = 4,
258 e1000_bus_width_pcie_x8 = 8,
261 e1000_bus_width_reserved
264 enum e1000_1000t_rx_status {
265 e1000_1000t_rx_status_not_ok = 0,
266 e1000_1000t_rx_status_ok,
267 e1000_1000t_rx_status_undefined = 0xFF
270 enum e1000_rev_polarity {
271 e1000_rev_polarity_normal = 0,
272 e1000_rev_polarity_reversed,
273 e1000_rev_polarity_undefined = 0xFF
281 e1000_fc_default = 0xFF
284 enum e1000_ffe_config {
285 e1000_ffe_config_enabled = 0,
286 e1000_ffe_config_active,
287 e1000_ffe_config_blocked
290 enum e1000_dsp_config {
291 e1000_dsp_config_disabled = 0,
292 e1000_dsp_config_enabled,
293 e1000_dsp_config_activated,
294 e1000_dsp_config_undefined = 0xFF
298 e1000_ms_hw_default = 0,
299 e1000_ms_force_master,
300 e1000_ms_force_slave,
304 enum e1000_smart_speed {
305 e1000_smart_speed_default = 0,
306 e1000_smart_speed_on,
307 e1000_smart_speed_off
310 enum e1000_serdes_link_state {
311 e1000_serdes_link_down = 0,
312 e1000_serdes_link_autoneg_progress,
313 e1000_serdes_link_autoneg_complete,
314 e1000_serdes_link_forced_up
317 /* Receive Descriptor */
318 struct e1000_rx_desc {
319 __le64 buffer_addr; /* Address of the descriptor's data buffer */
320 __le16 length; /* Length of data DMAed into data buffer */
321 __le16 csum; /* Packet checksum */
322 u8 status; /* Descriptor status */
323 u8 errors; /* Descriptor Errors */
327 /* Receive Descriptor - Extended */
328 union e1000_rx_desc_extended {
335 __le32 mrq; /* Multiple Rx Queues */
337 __le32 rss; /* RSS Hash */
339 __le16 ip_id; /* IP id */
340 __le16 csum; /* Packet Checksum */
345 __le32 status_error; /* ext status/error */
347 __le16 vlan; /* VLAN tag */
349 } wb; /* writeback */
352 #define MAX_PS_BUFFERS 4
353 /* Receive Descriptor - Packet Split */
354 union e1000_rx_desc_packet_split {
356 /* one buffer for protocol header(s), three data buffers */
357 __le64 buffer_addr[MAX_PS_BUFFERS];
361 __le32 mrq; /* Multiple Rx Queues */
363 __le32 rss; /* RSS Hash */
365 __le16 ip_id; /* IP id */
366 __le16 csum; /* Packet Checksum */
371 __le32 status_error; /* ext status/error */
372 __le16 length0; /* length of buffer 0 */
373 __le16 vlan; /* VLAN tag */
376 __le16 header_status;
377 __le16 length[3]; /* length of buffers 1-3 */
380 } wb; /* writeback */
383 /* Transmit Descriptor */
384 struct e1000_tx_desc {
385 __le64 buffer_addr; /* Address of the descriptor's data buffer */
389 __le16 length; /* Data buffer length */
390 u8 cso; /* Checksum offset */
391 u8 cmd; /* Descriptor control */
397 u8 status; /* Descriptor status */
398 u8 css; /* Checksum start */
404 /* Offload Context Descriptor */
405 struct e1000_context_desc {
409 u8 ipcss; /* IP checksum start */
410 u8 ipcso; /* IP checksum offset */
411 __le16 ipcse; /* IP checksum end */
417 u8 tucss; /* TCP checksum start */
418 u8 tucso; /* TCP checksum offset */
419 __le16 tucse; /* TCP checksum end */
422 __le32 cmd_and_length;
426 u8 status; /* Descriptor status */
427 u8 hdr_len; /* Header length */
428 __le16 mss; /* Maximum segment size */
433 /* Offload data descriptor */
434 struct e1000_data_desc {
435 __le64 buffer_addr; /* Address of the descriptor's buffer address */
439 __le16 length; /* Data buffer length */
447 u8 status; /* Descriptor status */
448 u8 popts; /* Packet Options */
454 /* Statistics counters collected by the MAC */
455 struct e1000_hw_stats {
535 struct e1000_phy_stats {
540 struct e1000_host_mng_dhcp_cookie {
551 /* Host Interface "Rev 1" */
552 struct e1000_host_command_header {
559 #define E1000_HI_MAX_DATA_LENGTH 252
560 struct e1000_host_command_info {
561 struct e1000_host_command_header command_header;
562 u8 command_data[E1000_HI_MAX_DATA_LENGTH];
565 /* Host Interface "Rev 2" */
566 struct e1000_host_mng_command_header {
574 #define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8
575 struct e1000_host_mng_command_info {
576 struct e1000_host_mng_command_header command_header;
577 u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH];
580 #include "e1000_mac.h"
581 #include "e1000_phy.h"
582 #include "e1000_nvm.h"
583 #include "e1000_manage.h"
585 struct e1000_mac_operations {
586 /* Function pointers for the MAC. */
587 s32 (*init_params)(struct e1000_hw *);
588 s32 (*id_led_init)(struct e1000_hw *);
589 s32 (*blink_led)(struct e1000_hw *);
590 s32 (*check_for_link)(struct e1000_hw *);
591 bool (*check_mng_mode)(struct e1000_hw *hw);
592 s32 (*cleanup_led)(struct e1000_hw *);
593 void (*clear_hw_cntrs)(struct e1000_hw *);
594 void (*clear_vfta)(struct e1000_hw *);
595 s32 (*get_bus_info)(struct e1000_hw *);
596 void (*set_lan_id)(struct e1000_hw *);
597 s32 (*get_link_up_info)(struct e1000_hw *, u16 *, u16 *);
598 s32 (*led_on)(struct e1000_hw *);
599 s32 (*led_off)(struct e1000_hw *);
600 void (*update_mc_addr_list)(struct e1000_hw *, u8 *, u32);
601 s32 (*reset_hw)(struct e1000_hw *);
602 s32 (*init_hw)(struct e1000_hw *);
603 void (*shutdown_serdes)(struct e1000_hw *);
604 void (*power_up_serdes)(struct e1000_hw *);
605 s32 (*setup_link)(struct e1000_hw *);
606 s32 (*setup_physical_interface)(struct e1000_hw *);
607 s32 (*setup_led)(struct e1000_hw *);
608 void (*write_vfta)(struct e1000_hw *, u32, u32);
609 void (*config_collision_dist)(struct e1000_hw *);
610 void (*rar_set)(struct e1000_hw *, u8*, u32);
611 s32 (*read_mac_addr)(struct e1000_hw *);
612 s32 (*validate_mdi_setting)(struct e1000_hw *);
613 s32 (*mng_host_if_write)(struct e1000_hw *, u8*, u16, u16, u8*);
614 s32 (*mng_write_cmd_header)(struct e1000_hw *hw,
615 struct e1000_host_mng_command_header*);
616 s32 (*mng_enable_host_if)(struct e1000_hw *);
617 s32 (*wait_autoneg)(struct e1000_hw *);
620 struct e1000_phy_operations {
621 s32 (*init_params)(struct e1000_hw *);
622 s32 (*acquire)(struct e1000_hw *);
623 s32 (*cfg_on_link_up)(struct e1000_hw *);
624 s32 (*check_polarity)(struct e1000_hw *);
625 s32 (*check_reset_block)(struct e1000_hw *);
626 s32 (*commit)(struct e1000_hw *);
627 s32 (*force_speed_duplex)(struct e1000_hw *);
628 s32 (*get_cfg_done)(struct e1000_hw *hw);
629 s32 (*get_cable_length)(struct e1000_hw *);
630 s32 (*get_info)(struct e1000_hw *);
631 s32 (*read_reg)(struct e1000_hw *, u32, u16 *);
632 s32 (*read_reg_locked)(struct e1000_hw *, u32, u16 *);
633 void (*release)(struct e1000_hw *);
634 s32 (*reset)(struct e1000_hw *);
635 s32 (*set_d0_lplu_state)(struct e1000_hw *, bool);
636 s32 (*set_d3_lplu_state)(struct e1000_hw *, bool);
637 s32 (*write_reg)(struct e1000_hw *, u32, u16);
638 s32 (*write_reg_locked)(struct e1000_hw *, u32, u16);
639 void (*power_up)(struct e1000_hw *);
640 void (*power_down)(struct e1000_hw *);
643 struct e1000_nvm_operations {
644 s32 (*init_params)(struct e1000_hw *);
645 s32 (*acquire)(struct e1000_hw *);
646 s32 (*read)(struct e1000_hw *, u16, u16, u16 *);
647 void (*release)(struct e1000_hw *);
648 void (*reload)(struct e1000_hw *);
649 s32 (*update)(struct e1000_hw *);
650 s32 (*valid_led_default)(struct e1000_hw *, u16 *);
651 s32 (*validate)(struct e1000_hw *);
652 s32 (*write)(struct e1000_hw *, u16, u16, u16 *);
655 struct e1000_mac_info {
656 struct e1000_mac_operations ops;
660 enum e1000_mac_type type;
678 /* Maximum size of the MTA register table in all supported adapters */
679 #define MAX_MTA_REG 128
680 u32 mta_shadow[MAX_MTA_REG];
683 u8 forced_speed_duplex;
687 bool arc_subsystem_valid;
688 bool asf_firmware_present;
691 bool get_link_status;
693 bool report_tx_early;
694 enum e1000_serdes_link_state serdes_link_state;
695 bool serdes_has_link;
696 bool tx_pkt_filtering;
699 struct e1000_phy_info {
700 struct e1000_phy_operations ops;
701 enum e1000_phy_type type;
703 enum e1000_1000t_rx_status local_rx;
704 enum e1000_1000t_rx_status remote_rx;
705 enum e1000_ms_type ms_type;
706 enum e1000_ms_type original_ms_type;
707 enum e1000_rev_polarity cable_polarity;
708 enum e1000_smart_speed smart_speed;
712 u32 reset_delay_us; /* in usec */
715 enum e1000_media_type media_type;
717 u16 autoneg_advertised;
720 u16 max_cable_length;
721 u16 min_cable_length;
725 bool disable_polarity_correction;
727 bool polarity_correction;
729 bool speed_downgraded;
730 bool autoneg_wait_to_complete;
733 struct e1000_nvm_info {
734 struct e1000_nvm_operations ops;
735 enum e1000_nvm_type type;
736 enum e1000_nvm_override override;
748 struct e1000_bus_info {
749 enum e1000_bus_type type;
750 enum e1000_bus_speed speed;
751 enum e1000_bus_width width;
757 struct e1000_fc_info {
758 u32 high_water; /* Flow control high-water mark */
759 u32 low_water; /* Flow control low-water mark */
760 u16 pause_time; /* Flow control pause timer */
761 bool send_xon; /* Flow control send XON */
762 bool strict_ieee; /* Strict IEEE mode */
763 enum e1000_fc_mode current_mode; /* FC mode in effect */
764 enum e1000_fc_mode requested_mode; /* FC mode requested by caller */
767 struct e1000_dev_spec_82541 {
768 enum e1000_dsp_config dsp_config;
769 enum e1000_ffe_config ffe_config;
771 bool phy_init_script;
774 struct e1000_dev_spec_82542 {
778 struct e1000_dev_spec_82543 {
779 u32 tbi_compatibility;
781 bool init_phy_disabled;
784 struct e1000_dev_spec_82571 {
789 struct e1000_dev_spec_80003es2lan {
793 struct e1000_shadow_ram {
798 #define E1000_SHADOW_RAM_WORDS 2048
800 struct e1000_dev_spec_ich8lan {
801 bool kmrn_lock_loss_workaround_enabled;
802 struct e1000_shadow_ram shadow_ram[E1000_SHADOW_RAM_WORDS];
803 E1000_MUTEX nvm_mutex;
804 E1000_MUTEX swflag_mutex;
808 struct e1000_dev_spec_82575 {
810 bool global_device_reset;
813 struct e1000_dev_spec_vf {
824 unsigned long io_base;
826 struct e1000_mac_info mac;
827 struct e1000_fc_info fc;
828 struct e1000_phy_info phy;
829 struct e1000_nvm_info nvm;
830 struct e1000_bus_info bus;
831 struct e1000_host_mng_dhcp_cookie mng_cookie;
834 struct e1000_dev_spec_82541 _82541;
835 struct e1000_dev_spec_82542 _82542;
836 struct e1000_dev_spec_82543 _82543;
837 struct e1000_dev_spec_82571 _82571;
838 struct e1000_dev_spec_80003es2lan _80003es2lan;
839 struct e1000_dev_spec_ich8lan ich8lan;
840 struct e1000_dev_spec_82575 _82575;
841 struct e1000_dev_spec_vf vf;
845 u16 subsystem_vendor_id;
846 u16 subsystem_device_id;
852 #include "e1000_82541.h"
853 #include "e1000_82543.h"
854 #include "e1000_82571.h"
855 #include "e1000_80003es2lan.h"
856 #include "e1000_ich8lan.h"
857 #include "e1000_82575.h"
859 /* These functions must be implemented by drivers */
860 void e1000_pci_clear_mwi(struct e1000_hw *hw);
861 void e1000_pci_set_mwi(struct e1000_hw *hw);
862 s32 e1000_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value);
863 s32 e1000_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value);
864 void e1000_read_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value);
865 void e1000_write_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value);