1 /******************************************************************************
3 Copyright (c) 2001-2010, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
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13 notice, this list of conditions and the following disclaimer in the
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21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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32 ******************************************************************************/
35 #include "e1000_api.h"
37 static s32 e1000_validate_mdi_setting_generic(struct e1000_hw *hw);
38 static void e1000_set_lan_id_multi_port_pcie(struct e1000_hw *hw);
41 * e1000_init_mac_ops_generic - Initialize MAC function pointers
42 * @hw: pointer to the HW structure
44 * Setups up the function pointers to no-op functions
46 void e1000_init_mac_ops_generic(struct e1000_hw *hw)
48 struct e1000_mac_info *mac = &hw->mac;
49 DEBUGFUNC("e1000_init_mac_ops_generic");
52 mac->ops.init_params = e1000_null_ops_generic;
53 mac->ops.init_hw = e1000_null_ops_generic;
54 mac->ops.reset_hw = e1000_null_ops_generic;
55 mac->ops.setup_physical_interface = e1000_null_ops_generic;
56 mac->ops.get_bus_info = e1000_null_ops_generic;
57 mac->ops.set_lan_id = e1000_set_lan_id_multi_port_pcie;
58 mac->ops.read_mac_addr = e1000_read_mac_addr_generic;
59 mac->ops.config_collision_dist = e1000_config_collision_dist_generic;
60 mac->ops.clear_hw_cntrs = e1000_null_mac_generic;
62 mac->ops.cleanup_led = e1000_null_ops_generic;
63 mac->ops.setup_led = e1000_null_ops_generic;
64 mac->ops.blink_led = e1000_null_ops_generic;
65 mac->ops.led_on = e1000_null_ops_generic;
66 mac->ops.led_off = e1000_null_ops_generic;
68 mac->ops.setup_link = e1000_null_ops_generic;
69 mac->ops.get_link_up_info = e1000_null_link_info;
70 mac->ops.check_for_link = e1000_null_ops_generic;
71 mac->ops.wait_autoneg = e1000_wait_autoneg_generic;
73 mac->ops.check_mng_mode = e1000_null_mng_mode;
74 mac->ops.mng_host_if_write = e1000_mng_host_if_write_generic;
75 mac->ops.mng_write_cmd_header = e1000_mng_write_cmd_header_generic;
76 mac->ops.mng_enable_host_if = e1000_mng_enable_host_if_generic;
78 mac->ops.update_mc_addr_list = e1000_null_update_mc;
79 mac->ops.clear_vfta = e1000_null_mac_generic;
80 mac->ops.write_vfta = e1000_null_write_vfta;
81 mac->ops.rar_set = e1000_rar_set_generic;
82 mac->ops.validate_mdi_setting = e1000_validate_mdi_setting_generic;
86 * e1000_null_ops_generic - No-op function, returns 0
87 * @hw: pointer to the HW structure
89 s32 e1000_null_ops_generic(struct e1000_hw *hw)
91 DEBUGFUNC("e1000_null_ops_generic");
96 * e1000_null_mac_generic - No-op function, return void
97 * @hw: pointer to the HW structure
99 void e1000_null_mac_generic(struct e1000_hw *hw)
101 DEBUGFUNC("e1000_null_mac_generic");
106 * e1000_null_link_info - No-op function, return 0
107 * @hw: pointer to the HW structure
109 s32 e1000_null_link_info(struct e1000_hw *hw, u16 *s, u16 *d)
111 DEBUGFUNC("e1000_null_link_info");
112 return E1000_SUCCESS;
116 * e1000_null_mng_mode - No-op function, return FALSE
117 * @hw: pointer to the HW structure
119 bool e1000_null_mng_mode(struct e1000_hw *hw)
121 DEBUGFUNC("e1000_null_mng_mode");
126 * e1000_null_update_mc - No-op function, return void
127 * @hw: pointer to the HW structure
129 void e1000_null_update_mc(struct e1000_hw *hw, u8 *h, u32 a)
131 DEBUGFUNC("e1000_null_update_mc");
136 * e1000_null_write_vfta - No-op function, return void
137 * @hw: pointer to the HW structure
139 void e1000_null_write_vfta(struct e1000_hw *hw, u32 a, u32 b)
141 DEBUGFUNC("e1000_null_write_vfta");
146 * e1000_null_rar_set - No-op function, return void
147 * @hw: pointer to the HW structure
149 void e1000_null_rar_set(struct e1000_hw *hw, u8 *h, u32 a)
151 DEBUGFUNC("e1000_null_rar_set");
156 * e1000_get_bus_info_pci_generic - Get PCI(x) bus information
157 * @hw: pointer to the HW structure
159 * Determines and stores the system bus information for a particular
160 * network interface. The following bus information is determined and stored:
161 * bus speed, bus width, type (PCI/PCIx), and PCI(-x) function.
163 s32 e1000_get_bus_info_pci_generic(struct e1000_hw *hw)
165 struct e1000_mac_info *mac = &hw->mac;
166 struct e1000_bus_info *bus = &hw->bus;
167 u32 status = E1000_READ_REG(hw, E1000_STATUS);
168 s32 ret_val = E1000_SUCCESS;
170 DEBUGFUNC("e1000_get_bus_info_pci_generic");
173 bus->type = (status & E1000_STATUS_PCIX_MODE)
174 ? e1000_bus_type_pcix
175 : e1000_bus_type_pci;
178 if (bus->type == e1000_bus_type_pci) {
179 bus->speed = (status & E1000_STATUS_PCI66)
181 : e1000_bus_speed_33;
183 switch (status & E1000_STATUS_PCIX_SPEED) {
184 case E1000_STATUS_PCIX_SPEED_66:
185 bus->speed = e1000_bus_speed_66;
187 case E1000_STATUS_PCIX_SPEED_100:
188 bus->speed = e1000_bus_speed_100;
190 case E1000_STATUS_PCIX_SPEED_133:
191 bus->speed = e1000_bus_speed_133;
194 bus->speed = e1000_bus_speed_reserved;
200 bus->width = (status & E1000_STATUS_BUS64)
202 : e1000_bus_width_32;
204 /* Which PCI(-X) function? */
205 mac->ops.set_lan_id(hw);
211 * e1000_get_bus_info_pcie_generic - Get PCIe bus information
212 * @hw: pointer to the HW structure
214 * Determines and stores the system bus information for a particular
215 * network interface. The following bus information is determined and stored:
216 * bus speed, bus width, type (PCIe), and PCIe function.
218 s32 e1000_get_bus_info_pcie_generic(struct e1000_hw *hw)
220 struct e1000_mac_info *mac = &hw->mac;
221 struct e1000_bus_info *bus = &hw->bus;
223 u16 pcie_link_status;
225 DEBUGFUNC("e1000_get_bus_info_pcie_generic");
227 bus->type = e1000_bus_type_pci_express;
229 ret_val = e1000_read_pcie_cap_reg(hw,
233 bus->width = e1000_bus_width_unknown;
234 bus->speed = e1000_bus_speed_unknown;
236 switch (pcie_link_status & PCIE_LINK_SPEED_MASK) {
237 case PCIE_LINK_SPEED_2500:
238 bus->speed = e1000_bus_speed_2500;
240 case PCIE_LINK_SPEED_5000:
241 bus->speed = e1000_bus_speed_5000;
244 bus->speed = e1000_bus_speed_unknown;
248 bus->width = (enum e1000_bus_width)((pcie_link_status &
249 PCIE_LINK_WIDTH_MASK) >>
250 PCIE_LINK_WIDTH_SHIFT);
253 mac->ops.set_lan_id(hw);
255 return E1000_SUCCESS;
259 * e1000_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices
261 * @hw: pointer to the HW structure
263 * Determines the LAN function id by reading memory-mapped registers
264 * and swaps the port value if requested.
266 static void e1000_set_lan_id_multi_port_pcie(struct e1000_hw *hw)
268 struct e1000_bus_info *bus = &hw->bus;
272 * The status register reports the correct function number
273 * for the device regardless of function swap state.
275 reg = E1000_READ_REG(hw, E1000_STATUS);
276 bus->func = (reg & E1000_STATUS_FUNC_MASK) >> E1000_STATUS_FUNC_SHIFT;
280 * e1000_set_lan_id_multi_port_pci - Set LAN id for PCI multiple port devices
281 * @hw: pointer to the HW structure
283 * Determines the LAN function id by reading PCI config space.
285 void e1000_set_lan_id_multi_port_pci(struct e1000_hw *hw)
287 struct e1000_bus_info *bus = &hw->bus;
291 e1000_read_pci_cfg(hw, PCI_HEADER_TYPE_REGISTER, &pci_header_type);
292 if (pci_header_type & PCI_HEADER_TYPE_MULTIFUNC) {
293 status = E1000_READ_REG(hw, E1000_STATUS);
294 bus->func = (status & E1000_STATUS_FUNC_MASK)
295 >> E1000_STATUS_FUNC_SHIFT;
302 * e1000_set_lan_id_single_port - Set LAN id for a single port device
303 * @hw: pointer to the HW structure
305 * Sets the LAN function id to zero for a single port device.
307 void e1000_set_lan_id_single_port(struct e1000_hw *hw)
309 struct e1000_bus_info *bus = &hw->bus;
315 * e1000_clear_vfta_generic - Clear VLAN filter table
316 * @hw: pointer to the HW structure
318 * Clears the register array which contains the VLAN filter table by
319 * setting all the values to 0.
321 void e1000_clear_vfta_generic(struct e1000_hw *hw)
325 DEBUGFUNC("e1000_clear_vfta_generic");
327 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
328 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, 0);
329 E1000_WRITE_FLUSH(hw);
334 * e1000_write_vfta_generic - Write value to VLAN filter table
335 * @hw: pointer to the HW structure
336 * @offset: register offset in VLAN filter table
337 * @value: register value written to VLAN filter table
339 * Writes value at the given offset in the register array which stores
340 * the VLAN filter table.
342 void e1000_write_vfta_generic(struct e1000_hw *hw, u32 offset, u32 value)
344 DEBUGFUNC("e1000_write_vfta_generic");
346 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, value);
347 E1000_WRITE_FLUSH(hw);
351 * e1000_init_rx_addrs_generic - Initialize receive address's
352 * @hw: pointer to the HW structure
353 * @rar_count: receive address registers
355 * Setups the receive address registers by setting the base receive address
356 * register to the devices MAC address and clearing all the other receive
357 * address registers to 0.
359 void e1000_init_rx_addrs_generic(struct e1000_hw *hw, u16 rar_count)
362 u8 mac_addr[ETH_ADDR_LEN] = {0};
364 DEBUGFUNC("e1000_init_rx_addrs_generic");
366 /* Setup the receive address */
367 DEBUGOUT("Programming MAC Address into RAR[0]\n");
369 hw->mac.ops.rar_set(hw, hw->mac.addr, 0);
371 /* Zero out the other (rar_entry_count - 1) receive addresses */
372 DEBUGOUT1("Clearing RAR[1-%u]\n", rar_count-1);
373 for (i = 1; i < rar_count; i++)
374 hw->mac.ops.rar_set(hw, mac_addr, i);
378 * e1000_check_alt_mac_addr_generic - Check for alternate MAC addr
379 * @hw: pointer to the HW structure
381 * Checks the nvm for an alternate MAC address. An alternate MAC address
382 * can be setup by pre-boot software and must be treated like a permanent
383 * address and must override the actual permanent MAC address. If an
384 * alternate MAC address is found it is programmed into RAR0, replacing
385 * the permanent address that was installed into RAR0 by the Si on reset.
386 * This function will return SUCCESS unless it encounters an error while
387 * reading the EEPROM.
389 s32 e1000_check_alt_mac_addr_generic(struct e1000_hw *hw)
392 s32 ret_val = E1000_SUCCESS;
393 u16 offset, nvm_alt_mac_addr_offset, nvm_data;
394 u8 alt_mac_addr[ETH_ADDR_LEN];
396 DEBUGFUNC("e1000_check_alt_mac_addr_generic");
398 ret_val = hw->nvm.ops.read(hw, NVM_ALT_MAC_ADDR_PTR, 1,
399 &nvm_alt_mac_addr_offset);
401 DEBUGOUT("NVM Read Error\n");
405 if (nvm_alt_mac_addr_offset == 0xFFFF) {
406 /* There is no Alternate MAC Address */
410 if (hw->bus.func == E1000_FUNC_1)
411 nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN1;
412 if (hw->bus.func == E1000_FUNC_2)
413 nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN2;
415 if (hw->bus.func == E1000_FUNC_3)
416 nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN3;
417 for (i = 0; i < ETH_ADDR_LEN; i += 2) {
418 offset = nvm_alt_mac_addr_offset + (i >> 1);
419 ret_val = hw->nvm.ops.read(hw, offset, 1, &nvm_data);
421 DEBUGOUT("NVM Read Error\n");
425 alt_mac_addr[i] = (u8)(nvm_data & 0xFF);
426 alt_mac_addr[i + 1] = (u8)(nvm_data >> 8);
429 /* if multicast bit is set, the alternate address will not be used */
430 if (alt_mac_addr[0] & 0x01) {
431 DEBUGOUT("Ignoring Alternate Mac Address with MC bit set\n");
436 * We have a valid alternate MAC address, and we want to treat it the
437 * same as the normal permanent MAC address stored by the HW into the
438 * RAR. Do this by mapping this address into RAR0.
440 hw->mac.ops.rar_set(hw, alt_mac_addr, 0);
447 * e1000_rar_set_generic - Set receive address register
448 * @hw: pointer to the HW structure
449 * @addr: pointer to the receive address
450 * @index: receive address array register
452 * Sets the receive address array register at index to the address passed
455 void e1000_rar_set_generic(struct e1000_hw *hw, u8 *addr, u32 index)
457 u32 rar_low, rar_high;
459 DEBUGFUNC("e1000_rar_set_generic");
462 * HW expects these in little endian so we reverse the byte order
463 * from network order (big endian) to little endian
465 rar_low = ((u32) addr[0] |
466 ((u32) addr[1] << 8) |
467 ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
469 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
471 /* If MAC address zero, no need to set the AV bit */
472 if (rar_low || rar_high)
473 rar_high |= E1000_RAH_AV;
476 * Some bridges will combine consecutive 32-bit writes into
477 * a single burst write, which will malfunction on some parts.
478 * The flushes avoid this.
480 E1000_WRITE_REG(hw, E1000_RAL(index), rar_low);
481 E1000_WRITE_FLUSH(hw);
482 E1000_WRITE_REG(hw, E1000_RAH(index), rar_high);
483 E1000_WRITE_FLUSH(hw);
487 * e1000_update_mc_addr_list_generic - Update Multicast addresses
488 * @hw: pointer to the HW structure
489 * @mc_addr_list: array of multicast addresses to program
490 * @mc_addr_count: number of multicast addresses to program
492 * Updates entire Multicast Table Array.
493 * The caller must have a packed mc_addr_list of multicast addresses.
495 void e1000_update_mc_addr_list_generic(struct e1000_hw *hw,
496 u8 *mc_addr_list, u32 mc_addr_count)
498 u32 hash_value, hash_bit, hash_reg;
501 DEBUGFUNC("e1000_update_mc_addr_list_generic");
503 /* clear mta_shadow */
504 memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow));
506 /* update mta_shadow from mc_addr_list */
507 for (i = 0; (u32) i < mc_addr_count; i++) {
508 hash_value = e1000_hash_mc_addr_generic(hw, mc_addr_list);
510 hash_reg = (hash_value >> 5) & (hw->mac.mta_reg_count - 1);
511 hash_bit = hash_value & 0x1F;
513 hw->mac.mta_shadow[hash_reg] |= (1 << hash_bit);
514 mc_addr_list += (ETH_ADDR_LEN);
517 /* replace the entire MTA table */
518 for (i = hw->mac.mta_reg_count - 1; i >= 0; i--)
519 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, hw->mac.mta_shadow[i]);
520 E1000_WRITE_FLUSH(hw);
524 * e1000_hash_mc_addr_generic - Generate a multicast hash value
525 * @hw: pointer to the HW structure
526 * @mc_addr: pointer to a multicast address
528 * Generates a multicast address hash value which is used to determine
529 * the multicast filter table array address and new table value.
531 u32 e1000_hash_mc_addr_generic(struct e1000_hw *hw, u8 *mc_addr)
533 u32 hash_value, hash_mask;
536 DEBUGFUNC("e1000_hash_mc_addr_generic");
538 /* Register count multiplied by bits per register */
539 hash_mask = (hw->mac.mta_reg_count * 32) - 1;
542 * For a mc_filter_type of 0, bit_shift is the number of left-shifts
543 * where 0xFF would still fall within the hash mask.
545 while (hash_mask >> bit_shift != 0xFF)
549 * The portion of the address that is used for the hash table
550 * is determined by the mc_filter_type setting.
551 * The algorithm is such that there is a total of 8 bits of shifting.
552 * The bit_shift for a mc_filter_type of 0 represents the number of
553 * left-shifts where the MSB of mc_addr[5] would still fall within
554 * the hash_mask. Case 0 does this exactly. Since there are a total
555 * of 8 bits of shifting, then mc_addr[4] will shift right the
556 * remaining number of bits. Thus 8 - bit_shift. The rest of the
557 * cases are a variation of this algorithm...essentially raising the
558 * number of bits to shift mc_addr[5] left, while still keeping the
559 * 8-bit shifting total.
561 * For example, given the following Destination MAC Address and an
562 * mta register count of 128 (thus a 4096-bit vector and 0xFFF mask),
563 * we can see that the bit_shift for case 0 is 4. These are the hash
564 * values resulting from each mc_filter_type...
565 * [0] [1] [2] [3] [4] [5]
569 * case 0: hash_value = ((0x34 >> 4) | (0x56 << 4)) & 0xFFF = 0x563
570 * case 1: hash_value = ((0x34 >> 3) | (0x56 << 5)) & 0xFFF = 0xAC6
571 * case 2: hash_value = ((0x34 >> 2) | (0x56 << 6)) & 0xFFF = 0x163
572 * case 3: hash_value = ((0x34 >> 0) | (0x56 << 8)) & 0xFFF = 0x634
574 switch (hw->mac.mc_filter_type) {
589 hash_value = hash_mask & (((mc_addr[4] >> (8 - bit_shift)) |
590 (((u16) mc_addr[5]) << bit_shift)));
596 * e1000_pcix_mmrbc_workaround_generic - Fix incorrect MMRBC value
597 * @hw: pointer to the HW structure
599 * In certain situations, a system BIOS may report that the PCIx maximum
600 * memory read byte count (MMRBC) value is higher than than the actual
601 * value. We check the PCIx command register with the current PCIx status
604 void e1000_pcix_mmrbc_workaround_generic(struct e1000_hw *hw)
608 u16 pcix_stat_hi_word;
611 DEBUGFUNC("e1000_pcix_mmrbc_workaround_generic");
613 /* Workaround for PCI-X issue when BIOS sets MMRBC incorrectly */
614 if (hw->bus.type != e1000_bus_type_pcix)
617 e1000_read_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd);
618 e1000_read_pci_cfg(hw, PCIX_STATUS_REGISTER_HI, &pcix_stat_hi_word);
619 cmd_mmrbc = (pcix_cmd & PCIX_COMMAND_MMRBC_MASK) >>
620 PCIX_COMMAND_MMRBC_SHIFT;
621 stat_mmrbc = (pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >>
622 PCIX_STATUS_HI_MMRBC_SHIFT;
623 if (stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K)
624 stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K;
625 if (cmd_mmrbc > stat_mmrbc) {
626 pcix_cmd &= ~PCIX_COMMAND_MMRBC_MASK;
627 pcix_cmd |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT;
628 e1000_write_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd);
633 * e1000_clear_hw_cntrs_base_generic - Clear base hardware counters
634 * @hw: pointer to the HW structure
636 * Clears the base hardware counters by reading the counter registers.
638 void e1000_clear_hw_cntrs_base_generic(struct e1000_hw *hw)
640 DEBUGFUNC("e1000_clear_hw_cntrs_base_generic");
642 E1000_READ_REG(hw, E1000_CRCERRS);
643 E1000_READ_REG(hw, E1000_SYMERRS);
644 E1000_READ_REG(hw, E1000_MPC);
645 E1000_READ_REG(hw, E1000_SCC);
646 E1000_READ_REG(hw, E1000_ECOL);
647 E1000_READ_REG(hw, E1000_MCC);
648 E1000_READ_REG(hw, E1000_LATECOL);
649 E1000_READ_REG(hw, E1000_COLC);
650 E1000_READ_REG(hw, E1000_DC);
651 E1000_READ_REG(hw, E1000_SEC);
652 E1000_READ_REG(hw, E1000_RLEC);
653 E1000_READ_REG(hw, E1000_XONRXC);
654 E1000_READ_REG(hw, E1000_XONTXC);
655 E1000_READ_REG(hw, E1000_XOFFRXC);
656 E1000_READ_REG(hw, E1000_XOFFTXC);
657 E1000_READ_REG(hw, E1000_FCRUC);
658 E1000_READ_REG(hw, E1000_GPRC);
659 E1000_READ_REG(hw, E1000_BPRC);
660 E1000_READ_REG(hw, E1000_MPRC);
661 E1000_READ_REG(hw, E1000_GPTC);
662 E1000_READ_REG(hw, E1000_GORCL);
663 E1000_READ_REG(hw, E1000_GORCH);
664 E1000_READ_REG(hw, E1000_GOTCL);
665 E1000_READ_REG(hw, E1000_GOTCH);
666 E1000_READ_REG(hw, E1000_RNBC);
667 E1000_READ_REG(hw, E1000_RUC);
668 E1000_READ_REG(hw, E1000_RFC);
669 E1000_READ_REG(hw, E1000_ROC);
670 E1000_READ_REG(hw, E1000_RJC);
671 E1000_READ_REG(hw, E1000_TORL);
672 E1000_READ_REG(hw, E1000_TORH);
673 E1000_READ_REG(hw, E1000_TOTL);
674 E1000_READ_REG(hw, E1000_TOTH);
675 E1000_READ_REG(hw, E1000_TPR);
676 E1000_READ_REG(hw, E1000_TPT);
677 E1000_READ_REG(hw, E1000_MPTC);
678 E1000_READ_REG(hw, E1000_BPTC);
682 * e1000_check_for_copper_link_generic - Check for link (Copper)
683 * @hw: pointer to the HW structure
685 * Checks to see of the link status of the hardware has changed. If a
686 * change in link status has been detected, then we read the PHY registers
687 * to get the current speed/duplex if link exists.
689 s32 e1000_check_for_copper_link_generic(struct e1000_hw *hw)
691 struct e1000_mac_info *mac = &hw->mac;
695 DEBUGFUNC("e1000_check_for_copper_link");
698 * We only want to go out to the PHY registers to see if Auto-Neg
699 * has completed and/or if our link status has changed. The
700 * get_link_status flag is set upon receiving a Link Status
701 * Change or Rx Sequence Error interrupt.
703 if (!mac->get_link_status) {
704 ret_val = E1000_SUCCESS;
709 * First we want to see if the MII Status Register reports
710 * link. If so, then we want to get the current speed/duplex
713 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
718 goto out; /* No link detected */
720 mac->get_link_status = FALSE;
723 * Check if there was DownShift, must be checked
724 * immediately after link-up
726 e1000_check_downshift_generic(hw);
729 * If we are forcing speed/duplex, then we simply return since
730 * we have already determined whether we have link or not.
733 ret_val = -E1000_ERR_CONFIG;
738 * Auto-Neg is enabled. Auto Speed Detection takes care
739 * of MAC speed/duplex configuration. So we only need to
740 * configure Collision Distance in the MAC.
742 mac->ops.config_collision_dist(hw);
745 * Configure Flow Control now that Auto-Neg has completed.
746 * First, we need to restore the desired flow control
747 * settings because we may have had to re-autoneg with a
748 * different link partner.
750 ret_val = e1000_config_fc_after_link_up_generic(hw);
752 DEBUGOUT("Error configuring flow control\n");
759 * e1000_check_for_fiber_link_generic - Check for link (Fiber)
760 * @hw: pointer to the HW structure
762 * Checks for link up on the hardware. If link is not up and we have
763 * a signal, then we need to force link up.
765 s32 e1000_check_for_fiber_link_generic(struct e1000_hw *hw)
767 struct e1000_mac_info *mac = &hw->mac;
771 s32 ret_val = E1000_SUCCESS;
773 DEBUGFUNC("e1000_check_for_fiber_link_generic");
775 ctrl = E1000_READ_REG(hw, E1000_CTRL);
776 status = E1000_READ_REG(hw, E1000_STATUS);
777 rxcw = E1000_READ_REG(hw, E1000_RXCW);
780 * If we don't have link (auto-negotiation failed or link partner
781 * cannot auto-negotiate), the cable is plugged in (we have signal),
782 * and our link partner is not trying to auto-negotiate with us (we
783 * are receiving idles or data), we need to force link up. We also
784 * need to give auto-negotiation time to complete, in case the cable
785 * was just plugged in. The autoneg_failed flag does this.
787 /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */
788 if ((ctrl & E1000_CTRL_SWDPIN1) && (!(status & E1000_STATUS_LU)) &&
789 (!(rxcw & E1000_RXCW_C))) {
790 if (mac->autoneg_failed == 0) {
791 mac->autoneg_failed = 1;
794 DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\n");
796 /* Disable auto-negotiation in the TXCW register */
797 E1000_WRITE_REG(hw, E1000_TXCW, (mac->txcw & ~E1000_TXCW_ANE));
799 /* Force link-up and also force full-duplex. */
800 ctrl = E1000_READ_REG(hw, E1000_CTRL);
801 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
802 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
804 /* Configure Flow Control after forcing link up. */
805 ret_val = e1000_config_fc_after_link_up_generic(hw);
807 DEBUGOUT("Error configuring flow control\n");
810 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
812 * If we are forcing link and we are receiving /C/ ordered
813 * sets, re-enable auto-negotiation in the TXCW register
814 * and disable forced link in the Device Control register
815 * in an attempt to auto-negotiate with our link partner.
817 DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\n");
818 E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw);
819 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl & ~E1000_CTRL_SLU));
821 mac->serdes_has_link = TRUE;
829 * e1000_check_for_serdes_link_generic - Check for link (Serdes)
830 * @hw: pointer to the HW structure
832 * Checks for link up on the hardware. If link is not up and we have
833 * a signal, then we need to force link up.
835 s32 e1000_check_for_serdes_link_generic(struct e1000_hw *hw)
837 struct e1000_mac_info *mac = &hw->mac;
841 s32 ret_val = E1000_SUCCESS;
843 DEBUGFUNC("e1000_check_for_serdes_link_generic");
845 ctrl = E1000_READ_REG(hw, E1000_CTRL);
846 status = E1000_READ_REG(hw, E1000_STATUS);
847 rxcw = E1000_READ_REG(hw, E1000_RXCW);
850 * If we don't have link (auto-negotiation failed or link partner
851 * cannot auto-negotiate), and our link partner is not trying to
852 * auto-negotiate with us (we are receiving idles or data),
853 * we need to force link up. We also need to give auto-negotiation
856 /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */
857 if ((!(status & E1000_STATUS_LU)) && (!(rxcw & E1000_RXCW_C))) {
858 if (mac->autoneg_failed == 0) {
859 mac->autoneg_failed = 1;
862 DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\n");
864 /* Disable auto-negotiation in the TXCW register */
865 E1000_WRITE_REG(hw, E1000_TXCW, (mac->txcw & ~E1000_TXCW_ANE));
867 /* Force link-up and also force full-duplex. */
868 ctrl = E1000_READ_REG(hw, E1000_CTRL);
869 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
870 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
872 /* Configure Flow Control after forcing link up. */
873 ret_val = e1000_config_fc_after_link_up_generic(hw);
875 DEBUGOUT("Error configuring flow control\n");
878 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
880 * If we are forcing link and we are receiving /C/ ordered
881 * sets, re-enable auto-negotiation in the TXCW register
882 * and disable forced link in the Device Control register
883 * in an attempt to auto-negotiate with our link partner.
885 DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\n");
886 E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw);
887 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl & ~E1000_CTRL_SLU));
889 mac->serdes_has_link = TRUE;
890 } else if (!(E1000_TXCW_ANE & E1000_READ_REG(hw, E1000_TXCW))) {
892 * If we force link for non-auto-negotiation switch, check
893 * link status based on MAC synchronization for internal
896 /* SYNCH bit and IV bit are sticky. */
898 rxcw = E1000_READ_REG(hw, E1000_RXCW);
899 if (rxcw & E1000_RXCW_SYNCH) {
900 if (!(rxcw & E1000_RXCW_IV)) {
901 mac->serdes_has_link = TRUE;
902 DEBUGOUT("SERDES: Link up - forced.\n");
905 mac->serdes_has_link = FALSE;
906 DEBUGOUT("SERDES: Link down - force failed.\n");
910 if (E1000_TXCW_ANE & E1000_READ_REG(hw, E1000_TXCW)) {
911 status = E1000_READ_REG(hw, E1000_STATUS);
912 if (status & E1000_STATUS_LU) {
913 /* SYNCH bit and IV bit are sticky, so reread rxcw. */
915 rxcw = E1000_READ_REG(hw, E1000_RXCW);
916 if (rxcw & E1000_RXCW_SYNCH) {
917 if (!(rxcw & E1000_RXCW_IV)) {
918 mac->serdes_has_link = TRUE;
919 DEBUGOUT("SERDES: Link up - autoneg "
920 "completed sucessfully.\n");
922 mac->serdes_has_link = FALSE;
923 DEBUGOUT("SERDES: Link down - invalid"
924 "codewords detected in autoneg.\n");
927 mac->serdes_has_link = FALSE;
928 DEBUGOUT("SERDES: Link down - no sync.\n");
931 mac->serdes_has_link = FALSE;
932 DEBUGOUT("SERDES: Link down - autoneg failed\n");
941 * e1000_setup_link_generic - Setup flow control and link settings
942 * @hw: pointer to the HW structure
944 * Determines which flow control settings to use, then configures flow
945 * control. Calls the appropriate media-specific link configuration
946 * function. Assuming the adapter has a valid link partner, a valid link
947 * should be established. Assumes the hardware has previously been reset
948 * and the transmitter and receiver are not enabled.
950 s32 e1000_setup_link_generic(struct e1000_hw *hw)
952 s32 ret_val = E1000_SUCCESS;
954 DEBUGFUNC("e1000_setup_link_generic");
957 * In the case of the phy reset being blocked, we already have a link.
958 * We do not need to set it up again.
960 if (e1000_check_reset_block(hw))
964 * If requested flow control is set to default, set flow control
965 * based on the EEPROM flow control settings.
967 if (hw->fc.requested_mode == e1000_fc_default) {
968 ret_val = e1000_set_default_fc_generic(hw);
974 * Save off the requested flow control mode for use later. Depending
975 * on the link partner's capabilities, we may or may not use this mode.
977 hw->fc.current_mode = hw->fc.requested_mode;
979 DEBUGOUT1("After fix-ups FlowControl is now = %x\n",
980 hw->fc.current_mode);
982 /* Call the necessary media_type subroutine to configure the link. */
983 ret_val = hw->mac.ops.setup_physical_interface(hw);
988 * Initialize the flow control address, type, and PAUSE timer
989 * registers to their default values. This is done even if flow
990 * control is disabled, because it does not hurt anything to
991 * initialize these registers.
993 DEBUGOUT("Initializing the Flow Control address, type and timer regs\n");
994 E1000_WRITE_REG(hw, E1000_FCT, FLOW_CONTROL_TYPE);
995 E1000_WRITE_REG(hw, E1000_FCAH, FLOW_CONTROL_ADDRESS_HIGH);
996 E1000_WRITE_REG(hw, E1000_FCAL, FLOW_CONTROL_ADDRESS_LOW);
998 E1000_WRITE_REG(hw, E1000_FCTTV, hw->fc.pause_time);
1000 ret_val = e1000_set_fc_watermarks_generic(hw);
1007 * e1000_setup_fiber_serdes_link_generic - Setup link for fiber/serdes
1008 * @hw: pointer to the HW structure
1010 * Configures collision distance and flow control for fiber and serdes
1011 * links. Upon successful setup, poll for link.
1013 s32 e1000_setup_fiber_serdes_link_generic(struct e1000_hw *hw)
1015 struct e1000_mac_info *mac = &hw->mac;
1017 s32 ret_val = E1000_SUCCESS;
1019 DEBUGFUNC("e1000_setup_fiber_serdes_link_generic");
1021 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1023 /* Take the link out of reset */
1024 ctrl &= ~E1000_CTRL_LRST;
1026 mac->ops.config_collision_dist(hw);
1028 ret_val = e1000_commit_fc_settings_generic(hw);
1033 * Since auto-negotiation is enabled, take the link out of reset (the
1034 * link will be in reset, because we previously reset the chip). This
1035 * will restart auto-negotiation. If auto-negotiation is successful
1036 * then the link-up status bit will be set and the flow control enable
1037 * bits (RFCE and TFCE) will be set according to their negotiated value.
1039 DEBUGOUT("Auto-negotiation enabled\n");
1041 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1042 E1000_WRITE_FLUSH(hw);
1046 * For these adapters, the SW definable pin 1 is set when the optics
1047 * detect a signal. If we have a signal, then poll for a "Link-Up"
1050 if (hw->phy.media_type == e1000_media_type_internal_serdes ||
1051 (E1000_READ_REG(hw, E1000_CTRL) & E1000_CTRL_SWDPIN1)) {
1052 ret_val = e1000_poll_fiber_serdes_link_generic(hw);
1054 DEBUGOUT("No signal detected\n");
1062 * e1000_config_collision_dist_generic - Configure collision distance
1063 * @hw: pointer to the HW structure
1065 * Configures the collision distance to the default value and is used
1066 * during link setup.
1068 void e1000_config_collision_dist_generic(struct e1000_hw *hw)
1072 DEBUGFUNC("e1000_config_collision_dist_generic");
1074 tctl = E1000_READ_REG(hw, E1000_TCTL);
1076 tctl &= ~E1000_TCTL_COLD;
1077 tctl |= E1000_COLLISION_DISTANCE << E1000_COLD_SHIFT;
1079 E1000_WRITE_REG(hw, E1000_TCTL, tctl);
1080 E1000_WRITE_FLUSH(hw);
1084 * e1000_poll_fiber_serdes_link_generic - Poll for link up
1085 * @hw: pointer to the HW structure
1087 * Polls for link up by reading the status register, if link fails to come
1088 * up with auto-negotiation, then the link is forced if a signal is detected.
1090 s32 e1000_poll_fiber_serdes_link_generic(struct e1000_hw *hw)
1092 struct e1000_mac_info *mac = &hw->mac;
1094 s32 ret_val = E1000_SUCCESS;
1096 DEBUGFUNC("e1000_poll_fiber_serdes_link_generic");
1099 * If we have a signal (the cable is plugged in, or assumed TRUE for
1100 * serdes media) then poll for a "Link-Up" indication in the Device
1101 * Status Register. Time-out if a link isn't seen in 500 milliseconds
1102 * seconds (Auto-negotiation should complete in less than 500
1103 * milliseconds even if the other end is doing it in SW).
1105 for (i = 0; i < FIBER_LINK_UP_LIMIT; i++) {
1107 status = E1000_READ_REG(hw, E1000_STATUS);
1108 if (status & E1000_STATUS_LU)
1111 if (i == FIBER_LINK_UP_LIMIT) {
1112 DEBUGOUT("Never got a valid link from auto-neg!!!\n");
1113 mac->autoneg_failed = 1;
1115 * AutoNeg failed to achieve a link, so we'll call
1116 * mac->check_for_link. This routine will force the
1117 * link up if we detect a signal. This will allow us to
1118 * communicate with non-autonegotiating link partners.
1120 ret_val = mac->ops.check_for_link(hw);
1122 DEBUGOUT("Error while checking for link\n");
1125 mac->autoneg_failed = 0;
1127 mac->autoneg_failed = 0;
1128 DEBUGOUT("Valid Link Found\n");
1136 * e1000_commit_fc_settings_generic - Configure flow control
1137 * @hw: pointer to the HW structure
1139 * Write the flow control settings to the Transmit Config Word Register (TXCW)
1140 * base on the flow control settings in e1000_mac_info.
1142 s32 e1000_commit_fc_settings_generic(struct e1000_hw *hw)
1144 struct e1000_mac_info *mac = &hw->mac;
1146 s32 ret_val = E1000_SUCCESS;
1148 DEBUGFUNC("e1000_commit_fc_settings_generic");
1151 * Check for a software override of the flow control settings, and
1152 * setup the device accordingly. If auto-negotiation is enabled, then
1153 * software will have to set the "PAUSE" bits to the correct value in
1154 * the Transmit Config Word Register (TXCW) and re-start auto-
1155 * negotiation. However, if auto-negotiation is disabled, then
1156 * software will have to manually configure the two flow control enable
1157 * bits in the CTRL register.
1159 * The possible values of the "fc" parameter are:
1160 * 0: Flow control is completely disabled
1161 * 1: Rx flow control is enabled (we can receive pause frames,
1162 * but not send pause frames).
1163 * 2: Tx flow control is enabled (we can send pause frames but we
1164 * do not support receiving pause frames).
1165 * 3: Both Rx and Tx flow control (symmetric) are enabled.
1167 switch (hw->fc.current_mode) {
1169 /* Flow control completely disabled by a software over-ride. */
1170 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD);
1172 case e1000_fc_rx_pause:
1174 * Rx Flow control is enabled and Tx Flow control is disabled
1175 * by a software over-ride. Since there really isn't a way to
1176 * advertise that we are capable of Rx Pause ONLY, we will
1177 * advertise that we support both symmetric and asymmetric Rx
1178 * PAUSE. Later, we will disable the adapter's ability to send
1181 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
1183 case e1000_fc_tx_pause:
1185 * Tx Flow control is enabled, and Rx Flow control is disabled,
1186 * by a software over-ride.
1188 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR);
1192 * Flow control (both Rx and Tx) is enabled by a software
1195 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
1198 DEBUGOUT("Flow control param set incorrectly\n");
1199 ret_val = -E1000_ERR_CONFIG;
1204 E1000_WRITE_REG(hw, E1000_TXCW, txcw);
1212 * e1000_set_fc_watermarks_generic - Set flow control high/low watermarks
1213 * @hw: pointer to the HW structure
1215 * Sets the flow control high/low threshold (watermark) registers. If
1216 * flow control XON frame transmission is enabled, then set XON frame
1217 * transmission as well.
1219 s32 e1000_set_fc_watermarks_generic(struct e1000_hw *hw)
1221 u32 fcrtl = 0, fcrth = 0;
1223 DEBUGFUNC("e1000_set_fc_watermarks_generic");
1226 * Set the flow control receive threshold registers. Normally,
1227 * these registers will be set to a default threshold that may be
1228 * adjusted later by the driver's runtime code. However, if the
1229 * ability to transmit pause frames is not enabled, then these
1230 * registers will be set to 0.
1232 if (hw->fc.current_mode & e1000_fc_tx_pause) {
1234 * We need to set up the Receive Threshold high and low water
1235 * marks as well as (optionally) enabling the transmission of
1238 fcrtl = hw->fc.low_water;
1239 if (hw->fc.send_xon)
1240 fcrtl |= E1000_FCRTL_XONE;
1242 fcrth = hw->fc.high_water;
1244 E1000_WRITE_REG(hw, E1000_FCRTL, fcrtl);
1245 E1000_WRITE_REG(hw, E1000_FCRTH, fcrth);
1247 return E1000_SUCCESS;
1251 * e1000_set_default_fc_generic - Set flow control default values
1252 * @hw: pointer to the HW structure
1254 * Read the EEPROM for the default values for flow control and store the
1257 s32 e1000_set_default_fc_generic(struct e1000_hw *hw)
1259 s32 ret_val = E1000_SUCCESS;
1262 DEBUGFUNC("e1000_set_default_fc_generic");
1265 * Read and store word 0x0F of the EEPROM. This word contains bits
1266 * that determine the hardware's default PAUSE (flow control) mode,
1267 * a bit that determines whether the HW defaults to enabling or
1268 * disabling auto-negotiation, and the direction of the
1269 * SW defined pins. If there is no SW over-ride of the flow
1270 * control setting, then the variable hw->fc will
1271 * be initialized based on a value in the EEPROM.
1273 ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL2_REG, 1, &nvm_data);
1276 DEBUGOUT("NVM Read Error\n");
1280 if ((nvm_data & NVM_WORD0F_PAUSE_MASK) == 0)
1281 hw->fc.requested_mode = e1000_fc_none;
1282 else if ((nvm_data & NVM_WORD0F_PAUSE_MASK) ==
1284 hw->fc.requested_mode = e1000_fc_tx_pause;
1286 hw->fc.requested_mode = e1000_fc_full;
1293 * e1000_force_mac_fc_generic - Force the MAC's flow control settings
1294 * @hw: pointer to the HW structure
1296 * Force the MAC's flow control settings. Sets the TFCE and RFCE bits in the
1297 * device control register to reflect the adapter settings. TFCE and RFCE
1298 * need to be explicitly set by software when a copper PHY is used because
1299 * autonegotiation is managed by the PHY rather than the MAC. Software must
1300 * also configure these bits when link is forced on a fiber connection.
1302 s32 e1000_force_mac_fc_generic(struct e1000_hw *hw)
1305 s32 ret_val = E1000_SUCCESS;
1307 DEBUGFUNC("e1000_force_mac_fc_generic");
1309 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1312 * Because we didn't get link via the internal auto-negotiation
1313 * mechanism (we either forced link or we got link via PHY
1314 * auto-neg), we have to manually enable/disable transmit an
1315 * receive flow control.
1317 * The "Case" statement below enables/disable flow control
1318 * according to the "hw->fc.current_mode" parameter.
1320 * The possible values of the "fc" parameter are:
1321 * 0: Flow control is completely disabled
1322 * 1: Rx flow control is enabled (we can receive pause
1323 * frames but not send pause frames).
1324 * 2: Tx flow control is enabled (we can send pause frames
1325 * frames but we do not receive pause frames).
1326 * 3: Both Rx and Tx flow control (symmetric) is enabled.
1327 * other: No other values should be possible at this point.
1329 DEBUGOUT1("hw->fc.current_mode = %u\n", hw->fc.current_mode);
1331 switch (hw->fc.current_mode) {
1333 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE));
1335 case e1000_fc_rx_pause:
1336 ctrl &= (~E1000_CTRL_TFCE);
1337 ctrl |= E1000_CTRL_RFCE;
1339 case e1000_fc_tx_pause:
1340 ctrl &= (~E1000_CTRL_RFCE);
1341 ctrl |= E1000_CTRL_TFCE;
1344 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE);
1347 DEBUGOUT("Flow control param set incorrectly\n");
1348 ret_val = -E1000_ERR_CONFIG;
1352 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1359 * e1000_config_fc_after_link_up_generic - Configures flow control after link
1360 * @hw: pointer to the HW structure
1362 * Checks the status of auto-negotiation after link up to ensure that the
1363 * speed and duplex were not forced. If the link needed to be forced, then
1364 * flow control needs to be forced also. If auto-negotiation is enabled
1365 * and did not fail, then we configure flow control based on our link
1368 s32 e1000_config_fc_after_link_up_generic(struct e1000_hw *hw)
1370 struct e1000_mac_info *mac = &hw->mac;
1371 s32 ret_val = E1000_SUCCESS;
1372 u16 mii_status_reg, mii_nway_adv_reg, mii_nway_lp_ability_reg;
1375 DEBUGFUNC("e1000_config_fc_after_link_up_generic");
1378 * Check for the case where we have fiber media and auto-neg failed
1379 * so we had to force link. In this case, we need to force the
1380 * configuration of the MAC to match the "fc" parameter.
1382 if (mac->autoneg_failed) {
1383 if (hw->phy.media_type == e1000_media_type_fiber ||
1384 hw->phy.media_type == e1000_media_type_internal_serdes)
1385 ret_val = e1000_force_mac_fc_generic(hw);
1387 if (hw->phy.media_type == e1000_media_type_copper)
1388 ret_val = e1000_force_mac_fc_generic(hw);
1392 DEBUGOUT("Error forcing flow control settings\n");
1397 * Check for the case where we have copper media and auto-neg is
1398 * enabled. In this case, we need to check and see if Auto-Neg
1399 * has completed, and if so, how the PHY and link partner has
1400 * flow control configured.
1402 if ((hw->phy.media_type == e1000_media_type_copper) && mac->autoneg) {
1404 * Read the MII Status Register and check to see if AutoNeg
1405 * has completed. We read this twice because this reg has
1406 * some "sticky" (latched) bits.
1408 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg);
1411 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg);
1415 if (!(mii_status_reg & MII_SR_AUTONEG_COMPLETE)) {
1416 DEBUGOUT("Copper PHY and Auto Neg "
1417 "has not completed.\n");
1422 * The AutoNeg process has completed, so we now need to
1423 * read both the Auto Negotiation Advertisement
1424 * Register (Address 4) and the Auto_Negotiation Base
1425 * Page Ability Register (Address 5) to determine how
1426 * flow control was negotiated.
1428 ret_val = hw->phy.ops.read_reg(hw, PHY_AUTONEG_ADV,
1432 ret_val = hw->phy.ops.read_reg(hw, PHY_LP_ABILITY,
1433 &mii_nway_lp_ability_reg);
1438 * Two bits in the Auto Negotiation Advertisement Register
1439 * (Address 4) and two bits in the Auto Negotiation Base
1440 * Page Ability Register (Address 5) determine flow control
1441 * for both the PHY and the link partner. The following
1442 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
1443 * 1999, describes these PAUSE resolution bits and how flow
1444 * control is determined based upon these settings.
1445 * NOTE: DC = Don't Care
1447 * LOCAL DEVICE | LINK PARTNER
1448 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
1449 *-------|---------|-------|---------|--------------------
1450 * 0 | 0 | DC | DC | e1000_fc_none
1451 * 0 | 1 | 0 | DC | e1000_fc_none
1452 * 0 | 1 | 1 | 0 | e1000_fc_none
1453 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
1454 * 1 | 0 | 0 | DC | e1000_fc_none
1455 * 1 | DC | 1 | DC | e1000_fc_full
1456 * 1 | 1 | 0 | 0 | e1000_fc_none
1457 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
1459 * Are both PAUSE bits set to 1? If so, this implies
1460 * Symmetric Flow Control is enabled at both ends. The
1461 * ASM_DIR bits are irrelevant per the spec.
1463 * For Symmetric Flow Control:
1465 * LOCAL DEVICE | LINK PARTNER
1466 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1467 *-------|---------|-------|---------|--------------------
1468 * 1 | DC | 1 | DC | E1000_fc_full
1471 if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
1472 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) {
1474 * Now we need to check if the user selected Rx ONLY
1475 * of pause frames. In this case, we had to advertise
1476 * FULL flow control because we could not advertise Rx
1477 * ONLY. Hence, we must now check to see if we need to
1478 * turn OFF the TRANSMISSION of PAUSE frames.
1480 if (hw->fc.requested_mode == e1000_fc_full) {
1481 hw->fc.current_mode = e1000_fc_full;
1482 DEBUGOUT("Flow Control = FULL.\r\n");
1484 hw->fc.current_mode = e1000_fc_rx_pause;
1485 DEBUGOUT("Flow Control = "
1486 "Rx PAUSE frames only.\r\n");
1490 * For receiving PAUSE frames ONLY.
1492 * LOCAL DEVICE | LINK PARTNER
1493 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1494 *-------|---------|-------|---------|--------------------
1495 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
1497 else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&
1498 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
1499 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
1500 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
1501 hw->fc.current_mode = e1000_fc_tx_pause;
1502 DEBUGOUT("Flow Control = Tx PAUSE frames only.\r\n");
1505 * For transmitting PAUSE frames ONLY.
1507 * LOCAL DEVICE | LINK PARTNER
1508 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1509 *-------|---------|-------|---------|--------------------
1510 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
1512 else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
1513 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
1514 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
1515 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
1516 hw->fc.current_mode = e1000_fc_rx_pause;
1517 DEBUGOUT("Flow Control = Rx PAUSE frames only.\r\n");
1520 * Per the IEEE spec, at this point flow control
1521 * should be disabled.
1523 hw->fc.current_mode = e1000_fc_none;
1524 DEBUGOUT("Flow Control = NONE.\r\n");
1528 * Now we need to do one last check... If we auto-
1529 * negotiated to HALF DUPLEX, flow control should not be
1530 * enabled per IEEE 802.3 spec.
1532 ret_val = mac->ops.get_link_up_info(hw, &speed, &duplex);
1534 DEBUGOUT("Error getting link speed and duplex\n");
1538 if (duplex == HALF_DUPLEX)
1539 hw->fc.current_mode = e1000_fc_none;
1542 * Now we call a subroutine to actually force the MAC
1543 * controller to use the correct flow control settings.
1545 ret_val = e1000_force_mac_fc_generic(hw);
1547 DEBUGOUT("Error forcing flow control settings\n");
1557 * e1000_get_speed_and_duplex_copper_generic - Retrieve current speed/duplex
1558 * @hw: pointer to the HW structure
1559 * @speed: stores the current speed
1560 * @duplex: stores the current duplex
1562 * Read the status register for the current speed/duplex and store the current
1563 * speed and duplex for copper connections.
1565 s32 e1000_get_speed_and_duplex_copper_generic(struct e1000_hw *hw, u16 *speed,
1570 DEBUGFUNC("e1000_get_speed_and_duplex_copper_generic");
1572 status = E1000_READ_REG(hw, E1000_STATUS);
1573 if (status & E1000_STATUS_SPEED_1000) {
1574 *speed = SPEED_1000;
1575 DEBUGOUT("1000 Mbs, ");
1576 } else if (status & E1000_STATUS_SPEED_100) {
1578 DEBUGOUT("100 Mbs, ");
1581 DEBUGOUT("10 Mbs, ");
1584 if (status & E1000_STATUS_FD) {
1585 *duplex = FULL_DUPLEX;
1586 DEBUGOUT("Full Duplex\n");
1588 *duplex = HALF_DUPLEX;
1589 DEBUGOUT("Half Duplex\n");
1592 return E1000_SUCCESS;
1596 * e1000_get_speed_and_duplex_fiber_generic - Retrieve current speed/duplex
1597 * @hw: pointer to the HW structure
1598 * @speed: stores the current speed
1599 * @duplex: stores the current duplex
1601 * Sets the speed and duplex to gigabit full duplex (the only possible option)
1602 * for fiber/serdes links.
1604 s32 e1000_get_speed_and_duplex_fiber_serdes_generic(struct e1000_hw *hw,
1605 u16 *speed, u16 *duplex)
1607 DEBUGFUNC("e1000_get_speed_and_duplex_fiber_serdes_generic");
1609 *speed = SPEED_1000;
1610 *duplex = FULL_DUPLEX;
1612 return E1000_SUCCESS;
1616 * e1000_get_hw_semaphore_generic - Acquire hardware semaphore
1617 * @hw: pointer to the HW structure
1619 * Acquire the HW semaphore to access the PHY or NVM
1621 s32 e1000_get_hw_semaphore_generic(struct e1000_hw *hw)
1624 s32 ret_val = E1000_SUCCESS;
1625 s32 timeout = hw->nvm.word_size + 1;
1628 DEBUGFUNC("e1000_get_hw_semaphore_generic");
1630 /* Get the SW semaphore */
1631 while (i < timeout) {
1632 swsm = E1000_READ_REG(hw, E1000_SWSM);
1633 if (!(swsm & E1000_SWSM_SMBI))
1641 DEBUGOUT("Driver can't access device - SMBI bit is set.\n");
1642 ret_val = -E1000_ERR_NVM;
1646 /* Get the FW semaphore. */
1647 for (i = 0; i < timeout; i++) {
1648 swsm = E1000_READ_REG(hw, E1000_SWSM);
1649 E1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_SWESMBI);
1651 /* Semaphore acquired if bit latched */
1652 if (E1000_READ_REG(hw, E1000_SWSM) & E1000_SWSM_SWESMBI)
1659 /* Release semaphores */
1660 e1000_put_hw_semaphore_generic(hw);
1661 DEBUGOUT("Driver can't access the NVM\n");
1662 ret_val = -E1000_ERR_NVM;
1671 * e1000_put_hw_semaphore_generic - Release hardware semaphore
1672 * @hw: pointer to the HW structure
1674 * Release hardware semaphore used to access the PHY or NVM
1676 void e1000_put_hw_semaphore_generic(struct e1000_hw *hw)
1680 DEBUGFUNC("e1000_put_hw_semaphore_generic");
1682 swsm = E1000_READ_REG(hw, E1000_SWSM);
1684 swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI);
1686 E1000_WRITE_REG(hw, E1000_SWSM, swsm);
1690 * e1000_get_auto_rd_done_generic - Check for auto read completion
1691 * @hw: pointer to the HW structure
1693 * Check EEPROM for Auto Read done bit.
1695 s32 e1000_get_auto_rd_done_generic(struct e1000_hw *hw)
1698 s32 ret_val = E1000_SUCCESS;
1700 DEBUGFUNC("e1000_get_auto_rd_done_generic");
1702 while (i < AUTO_READ_DONE_TIMEOUT) {
1703 if (E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_AUTO_RD)
1709 if (i == AUTO_READ_DONE_TIMEOUT) {
1710 DEBUGOUT("Auto read by HW from NVM has not completed.\n");
1711 ret_val = -E1000_ERR_RESET;
1720 * e1000_valid_led_default_generic - Verify a valid default LED config
1721 * @hw: pointer to the HW structure
1722 * @data: pointer to the NVM (EEPROM)
1724 * Read the EEPROM for the current default LED configuration. If the
1725 * LED configuration is not valid, set to a valid LED configuration.
1727 s32 e1000_valid_led_default_generic(struct e1000_hw *hw, u16 *data)
1731 DEBUGFUNC("e1000_valid_led_default_generic");
1733 ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data);
1735 DEBUGOUT("NVM Read Error\n");
1739 if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF)
1740 *data = ID_LED_DEFAULT;
1747 * e1000_id_led_init_generic -
1748 * @hw: pointer to the HW structure
1751 s32 e1000_id_led_init_generic(struct e1000_hw *hw)
1753 struct e1000_mac_info *mac = &hw->mac;
1755 const u32 ledctl_mask = 0x000000FF;
1756 const u32 ledctl_on = E1000_LEDCTL_MODE_LED_ON;
1757 const u32 ledctl_off = E1000_LEDCTL_MODE_LED_OFF;
1759 const u16 led_mask = 0x0F;
1761 DEBUGFUNC("e1000_id_led_init_generic");
1763 ret_val = hw->nvm.ops.valid_led_default(hw, &data);
1767 mac->ledctl_default = E1000_READ_REG(hw, E1000_LEDCTL);
1768 mac->ledctl_mode1 = mac->ledctl_default;
1769 mac->ledctl_mode2 = mac->ledctl_default;
1771 for (i = 0; i < 4; i++) {
1772 temp = (data >> (i << 2)) & led_mask;
1774 case ID_LED_ON1_DEF2:
1775 case ID_LED_ON1_ON2:
1776 case ID_LED_ON1_OFF2:
1777 mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
1778 mac->ledctl_mode1 |= ledctl_on << (i << 3);
1780 case ID_LED_OFF1_DEF2:
1781 case ID_LED_OFF1_ON2:
1782 case ID_LED_OFF1_OFF2:
1783 mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
1784 mac->ledctl_mode1 |= ledctl_off << (i << 3);
1791 case ID_LED_DEF1_ON2:
1792 case ID_LED_ON1_ON2:
1793 case ID_LED_OFF1_ON2:
1794 mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
1795 mac->ledctl_mode2 |= ledctl_on << (i << 3);
1797 case ID_LED_DEF1_OFF2:
1798 case ID_LED_ON1_OFF2:
1799 case ID_LED_OFF1_OFF2:
1800 mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
1801 mac->ledctl_mode2 |= ledctl_off << (i << 3);
1814 * e1000_setup_led_generic - Configures SW controllable LED
1815 * @hw: pointer to the HW structure
1817 * This prepares the SW controllable LED for use and saves the current state
1818 * of the LED so it can be later restored.
1820 s32 e1000_setup_led_generic(struct e1000_hw *hw)
1823 s32 ret_val = E1000_SUCCESS;
1825 DEBUGFUNC("e1000_setup_led_generic");
1827 if (hw->mac.ops.setup_led != e1000_setup_led_generic) {
1828 ret_val = -E1000_ERR_CONFIG;
1832 if (hw->phy.media_type == e1000_media_type_fiber) {
1833 ledctl = E1000_READ_REG(hw, E1000_LEDCTL);
1834 hw->mac.ledctl_default = ledctl;
1836 ledctl &= ~(E1000_LEDCTL_LED0_IVRT |
1837 E1000_LEDCTL_LED0_BLINK |
1838 E1000_LEDCTL_LED0_MODE_MASK);
1839 ledctl |= (E1000_LEDCTL_MODE_LED_OFF <<
1840 E1000_LEDCTL_LED0_MODE_SHIFT);
1841 E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl);
1842 } else if (hw->phy.media_type == e1000_media_type_copper) {
1843 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1);
1851 * e1000_cleanup_led_generic - Set LED config to default operation
1852 * @hw: pointer to the HW structure
1854 * Remove the current LED configuration and set the LED configuration
1855 * to the default value, saved from the EEPROM.
1857 s32 e1000_cleanup_led_generic(struct e1000_hw *hw)
1859 DEBUGFUNC("e1000_cleanup_led_generic");
1861 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_default);
1862 return E1000_SUCCESS;
1866 * e1000_blink_led_generic - Blink LED
1867 * @hw: pointer to the HW structure
1869 * Blink the LEDs which are set to be on.
1871 s32 e1000_blink_led_generic(struct e1000_hw *hw)
1873 u32 ledctl_blink = 0;
1876 DEBUGFUNC("e1000_blink_led_generic");
1878 if (hw->phy.media_type == e1000_media_type_fiber) {
1879 /* always blink LED0 for PCI-E fiber */
1880 ledctl_blink = E1000_LEDCTL_LED0_BLINK |
1881 (E1000_LEDCTL_MODE_LED_ON << E1000_LEDCTL_LED0_MODE_SHIFT);
1884 * set the blink bit for each LED that's "on" (0x0E)
1887 ledctl_blink = hw->mac.ledctl_mode2;
1888 for (i = 0; i < 4; i++)
1889 if (((hw->mac.ledctl_mode2 >> (i * 8)) & 0xFF) ==
1890 E1000_LEDCTL_MODE_LED_ON)
1891 ledctl_blink |= (E1000_LEDCTL_LED0_BLINK <<
1895 E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl_blink);
1897 return E1000_SUCCESS;
1901 * e1000_led_on_generic - Turn LED on
1902 * @hw: pointer to the HW structure
1906 s32 e1000_led_on_generic(struct e1000_hw *hw)
1910 DEBUGFUNC("e1000_led_on_generic");
1912 switch (hw->phy.media_type) {
1913 case e1000_media_type_fiber:
1914 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1915 ctrl &= ~E1000_CTRL_SWDPIN0;
1916 ctrl |= E1000_CTRL_SWDPIO0;
1917 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1919 case e1000_media_type_copper:
1920 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode2);
1926 return E1000_SUCCESS;
1930 * e1000_led_off_generic - Turn LED off
1931 * @hw: pointer to the HW structure
1935 s32 e1000_led_off_generic(struct e1000_hw *hw)
1939 DEBUGFUNC("e1000_led_off_generic");
1941 switch (hw->phy.media_type) {
1942 case e1000_media_type_fiber:
1943 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1944 ctrl |= E1000_CTRL_SWDPIN0;
1945 ctrl |= E1000_CTRL_SWDPIO0;
1946 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1948 case e1000_media_type_copper:
1949 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1);
1955 return E1000_SUCCESS;
1959 * e1000_set_pcie_no_snoop_generic - Set PCI-express capabilities
1960 * @hw: pointer to the HW structure
1961 * @no_snoop: bitmap of snoop events
1963 * Set the PCI-express register to snoop for events enabled in 'no_snoop'.
1965 void e1000_set_pcie_no_snoop_generic(struct e1000_hw *hw, u32 no_snoop)
1969 DEBUGFUNC("e1000_set_pcie_no_snoop_generic");
1971 if (hw->bus.type != e1000_bus_type_pci_express)
1975 gcr = E1000_READ_REG(hw, E1000_GCR);
1976 gcr &= ~(PCIE_NO_SNOOP_ALL);
1978 E1000_WRITE_REG(hw, E1000_GCR, gcr);
1985 * e1000_disable_pcie_master_generic - Disables PCI-express master access
1986 * @hw: pointer to the HW structure
1988 * Returns E1000_SUCCESS if successful, else returns -10
1989 * (-E1000_ERR_MASTER_REQUESTS_PENDING) if master disable bit has not caused
1990 * the master requests to be disabled.
1992 * Disables PCI-Express master access and verifies there are no pending
1995 s32 e1000_disable_pcie_master_generic(struct e1000_hw *hw)
1998 s32 timeout = MASTER_DISABLE_TIMEOUT;
1999 s32 ret_val = E1000_SUCCESS;
2001 DEBUGFUNC("e1000_disable_pcie_master_generic");
2003 if (hw->bus.type != e1000_bus_type_pci_express)
2006 ctrl = E1000_READ_REG(hw, E1000_CTRL);
2007 ctrl |= E1000_CTRL_GIO_MASTER_DISABLE;
2008 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
2011 if (!(E1000_READ_REG(hw, E1000_STATUS) &
2012 E1000_STATUS_GIO_MASTER_ENABLE))
2019 DEBUGOUT("Master requests are pending.\n");
2020 ret_val = -E1000_ERR_MASTER_REQUESTS_PENDING;
2028 * e1000_reset_adaptive_generic - Reset Adaptive Interframe Spacing
2029 * @hw: pointer to the HW structure
2031 * Reset the Adaptive Interframe Spacing throttle to default values.
2033 void e1000_reset_adaptive_generic(struct e1000_hw *hw)
2035 struct e1000_mac_info *mac = &hw->mac;
2037 DEBUGFUNC("e1000_reset_adaptive_generic");
2039 if (!mac->adaptive_ifs) {
2040 DEBUGOUT("Not in Adaptive IFS mode!\n");
2044 mac->current_ifs_val = 0;
2045 mac->ifs_min_val = IFS_MIN;
2046 mac->ifs_max_val = IFS_MAX;
2047 mac->ifs_step_size = IFS_STEP;
2048 mac->ifs_ratio = IFS_RATIO;
2050 mac->in_ifs_mode = FALSE;
2051 E1000_WRITE_REG(hw, E1000_AIT, 0);
2057 * e1000_update_adaptive_generic - Update Adaptive Interframe Spacing
2058 * @hw: pointer to the HW structure
2060 * Update the Adaptive Interframe Spacing Throttle value based on the
2061 * time between transmitted packets and time between collisions.
2063 void e1000_update_adaptive_generic(struct e1000_hw *hw)
2065 struct e1000_mac_info *mac = &hw->mac;
2067 DEBUGFUNC("e1000_update_adaptive_generic");
2069 if (!mac->adaptive_ifs) {
2070 DEBUGOUT("Not in Adaptive IFS mode!\n");
2074 if ((mac->collision_delta * mac->ifs_ratio) > mac->tx_packet_delta) {
2075 if (mac->tx_packet_delta > MIN_NUM_XMITS) {
2076 mac->in_ifs_mode = TRUE;
2077 if (mac->current_ifs_val < mac->ifs_max_val) {
2078 if (!mac->current_ifs_val)
2079 mac->current_ifs_val = mac->ifs_min_val;
2081 mac->current_ifs_val +=
2083 E1000_WRITE_REG(hw, E1000_AIT, mac->current_ifs_val);
2087 if (mac->in_ifs_mode &&
2088 (mac->tx_packet_delta <= MIN_NUM_XMITS)) {
2089 mac->current_ifs_val = 0;
2090 mac->in_ifs_mode = FALSE;
2091 E1000_WRITE_REG(hw, E1000_AIT, 0);
2099 * e1000_validate_mdi_setting_generic - Verify MDI/MDIx settings
2100 * @hw: pointer to the HW structure
2102 * Verify that when not using auto-negotiation that MDI/MDIx is correctly
2103 * set, which is forced to MDI mode only.
2105 static s32 e1000_validate_mdi_setting_generic(struct e1000_hw *hw)
2107 s32 ret_val = E1000_SUCCESS;
2109 DEBUGFUNC("e1000_validate_mdi_setting_generic");
2111 if (!hw->mac.autoneg && (hw->phy.mdix == 0 || hw->phy.mdix == 3)) {
2112 DEBUGOUT("Invalid MDI setting detected\n");
2114 ret_val = -E1000_ERR_CONFIG;
2123 * e1000_write_8bit_ctrl_reg_generic - Write a 8bit CTRL register
2124 * @hw: pointer to the HW structure
2125 * @reg: 32bit register offset such as E1000_SCTL
2126 * @offset: register offset to write to
2127 * @data: data to write at register offset
2129 * Writes an address/data control type register. There are several of these
2130 * and they all have the format address << 8 | data and bit 31 is polled for
2133 s32 e1000_write_8bit_ctrl_reg_generic(struct e1000_hw *hw, u32 reg,
2134 u32 offset, u8 data)
2136 u32 i, regvalue = 0;
2137 s32 ret_val = E1000_SUCCESS;
2139 DEBUGFUNC("e1000_write_8bit_ctrl_reg_generic");
2141 /* Set up the address and data */
2142 regvalue = ((u32)data) | (offset << E1000_GEN_CTL_ADDRESS_SHIFT);
2143 E1000_WRITE_REG(hw, reg, regvalue);
2145 /* Poll the ready bit to see if the MDI read completed */
2146 for (i = 0; i < E1000_GEN_POLL_TIMEOUT; i++) {
2148 regvalue = E1000_READ_REG(hw, reg);
2149 if (regvalue & E1000_GEN_CTL_READY)
2152 if (!(regvalue & E1000_GEN_CTL_READY)) {
2153 DEBUGOUT1("Reg %08x did not indicate ready\n", reg);
2154 ret_val = -E1000_ERR_PHY;