1 /******************************************************************************
3 Copyright (c) 2001-2010, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
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13 notice, this list of conditions and the following disclaimer in the
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18 this software without specific prior written permission.
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21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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32 ******************************************************************************/
35 #include "e1000_api.h"
37 static u32 e1000_get_phy_addr_for_bm_page(u32 page, u32 reg);
38 static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset,
39 u16 *data, bool read);
40 static u32 e1000_get_phy_addr_for_hv_page(u32 page);
41 static s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset,
42 u16 *data, bool read);
44 /* Cable length tables */
45 static const u16 e1000_m88_cable_length_table[] =
46 { 0, 50, 80, 110, 140, 140, E1000_CABLE_LENGTH_UNDEFINED };
47 #define M88E1000_CABLE_LENGTH_TABLE_SIZE \
48 (sizeof(e1000_m88_cable_length_table) / \
49 sizeof(e1000_m88_cable_length_table[0]))
51 static const u16 e1000_igp_2_cable_length_table[] =
52 { 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21,
53 0, 0, 0, 3, 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41,
54 6, 10, 14, 18, 22, 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61,
55 21, 26, 31, 35, 40, 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82,
56 40, 45, 51, 56, 61, 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104,
57 60, 66, 72, 77, 82, 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121,
58 83, 89, 95, 100, 105, 109, 113, 116, 119, 122, 124,
59 104, 109, 114, 118, 121, 124};
60 #define IGP02E1000_CABLE_LENGTH_TABLE_SIZE \
61 (sizeof(e1000_igp_2_cable_length_table) / \
62 sizeof(e1000_igp_2_cable_length_table[0]))
65 * e1000_init_phy_ops_generic - Initialize PHY function pointers
66 * @hw: pointer to the HW structure
68 * Setups up the function pointers to no-op functions
70 void e1000_init_phy_ops_generic(struct e1000_hw *hw)
72 struct e1000_phy_info *phy = &hw->phy;
73 DEBUGFUNC("e1000_init_phy_ops_generic");
75 /* Initialize function pointers */
76 phy->ops.init_params = e1000_null_ops_generic;
77 phy->ops.acquire = e1000_null_ops_generic;
78 phy->ops.check_polarity = e1000_null_ops_generic;
79 phy->ops.check_reset_block = e1000_null_ops_generic;
80 phy->ops.commit = e1000_null_ops_generic;
81 phy->ops.force_speed_duplex = e1000_null_ops_generic;
82 phy->ops.get_cfg_done = e1000_null_ops_generic;
83 phy->ops.get_cable_length = e1000_null_ops_generic;
84 phy->ops.get_info = e1000_null_ops_generic;
85 phy->ops.read_reg = e1000_null_read_reg;
86 phy->ops.read_reg_locked = e1000_null_read_reg;
87 phy->ops.release = e1000_null_phy_generic;
88 phy->ops.reset = e1000_null_ops_generic;
89 phy->ops.set_d0_lplu_state = e1000_null_lplu_state;
90 phy->ops.set_d3_lplu_state = e1000_null_lplu_state;
91 phy->ops.write_reg = e1000_null_write_reg;
92 phy->ops.write_reg_locked = e1000_null_write_reg;
93 phy->ops.power_up = e1000_null_phy_generic;
94 phy->ops.power_down = e1000_null_phy_generic;
95 phy->ops.cfg_on_link_up = e1000_null_ops_generic;
99 * e1000_null_read_reg - No-op function, return 0
100 * @hw: pointer to the HW structure
102 s32 e1000_null_read_reg(struct e1000_hw *hw, u32 offset, u16 *data)
104 DEBUGFUNC("e1000_null_read_reg");
105 return E1000_SUCCESS;
109 * e1000_null_phy_generic - No-op function, return void
110 * @hw: pointer to the HW structure
112 void e1000_null_phy_generic(struct e1000_hw *hw)
114 DEBUGFUNC("e1000_null_phy_generic");
119 * e1000_null_lplu_state - No-op function, return 0
120 * @hw: pointer to the HW structure
122 s32 e1000_null_lplu_state(struct e1000_hw *hw, bool active)
124 DEBUGFUNC("e1000_null_lplu_state");
125 return E1000_SUCCESS;
129 * e1000_null_write_reg - No-op function, return 0
130 * @hw: pointer to the HW structure
132 s32 e1000_null_write_reg(struct e1000_hw *hw, u32 offset, u16 data)
134 DEBUGFUNC("e1000_null_write_reg");
135 return E1000_SUCCESS;
139 * e1000_check_reset_block_generic - Check if PHY reset is blocked
140 * @hw: pointer to the HW structure
142 * Read the PHY management control register and check whether a PHY reset
143 * is blocked. If a reset is not blocked return E1000_SUCCESS, otherwise
144 * return E1000_BLK_PHY_RESET (12).
146 s32 e1000_check_reset_block_generic(struct e1000_hw *hw)
150 DEBUGFUNC("e1000_check_reset_block");
152 manc = E1000_READ_REG(hw, E1000_MANC);
154 return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ?
155 E1000_BLK_PHY_RESET : E1000_SUCCESS;
159 * e1000_get_phy_id - Retrieve the PHY ID and revision
160 * @hw: pointer to the HW structure
162 * Reads the PHY registers and stores the PHY ID and possibly the PHY
163 * revision in the hardware structure.
165 s32 e1000_get_phy_id(struct e1000_hw *hw)
167 struct e1000_phy_info *phy = &hw->phy;
168 s32 ret_val = E1000_SUCCESS;
172 DEBUGFUNC("e1000_get_phy_id");
174 if (!(phy->ops.read_reg))
177 while (retry_count < 2) {
178 ret_val = phy->ops.read_reg(hw, PHY_ID1, &phy_id);
182 phy->id = (u32)(phy_id << 16);
184 ret_val = phy->ops.read_reg(hw, PHY_ID2, &phy_id);
188 phy->id |= (u32)(phy_id & PHY_REVISION_MASK);
189 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK);
191 if (phy->id != 0 && phy->id != PHY_REVISION_MASK)
201 * e1000_phy_reset_dsp_generic - Reset PHY DSP
202 * @hw: pointer to the HW structure
204 * Reset the digital signal processor.
206 s32 e1000_phy_reset_dsp_generic(struct e1000_hw *hw)
208 s32 ret_val = E1000_SUCCESS;
210 DEBUGFUNC("e1000_phy_reset_dsp_generic");
212 if (!(hw->phy.ops.write_reg))
215 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xC1);
219 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0);
226 * e1000_read_phy_reg_mdic - Read MDI control register
227 * @hw: pointer to the HW structure
228 * @offset: register offset to be read
229 * @data: pointer to the read data
231 * Reads the MDI control register in the PHY at offset and stores the
232 * information read to data.
234 s32 e1000_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data)
236 struct e1000_phy_info *phy = &hw->phy;
238 s32 ret_val = E1000_SUCCESS;
240 DEBUGFUNC("e1000_read_phy_reg_mdic");
242 if (offset > MAX_PHY_REG_ADDRESS) {
243 DEBUGOUT1("PHY Address %d is out of range\n", offset);
244 return -E1000_ERR_PARAM;
248 * Set up Op-code, Phy Address, and register offset in the MDI
249 * Control register. The MAC will take care of interfacing with the
250 * PHY to retrieve the desired data.
252 mdic = ((offset << E1000_MDIC_REG_SHIFT) |
253 (phy->addr << E1000_MDIC_PHY_SHIFT) |
254 (E1000_MDIC_OP_READ));
256 E1000_WRITE_REG(hw, E1000_MDIC, mdic);
258 /* Workaround for Si errata */
259 if ((hw->phy.type == e1000_phy_82577) && (hw->revision_id <= 2))
263 * Poll the ready bit to see if the MDI read completed
264 * Increasing the time out as testing showed failures with
267 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {
269 mdic = E1000_READ_REG(hw, E1000_MDIC);
270 if (mdic & E1000_MDIC_READY)
273 if (!(mdic & E1000_MDIC_READY)) {
274 DEBUGOUT("MDI Read did not complete\n");
275 ret_val = -E1000_ERR_PHY;
278 if (mdic & E1000_MDIC_ERROR) {
279 DEBUGOUT("MDI Error\n");
280 ret_val = -E1000_ERR_PHY;
290 * e1000_write_phy_reg_mdic - Write MDI control register
291 * @hw: pointer to the HW structure
292 * @offset: register offset to write to
293 * @data: data to write to register at offset
295 * Writes data to MDI control register in the PHY at offset.
297 s32 e1000_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data)
299 struct e1000_phy_info *phy = &hw->phy;
301 s32 ret_val = E1000_SUCCESS;
303 DEBUGFUNC("e1000_write_phy_reg_mdic");
305 if (offset > MAX_PHY_REG_ADDRESS) {
306 DEBUGOUT1("PHY Address %d is out of range\n", offset);
307 return -E1000_ERR_PARAM;
311 * Set up Op-code, Phy Address, and register offset in the MDI
312 * Control register. The MAC will take care of interfacing with the
313 * PHY to retrieve the desired data.
315 mdic = (((u32)data) |
316 (offset << E1000_MDIC_REG_SHIFT) |
317 (phy->addr << E1000_MDIC_PHY_SHIFT) |
318 (E1000_MDIC_OP_WRITE));
320 E1000_WRITE_REG(hw, E1000_MDIC, mdic);
322 /* Workaround for Si errata */
323 if ((hw->phy.type == e1000_phy_82577) && (hw->revision_id <= 2))
327 * Poll the ready bit to see if the MDI read completed
328 * Increasing the time out as testing showed failures with
331 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {
333 mdic = E1000_READ_REG(hw, E1000_MDIC);
334 if (mdic & E1000_MDIC_READY)
337 if (!(mdic & E1000_MDIC_READY)) {
338 DEBUGOUT("MDI Write did not complete\n");
339 ret_val = -E1000_ERR_PHY;
342 if (mdic & E1000_MDIC_ERROR) {
343 DEBUGOUT("MDI Error\n");
344 ret_val = -E1000_ERR_PHY;
353 * e1000_read_phy_reg_i2c - Read PHY register using i2c
354 * @hw: pointer to the HW structure
355 * @offset: register offset to be read
356 * @data: pointer to the read data
358 * Reads the PHY register at offset using the i2c interface and stores the
359 * retrieved information in data.
361 s32 e1000_read_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 *data)
363 struct e1000_phy_info *phy = &hw->phy;
366 DEBUGFUNC("e1000_read_phy_reg_i2c");
369 * Set up Op-code, Phy Address, and register address in the I2CCMD
370 * register. The MAC will take care of interfacing with the
371 * PHY to retrieve the desired data.
373 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) |
374 (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) |
375 (E1000_I2CCMD_OPCODE_READ));
377 E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd);
379 /* Poll the ready bit to see if the I2C read completed */
380 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) {
382 i2ccmd = E1000_READ_REG(hw, E1000_I2CCMD);
383 if (i2ccmd & E1000_I2CCMD_READY)
386 if (!(i2ccmd & E1000_I2CCMD_READY)) {
387 DEBUGOUT("I2CCMD Read did not complete\n");
388 return -E1000_ERR_PHY;
390 if (i2ccmd & E1000_I2CCMD_ERROR) {
391 DEBUGOUT("I2CCMD Error bit set\n");
392 return -E1000_ERR_PHY;
395 /* Need to byte-swap the 16-bit value. */
396 *data = ((i2ccmd >> 8) & 0x00FF) | ((i2ccmd << 8) & 0xFF00);
398 return E1000_SUCCESS;
402 * e1000_write_phy_reg_i2c - Write PHY register using i2c
403 * @hw: pointer to the HW structure
404 * @offset: register offset to write to
405 * @data: data to write at register offset
407 * Writes the data to PHY register at the offset using the i2c interface.
409 s32 e1000_write_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 data)
411 struct e1000_phy_info *phy = &hw->phy;
413 u16 phy_data_swapped;
415 DEBUGFUNC("e1000_write_phy_reg_i2c");
417 /* Swap the data bytes for the I2C interface */
418 phy_data_swapped = ((data >> 8) & 0x00FF) | ((data << 8) & 0xFF00);
421 * Set up Op-code, Phy Address, and register address in the I2CCMD
422 * register. The MAC will take care of interfacing with the
423 * PHY to retrieve the desired data.
425 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) |
426 (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) |
427 E1000_I2CCMD_OPCODE_WRITE |
430 E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd);
432 /* Poll the ready bit to see if the I2C read completed */
433 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) {
435 i2ccmd = E1000_READ_REG(hw, E1000_I2CCMD);
436 if (i2ccmd & E1000_I2CCMD_READY)
439 if (!(i2ccmd & E1000_I2CCMD_READY)) {
440 DEBUGOUT("I2CCMD Write did not complete\n");
441 return -E1000_ERR_PHY;
443 if (i2ccmd & E1000_I2CCMD_ERROR) {
444 DEBUGOUT("I2CCMD Error bit set\n");
445 return -E1000_ERR_PHY;
448 return E1000_SUCCESS;
452 * e1000_read_phy_reg_m88 - Read m88 PHY register
453 * @hw: pointer to the HW structure
454 * @offset: register offset to be read
455 * @data: pointer to the read data
457 * Acquires semaphore, if necessary, then reads the PHY register at offset
458 * and storing the retrieved information in data. Release any acquired
459 * semaphores before exiting.
461 s32 e1000_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data)
463 s32 ret_val = E1000_SUCCESS;
465 DEBUGFUNC("e1000_read_phy_reg_m88");
467 if (!(hw->phy.ops.acquire))
470 ret_val = hw->phy.ops.acquire(hw);
474 ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
477 hw->phy.ops.release(hw);
484 * e1000_write_phy_reg_m88 - Write m88 PHY register
485 * @hw: pointer to the HW structure
486 * @offset: register offset to write to
487 * @data: data to write at register offset
489 * Acquires semaphore, if necessary, then writes the data to PHY register
490 * at the offset. Release any acquired semaphores before exiting.
492 s32 e1000_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data)
494 s32 ret_val = E1000_SUCCESS;
496 DEBUGFUNC("e1000_write_phy_reg_m88");
498 if (!(hw->phy.ops.acquire))
501 ret_val = hw->phy.ops.acquire(hw);
505 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
508 hw->phy.ops.release(hw);
515 * __e1000_read_phy_reg_igp - Read igp PHY register
516 * @hw: pointer to the HW structure
517 * @offset: register offset to be read
518 * @data: pointer to the read data
519 * @locked: semaphore has already been acquired or not
521 * Acquires semaphore, if necessary, then reads the PHY register at offset
522 * and stores the retrieved information in data. Release any acquired
523 * semaphores before exiting.
525 static s32 __e1000_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data,
528 s32 ret_val = E1000_SUCCESS;
530 DEBUGFUNC("__e1000_read_phy_reg_igp");
533 if (!(hw->phy.ops.acquire))
536 ret_val = hw->phy.ops.acquire(hw);
541 if (offset > MAX_PHY_MULTI_PAGE_REG) {
542 ret_val = e1000_write_phy_reg_mdic(hw,
543 IGP01E1000_PHY_PAGE_SELECT,
549 ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
554 hw->phy.ops.release(hw);
560 * e1000_read_phy_reg_igp - Read igp PHY register
561 * @hw: pointer to the HW structure
562 * @offset: register offset to be read
563 * @data: pointer to the read data
565 * Acquires semaphore then reads the PHY register at offset and stores the
566 * retrieved information in data.
567 * Release the acquired semaphore before exiting.
569 s32 e1000_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data)
571 return __e1000_read_phy_reg_igp(hw, offset, data, FALSE);
575 * e1000_read_phy_reg_igp_locked - Read igp PHY register
576 * @hw: pointer to the HW structure
577 * @offset: register offset to be read
578 * @data: pointer to the read data
580 * Reads the PHY register at offset and stores the retrieved information
581 * in data. Assumes semaphore already acquired.
583 s32 e1000_read_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 *data)
585 return __e1000_read_phy_reg_igp(hw, offset, data, TRUE);
589 * e1000_write_phy_reg_igp - Write igp PHY register
590 * @hw: pointer to the HW structure
591 * @offset: register offset to write to
592 * @data: data to write at register offset
593 * @locked: semaphore has already been acquired or not
595 * Acquires semaphore, if necessary, then writes the data to PHY register
596 * at the offset. Release any acquired semaphores before exiting.
598 static s32 __e1000_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data,
601 s32 ret_val = E1000_SUCCESS;
603 DEBUGFUNC("e1000_write_phy_reg_igp");
606 if (!(hw->phy.ops.acquire))
609 ret_val = hw->phy.ops.acquire(hw);
614 if (offset > MAX_PHY_MULTI_PAGE_REG) {
615 ret_val = e1000_write_phy_reg_mdic(hw,
616 IGP01E1000_PHY_PAGE_SELECT,
622 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
627 hw->phy.ops.release(hw);
634 * e1000_write_phy_reg_igp - Write igp PHY register
635 * @hw: pointer to the HW structure
636 * @offset: register offset to write to
637 * @data: data to write at register offset
639 * Acquires semaphore then writes the data to PHY register
640 * at the offset. Release any acquired semaphores before exiting.
642 s32 e1000_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data)
644 return __e1000_write_phy_reg_igp(hw, offset, data, FALSE);
648 * e1000_write_phy_reg_igp_locked - Write igp PHY register
649 * @hw: pointer to the HW structure
650 * @offset: register offset to write to
651 * @data: data to write at register offset
653 * Writes the data to PHY register at the offset.
654 * Assumes semaphore already acquired.
656 s32 e1000_write_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 data)
658 return __e1000_write_phy_reg_igp(hw, offset, data, TRUE);
662 * __e1000_read_kmrn_reg - Read kumeran register
663 * @hw: pointer to the HW structure
664 * @offset: register offset to be read
665 * @data: pointer to the read data
666 * @locked: semaphore has already been acquired or not
668 * Acquires semaphore, if necessary. Then reads the PHY register at offset
669 * using the kumeran interface. The information retrieved is stored in data.
670 * Release any acquired semaphores before exiting.
672 static s32 __e1000_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data,
676 s32 ret_val = E1000_SUCCESS;
678 DEBUGFUNC("__e1000_read_kmrn_reg");
681 if (!(hw->phy.ops.acquire))
684 ret_val = hw->phy.ops.acquire(hw);
689 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
690 E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN;
691 E1000_WRITE_REG(hw, E1000_KMRNCTRLSTA, kmrnctrlsta);
695 kmrnctrlsta = E1000_READ_REG(hw, E1000_KMRNCTRLSTA);
696 *data = (u16)kmrnctrlsta;
699 hw->phy.ops.release(hw);
706 * e1000_read_kmrn_reg_generic - Read kumeran register
707 * @hw: pointer to the HW structure
708 * @offset: register offset to be read
709 * @data: pointer to the read data
711 * Acquires semaphore then reads the PHY register at offset using the
712 * kumeran interface. The information retrieved is stored in data.
713 * Release the acquired semaphore before exiting.
715 s32 e1000_read_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 *data)
717 return __e1000_read_kmrn_reg(hw, offset, data, FALSE);
721 * e1000_read_kmrn_reg_locked - Read kumeran register
722 * @hw: pointer to the HW structure
723 * @offset: register offset to be read
724 * @data: pointer to the read data
726 * Reads the PHY register at offset using the kumeran interface. The
727 * information retrieved is stored in data.
728 * Assumes semaphore already acquired.
730 s32 e1000_read_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 *data)
732 return __e1000_read_kmrn_reg(hw, offset, data, TRUE);
736 * __e1000_write_kmrn_reg - Write kumeran register
737 * @hw: pointer to the HW structure
738 * @offset: register offset to write to
739 * @data: data to write at register offset
740 * @locked: semaphore has already been acquired or not
742 * Acquires semaphore, if necessary. Then write the data to PHY register
743 * at the offset using the kumeran interface. Release any acquired semaphores
746 static s32 __e1000_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data,
750 s32 ret_val = E1000_SUCCESS;
752 DEBUGFUNC("e1000_write_kmrn_reg_generic");
755 if (!(hw->phy.ops.acquire))
758 ret_val = hw->phy.ops.acquire(hw);
763 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
764 E1000_KMRNCTRLSTA_OFFSET) | data;
765 E1000_WRITE_REG(hw, E1000_KMRNCTRLSTA, kmrnctrlsta);
770 hw->phy.ops.release(hw);
777 * e1000_write_kmrn_reg_generic - Write kumeran register
778 * @hw: pointer to the HW structure
779 * @offset: register offset to write to
780 * @data: data to write at register offset
782 * Acquires semaphore then writes the data to the PHY register at the offset
783 * using the kumeran interface. Release the acquired semaphore before exiting.
785 s32 e1000_write_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 data)
787 return __e1000_write_kmrn_reg(hw, offset, data, FALSE);
791 * e1000_write_kmrn_reg_locked - Write kumeran register
792 * @hw: pointer to the HW structure
793 * @offset: register offset to write to
794 * @data: data to write at register offset
796 * Write the data to PHY register at the offset using the kumeran interface.
797 * Assumes semaphore already acquired.
799 s32 e1000_write_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 data)
801 return __e1000_write_kmrn_reg(hw, offset, data, TRUE);
805 * e1000_copper_link_setup_82577 - Setup 82577 PHY for copper link
806 * @hw: pointer to the HW structure
808 * Sets up Carrier-sense on Transmit and downshift values.
810 s32 e1000_copper_link_setup_82577(struct e1000_hw *hw)
815 DEBUGFUNC("e1000_copper_link_setup_82577");
817 if (hw->phy.reset_disable) {
818 ret_val = E1000_SUCCESS;
822 if (hw->phy.type == e1000_phy_82580) {
823 ret_val = hw->phy.ops.reset(hw);
825 DEBUGOUT("Error resetting the PHY.\n");
830 /* Enable CRS on TX. This must be set for half-duplex operation. */
831 ret_val = hw->phy.ops.read_reg(hw, I82577_CFG_REG, &phy_data);
835 phy_data |= I82577_CFG_ASSERT_CRS_ON_TX;
837 /* Enable downshift */
838 phy_data |= I82577_CFG_ENABLE_DOWNSHIFT;
840 ret_val = hw->phy.ops.write_reg(hw, I82577_CFG_REG, phy_data);
847 * e1000_copper_link_setup_m88 - Setup m88 PHY's for copper link
848 * @hw: pointer to the HW structure
850 * Sets up MDI/MDI-X and polarity for m88 PHY's. If necessary, transmit clock
851 * and downshift values are set also.
853 s32 e1000_copper_link_setup_m88(struct e1000_hw *hw)
855 struct e1000_phy_info *phy = &hw->phy;
859 DEBUGFUNC("e1000_copper_link_setup_m88");
861 if (phy->reset_disable) {
862 ret_val = E1000_SUCCESS;
866 /* Enable CRS on Tx. This must be set for half-duplex operation. */
867 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
871 /* For BM PHY this bit is downshift enable */
872 if (phy->type != e1000_phy_bm)
873 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
877 * MDI/MDI-X = 0 (default)
878 * 0 - Auto for all speeds
881 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
883 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
887 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
890 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
893 phy_data |= M88E1000_PSCR_AUTO_X_1000T;
897 phy_data |= M88E1000_PSCR_AUTO_X_MODE;
903 * disable_polarity_correction = 0 (default)
904 * Automatic Correction for Reversed Cable Polarity
908 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
909 if (phy->disable_polarity_correction == 1)
910 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
912 /* Enable downshift on BM (disabled by default) */
913 if (phy->type == e1000_phy_bm)
914 phy_data |= BME1000_PSCR_ENABLE_DOWNSHIFT;
916 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
920 if ((phy->type == e1000_phy_m88) &&
921 (phy->revision < E1000_REVISION_4) &&
922 (phy->id != BME1000_E_PHY_ID_R2)) {
924 * Force TX_CLK in the Extended PHY Specific Control Register
927 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
932 phy_data |= M88E1000_EPSCR_TX_CLK_25;
934 if ((phy->revision == E1000_REVISION_2) &&
935 (phy->id == M88E1111_I_PHY_ID)) {
936 /* 82573L PHY - set the downshift counter to 5x. */
937 phy_data &= ~M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK;
938 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X;
940 /* Configure Master and Slave downshift values */
941 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK |
942 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
943 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X |
944 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
946 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
952 if ((phy->type == e1000_phy_bm) && (phy->id == BME1000_E_PHY_ID_R2)) {
953 /* Set PHY page 0, register 29 to 0x0003 */
954 ret_val = phy->ops.write_reg(hw, 29, 0x0003);
958 /* Set PHY page 0, register 30 to 0x0000 */
959 ret_val = phy->ops.write_reg(hw, 30, 0x0000);
964 /* Commit the changes. */
965 ret_val = phy->ops.commit(hw);
967 DEBUGOUT("Error committing the PHY changes\n");
971 if (phy->type == e1000_phy_82578) {
972 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
977 /* 82578 PHY - set the downshift count to 1x. */
978 phy_data |= I82578_EPSCR_DOWNSHIFT_ENABLE;
979 phy_data &= ~I82578_EPSCR_DOWNSHIFT_COUNTER_MASK;
980 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
991 * e1000_copper_link_setup_igp - Setup igp PHY's for copper link
992 * @hw: pointer to the HW structure
994 * Sets up LPLU, MDI/MDI-X, polarity, Smartspeed and Master/Slave config for
997 s32 e1000_copper_link_setup_igp(struct e1000_hw *hw)
999 struct e1000_phy_info *phy = &hw->phy;
1003 DEBUGFUNC("e1000_copper_link_setup_igp");
1005 if (phy->reset_disable) {
1006 ret_val = E1000_SUCCESS;
1010 ret_val = hw->phy.ops.reset(hw);
1012 DEBUGOUT("Error resetting the PHY.\n");
1017 * Wait 100ms for MAC to configure PHY from NVM settings, to avoid
1018 * timeout issues when LFS is enabled.
1023 * The NVM settings will configure LPLU in D3 for
1026 if (phy->type == e1000_phy_igp) {
1027 /* disable lplu d3 during driver init */
1028 ret_val = hw->phy.ops.set_d3_lplu_state(hw, FALSE);
1030 DEBUGOUT("Error Disabling LPLU D3\n");
1035 /* disable lplu d0 during driver init */
1036 if (hw->phy.ops.set_d0_lplu_state) {
1037 ret_val = hw->phy.ops.set_d0_lplu_state(hw, FALSE);
1039 DEBUGOUT("Error Disabling LPLU D0\n");
1043 /* Configure mdi-mdix settings */
1044 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CTRL, &data);
1048 data &= ~IGP01E1000_PSCR_AUTO_MDIX;
1050 switch (phy->mdix) {
1052 data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
1055 data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
1059 data |= IGP01E1000_PSCR_AUTO_MDIX;
1062 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CTRL, data);
1066 /* set auto-master slave resolution settings */
1067 if (hw->mac.autoneg) {
1069 * when autonegotiation advertisement is only 1000Mbps then we
1070 * should disable SmartSpeed and enable Auto MasterSlave
1071 * resolution as hardware default.
1073 if (phy->autoneg_advertised == ADVERTISE_1000_FULL) {
1074 /* Disable SmartSpeed */
1075 ret_val = phy->ops.read_reg(hw,
1076 IGP01E1000_PHY_PORT_CONFIG,
1081 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1082 ret_val = phy->ops.write_reg(hw,
1083 IGP01E1000_PHY_PORT_CONFIG,
1088 /* Set auto Master/Slave resolution process */
1089 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, &data);
1093 data &= ~CR_1000T_MS_ENABLE;
1094 ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL, data);
1099 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, &data);
1103 /* load defaults for future use */
1104 phy->original_ms_type = (data & CR_1000T_MS_ENABLE) ?
1105 ((data & CR_1000T_MS_VALUE) ?
1106 e1000_ms_force_master :
1107 e1000_ms_force_slave) :
1110 switch (phy->ms_type) {
1111 case e1000_ms_force_master:
1112 data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
1114 case e1000_ms_force_slave:
1115 data |= CR_1000T_MS_ENABLE;
1116 data &= ~(CR_1000T_MS_VALUE);
1119 data &= ~CR_1000T_MS_ENABLE;
1123 ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL, data);
1133 * e1000_copper_link_autoneg - Setup/Enable autoneg for copper link
1134 * @hw: pointer to the HW structure
1136 * Performs initial bounds checking on autoneg advertisement parameter, then
1137 * configure to advertise the full capability. Setup the PHY to autoneg
1138 * and restart the negotiation process between the link partner. If
1139 * autoneg_wait_to_complete, then wait for autoneg to complete before exiting.
1141 s32 e1000_copper_link_autoneg(struct e1000_hw *hw)
1143 struct e1000_phy_info *phy = &hw->phy;
1147 DEBUGFUNC("e1000_copper_link_autoneg");
1150 * Perform some bounds checking on the autoneg advertisement
1153 phy->autoneg_advertised &= phy->autoneg_mask;
1156 * If autoneg_advertised is zero, we assume it was not defaulted
1157 * by the calling code so we set to advertise full capability.
1159 if (phy->autoneg_advertised == 0)
1160 phy->autoneg_advertised = phy->autoneg_mask;
1162 DEBUGOUT("Reconfiguring auto-neg advertisement params\n");
1163 ret_val = e1000_phy_setup_autoneg(hw);
1165 DEBUGOUT("Error Setting up Auto-Negotiation\n");
1168 DEBUGOUT("Restarting Auto-Neg\n");
1171 * Restart auto-negotiation by setting the Auto Neg Enable bit and
1172 * the Auto Neg Restart bit in the PHY control register.
1174 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_ctrl);
1178 phy_ctrl |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
1179 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_ctrl);
1184 * Does the user want to wait for Auto-Neg to complete here, or
1185 * check at a later time (for example, callback routine).
1187 if (phy->autoneg_wait_to_complete) {
1188 ret_val = hw->mac.ops.wait_autoneg(hw);
1190 DEBUGOUT("Error while waiting for "
1191 "autoneg to complete\n");
1196 hw->mac.get_link_status = TRUE;
1203 * e1000_phy_setup_autoneg - Configure PHY for auto-negotiation
1204 * @hw: pointer to the HW structure
1206 * Reads the MII auto-neg advertisement register and/or the 1000T control
1207 * register and if the PHY is already setup for auto-negotiation, then
1208 * return successful. Otherwise, setup advertisement and flow control to
1209 * the appropriate values for the wanted auto-negotiation.
1211 s32 e1000_phy_setup_autoneg(struct e1000_hw *hw)
1213 struct e1000_phy_info *phy = &hw->phy;
1215 u16 mii_autoneg_adv_reg;
1216 u16 mii_1000t_ctrl_reg = 0;
1218 DEBUGFUNC("e1000_phy_setup_autoneg");
1220 phy->autoneg_advertised &= phy->autoneg_mask;
1222 /* Read the MII Auto-Neg Advertisement Register (Address 4). */
1223 ret_val = phy->ops.read_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);
1227 if (phy->autoneg_mask & ADVERTISE_1000_FULL) {
1228 /* Read the MII 1000Base-T Control Register (Address 9). */
1229 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL,
1230 &mii_1000t_ctrl_reg);
1236 * Need to parse both autoneg_advertised and fc and set up
1237 * the appropriate PHY registers. First we will parse for
1238 * autoneg_advertised software override. Since we can advertise
1239 * a plethora of combinations, we need to check each bit
1244 * First we clear all the 10/100 mb speed bits in the Auto-Neg
1245 * Advertisement Register (Address 4) and the 1000 mb speed bits in
1246 * the 1000Base-T Control Register (Address 9).
1248 mii_autoneg_adv_reg &= ~(NWAY_AR_100TX_FD_CAPS |
1249 NWAY_AR_100TX_HD_CAPS |
1250 NWAY_AR_10T_FD_CAPS |
1251 NWAY_AR_10T_HD_CAPS);
1252 mii_1000t_ctrl_reg &= ~(CR_1000T_HD_CAPS | CR_1000T_FD_CAPS);
1254 DEBUGOUT1("autoneg_advertised %x\n", phy->autoneg_advertised);
1256 /* Do we want to advertise 10 Mb Half Duplex? */
1257 if (phy->autoneg_advertised & ADVERTISE_10_HALF) {
1258 DEBUGOUT("Advertise 10mb Half duplex\n");
1259 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
1262 /* Do we want to advertise 10 Mb Full Duplex? */
1263 if (phy->autoneg_advertised & ADVERTISE_10_FULL) {
1264 DEBUGOUT("Advertise 10mb Full duplex\n");
1265 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
1268 /* Do we want to advertise 100 Mb Half Duplex? */
1269 if (phy->autoneg_advertised & ADVERTISE_100_HALF) {
1270 DEBUGOUT("Advertise 100mb Half duplex\n");
1271 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
1274 /* Do we want to advertise 100 Mb Full Duplex? */
1275 if (phy->autoneg_advertised & ADVERTISE_100_FULL) {
1276 DEBUGOUT("Advertise 100mb Full duplex\n");
1277 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
1280 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
1281 if (phy->autoneg_advertised & ADVERTISE_1000_HALF)
1282 DEBUGOUT("Advertise 1000mb Half duplex request denied!\n");
1284 /* Do we want to advertise 1000 Mb Full Duplex? */
1285 if (phy->autoneg_advertised & ADVERTISE_1000_FULL) {
1286 DEBUGOUT("Advertise 1000mb Full duplex\n");
1287 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
1291 * Check for a software override of the flow control settings, and
1292 * setup the PHY advertisement registers accordingly. If
1293 * auto-negotiation is enabled, then software will have to set the
1294 * "PAUSE" bits to the correct value in the Auto-Negotiation
1295 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-
1298 * The possible values of the "fc" parameter are:
1299 * 0: Flow control is completely disabled
1300 * 1: Rx flow control is enabled (we can receive pause frames
1301 * but not send pause frames).
1302 * 2: Tx flow control is enabled (we can send pause frames
1303 * but we do not support receiving pause frames).
1304 * 3: Both Rx and Tx flow control (symmetric) are enabled.
1305 * other: No software override. The flow control configuration
1306 * in the EEPROM is used.
1308 switch (hw->fc.current_mode) {
1311 * Flow control (Rx & Tx) is completely disabled by a
1312 * software over-ride.
1314 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1316 case e1000_fc_rx_pause:
1318 * Rx Flow control is enabled, and Tx Flow control is
1319 * disabled, by a software over-ride.
1321 * Since there really isn't a way to advertise that we are
1322 * capable of Rx Pause ONLY, we will advertise that we
1323 * support both symmetric and asymmetric Rx PAUSE. Later
1324 * (in e1000_config_fc_after_link_up) we will disable the
1325 * hw's ability to send PAUSE frames.
1327 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1329 case e1000_fc_tx_pause:
1331 * Tx Flow control is enabled, and Rx Flow control is
1332 * disabled, by a software over-ride.
1334 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
1335 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
1339 * Flow control (both Rx and Tx) is enabled by a software
1342 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1345 DEBUGOUT("Flow control param set incorrectly\n");
1346 ret_val = -E1000_ERR_CONFIG;
1350 ret_val = phy->ops.write_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);
1354 DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
1356 if (phy->autoneg_mask & ADVERTISE_1000_FULL) {
1357 ret_val = phy->ops.write_reg(hw,
1359 mii_1000t_ctrl_reg);
1369 * e1000_setup_copper_link_generic - Configure copper link settings
1370 * @hw: pointer to the HW structure
1372 * Calls the appropriate function to configure the link for auto-neg or forced
1373 * speed and duplex. Then we check for link, once link is established calls
1374 * to configure collision distance and flow control are called. If link is
1375 * not established, we return -E1000_ERR_PHY (-2).
1377 s32 e1000_setup_copper_link_generic(struct e1000_hw *hw)
1382 DEBUGFUNC("e1000_setup_copper_link_generic");
1384 if (hw->mac.autoneg) {
1386 * Setup autoneg and flow control advertisement and perform
1389 ret_val = e1000_copper_link_autoneg(hw);
1394 * PHY will be set to 10H, 10F, 100H or 100F
1395 * depending on user settings.
1397 DEBUGOUT("Forcing Speed and Duplex\n");
1398 ret_val = hw->phy.ops.force_speed_duplex(hw);
1400 DEBUGOUT("Error Forcing Speed and Duplex\n");
1406 * Check link status. Wait up to 100 microseconds for link to become
1409 ret_val = e1000_phy_has_link_generic(hw,
1410 COPPER_LINK_UP_LIMIT,
1417 DEBUGOUT("Valid link established!!!\n");
1418 e1000_config_collision_dist_generic(hw);
1419 ret_val = e1000_config_fc_after_link_up_generic(hw);
1421 DEBUGOUT("Unable to establish link!!!\n");
1429 * e1000_phy_force_speed_duplex_igp - Force speed/duplex for igp PHY
1430 * @hw: pointer to the HW structure
1432 * Calls the PHY setup function to force speed and duplex. Clears the
1433 * auto-crossover to force MDI manually. Waits for link and returns
1434 * successful if link up is successful, else -E1000_ERR_PHY (-2).
1436 s32 e1000_phy_force_speed_duplex_igp(struct e1000_hw *hw)
1438 struct e1000_phy_info *phy = &hw->phy;
1443 DEBUGFUNC("e1000_phy_force_speed_duplex_igp");
1445 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data);
1449 e1000_phy_force_speed_duplex_setup(hw, &phy_data);
1451 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data);
1456 * Clear Auto-Crossover to force MDI manually. IGP requires MDI
1457 * forced whenever speed and duplex are forced.
1459 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
1463 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
1464 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
1466 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
1470 DEBUGOUT1("IGP PSCR: %X\n", phy_data);
1474 if (phy->autoneg_wait_to_complete) {
1475 DEBUGOUT("Waiting for forced speed/duplex link on IGP phy.\n");
1477 ret_val = e1000_phy_has_link_generic(hw,
1485 DEBUGOUT("Link taking longer than expected.\n");
1488 ret_val = e1000_phy_has_link_generic(hw,
1501 * e1000_phy_force_speed_duplex_m88 - Force speed/duplex for m88 PHY
1502 * @hw: pointer to the HW structure
1504 * Calls the PHY setup function to force speed and duplex. Clears the
1505 * auto-crossover to force MDI manually. Resets the PHY to commit the
1506 * changes. If time expires while waiting for link up, we reset the DSP.
1507 * After reset, TX_CLK and CRS on Tx must be set. Return successful upon
1508 * successful completion, else return corresponding error code.
1510 s32 e1000_phy_force_speed_duplex_m88(struct e1000_hw *hw)
1512 struct e1000_phy_info *phy = &hw->phy;
1517 DEBUGFUNC("e1000_phy_force_speed_duplex_m88");
1520 * Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI
1521 * forced whenever speed and duplex are forced.
1523 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1527 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1528 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1532 DEBUGOUT1("M88E1000 PSCR: %X\n", phy_data);
1534 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data);
1538 e1000_phy_force_speed_duplex_setup(hw, &phy_data);
1540 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data);
1544 /* Reset the phy to commit changes. */
1545 ret_val = hw->phy.ops.commit(hw);
1549 if (phy->autoneg_wait_to_complete) {
1550 DEBUGOUT("Waiting for forced speed/duplex link on M88 phy.\n");
1552 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1558 if (hw->phy.type != e1000_phy_m88) {
1559 DEBUGOUT("Link taking longer than expected.\n");
1562 * We didn't get link.
1563 * Reset the DSP and cross our fingers.
1565 ret_val = phy->ops.write_reg(hw,
1566 M88E1000_PHY_PAGE_SELECT,
1570 ret_val = e1000_phy_reset_dsp_generic(hw);
1577 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1583 if (hw->phy.type != e1000_phy_m88)
1586 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
1591 * Resetting the phy means we need to re-force TX_CLK in the
1592 * Extended PHY Specific Control Register to 25MHz clock from
1593 * the reset value of 2.5MHz.
1595 phy_data |= M88E1000_EPSCR_TX_CLK_25;
1596 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
1601 * In addition, we must re-enable CRS on Tx for both half and full
1604 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1608 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
1609 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1616 * e1000_phy_force_speed_duplex_ife - Force PHY speed & duplex
1617 * @hw: pointer to the HW structure
1619 * Forces the speed and duplex settings of the PHY.
1620 * This is a function pointer entry point only called by
1621 * PHY setup routines.
1623 s32 e1000_phy_force_speed_duplex_ife(struct e1000_hw *hw)
1625 struct e1000_phy_info *phy = &hw->phy;
1630 DEBUGFUNC("e1000_phy_force_speed_duplex_ife");
1632 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &data);
1636 e1000_phy_force_speed_duplex_setup(hw, &data);
1638 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, data);
1642 /* Disable MDI-X support for 10/100 */
1643 ret_val = phy->ops.read_reg(hw, IFE_PHY_MDIX_CONTROL, &data);
1647 data &= ~IFE_PMC_AUTO_MDIX;
1648 data &= ~IFE_PMC_FORCE_MDIX;
1650 ret_val = phy->ops.write_reg(hw, IFE_PHY_MDIX_CONTROL, data);
1654 DEBUGOUT1("IFE PMC: %X\n", data);
1658 if (phy->autoneg_wait_to_complete) {
1659 DEBUGOUT("Waiting for forced speed/duplex link on IFE phy.\n");
1661 ret_val = e1000_phy_has_link_generic(hw,
1669 DEBUGOUT("Link taking longer than expected.\n");
1672 ret_val = e1000_phy_has_link_generic(hw,
1685 * e1000_phy_force_speed_duplex_setup - Configure forced PHY speed/duplex
1686 * @hw: pointer to the HW structure
1687 * @phy_ctrl: pointer to current value of PHY_CONTROL
1689 * Forces speed and duplex on the PHY by doing the following: disable flow
1690 * control, force speed/duplex on the MAC, disable auto speed detection,
1691 * disable auto-negotiation, configure duplex, configure speed, configure
1692 * the collision distance, write configuration to CTRL register. The
1693 * caller must write to the PHY_CONTROL register for these settings to
1696 void e1000_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl)
1698 struct e1000_mac_info *mac = &hw->mac;
1701 DEBUGFUNC("e1000_phy_force_speed_duplex_setup");
1703 /* Turn off flow control when forcing speed/duplex */
1704 hw->fc.current_mode = e1000_fc_none;
1706 /* Force speed/duplex on the mac */
1707 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1708 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1709 ctrl &= ~E1000_CTRL_SPD_SEL;
1711 /* Disable Auto Speed Detection */
1712 ctrl &= ~E1000_CTRL_ASDE;
1714 /* Disable autoneg on the phy */
1715 *phy_ctrl &= ~MII_CR_AUTO_NEG_EN;
1717 /* Forcing Full or Half Duplex? */
1718 if (mac->forced_speed_duplex & E1000_ALL_HALF_DUPLEX) {
1719 ctrl &= ~E1000_CTRL_FD;
1720 *phy_ctrl &= ~MII_CR_FULL_DUPLEX;
1721 DEBUGOUT("Half Duplex\n");
1723 ctrl |= E1000_CTRL_FD;
1724 *phy_ctrl |= MII_CR_FULL_DUPLEX;
1725 DEBUGOUT("Full Duplex\n");
1728 /* Forcing 10mb or 100mb? */
1729 if (mac->forced_speed_duplex & E1000_ALL_100_SPEED) {
1730 ctrl |= E1000_CTRL_SPD_100;
1731 *phy_ctrl |= MII_CR_SPEED_100;
1732 *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10);
1733 DEBUGOUT("Forcing 100mb\n");
1735 ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
1736 *phy_ctrl |= MII_CR_SPEED_10;
1737 *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100);
1738 DEBUGOUT("Forcing 10mb\n");
1741 e1000_config_collision_dist_generic(hw);
1743 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1747 * e1000_set_d3_lplu_state_generic - Sets low power link up state for D3
1748 * @hw: pointer to the HW structure
1749 * @active: boolean used to enable/disable lplu
1751 * Success returns 0, Failure returns 1
1753 * The low power link up (lplu) state is set to the power management level D3
1754 * and SmartSpeed is disabled when active is TRUE, else clear lplu for D3
1755 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU
1756 * is used during Dx states where the power conservation is most important.
1757 * During driver activity, SmartSpeed should be enabled so performance is
1760 s32 e1000_set_d3_lplu_state_generic(struct e1000_hw *hw, bool active)
1762 struct e1000_phy_info *phy = &hw->phy;
1763 s32 ret_val = E1000_SUCCESS;
1766 DEBUGFUNC("e1000_set_d3_lplu_state_generic");
1768 if (!(hw->phy.ops.read_reg))
1771 ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);
1776 data &= ~IGP02E1000_PM_D3_LPLU;
1777 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
1782 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
1783 * during Dx states where the power conservation is most
1784 * important. During driver activity we should enable
1785 * SmartSpeed, so performance is maintained.
1787 if (phy->smart_speed == e1000_smart_speed_on) {
1788 ret_val = phy->ops.read_reg(hw,
1789 IGP01E1000_PHY_PORT_CONFIG,
1794 data |= IGP01E1000_PSCFR_SMART_SPEED;
1795 ret_val = phy->ops.write_reg(hw,
1796 IGP01E1000_PHY_PORT_CONFIG,
1800 } else if (phy->smart_speed == e1000_smart_speed_off) {
1801 ret_val = phy->ops.read_reg(hw,
1802 IGP01E1000_PHY_PORT_CONFIG,
1807 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1808 ret_val = phy->ops.write_reg(hw,
1809 IGP01E1000_PHY_PORT_CONFIG,
1814 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
1815 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
1816 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
1817 data |= IGP02E1000_PM_D3_LPLU;
1818 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
1823 /* When LPLU is enabled, we should disable SmartSpeed */
1824 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
1829 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1830 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
1839 * e1000_check_downshift_generic - Checks whether a downshift in speed occurred
1840 * @hw: pointer to the HW structure
1842 * Success returns 0, Failure returns 1
1844 * A downshift is detected by querying the PHY link health.
1846 s32 e1000_check_downshift_generic(struct e1000_hw *hw)
1848 struct e1000_phy_info *phy = &hw->phy;
1850 u16 phy_data, offset, mask;
1852 DEBUGFUNC("e1000_check_downshift_generic");
1854 switch (phy->type) {
1856 case e1000_phy_gg82563:
1858 case e1000_phy_82578:
1859 offset = M88E1000_PHY_SPEC_STATUS;
1860 mask = M88E1000_PSSR_DOWNSHIFT;
1863 case e1000_phy_igp_2:
1864 case e1000_phy_igp_3:
1865 offset = IGP01E1000_PHY_LINK_HEALTH;
1866 mask = IGP01E1000_PLHR_SS_DOWNGRADE;
1869 /* speed downshift not supported */
1870 phy->speed_downgraded = FALSE;
1871 ret_val = E1000_SUCCESS;
1875 ret_val = phy->ops.read_reg(hw, offset, &phy_data);
1878 phy->speed_downgraded = (phy_data & mask) ? TRUE : FALSE;
1885 * e1000_check_polarity_m88 - Checks the polarity.
1886 * @hw: pointer to the HW structure
1888 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
1890 * Polarity is determined based on the PHY specific status register.
1892 s32 e1000_check_polarity_m88(struct e1000_hw *hw)
1894 struct e1000_phy_info *phy = &hw->phy;
1898 DEBUGFUNC("e1000_check_polarity_m88");
1900 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &data);
1903 phy->cable_polarity = (data & M88E1000_PSSR_REV_POLARITY)
1904 ? e1000_rev_polarity_reversed
1905 : e1000_rev_polarity_normal;
1911 * e1000_check_polarity_igp - Checks the polarity.
1912 * @hw: pointer to the HW structure
1914 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
1916 * Polarity is determined based on the PHY port status register, and the
1917 * current speed (since there is no polarity at 100Mbps).
1919 s32 e1000_check_polarity_igp(struct e1000_hw *hw)
1921 struct e1000_phy_info *phy = &hw->phy;
1923 u16 data, offset, mask;
1925 DEBUGFUNC("e1000_check_polarity_igp");
1928 * Polarity is determined based on the speed of
1931 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data);
1935 if ((data & IGP01E1000_PSSR_SPEED_MASK) ==
1936 IGP01E1000_PSSR_SPEED_1000MBPS) {
1937 offset = IGP01E1000_PHY_PCS_INIT_REG;
1938 mask = IGP01E1000_PHY_POLARITY_MASK;
1941 * This really only applies to 10Mbps since
1942 * there is no polarity for 100Mbps (always 0).
1944 offset = IGP01E1000_PHY_PORT_STATUS;
1945 mask = IGP01E1000_PSSR_POLARITY_REVERSED;
1948 ret_val = phy->ops.read_reg(hw, offset, &data);
1951 phy->cable_polarity = (data & mask)
1952 ? e1000_rev_polarity_reversed
1953 : e1000_rev_polarity_normal;
1960 * e1000_check_polarity_ife - Check cable polarity for IFE PHY
1961 * @hw: pointer to the HW structure
1963 * Polarity is determined on the polarity reversal feature being enabled.
1965 s32 e1000_check_polarity_ife(struct e1000_hw *hw)
1967 struct e1000_phy_info *phy = &hw->phy;
1969 u16 phy_data, offset, mask;
1971 DEBUGFUNC("e1000_check_polarity_ife");
1974 * Polarity is determined based on the reversal feature being enabled.
1976 if (phy->polarity_correction) {
1977 offset = IFE_PHY_EXTENDED_STATUS_CONTROL;
1978 mask = IFE_PESC_POLARITY_REVERSED;
1980 offset = IFE_PHY_SPECIAL_CONTROL;
1981 mask = IFE_PSC_FORCE_POLARITY;
1984 ret_val = phy->ops.read_reg(hw, offset, &phy_data);
1987 phy->cable_polarity = (phy_data & mask)
1988 ? e1000_rev_polarity_reversed
1989 : e1000_rev_polarity_normal;
1995 * e1000_wait_autoneg_generic - Wait for auto-neg completion
1996 * @hw: pointer to the HW structure
1998 * Waits for auto-negotiation to complete or for the auto-negotiation time
1999 * limit to expire, which ever happens first.
2001 s32 e1000_wait_autoneg_generic(struct e1000_hw *hw)
2003 s32 ret_val = E1000_SUCCESS;
2006 DEBUGFUNC("e1000_wait_autoneg_generic");
2008 if (!(hw->phy.ops.read_reg))
2009 return E1000_SUCCESS;
2011 /* Break after autoneg completes or PHY_AUTO_NEG_LIMIT expires. */
2012 for (i = PHY_AUTO_NEG_LIMIT; i > 0; i--) {
2013 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
2016 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
2019 if (phy_status & MII_SR_AUTONEG_COMPLETE)
2025 * PHY_AUTO_NEG_TIME expiration doesn't guarantee auto-negotiation
2032 * e1000_phy_has_link_generic - Polls PHY for link
2033 * @hw: pointer to the HW structure
2034 * @iterations: number of times to poll for link
2035 * @usec_interval: delay between polling attempts
2036 * @success: pointer to whether polling was successful or not
2038 * Polls the PHY status register for link, 'iterations' number of times.
2040 s32 e1000_phy_has_link_generic(struct e1000_hw *hw, u32 iterations,
2041 u32 usec_interval, bool *success)
2043 s32 ret_val = E1000_SUCCESS;
2046 DEBUGFUNC("e1000_phy_has_link_generic");
2048 if (!(hw->phy.ops.read_reg))
2049 return E1000_SUCCESS;
2051 for (i = 0; i < iterations; i++) {
2053 * Some PHYs require the PHY_STATUS register to be read
2054 * twice due to the link bit being sticky. No harm doing
2055 * it across the board.
2057 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
2060 * If the first read fails, another entity may have
2061 * ownership of the resources, wait and try again to
2062 * see if they have relinquished the resources yet.
2064 usec_delay(usec_interval);
2065 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
2068 if (phy_status & MII_SR_LINK_STATUS)
2070 if (usec_interval >= 1000)
2071 msec_delay_irq(usec_interval/1000);
2073 usec_delay(usec_interval);
2076 *success = (i < iterations) ? TRUE : FALSE;
2082 * e1000_get_cable_length_m88 - Determine cable length for m88 PHY
2083 * @hw: pointer to the HW structure
2085 * Reads the PHY specific status register to retrieve the cable length
2086 * information. The cable length is determined by averaging the minimum and
2087 * maximum values to get the "average" cable length. The m88 PHY has four
2088 * possible cable length values, which are:
2089 * Register Value Cable Length
2093 * 3 110 - 140 meters
2096 s32 e1000_get_cable_length_m88(struct e1000_hw *hw)
2098 struct e1000_phy_info *phy = &hw->phy;
2100 u16 phy_data, index;
2102 DEBUGFUNC("e1000_get_cable_length_m88");
2104 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
2108 index = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
2109 M88E1000_PSSR_CABLE_LENGTH_SHIFT;
2110 if (index >= M88E1000_CABLE_LENGTH_TABLE_SIZE - 1) {
2111 ret_val = -E1000_ERR_PHY;
2115 phy->min_cable_length = e1000_m88_cable_length_table[index];
2116 phy->max_cable_length = e1000_m88_cable_length_table[index + 1];
2118 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
2125 * e1000_get_cable_length_igp_2 - Determine cable length for igp2 PHY
2126 * @hw: pointer to the HW structure
2128 * The automatic gain control (agc) normalizes the amplitude of the
2129 * received signal, adjusting for the attenuation produced by the
2130 * cable. By reading the AGC registers, which represent the
2131 * combination of coarse and fine gain value, the value can be put
2132 * into a lookup table to obtain the approximate cable length
2135 s32 e1000_get_cable_length_igp_2(struct e1000_hw *hw)
2137 struct e1000_phy_info *phy = &hw->phy;
2138 s32 ret_val = E1000_SUCCESS;
2139 u16 phy_data, i, agc_value = 0;
2140 u16 cur_agc_index, max_agc_index = 0;
2141 u16 min_agc_index = IGP02E1000_CABLE_LENGTH_TABLE_SIZE - 1;
2142 u16 agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] =
2143 {IGP02E1000_PHY_AGC_A,
2144 IGP02E1000_PHY_AGC_B,
2145 IGP02E1000_PHY_AGC_C,
2146 IGP02E1000_PHY_AGC_D};
2148 DEBUGFUNC("e1000_get_cable_length_igp_2");
2150 /* Read the AGC registers for all channels */
2151 for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) {
2152 ret_val = phy->ops.read_reg(hw, agc_reg_array[i], &phy_data);
2157 * Getting bits 15:9, which represent the combination of
2158 * coarse and fine gain values. The result is a number
2159 * that can be put into the lookup table to obtain the
2160 * approximate cable length.
2162 cur_agc_index = (phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) &
2163 IGP02E1000_AGC_LENGTH_MASK;
2165 /* Array index bound check. */
2166 if ((cur_agc_index >= IGP02E1000_CABLE_LENGTH_TABLE_SIZE) ||
2167 (cur_agc_index == 0)) {
2168 ret_val = -E1000_ERR_PHY;
2172 /* Remove min & max AGC values from calculation. */
2173 if (e1000_igp_2_cable_length_table[min_agc_index] >
2174 e1000_igp_2_cable_length_table[cur_agc_index])
2175 min_agc_index = cur_agc_index;
2176 if (e1000_igp_2_cable_length_table[max_agc_index] <
2177 e1000_igp_2_cable_length_table[cur_agc_index])
2178 max_agc_index = cur_agc_index;
2180 agc_value += e1000_igp_2_cable_length_table[cur_agc_index];
2183 agc_value -= (e1000_igp_2_cable_length_table[min_agc_index] +
2184 e1000_igp_2_cable_length_table[max_agc_index]);
2185 agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2);
2187 /* Calculate cable length with the error range of +/- 10 meters. */
2188 phy->min_cable_length = ((agc_value - IGP02E1000_AGC_RANGE) > 0) ?
2189 (agc_value - IGP02E1000_AGC_RANGE) : 0;
2190 phy->max_cable_length = agc_value + IGP02E1000_AGC_RANGE;
2192 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
2199 * e1000_get_phy_info_m88 - Retrieve PHY information
2200 * @hw: pointer to the HW structure
2202 * Valid for only copper links. Read the PHY status register (sticky read)
2203 * to verify that link is up. Read the PHY special control register to
2204 * determine the polarity and 10base-T extended distance. Read the PHY
2205 * special status register to determine MDI/MDIx and current speed. If
2206 * speed is 1000, then determine cable length, local and remote receiver.
2208 s32 e1000_get_phy_info_m88(struct e1000_hw *hw)
2210 struct e1000_phy_info *phy = &hw->phy;
2215 DEBUGFUNC("e1000_get_phy_info_m88");
2217 if (phy->media_type != e1000_media_type_copper) {
2218 DEBUGOUT("Phy info is only valid for copper media\n");
2219 ret_val = -E1000_ERR_CONFIG;
2223 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
2228 DEBUGOUT("Phy info is only valid if link is up\n");
2229 ret_val = -E1000_ERR_CONFIG;
2233 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
2237 phy->polarity_correction = (phy_data & M88E1000_PSCR_POLARITY_REVERSAL)
2240 ret_val = e1000_check_polarity_m88(hw);
2244 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
2248 phy->is_mdix = (phy_data & M88E1000_PSSR_MDIX) ? TRUE : FALSE;
2250 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) {
2251 ret_val = hw->phy.ops.get_cable_length(hw);
2255 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &phy_data);
2259 phy->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS)
2260 ? e1000_1000t_rx_status_ok
2261 : e1000_1000t_rx_status_not_ok;
2263 phy->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS)
2264 ? e1000_1000t_rx_status_ok
2265 : e1000_1000t_rx_status_not_ok;
2267 /* Set values to "undefined" */
2268 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
2269 phy->local_rx = e1000_1000t_rx_status_undefined;
2270 phy->remote_rx = e1000_1000t_rx_status_undefined;
2278 * e1000_get_phy_info_igp - Retrieve igp PHY information
2279 * @hw: pointer to the HW structure
2281 * Read PHY status to determine if link is up. If link is up, then
2282 * set/determine 10base-T extended distance and polarity correction. Read
2283 * PHY port status to determine MDI/MDIx and speed. Based on the speed,
2284 * determine on the cable length, local and remote receiver.
2286 s32 e1000_get_phy_info_igp(struct e1000_hw *hw)
2288 struct e1000_phy_info *phy = &hw->phy;
2293 DEBUGFUNC("e1000_get_phy_info_igp");
2295 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
2300 DEBUGOUT("Phy info is only valid if link is up\n");
2301 ret_val = -E1000_ERR_CONFIG;
2305 phy->polarity_correction = TRUE;
2307 ret_val = e1000_check_polarity_igp(hw);
2311 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data);
2315 phy->is_mdix = (data & IGP01E1000_PSSR_MDIX) ? TRUE : FALSE;
2317 if ((data & IGP01E1000_PSSR_SPEED_MASK) ==
2318 IGP01E1000_PSSR_SPEED_1000MBPS) {
2319 ret_val = phy->ops.get_cable_length(hw);
2323 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &data);
2327 phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS)
2328 ? e1000_1000t_rx_status_ok
2329 : e1000_1000t_rx_status_not_ok;
2331 phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS)
2332 ? e1000_1000t_rx_status_ok
2333 : e1000_1000t_rx_status_not_ok;
2335 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
2336 phy->local_rx = e1000_1000t_rx_status_undefined;
2337 phy->remote_rx = e1000_1000t_rx_status_undefined;
2345 * e1000_get_phy_info_ife - Retrieves various IFE PHY states
2346 * @hw: pointer to the HW structure
2348 * Populates "phy" structure with various feature states.
2350 s32 e1000_get_phy_info_ife(struct e1000_hw *hw)
2352 struct e1000_phy_info *phy = &hw->phy;
2357 DEBUGFUNC("e1000_get_phy_info_ife");
2359 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
2364 DEBUGOUT("Phy info is only valid if link is up\n");
2365 ret_val = -E1000_ERR_CONFIG;
2369 ret_val = phy->ops.read_reg(hw, IFE_PHY_SPECIAL_CONTROL, &data);
2372 phy->polarity_correction = (data & IFE_PSC_AUTO_POLARITY_DISABLE)
2375 if (phy->polarity_correction) {
2376 ret_val = e1000_check_polarity_ife(hw);
2380 /* Polarity is forced */
2381 phy->cable_polarity = (data & IFE_PSC_FORCE_POLARITY)
2382 ? e1000_rev_polarity_reversed
2383 : e1000_rev_polarity_normal;
2386 ret_val = phy->ops.read_reg(hw, IFE_PHY_MDIX_CONTROL, &data);
2390 phy->is_mdix = (data & IFE_PMC_MDIX_STATUS) ? TRUE : FALSE;
2392 /* The following parameters are undefined for 10/100 operation. */
2393 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
2394 phy->local_rx = e1000_1000t_rx_status_undefined;
2395 phy->remote_rx = e1000_1000t_rx_status_undefined;
2402 * e1000_phy_sw_reset_generic - PHY software reset
2403 * @hw: pointer to the HW structure
2405 * Does a software reset of the PHY by reading the PHY control register and
2406 * setting/write the control register reset bit to the PHY.
2408 s32 e1000_phy_sw_reset_generic(struct e1000_hw *hw)
2410 s32 ret_val = E1000_SUCCESS;
2413 DEBUGFUNC("e1000_phy_sw_reset_generic");
2415 if (!(hw->phy.ops.read_reg))
2418 ret_val = hw->phy.ops.read_reg(hw, PHY_CONTROL, &phy_ctrl);
2422 phy_ctrl |= MII_CR_RESET;
2423 ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL, phy_ctrl);
2434 * e1000_phy_hw_reset_generic - PHY hardware reset
2435 * @hw: pointer to the HW structure
2437 * Verify the reset block is not blocking us from resetting. Acquire
2438 * semaphore (if necessary) and read/set/write the device control reset
2439 * bit in the PHY. Wait the appropriate delay time for the device to
2440 * reset and release the semaphore (if necessary).
2442 s32 e1000_phy_hw_reset_generic(struct e1000_hw *hw)
2444 struct e1000_phy_info *phy = &hw->phy;
2445 s32 ret_val = E1000_SUCCESS;
2448 DEBUGFUNC("e1000_phy_hw_reset_generic");
2450 ret_val = phy->ops.check_reset_block(hw);
2452 ret_val = E1000_SUCCESS;
2456 ret_val = phy->ops.acquire(hw);
2460 ctrl = E1000_READ_REG(hw, E1000_CTRL);
2461 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_PHY_RST);
2462 E1000_WRITE_FLUSH(hw);
2464 usec_delay(phy->reset_delay_us);
2466 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
2467 E1000_WRITE_FLUSH(hw);
2471 phy->ops.release(hw);
2473 ret_val = phy->ops.get_cfg_done(hw);
2480 * e1000_get_cfg_done_generic - Generic configuration done
2481 * @hw: pointer to the HW structure
2483 * Generic function to wait 10 milli-seconds for configuration to complete
2484 * and return success.
2486 s32 e1000_get_cfg_done_generic(struct e1000_hw *hw)
2488 DEBUGFUNC("e1000_get_cfg_done_generic");
2492 return E1000_SUCCESS;
2496 * e1000_phy_init_script_igp3 - Inits the IGP3 PHY
2497 * @hw: pointer to the HW structure
2499 * Initializes a Intel Gigabit PHY3 when an EEPROM is not present.
2501 s32 e1000_phy_init_script_igp3(struct e1000_hw *hw)
2503 DEBUGOUT("Running IGP 3 PHY init script\n");
2505 /* PHY init IGP 3 */
2506 /* Enable rise/fall, 10-mode work in class-A */
2507 hw->phy.ops.write_reg(hw, 0x2F5B, 0x9018);
2508 /* Remove all caps from Replica path filter */
2509 hw->phy.ops.write_reg(hw, 0x2F52, 0x0000);
2510 /* Bias trimming for ADC, AFE and Driver (Default) */
2511 hw->phy.ops.write_reg(hw, 0x2FB1, 0x8B24);
2512 /* Increase Hybrid poly bias */
2513 hw->phy.ops.write_reg(hw, 0x2FB2, 0xF8F0);
2514 /* Add 4% to Tx amplitude in Gig mode */
2515 hw->phy.ops.write_reg(hw, 0x2010, 0x10B0);
2516 /* Disable trimming (TTT) */
2517 hw->phy.ops.write_reg(hw, 0x2011, 0x0000);
2518 /* Poly DC correction to 94.6% + 2% for all channels */
2519 hw->phy.ops.write_reg(hw, 0x20DD, 0x249A);
2520 /* ABS DC correction to 95.9% */
2521 hw->phy.ops.write_reg(hw, 0x20DE, 0x00D3);
2522 /* BG temp curve trim */
2523 hw->phy.ops.write_reg(hw, 0x28B4, 0x04CE);
2524 /* Increasing ADC OPAMP stage 1 currents to max */
2525 hw->phy.ops.write_reg(hw, 0x2F70, 0x29E4);
2526 /* Force 1000 ( required for enabling PHY regs configuration) */
2527 hw->phy.ops.write_reg(hw, 0x0000, 0x0140);
2528 /* Set upd_freq to 6 */
2529 hw->phy.ops.write_reg(hw, 0x1F30, 0x1606);
2531 hw->phy.ops.write_reg(hw, 0x1F31, 0xB814);
2532 /* Disable adaptive fixed FFE (Default) */
2533 hw->phy.ops.write_reg(hw, 0x1F35, 0x002A);
2534 /* Enable FFE hysteresis */
2535 hw->phy.ops.write_reg(hw, 0x1F3E, 0x0067);
2536 /* Fixed FFE for short cable lengths */
2537 hw->phy.ops.write_reg(hw, 0x1F54, 0x0065);
2538 /* Fixed FFE for medium cable lengths */
2539 hw->phy.ops.write_reg(hw, 0x1F55, 0x002A);
2540 /* Fixed FFE for long cable lengths */
2541 hw->phy.ops.write_reg(hw, 0x1F56, 0x002A);
2542 /* Enable Adaptive Clip Threshold */
2543 hw->phy.ops.write_reg(hw, 0x1F72, 0x3FB0);
2544 /* AHT reset limit to 1 */
2545 hw->phy.ops.write_reg(hw, 0x1F76, 0xC0FF);
2546 /* Set AHT master delay to 127 msec */
2547 hw->phy.ops.write_reg(hw, 0x1F77, 0x1DEC);
2548 /* Set scan bits for AHT */
2549 hw->phy.ops.write_reg(hw, 0x1F78, 0xF9EF);
2550 /* Set AHT Preset bits */
2551 hw->phy.ops.write_reg(hw, 0x1F79, 0x0210);
2552 /* Change integ_factor of channel A to 3 */
2553 hw->phy.ops.write_reg(hw, 0x1895, 0x0003);
2554 /* Change prop_factor of channels BCD to 8 */
2555 hw->phy.ops.write_reg(hw, 0x1796, 0x0008);
2556 /* Change cg_icount + enable integbp for channels BCD */
2557 hw->phy.ops.write_reg(hw, 0x1798, 0xD008);
2559 * Change cg_icount + enable integbp + change prop_factor_master
2560 * to 8 for channel A
2562 hw->phy.ops.write_reg(hw, 0x1898, 0xD918);
2563 /* Disable AHT in Slave mode on channel A */
2564 hw->phy.ops.write_reg(hw, 0x187A, 0x0800);
2566 * Enable LPLU and disable AN to 1000 in non-D0a states,
2569 hw->phy.ops.write_reg(hw, 0x0019, 0x008D);
2570 /* Enable restart AN on an1000_dis change */
2571 hw->phy.ops.write_reg(hw, 0x001B, 0x2080);
2572 /* Enable wh_fifo read clock in 10/100 modes */
2573 hw->phy.ops.write_reg(hw, 0x0014, 0x0045);
2574 /* Restart AN, Speed selection is 1000 */
2575 hw->phy.ops.write_reg(hw, 0x0000, 0x1340);
2577 return E1000_SUCCESS;
2581 * e1000_get_phy_type_from_id - Get PHY type from id
2582 * @phy_id: phy_id read from the phy
2584 * Returns the phy type from the id.
2586 enum e1000_phy_type e1000_get_phy_type_from_id(u32 phy_id)
2588 enum e1000_phy_type phy_type = e1000_phy_unknown;
2591 case M88E1000_I_PHY_ID:
2592 case M88E1000_E_PHY_ID:
2593 case M88E1111_I_PHY_ID:
2594 case M88E1011_I_PHY_ID:
2595 phy_type = e1000_phy_m88;
2597 case IGP01E1000_I_PHY_ID: /* IGP 1 & 2 share this */
2598 phy_type = e1000_phy_igp_2;
2600 case GG82563_E_PHY_ID:
2601 phy_type = e1000_phy_gg82563;
2603 case IGP03E1000_E_PHY_ID:
2604 phy_type = e1000_phy_igp_3;
2607 case IFE_PLUS_E_PHY_ID:
2608 case IFE_C_E_PHY_ID:
2609 phy_type = e1000_phy_ife;
2611 case BME1000_E_PHY_ID:
2612 case BME1000_E_PHY_ID_R2:
2613 phy_type = e1000_phy_bm;
2615 case I82578_E_PHY_ID:
2616 phy_type = e1000_phy_82578;
2618 case I82577_E_PHY_ID:
2619 phy_type = e1000_phy_82577;
2621 case I82580_I_PHY_ID:
2622 phy_type = e1000_phy_82580;
2625 phy_type = e1000_phy_unknown;
2632 * e1000_determine_phy_address - Determines PHY address.
2633 * @hw: pointer to the HW structure
2635 * This uses a trial and error method to loop through possible PHY
2636 * addresses. It tests each by reading the PHY ID registers and
2637 * checking for a match.
2639 s32 e1000_determine_phy_address(struct e1000_hw *hw)
2641 s32 ret_val = -E1000_ERR_PHY_TYPE;
2644 enum e1000_phy_type phy_type = e1000_phy_unknown;
2646 hw->phy.id = phy_type;
2648 for (phy_addr = 0; phy_addr < E1000_MAX_PHY_ADDR; phy_addr++) {
2649 hw->phy.addr = phy_addr;
2653 e1000_get_phy_id(hw);
2654 phy_type = e1000_get_phy_type_from_id(hw->phy.id);
2657 * If phy_type is valid, break - we found our
2660 if (phy_type != e1000_phy_unknown) {
2661 ret_val = E1000_SUCCESS;
2674 * e1000_get_phy_addr_for_bm_page - Retrieve PHY page address
2675 * @page: page to access
2677 * Returns the phy address for the page requested.
2679 static u32 e1000_get_phy_addr_for_bm_page(u32 page, u32 reg)
2683 if ((page >= 768) || (page == 0 && reg == 25) || (reg == 31))
2690 * e1000_write_phy_reg_bm - Write BM PHY register
2691 * @hw: pointer to the HW structure
2692 * @offset: register offset to write to
2693 * @data: data to write at register offset
2695 * Acquires semaphore, if necessary, then writes the data to PHY register
2696 * at the offset. Release any acquired semaphores before exiting.
2698 s32 e1000_write_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 data)
2701 u32 page_select = 0;
2702 u32 page = offset >> IGP_PAGE_SHIFT;
2705 DEBUGFUNC("e1000_write_phy_reg_bm");
2707 ret_val = hw->phy.ops.acquire(hw);
2711 /* Page 800 works differently than the rest so it has its own func */
2712 if (page == BM_WUC_PAGE) {
2713 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data,
2718 hw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset);
2720 if (offset > MAX_PHY_MULTI_PAGE_REG) {
2722 * Page select is register 31 for phy address 1 and 22 for
2723 * phy address 2 and 3. Page select is shifted only for
2726 if (hw->phy.addr == 1) {
2727 page_shift = IGP_PAGE_SHIFT;
2728 page_select = IGP01E1000_PHY_PAGE_SELECT;
2731 page_select = BM_PHY_PAGE_SELECT;
2734 /* Page is shifted left, PHY expects (page x 32) */
2735 ret_val = e1000_write_phy_reg_mdic(hw, page_select,
2736 (page << page_shift));
2741 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
2745 hw->phy.ops.release(hw);
2750 * e1000_read_phy_reg_bm - Read BM PHY register
2751 * @hw: pointer to the HW structure
2752 * @offset: register offset to be read
2753 * @data: pointer to the read data
2755 * Acquires semaphore, if necessary, then reads the PHY register at offset
2756 * and storing the retrieved information in data. Release any acquired
2757 * semaphores before exiting.
2759 s32 e1000_read_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 *data)
2762 u32 page_select = 0;
2763 u32 page = offset >> IGP_PAGE_SHIFT;
2766 DEBUGFUNC("e1000_read_phy_reg_bm");
2768 ret_val = hw->phy.ops.acquire(hw);
2772 /* Page 800 works differently than the rest so it has its own func */
2773 if (page == BM_WUC_PAGE) {
2774 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data,
2779 hw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset);
2781 if (offset > MAX_PHY_MULTI_PAGE_REG) {
2783 * Page select is register 31 for phy address 1 and 22 for
2784 * phy address 2 and 3. Page select is shifted only for
2787 if (hw->phy.addr == 1) {
2788 page_shift = IGP_PAGE_SHIFT;
2789 page_select = IGP01E1000_PHY_PAGE_SELECT;
2792 page_select = BM_PHY_PAGE_SELECT;
2795 /* Page is shifted left, PHY expects (page x 32) */
2796 ret_val = e1000_write_phy_reg_mdic(hw, page_select,
2797 (page << page_shift));
2802 ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
2805 hw->phy.ops.release(hw);
2810 * e1000_read_phy_reg_bm2 - Read BM PHY register
2811 * @hw: pointer to the HW structure
2812 * @offset: register offset to be read
2813 * @data: pointer to the read data
2815 * Acquires semaphore, if necessary, then reads the PHY register at offset
2816 * and storing the retrieved information in data. Release any acquired
2817 * semaphores before exiting.
2819 s32 e1000_read_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 *data)
2822 u16 page = (u16)(offset >> IGP_PAGE_SHIFT);
2824 DEBUGFUNC("e1000_write_phy_reg_bm2");
2826 ret_val = hw->phy.ops.acquire(hw);
2830 /* Page 800 works differently than the rest so it has its own func */
2831 if (page == BM_WUC_PAGE) {
2832 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data,
2839 if (offset > MAX_PHY_MULTI_PAGE_REG) {
2841 /* Page is shifted left, PHY expects (page x 32) */
2842 ret_val = e1000_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT,
2849 ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
2852 hw->phy.ops.release(hw);
2857 * e1000_write_phy_reg_bm2 - Write BM PHY register
2858 * @hw: pointer to the HW structure
2859 * @offset: register offset to write to
2860 * @data: data to write at register offset
2862 * Acquires semaphore, if necessary, then writes the data to PHY register
2863 * at the offset. Release any acquired semaphores before exiting.
2865 s32 e1000_write_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 data)
2868 u16 page = (u16)(offset >> IGP_PAGE_SHIFT);
2870 DEBUGFUNC("e1000_write_phy_reg_bm2");
2872 ret_val = hw->phy.ops.acquire(hw);
2876 /* Page 800 works differently than the rest so it has its own func */
2877 if (page == BM_WUC_PAGE) {
2878 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data,
2885 if (offset > MAX_PHY_MULTI_PAGE_REG) {
2886 /* Page is shifted left, PHY expects (page x 32) */
2887 ret_val = e1000_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT,
2894 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
2898 hw->phy.ops.release(hw);
2903 * e1000_access_phy_wakeup_reg_bm - Read BM PHY wakeup register
2904 * @hw: pointer to the HW structure
2905 * @offset: register offset to be read or written
2906 * @data: pointer to the data to read or write
2907 * @read: determines if operation is read or write
2909 * Acquires semaphore, if necessary, then reads the PHY register at offset
2910 * and storing the retrieved information in data. Release any acquired
2911 * semaphores before exiting. Note that procedure to read the wakeup
2912 * registers are different. It works as such:
2913 * 1) Set page 769, register 17, bit 2 = 1
2914 * 2) Set page to 800 for host (801 if we were manageability)
2915 * 3) Write the address using the address opcode (0x11)
2916 * 4) Read or write the data using the data opcode (0x12)
2917 * 5) Restore 769_17.2 to its original value
2919 * Assumes semaphore already acquired.
2921 static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset,
2922 u16 *data, bool read)
2925 u16 reg = BM_PHY_REG_NUM(offset);
2928 DEBUGFUNC("e1000_access_phy_wakeup_reg_bm");
2930 /* Gig must be disabled for MDIO accesses to page 800 */
2931 if ((hw->mac.type == e1000_pchlan) &&
2932 (!(E1000_READ_REG(hw, E1000_PHY_CTRL) & E1000_PHY_CTRL_GBE_DISABLE)))
2933 DEBUGOUT("Attempting to access page 800 while gig enabled.\n");
2935 /* All operations in this function are phy address 1 */
2939 e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT,
2940 (BM_WUC_ENABLE_PAGE << IGP_PAGE_SHIFT));
2942 ret_val = e1000_read_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, &phy_reg);
2944 DEBUGOUT("Could not read PHY page 769\n");
2948 /* First clear bit 4 to avoid a power state change */
2949 phy_reg &= ~(BM_WUC_HOST_WU_BIT);
2950 ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, phy_reg);
2952 DEBUGOUT("Could not clear PHY page 769 bit 4\n");
2956 /* Write bit 2 = 1, and clear bit 4 to 769_17 */
2957 ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG,
2958 phy_reg | BM_WUC_ENABLE_BIT);
2960 DEBUGOUT("Could not write PHY page 769 bit 2\n");
2964 /* Select page 800 */
2965 ret_val = e1000_write_phy_reg_mdic(hw,
2966 IGP01E1000_PHY_PAGE_SELECT,
2967 (BM_WUC_PAGE << IGP_PAGE_SHIFT));
2969 /* Write the page 800 offset value using opcode 0x11 */
2970 ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_ADDRESS_OPCODE, reg);
2972 DEBUGOUT("Could not write address opcode to page 800\n");
2977 /* Read the page 800 value using opcode 0x12 */
2978 ret_val = e1000_read_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE,
2981 /* Write the page 800 value using opcode 0x12 */
2982 ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE,
2987 DEBUGOUT("Could not access data value from page 800\n");
2992 * Restore 769_17.2 to its original value
2995 e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT,
2996 (BM_WUC_ENABLE_PAGE << IGP_PAGE_SHIFT));
2998 /* Clear 769_17.2 */
2999 ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, phy_reg);
3001 DEBUGOUT("Could not clear PHY page 769 bit 2\n");
3010 * e1000_power_up_phy_copper - Restore copper link in case of PHY power down
3011 * @hw: pointer to the HW structure
3013 * In the case of a PHY power down to save power, or to turn off link during a
3014 * driver unload, or wake on lan is not enabled, restore the link to previous
3017 void e1000_power_up_phy_copper(struct e1000_hw *hw)
3021 /* The PHY will retain its settings across a power down/up cycle */
3022 hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg);
3023 mii_reg &= ~MII_CR_POWER_DOWN;
3024 hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg);
3028 * e1000_power_down_phy_copper - Restore copper link in case of PHY power down
3029 * @hw: pointer to the HW structure
3031 * In the case of a PHY power down to save power, or to turn off link during a
3032 * driver unload, or wake on lan is not enabled, restore the link to previous
3035 void e1000_power_down_phy_copper(struct e1000_hw *hw)
3039 /* The PHY will retain its settings across a power down/up cycle */
3040 hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg);
3041 mii_reg |= MII_CR_POWER_DOWN;
3042 hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg);
3047 * __e1000_read_phy_reg_hv - Read HV PHY register
3048 * @hw: pointer to the HW structure
3049 * @offset: register offset to be read
3050 * @data: pointer to the read data
3051 * @locked: semaphore has already been acquired or not
3053 * Acquires semaphore, if necessary, then reads the PHY register at offset
3054 * and stores the retrieved information in data. Release any acquired
3055 * semaphore before exiting.
3057 static s32 __e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data,
3061 u16 page = BM_PHY_REG_PAGE(offset);
3062 u16 reg = BM_PHY_REG_NUM(offset);
3064 DEBUGFUNC("__e1000_read_phy_reg_hv");
3067 ret_val = hw->phy.ops.acquire(hw);
3072 /* Page 800 works differently than the rest so it has its own func */
3073 if (page == BM_WUC_PAGE) {
3074 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset,
3079 if (page > 0 && page < HV_INTC_FC_PAGE_START) {
3080 ret_val = e1000_access_phy_debug_regs_hv(hw, offset,
3085 hw->phy.addr = e1000_get_phy_addr_for_hv_page(page);
3087 if (page == HV_INTC_FC_PAGE_START)
3090 if (reg > MAX_PHY_MULTI_PAGE_REG) {
3091 u32 phy_addr = hw->phy.addr;
3095 /* Page is shifted left, PHY expects (page x 32) */
3096 ret_val = e1000_write_phy_reg_mdic(hw,
3097 IGP01E1000_PHY_PAGE_SELECT,
3098 (page << IGP_PAGE_SHIFT));
3099 hw->phy.addr = phy_addr;
3105 ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg,
3109 hw->phy.ops.release(hw);
3115 * e1000_read_phy_reg_hv - Read HV PHY register
3116 * @hw: pointer to the HW structure
3117 * @offset: register offset to be read
3118 * @data: pointer to the read data
3120 * Acquires semaphore then reads the PHY register at offset and stores
3121 * the retrieved information in data. Release the acquired semaphore
3124 s32 e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data)
3126 return __e1000_read_phy_reg_hv(hw, offset, data, FALSE);
3130 * e1000_read_phy_reg_hv_locked - Read HV PHY register
3131 * @hw: pointer to the HW structure
3132 * @offset: register offset to be read
3133 * @data: pointer to the read data
3135 * Reads the PHY register at offset and stores the retrieved information
3136 * in data. Assumes semaphore already acquired.
3138 s32 e1000_read_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 *data)
3140 return __e1000_read_phy_reg_hv(hw, offset, data, TRUE);
3144 * __e1000_write_phy_reg_hv - Write HV PHY register
3145 * @hw: pointer to the HW structure
3146 * @offset: register offset to write to
3147 * @data: data to write at register offset
3148 * @locked: semaphore has already been acquired or not
3150 * Acquires semaphore, if necessary, then writes the data to PHY register
3151 * at the offset. Release any acquired semaphores before exiting.
3153 static s32 __e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data,
3157 u16 page = BM_PHY_REG_PAGE(offset);
3158 u16 reg = BM_PHY_REG_NUM(offset);
3160 DEBUGFUNC("__e1000_write_phy_reg_hv");
3163 ret_val = hw->phy.ops.acquire(hw);
3168 /* Page 800 works differently than the rest so it has its own func */
3169 if (page == BM_WUC_PAGE) {
3170 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset,
3175 if (page > 0 && page < HV_INTC_FC_PAGE_START) {
3176 ret_val = e1000_access_phy_debug_regs_hv(hw, offset,
3181 hw->phy.addr = e1000_get_phy_addr_for_hv_page(page);
3183 if (page == HV_INTC_FC_PAGE_START)
3187 * Workaround MDIO accesses being disabled after entering IEEE Power
3188 * Down (whenever bit 11 of the PHY Control register is set)
3190 if ((hw->phy.type == e1000_phy_82578) &&
3191 (hw->phy.revision >= 1) &&
3192 (hw->phy.addr == 2) &&
3193 ((MAX_PHY_REG_ADDRESS & reg) == 0) &&
3194 (data & (1 << 11))) {
3196 ret_val = e1000_access_phy_debug_regs_hv(hw, (1 << 6) | 0x3,
3202 if (reg > MAX_PHY_MULTI_PAGE_REG) {
3203 u32 phy_addr = hw->phy.addr;
3207 /* Page is shifted left, PHY expects (page x 32) */
3208 ret_val = e1000_write_phy_reg_mdic(hw,
3209 IGP01E1000_PHY_PAGE_SELECT,
3210 (page << IGP_PAGE_SHIFT));
3211 hw->phy.addr = phy_addr;
3217 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg,
3222 hw->phy.ops.release(hw);
3228 * e1000_write_phy_reg_hv - Write HV PHY register
3229 * @hw: pointer to the HW structure
3230 * @offset: register offset to write to
3231 * @data: data to write at register offset
3233 * Acquires semaphore then writes the data to PHY register at the offset.
3234 * Release the acquired semaphores before exiting.
3236 s32 e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data)
3238 return __e1000_write_phy_reg_hv(hw, offset, data, FALSE);
3242 * e1000_write_phy_reg_hv_locked - Write HV PHY register
3243 * @hw: pointer to the HW structure
3244 * @offset: register offset to write to
3245 * @data: data to write at register offset
3247 * Writes the data to PHY register at the offset. Assumes semaphore
3250 s32 e1000_write_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 data)
3252 return __e1000_write_phy_reg_hv(hw, offset, data, TRUE);
3256 * e1000_get_phy_addr_for_hv_page - Get PHY adrress based on page
3257 * @page: page to be accessed
3259 static u32 e1000_get_phy_addr_for_hv_page(u32 page)
3263 if (page >= HV_INTC_FC_PAGE_START)
3270 * e1000_access_phy_debug_regs_hv - Read HV PHY vendor specific high registers
3271 * @hw: pointer to the HW structure
3272 * @offset: register offset to be read or written
3273 * @data: pointer to the data to be read or written
3274 * @read: determines if operation is read or written
3276 * Reads the PHY register at offset and stores the retreived information
3277 * in data. Assumes semaphore already acquired. Note that the procedure
3278 * to read these regs uses the address port and data port to read/write.
3280 static s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset,
3281 u16 *data, bool read)
3287 DEBUGFUNC("e1000_access_phy_debug_regs_hv");
3289 /* This takes care of the difference with desktop vs mobile phy */
3290 addr_reg = (hw->phy.type == e1000_phy_82578) ?
3291 I82578_ADDR_REG : I82577_ADDR_REG;
3292 data_reg = addr_reg + 1;
3294 /* All operations in this function are phy address 2 */
3297 /* masking with 0x3F to remove the page from offset */
3298 ret_val = e1000_write_phy_reg_mdic(hw, addr_reg, (u16)offset & 0x3F);
3300 DEBUGOUT("Could not write PHY the HV address register\n");
3304 /* Read or write the data value next */
3306 ret_val = e1000_read_phy_reg_mdic(hw, data_reg, data);
3308 ret_val = e1000_write_phy_reg_mdic(hw, data_reg, *data);
3311 DEBUGOUT("Could not read data value from HV data register\n");
3320 * e1000_link_stall_workaround_hv - Si workaround
3321 * @hw: pointer to the HW structure
3323 * This function works around a Si bug where the link partner can get
3324 * a link up indication before the PHY does. If small packets are sent
3325 * by the link partner they can be placed in the packet buffer without
3326 * being properly accounted for by the PHY and will stall preventing
3327 * further packets from being received. The workaround is to clear the
3328 * packet buffer after the PHY detects link up.
3330 s32 e1000_link_stall_workaround_hv(struct e1000_hw *hw)
3332 s32 ret_val = E1000_SUCCESS;
3335 DEBUGFUNC("e1000_link_stall_workaround_hv");
3337 if (hw->phy.type != e1000_phy_82578)
3340 /* Do not apply workaround if in PHY loopback bit 14 set */
3341 hw->phy.ops.read_reg(hw, PHY_CONTROL, &data);
3342 if (data & PHY_CONTROL_LB)
3345 /* check if link is up and at 1Gbps */
3346 ret_val = hw->phy.ops.read_reg(hw, BM_CS_STATUS, &data);
3350 data &= BM_CS_STATUS_LINK_UP |
3351 BM_CS_STATUS_RESOLVED |
3352 BM_CS_STATUS_SPEED_MASK;
3354 if (data != (BM_CS_STATUS_LINK_UP |
3355 BM_CS_STATUS_RESOLVED |
3356 BM_CS_STATUS_SPEED_1000))
3361 /* flush the packets in the fifo buffer */
3362 ret_val = hw->phy.ops.write_reg(hw, HV_MUX_DATA_CTRL,
3363 HV_MUX_DATA_CTRL_GEN_TO_MAC |
3364 HV_MUX_DATA_CTRL_FORCE_SPEED);
3368 ret_val = hw->phy.ops.write_reg(hw, HV_MUX_DATA_CTRL,
3369 HV_MUX_DATA_CTRL_GEN_TO_MAC);
3376 * e1000_check_polarity_82577 - Checks the polarity.
3377 * @hw: pointer to the HW structure
3379 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
3381 * Polarity is determined based on the PHY specific status register.
3383 s32 e1000_check_polarity_82577(struct e1000_hw *hw)
3385 struct e1000_phy_info *phy = &hw->phy;
3389 DEBUGFUNC("e1000_check_polarity_82577");
3391 ret_val = phy->ops.read_reg(hw, I82577_PHY_STATUS_2, &data);
3394 phy->cable_polarity = (data & I82577_PHY_STATUS2_REV_POLARITY)
3395 ? e1000_rev_polarity_reversed
3396 : e1000_rev_polarity_normal;
3402 * e1000_phy_force_speed_duplex_82577 - Force speed/duplex for I82577 PHY
3403 * @hw: pointer to the HW structure
3405 * Calls the PHY setup function to force speed and duplex.
3407 s32 e1000_phy_force_speed_duplex_82577(struct e1000_hw *hw)
3409 struct e1000_phy_info *phy = &hw->phy;
3414 DEBUGFUNC("e1000_phy_force_speed_duplex_82577");
3416 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data);
3420 e1000_phy_force_speed_duplex_setup(hw, &phy_data);
3422 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data);
3428 if (phy->autoneg_wait_to_complete) {
3429 DEBUGOUT("Waiting for forced speed/duplex link on 82577 phy\n");
3431 ret_val = e1000_phy_has_link_generic(hw,
3439 DEBUGOUT("Link taking longer than expected.\n");
3442 ret_val = e1000_phy_has_link_generic(hw,
3455 * e1000_get_phy_info_82577 - Retrieve I82577 PHY information
3456 * @hw: pointer to the HW structure
3458 * Read PHY status to determine if link is up. If link is up, then
3459 * set/determine 10base-T extended distance and polarity correction. Read
3460 * PHY port status to determine MDI/MDIx and speed. Based on the speed,
3461 * determine on the cable length, local and remote receiver.
3463 s32 e1000_get_phy_info_82577(struct e1000_hw *hw)
3465 struct e1000_phy_info *phy = &hw->phy;
3470 DEBUGFUNC("e1000_get_phy_info_82577");
3472 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
3477 DEBUGOUT("Phy info is only valid if link is up\n");
3478 ret_val = -E1000_ERR_CONFIG;
3482 phy->polarity_correction = TRUE;
3484 ret_val = e1000_check_polarity_82577(hw);
3488 ret_val = phy->ops.read_reg(hw, I82577_PHY_STATUS_2, &data);
3492 phy->is_mdix = (data & I82577_PHY_STATUS2_MDIX) ? TRUE : FALSE;
3494 if ((data & I82577_PHY_STATUS2_SPEED_MASK) ==
3495 I82577_PHY_STATUS2_SPEED_1000MBPS) {
3496 ret_val = hw->phy.ops.get_cable_length(hw);
3500 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &data);
3504 phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS)
3505 ? e1000_1000t_rx_status_ok
3506 : e1000_1000t_rx_status_not_ok;
3508 phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS)
3509 ? e1000_1000t_rx_status_ok
3510 : e1000_1000t_rx_status_not_ok;
3512 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
3513 phy->local_rx = e1000_1000t_rx_status_undefined;
3514 phy->remote_rx = e1000_1000t_rx_status_undefined;
3522 * e1000_get_cable_length_82577 - Determine cable length for 82577 PHY
3523 * @hw: pointer to the HW structure
3525 * Reads the diagnostic status register and verifies result is valid before
3526 * placing it in the phy_cable_length field.
3528 s32 e1000_get_cable_length_82577(struct e1000_hw *hw)
3530 struct e1000_phy_info *phy = &hw->phy;
3532 u16 phy_data, length;
3534 DEBUGFUNC("e1000_get_cable_length_82577");
3536 ret_val = phy->ops.read_reg(hw, I82577_PHY_DIAG_STATUS, &phy_data);
3540 length = (phy_data & I82577_DSTATUS_CABLE_LENGTH) >>
3541 I82577_DSTATUS_CABLE_LENGTH_SHIFT;
3543 if (length == E1000_CABLE_LENGTH_UNDEFINED)
3544 ret_val = -E1000_ERR_PHY;
3546 phy->cable_length = length;