1 /******************************************************************************
3 Copyright (c) 2001-2010, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
32 ******************************************************************************/
36 #ifndef _LEM_H_DEFINED_
37 #define _LEM_H_DEFINED_
43 * EM_TXD: Maximum number of Transmit Descriptors
44 * Valid Range: 80-256 for 82542 and 82543-based adapters
47 * This value is the number of transmit descriptors allocated by the driver.
48 * Increasing this value allows the driver to queue more transmits. Each
49 * descriptor is 16 bytes.
50 * Since TDLEN should be multiple of 128bytes, the number of transmit
51 * desscriptors should meet the following condition.
52 * (num_tx_desc * sizeof(struct e1000_tx_desc)) % 128 == 0
55 #define EM_MAX_TXD_82543 256
56 #define EM_MAX_TXD 4096
57 #define EM_DEFAULT_TXD EM_MAX_TXD_82543
60 * EM_RXD - Maximum number of receive Descriptors
61 * Valid Range: 80-256 for 82542 and 82543-based adapters
64 * This value is the number of receive descriptors allocated by the driver.
65 * Increasing this value allows the driver to buffer more incoming packets.
66 * Each descriptor is 16 bytes. A receive buffer is also allocated for each
67 * descriptor. The maximum MTU size is 16110.
68 * Since TDLEN should be multiple of 128bytes, the number of transmit
69 * desscriptors should meet the following condition.
70 * (num_tx_desc * sizeof(struct e1000_tx_desc)) % 128 == 0
73 #define EM_MAX_RXD_82543 256
74 #define EM_MAX_RXD 4096
75 #define EM_DEFAULT_RXD EM_MAX_RXD_82543
78 * EM_TIDV - Transmit Interrupt Delay Value
79 * Valid Range: 0-65535 (0=off)
81 * This value delays the generation of transmit interrupts in units of
82 * 1.024 microseconds. Transmit interrupt reduction can improve CPU
83 * efficiency if properly tuned for specific network traffic. If the
84 * system is reporting dropped transmits, this value may be set too high
85 * causing the driver to run out of available transmit descriptors.
90 * EM_TADV - Transmit Absolute Interrupt Delay Value
91 * (Not valid for 82542/82543/82544)
92 * Valid Range: 0-65535 (0=off)
94 * This value, in units of 1.024 microseconds, limits the delay in which a
95 * transmit interrupt is generated. Useful only if EM_TIDV is non-zero,
96 * this value ensures that an interrupt is generated after the initial
97 * packet is sent on the wire within the set amount of time. Proper tuning,
98 * along with EM_TIDV, may improve traffic throughput in specific
104 * EM_RDTR - Receive Interrupt Delay Timer (Packet Timer)
105 * Valid Range: 0-65535 (0=off)
107 * This value delays the generation of receive interrupts in units of 1.024
108 * microseconds. Receive interrupt reduction can improve CPU efficiency if
109 * properly tuned for specific network traffic. Increasing this value adds
110 * extra latency to frame reception and can end up decreasing the throughput
111 * of TCP traffic. If the system is reporting dropped receives, this value
112 * may be set too high, causing the driver to run out of available receive
115 * CAUTION: When setting EM_RDTR to a value other than 0, adapters
116 * may hang (stop transmitting) under certain network conditions.
117 * If this occurs a WATCHDOG message is logged in the system
118 * event log. In addition, the controller is automatically reset,
119 * restoring the network connection. To eliminate the potential
120 * for the hang ensure that EM_RDTR is set to 0.
125 * Receive Interrupt Absolute Delay Timer (Not valid for 82542/82543/82544)
126 * Valid Range: 0-65535 (0=off)
128 * This value, in units of 1.024 microseconds, limits the delay in which a
129 * receive interrupt is generated. Useful only if EM_RDTR is non-zero,
130 * this value ensures that an interrupt is generated after the initial
131 * packet is received within the set amount of time. Proper tuning,
132 * along with EM_RDTR, may improve traffic throughput in specific network
138 * This parameter controls the max duration of transmit watchdog.
140 #define EM_WATCHDOG (10 * hz)
143 * This parameter controls when the driver calls the routine to reclaim
144 * transmit descriptors.
146 #define EM_TX_CLEANUP_THRESHOLD (adapter->num_tx_desc / 8)
147 #define EM_TX_OP_THRESHOLD (adapter->num_tx_desc / 32)
150 * This parameter controls whether or not autonegotation is enabled.
151 * 0 - Disable autonegotiation
152 * 1 - Enable autonegotiation
154 #define DO_AUTO_NEG 1
157 * This parameter control whether or not the driver will wait for
158 * autonegotiation to complete.
159 * 1 - Wait for autonegotiation to complete
160 * 0 - Don't wait for autonegotiation to complete
162 #define WAIT_FOR_AUTO_NEG_DEFAULT 0
164 /* Tunables -- End */
166 #define AUTONEG_ADV_DEFAULT (ADVERTISE_10_HALF | ADVERTISE_10_FULL | \
167 ADVERTISE_100_HALF | ADVERTISE_100_FULL | \
170 #define AUTO_ALL_MODES 0
172 /* PHY master/slave setting */
173 #define EM_MASTER_SLAVE e1000_ms_hw_default
176 * Micellaneous constants
178 #define EM_VENDOR_ID 0x8086
179 #define EM_FLASH 0x0014
181 #define EM_JUMBO_PBA 0x00000028
182 #define EM_DEFAULT_PBA 0x00000030
183 #define EM_SMARTSPEED_DOWNSHIFT 3
184 #define EM_SMARTSPEED_MAX 15
185 #define EM_MAX_LOOP 10
187 #define MAX_NUM_MULTICAST_ADDRESSES 128
188 #define PCI_ANY_ID (~0U)
189 #define ETHER_ALIGN 2
190 #define EM_FC_PAUSE_TIME 0x0680
191 #define EM_EEPROM_APME 0x400;
192 #define EM_82544_APME 0x0004;
194 /* Code compatilbility between 6 and 7 */
195 #ifndef ETHER_BPF_MTAP
196 #define ETHER_BPF_MTAP BPF_MTAP
200 * TDBA/RDBA should be aligned on 16 byte boundary. But TDLEN/RDLEN should be
201 * multiple of 128 bytes. So we align TDBA/RDBA on 128 byte boundary. This will
202 * also optimize cache line size effect. H/W supports up to cache line size 128.
204 #define EM_DBA_ALIGN 128
206 #define SPEED_MODE_BIT (1<<21) /* On PCI-E MACs only */
208 /* PCI Config defines */
209 #define EM_BAR_TYPE(v) ((v) & EM_BAR_TYPE_MASK)
210 #define EM_BAR_TYPE_MASK 0x00000001
211 #define EM_BAR_TYPE_MMEM 0x00000000
212 #define EM_BAR_TYPE_IO 0x00000001
213 #define EM_BAR_TYPE_FLASH 0x0014
214 #define EM_BAR_MEM_TYPE(v) ((v) & EM_BAR_MEM_TYPE_MASK)
215 #define EM_BAR_MEM_TYPE_MASK 0x00000006
216 #define EM_BAR_MEM_TYPE_32BIT 0x00000000
217 #define EM_BAR_MEM_TYPE_64BIT 0x00000004
218 #define EM_MSIX_BAR 3 /* On 82575 */
220 /* Defines for printing debug information */
222 #define DEBUG_IOCTL 0
225 #define INIT_DEBUGOUT(S) if (DEBUG_INIT) printf(S "\n")
226 #define INIT_DEBUGOUT1(S, A) if (DEBUG_INIT) printf(S "\n", A)
227 #define INIT_DEBUGOUT2(S, A, B) if (DEBUG_INIT) printf(S "\n", A, B)
228 #define IOCTL_DEBUGOUT(S) if (DEBUG_IOCTL) printf(S "\n")
229 #define IOCTL_DEBUGOUT1(S, A) if (DEBUG_IOCTL) printf(S "\n", A)
230 #define IOCTL_DEBUGOUT2(S, A, B) if (DEBUG_IOCTL) printf(S "\n", A, B)
231 #define HW_DEBUGOUT(S) if (DEBUG_HW) printf(S "\n")
232 #define HW_DEBUGOUT1(S, A) if (DEBUG_HW) printf(S "\n", A)
233 #define HW_DEBUGOUT2(S, A, B) if (DEBUG_HW) printf(S "\n", A, B)
235 #define EM_MAX_SCATTER 64
236 #define EM_VFTA_SIZE 128
237 #define EM_TSO_SIZE (65535 + sizeof(struct ether_vlan_header))
238 #define EM_TSO_SEG_SIZE 4096 /* Max dma segment size */
239 #define EM_MSIX_MASK 0x01F00000 /* For 82574 use */
241 #define ETH_ADDR_LEN 6
242 #define CSUM_OFFLOAD 7 /* Offload bits in mbuf flag */
245 * 82574 has a nonstandard address for EIAC
246 * and since its only used in MSIX, and in
247 * the em driver only 82574 uses MSIX we can
248 * solve it just using this define.
250 #define EM_EIAC 0x000DC
252 /* Used in for 82547 10Mb Half workaround */
253 #define EM_PBA_BYTES_SHIFT 0xA
254 #define EM_TX_HEAD_ADDR_SHIFT 7
255 #define EM_PBA_TX_MASK 0xFFFF0000
256 #define EM_FIFO_HDR 0x10
257 #define EM_82547_PKT_THRESH 0x3e0
259 /* Precision Time Sync (IEEE 1588) defines */
260 #define ETHERTYPE_IEEE1588 0x88F7
261 #define PICOSECS_PER_TICK 20833
262 #define TSYNC_PORT 319 /* UDP port for the protocol */
265 * Bus dma allocation structure used by
266 * e1000_dma_malloc and e1000_dma_free.
268 struct em_dma_alloc {
269 bus_addr_t dma_paddr;
271 bus_dma_tag_t dma_tag;
272 bus_dmamap_t dma_map;
273 bus_dma_segment_t dma_seg;
279 struct em_int_delay_info {
280 struct adapter *adapter; /* Back-pointer to the adapter struct */
281 int offset; /* Register offset to read/write */
282 int value; /* Current value in usecs */
285 /* Our adapter structure */
288 #if __FreeBSD_version >= 800000
293 /* FreeBSD operating-system-specific structures. */
294 struct e1000_osdep osdep;
296 struct cdev *led_dev;
298 struct resource *memory;
299 struct resource *flash;
300 struct resource *msix;
302 struct resource *ioport;
305 /* 82574 may use 3 int vectors */
306 struct resource *res[3];
310 struct ifmedia media;
311 struct callout timer;
312 struct callout tx_fifo_timer;
322 int em_insert_vlan_header;
324 /* Task for FAST handling */
325 struct task link_task;
326 struct task rxtx_task;
329 struct taskqueue *tq; /* private task queue */
331 #if __FreeBSD_version >= 700029
332 eventhandler_tag vlan_attach;
333 eventhandler_tag vlan_detach;
337 /* Management and WOL features */
342 /* Info about the board itself */
345 uint16_t link_duplex;
347 struct em_int_delay_info tx_int_delay;
348 struct em_int_delay_info tx_abs_int_delay;
349 struct em_int_delay_info rx_int_delay;
350 struct em_int_delay_info rx_abs_int_delay;
353 * Transmit definitions
355 * We have an array of num_tx_desc descriptors (handled
356 * by the controller) paired with an array of tx_buffers
357 * (at tx_buffer_area).
358 * The index of the next available descriptor is next_avail_tx_desc.
359 * The number of remaining tx_desc is num_tx_desc_avail.
361 struct em_dma_alloc txdma; /* bus_dma glue for tx desc */
362 struct e1000_tx_desc *tx_desc_base;
363 uint32_t next_avail_tx_desc;
364 uint32_t next_tx_to_clean;
365 volatile uint16_t num_tx_desc_avail;
366 uint16_t num_tx_desc;
367 uint16_t last_hw_offload;
369 struct em_buffer *tx_buffer_area;
370 bus_dma_tag_t txtag; /* dma tag for tx */
371 uint32_t tx_tso; /* last tx was tso */
374 * Receive definitions
376 * we have an array of num_rx_desc rx_desc (handled by the
377 * controller), and paired with an array of rx_buffers
378 * (at rx_buffer_area).
379 * The next pair to check on receive is at offset next_rx_desc_to_check
381 struct em_dma_alloc rxdma; /* bus_dma glue for rx desc */
382 struct e1000_rx_desc *rx_desc_base;
383 uint32_t next_rx_desc_to_check;
384 uint32_t rx_buffer_len;
385 uint16_t num_rx_desc;
386 int rx_process_limit;
387 struct em_buffer *rx_buffer_area;
389 bus_dmamap_t rx_sparemap;
392 * First/last mbuf pointers, for
393 * collecting multisegment RX packets.
398 /* Misc stats maintained by the driver */
399 unsigned long dropped_pkts;
400 unsigned long mbuf_alloc_failed;
401 unsigned long mbuf_cluster_failed;
402 unsigned long no_tx_desc_avail1;
403 unsigned long no_tx_desc_avail2;
404 unsigned long no_tx_map_avail;
405 unsigned long no_tx_dma_setup;
406 unsigned long watchdog_events;
407 unsigned long rx_overruns;
408 unsigned long rx_irq;
409 unsigned long tx_irq;
410 unsigned long link_irq;
412 /* 82547 workaround */
413 uint32_t tx_fifo_size;
414 uint32_t tx_fifo_head;
415 uint32_t tx_fifo_head_addr;
416 uint64_t tx_fifo_reset_cnt;
417 uint64_t tx_fifo_wrk_cnt;
418 uint32_t tx_head_addr;
420 /* For 82544 PCIX Workaround */
421 boolean_t pcix_82544;
425 struct e1000_hw_stats stats;
428 /* ******************************************************************************
431 * This array contains the list of Subvendor/Subdevice IDs on which the driver
434 * ******************************************************************************/
435 typedef struct _em_vendor_info_t {
436 unsigned int vendor_id;
437 unsigned int device_id;
438 unsigned int subvendor_id;
439 unsigned int subdevice_id;
444 int next_eop; /* Index of the desc to watch */
446 bus_dmamap_t map; /* bus_dma map for packet */
449 /* For 82544 PCIX Workaround */
450 typedef struct _ADDRESS_LENGTH_PAIR
454 } ADDRESS_LENGTH_PAIR, *PADDRESS_LENGTH_PAIR;
456 typedef struct _DESCRIPTOR_PAIR
458 ADDRESS_LENGTH_PAIR descriptor[4];
460 } DESC_ARRAY, *PDESC_ARRAY;
462 #define EM_CORE_LOCK_INIT(_sc, _name) \
463 mtx_init(&(_sc)->core_mtx, _name, "EM Core Lock", MTX_DEF)
464 #define EM_TX_LOCK_INIT(_sc, _name) \
465 mtx_init(&(_sc)->tx_mtx, _name, "EM TX Lock", MTX_DEF)
466 #define EM_RX_LOCK_INIT(_sc, _name) \
467 mtx_init(&(_sc)->rx_mtx, _name, "EM RX Lock", MTX_DEF)
468 #define EM_CORE_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->core_mtx)
469 #define EM_TX_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->tx_mtx)
470 #define EM_RX_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->rx_mtx)
471 #define EM_CORE_LOCK(_sc) mtx_lock(&(_sc)->core_mtx)
472 #define EM_TX_LOCK(_sc) mtx_lock(&(_sc)->tx_mtx)
473 #define EM_TX_TRYLOCK(_sc) mtx_trylock(&(_sc)->tx_mtx)
474 #define EM_RX_LOCK(_sc) mtx_lock(&(_sc)->rx_mtx)
475 #define EM_CORE_UNLOCK(_sc) mtx_unlock(&(_sc)->core_mtx)
476 #define EM_TX_UNLOCK(_sc) mtx_unlock(&(_sc)->tx_mtx)
477 #define EM_RX_UNLOCK(_sc) mtx_unlock(&(_sc)->rx_mtx)
478 #define EM_CORE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->core_mtx, MA_OWNED)
479 #define EM_TX_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->tx_mtx, MA_OWNED)
481 #endif /* _LEM_H_DEFINED_ */