2 * Copyright (c) 2007 The DragonFly Project. All rights reserved.
4 * This code is derived from software contributed to The DragonFly Project
5 * by Sepherosa Ziehau <sepherosa@gmail.com>
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * 3. Neither the name of The DragonFly Project nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific, prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
24 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
25 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
27 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
28 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
29 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
31 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
34 * $DragonFly: src/sys/dev/netif/et/if_etvar.h,v 1.4 2007/10/23 14:28:42 sephe Exp $
41 /* DragonFly compatibility */
42 #define EVL_ENCAPLEN ETHER_VLAN_ENCAP_LEN
45 * Allocate the right type of mbuf for the desired total length.
47 static __inline struct mbuf *
48 m_getl(int len, int how, int type, int flags, int *psize)
53 if (len >= MINCLSIZE) {
54 m = m_getcl(how, type, flags);
56 } else if (flags & M_PKTHDR) {
57 m = m_gethdr(how, type);
69 #define ET_ALIGN 0x1000
70 #define ET_NSEG_MAX 32 /* XXX no limit actually */
71 #define ET_NSEG_SPARE 8
73 #define ET_TX_NDESC 512
74 #define ET_RX_NDESC 512
76 #define ET_RX_NSTAT (ET_RX_NRING * ET_RX_NDESC)
78 #define ET_TX_RING_SIZE (ET_TX_NDESC * sizeof(struct et_txdesc))
79 #define ET_RX_RING_SIZE (ET_RX_NDESC * sizeof(struct et_rxdesc))
80 #define ET_RXSTAT_RING_SIZE (ET_RX_NSTAT * sizeof(struct et_rxstat))
82 #define ET_JUMBO_FRAMELEN (ET_MEM_SIZE - ET_MEM_RXSIZE_MIN - \
84 #define ET_JUMBO_MTU (ET_JUMBO_FRAMELEN - ETHER_HDR_LEN - \
85 EVL_ENCAPLEN - ETHER_CRC_LEN)
87 #define ET_FRAMELEN(mtu) (ETHER_HDR_LEN + EVL_ENCAPLEN + (mtu) + \
90 #define ET_JSLOTS (ET_RX_NDESC + 128)
91 #define ET_JLEN (ET_JUMBO_FRAMELEN + ETHER_ALIGN)
92 #define ET_JUMBO_MEM_SIZE (ET_JSLOTS * ET_JLEN)
94 #define CSR_WRITE_4(sc, reg, val) \
95 bus_write_4((sc)->sc_mem_res, (reg), (val))
96 #define CSR_READ_4(sc, reg) \
97 bus_read_4((sc)->sc_mem_res, (reg))
99 #define ET_ADDR_HI(addr) ((uint64_t) (addr) >> 32)
100 #define ET_ADDR_LO(addr) ((uint64_t) (addr) & 0xffffffff)
105 uint32_t td_ctrl1; /* ET_TDCTRL1_ */
106 uint32_t td_ctrl2; /* ET_TDCTRL2_ */
109 #define ET_TDCTRL1_LEN_MASK 0x0000FFFF
111 #define ET_TDCTRL2_LAST_FRAG 0x00000001
112 #define ET_TDCTRL2_FIRST_FRAG 0x00000002
113 #define ET_TDCTRL2_INTR 0x00000004
114 #define ET_TDCTRL2_CTRL_WORD 0x00000008
115 #define ET_TDCTRL2_HDX_BACKP 0x00000010
116 #define ET_TDCTRL2_XMIT_PAUSE 0x00000020
117 #define ET_TDCTRL2_FRAME_ERR 0x00000040
118 #define ET_TDCTRL2_NO_CRC 0x00000080
119 #define ET_TDCTRL2_MAC_OVRRD 0x00000100
120 #define ET_TDCTRL2_PAD_PACKET 0x00000200
121 #define ET_TDCTRL2_JUMBO_PACKET 0x00000400
122 #define ET_TDCTRL2_INS_VLAN 0x00000800
123 #define ET_TDCTRL2_CSUM_IP 0x00001000
124 #define ET_TDCTRL2_CSUM_TCP 0x00002000
125 #define ET_TDCTRL2_CSUM_UDP 0x00004000
130 uint32_t rd_ctrl; /* ET_RDCTRL_ */
133 #define ET_RDCTRL_BUFIDX_MASK 0x000003FF
137 uint32_t rxst_info2; /* ET_RXST_INFO2_ */
140 #define ET_RXST_INFO2_LEN_MASK 0x0000FFFF
141 #define ET_RXST_INFO2_LEN_SHIFT 0
142 #define ET_RXST_INFO2_BUFIDX_MASK 0x03FF0000
143 #define ET_RXST_INFO2_BUFIDX_SHIFT 16
144 #define ET_RXST_INFO2_RINGIDX_MASK 0x0C000000
145 #define ET_RXST_INFO2_RINGIDX_SHIFT 26
149 uint32_t rxs_stat_ring; /* ET_RXS_STATRING_ */
152 #define ET_RXS_STATRING_INDEX_MASK 0x0FFF0000
153 #define ET_RXS_STATRING_INDEX_SHIFT 16
154 #define ET_RXS_STATRING_WRAP 0x10000000
156 struct et_dmamap_ctx {
158 bus_dma_segment_t *segs;
162 struct mbuf *tb_mbuf;
163 bus_dmamap_t tb_dmap;
167 struct mbuf *rb_mbuf;
168 bus_dmamap_t rb_dmap;
172 struct et_txstatus_data {
173 uint32_t *txsd_status;
174 bus_addr_t txsd_paddr;
175 bus_dma_tag_t txsd_dtag;
176 bus_dmamap_t txsd_dmap;
179 struct et_rxstatus_data {
180 struct et_rxstatus *rxsd_status;
181 bus_addr_t rxsd_paddr;
182 bus_dma_tag_t rxsd_dtag;
183 bus_dmamap_t rxsd_dmap;
186 struct et_rxstat_ring {
187 struct et_rxstat *rsr_stat;
188 bus_addr_t rsr_paddr;
189 bus_dma_tag_t rsr_dtag;
190 bus_dmamap_t rsr_dmap;
196 struct et_txdesc_ring {
197 struct et_txdesc *tr_desc;
199 bus_dma_tag_t tr_dtag;
200 bus_dmamap_t tr_dmap;
206 struct et_rxdesc_ring {
207 struct et_rxdesc *rr_desc;
209 bus_dma_tag_t rr_dtag;
210 bus_dmamap_t rr_dmap;
217 struct et_txbuf_data {
218 struct et_txbuf tbd_buf[ET_TX_NDESC];
226 struct et_rxbuf_data;
227 typedef int (*et_newbuf_t)(struct et_rxbuf_data *, int, int);
229 struct et_rxbuf_data {
230 struct et_rxbuf rbd_buf[ET_RX_NDESC];
232 struct et_softc *rbd_softc;
233 struct et_rxdesc_ring *rbd_ring;
236 et_newbuf_t rbd_newbuf;
245 struct resource *sc_irq_res;
246 struct resource *sc_mem_res;
248 struct arpcom arpcom;
250 uint32_t sc_flags; /* ET_FLAG_ */
257 struct callout sc_tick;
261 bus_dma_tag_t sc_dtag;
263 struct et_rxdesc_ring sc_rx_ring[ET_RX_NRING];
264 struct et_rxstat_ring sc_rxstat_ring;
265 struct et_rxstatus_data sc_rx_status;
267 struct et_txdesc_ring sc_tx_ring;
268 struct et_txstatus_data sc_tx_status;
270 bus_dma_tag_t sc_mbuf_dtag;
271 bus_dmamap_t sc_mbuf_tmp_dmap;
272 struct et_rxbuf_data sc_rx_data[ET_RX_NRING];
273 struct et_txbuf_data sc_tx_data;
281 int sc_rx_intr_npkts;
282 int sc_rx_intr_delay;
283 int sc_tx_intr_nsegs;
287 #define ET_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx)
288 #define ET_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx)
289 #define ET_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_mtx, MA_OWNED)
291 #define ET_FLAG_PCIE 0x0001
292 #define ET_FLAG_MSI 0x0002
293 #define ET_FLAG_TXRX_ENABLED 0x0100
294 #define ET_FLAG_JUMBO 0x0200
296 #endif /* !_IF_ETVAR_H */