2 * Copyright (c) 1995, David Greenman
3 * Copyright (c) 2001 Jonathan Lemon <jlemon@freebsd.org>
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice unmodified, this list of conditions, and the following
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD$");
34 * Intel EtherExpress Pro/100B PCI Fast Ethernet driver
37 #ifdef HAVE_KERNEL_OPTION_HEADERS
38 #include "opt_device_polling.h"
41 #include <sys/param.h>
42 #include <sys/systm.h>
44 #include <sys/endian.h>
45 #include <sys/kernel.h>
48 #include <sys/module.h>
49 #include <sys/mutex.h>
51 #include <sys/socket.h>
52 #include <sys/sockio.h>
53 #include <sys/sysctl.h>
56 #include <net/ethernet.h>
58 #include <net/if_arp.h>
59 #include <net/if_dl.h>
60 #include <net/if_media.h>
61 #include <net/if_types.h>
62 #include <net/if_vlan_var.h>
64 #include <netinet/in.h>
65 #include <netinet/in_systm.h>
66 #include <netinet/ip.h>
67 #include <netinet/tcp.h>
68 #include <netinet/udp.h>
70 #include <machine/bus.h>
71 #include <machine/in_cksum.h>
72 #include <machine/resource.h>
74 #include <dev/pci/pcivar.h>
75 #include <dev/pci/pcireg.h> /* for PCIM_CMD_xxx */
77 #include <dev/mii/mii.h>
78 #include <dev/mii/miivar.h>
80 #include <dev/fxp/if_fxpreg.h>
81 #include <dev/fxp/if_fxpvar.h>
82 #include <dev/fxp/rcvbundl.h>
84 MODULE_DEPEND(fxp, pci, 1, 1, 1);
85 MODULE_DEPEND(fxp, ether, 1, 1, 1);
86 MODULE_DEPEND(fxp, miibus, 1, 1, 1);
87 #include "miibus_if.h"
90 * NOTE! On the Alpha, we have an alignment constraint. The
91 * card DMAs the packet immediately following the RFA. However,
92 * the first thing in the packet is a 14-byte Ethernet header.
93 * This means that the packet is misaligned. To compensate,
94 * we actually offset the RFA 2 bytes into the cluster. This
95 * alignes the packet after the Ethernet header at a 32-bit
96 * boundary. HOWEVER! This means that the RFA is misaligned!
98 #define RFA_ALIGNMENT_FUDGE 2
101 * Set initial transmit threshold at 64 (512 bytes). This is
102 * increased by 64 (512 bytes) at a time, to maximum of 192
103 * (1536 bytes), if an underrun occurs.
105 static int tx_threshold = 64;
108 * The configuration byte map has several undefined fields which
109 * must be one or must be zero. Set up a template for these bits.
110 * The actual configuration is performed in fxp_init.
112 * See struct fxp_cb_config for the bit definitions.
114 static u_char fxp_cb_config_template[] = {
115 0x0, 0x0, /* cb_status */
116 0x0, 0x0, /* cb_command */
117 0x0, 0x0, 0x0, 0x0, /* link_addr */
153 * Claim various Intel PCI device identifiers for this driver. The
154 * sub-vendor and sub-device field are extensively used to identify
155 * particular variants, but we don't currently differentiate between
158 static struct fxp_ident fxp_ident_table[] = {
159 { 0x1029, -1, 0, "Intel 82559 PCI/CardBus Pro/100" },
160 { 0x1030, -1, 0, "Intel 82559 Pro/100 Ethernet" },
161 { 0x1031, -1, 3, "Intel 82801CAM (ICH3) Pro/100 VE Ethernet" },
162 { 0x1032, -1, 3, "Intel 82801CAM (ICH3) Pro/100 VE Ethernet" },
163 { 0x1033, -1, 3, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" },
164 { 0x1034, -1, 3, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" },
165 { 0x1035, -1, 3, "Intel 82801CAM (ICH3) Pro/100 Ethernet" },
166 { 0x1036, -1, 3, "Intel 82801CAM (ICH3) Pro/100 Ethernet" },
167 { 0x1037, -1, 3, "Intel 82801CAM (ICH3) Pro/100 Ethernet" },
168 { 0x1038, -1, 3, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" },
169 { 0x1039, -1, 4, "Intel 82801DB (ICH4) Pro/100 VE Ethernet" },
170 { 0x103A, -1, 4, "Intel 82801DB (ICH4) Pro/100 Ethernet" },
171 { 0x103B, -1, 4, "Intel 82801DB (ICH4) Pro/100 VM Ethernet" },
172 { 0x103C, -1, 4, "Intel 82801DB (ICH4) Pro/100 Ethernet" },
173 { 0x103D, -1, 4, "Intel 82801DB (ICH4) Pro/100 VE Ethernet" },
174 { 0x103E, -1, 4, "Intel 82801DB (ICH4) Pro/100 VM Ethernet" },
175 { 0x1050, -1, 5, "Intel 82801BA (D865) Pro/100 VE Ethernet" },
176 { 0x1051, -1, 5, "Intel 82562ET (ICH5/ICH5R) Pro/100 VE Ethernet" },
177 { 0x1059, -1, 0, "Intel 82551QM Pro/100 M Mobile Connection" },
178 { 0x1064, -1, 6, "Intel 82562EZ (ICH6)" },
179 { 0x1065, -1, 6, "Intel 82562ET/EZ/GT/GZ PRO/100 VE Ethernet" },
180 { 0x1068, -1, 6, "Intel 82801FBM (ICH6-M) Pro/100 VE Ethernet" },
181 { 0x1069, -1, 6, "Intel 82562EM/EX/GX Pro/100 Ethernet" },
182 { 0x1091, -1, 7, "Intel 82562GX Pro/100 Ethernet" },
183 { 0x1092, -1, 7, "Intel Pro/100 VE Network Connection" },
184 { 0x1093, -1, 7, "Intel Pro/100 VM Network Connection" },
185 { 0x1094, -1, 7, "Intel Pro/100 946GZ (ICH7) Network Connection" },
186 { 0x1209, -1, 0, "Intel 82559ER Embedded 10/100 Ethernet" },
187 { 0x1229, 0x01, 0, "Intel 82557 Pro/100 Ethernet" },
188 { 0x1229, 0x02, 0, "Intel 82557 Pro/100 Ethernet" },
189 { 0x1229, 0x03, 0, "Intel 82557 Pro/100 Ethernet" },
190 { 0x1229, 0x04, 0, "Intel 82558 Pro/100 Ethernet" },
191 { 0x1229, 0x05, 0, "Intel 82558 Pro/100 Ethernet" },
192 { 0x1229, 0x06, 0, "Intel 82559 Pro/100 Ethernet" },
193 { 0x1229, 0x07, 0, "Intel 82559 Pro/100 Ethernet" },
194 { 0x1229, 0x08, 0, "Intel 82559 Pro/100 Ethernet" },
195 { 0x1229, 0x09, 0, "Intel 82559ER Pro/100 Ethernet" },
196 { 0x1229, 0x0c, 0, "Intel 82550 Pro/100 Ethernet" },
197 { 0x1229, 0x0d, 0, "Intel 82550 Pro/100 Ethernet" },
198 { 0x1229, 0x0e, 0, "Intel 82550 Pro/100 Ethernet" },
199 { 0x1229, 0x0f, 0, "Intel 82551 Pro/100 Ethernet" },
200 { 0x1229, 0x10, 0, "Intel 82551 Pro/100 Ethernet" },
201 { 0x1229, -1, 0, "Intel 82557/8/9 Pro/100 Ethernet" },
202 { 0x2449, -1, 2, "Intel 82801BA/CAM (ICH2/3) Pro/100 Ethernet" },
203 { 0x27dc, -1, 7, "Intel 82801GB (ICH7) 10/100 Ethernet" },
207 #ifdef FXP_IP_CSUM_WAR
208 #define FXP_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
210 #define FXP_CSUM_FEATURES (CSUM_TCP | CSUM_UDP)
213 static int fxp_probe(device_t dev);
214 static int fxp_attach(device_t dev);
215 static int fxp_detach(device_t dev);
216 static int fxp_shutdown(device_t dev);
217 static int fxp_suspend(device_t dev);
218 static int fxp_resume(device_t dev);
220 static struct fxp_ident *fxp_find_ident(device_t dev);
221 static void fxp_intr(void *xsc);
222 static void fxp_rxcsum(struct fxp_softc *sc, struct ifnet *ifp,
223 struct mbuf *m, uint16_t status, int pos);
224 static int fxp_intr_body(struct fxp_softc *sc, struct ifnet *ifp,
225 uint8_t statack, int count);
226 static void fxp_init(void *xsc);
227 static void fxp_init_body(struct fxp_softc *sc);
228 static void fxp_tick(void *xsc);
229 static void fxp_start(struct ifnet *ifp);
230 static void fxp_start_body(struct ifnet *ifp);
231 static int fxp_encap(struct fxp_softc *sc, struct mbuf **m_head);
232 static void fxp_txeof(struct fxp_softc *sc);
233 static void fxp_stop(struct fxp_softc *sc);
234 static void fxp_release(struct fxp_softc *sc);
235 static int fxp_ioctl(struct ifnet *ifp, u_long command,
237 static void fxp_watchdog(struct fxp_softc *sc);
238 static void fxp_add_rfabuf(struct fxp_softc *sc,
240 static void fxp_discard_rfabuf(struct fxp_softc *sc,
242 static int fxp_new_rfabuf(struct fxp_softc *sc,
244 static int fxp_mc_addrs(struct fxp_softc *sc);
245 static void fxp_mc_setup(struct fxp_softc *sc);
246 static uint16_t fxp_eeprom_getword(struct fxp_softc *sc, int offset,
248 static void fxp_eeprom_putword(struct fxp_softc *sc, int offset,
250 static void fxp_autosize_eeprom(struct fxp_softc *sc);
251 static void fxp_read_eeprom(struct fxp_softc *sc, u_short *data,
252 int offset, int words);
253 static void fxp_write_eeprom(struct fxp_softc *sc, u_short *data,
254 int offset, int words);
255 static int fxp_ifmedia_upd(struct ifnet *ifp);
256 static void fxp_ifmedia_sts(struct ifnet *ifp,
257 struct ifmediareq *ifmr);
258 static int fxp_serial_ifmedia_upd(struct ifnet *ifp);
259 static void fxp_serial_ifmedia_sts(struct ifnet *ifp,
260 struct ifmediareq *ifmr);
261 static int fxp_miibus_readreg(device_t dev, int phy, int reg);
262 static int fxp_miibus_writereg(device_t dev, int phy, int reg,
264 static void fxp_load_ucode(struct fxp_softc *sc);
265 static void fxp_update_stats(struct fxp_softc *sc);
266 static void fxp_sysctl_node(struct fxp_softc *sc);
267 static int sysctl_int_range(SYSCTL_HANDLER_ARGS,
269 static int sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS);
270 static int sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS);
271 static void fxp_scb_wait(struct fxp_softc *sc);
272 static void fxp_scb_cmd(struct fxp_softc *sc, int cmd);
273 static void fxp_dma_wait(struct fxp_softc *sc,
274 volatile uint16_t *status, bus_dma_tag_t dmat,
277 static device_method_t fxp_methods[] = {
278 /* Device interface */
279 DEVMETHOD(device_probe, fxp_probe),
280 DEVMETHOD(device_attach, fxp_attach),
281 DEVMETHOD(device_detach, fxp_detach),
282 DEVMETHOD(device_shutdown, fxp_shutdown),
283 DEVMETHOD(device_suspend, fxp_suspend),
284 DEVMETHOD(device_resume, fxp_resume),
287 DEVMETHOD(miibus_readreg, fxp_miibus_readreg),
288 DEVMETHOD(miibus_writereg, fxp_miibus_writereg),
293 static driver_t fxp_driver = {
296 sizeof(struct fxp_softc),
299 static devclass_t fxp_devclass;
301 DRIVER_MODULE(fxp, pci, fxp_driver, fxp_devclass, 0, 0);
302 DRIVER_MODULE(miibus, fxp, miibus_driver, miibus_devclass, 0, 0);
304 static struct resource_spec fxp_res_spec_mem[] = {
305 { SYS_RES_MEMORY, FXP_PCI_MMBA, RF_ACTIVE },
306 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE },
310 static struct resource_spec fxp_res_spec_io[] = {
311 { SYS_RES_IOPORT, FXP_PCI_IOBA, RF_ACTIVE },
312 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE },
317 * Wait for the previous command to be accepted (but not necessarily
321 fxp_scb_wait(struct fxp_softc *sc)
329 while (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) && --i)
332 flowctl.b[0] = CSR_READ_1(sc, FXP_CSR_FLOWCONTROL);
333 flowctl.b[1] = CSR_READ_1(sc, FXP_CSR_FLOWCONTROL + 1);
334 device_printf(sc->dev, "SCB timeout: 0x%x 0x%x 0x%x 0x%x\n",
335 CSR_READ_1(sc, FXP_CSR_SCB_COMMAND),
336 CSR_READ_1(sc, FXP_CSR_SCB_STATACK),
337 CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS), flowctl.w);
342 fxp_scb_cmd(struct fxp_softc *sc, int cmd)
345 if (cmd == FXP_SCB_COMMAND_CU_RESUME && sc->cu_resume_bug) {
346 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_CB_COMMAND_NOP);
349 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, cmd);
353 fxp_dma_wait(struct fxp_softc *sc, volatile uint16_t *status,
354 bus_dma_tag_t dmat, bus_dmamap_t map)
358 for (i = 10000; i > 0; i--) {
360 bus_dmamap_sync(dmat, map,
361 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
362 if ((le16toh(*status) & FXP_CB_STATUS_C) != 0)
366 device_printf(sc->dev, "DMA timeout\n");
369 static struct fxp_ident *
370 fxp_find_ident(device_t dev)
374 struct fxp_ident *ident;
376 if (pci_get_vendor(dev) == FXP_VENDORID_INTEL) {
377 devid = pci_get_device(dev);
378 revid = pci_get_revid(dev);
379 for (ident = fxp_ident_table; ident->name != NULL; ident++) {
380 if (ident->devid == devid &&
381 (ident->revid == revid || ident->revid == -1)) {
390 * Return identification string if this device is ours.
393 fxp_probe(device_t dev)
395 struct fxp_ident *ident;
397 ident = fxp_find_ident(dev);
399 device_set_desc(dev, ident->name);
400 return (BUS_PROBE_DEFAULT);
406 fxp_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
413 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg));
415 *addr = segs->ds_addr;
419 fxp_attach(device_t dev)
421 struct fxp_softc *sc;
422 struct fxp_cb_tx *tcbp;
427 uint16_t data, myea[ETHER_ADDR_LEN / 2];
428 u_char eaddr[ETHER_ADDR_LEN];
429 int i, pmc, prefer_iomap;
433 sc = device_get_softc(dev);
435 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
437 callout_init_mtx(&sc->stat_ch, &sc->sc_mtx, 0);
438 ifmedia_init(&sc->sc_media, 0, fxp_serial_ifmedia_upd,
439 fxp_serial_ifmedia_sts);
441 ifp = sc->ifp = if_alloc(IFT_ETHER);
443 device_printf(dev, "can not if_alloc()\n");
449 * Enable bus mastering.
451 pci_enable_busmaster(dev);
452 val = pci_read_config(dev, PCIR_COMMAND, 2);
455 * Figure out which we should try first - memory mapping or i/o mapping?
456 * We default to memory mapping. Then we accept an override from the
457 * command line. Then we check to see which one is enabled.
460 resource_int_value(device_get_name(dev), device_get_unit(dev),
461 "prefer_iomap", &prefer_iomap);
463 sc->fxp_spec = fxp_res_spec_io;
465 sc->fxp_spec = fxp_res_spec_mem;
467 error = bus_alloc_resources(dev, sc->fxp_spec, sc->fxp_res);
469 if (sc->fxp_spec == fxp_res_spec_mem)
470 sc->fxp_spec = fxp_res_spec_io;
472 sc->fxp_spec = fxp_res_spec_mem;
473 error = bus_alloc_resources(dev, sc->fxp_spec, sc->fxp_res);
476 device_printf(dev, "could not allocate resources\n");
482 device_printf(dev, "using %s space register mapping\n",
483 sc->fxp_spec == fxp_res_spec_mem ? "memory" : "I/O");
487 * Put CU/RU idle state and prepare full reset.
489 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET);
491 /* Full reset and disable interrupts. */
492 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SOFTWARE_RESET);
494 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE);
497 * Find out how large of an SEEPROM we have.
499 fxp_autosize_eeprom(sc);
502 * Find out the chip revision; lump all 82557 revs together.
504 sc->ident = fxp_find_ident(dev);
505 if (sc->ident->ich > 0) {
506 /* Assume ICH controllers are 82559. */
507 sc->revision = FXP_REV_82559_A0;
509 fxp_read_eeprom(sc, &data, 5, 1);
510 if ((data >> 8) == 1)
511 sc->revision = FXP_REV_82557;
513 sc->revision = pci_get_revid(dev);
517 * Check availability of WOL. 82559ER does not support WOL.
519 if (sc->revision >= FXP_REV_82558_A4 &&
520 sc->revision != FXP_REV_82559S_A) {
521 fxp_read_eeprom(sc, &data, 10, 1);
522 if ((data & 0x20) != 0 &&
523 pci_find_extcap(sc->dev, PCIY_PMG, &pmc) == 0)
524 sc->flags |= FXP_FLAG_WOLCAP;
527 /* Receiver lock-up workaround detection. */
528 fxp_read_eeprom(sc, &data, 3, 1);
529 if ((data & 0x03) != 0x03) {
530 sc->flags |= FXP_FLAG_RXBUG;
531 device_printf(dev, "Enabling Rx lock-up workaround\n");
535 * Determine whether we must use the 503 serial interface.
537 fxp_read_eeprom(sc, &data, 6, 1);
538 if (sc->revision == FXP_REV_82557 && (data & FXP_PHY_DEVICE_MASK) != 0
539 && (data & FXP_PHY_SERIAL_ONLY))
540 sc->flags |= FXP_FLAG_SERIAL_MEDIA;
544 * Enable workarounds for certain chip revision deficiencies.
546 * Systems based on the ICH2/ICH2-M chip from Intel, and possibly
547 * some systems based a normal 82559 design, have a defect where
548 * the chip can cause a PCI protocol violation if it receives
549 * a CU_RESUME command when it is entering the IDLE state. The
550 * workaround is to disable Dynamic Standby Mode, so the chip never
551 * deasserts CLKRUN#, and always remains in an active state.
553 * See Intel 82801BA/82801BAM Specification Update, Errata #30.
555 if ((sc->ident->ich >= 2 && sc->ident->ich <= 3) ||
556 (sc->ident->ich == 0 && sc->revision >= FXP_REV_82559_A0)) {
557 fxp_read_eeprom(sc, &data, 10, 1);
558 if (data & 0x02) { /* STB enable */
563 "Disabling dynamic standby mode in EEPROM\n");
565 fxp_write_eeprom(sc, &data, 10, 1);
566 device_printf(dev, "New EEPROM ID: 0x%x\n", data);
568 for (i = 0; i < (1 << sc->eeprom_size) - 1; i++) {
569 fxp_read_eeprom(sc, &data, i, 1);
572 i = (1 << sc->eeprom_size) - 1;
573 cksum = 0xBABA - cksum;
574 fxp_read_eeprom(sc, &data, i, 1);
575 fxp_write_eeprom(sc, &cksum, i, 1);
577 "EEPROM checksum @ 0x%x: 0x%x -> 0x%x\n",
581 * If the user elects to continue, try the software
582 * workaround, as it is better than nothing.
584 sc->flags |= FXP_FLAG_CU_RESUME_BUG;
590 * If we are not a 82557 chip, we can enable extended features.
592 if (sc->revision != FXP_REV_82557) {
594 * If MWI is enabled in the PCI configuration, and there
595 * is a valid cacheline size (8 or 16 dwords), then tell
596 * the board to turn on MWI.
598 if (val & PCIM_CMD_MWRICEN &&
599 pci_read_config(dev, PCIR_CACHELNSZ, 1) != 0)
600 sc->flags |= FXP_FLAG_MWI_ENABLE;
602 /* turn on the extended TxCB feature */
603 sc->flags |= FXP_FLAG_EXT_TXCB;
605 /* enable reception of long frames for VLAN */
606 sc->flags |= FXP_FLAG_LONG_PKT_EN;
608 /* a hack to get long VLAN frames on a 82557 */
609 sc->flags |= FXP_FLAG_SAVE_BAD;
612 /* For 82559 or later chips, Rx checksum offload is supported. */
613 if (sc->revision >= FXP_REV_82559_A0) {
614 /* 82559ER does not support Rx checksum offloading. */
615 if (sc->ident->devid != 0x1209)
616 sc->flags |= FXP_FLAG_82559_RXCSUM;
619 * Enable use of extended RFDs and TCBs for 82550
620 * and later chips. Note: we need extended TXCB support
621 * too, but that's already enabled by the code above.
622 * Be careful to do this only on the right devices.
624 if (sc->revision == FXP_REV_82550 || sc->revision == FXP_REV_82550_C ||
625 sc->revision == FXP_REV_82551_E || sc->revision == FXP_REV_82551_F
626 || sc->revision == FXP_REV_82551_10) {
627 sc->rfa_size = sizeof (struct fxp_rfa);
628 sc->tx_cmd = FXP_CB_COMMAND_IPCBXMIT;
629 sc->flags |= FXP_FLAG_EXT_RFA;
630 /* Use extended RFA instead of 82559 checksum mode. */
631 sc->flags &= ~FXP_FLAG_82559_RXCSUM;
633 sc->rfa_size = sizeof (struct fxp_rfa) - FXP_RFAX_LEN;
634 sc->tx_cmd = FXP_CB_COMMAND_XMIT;
638 * Allocate DMA tags and DMA safe memory.
640 sc->maxtxseg = FXP_NTXSEG;
641 sc->maxsegsize = MCLBYTES;
642 if (sc->flags & FXP_FLAG_EXT_RFA) {
644 sc->maxsegsize = FXP_TSO_SEGSIZE;
646 error = bus_dma_tag_create(bus_get_dma_tag(dev), 2, 0,
647 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
648 sc->maxsegsize * sc->maxtxseg + sizeof(struct ether_vlan_header),
649 sc->maxtxseg, sc->maxsegsize, 0,
650 busdma_lock_mutex, &Giant, &sc->fxp_txmtag);
652 device_printf(dev, "could not create TX DMA tag\n");
656 error = bus_dma_tag_create(bus_get_dma_tag(dev), 2, 0,
657 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
658 MCLBYTES, 1, MCLBYTES, 0,
659 busdma_lock_mutex, &Giant, &sc->fxp_rxmtag);
661 device_printf(dev, "could not create RX DMA tag\n");
665 error = bus_dma_tag_create(bus_get_dma_tag(dev), 4, 0,
666 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
667 sizeof(struct fxp_stats), 1, sizeof(struct fxp_stats), 0,
668 busdma_lock_mutex, &Giant, &sc->fxp_stag);
670 device_printf(dev, "could not create stats DMA tag\n");
674 error = bus_dmamem_alloc(sc->fxp_stag, (void **)&sc->fxp_stats,
675 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->fxp_smap);
677 device_printf(dev, "could not allocate stats DMA memory\n");
680 error = bus_dmamap_load(sc->fxp_stag, sc->fxp_smap, sc->fxp_stats,
681 sizeof(struct fxp_stats), fxp_dma_map_addr, &sc->stats_addr, 0);
683 device_printf(dev, "could not load the stats DMA buffer\n");
687 error = bus_dma_tag_create(bus_get_dma_tag(dev), 4, 0,
688 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
689 FXP_TXCB_SZ, 1, FXP_TXCB_SZ, 0,
690 busdma_lock_mutex, &Giant, &sc->cbl_tag);
692 device_printf(dev, "could not create TxCB DMA tag\n");
696 error = bus_dmamem_alloc(sc->cbl_tag, (void **)&sc->fxp_desc.cbl_list,
697 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->cbl_map);
699 device_printf(dev, "could not allocate TxCB DMA memory\n");
703 error = bus_dmamap_load(sc->cbl_tag, sc->cbl_map,
704 sc->fxp_desc.cbl_list, FXP_TXCB_SZ, fxp_dma_map_addr,
705 &sc->fxp_desc.cbl_addr, 0);
707 device_printf(dev, "could not load TxCB DMA buffer\n");
711 error = bus_dma_tag_create(bus_get_dma_tag(dev), 4, 0,
712 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
713 sizeof(struct fxp_cb_mcs), 1, sizeof(struct fxp_cb_mcs), 0,
714 busdma_lock_mutex, &Giant, &sc->mcs_tag);
717 "could not create multicast setup DMA tag\n");
721 error = bus_dmamem_alloc(sc->mcs_tag, (void **)&sc->mcsp,
722 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->mcs_map);
725 "could not allocate multicast setup DMA memory\n");
728 error = bus_dmamap_load(sc->mcs_tag, sc->mcs_map, sc->mcsp,
729 sizeof(struct fxp_cb_mcs), fxp_dma_map_addr, &sc->mcs_addr, 0);
732 "can't load the multicast setup DMA buffer\n");
737 * Pre-allocate the TX DMA maps and setup the pointers to
738 * the TX command blocks.
740 txp = sc->fxp_desc.tx_list;
741 tcbp = sc->fxp_desc.cbl_list;
742 for (i = 0; i < FXP_NTXCB; i++) {
743 txp[i].tx_cb = tcbp + i;
744 error = bus_dmamap_create(sc->fxp_txmtag, 0, &txp[i].tx_map);
746 device_printf(dev, "can't create DMA map for TX\n");
750 error = bus_dmamap_create(sc->fxp_rxmtag, 0, &sc->spare_map);
752 device_printf(dev, "can't create spare DMA map\n");
757 * Pre-allocate our receive buffers.
759 sc->fxp_desc.rx_head = sc->fxp_desc.rx_tail = NULL;
760 for (i = 0; i < FXP_NRFABUFS; i++) {
761 rxp = &sc->fxp_desc.rx_list[i];
762 error = bus_dmamap_create(sc->fxp_rxmtag, 0, &rxp->rx_map);
764 device_printf(dev, "can't create DMA map for RX\n");
767 if (fxp_new_rfabuf(sc, rxp) != 0) {
771 fxp_add_rfabuf(sc, rxp);
777 fxp_read_eeprom(sc, myea, 0, 3);
778 eaddr[0] = myea[0] & 0xff;
779 eaddr[1] = myea[0] >> 8;
780 eaddr[2] = myea[1] & 0xff;
781 eaddr[3] = myea[1] >> 8;
782 eaddr[4] = myea[2] & 0xff;
783 eaddr[5] = myea[2] >> 8;
785 device_printf(dev, "PCI IDs: %04x %04x %04x %04x %04x\n",
786 pci_get_vendor(dev), pci_get_device(dev),
787 pci_get_subvendor(dev), pci_get_subdevice(dev),
789 fxp_read_eeprom(sc, &data, 10, 1);
790 device_printf(dev, "Dynamic Standby mode is %s\n",
791 data & 0x02 ? "enabled" : "disabled");
795 * If this is only a 10Mbps device, then there is no MII, and
796 * the PHY will use a serial interface instead.
798 * The Seeq 80c24 AutoDUPLEX(tm) Ethernet Interface Adapter
799 * doesn't have a programming interface of any sort. The
800 * media is sensed automatically based on how the link partner
801 * is configured. This is, in essence, manual configuration.
803 if (sc->flags & FXP_FLAG_SERIAL_MEDIA) {
804 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_MANUAL, 0, NULL);
805 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_MANUAL);
807 if (mii_phy_probe(dev, &sc->miibus, fxp_ifmedia_upd,
809 device_printf(dev, "MII without any PHY!\n");
815 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
816 ifp->if_init = fxp_init;
818 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
819 ifp->if_ioctl = fxp_ioctl;
820 ifp->if_start = fxp_start;
822 ifp->if_capabilities = ifp->if_capenable = 0;
824 /* Enable checksum offload/TSO for 82550 or better chips */
825 if (sc->flags & FXP_FLAG_EXT_RFA) {
826 ifp->if_hwassist = FXP_CSUM_FEATURES | CSUM_TSO;
827 ifp->if_capabilities |= IFCAP_HWCSUM | IFCAP_TSO4;
828 ifp->if_capenable |= IFCAP_HWCSUM | IFCAP_TSO4;
831 if (sc->flags & FXP_FLAG_82559_RXCSUM) {
832 ifp->if_capabilities |= IFCAP_RXCSUM;
833 ifp->if_capenable |= IFCAP_RXCSUM;
836 if (sc->flags & FXP_FLAG_WOLCAP) {
837 ifp->if_capabilities |= IFCAP_WOL_MAGIC;
838 ifp->if_capenable |= IFCAP_WOL_MAGIC;
841 #ifdef DEVICE_POLLING
842 /* Inform the world we support polling. */
843 ifp->if_capabilities |= IFCAP_POLLING;
847 * Attach the interface.
849 ether_ifattach(ifp, eaddr);
852 * Tell the upper layer(s) we support long frames.
853 * Must appear after the call to ether_ifattach() because
854 * ether_ifattach() sets ifi_hdrlen to the default value.
856 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
857 ifp->if_capabilities |= IFCAP_VLAN_MTU;
858 ifp->if_capenable |= IFCAP_VLAN_MTU; /* the hw bits already set */
859 if ((sc->flags & FXP_FLAG_EXT_RFA) != 0) {
860 ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING |
862 ifp->if_capenable |= IFCAP_VLAN_HWTAGGING |
867 * Let the system queue as many packets as we have available
870 IFQ_SET_MAXLEN(&ifp->if_snd, FXP_NTXCB - 1);
871 ifp->if_snd.ifq_drv_maxlen = FXP_NTXCB - 1;
872 IFQ_SET_READY(&ifp->if_snd);
875 * Hook our interrupt after all initialization is complete.
877 error = bus_setup_intr(dev, sc->fxp_res[1], INTR_TYPE_NET | INTR_MPSAFE,
878 NULL, fxp_intr, sc, &sc->ih);
880 device_printf(dev, "could not setup irq\n");
881 ether_ifdetach(sc->ifp);
886 * Configure hardware to reject magic frames otherwise
887 * system will hang on recipt of magic frames.
889 if ((sc->flags & FXP_FLAG_WOLCAP) != 0) {
891 /* Clear wakeup events. */
892 CSR_WRITE_1(sc, FXP_CSR_PMDR, CSR_READ_1(sc, FXP_CSR_PMDR));
905 * Release all resources. The softc lock should not be held and the
906 * interrupt should already be torn down.
909 fxp_release(struct fxp_softc *sc)
915 FXP_LOCK_ASSERT(sc, MA_NOTOWNED);
916 KASSERT(sc->ih == NULL,
917 ("fxp_release() called with intr handle still active"));
919 device_delete_child(sc->dev, sc->miibus);
920 bus_generic_detach(sc->dev);
921 ifmedia_removeall(&sc->sc_media);
922 if (sc->fxp_desc.cbl_list) {
923 bus_dmamap_unload(sc->cbl_tag, sc->cbl_map);
924 bus_dmamem_free(sc->cbl_tag, sc->fxp_desc.cbl_list,
928 bus_dmamap_unload(sc->fxp_stag, sc->fxp_smap);
929 bus_dmamem_free(sc->fxp_stag, sc->fxp_stats, sc->fxp_smap);
932 bus_dmamap_unload(sc->mcs_tag, sc->mcs_map);
933 bus_dmamem_free(sc->mcs_tag, sc->mcsp, sc->mcs_map);
935 bus_release_resources(sc->dev, sc->fxp_spec, sc->fxp_res);
936 if (sc->fxp_rxmtag) {
937 for (i = 0; i < FXP_NRFABUFS; i++) {
938 rxp = &sc->fxp_desc.rx_list[i];
939 if (rxp->rx_mbuf != NULL) {
940 bus_dmamap_sync(sc->fxp_rxmtag, rxp->rx_map,
941 BUS_DMASYNC_POSTREAD);
942 bus_dmamap_unload(sc->fxp_rxmtag, rxp->rx_map);
943 m_freem(rxp->rx_mbuf);
945 bus_dmamap_destroy(sc->fxp_rxmtag, rxp->rx_map);
947 bus_dmamap_destroy(sc->fxp_rxmtag, sc->spare_map);
948 bus_dma_tag_destroy(sc->fxp_rxmtag);
950 if (sc->fxp_txmtag) {
951 for (i = 0; i < FXP_NTXCB; i++) {
952 txp = &sc->fxp_desc.tx_list[i];
953 if (txp->tx_mbuf != NULL) {
954 bus_dmamap_sync(sc->fxp_txmtag, txp->tx_map,
955 BUS_DMASYNC_POSTWRITE);
956 bus_dmamap_unload(sc->fxp_txmtag, txp->tx_map);
957 m_freem(txp->tx_mbuf);
959 bus_dmamap_destroy(sc->fxp_txmtag, txp->tx_map);
961 bus_dma_tag_destroy(sc->fxp_txmtag);
964 bus_dma_tag_destroy(sc->fxp_stag);
966 bus_dma_tag_destroy(sc->cbl_tag);
968 bus_dma_tag_destroy(sc->mcs_tag);
972 mtx_destroy(&sc->sc_mtx);
979 fxp_detach(device_t dev)
981 struct fxp_softc *sc = device_get_softc(dev);
983 #ifdef DEVICE_POLLING
984 if (sc->ifp->if_capenable & IFCAP_POLLING)
985 ether_poll_deregister(sc->ifp);
990 * Stop DMA and drop transmit queue, but disable interrupts first.
992 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE);
995 callout_drain(&sc->stat_ch);
998 * Close down routes etc.
1000 ether_ifdetach(sc->ifp);
1003 * Unhook interrupt before dropping lock. This is to prevent
1004 * races with fxp_intr().
1006 bus_teardown_intr(sc->dev, sc->fxp_res[1], sc->ih);
1009 /* Release our allocated resources. */
1015 * Device shutdown routine. Called at system shutdown after sync. The
1016 * main purpose of this routine is to shut off receiver DMA so that
1017 * kernel memory doesn't get clobbered during warmboot.
1020 fxp_shutdown(device_t dev)
1024 * Make sure that DMA is disabled prior to reboot. Not doing
1025 * do could allow DMA to corrupt kernel memory during the
1026 * reboot before the driver initializes.
1028 return (fxp_suspend(dev));
1032 * Device suspend routine. Stop the interface and save some PCI
1033 * settings in case the BIOS doesn't restore them properly on
1037 fxp_suspend(device_t dev)
1039 struct fxp_softc *sc = device_get_softc(dev);
1047 if (pci_find_extcap(sc->dev, PCIY_PMG, &pmc) == 0) {
1048 pmstat = pci_read_config(sc->dev, pmc + PCIR_POWER_STATUS, 2);
1049 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE);
1050 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) {
1052 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
1053 sc->flags |= FXP_FLAG_WOL;
1054 /* Reconfigure hardware to accept magic frames. */
1057 pci_write_config(sc->dev, pmc + PCIR_POWER_STATUS, pmstat, 2);
1068 * Device resume routine. re-enable busmastering, and restart the interface if
1072 fxp_resume(device_t dev)
1074 struct fxp_softc *sc = device_get_softc(dev);
1075 struct ifnet *ifp = sc->ifp;
1081 if (pci_find_extcap(sc->dev, PCIY_PMG, &pmc) == 0) {
1082 sc->flags &= ~FXP_FLAG_WOL;
1083 pmstat = pci_read_config(sc->dev, pmc + PCIR_POWER_STATUS, 2);
1084 /* Disable PME and clear PME status. */
1085 pmstat &= ~PCIM_PSTAT_PMEENABLE;
1086 pci_write_config(sc->dev, pmc + PCIR_POWER_STATUS, pmstat, 2);
1087 if ((sc->flags & FXP_FLAG_WOLCAP) != 0)
1088 CSR_WRITE_1(sc, FXP_CSR_PMDR,
1089 CSR_READ_1(sc, FXP_CSR_PMDR));
1092 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET);
1095 /* reinitialize interface if necessary */
1096 if (ifp->if_flags & IFF_UP)
1106 fxp_eeprom_shiftin(struct fxp_softc *sc, int data, int length)
1114 for (x = 1 << (length - 1); x; x >>= 1) {
1116 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI;
1118 reg = FXP_EEPROM_EECS;
1119 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
1121 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK);
1123 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
1129 * Read from the serial EEPROM. Basically, you manually shift in
1130 * the read opcode (one bit at a time) and then shift in the address,
1131 * and then you shift out the data (all of this one bit at a time).
1132 * The word size is 16 bits, so you have to provide the address for
1133 * every 16 bits of data.
1136 fxp_eeprom_getword(struct fxp_softc *sc, int offset, int autosize)
1141 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
1143 * Shift in read opcode.
1145 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_READ, 3);
1150 for (x = 1 << (sc->eeprom_size - 1); x; x >>= 1) {
1152 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI;
1154 reg = FXP_EEPROM_EECS;
1155 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
1157 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK);
1159 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
1161 reg = CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO;
1163 if (autosize && reg == 0) {
1164 sc->eeprom_size = data;
1172 reg = FXP_EEPROM_EECS;
1173 for (x = 1 << 15; x; x >>= 1) {
1174 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK);
1176 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO)
1178 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
1181 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
1188 fxp_eeprom_putword(struct fxp_softc *sc, int offset, uint16_t data)
1193 * Erase/write enable.
1195 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
1196 fxp_eeprom_shiftin(sc, 0x4, 3);
1197 fxp_eeprom_shiftin(sc, 0x03 << (sc->eeprom_size - 2), sc->eeprom_size);
1198 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
1201 * Shift in write opcode, address, data.
1203 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
1204 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_WRITE, 3);
1205 fxp_eeprom_shiftin(sc, offset, sc->eeprom_size);
1206 fxp_eeprom_shiftin(sc, data, 16);
1207 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
1210 * Wait for EEPROM to finish up.
1212 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
1214 for (i = 0; i < 1000; i++) {
1215 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO)
1219 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
1222 * Erase/write disable.
1224 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
1225 fxp_eeprom_shiftin(sc, 0x4, 3);
1226 fxp_eeprom_shiftin(sc, 0, sc->eeprom_size);
1227 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
1234 * Figure out EEPROM size.
1236 * 559's can have either 64-word or 256-word EEPROMs, the 558
1237 * datasheet only talks about 64-word EEPROMs, and the 557 datasheet
1238 * talks about the existance of 16 to 256 word EEPROMs.
1240 * The only known sizes are 64 and 256, where the 256 version is used
1241 * by CardBus cards to store CIS information.
1243 * The address is shifted in msb-to-lsb, and after the last
1244 * address-bit the EEPROM is supposed to output a `dummy zero' bit,
1245 * after which follows the actual data. We try to detect this zero, by
1246 * probing the data-out bit in the EEPROM control register just after
1247 * having shifted in a bit. If the bit is zero, we assume we've
1248 * shifted enough address bits. The data-out should be tri-state,
1249 * before this, which should translate to a logical one.
1252 fxp_autosize_eeprom(struct fxp_softc *sc)
1255 /* guess maximum size of 256 words */
1256 sc->eeprom_size = 8;
1259 (void) fxp_eeprom_getword(sc, 0, 1);
1263 fxp_read_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words)
1267 for (i = 0; i < words; i++)
1268 data[i] = fxp_eeprom_getword(sc, offset + i, 0);
1272 fxp_write_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words)
1276 for (i = 0; i < words; i++)
1277 fxp_eeprom_putword(sc, offset + i, data[i]);
1281 * Grab the softc lock and call the real fxp_start_body() routine
1284 fxp_start(struct ifnet *ifp)
1286 struct fxp_softc *sc = ifp->if_softc;
1289 fxp_start_body(ifp);
1294 * Start packet transmission on the interface.
1295 * This routine must be called with the softc lock held, and is an
1296 * internal entry point only.
1299 fxp_start_body(struct ifnet *ifp)
1301 struct fxp_softc *sc = ifp->if_softc;
1302 struct mbuf *mb_head;
1305 FXP_LOCK_ASSERT(sc, MA_OWNED);
1307 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
1311 if (sc->tx_queued > FXP_NTXCB_HIWAT)
1314 * We're finished if there is nothing more to add to the list or if
1315 * we're all filled up with buffers to transmit.
1316 * NOTE: One TxCB is reserved to guarantee that fxp_mc_setup() can add
1317 * a NOP command when needed.
1320 while (!IFQ_DRV_IS_EMPTY(&ifp->if_snd) &&
1321 sc->tx_queued < FXP_NTXCB - 1) {
1324 * Grab a packet to transmit.
1326 IFQ_DRV_DEQUEUE(&ifp->if_snd, mb_head);
1327 if (mb_head == NULL)
1330 if (fxp_encap(sc, &mb_head)) {
1331 if (mb_head == NULL)
1333 IFQ_DRV_PREPEND(&ifp->if_snd, mb_head);
1334 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1338 * Pass packet to bpf if there is a listener.
1340 BPF_MTAP(ifp, mb_head);
1344 * We're finished. If we added to the list, issue a RESUME to get DMA
1345 * going again if suspended.
1348 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map,
1349 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1351 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME);
1353 * Set a 5 second timer just in case we don't hear
1354 * from the card again.
1356 sc->watchdog_timer = 5;
1361 fxp_encap(struct fxp_softc *sc, struct mbuf **m_head)
1366 struct fxp_cb_tx *cbp;
1368 bus_dma_segment_t segs[FXP_NTXSEG];
1369 int error, i, nseg, tcp_payload;
1371 FXP_LOCK_ASSERT(sc, MA_OWNED);
1377 * Get pointer to next available tx desc.
1379 txp = sc->fxp_desc.tx_last->tx_next;
1382 * A note in Appendix B of the Intel 8255x 10/100 Mbps
1383 * Ethernet Controller Family Open Source Software
1384 * Developer Manual says:
1385 * Using software parsing is only allowed with legal
1386 * TCP/IP or UDP/IP packets.
1388 * For all other datagrams, hardware parsing must
1390 * Software parsing appears to truncate ICMP and
1391 * fragmented UDP packets that contain one to three
1392 * bytes in the second (and final) mbuf of the packet.
1394 if (sc->flags & FXP_FLAG_EXT_RFA)
1395 txp->tx_cb->ipcb_ip_activation_high =
1396 FXP_IPCB_HARDWAREPARSING_ENABLE;
1399 if (m->m_pkthdr.csum_flags & CSUM_TSO) {
1401 * 82550/82551 requires ethernet/IP/TCP headers must be
1402 * contained in the first active transmit buffer.
1404 struct ether_header *eh;
1406 uint32_t ip_off, poff;
1408 if (M_WRITABLE(*m_head) == 0) {
1409 /* Get a writable copy. */
1410 m = m_dup(*m_head, M_DONTWAIT);
1418 ip_off = sizeof(struct ether_header);
1419 m = m_pullup(*m_head, ip_off);
1424 eh = mtod(m, struct ether_header *);
1425 /* Check the existence of VLAN tag. */
1426 if (eh->ether_type == htons(ETHERTYPE_VLAN)) {
1427 ip_off = sizeof(struct ether_vlan_header);
1428 m = m_pullup(m, ip_off);
1434 m = m_pullup(m, ip_off + sizeof(struct ip));
1439 ip = (struct ip *)(mtod(m, char *) + ip_off);
1440 poff = ip_off + (ip->ip_hl << 2);
1441 m = m_pullup(m, poff + sizeof(struct tcphdr));
1446 tcp = (struct tcphdr *)(mtod(m, char *) + poff);
1447 m = m_pullup(m, poff + sizeof(struct tcphdr) + tcp->th_off);
1454 * Since 82550/82551 doesn't modify IP length and pseudo
1455 * checksum in the first frame driver should compute it.
1458 ip->ip_len = htons(m->m_pkthdr.tso_segsz + (ip->ip_hl << 2) +
1459 (tcp->th_off << 2));
1460 tcp->th_sum = in_pseudo(ip->ip_src.s_addr, ip->ip_dst.s_addr,
1461 htons(IPPROTO_TCP + (tcp->th_off << 2) +
1462 m->m_pkthdr.tso_segsz));
1463 /* Compute total TCP payload. */
1464 tcp_payload = m->m_pkthdr.len - ip_off - (ip->ip_hl << 2);
1465 tcp_payload -= tcp->th_off << 2;
1467 } else if (m->m_pkthdr.csum_flags & FXP_CSUM_FEATURES) {
1469 * Deal with TCP/IP checksum offload. Note that
1470 * in order for TCP checksum offload to work,
1471 * the pseudo header checksum must have already
1472 * been computed and stored in the checksum field
1473 * in the TCP header. The stack should have
1474 * already done this for us.
1476 txp->tx_cb->ipcb_ip_schedule = FXP_IPCB_TCPUDP_CHECKSUM_ENABLE;
1477 if (m->m_pkthdr.csum_flags & CSUM_TCP)
1478 txp->tx_cb->ipcb_ip_schedule |= FXP_IPCB_TCP_PACKET;
1480 #ifdef FXP_IP_CSUM_WAR
1482 * XXX The 82550 chip appears to have trouble
1483 * dealing with IP header checksums in very small
1484 * datagrams, namely fragments from 1 to 3 bytes
1485 * in size. For example, say you want to transmit
1486 * a UDP packet of 1473 bytes. The packet will be
1487 * fragmented over two IP datagrams, the latter
1488 * containing only one byte of data. The 82550 will
1489 * botch the header checksum on the 1-byte fragment.
1490 * As long as the datagram contains 4 or more bytes
1491 * of data, you're ok.
1493 * The following code attempts to work around this
1494 * problem: if the datagram is less than 38 bytes
1495 * in size (14 bytes ether header, 20 bytes IP header,
1496 * plus 4 bytes of data), we punt and compute the IP
1497 * header checksum by hand. This workaround doesn't
1498 * work very well, however, since it can be fooled
1499 * by things like VLAN tags and IP options that make
1500 * the header sizes/offsets vary.
1503 if (m->m_pkthdr.csum_flags & CSUM_IP) {
1504 if (m->m_pkthdr.len < 38) {
1506 m->m_data += ETHER_HDR_LEN;
1507 ip = mtod(m, struct ip *);
1508 ip->ip_sum = in_cksum(m, ip->ip_hl << 2);
1509 m->m_data -= ETHER_HDR_LEN;
1510 m->m_pkthdr.csum_flags &= ~CSUM_IP;
1512 txp->tx_cb->ipcb_ip_activation_high =
1513 FXP_IPCB_HARDWAREPARSING_ENABLE;
1514 txp->tx_cb->ipcb_ip_schedule |=
1515 FXP_IPCB_IP_CHECKSUM_ENABLE;
1521 error = bus_dmamap_load_mbuf_sg(sc->fxp_txmtag, txp->tx_map, *m_head,
1523 if (error == EFBIG) {
1524 m = m_collapse(*m_head, M_DONTWAIT, sc->maxtxseg);
1531 error = bus_dmamap_load_mbuf_sg(sc->fxp_txmtag, txp->tx_map,
1532 *m_head, segs, &nseg, 0);
1538 } else if (error != 0)
1546 KASSERT(nseg <= sc->maxtxseg, ("too many DMA segments"));
1547 bus_dmamap_sync(sc->fxp_txmtag, txp->tx_map, BUS_DMASYNC_PREWRITE);
1550 for (i = 0; i < nseg; i++) {
1552 * If this is an 82550/82551, then we're using extended
1553 * TxCBs _and_ we're using checksum offload. This means
1554 * that the TxCB is really an IPCB. One major difference
1555 * between the two is that with plain extended TxCBs,
1556 * the bottom half of the TxCB contains two entries from
1557 * the TBD array, whereas IPCBs contain just one entry:
1558 * one entry (8 bytes) has been sacrificed for the TCP/IP
1559 * checksum offload control bits. So to make things work
1560 * right, we have to start filling in the TBD array
1561 * starting from a different place depending on whether
1562 * the chip is an 82550/82551 or not.
1564 if (sc->flags & FXP_FLAG_EXT_RFA) {
1565 cbp->tbd[i + 1].tb_addr = htole32(segs[i].ds_addr);
1566 cbp->tbd[i + 1].tb_size = htole32(segs[i].ds_len);
1568 cbp->tbd[i].tb_addr = htole32(segs[i].ds_addr);
1569 cbp->tbd[i].tb_size = htole32(segs[i].ds_len);
1572 if (sc->flags & FXP_FLAG_EXT_RFA) {
1573 /* Configure dynamic TBD for 82550/82551. */
1574 cbp->tbd_number = 0xFF;
1575 cbp->tbd[nseg].tb_size |= htole32(0x8000);
1577 cbp->tbd_number = nseg;
1578 /* Configure TSO. */
1579 if (m->m_pkthdr.csum_flags & CSUM_TSO) {
1580 cbp->tbd[-1].tb_size = htole32(m->m_pkthdr.tso_segsz << 16);
1581 cbp->tbd[1].tb_size |= htole32(tcp_payload << 16);
1582 cbp->ipcb_ip_schedule |= FXP_IPCB_LARGESEND_ENABLE |
1583 FXP_IPCB_IP_CHECKSUM_ENABLE |
1584 FXP_IPCB_TCP_PACKET |
1585 FXP_IPCB_TCPUDP_CHECKSUM_ENABLE;
1587 /* Configure VLAN hardware tag insertion. */
1588 if ((m->m_flags & M_VLANTAG) != 0) {
1589 cbp->ipcb_vlan_id = htons(m->m_pkthdr.ether_vtag);
1590 txp->tx_cb->ipcb_ip_activation_high |=
1591 FXP_IPCB_INSERTVLAN_ENABLE;
1595 txp->tx_cb->cb_status = 0;
1596 txp->tx_cb->byte_count = 0;
1597 if (sc->tx_queued != FXP_CXINT_THRESH - 1)
1598 txp->tx_cb->cb_command =
1599 htole16(sc->tx_cmd | FXP_CB_COMMAND_SF |
1602 txp->tx_cb->cb_command =
1603 htole16(sc->tx_cmd | FXP_CB_COMMAND_SF |
1604 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I);
1605 if ((m->m_pkthdr.csum_flags & CSUM_TSO) == 0)
1606 txp->tx_cb->tx_threshold = tx_threshold;
1609 * Advance the end of list forward.
1614 * On platforms which can't access memory in 16-bit
1615 * granularities, we must prevent the card from DMA'ing
1616 * up the status while we update the command field.
1617 * This could cause us to overwrite the completion status.
1618 * XXX This is probably bogus and we're _not_ looking
1619 * for atomicity here.
1621 atomic_clear_16(&sc->fxp_desc.tx_last->tx_cb->cb_command,
1622 htole16(FXP_CB_COMMAND_S));
1624 sc->fxp_desc.tx_last->tx_cb->cb_command &= htole16(~FXP_CB_COMMAND_S);
1625 #endif /*__alpha__*/
1626 sc->fxp_desc.tx_last = txp;
1629 * Advance the beginning of the list forward if there are
1630 * no other packets queued (when nothing is queued, tx_first
1631 * sits on the last TxCB that was sent out).
1633 if (sc->tx_queued == 0)
1634 sc->fxp_desc.tx_first = txp;
1641 #ifdef DEVICE_POLLING
1642 static poll_handler_t fxp_poll;
1645 fxp_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
1647 struct fxp_softc *sc = ifp->if_softc;
1652 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) {
1657 statack = FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA |
1659 if (cmd == POLL_AND_CHECK_STATUS) {
1662 tmp = CSR_READ_1(sc, FXP_CSR_SCB_STATACK);
1663 if (tmp == 0xff || tmp == 0) {
1665 return (rx_npkts); /* nothing to do */
1668 /* ack what we can */
1670 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, tmp);
1673 rx_npkts = fxp_intr_body(sc, ifp, statack, count);
1677 #endif /* DEVICE_POLLING */
1680 * Process interface interrupts.
1685 struct fxp_softc *sc = xsc;
1686 struct ifnet *ifp = sc->ifp;
1690 if (sc->suspended) {
1695 #ifdef DEVICE_POLLING
1696 if (ifp->if_capenable & IFCAP_POLLING) {
1701 while ((statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK)) != 0) {
1703 * It should not be possible to have all bits set; the
1704 * FXP_SCB_INTR_SWI bit always returns 0 on a read. If
1705 * all bits are set, this may indicate that the card has
1706 * been physically ejected, so ignore it.
1708 if (statack == 0xff) {
1714 * First ACK all the interrupts in this pass.
1716 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack);
1717 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
1718 fxp_intr_body(sc, ifp, statack, -1);
1724 fxp_txeof(struct fxp_softc *sc)
1730 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map,
1731 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1732 for (txp = sc->fxp_desc.tx_first; sc->tx_queued &&
1733 (le16toh(txp->tx_cb->cb_status) & FXP_CB_STATUS_C) != 0;
1734 txp = txp->tx_next) {
1735 if (txp->tx_mbuf != NULL) {
1736 bus_dmamap_sync(sc->fxp_txmtag, txp->tx_map,
1737 BUS_DMASYNC_POSTWRITE);
1738 bus_dmamap_unload(sc->fxp_txmtag, txp->tx_map);
1739 m_freem(txp->tx_mbuf);
1740 txp->tx_mbuf = NULL;
1741 /* clear this to reset csum offload bits */
1742 txp->tx_cb->tbd[0].tb_addr = 0;
1745 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1747 sc->fxp_desc.tx_first = txp;
1748 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map,
1749 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1750 if (sc->tx_queued == 0)
1751 sc->watchdog_timer = 0;
1755 fxp_rxcsum(struct fxp_softc *sc, struct ifnet *ifp, struct mbuf *m,
1756 uint16_t status, int pos)
1758 struct ether_header *eh;
1761 int32_t hlen, len, pktlen, temp32;
1762 uint16_t csum, *opts;
1764 if ((sc->flags & FXP_FLAG_82559_RXCSUM) == 0) {
1765 if ((status & FXP_RFA_STATUS_PARSE) != 0) {
1766 if (status & FXP_RFDX_CS_IP_CSUM_BIT_VALID)
1767 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
1768 if (status & FXP_RFDX_CS_IP_CSUM_VALID)
1769 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
1770 if ((status & FXP_RFDX_CS_TCPUDP_CSUM_BIT_VALID) &&
1771 (status & FXP_RFDX_CS_TCPUDP_CSUM_VALID)) {
1772 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID |
1774 m->m_pkthdr.csum_data = 0xffff;
1780 pktlen = m->m_pkthdr.len;
1781 if (pktlen < sizeof(struct ether_header) + sizeof(struct ip))
1783 eh = mtod(m, struct ether_header *);
1784 if (eh->ether_type != htons(ETHERTYPE_IP))
1786 ip = (struct ip *)(eh + 1);
1787 if (ip->ip_v != IPVERSION)
1790 hlen = ip->ip_hl << 2;
1791 pktlen -= sizeof(struct ether_header);
1792 if (hlen < sizeof(struct ip))
1794 if (ntohs(ip->ip_len) < hlen)
1796 if (ntohs(ip->ip_len) != pktlen)
1798 if (ip->ip_off & htons(IP_MF | IP_OFFMASK))
1799 return; /* can't handle fragmented packet */
1803 if (pktlen < (hlen + sizeof(struct tcphdr)))
1807 if (pktlen < (hlen + sizeof(struct udphdr)))
1809 uh = (struct udphdr *)((caddr_t)ip + hlen);
1810 if (uh->uh_sum == 0)
1811 return; /* no checksum */
1816 /* Extract computed checksum. */
1817 csum = be16dec(mtod(m, char *) + pos);
1818 /* checksum fixup for IP options */
1819 len = hlen - sizeof(struct ip);
1821 opts = (uint16_t *)(ip + 1);
1822 for (; len > 0; len -= sizeof(uint16_t), opts++) {
1823 temp32 = csum - *opts;
1824 temp32 = (temp32 >> 16) + (temp32 & 65535);
1825 csum = temp32 & 65535;
1828 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID;
1829 m->m_pkthdr.csum_data = csum;
1833 fxp_intr_body(struct fxp_softc *sc, struct ifnet *ifp, uint8_t statack,
1838 struct fxp_rfa *rfa;
1839 int rnr = (statack & FXP_SCB_STATACK_RNR) ? 1 : 0;
1844 FXP_LOCK_ASSERT(sc, MA_OWNED);
1848 #ifdef DEVICE_POLLING
1849 /* Pick up a deferred RNR condition if `count' ran out last time. */
1850 if (sc->flags & FXP_FLAG_DEFERRED_RNR) {
1851 sc->flags &= ~FXP_FLAG_DEFERRED_RNR;
1857 * Free any finished transmit mbuf chains.
1859 * Handle the CNA event likt a CXTNO event. It used to
1860 * be that this event (control unit not ready) was not
1861 * encountered, but it is now with the SMPng modifications.
1862 * The exact sequence of events that occur when the interface
1863 * is brought up are different now, and if this event
1864 * goes unhandled, the configuration/rxfilter setup sequence
1865 * can stall for several seconds. The result is that no
1866 * packets go out onto the wire for about 5 to 10 seconds
1867 * after the interface is ifconfig'ed for the first time.
1869 if (statack & (FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA))
1873 * Try to start more packets transmitting.
1875 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1876 fxp_start_body(ifp);
1879 * Just return if nothing happened on the receive side.
1881 if (!rnr && (statack & FXP_SCB_STATACK_FR) == 0)
1885 * Process receiver interrupts. If a no-resource (RNR)
1886 * condition exists, get whatever packets we can and
1887 * re-start the receiver.
1889 * When using polling, we do not process the list to completion,
1890 * so when we get an RNR interrupt we must defer the restart
1891 * until we hit the last buffer with the C bit set.
1892 * If we run out of cycles and rfa_headm has the C bit set,
1893 * record the pending RNR in the FXP_FLAG_DEFERRED_RNR flag so
1894 * that the info will be used in the subsequent polling cycle.
1897 rxp = sc->fxp_desc.rx_head;
1899 rfa = (struct fxp_rfa *)(m->m_ext.ext_buf +
1900 RFA_ALIGNMENT_FUDGE);
1901 bus_dmamap_sync(sc->fxp_rxmtag, rxp->rx_map,
1902 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1904 #ifdef DEVICE_POLLING /* loop at most count times if count >=0 */
1905 if (count >= 0 && count-- == 0) {
1907 /* Defer RNR processing until the next time. */
1908 sc->flags |= FXP_FLAG_DEFERRED_RNR;
1913 #endif /* DEVICE_POLLING */
1915 status = le16toh(rfa->rfa_status);
1916 if ((status & FXP_RFA_STATUS_C) == 0)
1919 if ((status & FXP_RFA_STATUS_RNR) != 0)
1922 * Advance head forward.
1924 sc->fxp_desc.rx_head = rxp->rx_next;
1927 * Add a new buffer to the receive chain.
1928 * If this fails, the old buffer is recycled
1931 if (fxp_new_rfabuf(sc, rxp) == 0) {
1935 * Fetch packet length (the top 2 bits of
1936 * actual_size are flags set by the controller
1937 * upon completion), and drop the packet in case
1938 * of bogus length or CRC errors.
1940 total_len = le16toh(rfa->actual_size) & 0x3fff;
1941 if ((sc->flags & FXP_FLAG_82559_RXCSUM) != 0 &&
1942 (ifp->if_capenable & IFCAP_RXCSUM) != 0) {
1943 /* Adjust for appended checksum bytes. */
1946 if (total_len < sizeof(struct ether_header) ||
1947 total_len > (MCLBYTES - RFA_ALIGNMENT_FUDGE -
1949 status & (FXP_RFA_STATUS_CRC |
1950 FXP_RFA_STATUS_ALIGN)) {
1952 fxp_add_rfabuf(sc, rxp);
1956 m->m_pkthdr.len = m->m_len = total_len;
1957 m->m_pkthdr.rcvif = ifp;
1959 /* Do IP checksum checking. */
1960 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0)
1961 fxp_rxcsum(sc, ifp, m, status, total_len);
1962 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0 &&
1963 (status & FXP_RFA_STATUS_VLAN) != 0) {
1964 m->m_pkthdr.ether_vtag =
1965 ntohs(rfa->rfax_vlan_id);
1966 m->m_flags |= M_VLANTAG;
1969 * Drop locks before calling if_input() since it
1970 * may re-enter fxp_start() in the netisr case.
1971 * This would result in a lock reversal. Better
1972 * performance might be obtained by chaining all
1973 * packets received, dropping the lock, and then
1974 * calling if_input() on each one.
1977 (*ifp->if_input)(ifp, m);
1980 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
1983 /* Reuse RFA and loaded DMA map. */
1985 fxp_discard_rfabuf(sc, rxp);
1987 fxp_add_rfabuf(sc, rxp);
1991 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL,
1992 sc->fxp_desc.rx_head->rx_addr);
1993 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START);
1999 fxp_update_stats(struct fxp_softc *sc)
2001 struct ifnet *ifp = sc->ifp;
2002 struct fxp_stats *sp = sc->fxp_stats;
2003 struct fxp_hwstats *hsp;
2006 FXP_LOCK_ASSERT(sc, MA_OWNED);
2008 bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap,
2009 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2010 /* Update statistical counters. */
2011 if (sc->revision >= FXP_REV_82559_A0)
2012 status = &sp->completion_status;
2013 else if (sc->revision >= FXP_REV_82558_A4)
2014 status = (uint32_t *)&sp->tx_tco;
2016 status = &sp->tx_pause;
2017 if (*status == htole32(FXP_STATS_DR_COMPLETE)) {
2018 hsp = &sc->fxp_hwstats;
2019 hsp->tx_good += le32toh(sp->tx_good);
2020 hsp->tx_maxcols += le32toh(sp->tx_maxcols);
2021 hsp->tx_latecols += le32toh(sp->tx_latecols);
2022 hsp->tx_underruns += le32toh(sp->tx_underruns);
2023 hsp->tx_lostcrs += le32toh(sp->tx_lostcrs);
2024 hsp->tx_deffered += le32toh(sp->tx_deffered);
2025 hsp->tx_single_collisions += le32toh(sp->tx_single_collisions);
2026 hsp->tx_multiple_collisions +=
2027 le32toh(sp->tx_multiple_collisions);
2028 hsp->tx_total_collisions += le32toh(sp->tx_total_collisions);
2029 hsp->rx_good += le32toh(sp->rx_good);
2030 hsp->rx_crc_errors += le32toh(sp->rx_crc_errors);
2031 hsp->rx_alignment_errors += le32toh(sp->rx_alignment_errors);
2032 hsp->rx_rnr_errors += le32toh(sp->rx_rnr_errors);
2033 hsp->rx_overrun_errors += le32toh(sp->rx_overrun_errors);
2034 hsp->rx_cdt_errors += le32toh(sp->rx_cdt_errors);
2035 hsp->rx_shortframes += le32toh(sp->rx_shortframes);
2036 hsp->tx_pause += le32toh(sp->tx_pause);
2037 hsp->rx_pause += le32toh(sp->rx_pause);
2038 hsp->rx_controls += le32toh(sp->rx_controls);
2039 hsp->tx_tco += le16toh(sp->tx_tco);
2040 hsp->rx_tco += le16toh(sp->rx_tco);
2042 ifp->if_opackets += le32toh(sp->tx_good);
2043 ifp->if_collisions += le32toh(sp->tx_total_collisions);
2045 ifp->if_ipackets += le32toh(sp->rx_good);
2046 sc->rx_idle_secs = 0;
2047 } else if (sc->flags & FXP_FLAG_RXBUG) {
2049 * Receiver's been idle for another second.
2054 le32toh(sp->rx_crc_errors) +
2055 le32toh(sp->rx_alignment_errors) +
2056 le32toh(sp->rx_rnr_errors) +
2057 le32toh(sp->rx_overrun_errors);
2059 * If any transmit underruns occured, bump up the transmit
2060 * threshold by another 512 bytes (64 * 8).
2062 if (sp->tx_underruns) {
2063 ifp->if_oerrors += le32toh(sp->tx_underruns);
2064 if (tx_threshold < 192)
2068 bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap,
2069 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2074 * Update packet in/out/collision statistics. The i82557 doesn't
2075 * allow you to access these counters without doing a fairly
2076 * expensive DMA to get _all_ of the statistics it maintains, so
2077 * we do this operation here only once per second. The statistics
2078 * counters in the kernel are updated from the previous dump-stats
2079 * DMA and then a new dump-stats DMA is started. The on-chip
2080 * counters are zeroed when the DMA completes. If we can't start
2081 * the DMA immediately, we don't wait - we just prepare to read
2082 * them again next time.
2087 struct fxp_softc *sc = xsc;
2088 struct ifnet *ifp = sc->ifp;
2090 FXP_LOCK_ASSERT(sc, MA_OWNED);
2092 /* Update statistical counters. */
2093 fxp_update_stats(sc);
2096 * Release any xmit buffers that have completed DMA. This isn't
2097 * strictly necessary to do here, but it's advantagous for mbufs
2098 * with external storage to be released in a timely manner rather
2099 * than being defered for a potentially long time. This limits
2100 * the delay to a maximum of one second.
2105 * If we haven't received any packets in FXP_MAC_RX_IDLE seconds,
2106 * then assume the receiver has locked up and attempt to clear
2107 * the condition by reprogramming the multicast filter. This is
2108 * a work-around for a bug in the 82557 where the receiver locks
2109 * up if it gets certain types of garbage in the syncronization
2110 * bits prior to the packet header. This bug is supposed to only
2111 * occur in 10Mbps mode, but has been seen to occur in 100Mbps
2112 * mode as well (perhaps due to a 10/100 speed transition).
2114 if (sc->rx_idle_secs > FXP_MAX_RX_IDLE) {
2115 sc->rx_idle_secs = 0;
2116 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
2121 * If there is no pending command, start another stats
2122 * dump. Otherwise punt for now.
2124 if (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) == 0) {
2126 * Start another stats dump.
2128 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMPRESET);
2130 if (sc->miibus != NULL)
2131 mii_tick(device_get_softc(sc->miibus));
2134 * Check that chip hasn't hung.
2139 * Schedule another timeout one second from now.
2141 callout_reset(&sc->stat_ch, hz, fxp_tick, sc);
2145 * Stop the interface. Cancels the statistics updater and resets
2149 fxp_stop(struct fxp_softc *sc)
2151 struct ifnet *ifp = sc->ifp;
2155 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
2156 sc->watchdog_timer = 0;
2159 * Cancel stats updater.
2161 callout_stop(&sc->stat_ch);
2164 * Preserve PCI configuration, configure, IA/multicast
2165 * setup and put RU and CU into idle state.
2167 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET);
2169 /* Disable interrupts. */
2170 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE);
2172 fxp_update_stats(sc);
2175 * Release any xmit buffers.
2177 txp = sc->fxp_desc.tx_list;
2179 for (i = 0; i < FXP_NTXCB; i++) {
2180 if (txp[i].tx_mbuf != NULL) {
2181 bus_dmamap_sync(sc->fxp_txmtag, txp[i].tx_map,
2182 BUS_DMASYNC_POSTWRITE);
2183 bus_dmamap_unload(sc->fxp_txmtag,
2185 m_freem(txp[i].tx_mbuf);
2186 txp[i].tx_mbuf = NULL;
2187 /* clear this to reset csum offload bits */
2188 txp[i].tx_cb->tbd[0].tb_addr = 0;
2192 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map,
2193 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2198 * Watchdog/transmission transmit timeout handler. Called when a
2199 * transmission is started on the interface, but no interrupt is
2200 * received before the timeout. This usually indicates that the
2201 * card has wedged for some reason.
2204 fxp_watchdog(struct fxp_softc *sc)
2207 FXP_LOCK_ASSERT(sc, MA_OWNED);
2209 if (sc->watchdog_timer == 0 || --sc->watchdog_timer)
2212 device_printf(sc->dev, "device timeout\n");
2213 sc->ifp->if_oerrors++;
2219 * Acquire locks and then call the real initialization function. This
2220 * is necessary because ether_ioctl() calls if_init() and this would
2221 * result in mutex recursion if the mutex was held.
2226 struct fxp_softc *sc = xsc;
2234 * Perform device initialization. This routine must be called with the
2238 fxp_init_body(struct fxp_softc *sc)
2240 struct ifnet *ifp = sc->ifp;
2241 struct fxp_cb_config *cbp;
2242 struct fxp_cb_ias *cb_ias;
2243 struct fxp_cb_tx *tcbp;
2247 FXP_LOCK_ASSERT(sc, MA_OWNED);
2249 * Cancel any pending I/O
2254 * Issue software reset, which also unloads the microcode.
2256 sc->flags &= ~FXP_FLAG_UCODE;
2257 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SOFTWARE_RESET);
2260 prm = (ifp->if_flags & IFF_PROMISC) ? 1 : 0;
2263 * Initialize base of CBL and RFA memory. Loading with zero
2264 * sets it up for regular linear addressing.
2266 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 0);
2267 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_BASE);
2270 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_BASE);
2273 * Initialize base of dump-stats buffer.
2276 bzero(sc->fxp_stats, sizeof(struct fxp_stats));
2277 bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap,
2278 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2279 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->stats_addr);
2280 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMP_ADR);
2283 * Attempt to load microcode if requested.
2284 * For ICH based controllers do not load microcode.
2286 if (sc->ident->ich == 0) {
2287 if (ifp->if_flags & IFF_LINK0 &&
2288 (sc->flags & FXP_FLAG_UCODE) == 0)
2293 * Set IFF_ALLMULTI status. It's needed in configure action
2299 * We temporarily use memory that contains the TxCB list to
2300 * construct the config CB. The TxCB list memory is rebuilt
2303 cbp = (struct fxp_cb_config *)sc->fxp_desc.cbl_list;
2306 * This bcopy is kind of disgusting, but there are a bunch of must be
2307 * zero and must be one bits in this structure and this is the easiest
2308 * way to initialize them all to proper values.
2310 bcopy(fxp_cb_config_template, cbp, sizeof(fxp_cb_config_template));
2313 cbp->cb_command = htole16(FXP_CB_COMMAND_CONFIG |
2315 cbp->link_addr = 0xffffffff; /* (no) next command */
2316 cbp->byte_count = sc->flags & FXP_FLAG_EXT_RFA ? 32 : 22;
2317 cbp->rx_fifo_limit = 8; /* rx fifo threshold (32 bytes) */
2318 cbp->tx_fifo_limit = 0; /* tx fifo threshold (0 bytes) */
2319 cbp->adaptive_ifs = 0; /* (no) adaptive interframe spacing */
2320 cbp->mwi_enable = sc->flags & FXP_FLAG_MWI_ENABLE ? 1 : 0;
2321 cbp->type_enable = 0; /* actually reserved */
2322 cbp->read_align_en = sc->flags & FXP_FLAG_READ_ALIGN ? 1 : 0;
2323 cbp->end_wr_on_cl = sc->flags & FXP_FLAG_WRITE_ALIGN ? 1 : 0;
2324 cbp->rx_dma_bytecount = 0; /* (no) rx DMA max */
2325 cbp->tx_dma_bytecount = 0; /* (no) tx DMA max */
2326 cbp->dma_mbce = 0; /* (disable) dma max counters */
2327 cbp->late_scb = 0; /* (don't) defer SCB update */
2328 cbp->direct_dma_dis = 1; /* disable direct rcv dma mode */
2329 cbp->tno_int_or_tco_en =0; /* (disable) tx not okay interrupt */
2330 cbp->ci_int = 1; /* interrupt on CU idle */
2331 cbp->ext_txcb_dis = sc->flags & FXP_FLAG_EXT_TXCB ? 0 : 1;
2332 cbp->ext_stats_dis = 1; /* disable extended counters */
2333 cbp->keep_overrun_rx = 0; /* don't pass overrun frames to host */
2334 cbp->save_bf = sc->flags & FXP_FLAG_SAVE_BAD ? 1 : prm;
2335 cbp->disc_short_rx = !prm; /* discard short packets */
2336 cbp->underrun_retry = 1; /* retry mode (once) on DMA underrun */
2337 cbp->two_frames = 0; /* do not limit FIFO to 2 frames */
2338 cbp->dyn_tbd = sc->flags & FXP_FLAG_EXT_RFA ? 1 : 0;
2339 cbp->ext_rfa = sc->flags & FXP_FLAG_EXT_RFA ? 1 : 0;
2340 cbp->mediatype = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 0 : 1;
2341 cbp->csma_dis = 0; /* (don't) disable link */
2342 cbp->tcp_udp_cksum = ((sc->flags & FXP_FLAG_82559_RXCSUM) != 0 &&
2343 (ifp->if_capenable & IFCAP_RXCSUM) != 0) ? 1 : 0;
2344 cbp->vlan_tco = 0; /* (don't) enable vlan wakeup */
2345 cbp->link_wake_en = 0; /* (don't) assert PME# on link change */
2346 cbp->arp_wake_en = 0; /* (don't) assert PME# on arp */
2347 cbp->mc_wake_en = 0; /* (don't) enable PME# on mcmatch */
2348 cbp->nsai = 1; /* (don't) disable source addr insert */
2349 cbp->preamble_length = 2; /* (7 byte) preamble */
2350 cbp->loopback = 0; /* (don't) loopback */
2351 cbp->linear_priority = 0; /* (normal CSMA/CD operation) */
2352 cbp->linear_pri_mode = 0; /* (wait after xmit only) */
2353 cbp->interfrm_spacing = 6; /* (96 bits of) interframe spacing */
2354 cbp->promiscuous = prm; /* promiscuous mode */
2355 cbp->bcast_disable = 0; /* (don't) disable broadcasts */
2356 cbp->wait_after_win = 0; /* (don't) enable modified backoff alg*/
2357 cbp->ignore_ul = 0; /* consider U/L bit in IA matching */
2358 cbp->crc16_en = 0; /* (don't) enable crc-16 algorithm */
2359 cbp->crscdt = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 1 : 0;
2361 cbp->stripping = !prm; /* truncate rx packet to byte count */
2362 cbp->padding = 1; /* (do) pad short tx packets */
2363 cbp->rcv_crc_xfer = 0; /* (don't) xfer CRC to host */
2364 cbp->long_rx_en = sc->flags & FXP_FLAG_LONG_PKT_EN ? 1 : 0;
2365 cbp->ia_wake_en = 0; /* (don't) wake up on address match */
2366 cbp->magic_pkt_dis = sc->flags & FXP_FLAG_WOL ? 0 : 1;
2367 cbp->force_fdx = 0; /* (don't) force full duplex */
2368 cbp->fdx_pin_en = 1; /* (enable) FDX# pin */
2369 cbp->multi_ia = 0; /* (don't) accept multiple IAs */
2370 cbp->mc_all = ifp->if_flags & IFF_ALLMULTI ? 1 : prm;
2371 cbp->gamla_rx = sc->flags & FXP_FLAG_EXT_RFA ? 1 : 0;
2372 cbp->vlan_strip_en = ((sc->flags & FXP_FLAG_EXT_RFA) != 0 &&
2373 (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) ? 1 : 0;
2375 if (sc->tunable_noflow || sc->revision == FXP_REV_82557) {
2377 * The 82557 has no hardware flow control, the values
2378 * below are the defaults for the chip.
2380 cbp->fc_delay_lsb = 0;
2381 cbp->fc_delay_msb = 0x40;
2382 cbp->pri_fc_thresh = 3;
2384 cbp->rx_fc_restop = 0;
2385 cbp->rx_fc_restart = 0;
2387 cbp->pri_fc_loc = 1;
2389 cbp->fc_delay_lsb = 0x1f;
2390 cbp->fc_delay_msb = 0x01;
2391 cbp->pri_fc_thresh = 3;
2392 cbp->tx_fc_dis = 0; /* enable transmit FC */
2393 cbp->rx_fc_restop = 1; /* enable FC restop frames */
2394 cbp->rx_fc_restart = 1; /* enable FC restart frames */
2395 cbp->fc_filter = !prm; /* drop FC frames to host */
2396 cbp->pri_fc_loc = 1; /* FC pri location (byte31) */
2399 /* Enable 82558 and 82559 extended statistics functionality. */
2400 if (sc->revision >= FXP_REV_82558_A4) {
2401 if (sc->revision >= FXP_REV_82559_A0) {
2403 * Extend configuration table size to 32
2404 * to include TCO configuration.
2406 cbp->byte_count = 32;
2407 cbp->ext_stats_dis = 1;
2408 /* Enable TCO stats. */
2409 cbp->tno_int_or_tco_en = 1;
2412 cbp->ext_stats_dis = 0;
2416 * Start the config command/DMA.
2419 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map,
2420 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2421 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.cbl_addr);
2422 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
2423 /* ...and wait for it to complete. */
2424 fxp_dma_wait(sc, &cbp->cb_status, sc->cbl_tag, sc->cbl_map);
2427 * Now initialize the station address. Temporarily use the TxCB
2428 * memory area like we did above for the config CB.
2430 cb_ias = (struct fxp_cb_ias *)sc->fxp_desc.cbl_list;
2431 cb_ias->cb_status = 0;
2432 cb_ias->cb_command = htole16(FXP_CB_COMMAND_IAS | FXP_CB_COMMAND_EL);
2433 cb_ias->link_addr = 0xffffffff;
2434 bcopy(IF_LLADDR(sc->ifp), cb_ias->macaddr, ETHER_ADDR_LEN);
2437 * Start the IAS (Individual Address Setup) command/DMA.
2440 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map,
2441 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2442 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.cbl_addr);
2443 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
2444 /* ...and wait for it to complete. */
2445 fxp_dma_wait(sc, &cb_ias->cb_status, sc->cbl_tag, sc->cbl_map);
2448 * Initialize the multicast address list.
2453 * Initialize transmit control block (TxCB) list.
2455 txp = sc->fxp_desc.tx_list;
2456 tcbp = sc->fxp_desc.cbl_list;
2457 bzero(tcbp, FXP_TXCB_SZ);
2458 for (i = 0; i < FXP_NTXCB; i++) {
2459 txp[i].tx_mbuf = NULL;
2460 tcbp[i].cb_status = htole16(FXP_CB_STATUS_C | FXP_CB_STATUS_OK);
2461 tcbp[i].cb_command = htole16(FXP_CB_COMMAND_NOP);
2462 tcbp[i].link_addr = htole32(sc->fxp_desc.cbl_addr +
2463 (((i + 1) & FXP_TXCB_MASK) * sizeof(struct fxp_cb_tx)));
2464 if (sc->flags & FXP_FLAG_EXT_TXCB)
2465 tcbp[i].tbd_array_addr =
2466 htole32(FXP_TXCB_DMA_ADDR(sc, &tcbp[i].tbd[2]));
2468 tcbp[i].tbd_array_addr =
2469 htole32(FXP_TXCB_DMA_ADDR(sc, &tcbp[i].tbd[0]));
2470 txp[i].tx_next = &txp[(i + 1) & FXP_TXCB_MASK];
2473 * Set the suspend flag on the first TxCB and start the control
2474 * unit. It will execute the NOP and then suspend.
2476 tcbp->cb_command = htole16(FXP_CB_COMMAND_NOP | FXP_CB_COMMAND_S);
2477 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map,
2478 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2479 sc->fxp_desc.tx_first = sc->fxp_desc.tx_last = txp;
2483 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.cbl_addr);
2484 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
2487 * Initialize receiver buffer area - RFA.
2490 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.rx_head->rx_addr);
2491 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START);
2494 * Set current media.
2496 if (sc->miibus != NULL)
2497 mii_mediachg(device_get_softc(sc->miibus));
2499 ifp->if_drv_flags |= IFF_DRV_RUNNING;
2500 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2503 * Enable interrupts.
2505 #ifdef DEVICE_POLLING
2507 * ... but only do that if we are not polling. And because (presumably)
2508 * the default is interrupts on, we need to disable them explicitly!
2510 if (ifp->if_capenable & IFCAP_POLLING )
2511 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE);
2513 #endif /* DEVICE_POLLING */
2514 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0);
2517 * Start stats updater.
2519 callout_reset(&sc->stat_ch, hz, fxp_tick, sc);
2523 fxp_serial_ifmedia_upd(struct ifnet *ifp)
2530 fxp_serial_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
2533 ifmr->ifm_active = IFM_ETHER|IFM_MANUAL;
2537 * Change media according to request.
2540 fxp_ifmedia_upd(struct ifnet *ifp)
2542 struct fxp_softc *sc = ifp->if_softc;
2543 struct mii_data *mii;
2545 mii = device_get_softc(sc->miibus);
2547 if (mii->mii_instance) {
2548 struct mii_softc *miisc;
2549 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
2550 mii_phy_reset(miisc);
2558 * Notify the world which media we're using.
2561 fxp_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
2563 struct fxp_softc *sc = ifp->if_softc;
2564 struct mii_data *mii;
2566 mii = device_get_softc(sc->miibus);
2569 ifmr->ifm_active = mii->mii_media_active;
2570 ifmr->ifm_status = mii->mii_media_status;
2572 if (IFM_SUBTYPE(ifmr->ifm_active) == IFM_10_T &&
2573 sc->flags & FXP_FLAG_CU_RESUME_BUG)
2574 sc->cu_resume_bug = 1;
2576 sc->cu_resume_bug = 0;
2581 * Add a buffer to the end of the RFA buffer list.
2582 * Return 0 if successful, 1 for failure. A failure results in
2583 * reusing the RFA buffer.
2584 * The RFA struct is stuck at the beginning of mbuf cluster and the
2585 * data pointer is fixed up to point just past it.
2588 fxp_new_rfabuf(struct fxp_softc *sc, struct fxp_rx *rxp)
2591 struct fxp_rfa *rfa;
2592 bus_dmamap_t tmp_map;
2595 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
2600 * Move the data pointer up so that the incoming data packet
2601 * will be 32-bit aligned.
2603 m->m_data += RFA_ALIGNMENT_FUDGE;
2606 * Get a pointer to the base of the mbuf cluster and move
2607 * data start past it.
2609 rfa = mtod(m, struct fxp_rfa *);
2610 m->m_data += sc->rfa_size;
2611 rfa->size = htole16(MCLBYTES - sc->rfa_size - RFA_ALIGNMENT_FUDGE);
2613 rfa->rfa_status = 0;
2614 rfa->rfa_control = htole16(FXP_RFA_CONTROL_EL);
2615 rfa->actual_size = 0;
2616 m->m_len = m->m_pkthdr.len = MCLBYTES - RFA_ALIGNMENT_FUDGE -
2620 * Initialize the rest of the RFA. Note that since the RFA
2621 * is misaligned, we cannot store values directly. We're thus
2622 * using the le32enc() function which handles endianness and
2623 * is also alignment-safe.
2625 le32enc(&rfa->link_addr, 0xffffffff);
2626 le32enc(&rfa->rbd_addr, 0xffffffff);
2628 /* Map the RFA into DMA memory. */
2629 error = bus_dmamap_load(sc->fxp_rxmtag, sc->spare_map, rfa,
2630 MCLBYTES - RFA_ALIGNMENT_FUDGE, fxp_dma_map_addr,
2631 &rxp->rx_addr, BUS_DMA_NOWAIT);
2637 if (rxp->rx_mbuf != NULL)
2638 bus_dmamap_unload(sc->fxp_rxmtag, rxp->rx_map);
2639 tmp_map = sc->spare_map;
2640 sc->spare_map = rxp->rx_map;
2641 rxp->rx_map = tmp_map;
2644 bus_dmamap_sync(sc->fxp_rxmtag, rxp->rx_map,
2645 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2650 fxp_add_rfabuf(struct fxp_softc *sc, struct fxp_rx *rxp)
2652 struct fxp_rfa *p_rfa;
2653 struct fxp_rx *p_rx;
2656 * If there are other buffers already on the list, attach this
2657 * one to the end by fixing up the tail to point to this one.
2659 if (sc->fxp_desc.rx_head != NULL) {
2660 p_rx = sc->fxp_desc.rx_tail;
2661 p_rfa = (struct fxp_rfa *)
2662 (p_rx->rx_mbuf->m_ext.ext_buf + RFA_ALIGNMENT_FUDGE);
2663 p_rx->rx_next = rxp;
2664 le32enc(&p_rfa->link_addr, rxp->rx_addr);
2665 p_rfa->rfa_control = 0;
2666 bus_dmamap_sync(sc->fxp_rxmtag, p_rx->rx_map,
2667 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2669 rxp->rx_next = NULL;
2670 sc->fxp_desc.rx_head = rxp;
2672 sc->fxp_desc.rx_tail = rxp;
2676 fxp_discard_rfabuf(struct fxp_softc *sc, struct fxp_rx *rxp)
2679 struct fxp_rfa *rfa;
2682 m->m_data = m->m_ext.ext_buf;
2684 * Move the data pointer up so that the incoming data packet
2685 * will be 32-bit aligned.
2687 m->m_data += RFA_ALIGNMENT_FUDGE;
2690 * Get a pointer to the base of the mbuf cluster and move
2691 * data start past it.
2693 rfa = mtod(m, struct fxp_rfa *);
2694 m->m_data += sc->rfa_size;
2695 rfa->size = htole16(MCLBYTES - sc->rfa_size - RFA_ALIGNMENT_FUDGE);
2697 rfa->rfa_status = 0;
2698 rfa->rfa_control = htole16(FXP_RFA_CONTROL_EL);
2699 rfa->actual_size = 0;
2702 * Initialize the rest of the RFA. Note that since the RFA
2703 * is misaligned, we cannot store values directly. We're thus
2704 * using the le32enc() function which handles endianness and
2705 * is also alignment-safe.
2707 le32enc(&rfa->link_addr, 0xffffffff);
2708 le32enc(&rfa->rbd_addr, 0xffffffff);
2710 bus_dmamap_sync(sc->fxp_rxmtag, rxp->rx_map,
2711 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2715 fxp_miibus_readreg(device_t dev, int phy, int reg)
2717 struct fxp_softc *sc = device_get_softc(dev);
2721 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL,
2722 (FXP_MDI_READ << 26) | (reg << 16) | (phy << 21));
2724 while (((value = CSR_READ_4(sc, FXP_CSR_MDICONTROL)) & 0x10000000) == 0
2729 device_printf(dev, "fxp_miibus_readreg: timed out\n");
2731 return (value & 0xffff);
2735 fxp_miibus_writereg(device_t dev, int phy, int reg, int value)
2737 struct fxp_softc *sc = device_get_softc(dev);
2740 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL,
2741 (FXP_MDI_WRITE << 26) | (reg << 16) | (phy << 21) |
2744 while ((CSR_READ_4(sc, FXP_CSR_MDICONTROL) & 0x10000000) == 0 &&
2749 device_printf(dev, "fxp_miibus_writereg: timed out\n");
2754 fxp_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
2756 struct fxp_softc *sc = ifp->if_softc;
2757 struct ifreq *ifr = (struct ifreq *)data;
2758 struct mii_data *mii;
2759 int flag, mask, error = 0, reinit;
2765 * If interface is marked up and not running, then start it.
2766 * If it is marked down and running, stop it.
2767 * XXX If it's up then re-initialize it. This is so flags
2768 * such as IFF_PROMISC are handled.
2770 if (ifp->if_flags & IFF_UP) {
2771 if (((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) &&
2772 ((ifp->if_flags ^ sc->if_flags) &
2773 (IFF_PROMISC | IFF_ALLMULTI | IFF_LINK0)) != 0)
2775 else if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
2778 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
2781 sc->if_flags = ifp->if_flags;
2787 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
2793 if (sc->miibus != NULL) {
2794 mii = device_get_softc(sc->miibus);
2795 error = ifmedia_ioctl(ifp, ifr,
2796 &mii->mii_media, command);
2798 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, command);
2804 mask = ifp->if_capenable ^ ifr->ifr_reqcap;
2805 #ifdef DEVICE_POLLING
2806 if (mask & IFCAP_POLLING) {
2807 if (ifr->ifr_reqcap & IFCAP_POLLING) {
2808 error = ether_poll_register(fxp_poll, ifp);
2812 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL,
2813 FXP_SCB_INTR_DISABLE);
2814 ifp->if_capenable |= IFCAP_POLLING;
2817 error = ether_poll_deregister(ifp);
2818 /* Enable interrupts in any case */
2820 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0);
2821 ifp->if_capenable &= ~IFCAP_POLLING;
2827 if ((mask & IFCAP_TXCSUM) != 0 &&
2828 (ifp->if_capabilities & IFCAP_TXCSUM) != 0) {
2829 ifp->if_capenable ^= IFCAP_TXCSUM;
2830 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0)
2831 ifp->if_hwassist |= FXP_CSUM_FEATURES;
2833 ifp->if_hwassist &= ~FXP_CSUM_FEATURES;
2835 if ((mask & IFCAP_RXCSUM) != 0 &&
2836 (ifp->if_capabilities & IFCAP_RXCSUM) != 0) {
2837 ifp->if_capenable ^= IFCAP_RXCSUM;
2838 if ((sc->flags & FXP_FLAG_82559_RXCSUM) != 0)
2841 if ((mask & IFCAP_TSO4) != 0 &&
2842 (ifp->if_capabilities & IFCAP_TSO4) != 0) {
2843 ifp->if_capenable ^= IFCAP_TSO4;
2844 if ((ifp->if_capenable & IFCAP_TSO4) != 0)
2845 ifp->if_hwassist |= CSUM_TSO;
2847 ifp->if_hwassist &= ~CSUM_TSO;
2849 if ((mask & IFCAP_WOL_MAGIC) != 0 &&
2850 (ifp->if_capabilities & IFCAP_WOL_MAGIC) != 0)
2851 ifp->if_capenable ^= IFCAP_WOL_MAGIC;
2852 if ((mask & IFCAP_VLAN_MTU) != 0 &&
2853 (ifp->if_capabilities & IFCAP_VLAN_MTU) != 0) {
2854 ifp->if_capenable ^= IFCAP_VLAN_MTU;
2855 if (sc->revision != FXP_REV_82557)
2856 flag = FXP_FLAG_LONG_PKT_EN;
2857 else /* a hack to get long frames on the old chip */
2858 flag = FXP_FLAG_SAVE_BAD;
2860 if (ifp->if_flags & IFF_UP)
2863 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 &&
2864 (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) != 0) {
2865 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
2868 if (reinit > 0 && ifp->if_flags & IFF_UP)
2871 VLAN_CAPABILITIES(ifp);
2875 error = ether_ioctl(ifp, command, data);
2881 * Fill in the multicast address list and return number of entries.
2884 fxp_mc_addrs(struct fxp_softc *sc)
2886 struct fxp_cb_mcs *mcsp = sc->mcsp;
2887 struct ifnet *ifp = sc->ifp;
2888 struct ifmultiaddr *ifma;
2892 if ((ifp->if_flags & IFF_ALLMULTI) == 0) {
2893 if_maddr_rlock(ifp);
2894 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
2895 if (ifma->ifma_addr->sa_family != AF_LINK)
2897 if (nmcasts >= MAXMCADDR) {
2898 ifp->if_flags |= IFF_ALLMULTI;
2902 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
2903 &sc->mcsp->mc_addr[nmcasts][0], ETHER_ADDR_LEN);
2906 if_maddr_runlock(ifp);
2908 mcsp->mc_cnt = htole16(nmcasts * ETHER_ADDR_LEN);
2913 * Program the multicast filter.
2915 * We have an artificial restriction that the multicast setup command
2916 * must be the first command in the chain, so we take steps to ensure
2917 * this. By requiring this, it allows us to keep up the performance of
2918 * the pre-initialized command ring (esp. link pointers) by not actually
2919 * inserting the mcsetup command in the ring - i.e. its link pointer
2920 * points to the TxCB ring, but the mcsetup descriptor itself is not part
2921 * of it. We then can do 'CU_START' on the mcsetup descriptor and have it
2922 * lead into the regular TxCB ring when it completes.
2925 fxp_mc_setup(struct fxp_softc *sc)
2927 struct fxp_cb_mcs *mcsp;
2930 FXP_LOCK_ASSERT(sc, MA_OWNED);
2933 mcsp->cb_status = 0;
2934 mcsp->cb_command = htole16(FXP_CB_COMMAND_MCAS | FXP_CB_COMMAND_EL);
2935 mcsp->link_addr = 0xffffffff;
2939 * Wait until command unit is idle. This should never be the
2940 * case when nothing is queued, but make sure anyway.
2943 while ((CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS) >> 6) !=
2944 FXP_SCB_CUS_IDLE && --count)
2947 device_printf(sc->dev, "command queue timeout\n");
2952 * Start the multicast setup command.
2955 bus_dmamap_sync(sc->mcs_tag, sc->mcs_map,
2956 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2957 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->mcs_addr);
2958 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
2959 /* ...and wait for it to complete. */
2960 fxp_dma_wait(sc, &mcsp->cb_status, sc->mcs_tag, sc->mcs_map);
2963 static uint32_t fxp_ucode_d101a[] = D101_A_RCVBUNDLE_UCODE;
2964 static uint32_t fxp_ucode_d101b0[] = D101_B0_RCVBUNDLE_UCODE;
2965 static uint32_t fxp_ucode_d101ma[] = D101M_B_RCVBUNDLE_UCODE;
2966 static uint32_t fxp_ucode_d101s[] = D101S_RCVBUNDLE_UCODE;
2967 static uint32_t fxp_ucode_d102[] = D102_B_RCVBUNDLE_UCODE;
2968 static uint32_t fxp_ucode_d102c[] = D102_C_RCVBUNDLE_UCODE;
2969 static uint32_t fxp_ucode_d102e[] = D102_E_RCVBUNDLE_UCODE;
2971 #define UCODE(x) x, sizeof(x)/sizeof(uint32_t)
2977 u_short int_delay_offset;
2978 u_short bundle_max_offset;
2980 { FXP_REV_82558_A4, UCODE(fxp_ucode_d101a), D101_CPUSAVER_DWORD, 0 },
2981 { FXP_REV_82558_B0, UCODE(fxp_ucode_d101b0), D101_CPUSAVER_DWORD, 0 },
2982 { FXP_REV_82559_A0, UCODE(fxp_ucode_d101ma),
2983 D101M_CPUSAVER_DWORD, D101M_CPUSAVER_BUNDLE_MAX_DWORD },
2984 { FXP_REV_82559S_A, UCODE(fxp_ucode_d101s),
2985 D101S_CPUSAVER_DWORD, D101S_CPUSAVER_BUNDLE_MAX_DWORD },
2986 { FXP_REV_82550, UCODE(fxp_ucode_d102),
2987 D102_B_CPUSAVER_DWORD, D102_B_CPUSAVER_BUNDLE_MAX_DWORD },
2988 { FXP_REV_82550_C, UCODE(fxp_ucode_d102c),
2989 D102_C_CPUSAVER_DWORD, D102_C_CPUSAVER_BUNDLE_MAX_DWORD },
2990 { FXP_REV_82551_F, UCODE(fxp_ucode_d102e),
2991 D102_E_CPUSAVER_DWORD, D102_E_CPUSAVER_BUNDLE_MAX_DWORD },
2992 { 0, NULL, 0, 0, 0 }
2996 fxp_load_ucode(struct fxp_softc *sc)
2999 struct fxp_cb_ucode *cbp;
3002 for (uc = ucode_table; uc->ucode != NULL; uc++)
3003 if (sc->revision == uc->revision)
3005 if (uc->ucode == NULL)
3007 cbp = (struct fxp_cb_ucode *)sc->fxp_desc.cbl_list;
3009 cbp->cb_command = htole16(FXP_CB_COMMAND_UCODE | FXP_CB_COMMAND_EL);
3010 cbp->link_addr = 0xffffffff; /* (no) next command */
3011 for (i = 0; i < uc->length; i++)
3012 cbp->ucode[i] = htole32(uc->ucode[i]);
3013 if (uc->int_delay_offset)
3014 *(uint16_t *)&cbp->ucode[uc->int_delay_offset] =
3015 htole16(sc->tunable_int_delay + sc->tunable_int_delay / 2);
3016 if (uc->bundle_max_offset)
3017 *(uint16_t *)&cbp->ucode[uc->bundle_max_offset] =
3018 htole16(sc->tunable_bundle_max);
3020 * Download the ucode to the chip.
3023 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map,
3024 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3025 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.cbl_addr);
3026 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
3027 /* ...and wait for it to complete. */
3028 fxp_dma_wait(sc, &cbp->cb_status, sc->cbl_tag, sc->cbl_map);
3029 device_printf(sc->dev,
3030 "Microcode loaded, int_delay: %d usec bundle_max: %d\n",
3031 sc->tunable_int_delay,
3032 uc->bundle_max_offset == 0 ? 0 : sc->tunable_bundle_max);
3033 sc->flags |= FXP_FLAG_UCODE;
3036 #define FXP_SYSCTL_STAT_ADD(c, h, n, p, d) \
3037 SYSCTL_ADD_UINT(c, h, OID_AUTO, n, CTLFLAG_RD, p, 0, d)
3040 fxp_sysctl_node(struct fxp_softc *sc)
3042 struct sysctl_ctx_list *ctx;
3043 struct sysctl_oid_list *child, *parent;
3044 struct sysctl_oid *tree;
3045 struct fxp_hwstats *hsp;
3047 ctx = device_get_sysctl_ctx(sc->dev);
3048 child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev));
3050 SYSCTL_ADD_PROC(ctx, child,
3051 OID_AUTO, "int_delay", CTLTYPE_INT | CTLFLAG_RW,
3052 &sc->tunable_int_delay, 0, sysctl_hw_fxp_int_delay, "I",
3053 "FXP driver receive interrupt microcode bundling delay");
3054 SYSCTL_ADD_PROC(ctx, child,
3055 OID_AUTO, "bundle_max", CTLTYPE_INT | CTLFLAG_RW,
3056 &sc->tunable_bundle_max, 0, sysctl_hw_fxp_bundle_max, "I",
3057 "FXP driver receive interrupt microcode bundle size limit");
3058 SYSCTL_ADD_INT(ctx, child,OID_AUTO, "rnr", CTLFLAG_RD, &sc->rnr, 0,
3060 SYSCTL_ADD_INT(ctx, child,
3061 OID_AUTO, "noflow", CTLFLAG_RW, &sc->tunable_noflow, 0,
3062 "FXP flow control disabled");
3065 * Pull in device tunables.
3067 sc->tunable_int_delay = TUNABLE_INT_DELAY;
3068 sc->tunable_bundle_max = TUNABLE_BUNDLE_MAX;
3069 sc->tunable_noflow = 1;
3070 (void) resource_int_value(device_get_name(sc->dev),
3071 device_get_unit(sc->dev), "int_delay", &sc->tunable_int_delay);
3072 (void) resource_int_value(device_get_name(sc->dev),
3073 device_get_unit(sc->dev), "bundle_max", &sc->tunable_bundle_max);
3074 (void) resource_int_value(device_get_name(sc->dev),
3075 device_get_unit(sc->dev), "noflow", &sc->tunable_noflow);
3078 hsp = &sc->fxp_hwstats;
3079 tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats", CTLFLAG_RD,
3080 NULL, "FXP statistics");
3081 parent = SYSCTL_CHILDREN(tree);
3083 /* Rx MAC statistics. */
3084 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "rx", CTLFLAG_RD,
3085 NULL, "Rx MAC statistics");
3086 child = SYSCTL_CHILDREN(tree);
3087 FXP_SYSCTL_STAT_ADD(ctx, child, "good_frames",
3088 &hsp->rx_good, "Good frames");
3089 FXP_SYSCTL_STAT_ADD(ctx, child, "crc_errors",
3090 &hsp->rx_crc_errors, "CRC errors");
3091 FXP_SYSCTL_STAT_ADD(ctx, child, "alignment_errors",
3092 &hsp->rx_alignment_errors, "Alignment errors");
3093 FXP_SYSCTL_STAT_ADD(ctx, child, "rnr_errors",
3094 &hsp->rx_rnr_errors, "RNR errors");
3095 FXP_SYSCTL_STAT_ADD(ctx, child, "overrun_errors",
3096 &hsp->rx_overrun_errors, "Overrun errors");
3097 FXP_SYSCTL_STAT_ADD(ctx, child, "cdt_errors",
3098 &hsp->rx_cdt_errors, "Collision detect errors");
3099 FXP_SYSCTL_STAT_ADD(ctx, child, "shortframes",
3100 &hsp->rx_shortframes, "Short frame errors");
3101 if (sc->revision >= FXP_REV_82558_A4) {
3102 FXP_SYSCTL_STAT_ADD(ctx, child, "pause",
3103 &hsp->rx_pause, "Pause frames");
3104 FXP_SYSCTL_STAT_ADD(ctx, child, "controls",
3105 &hsp->rx_controls, "Unsupported control frames");
3107 if (sc->revision >= FXP_REV_82559_A0)
3108 FXP_SYSCTL_STAT_ADD(ctx, child, "tco",
3109 &hsp->rx_tco, "TCO frames");
3111 /* Tx MAC statistics. */
3112 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "tx", CTLFLAG_RD,
3113 NULL, "Tx MAC statistics");
3114 child = SYSCTL_CHILDREN(tree);
3115 FXP_SYSCTL_STAT_ADD(ctx, child, "good_frames",
3116 &hsp->tx_good, "Good frames");
3117 FXP_SYSCTL_STAT_ADD(ctx, child, "maxcols",
3118 &hsp->tx_maxcols, "Maximum collisions errors");
3119 FXP_SYSCTL_STAT_ADD(ctx, child, "latecols",
3120 &hsp->tx_latecols, "Late collisions errors");
3121 FXP_SYSCTL_STAT_ADD(ctx, child, "underruns",
3122 &hsp->tx_underruns, "Underrun errors");
3123 FXP_SYSCTL_STAT_ADD(ctx, child, "lostcrs",
3124 &hsp->tx_lostcrs, "Lost carrier sense");
3125 FXP_SYSCTL_STAT_ADD(ctx, child, "deffered",
3126 &hsp->tx_deffered, "Deferred");
3127 FXP_SYSCTL_STAT_ADD(ctx, child, "single_collisions",
3128 &hsp->tx_single_collisions, "Single collisions");
3129 FXP_SYSCTL_STAT_ADD(ctx, child, "multiple_collisions",
3130 &hsp->tx_multiple_collisions, "Multiple collisions");
3131 FXP_SYSCTL_STAT_ADD(ctx, child, "total_collisions",
3132 &hsp->tx_total_collisions, "Total collisions");
3133 if (sc->revision >= FXP_REV_82558_A4)
3134 FXP_SYSCTL_STAT_ADD(ctx, child, "pause",
3135 &hsp->tx_pause, "Pause frames");
3136 if (sc->revision >= FXP_REV_82559_A0)
3137 FXP_SYSCTL_STAT_ADD(ctx, child, "tco",
3138 &hsp->tx_tco, "TCO frames");
3141 #undef FXP_SYSCTL_STAT_ADD
3144 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high)
3148 value = *(int *)arg1;
3149 error = sysctl_handle_int(oidp, &value, 0, req);
3150 if (error || !req->newptr)
3152 if (value < low || value > high)
3154 *(int *)arg1 = value;
3159 * Interrupt delay is expressed in microseconds, a multiplier is used
3160 * to convert this to the appropriate clock ticks before using.
3163 sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS)
3165 return (sysctl_int_range(oidp, arg1, arg2, req, 300, 3000));
3169 sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS)
3171 return (sysctl_int_range(oidp, arg1, arg2, req, 1, 0xffff));