2 * Copyright (c) 2008 Joseph Koshy
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * Intel Core, Core 2 and Atom PMCs.
31 #include <sys/cdefs.h>
32 __FBSDID("$FreeBSD$");
34 #include <sys/param.h>
37 #include <sys/pmckern.h>
38 #include <sys/systm.h>
40 #include <machine/intr_machdep.h>
41 #include <machine/apicvar.h>
42 #include <machine/cpu.h>
43 #include <machine/cpufunc.h>
44 #include <machine/specialreg.h>
46 #define CORE_CPUID_REQUEST 0xA
47 #define CORE_CPUID_REQUEST_SIZE 0x4
48 #define CORE_CPUID_EAX 0x0
49 #define CORE_CPUID_EBX 0x1
50 #define CORE_CPUID_ECX 0x2
51 #define CORE_CPUID_EDX 0x3
53 #define IAF_PMC_CAPS \
54 (PMC_CAP_READ | PMC_CAP_WRITE | PMC_CAP_INTERRUPT)
55 #define IAF_RI_TO_MSR(RI) ((RI) + (1 << 30))
57 #define IAP_PMC_CAPS (PMC_CAP_INTERRUPT | PMC_CAP_USER | PMC_CAP_SYSTEM | \
58 PMC_CAP_EDGE | PMC_CAP_THRESHOLD | PMC_CAP_READ | PMC_CAP_WRITE | \
59 PMC_CAP_INVERT | PMC_CAP_QUALIFIER | PMC_CAP_PRECISE)
62 * "Architectural" events defined by Intel. The values of these
63 * symbols correspond to positions in the bitmask returned by
64 * the CPUID.0AH instruction.
66 enum core_arch_events {
67 CORE_AE_BRANCH_INSTRUCTION_RETIRED = 5,
68 CORE_AE_BRANCH_MISSES_RETIRED = 6,
69 CORE_AE_INSTRUCTION_RETIRED = 1,
70 CORE_AE_LLC_MISSES = 4,
71 CORE_AE_LLC_REFERENCE = 3,
72 CORE_AE_UNHALTED_REFERENCE_CYCLES = 2,
73 CORE_AE_UNHALTED_CORE_CYCLES = 0
76 static enum pmc_cputype core_cputype;
79 volatile uint32_t pc_resync;
80 volatile uint32_t pc_iafctrl; /* Fixed function control. */
81 volatile uint64_t pc_globalctrl; /* Global control register. */
82 struct pmc_hw pc_corepmcs[];
85 static struct core_cpu **core_pcpu;
87 static uint32_t core_architectural_events;
88 static uint64_t core_pmcmask;
90 static int core_iaf_ri; /* relative index of fixed counters */
91 static int core_iaf_width;
92 static int core_iaf_npmc;
94 static int core_iap_width;
95 static int core_iap_npmc;
98 core_pcpu_noop(struct pmc_mdep *md, int cpu)
106 core_pcpu_init(struct pmc_mdep *md, int cpu)
111 int core_ri, n, npmc;
113 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
114 ("[iaf,%d] insane cpu number %d", __LINE__, cpu));
116 PMCDBG(MDP,INI,1,"core-init cpu=%d", cpu);
118 core_ri = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAP].pcd_ri;
119 npmc = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAP].pcd_num;
121 if (core_cputype != PMC_CPU_INTEL_CORE)
122 npmc += md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAF].pcd_num;
124 cc = malloc(sizeof(struct core_cpu) + npmc * sizeof(struct pmc_hw),
125 M_PMC, M_WAITOK | M_ZERO);
130 KASSERT(pc != NULL && cc != NULL,
131 ("[core,%d] NULL per-cpu structures cpu=%d", __LINE__, cpu));
133 for (n = 0, phw = cc->pc_corepmcs; n < npmc; n++, phw++) {
134 phw->phw_state = PMC_PHW_FLAG_IS_ENABLED |
135 PMC_PHW_CPU_TO_STATE(cpu) |
136 PMC_PHW_INDEX_TO_STATE(n + core_ri);
138 pc->pc_hwpmcs[n + core_ri] = phw;
145 core_pcpu_fini(struct pmc_mdep *md, int cpu)
147 int core_ri, n, npmc;
151 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
152 ("[core,%d] insane cpu number (%d)", __LINE__, cpu));
154 PMCDBG(MDP,INI,1,"core-pcpu-fini cpu=%d", cpu);
156 if ((cc = core_pcpu[cpu]) == NULL)
159 core_pcpu[cpu] = NULL;
163 KASSERT(pc != NULL, ("[core,%d] NULL per-cpu %d state", __LINE__,
166 npmc = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAP].pcd_num;
167 core_ri = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAP].pcd_ri;
169 for (n = 0; n < npmc; n++)
170 wrmsr(IAP_EVSEL0 + n, 0);
172 if (core_cputype != PMC_CPU_INTEL_CORE) {
174 npmc += md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAF].pcd_num;
177 for (n = 0; n < npmc; n++)
178 pc->pc_hwpmcs[n + core_ri] = NULL;
186 * Fixed function counters.
190 iaf_perfctr_value_to_reload_count(pmc_value_t v)
192 v &= (1ULL << core_iaf_width) - 1;
193 return (1ULL << core_iaf_width) - v;
197 iaf_reload_count_to_perfctr_value(pmc_value_t rlc)
199 return (1ULL << core_iaf_width) - rlc;
203 iaf_allocate_pmc(int cpu, int ri, struct pmc *pm,
204 const struct pmc_op_pmcallocate *a)
207 uint32_t caps, flags, validflags;
209 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
210 ("[core,%d] illegal CPU %d", __LINE__, cpu));
212 PMCDBG(MDP,ALL,1, "iaf-allocate ri=%d reqcaps=0x%x", ri, pm->pm_caps);
214 if (ri < 0 || ri > core_iaf_npmc)
219 if (a->pm_class != PMC_CLASS_IAF ||
220 (caps & IAF_PMC_CAPS) != caps)
224 if (ev < PMC_EV_IAF_FIRST || ev > PMC_EV_IAF_LAST)
227 if (ev == PMC_EV_IAF_INSTR_RETIRED_ANY && ri != 0)
229 if (ev == PMC_EV_IAF_CPU_CLK_UNHALTED_CORE && ri != 1)
231 if (ev == PMC_EV_IAF_CPU_CLK_UNHALTED_REF && ri != 2)
234 flags = a->pm_md.pm_iaf.pm_iaf_flags;
236 validflags = IAF_MASK;
238 if (core_cputype != PMC_CPU_INTEL_ATOM)
239 validflags &= ~IAF_ANY;
241 if ((flags & ~validflags) != 0)
244 if (caps & PMC_CAP_INTERRUPT)
246 if (caps & PMC_CAP_SYSTEM)
248 if (caps & PMC_CAP_USER)
250 if ((caps & (PMC_CAP_USER | PMC_CAP_SYSTEM)) == 0)
251 flags |= (IAF_OS | IAF_USR);
253 pm->pm_md.pm_iaf.pm_iaf_ctrl = (flags << (ri * 4));
255 PMCDBG(MDP,ALL,2, "iaf-allocate config=0x%jx",
256 (uintmax_t) pm->pm_md.pm_iaf.pm_iaf_ctrl);
262 iaf_config_pmc(int cpu, int ri, struct pmc *pm)
264 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
265 ("[core,%d] illegal CPU %d", __LINE__, cpu));
267 KASSERT(ri >= 0 && ri < core_iaf_npmc,
268 ("[core,%d] illegal row-index %d", __LINE__, ri));
270 PMCDBG(MDP,CFG,1, "iaf-config cpu=%d ri=%d pm=%p", cpu, ri, pm);
272 KASSERT(core_pcpu[cpu] != NULL, ("[core,%d] null per-cpu %d", __LINE__,
275 core_pcpu[cpu]->pc_corepmcs[ri + core_iaf_ri].phw_pmc = pm;
281 iaf_describe(int cpu, int ri, struct pmc_info *pi, struct pmc **ppmc)
285 char iaf_name[PMC_NAME_MAX];
287 phw = &core_pcpu[cpu]->pc_corepmcs[ri + core_iaf_ri];
289 (void) snprintf(iaf_name, sizeof(iaf_name), "IAF-%d", ri);
290 if ((error = copystr(iaf_name, pi->pm_name, PMC_NAME_MAX,
294 pi->pm_class = PMC_CLASS_IAF;
296 if (phw->phw_state & PMC_PHW_FLAG_IS_ENABLED) {
297 pi->pm_enabled = TRUE;
298 *ppmc = phw->phw_pmc;
300 pi->pm_enabled = FALSE;
308 iaf_get_config(int cpu, int ri, struct pmc **ppm)
310 *ppm = core_pcpu[cpu]->pc_corepmcs[ri + core_iaf_ri].phw_pmc;
316 iaf_get_msr(int ri, uint32_t *msr)
318 KASSERT(ri >= 0 && ri < core_iaf_npmc,
319 ("[iaf,%d] ri %d out of range", __LINE__, ri));
321 *msr = IAF_RI_TO_MSR(ri);
327 iaf_read_pmc(int cpu, int ri, pmc_value_t *v)
332 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
333 ("[core,%d] illegal cpu value %d", __LINE__, cpu));
334 KASSERT(ri >= 0 && ri < core_iaf_npmc,
335 ("[core,%d] illegal row-index %d", __LINE__, ri));
337 pm = core_pcpu[cpu]->pc_corepmcs[ri + core_iaf_ri].phw_pmc;
340 ("[core,%d] cpu %d ri %d(%d) pmc not configured", __LINE__, cpu,
341 ri, ri + core_iaf_ri));
343 tmp = rdpmc(IAF_RI_TO_MSR(ri));
345 if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm)))
346 *v = iaf_perfctr_value_to_reload_count(tmp);
350 PMCDBG(MDP,REA,1, "iaf-read cpu=%d ri=%d msr=0x%x -> v=%jx", cpu, ri,
351 IAF_RI_TO_MSR(ri), *v);
357 iaf_release_pmc(int cpu, int ri, struct pmc *pmc)
359 PMCDBG(MDP,REL,1, "iaf-release cpu=%d ri=%d pm=%p", cpu, ri, pmc);
361 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
362 ("[core,%d] illegal CPU value %d", __LINE__, cpu));
363 KASSERT(ri >= 0 && ri < core_iaf_npmc,
364 ("[core,%d] illegal row-index %d", __LINE__, ri));
366 KASSERT(core_pcpu[cpu]->pc_corepmcs[ri + core_iaf_ri].phw_pmc == NULL,
367 ("[core,%d] PHW pmc non-NULL", __LINE__));
373 iaf_start_pmc(int cpu, int ri)
376 struct core_cpu *iafc;
378 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
379 ("[core,%d] illegal CPU value %d", __LINE__, cpu));
380 KASSERT(ri >= 0 && ri < core_iaf_npmc,
381 ("[core,%d] illegal row-index %d", __LINE__, ri));
383 PMCDBG(MDP,STA,1,"iaf-start cpu=%d ri=%d", cpu, ri);
385 iafc = core_pcpu[cpu];
386 pm = iafc->pc_corepmcs[ri + core_iaf_ri].phw_pmc;
388 iafc->pc_iafctrl |= pm->pm_md.pm_iaf.pm_iaf_ctrl;
390 wrmsr(IAF_CTRL, iafc->pc_iafctrl);
394 iafc->pc_globalctrl |= (1ULL << (ri + IAF_OFFSET));
395 wrmsr(IA_GLOBAL_CTRL, iafc->pc_globalctrl);
396 } while (iafc->pc_resync != 0);
398 PMCDBG(MDP,STA,1,"iafctrl=%x(%x) globalctrl=%jx(%jx)",
399 iafc->pc_iafctrl, (uint32_t) rdmsr(IAF_CTRL),
400 iafc->pc_globalctrl, rdmsr(IA_GLOBAL_CTRL));
406 iaf_stop_pmc(int cpu, int ri)
409 struct core_cpu *iafc;
411 PMCDBG(MDP,STO,1,"iaf-stop cpu=%d ri=%d", cpu, ri);
413 iafc = core_pcpu[cpu];
415 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
416 ("[core,%d] illegal CPU value %d", __LINE__, cpu));
417 KASSERT(ri >= 0 && ri < core_iaf_npmc,
418 ("[core,%d] illegal row-index %d", __LINE__, ri));
420 fc = (IAF_MASK << (ri * 4));
422 if (core_cputype != PMC_CPU_INTEL_ATOM)
425 iafc->pc_iafctrl &= ~fc;
427 PMCDBG(MDP,STO,1,"iaf-stop iafctrl=%x", iafc->pc_iafctrl);
428 wrmsr(IAF_CTRL, iafc->pc_iafctrl);
432 iafc->pc_globalctrl &= ~(1ULL << (ri + IAF_OFFSET));
433 wrmsr(IA_GLOBAL_CTRL, iafc->pc_globalctrl);
434 } while (iafc->pc_resync != 0);
436 PMCDBG(MDP,STO,1,"iafctrl=%x(%x) globalctrl=%jx(%jx)",
437 iafc->pc_iafctrl, (uint32_t) rdmsr(IAF_CTRL),
438 iafc->pc_globalctrl, rdmsr(IA_GLOBAL_CTRL));
444 iaf_write_pmc(int cpu, int ri, pmc_value_t v)
449 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
450 ("[core,%d] illegal cpu value %d", __LINE__, cpu));
451 KASSERT(ri >= 0 && ri < core_iaf_npmc,
452 ("[core,%d] illegal row-index %d", __LINE__, ri));
455 pm = cc->pc_corepmcs[ri + core_iaf_ri].phw_pmc;
458 ("[core,%d] cpu %d ri %d pmc not configured", __LINE__, cpu, ri));
460 if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm)))
461 v = iaf_reload_count_to_perfctr_value(v);
463 wrmsr(IAF_CTRL, 0); /* Turn off fixed counters */
464 wrmsr(IAF_CTR0 + ri, v);
465 wrmsr(IAF_CTRL, cc->pc_iafctrl);
467 PMCDBG(MDP,WRI,1, "iaf-write cpu=%d ri=%d msr=0x%x v=%jx iafctrl=%jx "
468 "pmc=%jx", cpu, ri, IAF_RI_TO_MSR(ri), v,
469 (uintmax_t) rdmsr(IAF_CTRL),
470 (uintmax_t) rdpmc(IAF_RI_TO_MSR(ri)));
477 iaf_initialize(struct pmc_mdep *md, int maxcpu, int npmc, int pmcwidth)
479 struct pmc_classdep *pcd;
481 KASSERT(md != NULL, ("[iaf,%d] md is NULL", __LINE__));
483 PMCDBG(MDP,INI,1, "%s", "iaf-initialize");
485 pcd = &md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAF];
487 pcd->pcd_caps = IAF_PMC_CAPS;
488 pcd->pcd_class = PMC_CLASS_IAF;
490 pcd->pcd_ri = md->pmd_npmc;
491 pcd->pcd_width = pmcwidth;
493 pcd->pcd_allocate_pmc = iaf_allocate_pmc;
494 pcd->pcd_config_pmc = iaf_config_pmc;
495 pcd->pcd_describe = iaf_describe;
496 pcd->pcd_get_config = iaf_get_config;
497 pcd->pcd_get_msr = iaf_get_msr;
498 pcd->pcd_pcpu_fini = core_pcpu_noop;
499 pcd->pcd_pcpu_init = core_pcpu_noop;
500 pcd->pcd_read_pmc = iaf_read_pmc;
501 pcd->pcd_release_pmc = iaf_release_pmc;
502 pcd->pcd_start_pmc = iaf_start_pmc;
503 pcd->pcd_stop_pmc = iaf_stop_pmc;
504 pcd->pcd_write_pmc = iaf_write_pmc;
506 md->pmd_npmc += npmc;
510 * Intel programmable PMCs.
514 * Event descriptor tables.
516 * For each event id, we track:
518 * 1. The CPUs that the event is valid for.
520 * 2. If the event uses a fixed UMASK, the value of the umask field.
521 * If the event doesn't use a fixed UMASK, a mask of legal bits
525 struct iap_event_descr {
526 enum pmc_event iap_ev;
527 unsigned char iap_evcode;
528 unsigned char iap_umask;
529 unsigned char iap_flags;
532 #define IAP_F_CC (1 << 0) /* CPU: Core */
533 #define IAP_F_CC2 (1 << 1) /* CPU: Core2 family */
534 #define IAP_F_CC2E (1 << 2) /* CPU: Core2 Extreme only */
535 #define IAP_F_CA (1 << 3) /* CPU: Atom */
536 #define IAP_F_I7 (1 << 4) /* CPU: Core i7 */
537 #define IAP_F_I7O (1 << 4) /* CPU: Core i7 (old) */
538 #define IAP_F_WM (1 << 5) /* CPU: Westmere */
539 #define IAP_F_FM (1 << 6) /* Fixed mask */
541 #define IAP_F_ALLCPUSCORE2 \
542 (IAP_F_CC | IAP_F_CC2 | IAP_F_CC2E | IAP_F_CA)
544 /* Sub fields of UMASK that this event supports. */
545 #define IAP_M_CORE (1 << 0) /* Core specificity */
546 #define IAP_M_AGENT (1 << 1) /* Agent specificity */
547 #define IAP_M_PREFETCH (1 << 2) /* Prefetch */
548 #define IAP_M_MESI (1 << 3) /* MESI */
549 #define IAP_M_SNOOPRESPONSE (1 << 4) /* Snoop response */
550 #define IAP_M_SNOOPTYPE (1 << 5) /* Snoop type */
551 #define IAP_M_TRANSITION (1 << 6) /* Transition */
553 #define IAP_F_CORE (0x3 << 14) /* Core specificity */
554 #define IAP_F_AGENT (0x1 << 13) /* Agent specificity */
555 #define IAP_F_PREFETCH (0x3 << 12) /* Prefetch */
556 #define IAP_F_MESI (0xF << 8) /* MESI */
557 #define IAP_F_SNOOPRESPONSE (0xB << 8) /* Snoop response */
558 #define IAP_F_SNOOPTYPE (0x3 << 8) /* Snoop type */
559 #define IAP_F_TRANSITION (0x1 << 12) /* Transition */
561 #define IAP_PREFETCH_RESERVED (0x2 << 12)
562 #define IAP_CORE_THIS (0x1 << 14)
563 #define IAP_CORE_ALL (0x3 << 14)
564 #define IAP_F_CMASK 0xFF000000
566 static struct iap_event_descr iap_events[] = {
568 #define IAPDESCR(N,EV,UM,FLAGS) { \
569 .iap_ev = PMC_EV_IAP_EVENT_##N, \
570 .iap_evcode = (EV), \
572 .iap_flags = (FLAGS) \
575 IAPDESCR(02H_01H, 0x02, 0x01, IAP_F_FM | IAP_F_I7O),
576 IAPDESCR(02H_81H, 0x02, 0x81, IAP_F_FM | IAP_F_CA),
578 IAPDESCR(03H_00H, 0x03, 0x00, IAP_F_FM | IAP_F_CC),
579 IAPDESCR(03H_01H, 0x03, 0x01, IAP_F_FM | IAP_F_I7O),
580 IAPDESCR(03H_02H, 0x03, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_WM),
581 IAPDESCR(03H_04H, 0x03, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7O),
582 IAPDESCR(03H_08H, 0x03, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
583 IAPDESCR(03H_10H, 0x03, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
584 IAPDESCR(03H_20H, 0x03, 0x20, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
586 IAPDESCR(04H_00H, 0x04, 0x00, IAP_F_FM | IAP_F_CC),
587 IAPDESCR(04H_01H, 0x04, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7O),
588 IAPDESCR(04H_02H, 0x04, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
589 IAPDESCR(04H_07H, 0x04, 0x07, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
590 IAPDESCR(04H_08H, 0x04, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
592 IAPDESCR(05H_00H, 0x05, 0x00, IAP_F_FM | IAP_F_CC),
593 IAPDESCR(05H_01H, 0x05, 0x01, IAP_F_FM | IAP_F_I7O),
594 IAPDESCR(05H_02H, 0x05, 0x02, IAP_F_FM | IAP_F_I7O | IAP_F_WM),
595 IAPDESCR(05H_03H, 0x05, 0x03, IAP_F_FM | IAP_F_I7O),
597 IAPDESCR(06H_00H, 0x06, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CC2 |
598 IAP_F_CC2E | IAP_F_CA),
599 IAPDESCR(06H_01H, 0x06, 0x01, IAP_F_FM | IAP_F_I7O),
600 IAPDESCR(06H_02H, 0x06, 0x02, IAP_F_FM | IAP_F_I7O),
601 IAPDESCR(06H_04H, 0x06, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
602 IAPDESCR(06H_08H, 0x06, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
603 IAPDESCR(06H_0FH, 0x06, 0x0F, IAP_F_FM | IAP_F_I7O),
605 IAPDESCR(07H_00H, 0x07, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CC2),
606 IAPDESCR(07H_01H, 0x07, 0x01, IAP_F_FM | IAP_F_ALLCPUSCORE2 | IAP_F_I7 | IAP_F_WM),
607 IAPDESCR(07H_02H, 0x07, 0x02, IAP_F_FM | IAP_F_ALLCPUSCORE2),
608 IAPDESCR(07H_03H, 0x07, 0x03, IAP_F_FM | IAP_F_ALLCPUSCORE2),
609 IAPDESCR(07H_06H, 0x07, 0x06, IAP_F_FM | IAP_F_CA),
610 IAPDESCR(07H_08H, 0x07, 0x08, IAP_F_FM | IAP_F_CA),
612 IAPDESCR(08H_01H, 0x08, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
613 IAP_F_I7 | IAP_F_WM),
614 IAPDESCR(08H_02H, 0x08, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
615 IAP_F_I7 | IAP_F_WM),
616 IAPDESCR(08H_04H, 0x08, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
618 IAPDESCR(08H_05H, 0x08, 0x05, IAP_F_FM | IAP_F_CA),
619 IAPDESCR(08H_06H, 0x08, 0x06, IAP_F_FM | IAP_F_CA),
620 IAPDESCR(08H_07H, 0x08, 0x07, IAP_F_FM | IAP_F_CA),
621 IAPDESCR(08H_08H, 0x08, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
622 IAPDESCR(08H_09H, 0x08, 0x09, IAP_F_FM | IAP_F_CA),
623 IAPDESCR(08H_10H, 0x08, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
624 IAPDESCR(08H_20H, 0x08, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
625 IAPDESCR(08H_40H, 0x08, 0x40, IAP_F_FM | IAP_F_I7),
626 IAPDESCR(08H_80H, 0x08, 0x80, IAP_F_FM | IAP_F_I7),
628 IAPDESCR(09H_01H, 0x09, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7O),
629 IAPDESCR(09H_02H, 0x09, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7O),
630 IAPDESCR(09H_04H, 0x09, 0x04, IAP_F_FM | IAP_F_I7O),
631 IAPDESCR(09H_08H, 0x09, 0x08, IAP_F_FM | IAP_F_I7O),
633 IAPDESCR(0BH_01H, 0x0B, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
634 IAPDESCR(0BH_02H, 0x0B, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
635 IAPDESCR(0BH_10H, 0x0B, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
637 IAPDESCR(0CH_01H, 0x0C, 0x01, IAP_F_FM | IAP_F_CC2 | IAP_F_I7 |
639 IAPDESCR(0CH_02H, 0x0C, 0x02, IAP_F_FM | IAP_F_CC2),
640 IAPDESCR(0CH_03H, 0x0C, 0x03, IAP_F_FM | IAP_F_CA),
642 IAPDESCR(0EH_01H, 0x0E, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
643 IAPDESCR(0EH_02H, 0x0E, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
645 IAPDESCR(0FH_01H, 0x0F, 0x01, IAP_F_FM | IAP_F_I7),
646 IAPDESCR(0FH_02H, 0x0F, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
647 IAPDESCR(0FH_08H, 0x0F, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
648 IAPDESCR(0FH_10H, 0x0F, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
649 IAPDESCR(0FH_20H, 0x0F, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
650 IAPDESCR(0FH_80H, 0x0F, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
652 IAPDESCR(10H_00H, 0x10, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
653 IAPDESCR(10H_01H, 0x10, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_I7 | IAP_F_WM),
654 IAPDESCR(10H_02H, 0x10, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
655 IAPDESCR(10H_04H, 0x10, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
656 IAPDESCR(10H_08H, 0x10, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
657 IAPDESCR(10H_10H, 0x10, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
658 IAPDESCR(10H_20H, 0x10, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
659 IAPDESCR(10H_40H, 0x10, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
660 IAPDESCR(10H_80H, 0x10, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
661 IAPDESCR(10H_81H, 0x10, 0x81, IAP_F_FM | IAP_F_CA),
663 IAPDESCR(11H_00H, 0x11, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CC2),
664 IAPDESCR(11H_01H, 0x11, 0x01, IAP_F_FM | IAP_F_CA),
665 IAPDESCR(11H_81H, 0x11, 0x81, IAP_F_FM | IAP_F_CA),
667 IAPDESCR(12H_00H, 0x12, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
668 IAPDESCR(12H_01H, 0x12, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_I7 | IAP_F_WM),
669 IAPDESCR(12H_02H, 0x12, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
670 IAPDESCR(12H_04H, 0x12, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
671 IAPDESCR(12H_08H, 0x12, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
672 IAPDESCR(12H_10H, 0x12, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
673 IAPDESCR(12H_20H, 0x12, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
674 IAPDESCR(12H_40H, 0x12, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
675 IAPDESCR(12H_81H, 0x12, 0x81, IAP_F_FM | IAP_F_CA),
677 IAPDESCR(13H_00H, 0x13, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
678 IAPDESCR(13H_01H, 0x13, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_I7 | IAP_F_WM),
679 IAPDESCR(13H_02H, 0x13, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
680 IAPDESCR(13H_04H, 0x13, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
681 IAPDESCR(13H_07H, 0x13, 0x07, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
682 IAPDESCR(13H_81H, 0x13, 0x81, IAP_F_FM | IAP_F_CA),
684 IAPDESCR(14H_00H, 0x14, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CC2),
685 IAPDESCR(14H_01H, 0x14, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_I7 | IAP_F_WM),
686 IAPDESCR(14H_02H, 0x14, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
688 IAPDESCR(17H_01H, 0x17, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
690 IAPDESCR(18H_00H, 0x18, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
691 IAPDESCR(18H_01H, 0x18, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
693 IAPDESCR(19H_00H, 0x19, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
694 IAPDESCR(19H_01H, 0x19, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
695 IAP_F_I7 | IAP_F_WM),
696 IAPDESCR(19H_02H, 0x19, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
698 IAPDESCR(1DH_01H, 0x1D, 0x01, IAP_F_FM | IAP_F_I7O),
699 IAPDESCR(1DH_02H, 0x1D, 0x02, IAP_F_FM | IAP_F_I7O),
700 IAPDESCR(1DH_04H, 0x1D, 0x04, IAP_F_FM | IAP_F_I7O),
702 IAPDESCR(1EH_01H, 0x1E, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
704 IAPDESCR(20H_01H, 0x20, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
705 IAPDESCR(21H, 0x21, IAP_M_CORE, IAP_F_ALLCPUSCORE2),
706 IAPDESCR(22H, 0x22, IAP_M_CORE, IAP_F_CC2),
707 IAPDESCR(23H, 0x23, IAP_M_CORE, IAP_F_ALLCPUSCORE2),
709 IAPDESCR(24H, 0x24, IAP_M_CORE | IAP_M_PREFETCH, IAP_F_ALLCPUSCORE2),
710 IAPDESCR(24H_01H, 0x24, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
711 IAPDESCR(24H_02H, 0x24, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
712 IAPDESCR(24H_03H, 0x24, 0x03, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
713 IAPDESCR(24H_04H, 0x24, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
714 IAPDESCR(24H_08H, 0x24, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
715 IAPDESCR(24H_0CH, 0x24, 0x0C, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
716 IAPDESCR(24H_10H, 0x24, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
717 IAPDESCR(24H_20H, 0x24, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
718 IAPDESCR(24H_30H, 0x24, 0x30, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
719 IAPDESCR(24H_40H, 0x24, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
720 IAPDESCR(24H_80H, 0x24, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
721 IAPDESCR(24H_C0H, 0x24, 0xC0, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
722 IAPDESCR(24H_AAH, 0x24, 0xAA, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
723 IAPDESCR(24H_FFH, 0x24, 0xFF, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
725 IAPDESCR(25H, 0x25, IAP_M_CORE, IAP_F_ALLCPUSCORE2),
727 IAPDESCR(26H, 0x26, IAP_M_CORE | IAP_M_PREFETCH, IAP_F_ALLCPUSCORE2),
728 IAPDESCR(26H_01H, 0x26, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
729 IAPDESCR(26H_02H, 0x26, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
730 IAPDESCR(26H_04H, 0x26, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
731 IAPDESCR(26H_08H, 0x26, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
732 IAPDESCR(26H_0FH, 0x26, 0x0F, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
733 IAPDESCR(26H_10H, 0x26, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
734 IAPDESCR(26H_20H, 0x26, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
735 IAPDESCR(26H_40H, 0x26, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
736 IAPDESCR(26H_80H, 0x26, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
737 IAPDESCR(26H_F0H, 0x26, 0xF0, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
738 IAPDESCR(26H_FFH, 0x26, 0xFF, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
740 IAPDESCR(27H, 0x27, IAP_M_CORE | IAP_M_PREFETCH, IAP_F_ALLCPUSCORE2),
741 IAPDESCR(27H_01H, 0x27, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
742 IAPDESCR(27H_02H, 0x27, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
743 IAPDESCR(27H_04H, 0x27, 0x04, IAP_F_FM | IAP_F_I7O),
744 IAPDESCR(27H_08H, 0x27, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
745 IAPDESCR(27H_0EH, 0x27, 0x0E, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
746 IAPDESCR(27H_0FH, 0x27, 0x0F, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
747 IAPDESCR(27H_10H, 0x27, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
748 IAPDESCR(27H_20H, 0x27, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
749 IAPDESCR(27H_40H, 0x27, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
750 IAPDESCR(27H_80H, 0x27, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
751 IAPDESCR(27H_E0H, 0x27, 0xE0, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
752 IAPDESCR(27H_F0H, 0x27, 0xF0, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
754 IAPDESCR(28H, 0x28, IAP_M_CORE | IAP_M_MESI, IAP_F_ALLCPUSCORE2),
755 IAPDESCR(28H_01H, 0x28, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
756 IAPDESCR(28H_02H, 0x28, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
757 IAPDESCR(28H_04H, 0x28, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
758 IAPDESCR(28H_08H, 0x28, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
759 IAPDESCR(28H_0FH, 0x28, 0x0F, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
761 IAPDESCR(29H, 0x29, IAP_M_CORE | IAP_M_MESI, IAP_F_CC),
762 IAPDESCR(29H, 0x29, IAP_M_CORE | IAP_M_MESI | IAP_M_PREFETCH,
763 IAP_F_CA | IAP_F_CC2),
764 IAPDESCR(2AH, 0x2A, IAP_M_CORE | IAP_M_MESI, IAP_F_ALLCPUSCORE2),
765 IAPDESCR(2BH, 0x2B, IAP_M_CORE | IAP_M_MESI, IAP_F_CA | IAP_F_CC2),
767 IAPDESCR(2EH, 0x2E, IAP_M_CORE | IAP_M_MESI | IAP_M_PREFETCH,
769 IAPDESCR(2EH_01H, 0x2E, 0x01, IAP_F_FM | IAP_F_WM),
770 IAPDESCR(2EH_02H, 0x2E, 0x02, IAP_F_FM | IAP_F_WM),
771 IAPDESCR(2EH_41H, 0x2E, 0x41, IAP_F_FM | IAP_F_ALLCPUSCORE2 | IAP_F_I7),
772 IAPDESCR(2EH_4FH, 0x2E, 0x4F, IAP_F_FM | IAP_F_ALLCPUSCORE2 | IAP_F_I7),
774 IAPDESCR(30H, 0x30, IAP_M_CORE | IAP_M_MESI | IAP_M_PREFETCH,
776 IAPDESCR(32H, 0x32, IAP_M_CORE | IAP_M_MESI | IAP_M_PREFETCH, IAP_F_CC),
777 IAPDESCR(32H, 0x32, IAP_M_CORE, IAP_F_CA | IAP_F_CC2),
779 IAPDESCR(3AH, 0x3A, IAP_M_TRANSITION, IAP_F_CC),
780 IAPDESCR(3AH_00H, 0x3A, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
782 IAPDESCR(3BH_C0H, 0x3B, 0xC0, IAP_F_FM | IAP_F_ALLCPUSCORE2),
784 IAPDESCR(3CH_00H, 0x3C, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2 |
785 IAP_F_I7 | IAP_F_WM),
786 IAPDESCR(3CH_01H, 0x3C, 0x01, IAP_F_FM | IAP_F_ALLCPUSCORE2 |
787 IAP_F_I7 | IAP_F_WM),
788 IAPDESCR(3CH_02H, 0x3C, 0x02, IAP_F_FM | IAP_F_ALLCPUSCORE2),
790 IAPDESCR(3DH_01H, 0x3D, 0x01, IAP_F_FM | IAP_F_I7O),
792 IAPDESCR(40H, 0x40, IAP_M_MESI, IAP_F_CC | IAP_F_CC2),
793 IAPDESCR(40H_01H, 0x40, 0x01, IAP_F_FM | IAP_F_I7),
794 IAPDESCR(40H_02H, 0x40, 0x02, IAP_F_FM | IAP_F_I7),
795 IAPDESCR(40H_04H, 0x40, 0x04, IAP_F_FM | IAP_F_I7),
796 IAPDESCR(40H_08H, 0x40, 0x08, IAP_F_FM | IAP_F_I7),
797 IAPDESCR(40H_0FH, 0x40, 0x0F, IAP_F_FM | IAP_F_I7),
798 IAPDESCR(40H_21H, 0x40, 0x21, IAP_F_FM | IAP_F_CA),
800 IAPDESCR(41H, 0x41, IAP_M_MESI, IAP_F_CC | IAP_F_CC2),
801 IAPDESCR(41H_01H, 0x41, 0x01, IAP_F_FM | IAP_F_I7O),
802 IAPDESCR(41H_02H, 0x41, 0x02, IAP_F_FM | IAP_F_I7),
803 IAPDESCR(41H_04H, 0x41, 0x04, IAP_F_FM | IAP_F_I7),
804 IAPDESCR(41H_08H, 0x41, 0x08, IAP_F_FM | IAP_F_I7),
805 IAPDESCR(41H_0FH, 0x41, 0x0F, IAP_F_FM | IAP_F_I7O),
806 IAPDESCR(41H_22H, 0x41, 0x22, IAP_F_FM | IAP_F_CA),
808 IAPDESCR(42H, 0x42, IAP_M_MESI, IAP_F_ALLCPUSCORE2),
809 IAPDESCR(42H_01H, 0x42, 0x01, IAP_F_FM | IAP_F_I7),
810 IAPDESCR(42H_02H, 0x42, 0x02, IAP_F_FM | IAP_F_I7),
811 IAPDESCR(42H_04H, 0x42, 0x04, IAP_F_FM | IAP_F_I7),
812 IAPDESCR(42H_08H, 0x42, 0x08, IAP_F_FM | IAP_F_I7),
813 IAPDESCR(42H_10H, 0x42, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
815 IAPDESCR(43H_01H, 0x43, 0x01, IAP_F_FM | IAP_F_ALLCPUSCORE2 |
817 IAPDESCR(43H_02H, 0x43, 0x02, IAP_F_FM | IAP_F_CA |
818 IAP_F_CC2 | IAP_F_I7),
820 IAPDESCR(44H_02H, 0x44, 0x02, IAP_F_FM | IAP_F_CC),
822 IAPDESCR(45H_0FH, 0x45, 0x0F, IAP_F_FM | IAP_F_ALLCPUSCORE2),
824 IAPDESCR(46H_00H, 0x46, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
825 IAPDESCR(47H_00H, 0x47, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
827 IAPDESCR(48H_00H, 0x48, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
828 IAPDESCR(48H_02H, 0x48, 0x02, IAP_F_FM | IAP_F_I7),
830 IAPDESCR(49H_00H, 0x49, 0x00, IAP_F_FM | IAP_F_CC),
831 IAPDESCR(49H_01H, 0x49, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
832 IAP_F_I7 | IAP_F_WM),
833 IAPDESCR(49H_02H, 0x49, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
834 IAP_F_I7 | IAP_F_WM),
835 IAPDESCR(49H_04H, 0x49, 0x04, IAP_F_FM | IAP_F_WM),
836 IAPDESCR(49H_10H, 0x49, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
837 IAPDESCR(49H_20H, 0x49, 0x20, IAP_F_FM | IAP_F_I7O),
838 IAPDESCR(49H_40H, 0x49, 0x40, IAP_F_FM | IAP_F_I7O),
839 IAPDESCR(49H_80H, 0x49, 0x80, IAP_F_FM | IAP_F_WM | IAP_F_I7O),
841 IAPDESCR(4BH_00H, 0x4B, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
842 IAPDESCR(4BH_01H, 0x4B, 0x01, IAP_F_FM | IAP_F_ALLCPUSCORE2 | IAP_F_I7O),
843 IAPDESCR(4BH_02H, 0x4B, 0x02, IAP_F_FM | IAP_F_ALLCPUSCORE2),
844 IAPDESCR(4BH_03H, 0x4B, 0x03, IAP_F_FM | IAP_F_CC),
845 IAPDESCR(4BH_08H, 0x4B, 0x08, IAP_F_FM | IAP_F_I7O),
847 IAPDESCR(4CH_00H, 0x4C, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
848 IAPDESCR(4CH_01H, 0x4C, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
850 IAPDESCR(4DH_01H, 0x4D, 0x01, IAP_F_FM | IAP_F_I7O),
852 IAPDESCR(4EH_01H, 0x4E, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
853 IAPDESCR(4EH_02H, 0x4E, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
854 IAPDESCR(4EH_04H, 0x4E, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
855 IAPDESCR(4EH_10H, 0x4E, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
857 IAPDESCR(4FH_00H, 0x4F, 0x00, IAP_F_FM | IAP_F_CC),
858 IAPDESCR(4FH_02H, 0x4F, 0x02, IAP_F_FM | IAP_F_I7O),
859 IAPDESCR(4FH_04H, 0x4F, 0x04, IAP_F_FM | IAP_F_I7O),
860 IAPDESCR(4FH_08H, 0x4F, 0x08, IAP_F_FM | IAP_F_I7O),
861 IAPDESCR(4FH_10H, 0x4F, 0x10, IAP_F_FM | IAP_F_WM),
863 IAPDESCR(51H_01H, 0x51, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
864 IAPDESCR(51H_02H, 0x51, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
865 IAPDESCR(51H_04H, 0x51, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
866 IAPDESCR(51H_08H, 0x51, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
868 IAPDESCR(52H_01H, 0x52, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
869 IAPDESCR(53H_01H, 0x53, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
871 IAPDESCR(60H, 0x60, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUSCORE2),
872 IAPDESCR(60H_01H, 0x60, 0x01, IAP_F_FM | IAP_F_WM | IAP_F_I7O),
873 IAPDESCR(60H_02H, 0x60, 0x02, IAP_F_FM | IAP_F_WM | IAP_F_I7O),
874 IAPDESCR(60H_04H, 0x60, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_I7O),
875 IAPDESCR(60H_08H, 0x60, 0x08, IAP_F_FM | IAP_F_WM | IAP_F_I7O),
877 IAPDESCR(61H, 0x61, IAP_M_AGENT, IAP_F_CA | IAP_F_CC2),
878 IAPDESCR(61H_00H, 0x61, 0x00, IAP_F_FM | IAP_F_CC),
880 IAPDESCR(62H, 0x62, IAP_M_AGENT, IAP_F_ALLCPUSCORE2),
881 IAPDESCR(62H_00H, 0x62, 0x00, IAP_F_FM | IAP_F_CC),
883 IAPDESCR(63H, 0x63, IAP_M_AGENT | IAP_M_CORE,
884 IAP_F_CA | IAP_F_CC2),
885 IAPDESCR(63H, 0x63, IAP_M_CORE, IAP_F_CC),
886 IAPDESCR(63H_01H, 0x63, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
887 IAPDESCR(63H_02H, 0x63, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
889 IAPDESCR(64H, 0x64, IAP_M_CORE, IAP_F_CA | IAP_F_CC2),
890 IAPDESCR(64H_40H, 0x64, 0x40, IAP_F_FM | IAP_F_CC),
892 IAPDESCR(65H, 0x65, IAP_M_AGENT | IAP_M_CORE,
893 IAP_F_CA | IAP_F_CC2),
894 IAPDESCR(65H, 0x65, IAP_M_CORE, IAP_F_CC),
896 IAPDESCR(66H, 0x66, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUSCORE2),
898 IAPDESCR(67H, 0x67, IAP_M_AGENT | IAP_M_CORE, IAP_F_CA | IAP_F_CC2),
899 IAPDESCR(67H, 0x67, IAP_M_AGENT, IAP_F_CC),
901 IAPDESCR(68H, 0x68, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUSCORE2),
902 IAPDESCR(69H, 0x69, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUSCORE2),
903 IAPDESCR(6AH, 0x6A, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUSCORE2),
904 IAPDESCR(6BH, 0x6B, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUSCORE2),
906 IAPDESCR(6CH, 0x6C, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUSCORE2),
907 IAPDESCR(6CH_01H, 0x6C, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
909 IAPDESCR(6DH, 0x6D, IAP_M_AGENT | IAP_M_CORE, IAP_F_CA | IAP_F_CC2),
910 IAPDESCR(6DH, 0x6D, IAP_M_CORE, IAP_F_CC),
912 IAPDESCR(6EH, 0x6E, IAP_M_AGENT | IAP_M_CORE, IAP_F_CA | IAP_F_CC2),
913 IAPDESCR(6EH, 0x6E, IAP_M_CORE, IAP_F_CC),
915 IAPDESCR(6FH, 0x6F, IAP_M_AGENT | IAP_M_CORE, IAP_F_CA | IAP_F_CC2),
916 IAPDESCR(6FH, 0x6F, IAP_M_CORE, IAP_F_CC),
918 IAPDESCR(70H, 0x70, IAP_M_AGENT | IAP_M_CORE, IAP_F_CA | IAP_F_CC2),
919 IAPDESCR(70H, 0x70, IAP_M_CORE, IAP_F_CC),
921 IAPDESCR(77H, 0x77, IAP_M_AGENT | IAP_M_SNOOPRESPONSE,
922 IAP_F_CA | IAP_F_CC2),
923 IAPDESCR(77H, 0x77, IAP_M_AGENT | IAP_M_MESI, IAP_F_CC),
925 IAPDESCR(78H, 0x78, IAP_M_CORE, IAP_F_CC),
926 IAPDESCR(78H, 0x78, IAP_M_CORE | IAP_M_SNOOPTYPE, IAP_F_CA | IAP_F_CC2),
928 IAPDESCR(7AH, 0x7A, IAP_M_AGENT, IAP_F_CA | IAP_F_CC2),
930 IAPDESCR(7BH, 0x7B, IAP_M_AGENT, IAP_F_CA | IAP_F_CC2),
932 IAPDESCR(7DH, 0x7D, IAP_M_CORE, IAP_F_ALLCPUSCORE2),
934 IAPDESCR(7EH, 0x7E, IAP_M_AGENT | IAP_M_CORE, IAP_F_CA | IAP_F_CC2),
935 IAPDESCR(7EH_00H, 0x7E, 0x00, IAP_F_FM | IAP_F_CC),
937 IAPDESCR(7FH, 0x7F, IAP_M_CORE, IAP_F_CA | IAP_F_CC2),
939 IAPDESCR(80H_00H, 0x80, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
940 IAPDESCR(80H_01H, 0x80, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
941 IAPDESCR(80H_02H, 0x80, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_I7 |
943 IAPDESCR(80H_03H, 0x80, 0x03, IAP_F_FM | IAP_F_CA | IAP_F_I7 |
945 IAPDESCR(80H_04H, 0x80, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
947 IAPDESCR(81H_00H, 0x81, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
948 IAPDESCR(81H_01H, 0x81, 0x01, IAP_F_FM | IAP_F_I7O),
949 IAPDESCR(81H_02H, 0x81, 0x02, IAP_F_FM | IAP_F_I7O),
951 IAPDESCR(82H_01H, 0x82, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
952 IAPDESCR(82H_02H, 0x82, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
953 IAPDESCR(82H_04H, 0x82, 0x04, IAP_F_FM | IAP_F_CA),
954 IAPDESCR(82H_10H, 0x82, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
955 IAPDESCR(82H_12H, 0x82, 0x12, IAP_F_FM | IAP_F_CC2),
956 IAPDESCR(82H_40H, 0x82, 0x40, IAP_F_FM | IAP_F_CC2),
958 IAPDESCR(83H_01H, 0x83, 0x01, IAP_F_FM | IAP_F_I7O),
959 IAPDESCR(83H_02H, 0x83, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
961 IAPDESCR(85H_00H, 0x85, 0x00, IAP_F_FM | IAP_F_CC),
962 IAPDESCR(85H_01H, 0x85, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
963 IAPDESCR(85H_02H, 0x85, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
964 IAPDESCR(85H_04H, 0x85, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_I7O),
965 IAPDESCR(85H_10H, 0x85, 0x10, IAP_F_FM | IAP_F_I7O),
966 IAPDESCR(85H_20H, 0x85, 0x20, IAP_F_FM | IAP_F_I7O),
967 IAPDESCR(85H_40H, 0x85, 0x40, IAP_F_FM | IAP_F_I7O),
968 IAPDESCR(85H_80H, 0x85, 0x80, IAP_F_FM | IAP_F_WM | IAP_F_I7O),
970 IAPDESCR(86H_00H, 0x86, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
972 IAPDESCR(87H_00H, 0x87, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
973 IAPDESCR(87H_01H, 0x87, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
974 IAPDESCR(87H_02H, 0x87, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
975 IAPDESCR(87H_04H, 0x87, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
976 IAPDESCR(87H_08H, 0x87, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
977 IAPDESCR(87H_0FH, 0x87, 0x0F, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
979 IAPDESCR(88H_00H, 0x88, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
980 IAPDESCR(88H_01H, 0x88, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
981 IAPDESCR(88H_02H, 0x88, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
982 IAPDESCR(88H_04H, 0x88, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
983 IAPDESCR(88H_07H, 0x88, 0x07, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
984 IAPDESCR(88H_08H, 0x88, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
985 IAPDESCR(88H_10H, 0x88, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
986 IAPDESCR(88H_20H, 0x88, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
987 IAPDESCR(88H_30H, 0x88, 0x30, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
988 IAPDESCR(88H_40H, 0x88, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
989 IAPDESCR(88H_7FH, 0x88, 0x7F, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
991 IAPDESCR(89H_00H, 0x89, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
992 IAPDESCR(89H_01H, 0x89, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
993 IAPDESCR(89H_02H, 0x89, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
994 IAPDESCR(89H_04H, 0x89, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
995 IAPDESCR(89H_07H, 0x89, 0x07, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
996 IAPDESCR(89H_08H, 0x89, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
997 IAPDESCR(89H_10H, 0x89, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
998 IAPDESCR(89H_20H, 0x89, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
999 IAPDESCR(89H_30H, 0x89, 0x30, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1000 IAPDESCR(89H_40H, 0x89, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1001 IAPDESCR(89H_7FH, 0x89, 0x7F, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1003 IAPDESCR(8AH_00H, 0x8A, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1004 IAPDESCR(8BH_00H, 0x8B, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1005 IAPDESCR(8CH_00H, 0x8C, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1006 IAPDESCR(8DH_00H, 0x8D, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1007 IAPDESCR(8EH_00H, 0x8E, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1008 IAPDESCR(8FH_00H, 0x8F, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1010 IAPDESCR(90H_00H, 0x90, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1011 IAPDESCR(91H_00H, 0x91, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1012 IAPDESCR(92H_00H, 0x92, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1013 IAPDESCR(93H_00H, 0x93, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1014 IAPDESCR(94H_00H, 0x94, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1016 IAPDESCR(97H_00H, 0x97, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1017 IAPDESCR(98H_00H, 0x98, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1018 IAPDESCR(A0H_00H, 0xA0, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1020 IAPDESCR(A1H_01H, 0xA1, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1021 IAPDESCR(A1H_02H, 0xA1, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1022 IAPDESCR(A1H_04H, 0xA1, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1023 IAPDESCR(A1H_08H, 0xA1, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1024 IAPDESCR(A1H_10H, 0xA1, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1025 IAPDESCR(A1H_20H, 0xA1, 0x20, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1027 IAPDESCR(A2H_00H, 0xA2, 0x00, IAP_F_FM | IAP_F_CC),
1028 IAPDESCR(A2H_01H, 0xA2, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1029 IAPDESCR(A2H_02H, 0xA2, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1030 IAPDESCR(A2H_04H, 0xA2, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1031 IAPDESCR(A2H_08H, 0xA2, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1032 IAPDESCR(A2H_10H, 0xA2, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1033 IAPDESCR(A2H_20H, 0xA2, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1034 IAPDESCR(A2H_40H, 0xA2, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1035 IAPDESCR(A2H_80H, 0xA2, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1037 IAPDESCR(A6H_01H, 0xA6, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1038 IAPDESCR(A7H_01H, 0xA7, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1039 IAPDESCR(A8H_01H, 0xA8, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1041 IAPDESCR(AAH_01H, 0xAA, 0x01, IAP_F_FM | IAP_F_CC2),
1042 IAPDESCR(AAH_02H, 0xAA, 0x02, IAP_F_FM | IAP_F_CA),
1043 IAPDESCR(AAH_03H, 0xAA, 0x03, IAP_F_FM | IAP_F_CA),
1044 IAPDESCR(AAH_08H, 0xAA, 0x08, IAP_F_FM | IAP_F_CC2),
1046 IAPDESCR(ABH_01H, 0xAB, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1047 IAPDESCR(ABH_02H, 0xAB, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1049 IAPDESCR(AEH_01H, 0xAE, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1051 IAPDESCR(B0H_00H, 0xB0, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1052 IAPDESCR(B0H_01H, 0xB0, 0x01, IAP_F_FM | IAP_F_WM | IAP_F_I7O),
1053 IAPDESCR(B0H_02H, 0xB0, 0x02, IAP_F_FM | IAP_F_WM | IAP_F_I7O),
1054 IAPDESCR(B0H_04H, 0xB0, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_I7O),
1055 IAPDESCR(B0H_08H, 0xB0, 0x08, IAP_F_FM | IAP_F_WM | IAP_F_I7O),
1056 IAPDESCR(B0H_10H, 0xB0, 0x10, IAP_F_FM | IAP_F_WM | IAP_F_I7O),
1057 IAPDESCR(B0H_20H, 0xB0, 0x20, IAP_F_FM | IAP_F_I7O),
1058 IAPDESCR(B0H_40H, 0xB0, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1059 IAPDESCR(B0H_80H, 0xB0, 0x80, IAP_F_FM | IAP_F_CA | IAP_F_WM | IAP_F_I7O),
1061 IAPDESCR(B1H_00H, 0xB1, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1062 IAPDESCR(B1H_01H, 0xB1, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1063 IAPDESCR(B1H_02H, 0xB1, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1064 IAPDESCR(B1H_04H, 0xB1, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1065 IAPDESCR(B1H_08H, 0xB1, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1066 IAPDESCR(B1H_10H, 0xB1, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1067 IAPDESCR(B1H_1FH, 0xB1, 0x1F, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1068 IAPDESCR(B1H_20H, 0xB1, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1069 IAPDESCR(B1H_3FH, 0xB1, 0x3F, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1070 IAPDESCR(B1H_40H, 0xB1, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1071 IAPDESCR(B1H_80H, 0xB1, 0x80, IAP_F_FM | IAP_F_CA | IAP_F_I7 |
1074 IAPDESCR(B2H_01H, 0xB2, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1076 IAPDESCR(B3H_01H, 0xB3, 0x01, IAP_F_FM | IAP_F_ALLCPUSCORE2 |
1077 IAP_F_WM | IAP_F_I7O),
1078 IAPDESCR(B3H_02H, 0xB3, 0x02, IAP_F_FM | IAP_F_ALLCPUSCORE2 |
1079 IAP_F_WM | IAP_F_I7O),
1080 IAPDESCR(B3H_04H, 0xB3, 0x04, IAP_F_FM | IAP_F_ALLCPUSCORE2 |
1081 IAP_F_WM | IAP_F_I7O),
1082 IAPDESCR(B3H_08H, 0xB3, 0x08, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1083 IAPDESCR(B3H_10H, 0xB3, 0x10, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1084 IAPDESCR(B3H_20H, 0xB3, 0x20, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1085 IAPDESCR(B3H_81H, 0xB3, 0x81, IAP_F_FM | IAP_F_CA),
1086 IAPDESCR(B3H_82H, 0xB3, 0x82, IAP_F_FM | IAP_F_CA),
1087 IAPDESCR(B3H_84H, 0xB3, 0x84, IAP_F_FM | IAP_F_CA),
1088 IAPDESCR(B3H_88H, 0xB3, 0x88, IAP_F_FM | IAP_F_CA),
1089 IAPDESCR(B3H_90H, 0xB3, 0x90, IAP_F_FM | IAP_F_CA),
1090 IAPDESCR(B3H_A0H, 0xB3, 0xA0, IAP_F_FM | IAP_F_CA),
1092 IAPDESCR(B4H_01H, 0xB4, 0x01, IAP_F_FM | IAP_F_WM),
1093 IAPDESCR(B4H_02H, 0xB4, 0x02, IAP_F_FM | IAP_F_WM),
1094 IAPDESCR(B4H_04H, 0xB4, 0x04, IAP_F_FM | IAP_F_WM),
1096 IAPDESCR(B7H_01H, 0xB7, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1098 IAPDESCR(B8H_01H, 0xB8, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1099 IAPDESCR(B8H_02H, 0xB8, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1100 IAPDESCR(B8H_04H, 0xB8, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1102 IAPDESCR(BAH_01H, 0xBA, 0x01, IAP_F_FM | IAP_F_I7O),
1103 IAPDESCR(BAH_02H, 0xBA, 0x02, IAP_F_FM | IAP_F_I7O),
1105 IAPDESCR(BBH_01H, 0xBB, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1107 IAPDESCR(C0H_00H, 0xC0, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1108 IAPDESCR(C0H_01H, 0xC0, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1109 IAP_F_I7 | IAP_F_WM),
1110 IAPDESCR(C0H_02H, 0xC0, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1111 IAP_F_I7 | IAP_F_WM),
1112 IAPDESCR(C0H_04H, 0xC0, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1113 IAP_F_I7 | IAP_F_WM),
1114 IAPDESCR(C0H_08H, 0xC0, 0x08, IAP_F_FM | IAP_F_CC2E),
1116 IAPDESCR(C1H_00H, 0xC1, 0x00, IAP_F_FM | IAP_F_CC),
1117 IAPDESCR(C1H_01H, 0xC1, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1118 IAPDESCR(C1H_FEH, 0xC1, 0xFE, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1120 IAPDESCR(C2H_00H, 0xC2, 0x00, IAP_F_FM | IAP_F_CC),
1121 IAPDESCR(C2H_01H, 0xC2, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1122 IAP_F_I7 | IAP_F_WM),
1123 IAPDESCR(C2H_02H, 0xC2, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1124 IAP_F_I7 | IAP_F_WM),
1125 IAPDESCR(C2H_04H, 0xC2, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1126 IAP_F_I7 | IAP_F_WM),
1127 IAPDESCR(C2H_07H, 0xC2, 0x07, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1128 IAPDESCR(C2H_08H, 0xC2, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1129 IAPDESCR(C2H_0FH, 0xC2, 0x0F, IAP_F_FM | IAP_F_CC2),
1130 IAPDESCR(C2H_10H, 0xC2, 0x10, IAP_F_FM | IAP_F_CA),
1132 IAPDESCR(C3H_00H, 0xC3, 0x00, IAP_F_FM | IAP_F_CC),
1133 IAPDESCR(C3H_01H, 0xC3, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1134 IAP_F_I7 | IAP_F_WM),
1135 IAPDESCR(C3H_02H, 0xC3, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1136 IAPDESCR(C3H_04H, 0xC3, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1137 IAP_F_I7 | IAP_F_WM),
1138 IAPDESCR(C3H_10H, 0xC3, 0x10, IAP_F_FM | IAP_F_I7O),
1140 IAPDESCR(C4H_00H, 0xC4, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2 |
1141 IAP_F_I7 | IAP_F_WM),
1142 IAPDESCR(C4H_01H, 0xC4, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1143 IAP_F_I7 | IAP_F_WM),
1144 IAPDESCR(C4H_02H, 0xC4, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1145 IAP_F_I7 | IAP_F_WM),
1146 IAPDESCR(C4H_04H, 0xC4, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1147 IAP_F_I7 | IAP_F_WM),
1148 IAPDESCR(C4H_08H, 0xC4, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1149 IAPDESCR(C4H_0CH, 0xC4, 0x0C, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1150 IAPDESCR(C4H_0FH, 0xC4, 0x0F, IAP_F_FM | IAP_F_CA),
1152 IAPDESCR(C5H_00H, 0xC5, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2 |
1153 IAP_F_I7 | IAP_F_WM),
1154 IAPDESCR(C5H_01H, 0xC5, 0x01, IAP_F_FM | IAP_F_WM),
1155 IAPDESCR(C5H_02H, 0xC5, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1156 IAPDESCR(C5H_04H, 0xC5, 0x04, IAP_F_FM | IAP_F_WM),
1158 IAPDESCR(C6H_00H, 0xC6, 0x00, IAP_F_FM | IAP_F_CC),
1159 IAPDESCR(C6H_01H, 0xC6, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1160 IAPDESCR(C6H_02H, 0xC6, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1162 IAPDESCR(C7H_00H, 0xC7, 0x00, IAP_F_FM | IAP_F_CC),
1163 IAPDESCR(C7H_01H, 0xC7, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1164 IAP_F_I7 | IAP_F_WM),
1165 IAPDESCR(C7H_02H, 0xC7, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1166 IAP_F_I7 | IAP_F_WM),
1167 IAPDESCR(C7H_04H, 0xC7, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1168 IAP_F_I7 | IAP_F_WM),
1169 IAPDESCR(C7H_08H, 0xC7, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1170 IAP_F_I7 | IAP_F_WM),
1171 IAPDESCR(C7H_10H, 0xC7, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1172 IAP_F_I7 | IAP_F_WM),
1173 IAPDESCR(C7H_1FH, 0xC7, 0x1F, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1175 IAPDESCR(C8H_00H, 0xC8, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1176 IAPDESCR(C8H_20H, 0xC8, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1178 IAPDESCR(C9H_00H, 0xC9, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1180 IAPDESCR(CAH_00H, 0xCA, 0x00, IAP_F_FM | IAP_F_CC),
1181 IAPDESCR(CAH_01H, 0xCA, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1182 IAPDESCR(CAH_02H, 0xCA, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1183 IAPDESCR(CAH_04H, 0xCA, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1184 IAPDESCR(CAH_08H, 0xCA, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1186 IAPDESCR(CBH_01H, 0xCB, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1187 IAP_F_I7 | IAP_F_WM),
1188 IAPDESCR(CBH_02H, 0xCB, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1189 IAP_F_I7 | IAP_F_WM),
1190 IAPDESCR(CBH_04H, 0xCB, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1191 IAP_F_I7 | IAP_F_WM),
1192 IAPDESCR(CBH_08H, 0xCB, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1193 IAP_F_I7 | IAP_F_WM),
1194 IAPDESCR(CBH_10H, 0xCB, 0x10, IAP_F_FM | IAP_F_CC2 | IAP_F_I7 |
1196 IAPDESCR(CBH_40H, 0xCB, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1197 IAPDESCR(CBH_80H, 0xCB, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1199 IAPDESCR(CCH_00H, 0xCC, 0x00, IAP_F_FM | IAP_F_CC),
1200 IAPDESCR(CCH_01H, 0xCC, 0x01, IAP_F_FM | IAP_F_ALLCPUSCORE2 |
1201 IAP_F_I7 | IAP_F_WM),
1202 IAPDESCR(CCH_02H, 0xCC, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1203 IAP_F_I7 | IAP_F_WM),
1204 IAPDESCR(CCH_03H, 0xCC, 0x03, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1206 IAPDESCR(CDH_00H, 0xCD, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1207 IAPDESCR(CEH_00H, 0xCE, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1208 IAPDESCR(CFH_00H, 0xCF, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1210 IAPDESCR(D0H_00H, 0xD0, 0x00, IAP_F_FM | IAP_F_CC),
1211 IAPDESCR(D0H_01H, 0xD0, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1213 IAPDESCR(D1H_01H, 0xD1, 0x01, IAP_F_FM | IAP_F_WM),
1214 IAPDESCR(D1H_02H, 0xD1, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1215 IAPDESCR(D1H_04H, 0xD1, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1216 IAPDESCR(D1H_08H, 0xD1, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1218 IAPDESCR(D2H_01H, 0xD2, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1219 IAP_F_I7 | IAP_F_WM),
1220 IAPDESCR(D2H_02H, 0xD2, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1221 IAP_F_I7 | IAP_F_WM),
1222 IAPDESCR(D2H_04H, 0xD2, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1223 IAP_F_I7 | IAP_F_WM),
1224 IAPDESCR(D2H_08H, 0xD2, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1225 IAP_F_I7 | IAP_F_WM),
1226 IAPDESCR(D2H_0FH, 0xD2, 0x0F, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1227 IAP_F_I7 | IAP_F_WM),
1228 IAPDESCR(D2H_10H, 0xD2, 0x10, IAP_F_FM | IAP_F_CC2E),
1230 IAPDESCR(D4H_01H, 0xD4, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1231 IAP_F_I7 | IAP_F_WM),
1232 IAPDESCR(D4H_02H, 0xD4, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1233 IAPDESCR(D4H_04H, 0xD4, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1234 IAPDESCR(D4H_08H, 0xD4, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1235 IAPDESCR(D4H_0FH, 0xD4, 0x0F, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1237 IAPDESCR(D5H_01H, 0xD5, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1238 IAP_F_I7 | IAP_F_WM),
1239 IAPDESCR(D5H_02H, 0xD5, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1240 IAPDESCR(D5H_04H, 0xD5, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1241 IAPDESCR(D5H_08H, 0xD5, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1242 IAPDESCR(D5H_0FH, 0xD5, 0x0F, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1244 IAPDESCR(D7H_00H, 0xD7, 0x00, IAP_F_FM | IAP_F_CC),
1246 IAPDESCR(D8H_00H, 0xD8, 0x00, IAP_F_FM | IAP_F_CC),
1247 IAPDESCR(D8H_01H, 0xD8, 0x01, IAP_F_FM | IAP_F_CC),
1248 IAPDESCR(D8H_02H, 0xD8, 0x02, IAP_F_FM | IAP_F_CC),
1249 IAPDESCR(D8H_03H, 0xD8, 0x03, IAP_F_FM | IAP_F_CC),
1250 IAPDESCR(D8H_04H, 0xD8, 0x04, IAP_F_FM | IAP_F_CC),
1252 IAPDESCR(D9H_00H, 0xD9, 0x00, IAP_F_FM | IAP_F_CC),
1253 IAPDESCR(D9H_01H, 0xD9, 0x01, IAP_F_FM | IAP_F_CC),
1254 IAPDESCR(D9H_02H, 0xD9, 0x02, IAP_F_FM | IAP_F_CC),
1255 IAPDESCR(D9H_03H, 0xD9, 0x03, IAP_F_FM | IAP_F_CC),
1257 IAPDESCR(DAH_00H, 0xDA, 0x00, IAP_F_FM | IAP_F_CC),
1258 IAPDESCR(DAH_01H, 0xDA, 0x01, IAP_F_FM | IAP_F_CC),
1259 IAPDESCR(DAH_02H, 0xDA, 0x02, IAP_F_FM | IAP_F_CC),
1261 IAPDESCR(DBH_00H, 0xDB, 0x00, IAP_F_FM | IAP_F_CC),
1262 IAPDESCR(DBH_01H, 0xDB, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1264 IAPDESCR(DCH_01H, 0xDC, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1265 IAPDESCR(DCH_02H, 0xDC, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1266 IAPDESCR(DCH_04H, 0xDC, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1267 IAPDESCR(DCH_08H, 0xDC, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1268 IAPDESCR(DCH_10H, 0xDC, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1269 IAPDESCR(DCH_1FH, 0xDC, 0x1F, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1271 IAPDESCR(E0H_00H, 0xE0, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CC2),
1272 IAPDESCR(E0H_01H, 0xE0, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_I7 |
1275 IAPDESCR(E2H_00H, 0xE2, 0x00, IAP_F_FM | IAP_F_CC),
1277 IAPDESCR(E4H_00H, 0xE4, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1278 IAPDESCR(E4H_01H, 0xE4, 0x01, IAP_F_FM | IAP_F_I7O),
1280 IAPDESCR(E5H_01H, 0xE5, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1282 IAPDESCR(E6H_00H, 0xE6, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CC2),
1283 IAPDESCR(E6H_01H, 0xE6, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_I7 |
1285 IAPDESCR(E6H_02H, 0xE6, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1287 IAPDESCR(E8H_01H, 0xE8, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1288 IAPDESCR(E8H_02H, 0xE8, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1289 IAPDESCR(E8H_03H, 0xE8, 0x03, IAP_F_FM | IAP_F_I7),
1291 IAPDESCR(ECH_01H, 0xEC, 0x01, IAP_F_FM | IAP_F_WM),
1293 IAPDESCR(F0H_00H, 0xF0, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1294 IAPDESCR(F0H_01H, 0xF0, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1295 IAPDESCR(F0H_02H, 0xF0, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1296 IAPDESCR(F0H_04H, 0xF0, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1297 IAPDESCR(F0H_08H, 0xF0, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1298 IAPDESCR(F0H_10H, 0xF0, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1299 IAPDESCR(F0H_20H, 0xF0, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1300 IAPDESCR(F0H_40H, 0xF0, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1301 IAPDESCR(F0H_80H, 0xF0, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1303 IAPDESCR(F1H_02H, 0xF1, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1304 IAPDESCR(F1H_04H, 0xF1, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1305 IAPDESCR(F1H_07H, 0xF1, 0x07, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1307 IAPDESCR(F2H_01H, 0xF2, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1308 IAPDESCR(F2H_02H, 0xF2, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1309 IAPDESCR(F2H_04H, 0xF2, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1310 IAPDESCR(F2H_08H, 0xF2, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1311 IAPDESCR(F2H_0FH, 0xF2, 0x0F, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1313 IAPDESCR(F3H_01H, 0xF3, 0x01, IAP_F_FM | IAP_F_I7O),
1314 IAPDESCR(F3H_02H, 0xF3, 0x02, IAP_F_FM | IAP_F_I7O),
1315 IAPDESCR(F3H_04H, 0xF3, 0x04, IAP_F_FM | IAP_F_I7O),
1316 IAPDESCR(F3H_08H, 0xF3, 0x08, IAP_F_FM | IAP_F_I7O),
1317 IAPDESCR(F3H_10H, 0xF3, 0x10, IAP_F_FM | IAP_F_I7O),
1318 IAPDESCR(F3H_20H, 0xF3, 0x20, IAP_F_FM | IAP_F_I7O),
1320 IAPDESCR(F4H_01H, 0xF4, 0x01, IAP_F_FM | IAP_F_I7O),
1321 IAPDESCR(F4H_02H, 0xF4, 0x02, IAP_F_FM | IAP_F_I7O),
1322 IAPDESCR(F4H_04H, 0xF4, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_I7O),
1323 IAPDESCR(F4H_08H, 0xF4, 0x08, IAP_F_FM | IAP_F_I7O),
1324 IAPDESCR(F4H_10H, 0xF4, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1326 IAPDESCR(F6H_01H, 0xF6, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1328 IAPDESCR(F7H_01H, 0xF7, 0x01, IAP_F_FM | IAP_F_WM | IAP_F_I7),
1329 IAPDESCR(F7H_02H, 0xF7, 0x02, IAP_F_FM | IAP_F_WM | IAP_F_I7),
1330 IAPDESCR(F7H_04H, 0xF7, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_I7),
1332 IAPDESCR(F8H_00H, 0xF8, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1333 IAPDESCR(F8H_01H, 0xF8, 0x01, IAP_F_FM | IAP_F_I7O),
1335 IAPDESCR(FDH_01H, 0xFD, 0x01, IAP_F_FM | IAP_F_WM | IAP_F_I7),
1336 IAPDESCR(FDH_02H, 0xFD, 0x02, IAP_F_FM | IAP_F_WM | IAP_F_I7),
1337 IAPDESCR(FDH_04H, 0xFD, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_I7),
1338 IAPDESCR(FDH_08H, 0xFD, 0x08, IAP_F_FM | IAP_F_WM | IAP_F_I7),
1339 IAPDESCR(FDH_10H, 0xFD, 0x10, IAP_F_FM | IAP_F_WM | IAP_F_I7),
1340 IAPDESCR(FDH_20H, 0xFD, 0x20, IAP_F_FM | IAP_F_WM | IAP_F_I7),
1341 IAPDESCR(FDH_40H, 0xFD, 0x40, IAP_F_FM | IAP_F_WM | IAP_F_I7),
1344 static const int niap_events = sizeof(iap_events) / sizeof(iap_events[0]);
1347 iap_perfctr_value_to_reload_count(pmc_value_t v)
1349 v &= (1ULL << core_iap_width) - 1;
1350 return (1ULL << core_iap_width) - v;
1354 iap_reload_count_to_perfctr_value(pmc_value_t rlc)
1356 return (1ULL << core_iap_width) - rlc;
1360 iap_pmc_has_overflowed(int ri)
1365 * We treat a Core (i.e., Intel architecture v1) PMC as has
1366 * having overflowed if its MSB is zero.
1369 return ((v & (1ULL << (core_iap_width - 1))) == 0);
1373 * Check an event against the set of supported architectural events.
1375 * Returns 1 if the event is architectural and unsupported on this
1376 * CPU. Returns 0 otherwise.
1380 iap_architectural_event_is_unsupported(enum pmc_event pe)
1382 enum core_arch_events ae;
1385 case PMC_EV_IAP_EVENT_3CH_00H:
1386 ae = CORE_AE_UNHALTED_CORE_CYCLES;
1388 case PMC_EV_IAP_EVENT_C0H_00H:
1389 ae = CORE_AE_INSTRUCTION_RETIRED;
1391 case PMC_EV_IAP_EVENT_3CH_01H:
1392 ae = CORE_AE_UNHALTED_REFERENCE_CYCLES;
1394 case PMC_EV_IAP_EVENT_2EH_4FH:
1395 ae = CORE_AE_LLC_REFERENCE;
1397 case PMC_EV_IAP_EVENT_2EH_41H:
1398 ae = CORE_AE_LLC_MISSES;
1400 case PMC_EV_IAP_EVENT_C4H_00H:
1401 ae = CORE_AE_BRANCH_INSTRUCTION_RETIRED;
1403 case PMC_EV_IAP_EVENT_C5H_00H:
1404 ae = CORE_AE_BRANCH_MISSES_RETIRED;
1407 default: /* Non architectural event. */
1411 return ((core_architectural_events & (1 << ae)) == 0);
1415 iap_event_corei7_ok_on_counter(enum pmc_event pe, int ri)
1421 * Events valid only on counter 0, 1.
1423 case PMC_EV_IAP_EVENT_40H_01H:
1424 case PMC_EV_IAP_EVENT_40H_02H:
1425 case PMC_EV_IAP_EVENT_40H_04H:
1426 case PMC_EV_IAP_EVENT_40H_08H:
1427 case PMC_EV_IAP_EVENT_40H_0FH:
1428 case PMC_EV_IAP_EVENT_41H_02H:
1429 case PMC_EV_IAP_EVENT_41H_04H:
1430 case PMC_EV_IAP_EVENT_41H_08H:
1431 case PMC_EV_IAP_EVENT_42H_01H:
1432 case PMC_EV_IAP_EVENT_42H_02H:
1433 case PMC_EV_IAP_EVENT_42H_04H:
1434 case PMC_EV_IAP_EVENT_42H_08H:
1435 case PMC_EV_IAP_EVENT_43H_01H:
1436 case PMC_EV_IAP_EVENT_43H_02H:
1437 case PMC_EV_IAP_EVENT_48H_02H:
1438 case PMC_EV_IAP_EVENT_51H_01H:
1439 case PMC_EV_IAP_EVENT_51H_02H:
1440 case PMC_EV_IAP_EVENT_51H_04H:
1441 case PMC_EV_IAP_EVENT_51H_08H:
1442 case PMC_EV_IAP_EVENT_63H_01H:
1443 case PMC_EV_IAP_EVENT_63H_02H:
1448 mask = ~0; /* Any row index is ok. */
1451 return (mask & (1 << ri));
1455 iap_event_westmere_ok_on_counter(enum pmc_event pe, int ri)
1461 * Events valid only on counter 0.
1463 case PMC_EV_IAP_EVENT_B3H_01H:
1464 case PMC_EV_IAP_EVENT_B3H_02H:
1465 case PMC_EV_IAP_EVENT_B3H_04H:
1470 * Events valid only on counter 0, 1.
1472 case PMC_EV_IAP_EVENT_51H_01H:
1473 case PMC_EV_IAP_EVENT_51H_02H:
1474 case PMC_EV_IAP_EVENT_51H_04H:
1475 case PMC_EV_IAP_EVENT_51H_08H:
1476 case PMC_EV_IAP_EVENT_63H_01H:
1477 case PMC_EV_IAP_EVENT_63H_02H:
1482 mask = ~0; /* Any row index is ok. */
1485 return (mask & (1 << ri));
1489 iap_event_ok_on_counter(enum pmc_event pe, int ri)
1495 * Events valid only on counter 0.
1497 case PMC_EV_IAP_EVENT_10H_00H:
1498 case PMC_EV_IAP_EVENT_14H_00H:
1499 case PMC_EV_IAP_EVENT_18H_00H:
1500 case PMC_EV_IAP_EVENT_B3H_01H:
1501 case PMC_EV_IAP_EVENT_B3H_02H:
1502 case PMC_EV_IAP_EVENT_B3H_04H:
1503 case PMC_EV_IAP_EVENT_C1H_00H:
1504 case PMC_EV_IAP_EVENT_CBH_01H:
1505 case PMC_EV_IAP_EVENT_CBH_02H:
1510 * Events valid only on counter 1.
1512 case PMC_EV_IAP_EVENT_11H_00H:
1513 case PMC_EV_IAP_EVENT_12H_00H:
1514 case PMC_EV_IAP_EVENT_13H_00H:
1519 mask = ~0; /* Any row index is ok. */
1522 return (mask & (1 << ri));
1526 iap_allocate_pmc(int cpu, int ri, struct pmc *pm,
1527 const struct pmc_op_pmcallocate *a)
1531 struct iap_event_descr *ie;
1532 uint32_t c, caps, config, cpuflag, evsel, mask;
1534 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
1535 ("[core,%d] illegal CPU %d", __LINE__, cpu));
1536 KASSERT(ri >= 0 && ri < core_iap_npmc,
1537 ("[core,%d] illegal row-index value %d", __LINE__, ri));
1539 /* check requested capabilities */
1541 if ((IAP_PMC_CAPS & caps) != caps)
1546 if (iap_architectural_event_is_unsupported(ev))
1547 return (EOPNOTSUPP);
1549 switch (core_cputype) {
1550 case PMC_CPU_INTEL_COREI7:
1551 if (iap_event_corei7_ok_on_counter(ev, ri) == 0)
1554 case PMC_CPU_INTEL_WESTMERE:
1555 if (iap_event_westmere_ok_on_counter(ev, ri) == 0)
1559 if (iap_event_ok_on_counter(ev, ri) == 0)
1564 * Look for an event descriptor with matching CPU and event id
1568 switch (core_cputype) {
1570 case PMC_CPU_INTEL_ATOM:
1573 case PMC_CPU_INTEL_CORE:
1576 case PMC_CPU_INTEL_CORE2:
1577 cpuflag = IAP_F_CC2;
1579 case PMC_CPU_INTEL_CORE2EXTREME:
1580 cpuflag = IAP_F_CC2 | IAP_F_CC2E;
1582 case PMC_CPU_INTEL_COREI7:
1585 case PMC_CPU_INTEL_WESTMERE:
1590 for (n = 0, ie = iap_events; n < niap_events; n++, ie++)
1591 if (ie->iap_ev == ev && ie->iap_flags & cpuflag)
1594 if (n == niap_events)
1598 * A matching event descriptor has been found, so start
1599 * assembling the contents of the event select register.
1601 evsel = ie->iap_evcode;
1603 config = a->pm_md.pm_iap.pm_iap_config & ~IAP_F_CMASK;
1606 * If the event uses a fixed umask value, reject any umask
1607 * bits set by the user.
1609 if (ie->iap_flags & IAP_F_FM) {
1611 if (IAP_UMASK(config) != 0)
1614 evsel |= (ie->iap_umask << 8);
1619 * Otherwise, the UMASK value needs to be taken from
1620 * the MD fields of the allocation request. Reject
1621 * requests that specify reserved bits.
1626 if (ie->iap_umask & IAP_M_CORE) {
1627 if ((c = (config & IAP_F_CORE)) != IAP_CORE_ALL &&
1633 if (ie->iap_umask & IAP_M_AGENT)
1634 mask |= IAP_F_AGENT;
1636 if (ie->iap_umask & IAP_M_PREFETCH) {
1638 if ((c = (config & IAP_F_PREFETCH)) ==
1639 IAP_PREFETCH_RESERVED)
1642 mask |= IAP_F_PREFETCH;
1645 if (ie->iap_umask & IAP_M_MESI)
1648 if (ie->iap_umask & IAP_M_SNOOPRESPONSE)
1649 mask |= IAP_F_SNOOPRESPONSE;
1651 if (ie->iap_umask & IAP_M_SNOOPTYPE)
1652 mask |= IAP_F_SNOOPTYPE;
1654 if (ie->iap_umask & IAP_M_TRANSITION)
1655 mask |= IAP_F_TRANSITION;
1658 * If bits outside of the allowed set of umask bits
1659 * are set, reject the request.
1664 evsel |= (config & mask);
1669 * Only Atom CPUs support the 'ANY' qualifier.
1671 if (core_cputype == PMC_CPU_INTEL_ATOM)
1672 evsel |= (config & IAP_ANY);
1673 else if (config & IAP_ANY)
1677 * Check offcore response configuration.
1679 if (a->pm_md.pm_iap.pm_iap_rsp != 0) {
1680 if (ev != PMC_EV_IAP_EVENT_B7H_01H &&
1681 ev != PMC_EV_IAP_EVENT_BBH_01H)
1683 if (core_cputype == PMC_CPU_INTEL_COREI7 &&
1684 ev == PMC_EV_IAP_EVENT_BBH_01H)
1686 if ( a->pm_md.pm_iap.pm_iap_rsp & ~IA_OFFCORE_RSP_MASK)
1688 pm->pm_md.pm_iap.pm_iap_rsp =
1689 a->pm_md.pm_iap.pm_iap_rsp & IA_OFFCORE_RSP_MASK;
1692 if (caps & PMC_CAP_THRESHOLD)
1693 evsel |= (a->pm_md.pm_iap.pm_iap_config & IAP_F_CMASK);
1694 if (caps & PMC_CAP_USER)
1696 if (caps & PMC_CAP_SYSTEM)
1698 if ((caps & (PMC_CAP_USER | PMC_CAP_SYSTEM)) == 0)
1699 evsel |= (IAP_OS | IAP_USR);
1700 if (caps & PMC_CAP_EDGE)
1702 if (caps & PMC_CAP_INVERT)
1704 if (caps & PMC_CAP_INTERRUPT)
1707 pm->pm_md.pm_iap.pm_iap_evsel = evsel;
1713 iap_config_pmc(int cpu, int ri, struct pmc *pm)
1715 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
1716 ("[core,%d] illegal CPU %d", __LINE__, cpu));
1718 KASSERT(ri >= 0 && ri < core_iap_npmc,
1719 ("[core,%d] illegal row-index %d", __LINE__, ri));
1721 PMCDBG(MDP,CFG,1, "iap-config cpu=%d ri=%d pm=%p", cpu, ri, pm);
1723 KASSERT(core_pcpu[cpu] != NULL, ("[core,%d] null per-cpu %d", __LINE__,
1726 core_pcpu[cpu]->pc_corepmcs[ri].phw_pmc = pm;
1732 iap_describe(int cpu, int ri, struct pmc_info *pi, struct pmc **ppmc)
1736 char iap_name[PMC_NAME_MAX];
1738 phw = &core_pcpu[cpu]->pc_corepmcs[ri];
1740 (void) snprintf(iap_name, sizeof(iap_name), "IAP-%d", ri);
1741 if ((error = copystr(iap_name, pi->pm_name, PMC_NAME_MAX,
1745 pi->pm_class = PMC_CLASS_IAP;
1747 if (phw->phw_state & PMC_PHW_FLAG_IS_ENABLED) {
1748 pi->pm_enabled = TRUE;
1749 *ppmc = phw->phw_pmc;
1751 pi->pm_enabled = FALSE;
1759 iap_get_config(int cpu, int ri, struct pmc **ppm)
1761 *ppm = core_pcpu[cpu]->pc_corepmcs[ri].phw_pmc;
1767 iap_get_msr(int ri, uint32_t *msr)
1769 KASSERT(ri >= 0 && ri < core_iap_npmc,
1770 ("[iap,%d] ri %d out of range", __LINE__, ri));
1778 iap_read_pmc(int cpu, int ri, pmc_value_t *v)
1783 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
1784 ("[core,%d] illegal cpu value %d", __LINE__, cpu));
1785 KASSERT(ri >= 0 && ri < core_iap_npmc,
1786 ("[core,%d] illegal row-index %d", __LINE__, ri));
1788 pm = core_pcpu[cpu]->pc_corepmcs[ri].phw_pmc;
1791 ("[core,%d] cpu %d ri %d pmc not configured", __LINE__, cpu,
1795 if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm)))
1796 *v = iap_perfctr_value_to_reload_count(tmp);
1800 PMCDBG(MDP,REA,1, "iap-read cpu=%d ri=%d msr=0x%x -> v=%jx", cpu, ri,
1807 iap_release_pmc(int cpu, int ri, struct pmc *pm)
1811 PMCDBG(MDP,REL,1, "iap-release cpu=%d ri=%d pm=%p", cpu, ri,
1814 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
1815 ("[core,%d] illegal CPU value %d", __LINE__, cpu));
1816 KASSERT(ri >= 0 && ri < core_iap_npmc,
1817 ("[core,%d] illegal row-index %d", __LINE__, ri));
1819 KASSERT(core_pcpu[cpu]->pc_corepmcs[ri].phw_pmc
1820 == NULL, ("[core,%d] PHW pmc non-NULL", __LINE__));
1826 iap_start_pmc(int cpu, int ri)
1830 struct core_cpu *cc;
1832 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
1833 ("[core,%d] illegal CPU value %d", __LINE__, cpu));
1834 KASSERT(ri >= 0 && ri < core_iap_npmc,
1835 ("[core,%d] illegal row-index %d", __LINE__, ri));
1837 cc = core_pcpu[cpu];
1838 pm = cc->pc_corepmcs[ri].phw_pmc;
1841 ("[core,%d] starting cpu%d,ri%d with no pmc configured",
1842 __LINE__, cpu, ri));
1844 PMCDBG(MDP,STA,1, "iap-start cpu=%d ri=%d", cpu, ri);
1846 evsel = pm->pm_md.pm_iap.pm_iap_evsel;
1848 PMCDBG(MDP,STA,2, "iap-start/2 cpu=%d ri=%d evselmsr=0x%x evsel=0x%x",
1849 cpu, ri, IAP_EVSEL0 + ri, evsel);
1851 /* Event specific configuration. */
1852 switch (pm->pm_event) {
1853 case PMC_EV_IAP_EVENT_B7H_01H:
1854 wrmsr(IA_OFFCORE_RSP0, pm->pm_md.pm_iap.pm_iap_rsp);
1856 case PMC_EV_IAP_EVENT_BBH_01H:
1857 wrmsr(IA_OFFCORE_RSP1, pm->pm_md.pm_iap.pm_iap_rsp);
1863 wrmsr(IAP_EVSEL0 + ri, evsel | IAP_EN);
1865 if (core_cputype == PMC_CPU_INTEL_CORE)
1870 cc->pc_globalctrl |= (1ULL << ri);
1871 wrmsr(IA_GLOBAL_CTRL, cc->pc_globalctrl);
1872 } while (cc->pc_resync != 0);
1878 iap_stop_pmc(int cpu, int ri)
1881 struct core_cpu *cc;
1883 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
1884 ("[core,%d] illegal cpu value %d", __LINE__, cpu));
1885 KASSERT(ri >= 0 && ri < core_iap_npmc,
1886 ("[core,%d] illegal row index %d", __LINE__, ri));
1888 cc = core_pcpu[cpu];
1889 pm = cc->pc_corepmcs[ri].phw_pmc;
1892 ("[core,%d] cpu%d ri%d no configured PMC to stop", __LINE__,
1895 PMCDBG(MDP,STO,1, "iap-stop cpu=%d ri=%d", cpu, ri);
1897 wrmsr(IAP_EVSEL0 + ri, 0); /* stop hw */
1899 if (core_cputype == PMC_CPU_INTEL_CORE)
1904 cc->pc_globalctrl &= ~(1ULL << ri);
1905 wrmsr(IA_GLOBAL_CTRL, cc->pc_globalctrl);
1906 } while (cc->pc_resync != 0);
1912 iap_write_pmc(int cpu, int ri, pmc_value_t v)
1915 struct core_cpu *cc;
1917 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
1918 ("[core,%d] illegal cpu value %d", __LINE__, cpu));
1919 KASSERT(ri >= 0 && ri < core_iap_npmc,
1920 ("[core,%d] illegal row index %d", __LINE__, ri));
1922 cc = core_pcpu[cpu];
1923 pm = cc->pc_corepmcs[ri].phw_pmc;
1926 ("[core,%d] cpu%d ri%d no configured PMC to stop", __LINE__,
1929 PMCDBG(MDP,WRI,1, "iap-write cpu=%d ri=%d msr=0x%x v=%jx", cpu, ri,
1932 if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm)))
1933 v = iap_reload_count_to_perfctr_value(v);
1936 * Write the new value to the counter. The counter will be in
1937 * a stopped state when the pcd_write() entry point is called.
1940 wrmsr(IAP_PMC0 + ri, v);
1947 iap_initialize(struct pmc_mdep *md, int maxcpu, int npmc, int pmcwidth,
1950 struct pmc_classdep *pcd;
1952 KASSERT(md != NULL, ("[iap,%d] md is NULL", __LINE__));
1954 PMCDBG(MDP,INI,1, "%s", "iap-initialize");
1956 /* Remember the set of architectural events supported. */
1957 core_architectural_events = ~flags;
1959 pcd = &md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAP];
1961 pcd->pcd_caps = IAP_PMC_CAPS;
1962 pcd->pcd_class = PMC_CLASS_IAP;
1963 pcd->pcd_num = npmc;
1964 pcd->pcd_ri = md->pmd_npmc;
1965 pcd->pcd_width = pmcwidth;
1967 pcd->pcd_allocate_pmc = iap_allocate_pmc;
1968 pcd->pcd_config_pmc = iap_config_pmc;
1969 pcd->pcd_describe = iap_describe;
1970 pcd->pcd_get_config = iap_get_config;
1971 pcd->pcd_get_msr = iap_get_msr;
1972 pcd->pcd_pcpu_fini = core_pcpu_fini;
1973 pcd->pcd_pcpu_init = core_pcpu_init;
1974 pcd->pcd_read_pmc = iap_read_pmc;
1975 pcd->pcd_release_pmc = iap_release_pmc;
1976 pcd->pcd_start_pmc = iap_start_pmc;
1977 pcd->pcd_stop_pmc = iap_stop_pmc;
1978 pcd->pcd_write_pmc = iap_write_pmc;
1980 md->pmd_npmc += npmc;
1984 core_intr(int cpu, struct trapframe *tf)
1988 struct core_cpu *cc;
1989 int error, found_interrupt, ri;
1991 PMCDBG(MDP,INT, 1, "cpu=%d tf=0x%p um=%d", cpu, (void *) tf,
1992 TRAPF_USERMODE(tf));
1994 found_interrupt = 0;
1995 cc = core_pcpu[cpu];
1997 for (ri = 0; ri < core_iap_npmc; ri++) {
1999 if ((pm = cc->pc_corepmcs[ri].phw_pmc) == NULL ||
2000 !PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm)))
2003 if (!iap_pmc_has_overflowed(ri))
2006 found_interrupt = 1;
2008 if (pm->pm_state != PMC_STATE_RUNNING)
2011 error = pmc_process_interrupt(cpu, pm, tf,
2012 TRAPF_USERMODE(tf));
2014 v = pm->pm_sc.pm_reloadcount;
2015 v = iaf_reload_count_to_perfctr_value(v);
2018 * Stop the counter, reload it but only restart it if
2019 * the PMC is not stalled.
2021 wrmsr(IAP_EVSEL0 + ri, 0);
2022 wrmsr(IAP_PMC0 + ri, v);
2027 wrmsr(IAP_EVSEL0 + ri,
2028 pm->pm_md.pm_iap.pm_iap_evsel | IAP_EN);
2031 if (found_interrupt)
2032 lapic_reenable_pmc();
2034 atomic_add_int(found_interrupt ? &pmc_stats.pm_intr_processed :
2035 &pmc_stats.pm_intr_ignored, 1);
2037 return (found_interrupt);
2041 core2_intr(int cpu, struct trapframe *tf)
2043 int error, found_interrupt, n;
2044 uint64_t flag, intrstatus, intrenable;
2046 struct core_cpu *cc;
2049 PMCDBG(MDP,INT, 1, "cpu=%d tf=0x%p um=%d", cpu, (void *) tf,
2050 TRAPF_USERMODE(tf));
2053 * The IA_GLOBAL_STATUS (MSR 0x38E) register indicates which
2054 * PMCs have a pending PMI interrupt. We take a 'snapshot' of
2055 * the current set of interrupting PMCs and process these
2056 * after stopping them.
2058 intrstatus = rdmsr(IA_GLOBAL_STATUS);
2059 intrenable = intrstatus & core_pmcmask;
2061 PMCDBG(MDP,INT, 1, "cpu=%d intrstatus=%jx", cpu,
2062 (uintmax_t) intrstatus);
2064 found_interrupt = 0;
2065 cc = core_pcpu[cpu];
2067 KASSERT(cc != NULL, ("[core,%d] null pcpu", __LINE__));
2069 cc->pc_globalctrl &= ~intrenable;
2070 cc->pc_resync = 1; /* MSRs now potentially out of sync. */
2073 * Stop PMCs and clear overflow status bits.
2075 wrmsr(IA_GLOBAL_CTRL, 0);
2076 wrmsr(IA_GLOBAL_OVF_CTRL, intrenable |
2077 IA_GLOBAL_STATUS_FLAG_OVFBUF |
2078 IA_GLOBAL_STATUS_FLAG_CONDCHG);
2081 * Look for interrupts from fixed function PMCs.
2083 for (n = 0, flag = (1ULL << IAF_OFFSET); n < core_iaf_npmc;
2086 if ((intrstatus & flag) == 0)
2089 found_interrupt = 1;
2091 pm = cc->pc_corepmcs[n + core_iaf_ri].phw_pmc;
2092 if (pm == NULL || pm->pm_state != PMC_STATE_RUNNING ||
2093 !PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm)))
2096 error = pmc_process_interrupt(cpu, pm, tf,
2097 TRAPF_USERMODE(tf));
2099 intrenable &= ~flag;
2101 v = iaf_reload_count_to_perfctr_value(pm->pm_sc.pm_reloadcount);
2103 /* Reload sampling count. */
2104 wrmsr(IAF_CTR0 + n, v);
2106 PMCDBG(MDP,INT, 1, "iaf-intr cpu=%d error=%d v=%jx(%jx)", cpu, error,
2107 (uintmax_t) v, (uintmax_t) rdpmc(IAF_RI_TO_MSR(n)));
2111 * Process interrupts from the programmable counters.
2113 for (n = 0, flag = 1; n < core_iap_npmc; n++, flag <<= 1) {
2114 if ((intrstatus & flag) == 0)
2117 found_interrupt = 1;
2119 pm = cc->pc_corepmcs[n].phw_pmc;
2120 if (pm == NULL || pm->pm_state != PMC_STATE_RUNNING ||
2121 !PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm)))
2124 error = pmc_process_interrupt(cpu, pm, tf,
2125 TRAPF_USERMODE(tf));
2127 intrenable &= ~flag;
2129 v = iap_reload_count_to_perfctr_value(pm->pm_sc.pm_reloadcount);
2131 PMCDBG(MDP,INT, 1, "iap-intr cpu=%d error=%d v=%jx", cpu, error,
2134 /* Reload sampling count. */
2135 wrmsr(IAP_PMC0 + n, v);
2139 * Reenable all non-stalled PMCs.
2141 PMCDBG(MDP,INT, 1, "cpu=%d intrenable=%jx", cpu,
2142 (uintmax_t) intrenable);
2144 cc->pc_globalctrl |= intrenable;
2146 wrmsr(IA_GLOBAL_CTRL, cc->pc_globalctrl);
2148 PMCDBG(MDP,INT, 1, "cpu=%d fixedctrl=%jx globalctrl=%jx status=%jx "
2149 "ovf=%jx", cpu, (uintmax_t) rdmsr(IAF_CTRL),
2150 (uintmax_t) rdmsr(IA_GLOBAL_CTRL),
2151 (uintmax_t) rdmsr(IA_GLOBAL_STATUS),
2152 (uintmax_t) rdmsr(IA_GLOBAL_OVF_CTRL));
2154 if (found_interrupt)
2155 lapic_reenable_pmc();
2157 atomic_add_int(found_interrupt ? &pmc_stats.pm_intr_processed :
2158 &pmc_stats.pm_intr_ignored, 1);
2160 return (found_interrupt);
2164 pmc_core_initialize(struct pmc_mdep *md, int maxcpu)
2166 int cpuid[CORE_CPUID_REQUEST_SIZE];
2167 int ipa_version, flags, nflags;
2169 do_cpuid(CORE_CPUID_REQUEST, cpuid);
2171 ipa_version = cpuid[CORE_CPUID_EAX] & 0xFF;
2173 PMCDBG(MDP,INI,1,"core-init cputype=%d ncpu=%d ipa-version=%d",
2174 md->pmd_cputype, maxcpu, ipa_version);
2176 if (ipa_version < 1 || ipa_version > 3) /* Unknown PMC architecture. */
2177 return (EPROGMISMATCH);
2179 core_cputype = md->pmd_cputype;
2184 * Initialize programmable counters.
2186 KASSERT(ipa_version >= 1,
2187 ("[core,%d] ipa_version %d too small", __LINE__, ipa_version));
2189 core_iap_npmc = (cpuid[CORE_CPUID_EAX] >> 8) & 0xFF;
2190 core_iap_width = (cpuid[CORE_CPUID_EAX] >> 16) & 0xFF;
2192 core_pmcmask |= ((1ULL << core_iap_npmc) - 1);
2194 nflags = (cpuid[CORE_CPUID_EAX] >> 24) & 0xFF;
2195 flags = cpuid[CORE_CPUID_EBX] & ((1 << nflags) - 1);
2197 iap_initialize(md, maxcpu, core_iap_npmc, core_iap_width, flags);
2200 * Initialize fixed function counters, if present.
2202 if (core_cputype != PMC_CPU_INTEL_CORE) {
2203 KASSERT(ipa_version >= 2,
2204 ("[core,%d] ipa_version %d too small", __LINE__,
2207 core_iaf_ri = core_iap_npmc;
2208 core_iaf_npmc = cpuid[CORE_CPUID_EDX] & 0x1F;
2209 core_iaf_width = (cpuid[CORE_CPUID_EDX] >> 5) & 0xFF;
2211 if (core_iaf_npmc > 0) {
2212 iaf_initialize(md, maxcpu, core_iaf_npmc,
2214 core_pmcmask |= ((1ULL << core_iaf_npmc) - 1) <<
2218 * Adjust the number of classes exported to
2222 KASSERT(md->pmd_nclass == 2,
2223 ("[core,%d] unexpected nclass %d", __LINE__,
2228 PMCDBG(MDP,INI,1,"core-init pmcmask=0x%jx iafri=%d", core_pmcmask,
2231 core_pcpu = malloc(sizeof(struct core_cpu **) * maxcpu, M_PMC,
2235 * Choose the appropriate interrupt handler.
2237 if (ipa_version == 1)
2238 md->pmd_intr = core_intr;
2240 md->pmd_intr = core2_intr;
2242 md->pmd_pcpu_fini = NULL;
2243 md->pmd_pcpu_init = NULL;
2249 pmc_core_finalize(struct pmc_mdep *md)
2251 PMCDBG(MDP,INI,1, "%s", "core-finalize");
2253 free(core_pcpu, M_PMC);