sys/dev/hwpmc/hwpmc_intel.c

   1 /*-
   2  * Copyright (c) 2008 Joseph Koshy
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  * 1. Redistributions of source code must retain the above copyright
   9  *    notice, this list of conditions and the following disclaimer.
  10  * 2. Redistributions in binary form must reproduce the above copyright
  11  *    notice, this list of conditions and the following disclaimer in the
  12  *    documentation and/or other materials provided with the distribution.
  13  *
  14  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  15  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  16  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  17  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  18  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  19  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  20  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  21  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  22  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  23  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  24  * SUCH DAMAGE.
  25  */
  26
  27 /*
  28  * Common code for handling Intel CPUs.
  29  */
  30
  31 #include <sys/cdefs.h>
  32 __FBSDID("$FreeBSD$");
  33
  34 #include <sys/param.h>
  35 #include <sys/pmc.h>
  36 #include <sys/pmckern.h>
  37 #include <sys/systm.h>
  38
  39 #include <machine/cpu.h>
  40 #include <machine/cputypes.h>
  41 #include <machine/md_var.h>
  42 #include <machine/specialreg.h>
  43
  44 static int
  45 intel_switch_in(struct pmc_cpu *pc, struct pmc_process *pp)
  46 {
  47         (void) pc;
  48
  49         PMCDBG(MDP,SWI,1, "pc=%p pp=%p enable-msr=%d", pc, pp,
  50             pp->pp_flags & PMC_PP_ENABLE_MSR_ACCESS);
  51
  52         /* allow the RDPMC instruction if needed */
  53         if (pp->pp_flags & PMC_PP_ENABLE_MSR_ACCESS)
  54                 load_cr4(rcr4() | CR4_PCE);
  55
  56         PMCDBG(MDP,SWI,1, "cr4=0x%jx", (uintmax_t) rcr4());
  57
  58         return 0;
  59 }
  60
  61 static int
  62 intel_switch_out(struct pmc_cpu *pc, struct pmc_process *pp)
  63 {
  64         (void) pc;
  65         (void) pp;              /* can be NULL */
  66
  67         PMCDBG(MDP,SWO,1, "pc=%p pp=%p cr4=0x%jx", pc, pp,
  68             (uintmax_t) rcr4());
  69
  70         /* always turn off the RDPMC instruction */
  71         load_cr4(rcr4() & ~CR4_PCE);
  72
  73         return 0;
  74 }
  75
  76 struct pmc_mdep *
  77 pmc_intel_initialize(void)
  78 {
  79         struct pmc_mdep *pmc_mdep;
  80         enum pmc_cputype cputype;
  81         int error, model, nclasses, ncpus;
  82
  83         KASSERT(cpu_vendor_id == CPU_VENDOR_INTEL,
  84             ("[intel,%d] Initializing non-intel processor", __LINE__));
  85
  86         PMCDBG(MDP,INI,0, "intel-initialize cpuid=0x%x", cpu_id);
  87
  88         cputype = -1;
  89         nclasses = 2;
  90
  91         model = ((cpu_id & 0xF0000) >> 12) | ((cpu_id & 0xF0) >> 4);
  92
  93         switch (cpu_id & 0xF00) {
  94 #if     defined(__i386__)
  95         case 0x500:             /* Pentium family processors */
  96                 cputype = PMC_CPU_INTEL_P5;
  97                 break;
  98 #endif
  99         case 0x600:             /* Pentium Pro, Celeron, Pentium II & III */
 100                 switch (model) {
 101 #if     defined(__i386__)
 102                 case 0x1:
 103                         cputype = PMC_CPU_INTEL_P6;
 104                         break;
 105                 case 0x3: case 0x5:
 106                         cputype = PMC_CPU_INTEL_PII;
 107                         break;
 108                 case 0x6: case 0x16:
 109                         cputype = PMC_CPU_INTEL_CL;
 110                         break;
 111                 case 0x7: case 0x8: case 0xA: case 0xB:
 112                         cputype = PMC_CPU_INTEL_PIII;
 113                         break;
 114                 case 0x9: case 0xD:
 115                         cputype = PMC_CPU_INTEL_PM;
 116                         break;
 117 #endif
 118                 case 0xE:
 119                         cputype = PMC_CPU_INTEL_CORE;
 120                         break;
 121                 case 0xF:
 122                         cputype = PMC_CPU_INTEL_CORE2;
 123                         nclasses = 3;
 124                         break;
 125                 case 0x17:
 126                         cputype = PMC_CPU_INTEL_CORE2EXTREME;
 127                         nclasses = 3;
 128                         break;
 129                 case 0x1C:      /* Per Intel document 320047-002. */
 130                         cputype = PMC_CPU_INTEL_ATOM;
 131                         nclasses = 3;
 132                         break;
 133                 case 0x1A:
 134                 case 0x2E:
 135                         cputype = PMC_CPU_INTEL_COREI7;
 136                         nclasses = 5;
 137                         break;
 138                 case 0x25:      /* Per Intel document 253669-033US 12/2009. */
 139                 case 0x2C:      /* Per Intel document 253669-033US 12/2009. */
 140                         cputype = PMC_CPU_INTEL_WESTMERE;
 141                         nclasses = 5;
 142                         break;
 143                 }
 144                 break;
 145 #if     defined(__i386__) || defined(__amd64__)
 146         case 0xF00:             /* P4 */
 147                 if (model >= 0 && model <= 6) /* known models */
 148                         cputype = PMC_CPU_INTEL_PIV;
 149                 break;
 150         }
 151 #endif
 152
 153         if ((int) cputype == -1) {
 154                 printf("pmc: Unknown Intel CPU.\n");
 155                 return (NULL);
 156         }
 157
 158         pmc_mdep = malloc(sizeof(struct pmc_mdep) + nclasses *
 159             sizeof(struct pmc_classdep), M_PMC, M_WAITOK|M_ZERO);
 160
 161         pmc_mdep->pmd_cputype    = cputype;
 162         pmc_mdep->pmd_nclass     = nclasses;
 163
 164         pmc_mdep->pmd_switch_in  = intel_switch_in;
 165         pmc_mdep->pmd_switch_out = intel_switch_out;
 166
 167         ncpus = pmc_cpu_max();
 168
 169         error = pmc_tsc_initialize(pmc_mdep, ncpus);
 170         if (error)
 171                 goto error;
 172
 173         switch (cputype) {
 174 #if     defined(__i386__) || defined(__amd64__)
 175                 /*
 176                  * Intel Core, Core 2 and Atom processors.
 177                  */
 178         case PMC_CPU_INTEL_ATOM:
 179         case PMC_CPU_INTEL_CORE:
 180         case PMC_CPU_INTEL_CORE2:
 181         case PMC_CPU_INTEL_CORE2EXTREME:
 182         case PMC_CPU_INTEL_COREI7:
 183         case PMC_CPU_INTEL_WESTMERE:
 184                 error = pmc_core_initialize(pmc_mdep, ncpus);
 185                 break;
 186
 187                 /*
 188                  * Intel Pentium 4 Processors, and P4/EMT64 processors.
 189                  */
 190
 191         case PMC_CPU_INTEL_PIV:
 192                 error = pmc_p4_initialize(pmc_mdep, ncpus);
 193
 194                 KASSERT(pmc_mdep->pmd_npmc == TSC_NPMCS + P4_NPMCS,
 195                     ("[intel,%d] incorrect npmc count %d", __LINE__,
 196                     pmc_mdep->pmd_npmc));
 197                 break;
 198 #endif
 199
 200 #if     defined(__i386__)
 201                 /*
 202                  * P6 Family Processors
 203                  */
 204
 205         case PMC_CPU_INTEL_P6:
 206         case PMC_CPU_INTEL_CL:
 207         case PMC_CPU_INTEL_PII:
 208         case PMC_CPU_INTEL_PIII:
 209         case PMC_CPU_INTEL_PM:
 210                 error = pmc_p6_initialize(pmc_mdep, ncpus);
 211
 212                 KASSERT(pmc_mdep->pmd_npmc == TSC_NPMCS + P6_NPMCS,
 213                     ("[intel,%d] incorrect npmc count %d", __LINE__,
 214                     pmc_mdep->pmd_npmc));
 215                 break;
 216
 217                 /*
 218                  * Intel Pentium PMCs.
 219                  */
 220
 221         case PMC_CPU_INTEL_P5:
 222                 error = pmc_p5_initialize(pmc_mdep, ncpus);
 223
 224                 KASSERT(pmc_mdep->pmd_npmc == TSC_NPMCS + PENTIUM_NPMCS,
 225                     ("[intel,%d] incorrect npmc count %d", __LINE__,
 226                     pmc_mdep->pmd_npmc));
 227                 break;
 228 #endif
 229
 230         default:
 231                 KASSERT(0, ("[intel,%d] Unknown CPU type", __LINE__));
 232         }
 233
 234         /*
 235          * Init the uncore class.
 236          */
 237 #if     defined(__i386__) || defined(__amd64__)
 238         switch (cputype) {
 239                 /*
 240                  * Intel Corei7 and Westmere processors.
 241                  */
 242         case PMC_CPU_INTEL_COREI7:
 243         case PMC_CPU_INTEL_WESTMERE:
 244                 error = pmc_uncore_initialize(pmc_mdep, ncpus);
 245                 break;
 246         default:
 247                 break;
 248         }
 249 #endif
 250
 251   error:
 252         if (error) {
 253                 free(pmc_mdep, M_PMC);
 254                 pmc_mdep = NULL;
 255         }
 256
 257         return (pmc_mdep);
 258 }
 259
 260 void
 261 pmc_intel_finalize(struct pmc_mdep *md)
 262 {
 263         pmc_tsc_finalize(md);
 264
 265         switch (md->pmd_cputype) {
 266 #if     defined(__i386__) || defined(__amd64__)
 267         case PMC_CPU_INTEL_ATOM:
 268         case PMC_CPU_INTEL_CORE:
 269         case PMC_CPU_INTEL_CORE2:
 270         case PMC_CPU_INTEL_CORE2EXTREME:
 271         case PMC_CPU_INTEL_COREI7:
 272         case PMC_CPU_INTEL_WESTMERE:
 273                 pmc_core_finalize(md);
 274                 break;
 275
 276         case PMC_CPU_INTEL_PIV:
 277                 pmc_p4_finalize(md);
 278                 break;
 279 #endif
 280 #if     defined(__i386__)
 281         case PMC_CPU_INTEL_P6:
 282         case PMC_CPU_INTEL_CL:
 283         case PMC_CPU_INTEL_PII:
 284         case PMC_CPU_INTEL_PIII:
 285         case PMC_CPU_INTEL_PM:
 286                 pmc_p6_finalize(md);
 287                 break;
 288         case PMC_CPU_INTEL_P5:
 289                 pmc_p5_finalize(md);
 290                 break;
 291 #endif
 292         default:
 293                 KASSERT(0, ("[intel,%d] unknown CPU type", __LINE__));
 294         }
 295
 296         /*
 297          * Uncore.
 298          */
 299 #if     defined(__i386__) || defined(__amd64__)
 300         switch (md->pmd_cputype) {
 301         case PMC_CPU_INTEL_COREI7:
 302         case PMC_CPU_INTEL_WESTMERE:
 303                 pmc_uncore_finalize(md);
 304                 break;
 305         default:
 306                 break;
 307         }
 308 #endif
 309 }