2 * Copyright (c) 2004 Texas A&M University
5 * Developer: Wm. Daryl Hawkins
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 * Intel ICH Watchdog Timer (WDT) driver
32 * Originally developed by Wm. Daryl Hawkins of Texas A&M
33 * Heavily modified by <des@FreeBSD.org>
35 * This is a tricky one. The ICH WDT can't be treated as a regular PCI
36 * device as it's actually an integrated function of the ICH LPC interface
37 * bridge. Detection is also awkward, because we can only infer the
38 * presence of the watchdog timer from the fact that the machine has an
39 * ICH chipset, or, on ACPI 2.x systems, by the presence of the 'WDDT'
40 * ACPI table (although this driver does not support the ACPI detection
43 * There is one slight problem on non-ACPI or ACPI 1.x systems: we have no
44 * way of knowing if the WDT is permanently disabled (either by the BIOS
47 * The WDT is programmed through I/O registers in the ACPI I/O space.
48 * Intel swears it's always at offset 0x60, so we use that.
50 * For details about the ICH WDT, see Intel Application Note AP-725
51 * (document no. 292273-001). The WDT is also described in the individual
52 * chipset datasheets, e.g. Intel82801EB ICH5 / 82801ER ICH5R Datasheet
53 * (document no. 252516-001) sections 9.10 and 9.11.
55 * ICH6/7/8 support by Takeharu KATO <takeharu1219@ybb.ne.jp>
58 #include <sys/cdefs.h>
59 __FBSDID("$FreeBSD$");
61 #include <sys/param.h>
62 #include <sys/kernel.h>
63 #include <sys/module.h>
64 #include <sys/systm.h>
66 #include <machine/bus.h>
68 #include <machine/resource.h>
69 #include <sys/watchdog.h>
71 #include <isa/isavar.h>
72 #include <dev/pci/pcivar.h>
74 #include <dev/ichwd/ichwd.h>
76 static struct ichwd_device ichwd_devices[] = {
77 { DEVICEID_82801AA, "Intel 82801AA watchdog timer", 1 },
78 { DEVICEID_82801AB, "Intel 82801AB watchdog timer", 1 },
79 { DEVICEID_82801BA, "Intel 82801BA watchdog timer", 2 },
80 { DEVICEID_82801BAM, "Intel 82801BAM watchdog timer", 2 },
81 { DEVICEID_82801CA, "Intel 82801CA watchdog timer", 3 },
82 { DEVICEID_82801CAM, "Intel 82801CAM watchdog timer", 3 },
83 { DEVICEID_82801DB, "Intel 82801DB watchdog timer", 4 },
84 { DEVICEID_82801DBM, "Intel 82801DBM watchdog timer", 4 },
85 { DEVICEID_82801E, "Intel 82801E watchdog timer", 5 },
86 { DEVICEID_82801EB, "Intel 82801EB watchdog timer", 5 },
87 { DEVICEID_82801EBR, "Intel 82801EB/ER watchdog timer", 5 },
88 { DEVICEID_6300ESB, "Intel 6300ESB watchdog timer", 5 },
89 { DEVICEID_82801FBR, "Intel 82801FB/FR watchdog timer", 6 },
90 { DEVICEID_ICH6M, "Intel ICH6M watchdog timer", 6 },
91 { DEVICEID_ICH6W, "Intel ICH6W watchdog timer", 6 },
92 { DEVICEID_ICH7, "Intel ICH7 watchdog timer", 7 },
93 { DEVICEID_ICH7DH, "Intel ICH7DH watchdog timer", 7 },
94 { DEVICEID_ICH7M, "Intel ICH7M watchdog timer", 7 },
95 { DEVICEID_ICH7MDH, "Intel ICH7MDH watchdog timer", 7 },
96 { DEVICEID_ICH8, "Intel ICH8 watchdog timer", 8 },
97 { DEVICEID_ICH8DH, "Intel ICH8DH watchdog timer", 8 },
98 { DEVICEID_ICH8DO, "Intel ICH8DO watchdog timer", 8 },
99 { DEVICEID_ICH8M, "Intel ICH8M watchdog timer", 8 },
100 { DEVICEID_ICH8ME, "Intel ICH8M-E watchdog timer", 8 },
101 { DEVICEID_63XXESB, "Intel 63XXESB watchdog timer", 8 },
102 { DEVICEID_ICH9, "Intel ICH9 watchdog timer", 9 },
103 { DEVICEID_ICH9DH, "Intel ICH9DH watchdog timer", 9 },
104 { DEVICEID_ICH9DO, "Intel ICH9DO watchdog timer", 9 },
105 { DEVICEID_ICH9M, "Intel ICH9M watchdog timer", 9 },
106 { DEVICEID_ICH9ME, "Intel ICH9M-E watchdog timer", 9 },
107 { DEVICEID_ICH9R, "Intel ICH9R watchdog timer", 9 },
108 { DEVICEID_ICH10, "Intel ICH10 watchdog timer", 10 },
109 { DEVICEID_ICH10D, "Intel ICH10D watchdog timer", 10 },
110 { DEVICEID_ICH10DO, "Intel ICH10DO watchdog timer", 10 },
111 { DEVICEID_ICH10R, "Intel ICH10R watchdog timer", 10 },
112 { DEVICEID_H55, "Intel H55 watchdog timer", 10 },
116 static devclass_t ichwd_devclass;
118 #define ichwd_read_tco_1(sc, off) \
119 bus_space_read_1((sc)->tco_bst, (sc)->tco_bsh, (off))
120 #define ichwd_read_tco_2(sc, off) \
121 bus_space_read_2((sc)->tco_bst, (sc)->tco_bsh, (off))
122 #define ichwd_read_tco_4(sc, off) \
123 bus_space_read_4((sc)->tco_bst, (sc)->tco_bsh, (off))
124 #define ichwd_read_smi_4(sc, off) \
125 bus_space_read_4((sc)->smi_bst, (sc)->smi_bsh, (off))
126 #define ichwd_read_gcs_4(sc, off) \
127 bus_space_read_4((sc)->gcs_bst, (sc)->gcs_bsh, (off))
129 #define ichwd_write_tco_1(sc, off, val) \
130 bus_space_write_1((sc)->tco_bst, (sc)->tco_bsh, (off), (val))
131 #define ichwd_write_tco_2(sc, off, val) \
132 bus_space_write_2((sc)->tco_bst, (sc)->tco_bsh, (off), (val))
133 #define ichwd_write_tco_4(sc, off, val) \
134 bus_space_write_4((sc)->tco_bst, (sc)->tco_bsh, (off), (val))
135 #define ichwd_write_smi_4(sc, off, val) \
136 bus_space_write_4((sc)->smi_bst, (sc)->smi_bsh, (off), (val))
137 #define ichwd_write_gcs_4(sc, off, val) \
138 bus_space_write_4((sc)->gcs_bst, (sc)->gcs_bsh, (off), (val))
140 #define ichwd_verbose_printf(dev, ...) \
143 device_printf(dev, __VA_ARGS__);\
147 * Disable the watchdog timeout SMI handler.
149 * Apparently, some BIOSes install handlers that reset or disable the
150 * watchdog timer instead of resetting the system, so we disable the SMI
151 * (by clearing the SMI_TCO_EN bit of the SMI_EN register) to prevent this
155 ichwd_smi_disable(struct ichwd_softc *sc)
157 ichwd_write_smi_4(sc, SMI_EN, ichwd_read_smi_4(sc, SMI_EN) & ~SMI_TCO_EN);
161 * Enable the watchdog timeout SMI handler. See above for details.
164 ichwd_smi_enable(struct ichwd_softc *sc)
166 ichwd_write_smi_4(sc, SMI_EN, ichwd_read_smi_4(sc, SMI_EN) | SMI_TCO_EN);
170 * Reset the watchdog status bits.
173 ichwd_sts_reset(struct ichwd_softc *sc)
176 * The watchdog status bits are set to 1 by the hardware to
177 * indicate various conditions. They can be cleared by software
178 * by writing a 1, not a 0.
180 ichwd_write_tco_2(sc, TCO1_STS, TCO_TIMEOUT);
182 * XXX The datasheet says that TCO_SECOND_TO_STS must be cleared
183 * before TCO_BOOT_STS, not the other way around.
185 ichwd_write_tco_2(sc, TCO2_STS, TCO_BOOT_STS);
186 ichwd_write_tco_2(sc, TCO2_STS, TCO_SECOND_TO_STS);
190 * Enable the watchdog timer by clearing the TCO_TMR_HALT bit in the
191 * TCO1_CNT register. This is complicated by the need to preserve bit 9
192 * of that same register, and the requirement that all other bits must be
193 * written back as zero.
196 ichwd_tmr_enable(struct ichwd_softc *sc)
200 cnt = ichwd_read_tco_2(sc, TCO1_CNT) & TCO_CNT_PRESERVE;
201 ichwd_write_tco_2(sc, TCO1_CNT, cnt & ~TCO_TMR_HALT);
203 ichwd_verbose_printf(sc->device, "timer enabled\n");
207 * Disable the watchdog timer. See above for details.
210 ichwd_tmr_disable(struct ichwd_softc *sc)
214 cnt = ichwd_read_tco_2(sc, TCO1_CNT) & TCO_CNT_PRESERVE;
215 ichwd_write_tco_2(sc, TCO1_CNT, cnt | TCO_TMR_HALT);
217 ichwd_verbose_printf(sc->device, "timer disabled\n");
221 * Reload the watchdog timer: writing anything to any of the lower five
222 * bits of the TCO_RLD register reloads the timer from the last value
223 * written to TCO_TMR.
226 ichwd_tmr_reload(struct ichwd_softc *sc)
228 if (sc->ich_version <= 5)
229 ichwd_write_tco_1(sc, TCO_RLD, 1);
231 ichwd_write_tco_2(sc, TCO_RLD, 1);
233 ichwd_verbose_printf(sc->device, "timer reloaded\n");
237 * Set the initial timeout value. Note that this must always be followed
241 ichwd_tmr_set(struct ichwd_softc *sc, unsigned int timeout)
245 * If the datasheets are to be believed, the minimum value
246 * actually varies from chipset to chipset - 4 for ICH5 and 2 for
247 * all other chipsets. I suspect this is a bug in the ICH5
248 * datasheet and that the minimum is uniformly 2, but I'd rather
249 * err on the side of caution.
254 if (sc->ich_version <= 5) {
255 uint8_t tmr_val8 = ichwd_read_tco_1(sc, TCO_TMR1);
261 ichwd_write_tco_1(sc, TCO_TMR1, tmr_val8);
263 uint16_t tmr_val16 = ichwd_read_tco_2(sc, TCO_TMR2);
266 if (timeout > 0x03ff)
268 tmr_val16 |= timeout;
269 ichwd_write_tco_2(sc, TCO_TMR2, tmr_val16);
272 sc->timeout = timeout;
274 ichwd_verbose_printf(sc->device, "timeout set to %u ticks\n", timeout);
278 ichwd_clear_noreboot(struct ichwd_softc *sc)
283 /* try to clear the NO_REBOOT bit */
284 if (sc->ich_version <= 5) {
285 status = pci_read_config(sc->ich, ICH_GEN_STA, 1);
286 status &= ~ICH_GEN_STA_NO_REBOOT;
287 pci_write_config(sc->ich, ICH_GEN_STA, status, 1);
288 status = pci_read_config(sc->ich, ICH_GEN_STA, 1);
289 if (status & ICH_GEN_STA_NO_REBOOT)
292 status = ichwd_read_gcs_4(sc, 0);
293 status &= ~ICH_GCS_NO_REBOOT;
294 ichwd_write_gcs_4(sc, 0, status);
295 status = ichwd_read_gcs_4(sc, 0);
296 if (status & ICH_GCS_NO_REBOOT)
301 device_printf(sc->device,
302 "ICH WDT present but disabled in BIOS or hardware\n");
308 * Watchdog event handler - called by the framework to enable or disable
309 * the watchdog or change the initial timeout value.
312 ichwd_event(void *arg, unsigned int cmd, int *error)
314 struct ichwd_softc *sc = arg;
315 unsigned int timeout;
317 /* convert from power-of-two-ns to WDT ticks */
319 timeout = ((uint64_t)1 << cmd) / ICHWD_TICK;
321 if (timeout != sc->timeout) {
323 ichwd_tmr_enable(sc);
324 ichwd_tmr_set(sc, timeout);
326 ichwd_tmr_reload(sc);
330 ichwd_tmr_disable(sc);
335 ichwd_find_ich_lpc_bridge(struct ichwd_device **id_p)
337 struct ichwd_device *id;
340 /* look for an ICH LPC interface bridge */
341 for (id = ichwd_devices; id->desc != NULL; ++id)
342 if ((ich = pci_find_device(VENDORID_INTEL, id->device)) != NULL)
348 ichwd_verbose_printf(ich, "found ICH%d or equivalent chipset: %s\n",
349 id->version, id->desc);
358 * Look for an ICH LPC interface bridge. If one is found, register an
359 * ichwd device. There can be only one.
362 ichwd_identify(driver_t *driver, device_t parent)
364 struct ichwd_device *id_p;
370 ich = ichwd_find_ich_lpc_bridge(&id_p);
374 /* good, add child to bus */
375 if ((dev = device_find_child(parent, driver->name, 0)) == NULL)
376 dev = BUS_ADD_CHILD(parent, 0, driver->name, 0);
381 device_set_desc_copy(dev, id_p->desc);
383 if (id_p->version >= 6) {
384 /* get RCBA (root complex base address) */
385 rcba = pci_read_config(ich, ICH_RCBA, 4);
386 rc = bus_set_resource(ich, SYS_RES_MEMORY, 0,
387 (rcba & 0xffffc000) + ICH_GCS_OFFSET, ICH_GCS_SIZE);
389 ichwd_verbose_printf(dev,
390 "Can not set memory resource for RCBA\n");
395 ichwd_probe(device_t dev)
398 /* Do not claim some ISA PnP device by accident. */
399 if (isa_get_logicalid(dev) != 0)
405 ichwd_attach(device_t dev)
407 struct ichwd_softc *sc;
408 struct ichwd_device *id_p;
410 unsigned int pmbase = 0;
412 sc = device_get_softc(dev);
415 ich = ichwd_find_ich_lpc_bridge(&id_p);
417 device_printf(sc->device, "Can not find ICH device.\n");
421 sc->ich_version = id_p->version;
423 /* get ACPI base address */
424 pmbase = pci_read_config(ich, ICH_PMBASE, 2) & ICH_PMBASE_MASK;
426 device_printf(dev, "ICH PMBASE register is empty\n");
430 /* allocate I/O register space */
432 sc->smi_res = bus_alloc_resource(dev, SYS_RES_IOPORT, &sc->smi_rid,
433 pmbase + SMI_BASE, pmbase + SMI_BASE + SMI_LEN - 1, SMI_LEN,
434 RF_ACTIVE | RF_SHAREABLE);
435 if (sc->smi_res == NULL) {
436 device_printf(dev, "unable to reserve SMI registers\n");
439 sc->smi_bst = rman_get_bustag(sc->smi_res);
440 sc->smi_bsh = rman_get_bushandle(sc->smi_res);
443 sc->tco_res = bus_alloc_resource(dev, SYS_RES_IOPORT, &sc->tco_rid,
444 pmbase + TCO_BASE, pmbase + TCO_BASE + TCO_LEN - 1, TCO_LEN,
445 RF_ACTIVE | RF_SHAREABLE);
446 if (sc->tco_res == NULL) {
447 device_printf(dev, "unable to reserve TCO registers\n");
450 sc->tco_bst = rman_get_bustag(sc->tco_res);
451 sc->tco_bsh = rman_get_bushandle(sc->tco_res);
454 if (sc->ich_version >= 6) {
455 sc->gcs_res = bus_alloc_resource_any(ich, SYS_RES_MEMORY,
456 &sc->gcs_rid, RF_ACTIVE|RF_SHAREABLE);
457 if (sc->gcs_res == NULL) {
458 device_printf(dev, "unable to reserve GCS registers\n");
461 sc->gcs_bst = rman_get_bustag(sc->gcs_res);
462 sc->gcs_bsh = rman_get_bushandle(sc->gcs_res);
469 if (ichwd_clear_noreboot(sc) != 0)
472 device_printf(dev, "%s (ICH%d or equivalent)\n",
473 device_get_desc(dev), sc->ich_version);
476 * XXX we should check the status registers (specifically, the
477 * TCO_SECOND_TO_STS bit in the TCO2_STS register) to see if we
478 * just came back from a watchdog-induced reset, and let the user
482 /* reset the watchdog status registers */
485 /* make sure the WDT starts out inactive */
486 ichwd_tmr_disable(sc);
488 /* register the watchdog event handler */
489 sc->ev_tag = EVENTHANDLER_REGISTER(watchdog_list, ichwd_event, sc, 0);
491 /* disable the SMI handler */
492 ichwd_smi_disable(sc);
496 sc = device_get_softc(dev);
497 if (sc->tco_res != NULL)
498 bus_release_resource(dev, SYS_RES_IOPORT,
499 sc->tco_rid, sc->tco_res);
500 if (sc->smi_res != NULL)
501 bus_release_resource(dev, SYS_RES_IOPORT,
502 sc->smi_rid, sc->smi_res);
503 if (sc->gcs_res != NULL)
504 bus_release_resource(ich, SYS_RES_MEMORY,
505 sc->gcs_rid, sc->gcs_res);
511 ichwd_detach(device_t dev)
513 struct ichwd_softc *sc;
516 sc = device_get_softc(dev);
518 /* halt the watchdog timer */
520 ichwd_tmr_disable(sc);
522 /* enable the SMI handler */
523 ichwd_smi_enable(sc);
525 /* deregister event handler */
526 if (sc->ev_tag != NULL)
527 EVENTHANDLER_DEREGISTER(watchdog_list, sc->ev_tag);
530 /* reset the watchdog status registers */
533 /* deallocate I/O register space */
534 bus_release_resource(dev, SYS_RES_IOPORT, sc->tco_rid, sc->tco_res);
535 bus_release_resource(dev, SYS_RES_IOPORT, sc->smi_rid, sc->smi_res);
537 /* deallocate memory resource */
538 ich = ichwd_find_ich_lpc_bridge(NULL);
539 if (sc->gcs_res && ich)
540 bus_release_resource(ich, SYS_RES_MEMORY, sc->gcs_rid, sc->gcs_res);
545 static device_method_t ichwd_methods[] = {
546 DEVMETHOD(device_identify, ichwd_identify),
547 DEVMETHOD(device_probe, ichwd_probe),
548 DEVMETHOD(device_attach, ichwd_attach),
549 DEVMETHOD(device_detach, ichwd_detach),
550 DEVMETHOD(device_shutdown, ichwd_detach),
554 static driver_t ichwd_driver = {
557 sizeof(struct ichwd_softc),
561 ichwd_modevent(module_t mode, int type, void *data)
567 printf("ichwd module loaded\n");
570 printf("ichwd module unloaded\n");
573 printf("ichwd module shutting down\n");
579 DRIVER_MODULE(ichwd, isa, ichwd_driver, ichwd_devclass, ichwd_modevent, NULL);