1 /******************************************************************************
3 Copyright (c) 2001-2010, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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30 POSSIBILITY OF SUCH DAMAGE.
32 ******************************************************************************/
35 #ifndef _IXGBE_TYPE_H_
36 #define _IXGBE_TYPE_H_
38 #include "ixgbe_osdep.h"
42 #define IXGBE_INTEL_VENDOR_ID 0x8086
45 #define IXGBE_DEV_ID_82598 0x10B6
46 #define IXGBE_DEV_ID_82598_BX 0x1508
47 #define IXGBE_DEV_ID_82598AF_DUAL_PORT 0x10C6
48 #define IXGBE_DEV_ID_82598AF_SINGLE_PORT 0x10C7
49 #define IXGBE_DEV_ID_82598AT 0x10C8
50 #define IXGBE_DEV_ID_82598AT2 0x150B
51 #define IXGBE_DEV_ID_82598EB_SFP_LOM 0x10DB
52 #define IXGBE_DEV_ID_82598EB_CX4 0x10DD
53 #define IXGBE_DEV_ID_82598_CX4_DUAL_PORT 0x10EC
54 #define IXGBE_DEV_ID_82598_DA_DUAL_PORT 0x10F1
55 #define IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM 0x10E1
56 #define IXGBE_DEV_ID_82598EB_XF_LR 0x10F4
57 #define IXGBE_DEV_ID_82599_KX4 0x10F7
58 #define IXGBE_DEV_ID_82599_KX4_MEZZ 0x1514
59 #define IXGBE_DEV_ID_82599_COMBO_BACKPLANE 0x10F8
60 #define IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ 0x000C
61 #define IXGBE_DEV_ID_82599_CX4 0x10F9
62 #define IXGBE_DEV_ID_82599_SFP 0x10FB
63 #define IXGBE_DEV_ID_82599_XAUI_LOM 0x10FC
64 #define IXGBE_DEV_ID_82599_T3_LOM 0x151C
66 /* General Registers */
67 #define IXGBE_CTRL 0x00000
68 #define IXGBE_STATUS 0x00008
69 #define IXGBE_CTRL_EXT 0x00018
70 #define IXGBE_ESDP 0x00020
71 #define IXGBE_EODSDP 0x00028
72 #define IXGBE_I2CCTL 0x00028
73 #define IXGBE_LEDCTL 0x00200
74 #define IXGBE_FRTIMER 0x00048
75 #define IXGBE_TCPTIMER 0x0004C
76 #define IXGBE_CORESPARE 0x00600
77 #define IXGBE_EXVET 0x05078
80 #define IXGBE_EEC 0x10010
81 #define IXGBE_EERD 0x10014
82 #define IXGBE_EEWR 0x10018
83 #define IXGBE_FLA 0x1001C
84 #define IXGBE_EEMNGCTL 0x10110
85 #define IXGBE_EEMNGDATA 0x10114
86 #define IXGBE_FLMNGCTL 0x10118
87 #define IXGBE_FLMNGDATA 0x1011C
88 #define IXGBE_FLMNGCNT 0x10120
89 #define IXGBE_FLOP 0x1013C
90 #define IXGBE_GRC 0x10200
92 /* General Receive Control */
93 #define IXGBE_GRC_MNG 0x00000001 /* Manageability Enable */
94 #define IXGBE_GRC_APME 0x00000002 /* APM enabled in EEPROM */
96 #define IXGBE_VPDDIAG0 0x10204
97 #define IXGBE_VPDDIAG1 0x10208
99 /* I2CCTL Bit Masks */
100 #define IXGBE_I2C_CLK_IN 0x00000001
101 #define IXGBE_I2C_CLK_OUT 0x00000002
102 #define IXGBE_I2C_DATA_IN 0x00000004
103 #define IXGBE_I2C_DATA_OUT 0x00000008
105 /* Interrupt Registers */
106 #define IXGBE_EICR 0x00800
107 #define IXGBE_EICS 0x00808
108 #define IXGBE_EIMS 0x00880
109 #define IXGBE_EIMC 0x00888
110 #define IXGBE_EIAC 0x00810
111 #define IXGBE_EIAM 0x00890
112 #define IXGBE_EICS_EX(_i) (0x00A90 + (_i) * 4)
113 #define IXGBE_EIMS_EX(_i) (0x00AA0 + (_i) * 4)
114 #define IXGBE_EIMC_EX(_i) (0x00AB0 + (_i) * 4)
115 #define IXGBE_EIAM_EX(_i) (0x00AD0 + (_i) * 4)
116 /* 82599 EITR is only 12 bits, with the lower 3 always zero */
118 * 82598 EITR is 16 bits but set the limits based on the max
119 * supported by all ixgbe hardware
121 #define IXGBE_MAX_INT_RATE 488281
122 #define IXGBE_MIN_INT_RATE 956
123 #define IXGBE_MAX_EITR 0x00000FF8
124 #define IXGBE_MIN_EITR 8
125 #define IXGBE_EITR(_i) (((_i) <= 23) ? (0x00820 + ((_i) * 4)) : \
126 (0x012300 + (((_i) - 24) * 4)))
127 #define IXGBE_EITR_ITR_INT_MASK 0x00000FF8
128 #define IXGBE_EITR_LLI_MOD 0x00008000
129 #define IXGBE_EITR_CNT_WDIS 0x80000000
130 #define IXGBE_IVAR(_i) (0x00900 + ((_i) * 4)) /* 24 at 0x900-0x960 */
131 #define IXGBE_IVAR_MISC 0x00A00 /* misc MSI-X interrupt causes */
132 #define IXGBE_EITRSEL 0x00894
133 #define IXGBE_MSIXT 0x00000 /* MSI-X Table. 0x0000 - 0x01C */
134 #define IXGBE_MSIXPBA 0x02000 /* MSI-X Pending bit array */
135 #define IXGBE_PBACL(_i) (((_i) == 0) ? (0x11068) : (0x110C0 + ((_i) * 4)))
136 #define IXGBE_GPIE 0x00898
138 /* Flow Control Registers */
139 #define IXGBE_FCADBUL 0x03210
140 #define IXGBE_FCADBUH 0x03214
141 #define IXGBE_FCAMACL 0x04328
142 #define IXGBE_FCAMACH 0x0432C
143 #define IXGBE_FCRTH_82599(_i) (0x03260 + ((_i) * 4)) /* 8 of these (0-7) */
144 #define IXGBE_FCRTL_82599(_i) (0x03220 + ((_i) * 4)) /* 8 of these (0-7) */
145 #define IXGBE_PFCTOP 0x03008
146 #define IXGBE_FCTTV(_i) (0x03200 + ((_i) * 4)) /* 4 of these (0-3) */
147 #define IXGBE_FCRTL(_i) (0x03220 + ((_i) * 8)) /* 8 of these (0-7) */
148 #define IXGBE_FCRTH(_i) (0x03260 + ((_i) * 8)) /* 8 of these (0-7) */
149 #define IXGBE_FCRTV 0x032A0
150 #define IXGBE_FCCFG 0x03D00
151 #define IXGBE_TFCS 0x0CE00
153 /* Receive DMA Registers */
154 #define IXGBE_RDBAL(_i) (((_i) < 64) ? (0x01000 + ((_i) * 0x40)) : \
155 (0x0D000 + ((_i - 64) * 0x40)))
156 #define IXGBE_RDBAH(_i) (((_i) < 64) ? (0x01004 + ((_i) * 0x40)) : \
157 (0x0D004 + ((_i - 64) * 0x40)))
158 #define IXGBE_RDLEN(_i) (((_i) < 64) ? (0x01008 + ((_i) * 0x40)) : \
159 (0x0D008 + ((_i - 64) * 0x40)))
160 #define IXGBE_RDH(_i) (((_i) < 64) ? (0x01010 + ((_i) * 0x40)) : \
161 (0x0D010 + ((_i - 64) * 0x40)))
162 #define IXGBE_RDT(_i) (((_i) < 64) ? (0x01018 + ((_i) * 0x40)) : \
163 (0x0D018 + ((_i - 64) * 0x40)))
164 #define IXGBE_RXDCTL(_i) (((_i) < 64) ? (0x01028 + ((_i) * 0x40)) : \
165 (0x0D028 + ((_i - 64) * 0x40)))
166 #define IXGBE_RSCCTL(_i) (((_i) < 64) ? (0x0102C + ((_i) * 0x40)) : \
167 (0x0D02C + ((_i - 64) * 0x40)))
168 #define IXGBE_RSCDBU 0x03028
169 #define IXGBE_RDDCC 0x02F20
170 #define IXGBE_RXMEMWRAP 0x03190
171 #define IXGBE_STARCTRL 0x03024
173 * Split and Replication Receive Control Registers
174 * 00-15 : 0x02100 + n*4
175 * 16-64 : 0x01014 + n*0x40
176 * 64-127: 0x0D014 + (n-64)*0x40
178 #define IXGBE_SRRCTL(_i) (((_i) <= 15) ? (0x02100 + ((_i) * 4)) : \
179 (((_i) < 64) ? (0x01014 + ((_i) * 0x40)) : \
180 (0x0D014 + ((_i - 64) * 0x40))))
182 * Rx DCA Control Register:
183 * 00-15 : 0x02200 + n*4
184 * 16-64 : 0x0100C + n*0x40
185 * 64-127: 0x0D00C + (n-64)*0x40
187 #define IXGBE_DCA_RXCTRL(_i) (((_i) <= 15) ? (0x02200 + ((_i) * 4)) : \
188 (((_i) < 64) ? (0x0100C + ((_i) * 0x40)) : \
189 (0x0D00C + ((_i - 64) * 0x40))))
190 #define IXGBE_RDRXCTL 0x02F00
191 #define IXGBE_RDRXCTL_RSC_PUSH 0x80
192 #define IXGBE_RXPBSIZE(_i) (0x03C00 + ((_i) * 4))
193 /* 8 of these 0x03C00 - 0x03C1C */
194 #define IXGBE_RXCTRL 0x03000
195 #define IXGBE_DROPEN 0x03D04
196 #define IXGBE_RXPBSIZE_SHIFT 10
198 /* Receive Registers */
199 #define IXGBE_RXCSUM 0x05000
200 #define IXGBE_RFCTL 0x05008
201 #define IXGBE_DRECCCTL 0x02F08
202 #define IXGBE_DRECCCTL_DISABLE 0
204 /* Multicast Table Array - 128 entries */
205 #define IXGBE_MTA(_i) (0x05200 + ((_i) * 4))
206 #define IXGBE_RAL(_i) (((_i) <= 15) ? (0x05400 + ((_i) * 8)) : \
207 (0x0A200 + ((_i) * 8)))
208 #define IXGBE_RAH(_i) (((_i) <= 15) ? (0x05404 + ((_i) * 8)) : \
209 (0x0A204 + ((_i) * 8)))
210 #define IXGBE_MPSAR_LO(_i) (0x0A600 + ((_i) * 8))
211 #define IXGBE_MPSAR_HI(_i) (0x0A604 + ((_i) * 8))
212 /* Packet split receive type */
213 #define IXGBE_PSRTYPE(_i) (((_i) <= 15) ? (0x05480 + ((_i) * 4)) : \
214 (0x0EA00 + ((_i) * 4)))
215 /* array of 4096 1-bit vlan filters */
216 #define IXGBE_VFTA(_i) (0x0A000 + ((_i) * 4))
217 /*array of 4096 4-bit vlan vmdq indices */
218 #define IXGBE_VFTAVIND(_j, _i) (0x0A200 + ((_j) * 0x200) + ((_i) * 4))
219 #define IXGBE_FCTRL 0x05080
220 #define IXGBE_VLNCTRL 0x05088
221 #define IXGBE_MCSTCTRL 0x05090
222 #define IXGBE_MRQC 0x05818
223 #define IXGBE_SAQF(_i) (0x0E000 + ((_i) * 4)) /* Source Address Queue Filter */
224 #define IXGBE_DAQF(_i) (0x0E200 + ((_i) * 4)) /* Dest. Address Queue Filter */
225 #define IXGBE_SDPQF(_i) (0x0E400 + ((_i) * 4)) /* Src Dest. Addr Queue Filter */
226 #define IXGBE_FTQF(_i) (0x0E600 + ((_i) * 4)) /* Five Tuple Queue Filter */
227 #define IXGBE_ETQF(_i) (0x05128 + ((_i) * 4)) /* EType Queue Filter */
228 #define IXGBE_ETQS(_i) (0x0EC00 + ((_i) * 4)) /* EType Queue Select */
229 #define IXGBE_SYNQF 0x0EC30 /* SYN Packet Queue Filter */
230 #define IXGBE_RQTC 0x0EC70
231 #define IXGBE_MTQC 0x08120
232 #define IXGBE_VLVF(_i) (0x0F100 + ((_i) * 4)) /* 64 of these (0-63) */
233 #define IXGBE_VLVFB(_i) (0x0F200 + ((_i) * 4)) /* 128 of these (0-127) */
234 #define IXGBE_VT_CTL 0x051B0
235 #define IXGBE_VFRE(_i) (0x051E0 + ((_i) * 4))
236 #define IXGBE_VFTE(_i) (0x08110 + ((_i) * 4))
237 #define IXGBE_QDE 0x2F04
238 #define IXGBE_VMOLR(_i) (0x0F000 + ((_i) * 4)) /* 64 total */
239 #define IXGBE_UTA(_i) (0x0F400 + ((_i) * 4))
240 #define IXGBE_VMRCTL(_i) (0x0F600 + ((_i) * 4))
241 #define IXGBE_VMRVLAN(_i) (0x0F610 + ((_i) * 4))
242 #define IXGBE_VMRVM(_i) (0x0F630 + ((_i) * 4))
243 #define IXGBE_L34T_IMIR(_i) (0x0E800 + ((_i) * 4)) /*128 of these (0-127)*/
244 #define IXGBE_LLITHRESH 0x0EC90
245 #define IXGBE_IMIR(_i) (0x05A80 + ((_i) * 4)) /* 8 of these (0-7) */
246 #define IXGBE_IMIREXT(_i) (0x05AA0 + ((_i) * 4)) /* 8 of these (0-7) */
247 #define IXGBE_IMIRVP 0x05AC0
248 #define IXGBE_VMD_CTL 0x0581C
249 #define IXGBE_RETA(_i) (0x05C00 + ((_i) * 4)) /* 32 of these (0-31) */
250 #define IXGBE_RSSRK(_i) (0x05C80 + ((_i) * 4)) /* 10 of these (0-9) */
252 /* Flow Director registers */
253 #define IXGBE_FDIRCTRL 0x0EE00
254 #define IXGBE_FDIRHKEY 0x0EE68
255 #define IXGBE_FDIRSKEY 0x0EE6C
256 #define IXGBE_FDIRDIP4M 0x0EE3C
257 #define IXGBE_FDIRSIP4M 0x0EE40
258 #define IXGBE_FDIRTCPM 0x0EE44
259 #define IXGBE_FDIRUDPM 0x0EE48
260 #define IXGBE_FDIRIP6M 0x0EE74
261 #define IXGBE_FDIRM 0x0EE70
263 /* Flow Director Stats registers */
264 #define IXGBE_FDIRFREE 0x0EE38
265 #define IXGBE_FDIRLEN 0x0EE4C
266 #define IXGBE_FDIRUSTAT 0x0EE50
267 #define IXGBE_FDIRFSTAT 0x0EE54
268 #define IXGBE_FDIRMATCH 0x0EE58
269 #define IXGBE_FDIRMISS 0x0EE5C
271 /* Flow Director Programming registers */
272 #define IXGBE_FDIRSIPv6(_i) (0x0EE0C + ((_i) * 4)) /* 3 of these (0-2) */
273 #define IXGBE_FDIRIPSA 0x0EE18
274 #define IXGBE_FDIRIPDA 0x0EE1C
275 #define IXGBE_FDIRPORT 0x0EE20
276 #define IXGBE_FDIRVLAN 0x0EE24
277 #define IXGBE_FDIRHASH 0x0EE28
278 #define IXGBE_FDIRCMD 0x0EE2C
280 /* Transmit DMA registers */
281 #define IXGBE_TDBAL(_i) (0x06000 + ((_i) * 0x40)) /* 32 of these (0-31)*/
282 #define IXGBE_TDBAH(_i) (0x06004 + ((_i) * 0x40))
283 #define IXGBE_TDLEN(_i) (0x06008 + ((_i) * 0x40))
284 #define IXGBE_TDH(_i) (0x06010 + ((_i) * 0x40))
285 #define IXGBE_TDT(_i) (0x06018 + ((_i) * 0x40))
286 #define IXGBE_TXDCTL(_i) (0x06028 + ((_i) * 0x40))
287 #define IXGBE_TDWBAL(_i) (0x06038 + ((_i) * 0x40))
288 #define IXGBE_TDWBAH(_i) (0x0603C + ((_i) * 0x40))
289 #define IXGBE_DTXCTL 0x07E00
291 #define IXGBE_DMATXCTL 0x04A80
292 #define IXGBE_PFDTXGSWC 0x08220
293 #define IXGBE_DTXMXSZRQ 0x08100
294 #define IXGBE_DTXTCPFLGL 0x04A88
295 #define IXGBE_DTXTCPFLGH 0x04A8C
296 #define IXGBE_LBDRPEN 0x0CA00
297 #define IXGBE_TXPBTHRESH(_i) (0x04950 + ((_i) * 4)) /* 8 of these 0 - 7 */
299 #define IXGBE_DMATXCTL_TE 0x1 /* Transmit Enable */
300 #define IXGBE_DMATXCTL_NS 0x2 /* No Snoop LSO hdr buffer */
301 #define IXGBE_DMATXCTL_GDV 0x8 /* Global Double VLAN */
302 #define IXGBE_DMATXCTL_VT_SHIFT 16 /* VLAN EtherType */
304 #define IXGBE_PFDTXGSWC_VT_LBEN 0x1 /* Local L2 VT switch enable */
305 #define IXGBE_DCA_TXCTRL(_i) (0x07200 + ((_i) * 4)) /* 16 of these (0-15) */
306 /* Tx DCA Control register : 128 of these (0-127) */
307 #define IXGBE_DCA_TXCTRL_82599(_i) (0x0600C + ((_i) * 0x40))
308 #define IXGBE_TIPG 0x0CB00
309 #define IXGBE_TXPBSIZE(_i) (0x0CC00 + ((_i) * 4)) /* 8 of these */
310 #define IXGBE_MNGTXMAP 0x0CD10
311 #define IXGBE_TIPG_FIBER_DEFAULT 3
312 #define IXGBE_TXPBSIZE_SHIFT 10
314 /* Wake up registers */
315 #define IXGBE_WUC 0x05800
316 #define IXGBE_WUFC 0x05808
317 #define IXGBE_WUS 0x05810
318 #define IXGBE_IPAV 0x05838
319 #define IXGBE_IP4AT 0x05840 /* IPv4 table 0x5840-0x5858 */
320 #define IXGBE_IP6AT 0x05880 /* IPv6 table 0x5880-0x588F */
322 #define IXGBE_WUPL 0x05900
323 #define IXGBE_WUPM 0x05A00 /* wake up pkt memory 0x5A00-0x5A7C */
324 #define IXGBE_FHFT(_n) (0x09000 + (_n * 0x100)) /* Flex host filter table */
325 #define IXGBE_FHFT_EXT(_n) (0x09800 + (_n * 0x100)) /* Ext Flexible Host
328 #define IXGBE_FLEXIBLE_FILTER_COUNT_MAX 4
329 #define IXGBE_EXT_FLEXIBLE_FILTER_COUNT_MAX 2
331 /* Each Flexible Filter is at most 128 (0x80) bytes in length */
332 #define IXGBE_FLEXIBLE_FILTER_SIZE_MAX 128
333 #define IXGBE_FHFT_LENGTH_OFFSET 0xFC /* Length byte in FHFT */
334 #define IXGBE_FHFT_LENGTH_MASK 0x0FF /* Length in lower byte */
336 /* Definitions for power management and wakeup registers */
337 /* Wake Up Control */
338 #define IXGBE_WUC_PME_EN 0x00000002 /* PME Enable */
339 #define IXGBE_WUC_PME_STATUS 0x00000004 /* PME Status */
340 #define IXGBE_WUC_WKEN 0x00000010 /* Enable PE_WAKE_N pin assertion */
342 /* Wake Up Filter Control */
343 #define IXGBE_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */
344 #define IXGBE_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */
345 #define IXGBE_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */
346 #define IXGBE_WUFC_MC 0x00000008 /* Directed Multicast Wakeup Enable */
347 #define IXGBE_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */
348 #define IXGBE_WUFC_ARP 0x00000020 /* ARP Request Packet Wakeup Enable */
349 #define IXGBE_WUFC_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup Enable */
350 #define IXGBE_WUFC_IPV6 0x00000080 /* Directed IPv6 Packet Wakeup Enable */
351 #define IXGBE_WUFC_MNG 0x00000100 /* Directed Mgmt Packet Wakeup Enable */
353 #define IXGBE_WUFC_IGNORE_TCO 0x00008000 /* Ignore WakeOn TCO packets */
354 #define IXGBE_WUFC_FLX0 0x00010000 /* Flexible Filter 0 Enable */
355 #define IXGBE_WUFC_FLX1 0x00020000 /* Flexible Filter 1 Enable */
356 #define IXGBE_WUFC_FLX2 0x00040000 /* Flexible Filter 2 Enable */
357 #define IXGBE_WUFC_FLX3 0x00080000 /* Flexible Filter 3 Enable */
358 #define IXGBE_WUFC_FLX4 0x00100000 /* Flexible Filter 4 Enable */
359 #define IXGBE_WUFC_FLX5 0x00200000 /* Flexible Filter 5 Enable */
360 #define IXGBE_WUFC_FLX_FILTERS 0x000F0000 /* Mask for 4 flex filters */
361 #define IXGBE_WUFC_EXT_FLX_FILTERS 0x00300000 /* Mask for Ext. flex filters */
362 #define IXGBE_WUFC_ALL_FILTERS 0x003F00FF /* Mask for all wakeup filters */
363 #define IXGBE_WUFC_FLX_OFFSET 16 /* Offset to the Flexible Filters bits */
366 #define IXGBE_WUS_LNKC IXGBE_WUFC_LNKC
367 #define IXGBE_WUS_MAG IXGBE_WUFC_MAG
368 #define IXGBE_WUS_EX IXGBE_WUFC_EX
369 #define IXGBE_WUS_MC IXGBE_WUFC_MC
370 #define IXGBE_WUS_BC IXGBE_WUFC_BC
371 #define IXGBE_WUS_ARP IXGBE_WUFC_ARP
372 #define IXGBE_WUS_IPV4 IXGBE_WUFC_IPV4
373 #define IXGBE_WUS_IPV6 IXGBE_WUFC_IPV6
374 #define IXGBE_WUS_MNG IXGBE_WUFC_MNG
375 #define IXGBE_WUS_FLX0 IXGBE_WUFC_FLX0
376 #define IXGBE_WUS_FLX1 IXGBE_WUFC_FLX1
377 #define IXGBE_WUS_FLX2 IXGBE_WUFC_FLX2
378 #define IXGBE_WUS_FLX3 IXGBE_WUFC_FLX3
379 #define IXGBE_WUS_FLX4 IXGBE_WUFC_FLX4
380 #define IXGBE_WUS_FLX5 IXGBE_WUFC_FLX5
381 #define IXGBE_WUS_FLX_FILTERS IXGBE_WUFC_FLX_FILTERS
383 /* Wake Up Packet Length */
384 #define IXGBE_WUPL_LENGTH_MASK 0xFFFF
387 #define IXGBE_RMCS 0x03D00
388 #define IXGBE_DPMCS 0x07F40
389 #define IXGBE_PDPMCS 0x0CD00
390 #define IXGBE_RUPPBMR 0x050A0
391 #define IXGBE_RT2CR(_i) (0x03C20 + ((_i) * 4)) /* 8 of these (0-7) */
392 #define IXGBE_RT2SR(_i) (0x03C40 + ((_i) * 4)) /* 8 of these (0-7) */
393 #define IXGBE_TDTQ2TCCR(_i) (0x0602C + ((_i) * 0x40)) /* 8 of these (0-7) */
394 #define IXGBE_TDTQ2TCSR(_i) (0x0622C + ((_i) * 0x40)) /* 8 of these (0-7) */
395 #define IXGBE_TDPT2TCCR(_i) (0x0CD20 + ((_i) * 4)) /* 8 of these (0-7) */
396 #define IXGBE_TDPT2TCSR(_i) (0x0CD40 + ((_i) * 4)) /* 8 of these (0-7) */
399 /* Security Control Registers */
400 #define IXGBE_SECTXCTRL 0x08800
401 #define IXGBE_SECTXSTAT 0x08804
402 #define IXGBE_SECTXBUFFAF 0x08808
403 #define IXGBE_SECTXMINIFG 0x08810
404 #define IXGBE_SECTXSTAT 0x08804
405 #define IXGBE_SECRXCTRL 0x08D00
406 #define IXGBE_SECRXSTAT 0x08D04
408 /* Security Bit Fields and Masks */
409 #define IXGBE_SECTXCTRL_SECTX_DIS 0x00000001
410 #define IXGBE_SECTXCTRL_TX_DIS 0x00000002
411 #define IXGBE_SECTXCTRL_STORE_FORWARD 0x00000004
413 #define IXGBE_SECTXSTAT_SECTX_RDY 0x00000001
414 #define IXGBE_SECTXSTAT_ECC_TXERR 0x00000002
416 #define IXGBE_SECRXCTRL_SECRX_DIS 0x00000001
417 #define IXGBE_SECRXCTRL_RX_DIS 0x00000002
419 #define IXGBE_SECRXSTAT_SECRX_RDY 0x00000001
420 #define IXGBE_SECRXSTAT_ECC_RXERR 0x00000002
422 /* LinkSec (MacSec) Registers */
423 #define IXGBE_LSECTXCAP 0x08A00
424 #define IXGBE_LSECRXCAP 0x08F00
425 #define IXGBE_LSECTXCTRL 0x08A04
426 #define IXGBE_LSECTXSCL 0x08A08 /* SCI Low */
427 #define IXGBE_LSECTXSCH 0x08A0C /* SCI High */
428 #define IXGBE_LSECTXSA 0x08A10
429 #define IXGBE_LSECTXPN0 0x08A14
430 #define IXGBE_LSECTXPN1 0x08A18
431 #define IXGBE_LSECTXKEY0(_n) (0x08A1C + (4 * (_n))) /* 4 of these (0-3) */
432 #define IXGBE_LSECTXKEY1(_n) (0x08A2C + (4 * (_n))) /* 4 of these (0-3) */
433 #define IXGBE_LSECRXCTRL 0x08F04
434 #define IXGBE_LSECRXSCL 0x08F08
435 #define IXGBE_LSECRXSCH 0x08F0C
436 #define IXGBE_LSECRXSA(_i) (0x08F10 + (4 * (_i))) /* 2 of these (0-1) */
437 #define IXGBE_LSECRXPN(_i) (0x08F18 + (4 * (_i))) /* 2 of these (0-1) */
438 #define IXGBE_LSECRXKEY(_n, _m) (0x08F20 + ((0x10 * (_n)) + (4 * (_m))))
439 #define IXGBE_LSECTXUT 0x08A3C /* OutPktsUntagged */
440 #define IXGBE_LSECTXPKTE 0x08A40 /* OutPktsEncrypted */
441 #define IXGBE_LSECTXPKTP 0x08A44 /* OutPktsProtected */
442 #define IXGBE_LSECTXOCTE 0x08A48 /* OutOctetsEncrypted */
443 #define IXGBE_LSECTXOCTP 0x08A4C /* OutOctetsProtected */
444 #define IXGBE_LSECRXUT 0x08F40 /* InPktsUntagged/InPktsNoTag */
445 #define IXGBE_LSECRXOCTD 0x08F44 /* InOctetsDecrypted */
446 #define IXGBE_LSECRXOCTV 0x08F48 /* InOctetsValidated */
447 #define IXGBE_LSECRXBAD 0x08F4C /* InPktsBadTag */
448 #define IXGBE_LSECRXNOSCI 0x08F50 /* InPktsNoSci */
449 #define IXGBE_LSECRXUNSCI 0x08F54 /* InPktsUnknownSci */
450 #define IXGBE_LSECRXUNCH 0x08F58 /* InPktsUnchecked */
451 #define IXGBE_LSECRXDELAY 0x08F5C /* InPktsDelayed */
452 #define IXGBE_LSECRXLATE 0x08F60 /* InPktsLate */
453 #define IXGBE_LSECRXOK(_n) (0x08F64 + (0x04 * (_n))) /* InPktsOk */
454 #define IXGBE_LSECRXINV(_n) (0x08F6C + (0x04 * (_n))) /* InPktsInvalid */
455 #define IXGBE_LSECRXNV(_n) (0x08F74 + (0x04 * (_n))) /* InPktsNotValid */
456 #define IXGBE_LSECRXUNSA 0x08F7C /* InPktsUnusedSa */
457 #define IXGBE_LSECRXNUSA 0x08F80 /* InPktsNotUsingSa */
459 /* LinkSec (MacSec) Bit Fields and Masks */
460 #define IXGBE_LSECTXCAP_SUM_MASK 0x00FF0000
461 #define IXGBE_LSECTXCAP_SUM_SHIFT 16
462 #define IXGBE_LSECRXCAP_SUM_MASK 0x00FF0000
463 #define IXGBE_LSECRXCAP_SUM_SHIFT 16
465 #define IXGBE_LSECTXCTRL_EN_MASK 0x00000003
466 #define IXGBE_LSECTXCTRL_DISABLE 0x0
467 #define IXGBE_LSECTXCTRL_AUTH 0x1
468 #define IXGBE_LSECTXCTRL_AUTH_ENCRYPT 0x2
469 #define IXGBE_LSECTXCTRL_AISCI 0x00000020
470 #define IXGBE_LSECTXCTRL_PNTHRSH_MASK 0xFFFFFF00
471 #define IXGBE_LSECTXCTRL_RSV_MASK 0x000000D8
473 #define IXGBE_LSECRXCTRL_EN_MASK 0x0000000C
474 #define IXGBE_LSECRXCTRL_EN_SHIFT 2
475 #define IXGBE_LSECRXCTRL_DISABLE 0x0
476 #define IXGBE_LSECRXCTRL_CHECK 0x1
477 #define IXGBE_LSECRXCTRL_STRICT 0x2
478 #define IXGBE_LSECRXCTRL_DROP 0x3
479 #define IXGBE_LSECRXCTRL_PLSH 0x00000040
480 #define IXGBE_LSECRXCTRL_RP 0x00000080
481 #define IXGBE_LSECRXCTRL_RSV_MASK 0xFFFFFF33
483 /* IpSec Registers */
484 #define IXGBE_IPSTXIDX 0x08900
485 #define IXGBE_IPSTXSALT 0x08904
486 #define IXGBE_IPSTXKEY(_i) (0x08908 + (4 * (_i))) /* 4 of these (0-3) */
487 #define IXGBE_IPSRXIDX 0x08E00
488 #define IXGBE_IPSRXIPADDR(_i) (0x08E04 + (4 * (_i))) /* 4 of these (0-3) */
489 #define IXGBE_IPSRXSPI 0x08E14
490 #define IXGBE_IPSRXIPIDX 0x08E18
491 #define IXGBE_IPSRXKEY(_i) (0x08E1C + (4 * (_i))) /* 4 of these (0-3) */
492 #define IXGBE_IPSRXSALT 0x08E2C
493 #define IXGBE_IPSRXMOD 0x08E30
495 #define IXGBE_SECTXCTRL_STORE_FORWARD_ENABLE 0x4
498 #define IXGBE_RTRPCS 0x02430
499 #define IXGBE_RTTDCS 0x04900
500 #define IXGBE_RTTDCS_ARBDIS 0x00000040 /* DCB arbiter disable */
501 #define IXGBE_RTTPCS 0x0CD00
502 #define IXGBE_RTRUP2TC 0x03020
503 #define IXGBE_RTTUP2TC 0x0C800
504 #define IXGBE_RTRPT4C(_i) (0x02140 + ((_i) * 4)) /* 8 of these (0-7) */
505 #define IXGBE_RTRPT4S(_i) (0x02160 + ((_i) * 4)) /* 8 of these (0-7) */
506 #define IXGBE_RTTDT2C(_i) (0x04910 + ((_i) * 4)) /* 8 of these (0-7) */
507 #define IXGBE_RTTDT2S(_i) (0x04930 + ((_i) * 4)) /* 8 of these (0-7) */
508 #define IXGBE_RTTPT2C(_i) (0x0CD20 + ((_i) * 4)) /* 8 of these (0-7) */
509 #define IXGBE_RTTPT2S(_i) (0x0CD40 + ((_i) * 4)) /* 8 of these (0-7) */
510 #define IXGBE_RTTDQSEL 0x04904
511 #define IXGBE_RTTDT1C 0x04908
512 #define IXGBE_RTTDT1S 0x0490C
513 #define IXGBE_RTTDTECC 0x04990
514 #define IXGBE_RTTDTECC_NO_BCN 0x00000100
516 #define IXGBE_RTTBCNRC 0x04984
518 /* BCN (for DCB) Registers */
519 #define IXGBE_RTTBCNRM 0x04980
520 #define IXGBE_RTTBCNRS 0x04988
521 #define IXGBE_RTTBCNCR 0x08B00
522 #define IXGBE_RTTBCNACH 0x08B04
523 #define IXGBE_RTTBCNACL 0x08B08
524 #define IXGBE_RTTBCNTG 0x04A90
525 #define IXGBE_RTTBCNIDX 0x08B0C
526 #define IXGBE_RTTBCNCP 0x08B10
527 #define IXGBE_RTFRTIMER 0x08B14
528 #define IXGBE_RTTBCNRTT 0x05150
529 #define IXGBE_RTTBCNRD 0x0498C
531 /* FCoE DMA Context Registers */
532 #define IXGBE_FCPTRL 0x02410 /* FC User Desc. PTR Low */
533 #define IXGBE_FCPTRH 0x02414 /* FC USer Desc. PTR High */
534 #define IXGBE_FCBUFF 0x02418 /* FC Buffer Control */
535 #define IXGBE_FCDMARW 0x02420 /* FC Receive DMA RW */
536 #define IXGBE_FCINVST0 0x03FC0 /* FC Invalid DMA Context Status Reg 0 */
537 #define IXGBE_FCINVST(_i) (IXGBE_FCINVST0 + ((_i) * 4))
538 #define IXGBE_FCBUFF_VALID (1 << 0) /* DMA Context Valid */
539 #define IXGBE_FCBUFF_BUFFSIZE (3 << 3) /* User Buffer Size */
540 #define IXGBE_FCBUFF_WRCONTX (1 << 7) /* 0: Initiator, 1: Target */
541 #define IXGBE_FCBUFF_BUFFCNT 0x0000ff00 /* Number of User Buffers */
542 #define IXGBE_FCBUFF_OFFSET 0xffff0000 /* User Buffer Offset */
543 #define IXGBE_FCBUFF_BUFFSIZE_SHIFT 3
544 #define IXGBE_FCBUFF_BUFFCNT_SHIFT 8
545 #define IXGBE_FCBUFF_OFFSET_SHIFT 16
546 #define IXGBE_FCDMARW_WE (1 << 14) /* Write enable */
547 #define IXGBE_FCDMARW_RE (1 << 15) /* Read enable */
548 #define IXGBE_FCDMARW_FCOESEL 0x000001ff /* FC X_ID: 11 bits */
549 #define IXGBE_FCDMARW_LASTSIZE 0xffff0000 /* Last User Buffer Size */
550 #define IXGBE_FCDMARW_LASTSIZE_SHIFT 16
552 #define IXGBE_TEOFF 0x04A94 /* Tx FC EOF */
553 #define IXGBE_TSOFF 0x04A98 /* Tx FC SOF */
554 #define IXGBE_REOFF 0x05158 /* Rx FC EOF */
555 #define IXGBE_RSOFF 0x051F8 /* Rx FC SOF */
556 /* FCoE Filter Context Registers */
557 #define IXGBE_FCFLT 0x05108 /* FC FLT Context */
558 #define IXGBE_FCFLTRW 0x05110 /* FC Filter RW Control */
559 #define IXGBE_FCPARAM 0x051d8 /* FC Offset Parameter */
560 #define IXGBE_FCFLT_VALID (1 << 0) /* Filter Context Valid */
561 #define IXGBE_FCFLT_FIRST (1 << 1) /* Filter First */
562 #define IXGBE_FCFLT_SEQID 0x00ff0000 /* Sequence ID */
563 #define IXGBE_FCFLT_SEQCNT 0xff000000 /* Sequence Count */
564 #define IXGBE_FCFLTRW_RVALDT (1 << 13) /* Fast Re-Validation */
565 #define IXGBE_FCFLTRW_WE (1 << 14) /* Write Enable */
566 #define IXGBE_FCFLTRW_RE (1 << 15) /* Read Enable */
567 /* FCoE Receive Control */
568 #define IXGBE_FCRXCTRL 0x05100 /* FC Receive Control */
569 #define IXGBE_FCRXCTRL_FCOELLI (1 << 0) /* Low latency interrupt */
570 #define IXGBE_FCRXCTRL_SAVBAD (1 << 1) /* Save Bad Frames */
571 #define IXGBE_FCRXCTRL_FRSTRDH (1 << 2) /* EN 1st Read Header */
572 #define IXGBE_FCRXCTRL_LASTSEQH (1 << 3) /* EN Last Header in Seq */
573 #define IXGBE_FCRXCTRL_ALLH (1 << 4) /* EN All Headers */
574 #define IXGBE_FCRXCTRL_FRSTSEQH (1 << 5) /* EN 1st Seq. Header */
575 #define IXGBE_FCRXCTRL_ICRC (1 << 6) /* Ignore Bad FC CRC */
576 #define IXGBE_FCRXCTRL_FCCRCBO (1 << 7) /* FC CRC Byte Ordering */
577 #define IXGBE_FCRXCTRL_FCOEVER 0x00000f00 /* FCoE Version: 4 bits */
578 #define IXGBE_FCRXCTRL_FCOEVER_SHIFT 8
579 /* FCoE Redirection */
580 #define IXGBE_FCRECTL 0x0ED00 /* FC Redirection Control */
581 #define IXGBE_FCRETA0 0x0ED10 /* FC Redirection Table 0 */
582 #define IXGBE_FCRETA(_i) (IXGBE_FCRETA0 + ((_i) * 4)) /* FCoE Redir */
583 #define IXGBE_FCRECTL_ENA 0x1 /* FCoE Redir Table Enable */
584 #define IXGBE_FCRETA_SIZE 8 /* Max entries in FCRETA */
585 #define IXGBE_FCRETA_ENTRY_MASK 0x0000007f /* 7 bits for the queue index */
587 /* Stats registers */
588 #define IXGBE_CRCERRS 0x04000
589 #define IXGBE_ILLERRC 0x04004
590 #define IXGBE_ERRBC 0x04008
591 #define IXGBE_MSPDC 0x04010
592 #define IXGBE_MPC(_i) (0x03FA0 + ((_i) * 4)) /* 8 of these 3FA0-3FBC*/
593 #define IXGBE_MLFC 0x04034
594 #define IXGBE_MRFC 0x04038
595 #define IXGBE_RLEC 0x04040
596 #define IXGBE_LXONTXC 0x03F60
597 #define IXGBE_LXONRXC 0x0CF60
598 #define IXGBE_LXOFFTXC 0x03F68
599 #define IXGBE_LXOFFRXC 0x0CF68
600 #define IXGBE_LXONRXCNT 0x041A4
601 #define IXGBE_LXOFFRXCNT 0x041A8
602 #define IXGBE_PXONRXCNT(_i) (0x04140 + ((_i) * 4)) /* 8 of these */
603 #define IXGBE_PXOFFRXCNT(_i) (0x04160 + ((_i) * 4)) /* 8 of these */
604 #define IXGBE_PXON2OFFCNT(_i) (0x03240 + ((_i) * 4)) /* 8 of these */
605 #define IXGBE_PXONTXC(_i) (0x03F00 + ((_i) * 4)) /* 8 of these 3F00-3F1C*/
606 #define IXGBE_PXONRXC(_i) (0x0CF00 + ((_i) * 4)) /* 8 of these CF00-CF1C*/
607 #define IXGBE_PXOFFTXC(_i) (0x03F20 + ((_i) * 4)) /* 8 of these 3F20-3F3C*/
608 #define IXGBE_PXOFFRXC(_i) (0x0CF20 + ((_i) * 4)) /* 8 of these CF20-CF3C*/
609 #define IXGBE_PRC64 0x0405C
610 #define IXGBE_PRC127 0x04060
611 #define IXGBE_PRC255 0x04064
612 #define IXGBE_PRC511 0x04068
613 #define IXGBE_PRC1023 0x0406C
614 #define IXGBE_PRC1522 0x04070
615 #define IXGBE_GPRC 0x04074
616 #define IXGBE_BPRC 0x04078
617 #define IXGBE_MPRC 0x0407C
618 #define IXGBE_GPTC 0x04080
619 #define IXGBE_GORCL 0x04088
620 #define IXGBE_GORCH 0x0408C
621 #define IXGBE_GOTCL 0x04090
622 #define IXGBE_GOTCH 0x04094
623 #define IXGBE_RNBC(_i) (0x03FC0 + ((_i) * 4)) /* 8 of these 3FC0-3FDC*/
624 #define IXGBE_RUC 0x040A4
625 #define IXGBE_RFC 0x040A8
626 #define IXGBE_ROC 0x040AC
627 #define IXGBE_RJC 0x040B0
628 #define IXGBE_MNGPRC 0x040B4
629 #define IXGBE_MNGPDC 0x040B8
630 #define IXGBE_MNGPTC 0x0CF90
631 #define IXGBE_TORL 0x040C0
632 #define IXGBE_TORH 0x040C4
633 #define IXGBE_TPR 0x040D0
634 #define IXGBE_TPT 0x040D4
635 #define IXGBE_PTC64 0x040D8
636 #define IXGBE_PTC127 0x040DC
637 #define IXGBE_PTC255 0x040E0
638 #define IXGBE_PTC511 0x040E4
639 #define IXGBE_PTC1023 0x040E8
640 #define IXGBE_PTC1522 0x040EC
641 #define IXGBE_MPTC 0x040F0
642 #define IXGBE_BPTC 0x040F4
643 #define IXGBE_XEC 0x04120
644 #define IXGBE_SSVPC 0x08780
646 #define IXGBE_RQSMR(_i) (0x02300 + ((_i) * 4))
647 #define IXGBE_TQSMR(_i) (((_i) <= 7) ? (0x07300 + ((_i) * 4)) : \
648 (0x08600 + ((_i) * 4)))
649 #define IXGBE_TQSM(_i) (0x08600 + ((_i) * 4))
651 #define IXGBE_QPRC(_i) (0x01030 + ((_i) * 0x40)) /* 16 of these */
652 #define IXGBE_QPTC(_i) (0x06030 + ((_i) * 0x40)) /* 16 of these */
653 #define IXGBE_QBRC(_i) (0x01034 + ((_i) * 0x40)) /* 16 of these */
654 #define IXGBE_QBTC(_i) (0x06034 + ((_i) * 0x40)) /* 16 of these */
655 #define IXGBE_QPRDC(_i) (0x01430 + ((_i) * 0x40)) /* 16 of these */
656 #define IXGBE_QBTC_L(_i) (0x08700 + ((_i) * 0x8)) /* 16 of these */
657 #define IXGBE_QBTC_H(_i) (0x08704 + ((_i) * 0x8)) /* 16 of these */
658 #define IXGBE_FCCRC 0x05118 /* Count of Good Eth CRC w/ Bad FC CRC */
659 #define IXGBE_FCOERPDC 0x0241C /* FCoE Rx Packets Dropped Count */
660 #define IXGBE_FCLAST 0x02424 /* FCoE Last Error Count */
661 #define IXGBE_FCOEPRC 0x02428 /* Number of FCoE Packets Received */
662 #define IXGBE_FCOEDWRC 0x0242C /* Number of FCoE DWords Received */
663 #define IXGBE_FCOEPTC 0x08784 /* Number of FCoE Packets Transmitted */
664 #define IXGBE_FCOEDWTC 0x08788 /* Number of FCoE DWords Transmitted */
665 #define IXGBE_FCCRC_CNT_MASK 0x0000FFFF /* CRC_CNT: bit 0 - 15 */
666 #define IXGBE_FCLAST_CNT_MASK 0x0000FFFF /* Last_CNT: bit 0 - 15 */
669 #define IXGBE_MAVTV(_i) (0x05010 + ((_i) * 4)) /* 8 of these (0-7) */
670 #define IXGBE_MFUTP(_i) (0x05030 + ((_i) * 4)) /* 8 of these (0-7) */
671 #define IXGBE_MANC 0x05820
672 #define IXGBE_MFVAL 0x05824
673 #define IXGBE_MANC2H 0x05860
674 #define IXGBE_MDEF(_i) (0x05890 + ((_i) * 4)) /* 8 of these (0-7) */
675 #define IXGBE_MIPAF 0x058B0
676 #define IXGBE_MMAL(_i) (0x05910 + ((_i) * 8)) /* 4 of these (0-3) */
677 #define IXGBE_MMAH(_i) (0x05914 + ((_i) * 8)) /* 4 of these (0-3) */
678 #define IXGBE_FTFT 0x09400 /* 0x9400-0x97FC */
679 #define IXGBE_METF(_i) (0x05190 + ((_i) * 4)) /* 4 of these (0-3) */
680 #define IXGBE_MDEF_EXT(_i) (0x05160 + ((_i) * 4)) /* 8 of these (0-7) */
681 #define IXGBE_LSWFW 0x15014
683 /* ARC Subsystem registers */
684 #define IXGBE_HICR 0x15F00
685 #define IXGBE_FWSTS 0x15F0C
686 #define IXGBE_HSMC0R 0x15F04
687 #define IXGBE_HSMC1R 0x15F08
688 #define IXGBE_SWSR 0x15F10
689 #define IXGBE_HFDR 0x15FE8
690 #define IXGBE_FLEX_MNG 0x15800 /* 0x15800 - 0x15EFC */
692 /* PCI-E registers */
693 #define IXGBE_GCR 0x11000
694 #define IXGBE_GTV 0x11004
695 #define IXGBE_FUNCTAG 0x11008
696 #define IXGBE_GLT 0x1100C
697 #define IXGBE_GSCL_1 0x11010
698 #define IXGBE_GSCL_2 0x11014
699 #define IXGBE_GSCL_3 0x11018
700 #define IXGBE_GSCL_4 0x1101C
701 #define IXGBE_GSCN_0 0x11020
702 #define IXGBE_GSCN_1 0x11024
703 #define IXGBE_GSCN_2 0x11028
704 #define IXGBE_GSCN_3 0x1102C
705 #define IXGBE_FACTPS 0x10150
706 #define IXGBE_PCIEANACTL 0x11040
707 #define IXGBE_SWSM 0x10140
708 #define IXGBE_FWSM 0x10148
709 #define IXGBE_GSSR 0x10160
710 #define IXGBE_MREVID 0x11064
711 #define IXGBE_DCA_ID 0x11070
712 #define IXGBE_DCA_CTRL 0x11074
713 #define IXGBE_SWFW_SYNC IXGBE_GSSR
715 /* PCI-E registers 82599-Specific */
716 #define IXGBE_GCR_EXT 0x11050
717 #define IXGBE_GSCL_5_82599 0x11030
718 #define IXGBE_GSCL_6_82599 0x11034
719 #define IXGBE_GSCL_7_82599 0x11038
720 #define IXGBE_GSCL_8_82599 0x1103C
721 #define IXGBE_PHYADR_82599 0x11040
722 #define IXGBE_PHYDAT_82599 0x11044
723 #define IXGBE_PHYCTL_82599 0x11048
724 #define IXGBE_PBACLR_82599 0x11068
725 #define IXGBE_CIAA_82599 0x11088
726 #define IXGBE_CIAD_82599 0x1108C
727 #define IXGBE_INTRPT_CSR_82599 0x110B0
728 #define IXGBE_INTRPT_MASK_82599 0x110B8
729 #define IXGBE_CDQ_MBR_82599 0x110B4
730 #define IXGBE_MISC_REG_82599 0x110F0
731 #define IXGBE_ECC_CTRL_0_82599 0x11100
732 #define IXGBE_ECC_CTRL_1_82599 0x11104
733 #define IXGBE_ECC_STATUS_82599 0x110E0
734 #define IXGBE_BAR_CTRL_82599 0x110F4
736 /* PCI Express Control */
737 #define IXGBE_GCR_CMPL_TMOUT_MASK 0x0000F000
738 #define IXGBE_GCR_CMPL_TMOUT_10ms 0x00001000
739 #define IXGBE_GCR_CMPL_TMOUT_RESEND 0x00010000
740 #define IXGBE_GCR_CAP_VER2 0x00040000
742 #define IXGBE_GCR_EXT_MSIX_EN 0x80000000
743 #define IXGBE_GCR_EXT_VT_MODE_16 0x00000001
744 #define IXGBE_GCR_EXT_VT_MODE_32 0x00000002
745 #define IXGBE_GCR_EXT_VT_MODE_64 0x00000003
746 #define IXGBE_GCR_EXT_SRIOV (IXGBE_GCR_EXT_MSIX_EN | \
747 IXGBE_GCR_EXT_VT_MODE_64)
748 /* Time Sync Registers */
749 #define IXGBE_TSYNCRXCTL 0x05188 /* Rx Time Sync Control register - RW */
750 #define IXGBE_TSYNCTXCTL 0x08C00 /* Tx Time Sync Control register - RW */
751 #define IXGBE_RXSTMPL 0x051E8 /* Rx timestamp Low - RO */
752 #define IXGBE_RXSTMPH 0x051A4 /* Rx timestamp High - RO */
753 #define IXGBE_RXSATRL 0x051A0 /* Rx timestamp attribute low - RO */
754 #define IXGBE_RXSATRH 0x051A8 /* Rx timestamp attribute high - RO */
755 #define IXGBE_RXMTRL 0x05120 /* RX message type register low - RW */
756 #define IXGBE_TXSTMPL 0x08C04 /* Tx timestamp value Low - RO */
757 #define IXGBE_TXSTMPH 0x08C08 /* Tx timestamp value High - RO */
758 #define IXGBE_SYSTIML 0x08C0C /* System time register Low - RO */
759 #define IXGBE_SYSTIMH 0x08C10 /* System time register High - RO */
760 #define IXGBE_TIMINCA 0x08C14 /* Increment attributes register - RW */
761 #define IXGBE_RXUDP 0x08C1C /* Time Sync Rx UDP Port - RW */
763 /* Diagnostic Registers */
764 #define IXGBE_RDSTATCTL 0x02C20
765 #define IXGBE_RDSTAT(_i) (0x02C00 + ((_i) * 4)) /* 0x02C00-0x02C1C */
766 #define IXGBE_RDHMPN 0x02F08
767 #define IXGBE_RIC_DW(_i) (0x02F10 + ((_i) * 4))
768 #define IXGBE_RDPROBE 0x02F20
769 #define IXGBE_RDMAM 0x02F30
770 #define IXGBE_RDMAD 0x02F34
771 #define IXGBE_TDSTATCTL 0x07C20
772 #define IXGBE_TDSTAT(_i) (0x07C00 + ((_i) * 4)) /* 0x07C00 - 0x07C1C */
773 #define IXGBE_TDHMPN 0x07F08
774 #define IXGBE_TDHMPN2 0x082FC
775 #define IXGBE_TXDESCIC 0x082CC
776 #define IXGBE_TIC_DW(_i) (0x07F10 + ((_i) * 4))
777 #define IXGBE_TIC_DW2(_i) (0x082B0 + ((_i) * 4))
778 #define IXGBE_TDPROBE 0x07F20
779 #define IXGBE_TXBUFCTRL 0x0C600
780 #define IXGBE_TXBUFDATA0 0x0C610
781 #define IXGBE_TXBUFDATA1 0x0C614
782 #define IXGBE_TXBUFDATA2 0x0C618
783 #define IXGBE_TXBUFDATA3 0x0C61C
784 #define IXGBE_RXBUFCTRL 0x03600
785 #define IXGBE_RXBUFDATA0 0x03610
786 #define IXGBE_RXBUFDATA1 0x03614
787 #define IXGBE_RXBUFDATA2 0x03618
788 #define IXGBE_RXBUFDATA3 0x0361C
789 #define IXGBE_PCIE_DIAG(_i) (0x11090 + ((_i) * 4)) /* 8 of these */
790 #define IXGBE_RFVAL 0x050A4
791 #define IXGBE_MDFTC1 0x042B8
792 #define IXGBE_MDFTC2 0x042C0
793 #define IXGBE_MDFTFIFO1 0x042C4
794 #define IXGBE_MDFTFIFO2 0x042C8
795 #define IXGBE_MDFTS 0x042CC
796 #define IXGBE_RXDATAWRPTR(_i) (0x03700 + ((_i) * 4)) /* 8 of these 3700-370C*/
797 #define IXGBE_RXDESCWRPTR(_i) (0x03710 + ((_i) * 4)) /* 8 of these 3710-371C*/
798 #define IXGBE_RXDATARDPTR(_i) (0x03720 + ((_i) * 4)) /* 8 of these 3720-372C*/
799 #define IXGBE_RXDESCRDPTR(_i) (0x03730 + ((_i) * 4)) /* 8 of these 3730-373C*/
800 #define IXGBE_TXDATAWRPTR(_i) (0x0C700 + ((_i) * 4)) /* 8 of these C700-C70C*/
801 #define IXGBE_TXDESCWRPTR(_i) (0x0C710 + ((_i) * 4)) /* 8 of these C710-C71C*/
802 #define IXGBE_TXDATARDPTR(_i) (0x0C720 + ((_i) * 4)) /* 8 of these C720-C72C*/
803 #define IXGBE_TXDESCRDPTR(_i) (0x0C730 + ((_i) * 4)) /* 8 of these C730-C73C*/
804 #define IXGBE_PCIEECCCTL 0x1106C
805 #define IXGBE_RXWRPTR(_i) (0x03100 + ((_i) * 4)) /* 8 of these 3100-310C*/
806 #define IXGBE_RXUSED(_i) (0x03120 + ((_i) * 4)) /* 8 of these 3120-312C*/
807 #define IXGBE_RXRDPTR(_i) (0x03140 + ((_i) * 4)) /* 8 of these 3140-314C*/
808 #define IXGBE_RXRDWRPTR(_i) (0x03160 + ((_i) * 4)) /* 8 of these 3160-310C*/
809 #define IXGBE_TXWRPTR(_i) (0x0C100 + ((_i) * 4)) /* 8 of these C100-C10C*/
810 #define IXGBE_TXUSED(_i) (0x0C120 + ((_i) * 4)) /* 8 of these C120-C12C*/
811 #define IXGBE_TXRDPTR(_i) (0x0C140 + ((_i) * 4)) /* 8 of these C140-C14C*/
812 #define IXGBE_TXRDWRPTR(_i) (0x0C160 + ((_i) * 4)) /* 8 of these C160-C10C*/
813 #define IXGBE_PCIEECCCTL0 0x11100
814 #define IXGBE_PCIEECCCTL1 0x11104
815 #define IXGBE_RXDBUECC 0x03F70
816 #define IXGBE_TXDBUECC 0x0CF70
817 #define IXGBE_RXDBUEST 0x03F74
818 #define IXGBE_TXDBUEST 0x0CF74
819 #define IXGBE_PBTXECC 0x0C300
820 #define IXGBE_PBRXECC 0x03300
821 #define IXGBE_GHECCR 0x110B0
824 #define IXGBE_PCS1GCFIG 0x04200
825 #define IXGBE_PCS1GLCTL 0x04208
826 #define IXGBE_PCS1GLSTA 0x0420C
827 #define IXGBE_PCS1GDBG0 0x04210
828 #define IXGBE_PCS1GDBG1 0x04214
829 #define IXGBE_PCS1GANA 0x04218
830 #define IXGBE_PCS1GANLP 0x0421C
831 #define IXGBE_PCS1GANNP 0x04220
832 #define IXGBE_PCS1GANLPNP 0x04224
833 #define IXGBE_HLREG0 0x04240
834 #define IXGBE_HLREG1 0x04244
835 #define IXGBE_PAP 0x04248
836 #define IXGBE_MACA 0x0424C
837 #define IXGBE_APAE 0x04250
838 #define IXGBE_ARD 0x04254
839 #define IXGBE_AIS 0x04258
840 #define IXGBE_MSCA 0x0425C
841 #define IXGBE_MSRWD 0x04260
842 #define IXGBE_MLADD 0x04264
843 #define IXGBE_MHADD 0x04268
844 #define IXGBE_MAXFRS 0x04268
845 #define IXGBE_TREG 0x0426C
846 #define IXGBE_PCSS1 0x04288
847 #define IXGBE_PCSS2 0x0428C
848 #define IXGBE_XPCSS 0x04290
849 #define IXGBE_MFLCN 0x04294
850 #define IXGBE_SERDESC 0x04298
851 #define IXGBE_MACS 0x0429C
852 #define IXGBE_AUTOC 0x042A0
853 #define IXGBE_LINKS 0x042A4
854 #define IXGBE_LINKS2 0x04324
855 #define IXGBE_AUTOC2 0x042A8
856 #define IXGBE_AUTOC3 0x042AC
857 #define IXGBE_ANLP1 0x042B0
858 #define IXGBE_ANLP2 0x042B4
859 #define IXGBE_ATLASCTL 0x04800
860 #define IXGBE_MMNGC 0x042D0
861 #define IXGBE_ANLPNP1 0x042D4
862 #define IXGBE_ANLPNP2 0x042D8
863 #define IXGBE_KRPCSFC 0x042E0
864 #define IXGBE_KRPCSS 0x042E4
865 #define IXGBE_FECS1 0x042E8
866 #define IXGBE_FECS2 0x042EC
867 #define IXGBE_SMADARCTL 0x14F10
868 #define IXGBE_MPVC 0x04318
869 #define IXGBE_SGMIIC 0x04314
871 /* Copper Pond 2 link timeout */
872 #define IXGBE_VALIDATE_LINK_READY_TIMEOUT 50
875 #define IXGBE_CORECTL 0x014F00
877 #define IXGBE_BARCTRL 0x110F4
878 #define IXGBE_BARCTRL_FLSIZE 0x0700
879 #define IXGBE_BARCTRL_FLSIZE_SHIFT 8
880 #define IXGBE_BARCTRL_CSRSIZE 0x2000
882 /* RSCCTL Bit Masks */
883 #define IXGBE_RSCCTL_RSCEN 0x01
884 #define IXGBE_RSCCTL_MAXDESC_1 0x00
885 #define IXGBE_RSCCTL_MAXDESC_4 0x04
886 #define IXGBE_RSCCTL_MAXDESC_8 0x08
887 #define IXGBE_RSCCTL_MAXDESC_16 0x0C
889 /* RSCDBU Bit Masks */
890 #define IXGBE_RSCDBU_RSCSMALDIS_MASK 0x0000007F
891 #define IXGBE_RSCDBU_RSCACKDIS 0x00000080
893 /* RDRXCTL Bit Masks */
894 #define IXGBE_RDRXCTL_RDMTS_1_2 0x00000000 /* Rx Desc Min Threshold Size */
895 #define IXGBE_RDRXCTL_CRCSTRIP 0x00000002 /* CRC Strip */
896 #define IXGBE_RDRXCTL_MVMEN 0x00000020
897 #define IXGBE_RDRXCTL_DMAIDONE 0x00000008 /* DMA init cycle done */
898 #define IXGBE_RDRXCTL_AGGDIS 0x00010000 /* Aggregation disable */
899 #define IXGBE_RDRXCTL_RSCFRSTSIZE 0x003E0000 /* RSC First packet size */
900 #define IXGBE_RDRXCTL_RSCLLIDIS 0x00800000 /* Disable RSC compl on LLI */
901 #define IXGBE_RDRXCTL_RSCACKC 0x02000000 /* must set 1 when RSC enabled */
902 #define IXGBE_RDRXCTL_FCOE_WRFIX 0x04000000 /* must set 1 when RSC enabled */
904 /* RQTC Bit Masks and Shifts */
905 #define IXGBE_RQTC_SHIFT_TC(_i) ((_i) * 4)
906 #define IXGBE_RQTC_TC0_MASK (0x7 << 0)
907 #define IXGBE_RQTC_TC1_MASK (0x7 << 4)
908 #define IXGBE_RQTC_TC2_MASK (0x7 << 8)
909 #define IXGBE_RQTC_TC3_MASK (0x7 << 12)
910 #define IXGBE_RQTC_TC4_MASK (0x7 << 16)
911 #define IXGBE_RQTC_TC5_MASK (0x7 << 20)
912 #define IXGBE_RQTC_TC6_MASK (0x7 << 24)
913 #define IXGBE_RQTC_TC7_MASK (0x7 << 28)
915 /* PSRTYPE.RQPL Bit masks and shift */
916 #define IXGBE_PSRTYPE_RQPL_MASK 0x7
917 #define IXGBE_PSRTYPE_RQPL_SHIFT 29
920 #define IXGBE_CTRL_GIO_DIS 0x00000004 /* Global IO Master Disable bit */
921 #define IXGBE_CTRL_LNK_RST 0x00000008 /* Link Reset. Resets everything. */
922 #define IXGBE_CTRL_RST 0x04000000 /* Reset (SW) */
925 #define IXGBE_FACTPS_LFS 0x40000000 /* LAN Function Select */
927 /* MHADD Bit Masks */
928 #define IXGBE_MHADD_MFS_MASK 0xFFFF0000
929 #define IXGBE_MHADD_MFS_SHIFT 16
931 /* Extended Device Control */
932 #define IXGBE_CTRL_EXT_PFRSTD 0x00004000 /* Physical Function Reset Done */
933 #define IXGBE_CTRL_EXT_NS_DIS 0x00010000 /* No Snoop disable */
934 #define IXGBE_CTRL_EXT_RO_DIS 0x00020000 /* Relaxed Ordering disable */
935 #define IXGBE_CTRL_EXT_DRV_LOAD 0x10000000 /* Driver loaded bit for FW */
937 /* Direct Cache Access (DCA) definitions */
938 #define IXGBE_DCA_CTRL_DCA_ENABLE 0x00000000 /* DCA Enable */
939 #define IXGBE_DCA_CTRL_DCA_DISABLE 0x00000001 /* DCA Disable */
941 #define IXGBE_DCA_CTRL_DCA_MODE_CB1 0x00 /* DCA Mode CB1 */
942 #define IXGBE_DCA_CTRL_DCA_MODE_CB2 0x02 /* DCA Mode CB2 */
944 #define IXGBE_DCA_RXCTRL_CPUID_MASK 0x0000001F /* Rx CPUID Mask */
945 #define IXGBE_DCA_RXCTRL_CPUID_MASK_82599 0xFF000000 /* Rx CPUID Mask */
946 #define IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599 24 /* Rx CPUID Shift */
947 #define IXGBE_DCA_RXCTRL_DESC_DCA_EN (1 << 5) /* DCA Rx Desc enable */
948 #define IXGBE_DCA_RXCTRL_HEAD_DCA_EN (1 << 6) /* DCA Rx Desc header enable */
949 #define IXGBE_DCA_RXCTRL_DATA_DCA_EN (1 << 7) /* DCA Rx Desc payload enable */
950 #define IXGBE_DCA_RXCTRL_DESC_RRO_EN (1 << 9) /* DCA Rx rd Desc Relax Order */
951 #define IXGBE_DCA_RXCTRL_DESC_WRO_EN (1 << 13) /* DCA Rx wr Desc Relax Order */
952 #define IXGBE_DCA_RXCTRL_DESC_HSRO_EN (1 << 15) /* DCA Rx Split Header RO */
954 #define IXGBE_DCA_TXCTRL_CPUID_MASK 0x0000001F /* Tx CPUID Mask */
955 #define IXGBE_DCA_TXCTRL_CPUID_MASK_82599 0xFF000000 /* Tx CPUID Mask */
956 #define IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599 24 /* Tx CPUID Shift */
957 #define IXGBE_DCA_TXCTRL_DESC_DCA_EN (1 << 5) /* DCA Tx Desc enable */
958 #define IXGBE_DCA_TXCTRL_TX_WB_RO_EN (1 << 11) /* Tx Desc writeback RO bit */
959 #define IXGBE_DCA_MAX_QUEUES_82598 16 /* DCA regs only on 16 queues */
962 #define IXGBE_MSCA_NP_ADDR_MASK 0x0000FFFF /* MDI Address (new protocol) */
963 #define IXGBE_MSCA_NP_ADDR_SHIFT 0
964 #define IXGBE_MSCA_DEV_TYPE_MASK 0x001F0000 /* Device Type (new protocol) */
965 #define IXGBE_MSCA_DEV_TYPE_SHIFT 16 /* Register Address (old protocol */
966 #define IXGBE_MSCA_PHY_ADDR_MASK 0x03E00000 /* PHY Address mask */
967 #define IXGBE_MSCA_PHY_ADDR_SHIFT 21 /* PHY Address shift*/
968 #define IXGBE_MSCA_OP_CODE_MASK 0x0C000000 /* OP CODE mask */
969 #define IXGBE_MSCA_OP_CODE_SHIFT 26 /* OP CODE shift */
970 #define IXGBE_MSCA_ADDR_CYCLE 0x00000000 /* OP CODE 00 (addr cycle) */
971 #define IXGBE_MSCA_WRITE 0x04000000 /* OP CODE 01 (write) */
972 #define IXGBE_MSCA_READ 0x08000000 /* OP CODE 10 (read) */
973 #define IXGBE_MSCA_READ_AUTOINC 0x0C000000 /* OP CODE 11 (read, auto inc)*/
974 #define IXGBE_MSCA_ST_CODE_MASK 0x30000000 /* ST Code mask */
975 #define IXGBE_MSCA_ST_CODE_SHIFT 28 /* ST Code shift */
976 #define IXGBE_MSCA_NEW_PROTOCOL 0x00000000 /* ST CODE 00 (new protocol) */
977 #define IXGBE_MSCA_OLD_PROTOCOL 0x10000000 /* ST CODE 01 (old protocol) */
978 #define IXGBE_MSCA_MDI_COMMAND 0x40000000 /* Initiate MDI command */
979 #define IXGBE_MSCA_MDI_IN_PROG_EN 0x80000000 /* MDI in progress enable */
981 /* MSRWD bit masks */
982 #define IXGBE_MSRWD_WRITE_DATA_MASK 0x0000FFFF
983 #define IXGBE_MSRWD_WRITE_DATA_SHIFT 0
984 #define IXGBE_MSRWD_READ_DATA_MASK 0xFFFF0000
985 #define IXGBE_MSRWD_READ_DATA_SHIFT 16
987 /* Atlas registers */
988 #define IXGBE_ATLAS_PDN_LPBK 0x24
989 #define IXGBE_ATLAS_PDN_10G 0xB
990 #define IXGBE_ATLAS_PDN_1G 0xC
991 #define IXGBE_ATLAS_PDN_AN 0xD
993 /* Atlas bit masks */
994 #define IXGBE_ATLASCTL_WRITE_CMD 0x00010000
995 #define IXGBE_ATLAS_PDN_TX_REG_EN 0x10
996 #define IXGBE_ATLAS_PDN_TX_10G_QL_ALL 0xF0
997 #define IXGBE_ATLAS_PDN_TX_1G_QL_ALL 0xF0
998 #define IXGBE_ATLAS_PDN_TX_AN_QL_ALL 0xF0
1000 /* Omer bit masks */
1001 #define IXGBE_CORECTL_WRITE_CMD 0x00010000
1003 /* Device Type definitions for new protocol MDIO commands */
1004 #define IXGBE_MDIO_PMA_PMD_DEV_TYPE 0x1
1005 #define IXGBE_MDIO_PCS_DEV_TYPE 0x3
1006 #define IXGBE_MDIO_PHY_XS_DEV_TYPE 0x4
1007 #define IXGBE_MDIO_AUTO_NEG_DEV_TYPE 0x7
1008 #define IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE 0x1E /* Device 30 */
1009 #define IXGBE_TWINAX_DEV 1
1011 #define IXGBE_MDIO_COMMAND_TIMEOUT 100 /* PHY Timeout for 1 GB mode */
1013 #define IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL 0x0 /* VS1 Control Reg */
1014 #define IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS 0x1 /* VS1 Status Reg */
1015 #define IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS 0x0008 /* 1 = Link Up */
1016 #define IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS 0x0010 /* 0 - 10G, 1 - 1G */
1017 #define IXGBE_MDIO_VENDOR_SPECIFIC_1_10G_SPEED 0x0018
1018 #define IXGBE_MDIO_VENDOR_SPECIFIC_1_1G_SPEED 0x0010
1020 #define IXGBE_MDIO_AUTO_NEG_CONTROL 0x0 /* AUTO_NEG Control Reg */
1021 #define IXGBE_MDIO_AUTO_NEG_STATUS 0x1 /* AUTO_NEG Status Reg */
1022 #define IXGBE_MDIO_PHY_XS_CONTROL 0x0 /* PHY_XS Control Reg */
1023 #define IXGBE_MDIO_PHY_XS_RESET 0x8000 /* PHY_XS Reset */
1024 #define IXGBE_MDIO_PHY_ID_HIGH 0x2 /* PHY ID High Reg*/
1025 #define IXGBE_MDIO_PHY_ID_LOW 0x3 /* PHY ID Low Reg*/
1026 #define IXGBE_MDIO_PHY_SPEED_ABILITY 0x4 /* Speed Ability Reg */
1027 #define IXGBE_MDIO_PHY_SPEED_10G 0x0001 /* 10G capable */
1028 #define IXGBE_MDIO_PHY_SPEED_1G 0x0010 /* 1G capable */
1029 #define IXGBE_MDIO_PHY_SPEED_100M 0x0020 /* 100M capable */
1030 #define IXGBE_MDIO_PHY_EXT_ABILITY 0xB /* Ext Ability Reg */
1031 #define IXGBE_MDIO_PHY_10GBASET_ABILITY 0x0004 /* 10GBaseT capable */
1032 #define IXGBE_MDIO_PHY_1000BASET_ABILITY 0x0020 /* 1000BaseT capable */
1033 #define IXGBE_MDIO_PHY_100BASETX_ABILITY 0x0080 /* 100BaseTX capable */
1034 #define IXGBE_MDIO_PHY_SET_LOW_POWER_MODE 0x0800 /* Set low power mode */
1036 #define IXGBE_MDIO_PMA_PMD_CONTROL_ADDR 0x0000 /* PMA/PMD Control Reg */
1037 #define IXGBE_MDIO_PMA_PMD_SDA_SCL_ADDR 0xC30A /* PHY_XS SDA/SCL Addr Reg */
1038 #define IXGBE_MDIO_PMA_PMD_SDA_SCL_DATA 0xC30B /* PHY_XS SDA/SCL Data Reg */
1039 #define IXGBE_MDIO_PMA_PMD_SDA_SCL_STAT 0xC30C /* PHY_XS SDA/SCL Status Reg */
1041 /* MII clause 22/28 definitions */
1042 #define IXGBE_MDIO_PHY_LOW_POWER_MODE 0x0800
1044 #define IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG 0x20 /* 10G Control Reg */
1045 #define IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG 0xC400 /* 1G Provisioning 1 */
1046 #define IXGBE_MII_AUTONEG_XNP_TX_REG 0x17 /* 1G XNP Transmit */
1047 #define IXGBE_MII_AUTONEG_ADVERTISE_REG 0x10 /* 100M Advertisement */
1048 #define IXGBE_MII_10GBASE_T_ADVERTISE 0x1000 /* full duplex, bit:12*/
1049 #define IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX 0x4000 /* full duplex, bit:14*/
1050 #define IXGBE_MII_1GBASE_T_ADVERTISE 0x8000 /* full duplex, bit:15*/
1051 #define IXGBE_MII_100BASE_T_ADVERTISE 0x0100 /* full duplex, bit:8 */
1052 #define IXGBE_MII_RESTART 0x200
1053 #define IXGBE_MII_AUTONEG_COMPLETE 0x20
1054 #define IXGBE_MII_AUTONEG_LINK_UP 0x04
1055 #define IXGBE_MII_AUTONEG_REG 0x0
1057 #define IXGBE_PHY_REVISION_MASK 0xFFFFFFF0
1058 #define IXGBE_MAX_PHY_ADDR 32
1061 #define TN1010_PHY_ID 0x00A19410
1062 #define TNX_FW_REV 0xB
1063 #define AQ1002_PHY_ID 0x03A1B420
1064 #define AQ_FW_REV 0x20
1065 #define QT2022_PHY_ID 0x0043A400
1066 #define ATH_PHY_ID 0x03429050
1069 #define IXGBE_M88E1145_E_PHY_ID 0x01410CD0
1071 /* Special PHY Init Routine */
1072 #define IXGBE_PHY_INIT_OFFSET_NL 0x002B
1073 #define IXGBE_PHY_INIT_END_NL 0xFFFF
1074 #define IXGBE_CONTROL_MASK_NL 0xF000
1075 #define IXGBE_DATA_MASK_NL 0x0FFF
1076 #define IXGBE_CONTROL_SHIFT_NL 12
1077 #define IXGBE_DELAY_NL 0
1078 #define IXGBE_DATA_NL 1
1079 #define IXGBE_CONTROL_NL 0x000F
1080 #define IXGBE_CONTROL_EOL_NL 0x0FFF
1081 #define IXGBE_CONTROL_SOL_NL 0x0000
1083 /* General purpose Interrupt Enable */
1084 #define IXGBE_SDP0_GPIEN 0x00000001 /* SDP0 */
1085 #define IXGBE_SDP1_GPIEN 0x00000002 /* SDP1 */
1086 #define IXGBE_SDP2_GPIEN 0x00000004 /* SDP2 */
1087 #define IXGBE_GPIE_MSIX_MODE 0x00000010 /* MSI-X mode */
1088 #define IXGBE_GPIE_OCD 0x00000020 /* Other Clear Disable */
1089 #define IXGBE_GPIE_EIMEN 0x00000040 /* Immediate Interrupt Enable */
1090 #define IXGBE_GPIE_EIAME 0x40000000
1091 #define IXGBE_GPIE_PBA_SUPPORT 0x80000000
1092 #define IXGBE_GPIE_RSC_DELAY_SHIFT 11
1093 #define IXGBE_GPIE_VTMODE_MASK 0x0000C000 /* VT Mode Mask */
1094 #define IXGBE_GPIE_VTMODE_16 0x00004000 /* 16 VFs 8 queues per VF */
1095 #define IXGBE_GPIE_VTMODE_32 0x00008000 /* 32 VFs 4 queues per VF */
1096 #define IXGBE_GPIE_VTMODE_64 0x0000C000 /* 64 VFs 2 queues per VF */
1098 /* Transmit Flow Control status */
1099 #define IXGBE_TFCS_TXOFF 0x00000001
1100 #define IXGBE_TFCS_TXOFF0 0x00000100
1101 #define IXGBE_TFCS_TXOFF1 0x00000200
1102 #define IXGBE_TFCS_TXOFF2 0x00000400
1103 #define IXGBE_TFCS_TXOFF3 0x00000800
1104 #define IXGBE_TFCS_TXOFF4 0x00001000
1105 #define IXGBE_TFCS_TXOFF5 0x00002000
1106 #define IXGBE_TFCS_TXOFF6 0x00004000
1107 #define IXGBE_TFCS_TXOFF7 0x00008000
1110 #define IXGBE_TCPTIMER_KS 0x00000100
1111 #define IXGBE_TCPTIMER_COUNT_ENABLE 0x00000200
1112 #define IXGBE_TCPTIMER_COUNT_FINISH 0x00000400
1113 #define IXGBE_TCPTIMER_LOOP 0x00000800
1114 #define IXGBE_TCPTIMER_DURATION_MASK 0x000000FF
1116 /* HLREG0 Bit Masks */
1117 #define IXGBE_HLREG0_TXCRCEN 0x00000001 /* bit 0 */
1118 #define IXGBE_HLREG0_RXCRCSTRP 0x00000002 /* bit 1 */
1119 #define IXGBE_HLREG0_JUMBOEN 0x00000004 /* bit 2 */
1120 #define IXGBE_HLREG0_TXPADEN 0x00000400 /* bit 10 */
1121 #define IXGBE_HLREG0_TXPAUSEEN 0x00001000 /* bit 12 */
1122 #define IXGBE_HLREG0_RXPAUSEEN 0x00004000 /* bit 14 */
1123 #define IXGBE_HLREG0_LPBK 0x00008000 /* bit 15 */
1124 #define IXGBE_HLREG0_MDCSPD 0x00010000 /* bit 16 */
1125 #define IXGBE_HLREG0_CONTMDC 0x00020000 /* bit 17 */
1126 #define IXGBE_HLREG0_CTRLFLTR 0x00040000 /* bit 18 */
1127 #define IXGBE_HLREG0_PREPEND 0x00F00000 /* bits 20-23 */
1128 #define IXGBE_HLREG0_PRIPAUSEEN 0x01000000 /* bit 24 */
1129 #define IXGBE_HLREG0_RXPAUSERECDA 0x06000000 /* bits 25-26 */
1130 #define IXGBE_HLREG0_RXLNGTHERREN 0x08000000 /* bit 27 */
1131 #define IXGBE_HLREG0_RXPADSTRIPEN 0x10000000 /* bit 28 */
1133 /* VMD_CTL bitmasks */
1134 #define IXGBE_VMD_CTL_VMDQ_EN 0x00000001
1135 #define IXGBE_VMD_CTL_VMDQ_FILTER 0x00000002
1137 /* VT_CTL bitmasks */
1138 #define IXGBE_VT_CTL_DIS_DEFPL 0x20000000 /* disable default pool */
1139 #define IXGBE_VT_CTL_REPLEN 0x40000000 /* replication enabled */
1140 #define IXGBE_VT_CTL_VT_ENABLE 0x00000001 /* Enable VT Mode */
1141 #define IXGBE_VT_CTL_POOL_SHIFT 7
1142 #define IXGBE_VT_CTL_POOL_MASK (0x3F << IXGBE_VT_CTL_POOL_SHIFT)
1144 /* VMOLR bitmasks */
1145 #define IXGBE_VMOLR_AUPE 0x01000000 /* accept untagged packets */
1146 #define IXGBE_VMOLR_ROMPE 0x02000000 /* accept packets in MTA tbl */
1147 #define IXGBE_VMOLR_ROPE 0x04000000 /* accept packets in UC tbl */
1148 #define IXGBE_VMOLR_BAM 0x08000000 /* accept broadcast packets */
1149 #define IXGBE_VMOLR_MPE 0x10000000 /* multicast promiscuous */
1152 #define IXGBE_VFRE_ENABLE_ALL 0xFFFFFFFF
1154 #define IXGBE_VF_INIT_TIMEOUT 200 /* Number of retries to clear RSTI */
1156 /* RDHMPN and TDHMPN bitmasks */
1157 #define IXGBE_RDHMPN_RDICADDR 0x007FF800
1158 #define IXGBE_RDHMPN_RDICRDREQ 0x00800000
1159 #define IXGBE_RDHMPN_RDICADDR_SHIFT 11
1160 #define IXGBE_TDHMPN_TDICADDR 0x003FF800
1161 #define IXGBE_TDHMPN_TDICRDREQ 0x00800000
1162 #define IXGBE_TDHMPN_TDICADDR_SHIFT 11
1164 #define IXGBE_RDMAM_MEM_SEL_SHIFT 13
1165 #define IXGBE_RDMAM_DWORD_SHIFT 9
1166 #define IXGBE_RDMAM_DESC_COMP_FIFO 1
1167 #define IXGBE_RDMAM_DFC_CMD_FIFO 2
1168 #define IXGBE_RDMAM_RSC_HEADER_ADDR 3
1169 #define IXGBE_RDMAM_TCN_STATUS_RAM 4
1170 #define IXGBE_RDMAM_WB_COLL_FIFO 5
1171 #define IXGBE_RDMAM_QSC_CNT_RAM 6
1172 #define IXGBE_RDMAM_QSC_FCOE_RAM 7
1173 #define IXGBE_RDMAM_QSC_QUEUE_CNT 8
1174 #define IXGBE_RDMAM_QSC_QUEUE_RAM 0xA
1175 #define IXGBE_RDMAM_QSC_RSC_RAM 0xB
1176 #define IXGBE_RDMAM_DESC_COM_FIFO_RANGE 135
1177 #define IXGBE_RDMAM_DESC_COM_FIFO_COUNT 4
1178 #define IXGBE_RDMAM_DFC_CMD_FIFO_RANGE 48
1179 #define IXGBE_RDMAM_DFC_CMD_FIFO_COUNT 7
1180 #define IXGBE_RDMAM_RSC_HEADER_ADDR_RANGE 32
1181 #define IXGBE_RDMAM_RSC_HEADER_ADDR_COUNT 4
1182 #define IXGBE_RDMAM_TCN_STATUS_RAM_RANGE 256
1183 #define IXGBE_RDMAM_TCN_STATUS_RAM_COUNT 9
1184 #define IXGBE_RDMAM_WB_COLL_FIFO_RANGE 8
1185 #define IXGBE_RDMAM_WB_COLL_FIFO_COUNT 4
1186 #define IXGBE_RDMAM_QSC_CNT_RAM_RANGE 64
1187 #define IXGBE_RDMAM_QSC_CNT_RAM_COUNT 4
1188 #define IXGBE_RDMAM_QSC_FCOE_RAM_RANGE 512
1189 #define IXGBE_RDMAM_QSC_FCOE_RAM_COUNT 5
1190 #define IXGBE_RDMAM_QSC_QUEUE_CNT_RANGE 32
1191 #define IXGBE_RDMAM_QSC_QUEUE_CNT_COUNT 4
1192 #define IXGBE_RDMAM_QSC_QUEUE_RAM_RANGE 128
1193 #define IXGBE_RDMAM_QSC_QUEUE_RAM_COUNT 8
1194 #define IXGBE_RDMAM_QSC_RSC_RAM_RANGE 32
1195 #define IXGBE_RDMAM_QSC_RSC_RAM_COUNT 8
1197 #define IXGBE_TXDESCIC_READY 0x80000000
1199 /* Receive Checksum Control */
1200 #define IXGBE_RXCSUM_IPPCSE 0x00001000 /* IP payload checksum enable */
1201 #define IXGBE_RXCSUM_PCSD 0x00002000 /* packet checksum disabled */
1203 /* FCRTL Bit Masks */
1204 #define IXGBE_FCRTL_XONE 0x80000000 /* XON enable */
1205 #define IXGBE_FCRTH_FCEN 0x80000000 /* Packet buffer fc enable */
1208 #define IXGBE_PAP_TXPAUSECNT_MASK 0x0000FFFF /* Pause counter mask */
1210 /* RMCS Bit Masks */
1211 #define IXGBE_RMCS_RRM 0x00000002 /* Receive Recycle Mode enable */
1212 /* Receive Arbitration Control: 0 Round Robin, 1 DFP */
1213 #define IXGBE_RMCS_RAC 0x00000004
1214 #define IXGBE_RMCS_DFP IXGBE_RMCS_RAC /* Deficit Fixed Priority ena */
1215 #define IXGBE_RMCS_TFCE_802_3X 0x00000008 /* Tx Priority FC ena */
1216 #define IXGBE_RMCS_TFCE_PRIORITY 0x00000010 /* Tx Priority FC ena */
1217 #define IXGBE_RMCS_ARBDIS 0x00000040 /* Arbitration disable bit */
1219 /* FCCFG Bit Masks */
1220 #define IXGBE_FCCFG_TFCE_802_3X 0x00000008 /* Tx link FC enable */
1221 #define IXGBE_FCCFG_TFCE_PRIORITY 0x00000010 /* Tx priority FC enable */
1223 /* Interrupt register bitmasks */
1225 /* Extended Interrupt Cause Read */
1226 #define IXGBE_EICR_RTX_QUEUE 0x0000FFFF /* RTx Queue Interrupt */
1227 #define IXGBE_EICR_FLOW_DIR 0x00010000 /* FDir Exception */
1228 #define IXGBE_EICR_RX_MISS 0x00020000 /* Packet Buffer Overrun */
1229 #define IXGBE_EICR_PCI 0x00040000 /* PCI Exception */
1230 #define IXGBE_EICR_MAILBOX 0x00080000 /* VF to PF Mailbox Interrupt */
1231 #define IXGBE_EICR_LSC 0x00100000 /* Link Status Change */
1232 #define IXGBE_EICR_LINKSEC 0x00200000 /* PN Threshold */
1233 #define IXGBE_EICR_MNG 0x00400000 /* Manageability Event Interrupt */
1234 #define IXGBE_EICR_GPI_SDP0 0x01000000 /* Gen Purpose Interrupt on SDP0 */
1235 #define IXGBE_EICR_GPI_SDP1 0x02000000 /* Gen Purpose Interrupt on SDP1 */
1236 #define IXGBE_EICR_GPI_SDP2 0x04000000 /* Gen Purpose Interrupt on SDP2 */
1237 #define IXGBE_EICR_ECC 0x10000000 /* ECC Error */
1238 #define IXGBE_EICR_PBUR 0x10000000 /* Packet Buffer Handler Error */
1239 #define IXGBE_EICR_DHER 0x20000000 /* Descriptor Handler Error */
1240 #define IXGBE_EICR_TCP_TIMER 0x40000000 /* TCP Timer */
1241 #define IXGBE_EICR_OTHER 0x80000000 /* Interrupt Cause Active */
1243 /* Extended Interrupt Cause Set */
1244 #define IXGBE_EICS_RTX_QUEUE IXGBE_EICR_RTX_QUEUE /* RTx Queue Interrupt */
1245 #define IXGBE_EICS_FLOW_DIR IXGBE_EICR_FLOW_DIR /* FDir Exception */
1246 #define IXGBE_EICS_RX_MISS IXGBE_EICR_RX_MISS /* Pkt Buffer Overrun */
1247 #define IXGBE_EICS_PCI IXGBE_EICR_PCI /* PCI Exception */
1248 #define IXGBE_EICS_MAILBOX IXGBE_EICR_MAILBOX /* VF to PF Mailbox Int */
1249 #define IXGBE_EICS_LSC IXGBE_EICR_LSC /* Link Status Change */
1250 #define IXGBE_EICS_MNG IXGBE_EICR_MNG /* MNG Event Interrupt */
1251 #define IXGBE_EICS_GPI_SDP0 IXGBE_EICR_GPI_SDP0 /* SDP0 Gen Purpose Int */
1252 #define IXGBE_EICS_GPI_SDP1 IXGBE_EICR_GPI_SDP1 /* SDP1 Gen Purpose Int */
1253 #define IXGBE_EICS_GPI_SDP2 IXGBE_EICR_GPI_SDP2 /* SDP2 Gen Purpose Int */
1254 #define IXGBE_EICS_ECC IXGBE_EICR_ECC /* ECC Error */
1255 #define IXGBE_EICS_PBUR IXGBE_EICR_PBUR /* Pkt Buf Handler Err */
1256 #define IXGBE_EICS_DHER IXGBE_EICR_DHER /* Desc Handler Error */
1257 #define IXGBE_EICS_TCP_TIMER IXGBE_EICR_TCP_TIMER /* TCP Timer */
1258 #define IXGBE_EICS_OTHER IXGBE_EICR_OTHER /* INT Cause Active */
1260 /* Extended Interrupt Mask Set */
1261 #define IXGBE_EIMS_RTX_QUEUE IXGBE_EICR_RTX_QUEUE /* RTx Queue Interrupt */
1262 #define IXGBE_EIMS_FLOW_DIR IXGBE_EICR_FLOW_DIR /* FDir Exception */
1263 #define IXGBE_EIMS_RX_MISS IXGBE_EICR_RX_MISS /* Packet Buffer Overrun */
1264 #define IXGBE_EIMS_PCI IXGBE_EICR_PCI /* PCI Exception */
1265 #define IXGBE_EIMS_MAILBOX IXGBE_EICR_MAILBOX /* VF to PF Mailbox Int */
1266 #define IXGBE_EIMS_LSC IXGBE_EICR_LSC /* Link Status Change */
1267 #define IXGBE_EIMS_MNG IXGBE_EICR_MNG /* MNG Event Interrupt */
1268 #define IXGBE_EIMS_GPI_SDP0 IXGBE_EICR_GPI_SDP0 /* SDP0 Gen Purpose Int */
1269 #define IXGBE_EIMS_GPI_SDP1 IXGBE_EICR_GPI_SDP1 /* SDP1 Gen Purpose Int */
1270 #define IXGBE_EIMS_GPI_SDP2 IXGBE_EICR_GPI_SDP2 /* SDP2 Gen Purpose Int */
1271 #define IXGBE_EIMS_ECC IXGBE_EICR_ECC /* ECC Error */
1272 #define IXGBE_EIMS_PBUR IXGBE_EICR_PBUR /* Pkt Buf Handler Err */
1273 #define IXGBE_EIMS_DHER IXGBE_EICR_DHER /* Descr Handler Error */
1274 #define IXGBE_EIMS_TCP_TIMER IXGBE_EICR_TCP_TIMER /* TCP Timer */
1275 #define IXGBE_EIMS_OTHER IXGBE_EICR_OTHER /* INT Cause Active */
1277 /* Extended Interrupt Mask Clear */
1278 #define IXGBE_EIMC_RTX_QUEUE IXGBE_EICR_RTX_QUEUE /* RTx Queue Interrupt */
1279 #define IXGBE_EIMC_FLOW_DIR IXGBE_EICR_FLOW_DIR /* FDir Exception */
1280 #define IXGBE_EIMC_RX_MISS IXGBE_EICR_RX_MISS /* Packet Buffer Overrun */
1281 #define IXGBE_EIMC_PCI IXGBE_EICR_PCI /* PCI Exception */
1282 #define IXGBE_EIMC_MAILBOX IXGBE_EICR_MAILBOX /* VF to PF Mailbox Int */
1283 #define IXGBE_EIMC_LSC IXGBE_EICR_LSC /* Link Status Change */
1284 #define IXGBE_EIMC_MNG IXGBE_EICR_MNG /* MNG Event Interrupt */
1285 #define IXGBE_EIMC_GPI_SDP0 IXGBE_EICR_GPI_SDP0 /* SDP0 Gen Purpose Int */
1286 #define IXGBE_EIMC_GPI_SDP1 IXGBE_EICR_GPI_SDP1 /* SDP1 Gen Purpose Int */
1287 #define IXGBE_EIMC_GPI_SDP2 IXGBE_EICR_GPI_SDP2 /* SDP2 Gen Purpose Int */
1288 #define IXGBE_EIMC_ECC IXGBE_EICR_ECC /* ECC Error */
1289 #define IXGBE_EIMC_PBUR IXGBE_EICR_PBUR /* Pkt Buf Handler Err */
1290 #define IXGBE_EIMC_DHER IXGBE_EICR_DHER /* Desc Handler Err */
1291 #define IXGBE_EIMC_TCP_TIMER IXGBE_EICR_TCP_TIMER /* TCP Timer */
1292 #define IXGBE_EIMC_OTHER IXGBE_EICR_OTHER /* INT Cause Active */
1294 #define IXGBE_EIMS_ENABLE_MASK ( \
1295 IXGBE_EIMS_RTX_QUEUE | \
1297 IXGBE_EIMS_TCP_TIMER | \
1300 /* Immediate Interrupt Rx (A.K.A. Low Latency Interrupt) */
1301 #define IXGBE_IMIR_PORT_IM_EN 0x00010000 /* TCP port enable */
1302 #define IXGBE_IMIR_PORT_BP 0x00020000 /* TCP port check bypass */
1303 #define IXGBE_IMIREXT_SIZE_BP 0x00001000 /* Packet size bypass */
1304 #define IXGBE_IMIREXT_CTRL_URG 0x00002000 /* Check URG bit in header */
1305 #define IXGBE_IMIREXT_CTRL_ACK 0x00004000 /* Check ACK bit in header */
1306 #define IXGBE_IMIREXT_CTRL_PSH 0x00008000 /* Check PSH bit in header */
1307 #define IXGBE_IMIREXT_CTRL_RST 0x00010000 /* Check RST bit in header */
1308 #define IXGBE_IMIREXT_CTRL_SYN 0x00020000 /* Check SYN bit in header */
1309 #define IXGBE_IMIREXT_CTRL_FIN 0x00040000 /* Check FIN bit in header */
1310 #define IXGBE_IMIREXT_CTRL_BP 0x00080000 /* Bypass check of control bits */
1311 #define IXGBE_IMIR_SIZE_BP_82599 0x00001000 /* Packet size bypass */
1312 #define IXGBE_IMIR_CTRL_URG_82599 0x00002000 /* Check URG bit in header */
1313 #define IXGBE_IMIR_CTRL_ACK_82599 0x00004000 /* Check ACK bit in header */
1314 #define IXGBE_IMIR_CTRL_PSH_82599 0x00008000 /* Check PSH bit in header */
1315 #define IXGBE_IMIR_CTRL_RST_82599 0x00010000 /* Check RST bit in header */
1316 #define IXGBE_IMIR_CTRL_SYN_82599 0x00020000 /* Check SYN bit in header */
1317 #define IXGBE_IMIR_CTRL_FIN_82599 0x00040000 /* Check FIN bit in header */
1318 #define IXGBE_IMIR_CTRL_BP_82599 0x00080000 /* Bypass check of control bits */
1319 #define IXGBE_IMIR_LLI_EN_82599 0x00100000 /* Enables low latency Int */
1320 #define IXGBE_IMIR_RX_QUEUE_MASK_82599 0x0000007F /* Rx Queue Mask */
1321 #define IXGBE_IMIR_RX_QUEUE_SHIFT_82599 21 /* Rx Queue Shift */
1322 #define IXGBE_IMIRVP_PRIORITY_MASK 0x00000007 /* VLAN priority mask */
1323 #define IXGBE_IMIRVP_PRIORITY_EN 0x00000008 /* VLAN priority enable */
1325 #define IXGBE_MAX_FTQF_FILTERS 128
1326 #define IXGBE_FTQF_PROTOCOL_MASK 0x00000003
1327 #define IXGBE_FTQF_PROTOCOL_TCP 0x00000000
1328 #define IXGBE_FTQF_PROTOCOL_UDP 0x00000001
1329 #define IXGBE_FTQF_PROTOCOL_SCTP 2
1330 #define IXGBE_FTQF_PRIORITY_MASK 0x00000007
1331 #define IXGBE_FTQF_PRIORITY_SHIFT 2
1332 #define IXGBE_FTQF_POOL_MASK 0x0000003F
1333 #define IXGBE_FTQF_POOL_SHIFT 8
1334 #define IXGBE_FTQF_5TUPLE_MASK_MASK 0x0000001F
1335 #define IXGBE_FTQF_5TUPLE_MASK_SHIFT 25
1336 #define IXGBE_FTQF_SOURCE_ADDR_MASK 0x1E
1337 #define IXGBE_FTQF_DEST_ADDR_MASK 0x1D
1338 #define IXGBE_FTQF_SOURCE_PORT_MASK 0x1B
1339 #define IXGBE_FTQF_DEST_PORT_MASK 0x17
1340 #define IXGBE_FTQF_PROTOCOL_COMP_MASK 0x0F
1341 #define IXGBE_FTQF_POOL_MASK_EN 0x40000000
1342 #define IXGBE_FTQF_QUEUE_ENABLE 0x80000000
1344 /* Interrupt clear mask */
1345 #define IXGBE_IRQ_CLEAR_MASK 0xFFFFFFFF
1347 /* Interrupt Vector Allocation Registers */
1348 #define IXGBE_IVAR_REG_NUM 25
1349 #define IXGBE_IVAR_REG_NUM_82599 64
1350 #define IXGBE_IVAR_TXRX_ENTRY 96
1351 #define IXGBE_IVAR_RX_ENTRY 64
1352 #define IXGBE_IVAR_RX_QUEUE(_i) (0 + (_i))
1353 #define IXGBE_IVAR_TX_QUEUE(_i) (64 + (_i))
1354 #define IXGBE_IVAR_TX_ENTRY 32
1356 #define IXGBE_IVAR_TCP_TIMER_INDEX 96 /* 0 based index */
1357 #define IXGBE_IVAR_OTHER_CAUSES_INDEX 97 /* 0 based index */
1359 #define IXGBE_MSIX_VECTOR(_i) (0 + (_i))
1361 #define IXGBE_IVAR_ALLOC_VAL 0x80 /* Interrupt Allocation valid */
1363 /* ETYPE Queue Filter/Select Bit Masks */
1364 #define IXGBE_MAX_ETQF_FILTERS 8
1365 #define IXGBE_ETQF_FCOE 0x08000000 /* bit 27 */
1366 #define IXGBE_ETQF_BCN 0x10000000 /* bit 28 */
1367 #define IXGBE_ETQF_1588 0x40000000 /* bit 30 */
1368 #define IXGBE_ETQF_FILTER_EN 0x80000000 /* bit 31 */
1369 #define IXGBE_ETQF_POOL_ENABLE (1 << 26) /* bit 26 */
1371 #define IXGBE_ETQS_RX_QUEUE 0x007F0000 /* bits 22:16 */
1372 #define IXGBE_ETQS_RX_QUEUE_SHIFT 16
1373 #define IXGBE_ETQS_LLI 0x20000000 /* bit 29 */
1374 #define IXGBE_ETQS_QUEUE_EN 0x80000000 /* bit 31 */
1377 * ETQF filter list: one static filter per filter consumer. This is
1378 * to avoid filter collisions later. Add new filters
1382 * EAPOL 802.1x (0x888e): Filter 0
1383 * FCoE (0x8906): Filter 2
1384 * 1588 (0x88f7): Filter 3
1385 * FIP (0x8914): Filter 4
1387 #define IXGBE_ETQF_FILTER_EAPOL 0
1388 #define IXGBE_ETQF_FILTER_FCOE 2
1389 #define IXGBE_ETQF_FILTER_1588 3
1390 #define IXGBE_ETQF_FILTER_FIP 4
1391 /* VLAN Control Bit Masks */
1392 #define IXGBE_VLNCTRL_VET 0x0000FFFF /* bits 0-15 */
1393 #define IXGBE_VLNCTRL_CFI 0x10000000 /* bit 28 */
1394 #define IXGBE_VLNCTRL_CFIEN 0x20000000 /* bit 29 */
1395 #define IXGBE_VLNCTRL_VFE 0x40000000 /* bit 30 */
1396 #define IXGBE_VLNCTRL_VME 0x80000000 /* bit 31 */
1398 /* VLAN pool filtering masks */
1399 #define IXGBE_VLVF_VIEN 0x80000000 /* filter is valid */
1400 #define IXGBE_VLVF_ENTRIES 64
1401 #define IXGBE_VLVF_VLANID_MASK 0x00000FFF
1403 #define IXGBE_ETHERNET_IEEE_VLAN_TYPE 0x8100 /* 802.1q protocol */
1405 /* STATUS Bit Masks */
1406 #define IXGBE_STATUS_LAN_ID 0x0000000C /* LAN ID */
1407 #define IXGBE_STATUS_LAN_ID_SHIFT 2 /* LAN ID Shift*/
1408 #define IXGBE_STATUS_GIO 0x00080000 /* GIO Master Enable Status */
1410 #define IXGBE_STATUS_LAN_ID_0 0x00000000 /* LAN ID 0 */
1411 #define IXGBE_STATUS_LAN_ID_1 0x00000004 /* LAN ID 1 */
1413 /* ESDP Bit Masks */
1414 #define IXGBE_ESDP_SDP0 0x00000001 /* SDP0 Data Value */
1415 #define IXGBE_ESDP_SDP1 0x00000002 /* SDP1 Data Value */
1416 #define IXGBE_ESDP_SDP2 0x00000004 /* SDP2 Data Value */
1417 #define IXGBE_ESDP_SDP3 0x00000008 /* SDP3 Data Value */
1418 #define IXGBE_ESDP_SDP4 0x00000010 /* SDP4 Data Value */
1419 #define IXGBE_ESDP_SDP5 0x00000020 /* SDP5 Data Value */
1420 #define IXGBE_ESDP_SDP6 0x00000040 /* SDP6 Data Value */
1421 #define IXGBE_ESDP_SDP4_DIR 0x00000004 /* SDP4 IO direction */
1422 #define IXGBE_ESDP_SDP5_DIR 0x00002000 /* SDP5 IO direction */
1424 /* LEDCTL Bit Masks */
1425 #define IXGBE_LED_IVRT_BASE 0x00000040
1426 #define IXGBE_LED_BLINK_BASE 0x00000080
1427 #define IXGBE_LED_MODE_MASK_BASE 0x0000000F
1428 #define IXGBE_LED_OFFSET(_base, _i) (_base << (8 * (_i)))
1429 #define IXGBE_LED_MODE_SHIFT(_i) (8*(_i))
1430 #define IXGBE_LED_IVRT(_i) IXGBE_LED_OFFSET(IXGBE_LED_IVRT_BASE, _i)
1431 #define IXGBE_LED_BLINK(_i) IXGBE_LED_OFFSET(IXGBE_LED_BLINK_BASE, _i)
1432 #define IXGBE_LED_MODE_MASK(_i) IXGBE_LED_OFFSET(IXGBE_LED_MODE_MASK_BASE, _i)
1435 #define IXGBE_LED_LINK_UP 0x0
1436 #define IXGBE_LED_LINK_10G 0x1
1437 #define IXGBE_LED_MAC 0x2
1438 #define IXGBE_LED_FILTER 0x3
1439 #define IXGBE_LED_LINK_ACTIVE 0x4
1440 #define IXGBE_LED_LINK_1G 0x5
1441 #define IXGBE_LED_ON 0xE
1442 #define IXGBE_LED_OFF 0xF
1444 /* AUTOC Bit Masks */
1445 #define IXGBE_AUTOC_KX4_KX_SUPP_MASK 0xC0000000
1446 #define IXGBE_AUTOC_KX4_SUPP 0x80000000
1447 #define IXGBE_AUTOC_KX_SUPP 0x40000000
1448 #define IXGBE_AUTOC_PAUSE 0x30000000
1449 #define IXGBE_AUTOC_ASM_PAUSE 0x20000000
1450 #define IXGBE_AUTOC_SYM_PAUSE 0x10000000
1451 #define IXGBE_AUTOC_RF 0x08000000
1452 #define IXGBE_AUTOC_PD_TMR 0x06000000
1453 #define IXGBE_AUTOC_AN_RX_LOOSE 0x01000000
1454 #define IXGBE_AUTOC_AN_RX_DRIFT 0x00800000
1455 #define IXGBE_AUTOC_AN_RX_ALIGN 0x007C0000
1456 #define IXGBE_AUTOC_FECA 0x00040000
1457 #define IXGBE_AUTOC_FECR 0x00020000
1458 #define IXGBE_AUTOC_KR_SUPP 0x00010000
1459 #define IXGBE_AUTOC_AN_RESTART 0x00001000
1460 #define IXGBE_AUTOC_FLU 0x00000001
1461 #define IXGBE_AUTOC_LMS_SHIFT 13
1462 #define IXGBE_AUTOC_LMS_10G_SERIAL (0x3 << IXGBE_AUTOC_LMS_SHIFT)
1463 #define IXGBE_AUTOC_LMS_KX4_KX_KR (0x4 << IXGBE_AUTOC_LMS_SHIFT)
1464 #define IXGBE_AUTOC_LMS_SGMII_1G_100M (0x5 << IXGBE_AUTOC_LMS_SHIFT)
1465 #define IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN (0x6 << IXGBE_AUTOC_LMS_SHIFT)
1466 #define IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII (0x7 << IXGBE_AUTOC_LMS_SHIFT)
1467 #define IXGBE_AUTOC_LMS_MASK (0x7 << IXGBE_AUTOC_LMS_SHIFT)
1468 #define IXGBE_AUTOC_LMS_1G_LINK_NO_AN (0x0 << IXGBE_AUTOC_LMS_SHIFT)
1469 #define IXGBE_AUTOC_LMS_10G_LINK_NO_AN (0x1 << IXGBE_AUTOC_LMS_SHIFT)
1470 #define IXGBE_AUTOC_LMS_1G_AN (0x2 << IXGBE_AUTOC_LMS_SHIFT)
1471 #define IXGBE_AUTOC_LMS_KX4_AN (0x4 << IXGBE_AUTOC_LMS_SHIFT)
1472 #define IXGBE_AUTOC_LMS_KX4_AN_1G_AN (0x6 << IXGBE_AUTOC_LMS_SHIFT)
1473 #define IXGBE_AUTOC_LMS_ATTACH_TYPE (0x7 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT)
1475 #define IXGBE_AUTOC_1G_PMA_PMD_MASK 0x00000200
1476 #define IXGBE_AUTOC_1G_PMA_PMD_SHIFT 9
1477 #define IXGBE_AUTOC_10G_PMA_PMD_MASK 0x00000180
1478 #define IXGBE_AUTOC_10G_PMA_PMD_SHIFT 7
1479 #define IXGBE_AUTOC_10G_XAUI (0x0 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT)
1480 #define IXGBE_AUTOC_10G_KX4 (0x1 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT)
1481 #define IXGBE_AUTOC_10G_CX4 (0x2 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT)
1482 #define IXGBE_AUTOC_1G_BX (0x0 << IXGBE_AUTOC_1G_PMA_PMD_SHIFT)
1483 #define IXGBE_AUTOC_1G_KX (0x1 << IXGBE_AUTOC_1G_PMA_PMD_SHIFT)
1484 #define IXGBE_AUTOC_1G_SFI (0x0 << IXGBE_AUTOC_1G_PMA_PMD_SHIFT)
1485 #define IXGBE_AUTOC_1G_KX_BX (0x1 << IXGBE_AUTOC_1G_PMA_PMD_SHIFT)
1487 #define IXGBE_AUTOC2_UPPER_MASK 0xFFFF0000
1488 #define IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK 0x00030000
1489 #define IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT 16
1490 #define IXGBE_AUTOC2_10G_KR (0x0 << IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT)
1491 #define IXGBE_AUTOC2_10G_XFI (0x1 << IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT)
1492 #define IXGBE_AUTOC2_10G_SFI (0x2 << IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT)
1495 /* LINKS Bit Masks */
1496 #define IXGBE_LINKS_KX_AN_COMP 0x80000000
1497 #define IXGBE_LINKS_UP 0x40000000
1498 #define IXGBE_LINKS_SPEED 0x20000000
1499 #define IXGBE_LINKS_MODE 0x18000000
1500 #define IXGBE_LINKS_RX_MODE 0x06000000
1501 #define IXGBE_LINKS_TX_MODE 0x01800000
1502 #define IXGBE_LINKS_XGXS_EN 0x00400000
1503 #define IXGBE_LINKS_SGMII_EN 0x02000000
1504 #define IXGBE_LINKS_PCS_1G_EN 0x00200000
1505 #define IXGBE_LINKS_1G_AN_EN 0x00100000
1506 #define IXGBE_LINKS_KX_AN_IDLE 0x00080000
1507 #define IXGBE_LINKS_1G_SYNC 0x00040000
1508 #define IXGBE_LINKS_10G_ALIGN 0x00020000
1509 #define IXGBE_LINKS_10G_LANE_SYNC 0x00017000
1510 #define IXGBE_LINKS_TL_FAULT 0x00001000
1511 #define IXGBE_LINKS_SIGNAL 0x00000F00
1513 #define IXGBE_LINKS_SPEED_82599 0x30000000
1514 #define IXGBE_LINKS_SPEED_10G_82599 0x30000000
1515 #define IXGBE_LINKS_SPEED_1G_82599 0x20000000
1516 #define IXGBE_LINKS_SPEED_100_82599 0x10000000
1517 #define IXGBE_LINK_UP_TIME 90 /* 9.0 Seconds */
1518 #define IXGBE_AUTO_NEG_TIME 45 /* 4.5 Seconds */
1520 #define IXGBE_LINKS2_AN_SUPPORTED 0x00000040
1522 /* PCS1GLSTA Bit Masks */
1523 #define IXGBE_PCS1GLSTA_LINK_OK 1
1524 #define IXGBE_PCS1GLSTA_SYNK_OK 0x10
1525 #define IXGBE_PCS1GLSTA_AN_COMPLETE 0x10000
1526 #define IXGBE_PCS1GLSTA_AN_PAGE_RX 0x20000
1527 #define IXGBE_PCS1GLSTA_AN_TIMED_OUT 0x40000
1528 #define IXGBE_PCS1GLSTA_AN_REMOTE_FAULT 0x80000
1529 #define IXGBE_PCS1GLSTA_AN_ERROR_RWS 0x100000
1531 #define IXGBE_PCS1GANA_SYM_PAUSE 0x80
1532 #define IXGBE_PCS1GANA_ASM_PAUSE 0x100
1534 /* PCS1GLCTL Bit Masks */
1535 #define IXGBE_PCS1GLCTL_AN_1G_TIMEOUT_EN 0x00040000 /* PCS 1G autoneg to en */
1536 #define IXGBE_PCS1GLCTL_FLV_LINK_UP 1
1537 #define IXGBE_PCS1GLCTL_FORCE_LINK 0x20
1538 #define IXGBE_PCS1GLCTL_LOW_LINK_LATCH 0x40
1539 #define IXGBE_PCS1GLCTL_AN_ENABLE 0x10000
1540 #define IXGBE_PCS1GLCTL_AN_RESTART 0x20000
1542 /* ANLP1 Bit Masks */
1543 #define IXGBE_ANLP1_PAUSE 0x0C00
1544 #define IXGBE_ANLP1_SYM_PAUSE 0x0400
1545 #define IXGBE_ANLP1_ASM_PAUSE 0x0800
1547 /* SW Semaphore Register bitmasks */
1548 #define IXGBE_SWSM_SMBI 0x00000001 /* Driver Semaphore bit */
1549 #define IXGBE_SWSM_SWESMBI 0x00000002 /* FW Semaphore bit */
1550 #define IXGBE_SWSM_WMNG 0x00000004 /* Wake MNG Clock */
1551 #define IXGBE_SWFW_REGSMP 0x80000000 /* Register Semaphore bit 31 */
1553 /* SW_FW_SYNC/GSSR definitions */
1554 #define IXGBE_GSSR_EEP_SM 0x0001
1555 #define IXGBE_GSSR_PHY0_SM 0x0002
1556 #define IXGBE_GSSR_PHY1_SM 0x0004
1557 #define IXGBE_GSSR_MAC_CSR_SM 0x0008
1558 #define IXGBE_GSSR_FLASH_SM 0x0010
1561 #define IXGBE_EEC_SK 0x00000001 /* EEPROM Clock */
1562 #define IXGBE_EEC_CS 0x00000002 /* EEPROM Chip Select */
1563 #define IXGBE_EEC_DI 0x00000004 /* EEPROM Data In */
1564 #define IXGBE_EEC_DO 0x00000008 /* EEPROM Data Out */
1565 #define IXGBE_EEC_FWE_MASK 0x00000030 /* FLASH Write Enable */
1566 #define IXGBE_EEC_FWE_DIS 0x00000010 /* Disable FLASH writes */
1567 #define IXGBE_EEC_FWE_EN 0x00000020 /* Enable FLASH writes */
1568 #define IXGBE_EEC_FWE_SHIFT 4
1569 #define IXGBE_EEC_REQ 0x00000040 /* EEPROM Access Request */
1570 #define IXGBE_EEC_GNT 0x00000080 /* EEPROM Access Grant */
1571 #define IXGBE_EEC_PRES 0x00000100 /* EEPROM Present */
1572 #define IXGBE_EEC_ARD 0x00000200 /* EEPROM Auto Read Done */
1573 #define IXGBE_EEC_FLUP 0x00800000 /* Flash update command */
1574 #define IXGBE_EEC_FLUDONE 0x04000000 /* Flash update done */
1575 /* EEPROM Addressing bits based on type (0-small, 1-large) */
1576 #define IXGBE_EEC_ADDR_SIZE 0x00000400
1577 #define IXGBE_EEC_SIZE 0x00007800 /* EEPROM Size */
1579 #define IXGBE_EEC_SIZE_SHIFT 11
1580 #define IXGBE_EEPROM_WORD_SIZE_BASE_SHIFT 6
1581 #define IXGBE_EEPROM_OPCODE_BITS 8
1583 /* Checksum and EEPROM pointers */
1584 #define IXGBE_EEPROM_CHECKSUM 0x3F
1585 #define IXGBE_EEPROM_SUM 0xBABA
1586 #define IXGBE_PCIE_ANALOG_PTR 0x03
1587 #define IXGBE_ATLAS0_CONFIG_PTR 0x04
1588 #define IXGBE_PHY_PTR 0x04
1589 #define IXGBE_ATLAS1_CONFIG_PTR 0x05
1590 #define IXGBE_OPTION_ROM_PTR 0x05
1591 #define IXGBE_PCIE_GENERAL_PTR 0x06
1592 #define IXGBE_PCIE_CONFIG0_PTR 0x07
1593 #define IXGBE_PCIE_CONFIG1_PTR 0x08
1594 #define IXGBE_CORE0_PTR 0x09
1595 #define IXGBE_CORE1_PTR 0x0A
1596 #define IXGBE_MAC0_PTR 0x0B
1597 #define IXGBE_MAC1_PTR 0x0C
1598 #define IXGBE_CSR0_CONFIG_PTR 0x0D
1599 #define IXGBE_CSR1_CONFIG_PTR 0x0E
1600 #define IXGBE_FW_PTR 0x0F
1601 #define IXGBE_PBANUM0_PTR 0x15
1602 #define IXGBE_PBANUM1_PTR 0x16
1603 #define IXGBE_SAN_MAC_ADDR_PTR 0x28
1604 #define IXGBE_DEVICE_CAPS 0x2C
1605 #define IXGBE_SERIAL_NUMBER_MAC_ADDR 0x11
1606 #define IXGBE_PCIE_MSIX_82599_CAPS 0x72
1607 #define IXGBE_PCIE_MSIX_82598_CAPS 0x62
1609 /* MSI-X capability fields masks */
1610 #define IXGBE_PCIE_MSIX_TBL_SZ_MASK 0x7FF
1612 /* Legacy EEPROM word offsets */
1613 #define IXGBE_ISCSI_BOOT_CAPS 0x0033
1614 #define IXGBE_ISCSI_SETUP_PORT_0 0x0030
1615 #define IXGBE_ISCSI_SETUP_PORT_1 0x0034
1617 /* EEPROM Commands - SPI */
1618 #define IXGBE_EEPROM_MAX_RETRY_SPI 5000 /* Max wait 5ms for RDY signal */
1619 #define IXGBE_EEPROM_STATUS_RDY_SPI 0x01
1620 #define IXGBE_EEPROM_READ_OPCODE_SPI 0x03 /* EEPROM read opcode */
1621 #define IXGBE_EEPROM_WRITE_OPCODE_SPI 0x02 /* EEPROM write opcode */
1622 #define IXGBE_EEPROM_A8_OPCODE_SPI 0x08 /* opcode bit-3 = addr bit-8 */
1623 #define IXGBE_EEPROM_WREN_OPCODE_SPI 0x06 /* EEPROM set Write Ena latch */
1624 /* EEPROM reset Write Enable latch */
1625 #define IXGBE_EEPROM_WRDI_OPCODE_SPI 0x04
1626 #define IXGBE_EEPROM_RDSR_OPCODE_SPI 0x05 /* EEPROM read Status reg */
1627 #define IXGBE_EEPROM_WRSR_OPCODE_SPI 0x01 /* EEPROM write Status reg */
1628 #define IXGBE_EEPROM_ERASE4K_OPCODE_SPI 0x20 /* EEPROM ERASE 4KB */
1629 #define IXGBE_EEPROM_ERASE64K_OPCODE_SPI 0xD8 /* EEPROM ERASE 64KB */
1630 #define IXGBE_EEPROM_ERASE256_OPCODE_SPI 0xDB /* EEPROM ERASE 256B */
1632 /* EEPROM Read Register */
1633 #define IXGBE_EEPROM_RW_REG_DATA 16 /* data offset in EEPROM read reg */
1634 #define IXGBE_EEPROM_RW_REG_DONE 2 /* Offset to READ done bit */
1635 #define IXGBE_EEPROM_RW_REG_START 1 /* First bit to start operation */
1636 #define IXGBE_EEPROM_RW_ADDR_SHIFT 2 /* Shift to the address bits */
1637 #define IXGBE_NVM_POLL_WRITE 1 /* Flag for polling for write complete */
1638 #define IXGBE_NVM_POLL_READ 0 /* Flag for polling for read complete */
1640 #define IXGBE_ETH_LENGTH_OF_ADDRESS 6
1642 #ifndef IXGBE_EEPROM_GRANT_ATTEMPTS
1643 #define IXGBE_EEPROM_GRANT_ATTEMPTS 1000 /* EEPROM # attempts to gain grant */
1646 /* Number of 5 microseconds we wait for EERD read and
1647 * EERW write to complete */
1648 #define IXGBE_EERD_EEWR_ATTEMPTS 100000
1650 /* # attempts we wait for flush update to complete */
1651 #define IXGBE_FLUDONE_ATTEMPTS 20000
1653 #define IXGBE_PCIE_CTRL2 0x5 /* PCIe Control 2 Offset */
1654 #define IXGBE_PCIE_CTRL2_DUMMY_ENABLE 0x8 /* Dummy Function Enable */
1655 #define IXGBE_PCIE_CTRL2_LAN_DISABLE 0x2 /* LAN PCI Disable */
1656 #define IXGBE_PCIE_CTRL2_DISABLE_SELECT 0x1 /* LAN Disable Select */
1658 #define IXGBE_SAN_MAC_ADDR_PORT0_OFFSET 0x0
1659 #define IXGBE_SAN_MAC_ADDR_PORT1_OFFSET 0x3
1660 #define IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP 0x1
1661 #define IXGBE_DEVICE_CAPS_FCOE_OFFLOADS 0x2
1662 #define IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR 0x4
1663 #define IXGBE_FW_PATCH_VERSION_4 0x7
1664 #define IXGBE_ALT_SAN_MAC_ADDR_BLK_PTR 0x27 /* Alt. SAN MAC block */
1665 #define IXGBE_ALT_SAN_MAC_ADDR_CAPS_OFFSET 0x0 /* Alt. SAN MAC capability */
1666 #define IXGBE_ALT_SAN_MAC_ADDR_PORT0_OFFSET 0x1 /* Alt. SAN MAC 0 offset */
1667 #define IXGBE_ALT_SAN_MAC_ADDR_PORT1_OFFSET 0x4 /* Alt. SAN MAC 1 offset */
1668 #define IXGBE_ALT_SAN_MAC_ADDR_WWNN_OFFSET 0x7 /* Alt. WWNN prefix offset */
1669 #define IXGBE_ALT_SAN_MAC_ADDR_WWPN_OFFSET 0x8 /* Alt. WWPN prefix offset */
1670 #define IXGBE_ALT_SAN_MAC_ADDR_CAPS_SANMAC 0x0 /* Alt. SAN MAC exists */
1671 #define IXGBE_ALT_SAN_MAC_ADDR_CAPS_ALTWWN 0x1 /* Alt. WWN base exists */
1674 #define IXGBE_PCI_DEVICE_STATUS 0xAA
1675 #define IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING 0x0020
1676 #define IXGBE_PCI_LINK_STATUS 0xB2
1677 #define IXGBE_PCI_DEVICE_CONTROL2 0xC8
1678 #define IXGBE_PCI_LINK_WIDTH 0x3F0
1679 #define IXGBE_PCI_LINK_WIDTH_1 0x10
1680 #define IXGBE_PCI_LINK_WIDTH_2 0x20
1681 #define IXGBE_PCI_LINK_WIDTH_4 0x40
1682 #define IXGBE_PCI_LINK_WIDTH_8 0x80
1683 #define IXGBE_PCI_LINK_SPEED 0xF
1684 #define IXGBE_PCI_LINK_SPEED_2500 0x1
1685 #define IXGBE_PCI_LINK_SPEED_5000 0x2
1686 #define IXGBE_PCI_HEADER_TYPE_REGISTER 0x0E
1687 #define IXGBE_PCI_HEADER_TYPE_MULTIFUNC 0x80
1688 #define IXGBE_PCI_DEVICE_CONTROL2_16ms 0x0005
1690 /* Number of 100 microseconds we wait for PCI Express master disable */
1691 #define IXGBE_PCI_MASTER_DISABLE_TIMEOUT 800
1693 /* Check whether address is multicast. This is little-endian specific check.*/
1694 #define IXGBE_IS_MULTICAST(Address) \
1695 (bool)(((u8 *)(Address))[0] & ((u8)0x01))
1697 /* Check whether an address is broadcast. */
1698 #define IXGBE_IS_BROADCAST(Address) \
1699 ((((u8 *)(Address))[0] == ((u8)0xff)) && \
1700 (((u8 *)(Address))[1] == ((u8)0xff)))
1703 #define IXGBE_RAH_VIND_MASK 0x003C0000
1704 #define IXGBE_RAH_VIND_SHIFT 18
1705 #define IXGBE_RAH_AV 0x80000000
1706 #define IXGBE_CLEAR_VMDQ_ALL 0xFFFFFFFF
1708 /* Header split receive */
1709 #define IXGBE_RFCTL_ISCSI_DIS 0x00000001
1710 #define IXGBE_RFCTL_ISCSI_DWC_MASK 0x0000003E
1711 #define IXGBE_RFCTL_ISCSI_DWC_SHIFT 1
1712 #define IXGBE_RFCTL_NFSW_DIS 0x00000040
1713 #define IXGBE_RFCTL_NFSR_DIS 0x00000080
1714 #define IXGBE_RFCTL_NFS_VER_MASK 0x00000300
1715 #define IXGBE_RFCTL_NFS_VER_SHIFT 8
1716 #define IXGBE_RFCTL_NFS_VER_2 0
1717 #define IXGBE_RFCTL_NFS_VER_3 1
1718 #define IXGBE_RFCTL_NFS_VER_4 2
1719 #define IXGBE_RFCTL_IPV6_DIS 0x00000400
1720 #define IXGBE_RFCTL_IPV6_XSUM_DIS 0x00000800
1721 #define IXGBE_RFCTL_IPFRSP_DIS 0x00004000
1722 #define IXGBE_RFCTL_IPV6_EX_DIS 0x00010000
1723 #define IXGBE_RFCTL_NEW_IPV6_EXT_DIS 0x00020000
1725 /* Transmit Config masks */
1726 #define IXGBE_TXDCTL_ENABLE 0x02000000 /* Enable specific Tx Queue */
1727 #define IXGBE_TXDCTL_SWFLSH 0x04000000 /* Tx Desc. write-back flushing */
1728 #define IXGBE_TXDCTL_WTHRESH_SHIFT 16 /* shift to WTHRESH bits */
1729 /* Enable short packet padding to 64 bytes */
1730 #define IXGBE_TX_PAD_ENABLE 0x00000400
1731 #define IXGBE_JUMBO_FRAME_ENABLE 0x00000004 /* Allow jumbo frames */
1732 /* This allows for 16K packets + 4k for vlan */
1733 #define IXGBE_MAX_FRAME_SZ 0x40040000
1735 #define IXGBE_TDWBAL_HEAD_WB_ENABLE 0x1 /* Tx head write-back enable */
1736 #define IXGBE_TDWBAL_SEQNUM_WB_ENABLE 0x2 /* Tx seq# write-back enable */
1738 /* Receive Config masks */
1739 #define IXGBE_RXCTRL_RXEN 0x00000001 /* Enable Receiver */
1740 #define IXGBE_RXCTRL_DMBYPS 0x00000002 /* Descriptor Monitor Bypass */
1741 #define IXGBE_RXDCTL_ENABLE 0x02000000 /* Enable specific Rx Queue */
1742 #define IXGBE_RXDCTL_VME 0x40000000 /* VLAN mode enable */
1744 #define IXGBE_FCTRL_SBP 0x00000002 /* Store Bad Packet */
1745 #define IXGBE_FCTRL_MPE 0x00000100 /* Multicast Promiscuous Ena*/
1746 #define IXGBE_FCTRL_UPE 0x00000200 /* Unicast Promiscuous Ena */
1747 #define IXGBE_FCTRL_BAM 0x00000400 /* Broadcast Accept Mode */
1748 #define IXGBE_FCTRL_PMCF 0x00001000 /* Pass MAC Control Frames */
1749 #define IXGBE_FCTRL_DPF 0x00002000 /* Discard Pause Frame */
1750 /* Receive Priority Flow Control Enable */
1751 #define IXGBE_FCTRL_RPFCE 0x00004000
1752 #define IXGBE_FCTRL_RFCE 0x00008000 /* Receive Flow Control Ena */
1753 #define IXGBE_MFLCN_PMCF 0x00000001 /* Pass MAC Control Frames */
1754 #define IXGBE_MFLCN_DPF 0x00000002 /* Discard Pause Frame */
1755 #define IXGBE_MFLCN_RPFCE 0x00000004 /* Receive Priority FC Enable */
1756 #define IXGBE_MFLCN_RFCE 0x00000008 /* Receive FC Enable */
1758 /* Multiple Receive Queue Control */
1759 #define IXGBE_MRQC_RSSEN 0x00000001 /* RSS Enable */
1760 #define IXGBE_MRQC_MRQE_MASK 0xF /* Bits 3:0 */
1761 #define IXGBE_MRQC_RT8TCEN 0x00000002 /* 8 TC no RSS */
1762 #define IXGBE_MRQC_RT4TCEN 0x00000003 /* 4 TC no RSS */
1763 #define IXGBE_MRQC_RTRSS8TCEN 0x00000004 /* 8 TC w/ RSS */
1764 #define IXGBE_MRQC_RTRSS4TCEN 0x00000005 /* 4 TC w/ RSS */
1765 #define IXGBE_MRQC_VMDQEN 0x00000008 /* VMDq2 64 pools no RSS */
1766 #define IXGBE_MRQC_VMDQRSS32EN 0x0000000A /* VMDq2 32 pools w/ RSS */
1767 #define IXGBE_MRQC_VMDQRSS64EN 0x0000000B /* VMDq2 64 pools w/ RSS */
1768 #define IXGBE_MRQC_VMDQRT8TCEN 0x0000000C /* VMDq2/RT 16 pool 8 TC */
1769 #define IXGBE_MRQC_VMDQRT4TCEN 0x0000000D /* VMDq2/RT 32 pool 4 TC */
1770 #define IXGBE_MRQC_RSS_FIELD_MASK 0xFFFF0000
1771 #define IXGBE_MRQC_RSS_FIELD_IPV4_TCP 0x00010000
1772 #define IXGBE_MRQC_RSS_FIELD_IPV4 0x00020000
1773 #define IXGBE_MRQC_RSS_FIELD_IPV6_EX_TCP 0x00040000
1774 #define IXGBE_MRQC_RSS_FIELD_IPV6_EX 0x00080000
1775 #define IXGBE_MRQC_RSS_FIELD_IPV6 0x00100000
1776 #define IXGBE_MRQC_RSS_FIELD_IPV6_TCP 0x00200000
1777 #define IXGBE_MRQC_RSS_FIELD_IPV4_UDP 0x00400000
1778 #define IXGBE_MRQC_RSS_FIELD_IPV6_UDP 0x00800000
1779 #define IXGBE_MRQC_RSS_FIELD_IPV6_EX_UDP 0x01000000
1780 #define IXGBE_MRQC_L3L4TXSWEN 0x00008000
1782 /* Queue Drop Enable */
1783 #define IXGBE_QDE_ENABLE 0x00000001
1784 #define IXGBE_QDE_IDX_MASK 0x00007F00
1785 #define IXGBE_QDE_IDX_SHIFT 8
1787 #define IXGBE_TXD_POPTS_IXSM 0x01 /* Insert IP checksum */
1788 #define IXGBE_TXD_POPTS_TXSM 0x02 /* Insert TCP/UDP checksum */
1789 #define IXGBE_TXD_CMD_EOP 0x01000000 /* End of Packet */
1790 #define IXGBE_TXD_CMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */
1791 #define IXGBE_TXD_CMD_IC 0x04000000 /* Insert Checksum */
1792 #define IXGBE_TXD_CMD_RS 0x08000000 /* Report Status */
1793 #define IXGBE_TXD_CMD_DEXT 0x20000000 /* Descriptor extension (0 = legacy) */
1794 #define IXGBE_TXD_CMD_VLE 0x40000000 /* Add VLAN tag */
1795 #define IXGBE_TXD_STAT_DD 0x00000001 /* Descriptor Done */
1797 #define IXGBE_RXDADV_IPSEC_STATUS_SECP 0x00020000
1798 #define IXGBE_RXDADV_IPSEC_ERROR_INVALID_PROTOCOL 0x08000000
1799 #define IXGBE_RXDADV_IPSEC_ERROR_INVALID_LENGTH 0x10000000
1800 #define IXGBE_RXDADV_IPSEC_ERROR_AUTH_FAILED 0x18000000
1801 #define IXGBE_RXDADV_IPSEC_ERROR_BIT_MASK 0x18000000
1802 /* Multiple Transmit Queue Command Register */
1803 #define IXGBE_MTQC_RT_ENA 0x1 /* DCB Enable */
1804 #define IXGBE_MTQC_VT_ENA 0x2 /* VMDQ2 Enable */
1805 #define IXGBE_MTQC_64Q_1PB 0x0 /* 64 queues 1 pack buffer */
1806 #define IXGBE_MTQC_32VF 0x8 /* 4 TX Queues per pool w/32VF's */
1807 #define IXGBE_MTQC_64VF 0x4 /* 2 TX Queues per pool w/64VF's */
1808 #define IXGBE_MTQC_4TC_4TQ 0x8 /* 4 TC if RT_ENA and VT_ENA */
1809 #define IXGBE_MTQC_8TC_8TQ 0xC /* 8 TC if RT_ENA or 8 TQ if VT_ENA */
1811 /* Receive Descriptor bit definitions */
1812 #define IXGBE_RXD_STAT_DD 0x01 /* Descriptor Done */
1813 #define IXGBE_RXD_STAT_EOP 0x02 /* End of Packet */
1814 #define IXGBE_RXD_STAT_FLM 0x04 /* FDir Match */
1815 #define IXGBE_RXD_STAT_VP 0x08 /* IEEE VLAN Packet */
1816 #define IXGBE_RXDADV_NEXTP_MASK 0x000FFFF0 /* Next Descriptor Index */
1817 #define IXGBE_RXDADV_NEXTP_SHIFT 0x00000004
1818 #define IXGBE_RXD_STAT_UDPCS 0x10 /* UDP xsum calculated */
1819 #define IXGBE_RXD_STAT_L4CS 0x20 /* L4 xsum calculated */
1820 #define IXGBE_RXD_STAT_IPCS 0x40 /* IP xsum calculated */
1821 #define IXGBE_RXD_STAT_PIF 0x80 /* passed in-exact filter */
1822 #define IXGBE_RXD_STAT_CRCV 0x100 /* Speculative CRC Valid */
1823 #define IXGBE_RXD_STAT_VEXT 0x200 /* 1st VLAN found */
1824 #define IXGBE_RXD_STAT_UDPV 0x400 /* Valid UDP checksum */
1825 #define IXGBE_RXD_STAT_DYNINT 0x800 /* Pkt caused INT via DYNINT */
1826 #define IXGBE_RXD_STAT_LLINT 0x800 /* Pkt caused Low Latency Interrupt */
1827 #define IXGBE_RXD_STAT_TS 0x10000 /* Time Stamp */
1828 #define IXGBE_RXD_STAT_SECP 0x20000 /* Security Processing */
1829 #define IXGBE_RXD_STAT_LB 0x40000 /* Loopback Status */
1830 #define IXGBE_RXD_STAT_ACK 0x8000 /* ACK Packet indication */
1831 #define IXGBE_RXD_ERR_CE 0x01 /* CRC Error */
1832 #define IXGBE_RXD_ERR_LE 0x02 /* Length Error */
1833 #define IXGBE_RXD_ERR_PE 0x08 /* Packet Error */
1834 #define IXGBE_RXD_ERR_OSE 0x10 /* Oversize Error */
1835 #define IXGBE_RXD_ERR_USE 0x20 /* Undersize Error */
1836 #define IXGBE_RXD_ERR_TCPE 0x40 /* TCP/UDP Checksum Error */
1837 #define IXGBE_RXD_ERR_IPE 0x80 /* IP Checksum Error */
1838 #define IXGBE_RXDADV_ERR_MASK 0xfff00000 /* RDESC.ERRORS mask */
1839 #define IXGBE_RXDADV_ERR_SHIFT 20 /* RDESC.ERRORS shift */
1840 #define IXGBE_RXDADV_ERR_FCEOFE 0x80000000 /* FCoEFe/IPE */
1841 #define IXGBE_RXDADV_ERR_FCERR 0x00700000 /* FCERR/FDIRERR */
1842 #define IXGBE_RXDADV_ERR_FDIR_LEN 0x00100000 /* FDIR Length error */
1843 #define IXGBE_RXDADV_ERR_FDIR_DROP 0x00200000 /* FDIR Drop error */
1844 #define IXGBE_RXDADV_ERR_FDIR_COLL 0x00400000 /* FDIR Collision error */
1845 #define IXGBE_RXDADV_ERR_HBO 0x00800000 /*Header Buffer Overflow */
1846 #define IXGBE_RXDADV_ERR_CE 0x01000000 /* CRC Error */
1847 #define IXGBE_RXDADV_ERR_LE 0x02000000 /* Length Error */
1848 #define IXGBE_RXDADV_ERR_PE 0x08000000 /* Packet Error */
1849 #define IXGBE_RXDADV_ERR_OSE 0x10000000 /* Oversize Error */
1850 #define IXGBE_RXDADV_ERR_USE 0x20000000 /* Undersize Error */
1851 #define IXGBE_RXDADV_ERR_TCPE 0x40000000 /* TCP/UDP Checksum Error */
1852 #define IXGBE_RXDADV_ERR_IPE 0x80000000 /* IP Checksum Error */
1853 #define IXGBE_RXD_VLAN_ID_MASK 0x0FFF /* VLAN ID is in lower 12 bits */
1854 #define IXGBE_RXD_PRI_MASK 0xE000 /* Priority is in upper 3 bits */
1855 #define IXGBE_RXD_PRI_SHIFT 13
1856 #define IXGBE_RXD_CFI_MASK 0x1000 /* CFI is bit 12 */
1857 #define IXGBE_RXD_CFI_SHIFT 12
1859 #define IXGBE_RXDADV_STAT_DD IXGBE_RXD_STAT_DD /* Done */
1860 #define IXGBE_RXDADV_STAT_EOP IXGBE_RXD_STAT_EOP /* End of Packet */
1861 #define IXGBE_RXDADV_STAT_FLM IXGBE_RXD_STAT_FLM /* FDir Match */
1862 #define IXGBE_RXDADV_STAT_VP IXGBE_RXD_STAT_VP /* IEEE VLAN Pkt */
1863 #define IXGBE_RXDADV_STAT_MASK 0x000fffff /* Stat/NEXTP: bit 0-19 */
1864 #define IXGBE_RXDADV_STAT_FCEOFS 0x00000040 /* FCoE EOF/SOF Stat */
1865 #define IXGBE_RXDADV_STAT_FCSTAT 0x00000030 /* FCoE Pkt Stat */
1866 #define IXGBE_RXDADV_STAT_FCSTAT_NOMTCH 0x00000000 /* 00: No Ctxt Match */
1867 #define IXGBE_RXDADV_STAT_FCSTAT_NODDP 0x00000010 /* 01: Ctxt w/o DDP */
1868 #define IXGBE_RXDADV_STAT_FCSTAT_FCPRSP 0x00000020 /* 10: Recv. FCP_RSP */
1869 #define IXGBE_RXDADV_STAT_FCSTAT_DDP 0x00000030 /* 11: Ctxt w/ DDP */
1871 /* PSRTYPE bit definitions */
1872 #define IXGBE_PSRTYPE_TCPHDR 0x00000010
1873 #define IXGBE_PSRTYPE_UDPHDR 0x00000020
1874 #define IXGBE_PSRTYPE_IPV4HDR 0x00000100
1875 #define IXGBE_PSRTYPE_IPV6HDR 0x00000200
1876 #define IXGBE_PSRTYPE_L2HDR 0x00001000
1878 /* SRRCTL bit definitions */
1879 #define IXGBE_SRRCTL_BSIZEPKT_SHIFT 10 /* so many KBs */
1880 #define IXGBE_SRRCTL_RDMTS_SHIFT 22
1881 #define IXGBE_SRRCTL_RDMTS_MASK 0x01C00000
1882 #define IXGBE_SRRCTL_DROP_EN 0x10000000
1883 #define IXGBE_SRRCTL_BSIZEPKT_MASK 0x0000007F
1884 #define IXGBE_SRRCTL_BSIZEHDR_MASK 0x00003F00
1885 #define IXGBE_SRRCTL_DESCTYPE_LEGACY 0x00000000
1886 #define IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF 0x02000000
1887 #define IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT 0x04000000
1888 #define IXGBE_SRRCTL_DESCTYPE_HDR_REPLICATION_LARGE_PKT 0x08000000
1889 #define IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS 0x0A000000
1890 #define IXGBE_SRRCTL_DESCTYPE_MASK 0x0E000000
1892 #define IXGBE_RXDPS_HDRSTAT_HDRSP 0x00008000
1893 #define IXGBE_RXDPS_HDRSTAT_HDRLEN_MASK 0x000003FF
1895 #define IXGBE_RXDADV_RSSTYPE_MASK 0x0000000F
1896 #define IXGBE_RXDADV_PKTTYPE_MASK 0x0000FFF0
1897 #define IXGBE_RXDADV_PKTTYPE_MASK_EX 0x0001FFF0
1898 #define IXGBE_RXDADV_HDRBUFLEN_MASK 0x00007FE0
1899 #define IXGBE_RXDADV_RSCCNT_MASK 0x001E0000
1900 #define IXGBE_RXDADV_RSCCNT_SHIFT 17
1901 #define IXGBE_RXDADV_HDRBUFLEN_SHIFT 5
1902 #define IXGBE_RXDADV_SPLITHEADER_EN 0x00001000
1903 #define IXGBE_RXDADV_SPH 0x8000
1905 /* RSS Hash results */
1906 #define IXGBE_RXDADV_RSSTYPE_NONE 0x00000000
1907 #define IXGBE_RXDADV_RSSTYPE_IPV4_TCP 0x00000001
1908 #define IXGBE_RXDADV_RSSTYPE_IPV4 0x00000002
1909 #define IXGBE_RXDADV_RSSTYPE_IPV6_TCP 0x00000003
1910 #define IXGBE_RXDADV_RSSTYPE_IPV6_EX 0x00000004
1911 #define IXGBE_RXDADV_RSSTYPE_IPV6 0x00000005
1912 #define IXGBE_RXDADV_RSSTYPE_IPV6_TCP_EX 0x00000006
1913 #define IXGBE_RXDADV_RSSTYPE_IPV4_UDP 0x00000007
1914 #define IXGBE_RXDADV_RSSTYPE_IPV6_UDP 0x00000008
1915 #define IXGBE_RXDADV_RSSTYPE_IPV6_UDP_EX 0x00000009
1917 /* RSS Packet Types as indicated in the receive descriptor. */
1918 #define IXGBE_RXDADV_PKTTYPE_NONE 0x00000000
1919 #define IXGBE_RXDADV_PKTTYPE_IPV4 0x00000010 /* IPv4 hdr present */
1920 #define IXGBE_RXDADV_PKTTYPE_IPV4_EX 0x00000020 /* IPv4 hdr + extensions */
1921 #define IXGBE_RXDADV_PKTTYPE_IPV6 0x00000040 /* IPv6 hdr present */
1922 #define IXGBE_RXDADV_PKTTYPE_IPV6_EX 0x00000080 /* IPv6 hdr + extensions */
1923 #define IXGBE_RXDADV_PKTTYPE_TCP 0x00000100 /* TCP hdr present */
1924 #define IXGBE_RXDADV_PKTTYPE_UDP 0x00000200 /* UDP hdr present */
1925 #define IXGBE_RXDADV_PKTTYPE_SCTP 0x00000400 /* SCTP hdr present */
1926 #define IXGBE_RXDADV_PKTTYPE_NFS 0x00000800 /* NFS hdr present */
1927 #define IXGBE_RXDADV_PKTTYPE_IPSEC_ESP 0x00001000 /* IPSec ESP */
1928 #define IXGBE_RXDADV_PKTTYPE_IPSEC_AH 0x00002000 /* IPSec AH */
1929 #define IXGBE_RXDADV_PKTTYPE_LINKSEC 0x00004000 /* LinkSec Encap */
1930 #define IXGBE_RXDADV_PKTTYPE_ETQF 0x00008000 /* PKTTYPE is ETQF index */
1931 #define IXGBE_RXDADV_PKTTYPE_ETQF_MASK 0x00000070 /* ETQF has 8 indices */
1932 #define IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT 4 /* Right-shift 4 bits */
1934 /* Security Processing bit Indication */
1935 #define IXGBE_RXDADV_LNKSEC_STATUS_SECP 0x00020000
1936 #define IXGBE_RXDADV_LNKSEC_ERROR_NO_SA_MATCH 0x08000000
1937 #define IXGBE_RXDADV_LNKSEC_ERROR_REPLAY_ERROR 0x10000000
1938 #define IXGBE_RXDADV_LNKSEC_ERROR_BIT_MASK 0x18000000
1939 #define IXGBE_RXDADV_LNKSEC_ERROR_BAD_SIG 0x18000000
1941 /* Masks to determine if packets should be dropped due to frame errors */
1942 #define IXGBE_RXD_ERR_FRAME_ERR_MASK ( \
1943 IXGBE_RXD_ERR_CE | \
1944 IXGBE_RXD_ERR_LE | \
1945 IXGBE_RXD_ERR_PE | \
1946 IXGBE_RXD_ERR_OSE | \
1949 #define IXGBE_RXDADV_ERR_FRAME_ERR_MASK ( \
1950 IXGBE_RXDADV_ERR_CE | \
1951 IXGBE_RXDADV_ERR_LE | \
1952 IXGBE_RXDADV_ERR_PE | \
1953 IXGBE_RXDADV_ERR_OSE | \
1954 IXGBE_RXDADV_ERR_USE)
1956 /* Multicast bit mask */
1957 #define IXGBE_MCSTCTRL_MFE 0x4
1959 /* Number of Transmit and Receive Descriptors must be a multiple of 8 */
1960 #define IXGBE_REQ_TX_DESCRIPTOR_MULTIPLE 8
1961 #define IXGBE_REQ_RX_DESCRIPTOR_MULTIPLE 8
1962 #define IXGBE_REQ_TX_BUFFER_GRANULARITY 1024
1964 /* Vlan-specific macros */
1965 #define IXGBE_RX_DESC_SPECIAL_VLAN_MASK 0x0FFF /* VLAN ID in lower 12 bits */
1966 #define IXGBE_RX_DESC_SPECIAL_PRI_MASK 0xE000 /* Priority in upper 3 bits */
1967 #define IXGBE_RX_DESC_SPECIAL_PRI_SHIFT 0x000D /* Priority in upper 3 of 16 */
1968 #define IXGBE_TX_DESC_SPECIAL_PRI_SHIFT IXGBE_RX_DESC_SPECIAL_PRI_SHIFT
1970 /* SR-IOV specific macros */
1971 #define IXGBE_MBVFICR_INDEX(vf_number) (vf_number >> 4)
1972 #define IXGBE_MBVFICR(_i) (0x00710 + (_i * 4))
1973 #define IXGBE_VFLRE(_i) (((_i & 1) ? 0x001C0 : 0x00600))
1974 #define IXGBE_VFLREC(_i) (0x00700 + (_i * 4))
1976 /* Little Endian defines */
1988 /* Big Endian defines */
1994 enum ixgbe_fdir_pballoc_type {
1995 IXGBE_FDIR_PBALLOC_64K = 0,
1996 IXGBE_FDIR_PBALLOC_128K,
1997 IXGBE_FDIR_PBALLOC_256K,
1999 #define IXGBE_FDIR_PBALLOC_SIZE_SHIFT 16
2001 /* Flow Director register values */
2002 #define IXGBE_FDIRCTRL_PBALLOC_64K 0x00000001
2003 #define IXGBE_FDIRCTRL_PBALLOC_128K 0x00000002
2004 #define IXGBE_FDIRCTRL_PBALLOC_256K 0x00000003
2005 #define IXGBE_FDIRCTRL_INIT_DONE 0x00000008
2006 #define IXGBE_FDIRCTRL_PERFECT_MATCH 0x00000010
2007 #define IXGBE_FDIRCTRL_REPORT_STATUS 0x00000020
2008 #define IXGBE_FDIRCTRL_REPORT_STATUS_ALWAYS 0x00000080
2009 #define IXGBE_FDIRCTRL_DROP_Q_SHIFT 8
2010 #define IXGBE_FDIRCTRL_FLEX_SHIFT 16
2011 #define IXGBE_FDIRCTRL_SEARCHLIM 0x00800000
2012 #define IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT 24
2013 #define IXGBE_FDIRCTRL_FULL_THRESH_MASK 0xF0000000
2014 #define IXGBE_FDIRCTRL_FULL_THRESH_SHIFT 28
2016 #define IXGBE_FDIRTCPM_DPORTM_SHIFT 16
2017 #define IXGBE_FDIRUDPM_DPORTM_SHIFT 16
2018 #define IXGBE_FDIRIP6M_DIPM_SHIFT 16
2019 #define IXGBE_FDIRM_VLANID 0x00000001
2020 #define IXGBE_FDIRM_VLANP 0x00000002
2021 #define IXGBE_FDIRM_POOL 0x00000004
2022 #define IXGBE_FDIRM_L4P 0x00000008
2023 #define IXGBE_FDIRM_FLEX 0x00000010
2024 #define IXGBE_FDIRM_DIPv6 0x00000020
2026 #define IXGBE_FDIRFREE_FREE_MASK 0xFFFF
2027 #define IXGBE_FDIRFREE_FREE_SHIFT 0
2028 #define IXGBE_FDIRFREE_COLL_MASK 0x7FFF0000
2029 #define IXGBE_FDIRFREE_COLL_SHIFT 16
2030 #define IXGBE_FDIRLEN_MAXLEN_MASK 0x3F
2031 #define IXGBE_FDIRLEN_MAXLEN_SHIFT 0
2032 #define IXGBE_FDIRLEN_MAXHASH_MASK 0x7FFF0000
2033 #define IXGBE_FDIRLEN_MAXHASH_SHIFT 16
2034 #define IXGBE_FDIRUSTAT_ADD_MASK 0xFFFF
2035 #define IXGBE_FDIRUSTAT_ADD_SHIFT 0
2036 #define IXGBE_FDIRUSTAT_REMOVE_MASK 0xFFFF0000
2037 #define IXGBE_FDIRUSTAT_REMOVE_SHIFT 16
2038 #define IXGBE_FDIRFSTAT_FADD_MASK 0x00FF
2039 #define IXGBE_FDIRFSTAT_FADD_SHIFT 0
2040 #define IXGBE_FDIRFSTAT_FREMOVE_MASK 0xFF00
2041 #define IXGBE_FDIRFSTAT_FREMOVE_SHIFT 8
2042 #define IXGBE_FDIRPORT_DESTINATION_SHIFT 16
2043 #define IXGBE_FDIRVLAN_FLEX_SHIFT 16
2044 #define IXGBE_FDIRHASH_BUCKET_VALID_SHIFT 15
2045 #define IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT 16
2047 #define IXGBE_FDIRCMD_CMD_MASK 0x00000003
2048 #define IXGBE_FDIRCMD_CMD_ADD_FLOW 0x00000001
2049 #define IXGBE_FDIRCMD_CMD_REMOVE_FLOW 0x00000002
2050 #define IXGBE_FDIRCMD_CMD_QUERY_REM_FILT 0x00000003
2051 #define IXGBE_FDIRCMD_CMD_QUERY_REM_HASH 0x00000007
2052 #define IXGBE_FDIRCMD_FILTER_UPDATE 0x00000008
2053 #define IXGBE_FDIRCMD_IPv6DMATCH 0x00000010
2054 #define IXGBE_FDIRCMD_L4TYPE_UDP 0x00000020
2055 #define IXGBE_FDIRCMD_L4TYPE_TCP 0x00000040
2056 #define IXGBE_FDIRCMD_L4TYPE_SCTP 0x00000060
2057 #define IXGBE_FDIRCMD_IPV6 0x00000080
2058 #define IXGBE_FDIRCMD_CLEARHT 0x00000100
2059 #define IXGBE_FDIRCMD_DROP 0x00000200
2060 #define IXGBE_FDIRCMD_INT 0x00000400
2061 #define IXGBE_FDIRCMD_LAST 0x00000800
2062 #define IXGBE_FDIRCMD_COLLISION 0x00001000
2063 #define IXGBE_FDIRCMD_QUEUE_EN 0x00008000
2064 #define IXGBE_FDIRCMD_RX_QUEUE_SHIFT 16
2065 #define IXGBE_FDIRCMD_VT_POOL_SHIFT 24
2066 #define IXGBE_FDIR_INIT_DONE_POLL 10
2067 #define IXGBE_FDIRCMD_CMD_POLL 10
2069 /* Transmit Descriptor - Legacy */
2070 struct ixgbe_legacy_tx_desc {
2071 u64 buffer_addr; /* Address of the descriptor's data buffer */
2075 __le16 length; /* Data buffer length */
2076 u8 cso; /* Checksum offset */
2077 u8 cmd; /* Descriptor control */
2083 u8 status; /* Descriptor status */
2084 u8 css; /* Checksum start */
2090 /* Transmit Descriptor - Advanced */
2091 union ixgbe_adv_tx_desc {
2093 __le64 buffer_addr; /* Address of descriptor's data buf */
2094 __le32 cmd_type_len;
2095 __le32 olinfo_status;
2098 __le64 rsvd; /* Reserved */
2104 /* Receive Descriptor - Legacy */
2105 struct ixgbe_legacy_rx_desc {
2106 __le64 buffer_addr; /* Address of the descriptor's data buffer */
2107 __le16 length; /* Length of data DMAed into data buffer */
2108 __le16 csum; /* Packet checksum */
2109 u8 status; /* Descriptor status */
2110 u8 errors; /* Descriptor Errors */
2114 /* Receive Descriptor - Advanced */
2115 union ixgbe_adv_rx_desc {
2117 __le64 pkt_addr; /* Packet buffer address */
2118 __le64 hdr_addr; /* Header buffer address */
2125 __le16 pkt_info; /* RSS, Pkt type */
2126 __le16 hdr_info; /* Splithdr, hdrlen */
2130 __le32 rss; /* RSS Hash */
2132 __le16 ip_id; /* IP id */
2133 __le16 csum; /* Packet Checksum */
2138 __le32 status_error; /* ext status/error */
2139 __le16 length; /* Packet length */
2140 __le16 vlan; /* VLAN tag */
2142 } wb; /* writeback */
2145 /* Context descriptors */
2146 struct ixgbe_adv_tx_context_desc {
2147 __le32 vlan_macip_lens;
2149 __le32 type_tucmd_mlhl;
2150 __le32 mss_l4len_idx;
2153 /* Adv Transmit Descriptor Config Masks */
2154 #define IXGBE_ADVTXD_DTALEN_MASK 0x0000FFFF /* Data buf length(bytes) */
2155 #define IXGBE_ADVTXD_MAC_LINKSEC 0x00040000 /* Insert LinkSec */
2156 #define IXGBE_ADVTXD_IPSEC_SA_INDEX_MASK 0x000003FF /* IPSec SA index */
2157 #define IXGBE_ADVTXD_IPSEC_ESP_LEN_MASK 0x000001FF /* IPSec ESP length */
2158 #define IXGBE_ADVTXD_DTYP_MASK 0x00F00000 /* DTYP mask */
2159 #define IXGBE_ADVTXD_DTYP_CTXT 0x00200000 /* Advanced Context Desc */
2160 #define IXGBE_ADVTXD_DTYP_DATA 0x00300000 /* Advanced Data Descriptor */
2161 #define IXGBE_ADVTXD_DCMD_EOP IXGBE_TXD_CMD_EOP /* End of Packet */
2162 #define IXGBE_ADVTXD_DCMD_IFCS IXGBE_TXD_CMD_IFCS /* Insert FCS */
2163 #define IXGBE_ADVTXD_DCMD_RS IXGBE_TXD_CMD_RS /* Report Status */
2164 #define IXGBE_ADVTXD_DCMD_DDTYP_ISCSI 0x10000000 /* DDP hdr type or iSCSI */
2165 #define IXGBE_ADVTXD_DCMD_DEXT IXGBE_TXD_CMD_DEXT /* Desc ext (1=Adv) */
2166 #define IXGBE_ADVTXD_DCMD_VLE IXGBE_TXD_CMD_VLE /* VLAN pkt enable */
2167 #define IXGBE_ADVTXD_DCMD_TSE 0x80000000 /* TCP Seg enable */
2168 #define IXGBE_ADVTXD_STAT_DD IXGBE_TXD_STAT_DD /* Descriptor Done */
2169 #define IXGBE_ADVTXD_STAT_SN_CRC 0x00000002 /* NXTSEQ/SEED pres in WB */
2170 #define IXGBE_ADVTXD_STAT_RSV 0x0000000C /* STA Reserved */
2171 #define IXGBE_ADVTXD_IDX_SHIFT 4 /* Adv desc Index shift */
2172 #define IXGBE_ADVTXD_CC 0x00000080 /* Check Context */
2173 #define IXGBE_ADVTXD_POPTS_SHIFT 8 /* Adv desc POPTS shift */
2174 #define IXGBE_ADVTXD_POPTS_IXSM (IXGBE_TXD_POPTS_IXSM << \
2175 IXGBE_ADVTXD_POPTS_SHIFT)
2176 #define IXGBE_ADVTXD_POPTS_TXSM (IXGBE_TXD_POPTS_TXSM << \
2177 IXGBE_ADVTXD_POPTS_SHIFT)
2178 #define IXGBE_ADVTXD_POPTS_ISCO_1ST 0x00000000 /* 1st TSO of iSCSI PDU */
2179 #define IXGBE_ADVTXD_POPTS_ISCO_MDL 0x00000800 /* Middle TSO of iSCSI PDU */
2180 #define IXGBE_ADVTXD_POPTS_ISCO_LAST 0x00001000 /* Last TSO of iSCSI PDU */
2181 #define IXGBE_ADVTXD_POPTS_ISCO_FULL 0x00001800 /* 1st&Last TSO-full iSCSI PDU */
2182 #define IXGBE_ADVTXD_POPTS_RSV 0x00002000 /* POPTS Reserved */
2183 #define IXGBE_ADVTXD_PAYLEN_SHIFT 14 /* Adv desc PAYLEN shift */
2184 #define IXGBE_ADVTXD_MACLEN_SHIFT 9 /* Adv ctxt desc mac len shift */
2185 #define IXGBE_ADVTXD_VLAN_SHIFT 16 /* Adv ctxt vlan tag shift */
2186 #define IXGBE_ADVTXD_TUCMD_IPV4 0x00000400 /* IP Packet Type: 1=IPv4 */
2187 #define IXGBE_ADVTXD_TUCMD_IPV6 0x00000000 /* IP Packet Type: 0=IPv6 */
2188 #define IXGBE_ADVTXD_TUCMD_L4T_UDP 0x00000000 /* L4 Packet TYPE of UDP */
2189 #define IXGBE_ADVTXD_TUCMD_L4T_TCP 0x00000800 /* L4 Packet TYPE of TCP */
2190 #define IXGBE_ADVTXD_TUCMD_L4T_SCTP 0x00001000 /* L4 Packet TYPE of SCTP */
2191 #define IXGBE_ADVTXD_TUCMD_MKRREQ 0x00002000 /*Req requires Markers and CRC*/
2192 #define IXGBE_ADVTXD_POPTS_IPSEC 0x00000400 /* IPSec offload request */
2193 #define IXGBE_ADVTXD_TUCMD_IPSEC_TYPE_ESP 0x00002000 /* IPSec Type ESP */
2194 #define IXGBE_ADVTXD_TUCMD_IPSEC_ENCRYPT_EN 0x00004000/* ESP Encrypt Enable */
2195 #define IXGBE_ADVTXT_TUCMD_FCOE 0x00008000 /* FCoE Frame Type */
2196 #define IXGBE_ADVTXD_FCOEF_EOF_MASK (0x3 << 10) /* FC EOF index */
2197 #define IXGBE_ADVTXD_FCOEF_SOF ((1 << 2) << 10) /* FC SOF index */
2198 #define IXGBE_ADVTXD_FCOEF_PARINC ((1 << 3) << 10) /* Rel_Off in F_CTL */
2199 #define IXGBE_ADVTXD_FCOEF_ORIE ((1 << 4) << 10) /* Orientation: End */
2200 #define IXGBE_ADVTXD_FCOEF_ORIS ((1 << 5) << 10) /* Orientation: Start */
2201 #define IXGBE_ADVTXD_FCOEF_EOF_N (0x0 << 10) /* 00: EOFn */
2202 #define IXGBE_ADVTXD_FCOEF_EOF_T (0x1 << 10) /* 01: EOFt */
2203 #define IXGBE_ADVTXD_FCOEF_EOF_NI (0x2 << 10) /* 10: EOFni */
2204 #define IXGBE_ADVTXD_FCOEF_EOF_A (0x3 << 10) /* 11: EOFa */
2205 #define IXGBE_ADVTXD_L4LEN_SHIFT 8 /* Adv ctxt L4LEN shift */
2206 #define IXGBE_ADVTXD_MSS_SHIFT 16 /* Adv ctxt MSS shift */
2208 /* Autonegotiation advertised speeds */
2209 typedef u32 ixgbe_autoneg_advertised;
2211 typedef u32 ixgbe_link_speed;
2212 #define IXGBE_LINK_SPEED_UNKNOWN 0
2213 #define IXGBE_LINK_SPEED_100_FULL 0x0008
2214 #define IXGBE_LINK_SPEED_1GB_FULL 0x0020
2215 #define IXGBE_LINK_SPEED_10GB_FULL 0x0080
2216 #define IXGBE_LINK_SPEED_82598_AUTONEG (IXGBE_LINK_SPEED_1GB_FULL | \
2217 IXGBE_LINK_SPEED_10GB_FULL)
2218 #define IXGBE_LINK_SPEED_82599_AUTONEG (IXGBE_LINK_SPEED_100_FULL | \
2219 IXGBE_LINK_SPEED_1GB_FULL | \
2220 IXGBE_LINK_SPEED_10GB_FULL)
2223 /* Physical layer type */
2224 typedef u32 ixgbe_physical_layer;
2225 #define IXGBE_PHYSICAL_LAYER_UNKNOWN 0
2226 #define IXGBE_PHYSICAL_LAYER_10GBASE_T 0x0001
2227 #define IXGBE_PHYSICAL_LAYER_1000BASE_T 0x0002
2228 #define IXGBE_PHYSICAL_LAYER_100BASE_TX 0x0004
2229 #define IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU 0x0008
2230 #define IXGBE_PHYSICAL_LAYER_10GBASE_LR 0x0010
2231 #define IXGBE_PHYSICAL_LAYER_10GBASE_LRM 0x0020
2232 #define IXGBE_PHYSICAL_LAYER_10GBASE_SR 0x0040
2233 #define IXGBE_PHYSICAL_LAYER_10GBASE_KX4 0x0080
2234 #define IXGBE_PHYSICAL_LAYER_10GBASE_CX4 0x0100
2235 #define IXGBE_PHYSICAL_LAYER_1000BASE_KX 0x0200
2236 #define IXGBE_PHYSICAL_LAYER_1000BASE_BX 0x0400
2237 #define IXGBE_PHYSICAL_LAYER_10GBASE_KR 0x0800
2238 #define IXGBE_PHYSICAL_LAYER_10GBASE_XAUI 0x1000
2239 #define IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA 0x2000
2242 /* Software ATR hash keys */
2243 #define IXGBE_ATR_BUCKET_HASH_KEY 0xE214AD3D
2244 #define IXGBE_ATR_SIGNATURE_HASH_KEY 0x14364D17
2246 /* Software ATR input stream offsets and masks */
2247 #define IXGBE_ATR_VLAN_OFFSET 0
2248 #define IXGBE_ATR_SRC_IPV6_OFFSET 2
2249 #define IXGBE_ATR_SRC_IPV4_OFFSET 14
2250 #define IXGBE_ATR_DST_IPV6_OFFSET 18
2251 #define IXGBE_ATR_DST_IPV4_OFFSET 30
2252 #define IXGBE_ATR_SRC_PORT_OFFSET 34
2253 #define IXGBE_ATR_DST_PORT_OFFSET 36
2254 #define IXGBE_ATR_FLEX_BYTE_OFFSET 38
2255 #define IXGBE_ATR_VM_POOL_OFFSET 40
2256 #define IXGBE_ATR_L4TYPE_OFFSET 41
2258 #define IXGBE_ATR_L4TYPE_MASK 0x3
2259 #define IXGBE_ATR_L4TYPE_IPV6_MASK 0x4
2260 #define IXGBE_ATR_L4TYPE_UDP 0x1
2261 #define IXGBE_ATR_L4TYPE_TCP 0x2
2262 #define IXGBE_ATR_L4TYPE_SCTP 0x3
2263 #define IXGBE_ATR_HASH_MASK 0x7fff
2265 /* Flow Director ATR input struct. */
2266 struct ixgbe_atr_input {
2267 /* Byte layout in order, all values with MSB first:
2272 * src_port - 2 bytes
2273 * dst_port - 2 bytes
2274 * flex_bytes - 2 bytes
2281 struct ixgbe_atr_input_masks {
2290 enum ixgbe_eeprom_type {
2291 ixgbe_eeprom_uninitialized = 0,
2294 ixgbe_eeprom_none /* No NVM support */
2297 enum ixgbe_mac_type {
2298 ixgbe_mac_unknown = 0,
2304 enum ixgbe_phy_type {
2305 ixgbe_phy_unknown = 0,
2309 ixgbe_phy_cu_unknown,
2313 ixgbe_phy_sfp_passive_tyco,
2314 ixgbe_phy_sfp_passive_unknown,
2315 ixgbe_phy_sfp_active_unknown,
2316 ixgbe_phy_sfp_avago,
2318 ixgbe_phy_sfp_ftl_active,
2319 ixgbe_phy_sfp_unknown,
2320 ixgbe_phy_sfp_intel,
2321 ixgbe_phy_sfp_unsupported, /*Enforce bit set with unsupported module*/
2326 * SFP+ module type IDs:
2333 * 3 SFP_DA_CU_CORE0 - 82599-specific
2334 * 4 SFP_DA_CU_CORE1 - 82599-specific
2335 * 5 SFP_SR/LR_CORE0 - 82599-specific
2336 * 6 SFP_SR/LR_CORE1 - 82599-specific
2338 enum ixgbe_sfp_type {
2339 ixgbe_sfp_type_da_cu = 0,
2340 ixgbe_sfp_type_sr = 1,
2341 ixgbe_sfp_type_lr = 2,
2342 ixgbe_sfp_type_da_cu_core0 = 3,
2343 ixgbe_sfp_type_da_cu_core1 = 4,
2344 ixgbe_sfp_type_srlr_core0 = 5,
2345 ixgbe_sfp_type_srlr_core1 = 6,
2346 ixgbe_sfp_type_da_act_lmt_core0 = 7,
2347 ixgbe_sfp_type_da_act_lmt_core1 = 8,
2348 ixgbe_sfp_type_not_present = 0xFFFE,
2349 ixgbe_sfp_type_unknown = 0xFFFF
2352 enum ixgbe_media_type {
2353 ixgbe_media_type_unknown = 0,
2354 ixgbe_media_type_fiber,
2355 ixgbe_media_type_copper,
2356 ixgbe_media_type_backplane,
2357 ixgbe_media_type_cx4,
2358 ixgbe_media_type_virtual
2361 /* Flow Control Settings */
2362 enum ixgbe_fc_mode {
2370 /* Smart Speed Settings */
2371 #define IXGBE_SMARTSPEED_MAX_RETRIES 3
2372 enum ixgbe_smart_speed {
2373 ixgbe_smart_speed_auto = 0,
2374 ixgbe_smart_speed_on,
2375 ixgbe_smart_speed_off
2379 enum ixgbe_bus_type {
2380 ixgbe_bus_type_unknown = 0,
2382 ixgbe_bus_type_pcix,
2383 ixgbe_bus_type_pci_express,
2384 ixgbe_bus_type_reserved
2387 /* PCI bus speeds */
2388 enum ixgbe_bus_speed {
2389 ixgbe_bus_speed_unknown = 0,
2390 ixgbe_bus_speed_33 = 33,
2391 ixgbe_bus_speed_66 = 66,
2392 ixgbe_bus_speed_100 = 100,
2393 ixgbe_bus_speed_120 = 120,
2394 ixgbe_bus_speed_133 = 133,
2395 ixgbe_bus_speed_2500 = 2500,
2396 ixgbe_bus_speed_5000 = 5000,
2397 ixgbe_bus_speed_reserved
2400 /* PCI bus widths */
2401 enum ixgbe_bus_width {
2402 ixgbe_bus_width_unknown = 0,
2403 ixgbe_bus_width_pcie_x1 = 1,
2404 ixgbe_bus_width_pcie_x2 = 2,
2405 ixgbe_bus_width_pcie_x4 = 4,
2406 ixgbe_bus_width_pcie_x8 = 8,
2407 ixgbe_bus_width_32 = 32,
2408 ixgbe_bus_width_64 = 64,
2409 ixgbe_bus_width_reserved
2412 struct ixgbe_addr_filter_info {
2416 u32 overflow_promisc;
2417 bool user_set_promisc;
2420 /* Bus parameters */
2421 struct ixgbe_bus_info {
2422 enum ixgbe_bus_speed speed;
2423 enum ixgbe_bus_width width;
2424 enum ixgbe_bus_type type;
2430 /* Flow control parameters */
2431 struct ixgbe_fc_info {
2432 u32 high_water; /* Flow Control High-water */
2433 u32 low_water; /* Flow Control Low-water */
2434 u16 pause_time; /* Flow Control Pause timer */
2435 bool send_xon; /* Flow control send XON */
2436 bool strict_ieee; /* Strict IEEE mode */
2437 bool disable_fc_autoneg; /* Do not autonegotiate FC */
2438 bool fc_was_autonegged; /* Is current_mode the result of autonegging? */
2439 enum ixgbe_fc_mode current_mode; /* FC mode in effect */
2440 enum ixgbe_fc_mode requested_mode; /* FC mode requested by caller */
2443 /* Statistics counters collected by the MAC */
2444 struct ixgbe_hw_stats {
2503 u64 fdirustat_remove;
2505 u64 fdirfstat_fremove;
2517 /* forward declaration */
2520 /* iterator type for walking multicast address lists */
2521 typedef u8* (*ixgbe_mc_addr_itr) (struct ixgbe_hw *hw, u8 **mc_addr_ptr,
2524 /* Function pointer table */
2525 struct ixgbe_eeprom_operations {
2526 s32 (*init_params)(struct ixgbe_hw *);
2527 s32 (*read)(struct ixgbe_hw *, u16, u16 *);
2528 s32 (*write)(struct ixgbe_hw *, u16, u16);
2529 s32 (*validate_checksum)(struct ixgbe_hw *, u16 *);
2530 s32 (*update_checksum)(struct ixgbe_hw *);
2531 u16 (*calc_checksum)(struct ixgbe_hw *);
2534 struct ixgbe_mac_operations {
2535 s32 (*init_hw)(struct ixgbe_hw *);
2536 s32 (*reset_hw)(struct ixgbe_hw *);
2537 s32 (*start_hw)(struct ixgbe_hw *);
2538 s32 (*clear_hw_cntrs)(struct ixgbe_hw *);
2539 void (*enable_relaxed_ordering)(struct ixgbe_hw *);
2540 enum ixgbe_media_type (*get_media_type)(struct ixgbe_hw *);
2541 u32 (*get_supported_physical_layer)(struct ixgbe_hw *);
2542 s32 (*get_mac_addr)(struct ixgbe_hw *, u8 *);
2543 s32 (*get_san_mac_addr)(struct ixgbe_hw *, u8 *);
2544 s32 (*set_san_mac_addr)(struct ixgbe_hw *, u8 *);
2545 s32 (*get_device_caps)(struct ixgbe_hw *, u16 *);
2546 s32 (*get_wwn_prefix)(struct ixgbe_hw *, u16 *, u16 *);
2547 s32 (*stop_adapter)(struct ixgbe_hw *);
2548 s32 (*get_bus_info)(struct ixgbe_hw *);
2549 void (*set_lan_id)(struct ixgbe_hw *);
2550 s32 (*read_analog_reg8)(struct ixgbe_hw*, u32, u8*);
2551 s32 (*write_analog_reg8)(struct ixgbe_hw*, u32, u8);
2552 s32 (*setup_sfp)(struct ixgbe_hw *);
2553 s32 (*enable_rx_dma)(struct ixgbe_hw *, u32);
2554 s32 (*acquire_swfw_sync)(struct ixgbe_hw *, u16);
2555 void (*release_swfw_sync)(struct ixgbe_hw *, u16);
2558 s32 (*setup_link)(struct ixgbe_hw *, ixgbe_link_speed, bool, bool);
2559 s32 (*check_link)(struct ixgbe_hw *, ixgbe_link_speed *, bool *, bool);
2560 s32 (*get_link_capabilities)(struct ixgbe_hw *, ixgbe_link_speed *,
2564 s32 (*led_on)(struct ixgbe_hw *, u32);
2565 s32 (*led_off)(struct ixgbe_hw *, u32);
2566 s32 (*blink_led_start)(struct ixgbe_hw *, u32);
2567 s32 (*blink_led_stop)(struct ixgbe_hw *, u32);
2569 /* RAR, Multicast, VLAN */
2570 s32 (*set_rar)(struct ixgbe_hw *, u32, u8 *, u32, u32);
2571 s32 (*clear_rar)(struct ixgbe_hw *, u32);
2572 s32 (*insert_mac_addr)(struct ixgbe_hw *, u8 *, u32);
2573 s32 (*set_vmdq)(struct ixgbe_hw *, u32, u32);
2574 s32 (*clear_vmdq)(struct ixgbe_hw *, u32, u32);
2575 s32 (*init_rx_addrs)(struct ixgbe_hw *);
2576 s32 (*update_uc_addr_list)(struct ixgbe_hw *, u8 *, u32,
2578 s32 (*update_mc_addr_list)(struct ixgbe_hw *, u8 *, u32,
2580 s32 (*enable_mc)(struct ixgbe_hw *);
2581 s32 (*disable_mc)(struct ixgbe_hw *);
2582 s32 (*clear_vfta)(struct ixgbe_hw *);
2583 s32 (*set_vfta)(struct ixgbe_hw *, u32, u32, bool);
2584 s32 (*init_uta_tables)(struct ixgbe_hw *);
2587 s32 (*fc_enable)(struct ixgbe_hw *, s32);
2590 struct ixgbe_phy_operations {
2591 s32 (*identify)(struct ixgbe_hw *);
2592 s32 (*identify_sfp)(struct ixgbe_hw *);
2593 s32 (*init)(struct ixgbe_hw *);
2594 s32 (*reset)(struct ixgbe_hw *);
2595 s32 (*read_reg)(struct ixgbe_hw *, u32, u32, u16 *);
2596 s32 (*write_reg)(struct ixgbe_hw *, u32, u32, u16);
2597 s32 (*setup_link)(struct ixgbe_hw *);
2598 s32 (*setup_link_speed)(struct ixgbe_hw *, ixgbe_link_speed, bool,
2600 s32 (*check_link)(struct ixgbe_hw *, ixgbe_link_speed *, bool *);
2601 s32 (*get_firmware_version)(struct ixgbe_hw *, u16 *);
2602 s32 (*read_i2c_byte)(struct ixgbe_hw *, u8, u8, u8 *);
2603 s32 (*write_i2c_byte)(struct ixgbe_hw *, u8, u8, u8);
2604 s32 (*read_i2c_eeprom)(struct ixgbe_hw *, u8 , u8 *);
2605 s32 (*write_i2c_eeprom)(struct ixgbe_hw *, u8, u8);
2606 void (*i2c_bus_clear)(struct ixgbe_hw *);
2607 s32 (*check_overtemp)(struct ixgbe_hw *);
2608 s32 (*set_low_power_state)(struct ixgbe_hw *);
2611 struct ixgbe_eeprom_info {
2612 struct ixgbe_eeprom_operations ops;
2613 enum ixgbe_eeprom_type type;
2614 u32 semaphore_delay;
2619 #define IXGBE_FLAGS_DOUBLE_RESET_REQUIRED 0x01
2620 struct ixgbe_mac_info {
2621 struct ixgbe_mac_operations ops;
2622 enum ixgbe_mac_type type;
2623 u8 addr[IXGBE_ETH_LENGTH_OF_ADDRESS];
2624 u8 perm_addr[IXGBE_ETH_LENGTH_OF_ADDRESS];
2625 u8 san_addr[IXGBE_ETH_LENGTH_OF_ADDRESS];
2626 /* prefix for World Wide Node Name (WWNN) */
2628 /* prefix for World Wide Port Name (WWPN) */
2633 u32 num_rar_entries;
2637 u32 max_msix_vectors;
2638 bool msix_vectors_from_pcie;
2641 bool orig_link_settings_stored;
2642 bool autotry_restart;
2646 struct ixgbe_phy_info {
2647 struct ixgbe_phy_operations ops;
2648 enum ixgbe_phy_type type;
2651 enum ixgbe_sfp_type sfp_type;
2652 bool sfp_setup_needed;
2654 enum ixgbe_media_type media_type;
2656 ixgbe_autoneg_advertised autoneg_advertised;
2657 enum ixgbe_smart_speed smart_speed;
2658 bool smart_speed_active;
2659 bool multispeed_fiber;
2665 struct ixgbe_mac_info mac;
2666 struct ixgbe_addr_filter_info addr_ctrl;
2667 struct ixgbe_fc_info fc;
2668 struct ixgbe_phy_info phy;
2669 struct ixgbe_eeprom_info eeprom;
2670 struct ixgbe_bus_info bus;
2673 u16 subsystem_device_id;
2674 u16 subsystem_vendor_id;
2676 bool adapter_stopped;
2679 #define ixgbe_call_func(hw, func, params, error) \
2680 (func != NULL) ? func params : error
2684 #define IXGBE_SUCCESS 0
2685 #define IXGBE_ERR_EEPROM -1
2686 #define IXGBE_ERR_EEPROM_CHECKSUM -2
2687 #define IXGBE_ERR_PHY -3
2688 #define IXGBE_ERR_CONFIG -4
2689 #define IXGBE_ERR_PARAM -5
2690 #define IXGBE_ERR_MAC_TYPE -6
2691 #define IXGBE_ERR_UNKNOWN_PHY -7
2692 #define IXGBE_ERR_LINK_SETUP -8
2693 #define IXGBE_ERR_ADAPTER_STOPPED -9
2694 #define IXGBE_ERR_INVALID_MAC_ADDR -10
2695 #define IXGBE_ERR_DEVICE_NOT_SUPPORTED -11
2696 #define IXGBE_ERR_MASTER_REQUESTS_PENDING -12
2697 #define IXGBE_ERR_INVALID_LINK_SETTINGS -13
2698 #define IXGBE_ERR_AUTONEG_NOT_COMPLETE -14
2699 #define IXGBE_ERR_RESET_FAILED -15
2700 #define IXGBE_ERR_SWFW_SYNC -16
2701 #define IXGBE_ERR_PHY_ADDR_INVALID -17
2702 #define IXGBE_ERR_I2C -18
2703 #define IXGBE_ERR_SFP_NOT_SUPPORTED -19
2704 #define IXGBE_ERR_SFP_NOT_PRESENT -20
2705 #define IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT -21
2706 #define IXGBE_ERR_NO_SAN_ADDR_PTR -22
2707 #define IXGBE_ERR_FDIR_REINIT_FAILED -23
2708 #define IXGBE_ERR_EEPROM_VERSION -24
2709 #define IXGBE_ERR_NO_SPACE -25
2710 #define IXGBE_ERR_OVERTEMP -26
2711 #define IXGBE_NOT_IMPLEMENTED 0x7FFFFFFF
2714 #endif /* _IXGBE_TYPE_H_ */