2 * Copyright (c) 2008, Pyun YongHyeon <yongari@FreeBSD.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice unmodified, this list of conditions, and the following
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 #include <sys/cdefs.h>
29 __FBSDID("$FreeBSD$");
31 #include <sys/param.h>
32 #include <sys/systm.h>
34 #include <sys/endian.h>
35 #include <sys/kernel.h>
36 #include <sys/malloc.h>
39 #include <sys/module.h>
41 #include <sys/queue.h>
42 #include <sys/socket.h>
43 #include <sys/sockio.h>
44 #include <sys/sysctl.h>
45 #include <sys/taskqueue.h>
49 #include <net/if_arp.h>
50 #include <net/ethernet.h>
51 #include <net/if_dl.h>
52 #include <net/if_media.h>
53 #include <net/if_types.h>
54 #include <net/if_vlan_var.h>
56 #include <netinet/in.h>
57 #include <netinet/in_systm.h>
58 #include <netinet/ip.h>
59 #include <netinet/tcp.h>
61 #include <dev/mii/mii.h>
62 #include <dev/mii/miivar.h>
64 #include <dev/pci/pcireg.h>
65 #include <dev/pci/pcivar.h>
67 #include <machine/atomic.h>
68 #include <machine/bus.h>
69 #include <machine/in_cksum.h>
71 #include <dev/jme/if_jmereg.h>
72 #include <dev/jme/if_jmevar.h>
74 /* "device miibus" required. See GENERIC if you get errors here. */
75 #include "miibus_if.h"
77 /* Define the following to disable printing Rx errors. */
78 #undef JME_SHOW_ERRORS
80 #define JME_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
82 MODULE_DEPEND(jme, pci, 1, 1, 1);
83 MODULE_DEPEND(jme, ether, 1, 1, 1);
84 MODULE_DEPEND(jme, miibus, 1, 1, 1);
87 static int msi_disable = 0;
88 static int msix_disable = 0;
89 TUNABLE_INT("hw.jme.msi_disable", &msi_disable);
90 TUNABLE_INT("hw.jme.msix_disable", &msix_disable);
93 * Devices supported by this driver.
95 static struct jme_dev {
96 uint16_t jme_vendorid;
97 uint16_t jme_deviceid;
100 { VENDORID_JMICRON, DEVICEID_JMC250,
101 "JMicron Inc, JMC250 Gigabit Ethernet" },
102 { VENDORID_JMICRON, DEVICEID_JMC260,
103 "JMicron Inc, JMC260 Fast Ethernet" },
106 static int jme_miibus_readreg(device_t, int, int);
107 static int jme_miibus_writereg(device_t, int, int, int);
108 static void jme_miibus_statchg(device_t);
109 static void jme_mediastatus(struct ifnet *, struct ifmediareq *);
110 static int jme_mediachange(struct ifnet *);
111 static int jme_probe(device_t);
112 static int jme_eeprom_read_byte(struct jme_softc *, uint8_t, uint8_t *);
113 static int jme_eeprom_macaddr(struct jme_softc *);
114 static void jme_reg_macaddr(struct jme_softc *);
115 static void jme_map_intr_vector(struct jme_softc *);
116 static int jme_attach(device_t);
117 static int jme_detach(device_t);
118 static void jme_sysctl_node(struct jme_softc *);
119 static void jme_dmamap_cb(void *, bus_dma_segment_t *, int, int);
120 static int jme_dma_alloc(struct jme_softc *);
121 static void jme_dma_free(struct jme_softc *);
122 static int jme_shutdown(device_t);
123 static void jme_setlinkspeed(struct jme_softc *);
124 static void jme_setwol(struct jme_softc *);
125 static int jme_suspend(device_t);
126 static int jme_resume(device_t);
127 static int jme_encap(struct jme_softc *, struct mbuf **);
128 static void jme_tx_task(void *, int);
129 static void jme_start(struct ifnet *);
130 static void jme_watchdog(struct jme_softc *);
131 static int jme_ioctl(struct ifnet *, u_long, caddr_t);
132 static void jme_mac_config(struct jme_softc *);
133 static void jme_link_task(void *, int);
134 static int jme_intr(void *);
135 static void jme_int_task(void *, int);
136 static void jme_txeof(struct jme_softc *);
137 static __inline void jme_discard_rxbuf(struct jme_softc *, int);
138 static void jme_rxeof(struct jme_softc *);
139 static int jme_rxintr(struct jme_softc *, int);
140 static void jme_tick(void *);
141 static void jme_reset(struct jme_softc *);
142 static void jme_init(void *);
143 static void jme_init_locked(struct jme_softc *);
144 static void jme_stop(struct jme_softc *);
145 static void jme_stop_tx(struct jme_softc *);
146 static void jme_stop_rx(struct jme_softc *);
147 static int jme_init_rx_ring(struct jme_softc *);
148 static void jme_init_tx_ring(struct jme_softc *);
149 static void jme_init_ssb(struct jme_softc *);
150 static int jme_newbuf(struct jme_softc *, struct jme_rxdesc *);
151 static void jme_set_vlan(struct jme_softc *);
152 static void jme_set_filter(struct jme_softc *);
153 static void jme_stats_clear(struct jme_softc *);
154 static void jme_stats_save(struct jme_softc *);
155 static void jme_stats_update(struct jme_softc *);
156 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int);
157 static int sysctl_hw_jme_tx_coal_to(SYSCTL_HANDLER_ARGS);
158 static int sysctl_hw_jme_tx_coal_pkt(SYSCTL_HANDLER_ARGS);
159 static int sysctl_hw_jme_rx_coal_to(SYSCTL_HANDLER_ARGS);
160 static int sysctl_hw_jme_rx_coal_pkt(SYSCTL_HANDLER_ARGS);
161 static int sysctl_hw_jme_proc_limit(SYSCTL_HANDLER_ARGS);
164 static device_method_t jme_methods[] = {
165 /* Device interface. */
166 DEVMETHOD(device_probe, jme_probe),
167 DEVMETHOD(device_attach, jme_attach),
168 DEVMETHOD(device_detach, jme_detach),
169 DEVMETHOD(device_shutdown, jme_shutdown),
170 DEVMETHOD(device_suspend, jme_suspend),
171 DEVMETHOD(device_resume, jme_resume),
174 DEVMETHOD(miibus_readreg, jme_miibus_readreg),
175 DEVMETHOD(miibus_writereg, jme_miibus_writereg),
176 DEVMETHOD(miibus_statchg, jme_miibus_statchg),
181 static driver_t jme_driver = {
184 sizeof(struct jme_softc)
187 static devclass_t jme_devclass;
189 DRIVER_MODULE(jme, pci, jme_driver, jme_devclass, 0, 0);
190 DRIVER_MODULE(miibus, jme, miibus_driver, miibus_devclass, 0, 0);
192 static struct resource_spec jme_res_spec_mem[] = {
193 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE },
197 static struct resource_spec jme_irq_spec_legacy[] = {
198 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE },
202 static struct resource_spec jme_irq_spec_msi[] = {
203 { SYS_RES_IRQ, 1, RF_ACTIVE },
204 { SYS_RES_IRQ, 2, RF_ACTIVE },
205 { SYS_RES_IRQ, 3, RF_ACTIVE },
206 { SYS_RES_IRQ, 4, RF_ACTIVE },
207 { SYS_RES_IRQ, 5, RF_ACTIVE },
208 { SYS_RES_IRQ, 6, RF_ACTIVE },
209 { SYS_RES_IRQ, 7, RF_ACTIVE },
210 { SYS_RES_IRQ, 8, RF_ACTIVE },
215 * Read a PHY register on the MII of the JMC250.
218 jme_miibus_readreg(device_t dev, int phy, int reg)
220 struct jme_softc *sc;
224 sc = device_get_softc(dev);
226 /* For FPGA version, PHY address 0 should be ignored. */
227 if ((sc->jme_flags & JME_FLAG_FPGA) != 0) {
231 if (sc->jme_phyaddr != phy)
235 CSR_WRITE_4(sc, JME_SMI, SMI_OP_READ | SMI_OP_EXECUTE |
236 SMI_PHY_ADDR(phy) | SMI_REG_ADDR(reg));
237 for (i = JME_PHY_TIMEOUT; i > 0; i--) {
239 if (((val = CSR_READ_4(sc, JME_SMI)) & SMI_OP_EXECUTE) == 0)
244 device_printf(sc->jme_dev, "phy read timeout : %d\n", reg);
248 return ((val & SMI_DATA_MASK) >> SMI_DATA_SHIFT);
252 * Write a PHY register on the MII of the JMC250.
255 jme_miibus_writereg(device_t dev, int phy, int reg, int val)
257 struct jme_softc *sc;
260 sc = device_get_softc(dev);
262 /* For FPGA version, PHY address 0 should be ignored. */
263 if ((sc->jme_flags & JME_FLAG_FPGA) != 0) {
267 if (sc->jme_phyaddr != phy)
271 CSR_WRITE_4(sc, JME_SMI, SMI_OP_WRITE | SMI_OP_EXECUTE |
272 ((val << SMI_DATA_SHIFT) & SMI_DATA_MASK) |
273 SMI_PHY_ADDR(phy) | SMI_REG_ADDR(reg));
274 for (i = JME_PHY_TIMEOUT; i > 0; i--) {
276 if (((val = CSR_READ_4(sc, JME_SMI)) & SMI_OP_EXECUTE) == 0)
281 device_printf(sc->jme_dev, "phy write timeout : %d\n", reg);
287 * Callback from MII layer when media changes.
290 jme_miibus_statchg(device_t dev)
292 struct jme_softc *sc;
294 sc = device_get_softc(dev);
295 taskqueue_enqueue(taskqueue_swi, &sc->jme_link_task);
299 * Get the current interface media status.
302 jme_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr)
304 struct jme_softc *sc;
305 struct mii_data *mii;
309 if ((ifp->if_flags & IFF_UP) == 0) {
313 mii = device_get_softc(sc->jme_miibus);
316 ifmr->ifm_status = mii->mii_media_status;
317 ifmr->ifm_active = mii->mii_media_active;
322 * Set hardware to newly-selected media.
325 jme_mediachange(struct ifnet *ifp)
327 struct jme_softc *sc;
328 struct mii_data *mii;
329 struct mii_softc *miisc;
334 mii = device_get_softc(sc->jme_miibus);
335 if (mii->mii_instance != 0) {
336 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
337 mii_phy_reset(miisc);
339 error = mii_mediachg(mii);
346 jme_probe(device_t dev)
350 uint16_t vendor, devid;
352 vendor = pci_get_vendor(dev);
353 devid = pci_get_device(dev);
355 for (i = 0; i < sizeof(jme_devs) / sizeof(jme_devs[0]);
357 if (vendor == sp->jme_vendorid &&
358 devid == sp->jme_deviceid) {
359 device_set_desc(dev, sp->jme_name);
360 return (BUS_PROBE_DEFAULT);
368 jme_eeprom_read_byte(struct jme_softc *sc, uint8_t addr, uint8_t *val)
374 for (i = JME_TIMEOUT; i > 0; i--) {
375 reg = CSR_READ_4(sc, JME_SMBCSR);
376 if ((reg & SMBCSR_HW_BUSY_MASK) == SMBCSR_HW_IDLE)
382 device_printf(sc->jme_dev, "EEPROM idle timeout!\n");
386 reg = ((uint32_t)addr << SMBINTF_ADDR_SHIFT) & SMBINTF_ADDR_MASK;
387 CSR_WRITE_4(sc, JME_SMBINTF, reg | SMBINTF_RD | SMBINTF_CMD_TRIGGER);
388 for (i = JME_TIMEOUT; i > 0; i--) {
390 reg = CSR_READ_4(sc, JME_SMBINTF);
391 if ((reg & SMBINTF_CMD_TRIGGER) == 0)
396 device_printf(sc->jme_dev, "EEPROM read timeout!\n");
400 reg = CSR_READ_4(sc, JME_SMBINTF);
401 *val = (reg & SMBINTF_RD_DATA_MASK) >> SMBINTF_RD_DATA_SHIFT;
407 jme_eeprom_macaddr(struct jme_softc *sc)
409 uint8_t eaddr[ETHER_ADDR_LEN];
410 uint8_t fup, reg, val;
415 if (jme_eeprom_read_byte(sc, offset++, &fup) != 0 ||
416 fup != JME_EEPROM_SIG0)
418 if (jme_eeprom_read_byte(sc, offset++, &fup) != 0 ||
419 fup != JME_EEPROM_SIG1)
423 if (jme_eeprom_read_byte(sc, offset, &fup) != 0)
425 if (JME_EEPROM_MKDESC(JME_EEPROM_FUNC0, JME_EEPROM_PAGE_BAR1) ==
426 (fup & (JME_EEPROM_FUNC_MASK | JME_EEPROM_PAGE_MASK))) {
427 if (jme_eeprom_read_byte(sc, offset + 1, ®) != 0)
429 if (reg >= JME_PAR0 &&
430 reg < JME_PAR0 + ETHER_ADDR_LEN) {
431 if (jme_eeprom_read_byte(sc, offset + 2,
434 eaddr[reg - JME_PAR0] = val;
438 /* Check for the end of EEPROM descriptor. */
439 if ((fup & JME_EEPROM_DESC_END) == JME_EEPROM_DESC_END)
441 /* Try next eeprom descriptor. */
442 offset += JME_EEPROM_DESC_BYTES;
443 } while (match != ETHER_ADDR_LEN && offset < JME_EEPROM_END);
445 if (match == ETHER_ADDR_LEN) {
446 bcopy(eaddr, sc->jme_eaddr, ETHER_ADDR_LEN);
454 jme_reg_macaddr(struct jme_softc *sc)
458 /* Read station address. */
459 par0 = CSR_READ_4(sc, JME_PAR0);
460 par1 = CSR_READ_4(sc, JME_PAR1);
462 if ((par0 == 0 && par1 == 0) ||
463 (par0 == 0xFFFFFFFF && par1 == 0xFFFF)) {
464 device_printf(sc->jme_dev,
465 "generating fake ethernet address.\n");
467 /* Set OUI to JMicron. */
468 sc->jme_eaddr[0] = 0x02; /* U/L bit set. */
469 sc->jme_eaddr[1] = 0x1B;
470 sc->jme_eaddr[2] = 0x8C;
471 sc->jme_eaddr[3] = (par0 >> 16) & 0xff;
472 sc->jme_eaddr[4] = (par0 >> 8) & 0xff;
473 sc->jme_eaddr[5] = par0 & 0xff;
475 sc->jme_eaddr[0] = (par0 >> 0) & 0xFF;
476 sc->jme_eaddr[1] = (par0 >> 8) & 0xFF;
477 sc->jme_eaddr[2] = (par0 >> 16) & 0xFF;
478 sc->jme_eaddr[3] = (par0 >> 24) & 0xFF;
479 sc->jme_eaddr[4] = (par1 >> 0) & 0xFF;
480 sc->jme_eaddr[5] = (par1 >> 8) & 0xFF;
485 jme_map_intr_vector(struct jme_softc *sc)
487 uint32_t map[MSINUM_NUM_INTR_SOURCE / JME_MSI_MESSAGES];
489 bzero(map, sizeof(map));
491 /* Map Tx interrupts source to MSI/MSIX vector 2. */
492 map[MSINUM_REG_INDEX(N_INTR_TXQ0_COMP)] =
493 MSINUM_INTR_SOURCE(2, N_INTR_TXQ0_COMP);
494 map[MSINUM_REG_INDEX(N_INTR_TXQ1_COMP)] |=
495 MSINUM_INTR_SOURCE(2, N_INTR_TXQ1_COMP);
496 map[MSINUM_REG_INDEX(N_INTR_TXQ2_COMP)] |=
497 MSINUM_INTR_SOURCE(2, N_INTR_TXQ2_COMP);
498 map[MSINUM_REG_INDEX(N_INTR_TXQ3_COMP)] |=
499 MSINUM_INTR_SOURCE(2, N_INTR_TXQ3_COMP);
500 map[MSINUM_REG_INDEX(N_INTR_TXQ4_COMP)] |=
501 MSINUM_INTR_SOURCE(2, N_INTR_TXQ4_COMP);
502 map[MSINUM_REG_INDEX(N_INTR_TXQ4_COMP)] |=
503 MSINUM_INTR_SOURCE(2, N_INTR_TXQ5_COMP);
504 map[MSINUM_REG_INDEX(N_INTR_TXQ6_COMP)] |=
505 MSINUM_INTR_SOURCE(2, N_INTR_TXQ6_COMP);
506 map[MSINUM_REG_INDEX(N_INTR_TXQ7_COMP)] |=
507 MSINUM_INTR_SOURCE(2, N_INTR_TXQ7_COMP);
508 map[MSINUM_REG_INDEX(N_INTR_TXQ_COAL)] |=
509 MSINUM_INTR_SOURCE(2, N_INTR_TXQ_COAL);
510 map[MSINUM_REG_INDEX(N_INTR_TXQ_COAL_TO)] |=
511 MSINUM_INTR_SOURCE(2, N_INTR_TXQ_COAL_TO);
513 /* Map Rx interrupts source to MSI/MSIX vector 1. */
514 map[MSINUM_REG_INDEX(N_INTR_RXQ0_COMP)] =
515 MSINUM_INTR_SOURCE(1, N_INTR_RXQ0_COMP);
516 map[MSINUM_REG_INDEX(N_INTR_RXQ1_COMP)] =
517 MSINUM_INTR_SOURCE(1, N_INTR_RXQ1_COMP);
518 map[MSINUM_REG_INDEX(N_INTR_RXQ2_COMP)] =
519 MSINUM_INTR_SOURCE(1, N_INTR_RXQ2_COMP);
520 map[MSINUM_REG_INDEX(N_INTR_RXQ3_COMP)] =
521 MSINUM_INTR_SOURCE(1, N_INTR_RXQ3_COMP);
522 map[MSINUM_REG_INDEX(N_INTR_RXQ0_DESC_EMPTY)] =
523 MSINUM_INTR_SOURCE(1, N_INTR_RXQ0_DESC_EMPTY);
524 map[MSINUM_REG_INDEX(N_INTR_RXQ1_DESC_EMPTY)] =
525 MSINUM_INTR_SOURCE(1, N_INTR_RXQ1_DESC_EMPTY);
526 map[MSINUM_REG_INDEX(N_INTR_RXQ2_DESC_EMPTY)] =
527 MSINUM_INTR_SOURCE(1, N_INTR_RXQ2_DESC_EMPTY);
528 map[MSINUM_REG_INDEX(N_INTR_RXQ3_DESC_EMPTY)] =
529 MSINUM_INTR_SOURCE(1, N_INTR_RXQ3_DESC_EMPTY);
530 map[MSINUM_REG_INDEX(N_INTR_RXQ0_COAL)] =
531 MSINUM_INTR_SOURCE(1, N_INTR_RXQ0_COAL);
532 map[MSINUM_REG_INDEX(N_INTR_RXQ1_COAL)] =
533 MSINUM_INTR_SOURCE(1, N_INTR_RXQ1_COAL);
534 map[MSINUM_REG_INDEX(N_INTR_RXQ2_COAL)] =
535 MSINUM_INTR_SOURCE(1, N_INTR_RXQ2_COAL);
536 map[MSINUM_REG_INDEX(N_INTR_RXQ3_COAL)] =
537 MSINUM_INTR_SOURCE(1, N_INTR_RXQ3_COAL);
538 map[MSINUM_REG_INDEX(N_INTR_RXQ0_COAL_TO)] =
539 MSINUM_INTR_SOURCE(1, N_INTR_RXQ0_COAL_TO);
540 map[MSINUM_REG_INDEX(N_INTR_RXQ1_COAL_TO)] =
541 MSINUM_INTR_SOURCE(1, N_INTR_RXQ1_COAL_TO);
542 map[MSINUM_REG_INDEX(N_INTR_RXQ2_COAL_TO)] =
543 MSINUM_INTR_SOURCE(1, N_INTR_RXQ2_COAL_TO);
544 map[MSINUM_REG_INDEX(N_INTR_RXQ3_COAL_TO)] =
545 MSINUM_INTR_SOURCE(1, N_INTR_RXQ3_COAL_TO);
547 /* Map all other interrupts source to MSI/MSIX vector 0. */
548 CSR_WRITE_4(sc, JME_MSINUM_BASE + sizeof(uint32_t) * 0, map[0]);
549 CSR_WRITE_4(sc, JME_MSINUM_BASE + sizeof(uint32_t) * 1, map[1]);
550 CSR_WRITE_4(sc, JME_MSINUM_BASE + sizeof(uint32_t) * 2, map[2]);
551 CSR_WRITE_4(sc, JME_MSINUM_BASE + sizeof(uint32_t) * 3, map[3]);
555 jme_attach(device_t dev)
557 struct jme_softc *sc;
559 struct mii_softc *miisc;
560 struct mii_data *mii;
563 int error, i, msic, msixc, pmc;
566 sc = device_get_softc(dev);
569 mtx_init(&sc->jme_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
571 callout_init_mtx(&sc->jme_tick_ch, &sc->jme_mtx, 0);
572 TASK_INIT(&sc->jme_int_task, 0, jme_int_task, sc);
573 TASK_INIT(&sc->jme_link_task, 0, jme_link_task, sc);
576 * Map the device. JMC250 supports both memory mapped and I/O
577 * register space access. Because I/O register access should
578 * use different BARs to access registers it's waste of time
579 * to use I/O register spce access. JMC250 uses 16K to map
580 * entire memory space.
582 pci_enable_busmaster(dev);
583 sc->jme_res_spec = jme_res_spec_mem;
584 sc->jme_irq_spec = jme_irq_spec_legacy;
585 error = bus_alloc_resources(dev, sc->jme_res_spec, sc->jme_res);
587 device_printf(dev, "cannot allocate memory resources.\n");
591 /* Allocate IRQ resources. */
592 msixc = pci_msix_count(dev);
593 msic = pci_msi_count(dev);
595 device_printf(dev, "MSIX count : %d\n", msixc);
596 device_printf(dev, "MSI count : %d\n", msic);
599 /* Prefer MSIX over MSI. */
600 if (msix_disable == 0 || msi_disable == 0) {
601 if (msix_disable == 0 && msixc == JME_MSIX_MESSAGES &&
602 pci_alloc_msix(dev, &msixc) == 0) {
603 if (msic == JME_MSIX_MESSAGES) {
604 device_printf(dev, "Using %d MSIX messages.\n",
606 sc->jme_flags |= JME_FLAG_MSIX;
607 sc->jme_irq_spec = jme_irq_spec_msi;
609 pci_release_msi(dev);
611 if (msi_disable == 0 && (sc->jme_flags & JME_FLAG_MSIX) == 0 &&
612 msic == JME_MSI_MESSAGES &&
613 pci_alloc_msi(dev, &msic) == 0) {
614 if (msic == JME_MSI_MESSAGES) {
615 device_printf(dev, "Using %d MSI messages.\n",
617 sc->jme_flags |= JME_FLAG_MSI;
618 sc->jme_irq_spec = jme_irq_spec_msi;
620 pci_release_msi(dev);
622 /* Map interrupt vector 0, 1 and 2. */
623 if ((sc->jme_flags & JME_FLAG_MSI) != 0 ||
624 (sc->jme_flags & JME_FLAG_MSIX) != 0)
625 jme_map_intr_vector(sc);
628 error = bus_alloc_resources(dev, sc->jme_irq_spec, sc->jme_irq);
630 device_printf(dev, "cannot allocate IRQ resources.\n");
634 sc->jme_rev = pci_get_device(dev);
635 if ((sc->jme_rev & DEVICEID_JMC2XX_MASK) == DEVICEID_JMC260) {
636 sc->jme_flags |= JME_FLAG_FASTETH;
637 sc->jme_flags |= JME_FLAG_NOJUMBO;
639 reg = CSR_READ_4(sc, JME_CHIPMODE);
640 sc->jme_chip_rev = (reg & CHIPMODE_REV_MASK) >> CHIPMODE_REV_SHIFT;
641 if (((reg & CHIPMODE_FPGA_REV_MASK) >> CHIPMODE_FPGA_REV_SHIFT) !=
643 sc->jme_flags |= JME_FLAG_FPGA;
645 device_printf(dev, "PCI device revision : 0x%04x\n",
647 device_printf(dev, "Chip revision : 0x%02x\n",
649 if ((sc->jme_flags & JME_FLAG_FPGA) != 0)
650 device_printf(dev, "FPGA revision : 0x%04x\n",
651 (reg & CHIPMODE_FPGA_REV_MASK) >>
652 CHIPMODE_FPGA_REV_SHIFT);
654 if (sc->jme_chip_rev == 0xFF) {
655 device_printf(dev, "Unknown chip revision : 0x%02x\n",
661 if (CHIPMODE_REVFM(sc->jme_chip_rev) >= 2) {
662 if ((sc->jme_rev & DEVICEID_JMC2XX_MASK) == DEVICEID_JMC260 &&
663 CHIPMODE_REVFM(sc->jme_chip_rev) == 2)
664 sc->jme_flags |= JME_FLAG_DMA32BIT;
665 sc->jme_flags |= JME_FLAG_TXCLK;
666 sc->jme_flags |= JME_FLAG_HWMIB;
669 /* Reset the ethernet controller. */
672 /* Get station address. */
673 reg = CSR_READ_4(sc, JME_SMBCSR);
674 if ((reg & SMBCSR_EEPROM_PRESENT) != 0)
675 error = jme_eeprom_macaddr(sc);
676 if (error != 0 || (reg & SMBCSR_EEPROM_PRESENT) == 0) {
677 if (error != 0 && (bootverbose))
678 device_printf(sc->jme_dev,
679 "ethernet hardware address not found in EEPROM.\n");
685 * Integrated JR0211 has fixed PHY address whereas FPGA version
686 * requires PHY probing to get correct PHY address.
688 if ((sc->jme_flags & JME_FLAG_FPGA) == 0) {
689 sc->jme_phyaddr = CSR_READ_4(sc, JME_GPREG0) &
690 GPREG0_PHY_ADDR_MASK;
692 device_printf(dev, "PHY is at address %d.\n",
697 /* Set max allowable DMA size. */
698 if (pci_find_extcap(dev, PCIY_EXPRESS, &i) == 0) {
699 sc->jme_flags |= JME_FLAG_PCIE;
700 burst = pci_read_config(dev, i + 0x08, 2);
702 device_printf(dev, "Read request size : %d bytes.\n",
703 128 << ((burst >> 12) & 0x07));
704 device_printf(dev, "TLP payload size : %d bytes.\n",
705 128 << ((burst >> 5) & 0x07));
707 switch ((burst >> 12) & 0x07) {
709 sc->jme_tx_dma_size = TXCSR_DMA_SIZE_128;
712 sc->jme_tx_dma_size = TXCSR_DMA_SIZE_256;
715 sc->jme_tx_dma_size = TXCSR_DMA_SIZE_512;
718 sc->jme_rx_dma_size = RXCSR_DMA_SIZE_128;
720 sc->jme_tx_dma_size = TXCSR_DMA_SIZE_512;
721 sc->jme_rx_dma_size = RXCSR_DMA_SIZE_128;
723 /* Create coalescing sysctl node. */
725 if ((error = jme_dma_alloc(sc) != 0))
728 ifp = sc->jme_ifp = if_alloc(IFT_ETHER);
730 device_printf(dev, "cannot allocate ifnet structure.\n");
736 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
737 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
738 ifp->if_ioctl = jme_ioctl;
739 ifp->if_start = jme_start;
740 ifp->if_init = jme_init;
741 ifp->if_snd.ifq_drv_maxlen = JME_TX_RING_CNT - 1;
742 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen);
743 IFQ_SET_READY(&ifp->if_snd);
744 /* JMC250 supports Tx/Rx checksum offload as well as TSO. */
745 ifp->if_capabilities = IFCAP_HWCSUM | IFCAP_TSO4;
746 ifp->if_hwassist = JME_CSUM_FEATURES | CSUM_TSO;
747 if (pci_find_extcap(dev, PCIY_PMG, &pmc) == 0) {
748 sc->jme_flags |= JME_FLAG_PMCAP;
749 ifp->if_capabilities |= IFCAP_WOL_MAGIC;
751 ifp->if_capenable = ifp->if_capabilities;
753 /* Set up MII bus. */
754 if ((error = mii_phy_probe(dev, &sc->jme_miibus, jme_mediachange,
755 jme_mediastatus)) != 0) {
756 device_printf(dev, "no PHY found!\n");
761 * Force PHY to FPGA mode.
763 if ((sc->jme_flags & JME_FLAG_FPGA) != 0) {
764 mii = device_get_softc(sc->jme_miibus);
765 if (mii->mii_instance != 0) {
766 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) {
767 if (miisc->mii_phy != 0) {
768 sc->jme_phyaddr = miisc->mii_phy;
772 if (sc->jme_phyaddr != 0) {
773 device_printf(sc->jme_dev,
774 "FPGA PHY is at %d\n", sc->jme_phyaddr);
776 jme_miibus_writereg(dev, sc->jme_phyaddr, 27,
782 ether_ifattach(ifp, sc->jme_eaddr);
784 /* VLAN capability setup */
785 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING |
786 IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWTSO;
787 ifp->if_capenable = ifp->if_capabilities;
789 /* Tell the upper layer(s) we support long frames. */
790 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
792 /* Create local taskq. */
793 TASK_INIT(&sc->jme_tx_task, 1, jme_tx_task, ifp);
794 sc->jme_tq = taskqueue_create_fast("jme_taskq", M_WAITOK,
795 taskqueue_thread_enqueue, &sc->jme_tq);
796 if (sc->jme_tq == NULL) {
797 device_printf(dev, "could not create taskqueue.\n");
802 taskqueue_start_threads(&sc->jme_tq, 1, PI_NET, "%s taskq",
803 device_get_nameunit(sc->jme_dev));
805 if ((sc->jme_flags & JME_FLAG_MSIX) != 0)
806 msic = JME_MSIX_MESSAGES;
807 else if ((sc->jme_flags & JME_FLAG_MSI) != 0)
808 msic = JME_MSI_MESSAGES;
811 for (i = 0; i < msic; i++) {
812 error = bus_setup_intr(dev, sc->jme_irq[i],
813 INTR_TYPE_NET | INTR_MPSAFE, jme_intr, NULL, sc,
814 &sc->jme_intrhand[i]);
820 device_printf(dev, "could not set up interrupt handler.\n");
821 taskqueue_free(sc->jme_tq);
835 jme_detach(device_t dev)
837 struct jme_softc *sc;
841 sc = device_get_softc(dev);
844 if (device_is_attached(dev)) {
846 sc->jme_flags |= JME_FLAG_DETACH;
849 callout_drain(&sc->jme_tick_ch);
850 taskqueue_drain(sc->jme_tq, &sc->jme_int_task);
851 taskqueue_drain(sc->jme_tq, &sc->jme_tx_task);
852 taskqueue_drain(taskqueue_swi, &sc->jme_link_task);
856 if (sc->jme_tq != NULL) {
857 taskqueue_drain(sc->jme_tq, &sc->jme_int_task);
858 taskqueue_free(sc->jme_tq);
862 if (sc->jme_miibus != NULL) {
863 device_delete_child(dev, sc->jme_miibus);
864 sc->jme_miibus = NULL;
866 bus_generic_detach(dev);
875 if ((sc->jme_flags & JME_FLAG_MSIX) != 0)
876 msic = JME_MSIX_MESSAGES;
877 else if ((sc->jme_flags & JME_FLAG_MSI) != 0)
878 msic = JME_MSI_MESSAGES;
881 for (i = 0; i < msic; i++) {
882 if (sc->jme_intrhand[i] != NULL) {
883 bus_teardown_intr(dev, sc->jme_irq[i],
884 sc->jme_intrhand[i]);
885 sc->jme_intrhand[i] = NULL;
889 bus_release_resources(dev, sc->jme_irq_spec, sc->jme_irq);
890 if ((sc->jme_flags & (JME_FLAG_MSIX | JME_FLAG_MSI)) != 0)
891 pci_release_msi(dev);
892 bus_release_resources(dev, sc->jme_res_spec, sc->jme_res);
893 mtx_destroy(&sc->jme_mtx);
898 #define JME_SYSCTL_STAT_ADD32(c, h, n, p, d) \
899 SYSCTL_ADD_UINT(c, h, OID_AUTO, n, CTLFLAG_RD, p, 0, d)
902 jme_sysctl_node(struct jme_softc *sc)
904 struct sysctl_ctx_list *ctx;
905 struct sysctl_oid_list *child, *parent;
906 struct sysctl_oid *tree;
907 struct jme_hw_stats *stats;
910 stats = &sc->jme_stats;
911 ctx = device_get_sysctl_ctx(sc->jme_dev);
912 child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->jme_dev));
914 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "tx_coal_to",
915 CTLTYPE_INT | CTLFLAG_RW, &sc->jme_tx_coal_to, 0,
916 sysctl_hw_jme_tx_coal_to, "I", "jme tx coalescing timeout");
918 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "tx_coal_pkt",
919 CTLTYPE_INT | CTLFLAG_RW, &sc->jme_tx_coal_pkt, 0,
920 sysctl_hw_jme_tx_coal_pkt, "I", "jme tx coalescing packet");
922 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "rx_coal_to",
923 CTLTYPE_INT | CTLFLAG_RW, &sc->jme_rx_coal_to, 0,
924 sysctl_hw_jme_rx_coal_to, "I", "jme rx coalescing timeout");
926 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "rx_coal_pkt",
927 CTLTYPE_INT | CTLFLAG_RW, &sc->jme_rx_coal_pkt, 0,
928 sysctl_hw_jme_rx_coal_pkt, "I", "jme rx coalescing packet");
930 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "process_limit",
931 CTLTYPE_INT | CTLFLAG_RW, &sc->jme_process_limit, 0,
932 sysctl_hw_jme_proc_limit, "I",
933 "max number of Rx events to process");
935 /* Pull in device tunables. */
936 sc->jme_process_limit = JME_PROC_DEFAULT;
937 error = resource_int_value(device_get_name(sc->jme_dev),
938 device_get_unit(sc->jme_dev), "process_limit",
939 &sc->jme_process_limit);
941 if (sc->jme_process_limit < JME_PROC_MIN ||
942 sc->jme_process_limit > JME_PROC_MAX) {
943 device_printf(sc->jme_dev,
944 "process_limit value out of range; "
945 "using default: %d\n", JME_PROC_DEFAULT);
946 sc->jme_process_limit = JME_PROC_DEFAULT;
950 sc->jme_tx_coal_to = PCCTX_COAL_TO_DEFAULT;
951 error = resource_int_value(device_get_name(sc->jme_dev),
952 device_get_unit(sc->jme_dev), "tx_coal_to", &sc->jme_tx_coal_to);
954 if (sc->jme_tx_coal_to < PCCTX_COAL_TO_MIN ||
955 sc->jme_tx_coal_to > PCCTX_COAL_TO_MAX) {
956 device_printf(sc->jme_dev,
957 "tx_coal_to value out of range; "
958 "using default: %d\n", PCCTX_COAL_TO_DEFAULT);
959 sc->jme_tx_coal_to = PCCTX_COAL_TO_DEFAULT;
963 sc->jme_tx_coal_pkt = PCCTX_COAL_PKT_DEFAULT;
964 error = resource_int_value(device_get_name(sc->jme_dev),
965 device_get_unit(sc->jme_dev), "tx_coal_pkt", &sc->jme_tx_coal_to);
967 if (sc->jme_tx_coal_pkt < PCCTX_COAL_PKT_MIN ||
968 sc->jme_tx_coal_pkt > PCCTX_COAL_PKT_MAX) {
969 device_printf(sc->jme_dev,
970 "tx_coal_pkt value out of range; "
971 "using default: %d\n", PCCTX_COAL_PKT_DEFAULT);
972 sc->jme_tx_coal_pkt = PCCTX_COAL_PKT_DEFAULT;
976 sc->jme_rx_coal_to = PCCRX_COAL_TO_DEFAULT;
977 error = resource_int_value(device_get_name(sc->jme_dev),
978 device_get_unit(sc->jme_dev), "rx_coal_to", &sc->jme_rx_coal_to);
980 if (sc->jme_rx_coal_to < PCCRX_COAL_TO_MIN ||
981 sc->jme_rx_coal_to > PCCRX_COAL_TO_MAX) {
982 device_printf(sc->jme_dev,
983 "rx_coal_to value out of range; "
984 "using default: %d\n", PCCRX_COAL_TO_DEFAULT);
985 sc->jme_rx_coal_to = PCCRX_COAL_TO_DEFAULT;
989 sc->jme_rx_coal_pkt = PCCRX_COAL_PKT_DEFAULT;
990 error = resource_int_value(device_get_name(sc->jme_dev),
991 device_get_unit(sc->jme_dev), "rx_coal_pkt", &sc->jme_rx_coal_to);
993 if (sc->jme_rx_coal_pkt < PCCRX_COAL_PKT_MIN ||
994 sc->jme_rx_coal_pkt > PCCRX_COAL_PKT_MAX) {
995 device_printf(sc->jme_dev,
996 "tx_coal_pkt value out of range; "
997 "using default: %d\n", PCCRX_COAL_PKT_DEFAULT);
998 sc->jme_rx_coal_pkt = PCCRX_COAL_PKT_DEFAULT;
1002 if ((sc->jme_flags & JME_FLAG_HWMIB) == 0)
1005 tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats", CTLFLAG_RD,
1006 NULL, "JME statistics");
1007 parent = SYSCTL_CHILDREN(tree);
1009 /* Rx statistics. */
1010 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "rx", CTLFLAG_RD,
1011 NULL, "Rx MAC statistics");
1012 child = SYSCTL_CHILDREN(tree);
1013 JME_SYSCTL_STAT_ADD32(ctx, child, "good_frames",
1014 &stats->rx_good_frames, "Good frames");
1015 JME_SYSCTL_STAT_ADD32(ctx, child, "crc_errs",
1016 &stats->rx_crc_errs, "CRC errors");
1017 JME_SYSCTL_STAT_ADD32(ctx, child, "mii_errs",
1018 &stats->rx_mii_errs, "MII errors");
1019 JME_SYSCTL_STAT_ADD32(ctx, child, "fifo_oflows",
1020 &stats->rx_fifo_oflows, "FIFO overflows");
1021 JME_SYSCTL_STAT_ADD32(ctx, child, "desc_empty",
1022 &stats->rx_desc_empty, "Descriptor empty");
1023 JME_SYSCTL_STAT_ADD32(ctx, child, "bad_frames",
1024 &stats->rx_bad_frames, "Bad frames");
1026 /* Tx statistics. */
1027 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "tx", CTLFLAG_RD,
1028 NULL, "Tx MAC statistics");
1029 child = SYSCTL_CHILDREN(tree);
1030 JME_SYSCTL_STAT_ADD32(ctx, child, "good_frames",
1031 &stats->tx_good_frames, "Good frames");
1032 JME_SYSCTL_STAT_ADD32(ctx, child, "bad_frames",
1033 &stats->tx_bad_frames, "Bad frames");
1036 #undef JME_SYSCTL_STAT_ADD32
1038 struct jme_dmamap_arg {
1039 bus_addr_t jme_busaddr;
1043 jme_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
1045 struct jme_dmamap_arg *ctx;
1050 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
1052 ctx = (struct jme_dmamap_arg *)arg;
1053 ctx->jme_busaddr = segs[0].ds_addr;
1057 jme_dma_alloc(struct jme_softc *sc)
1059 struct jme_dmamap_arg ctx;
1060 struct jme_txdesc *txd;
1061 struct jme_rxdesc *rxd;
1062 bus_addr_t lowaddr, rx_ring_end, tx_ring_end;
1065 lowaddr = BUS_SPACE_MAXADDR;
1066 if ((sc->jme_flags & JME_FLAG_DMA32BIT) != 0)
1067 lowaddr = BUS_SPACE_MAXADDR_32BIT;
1070 /* Create parent ring tag. */
1071 error = bus_dma_tag_create(bus_get_dma_tag(sc->jme_dev),/* parent */
1072 1, 0, /* algnmnt, boundary */
1073 lowaddr, /* lowaddr */
1074 BUS_SPACE_MAXADDR, /* highaddr */
1075 NULL, NULL, /* filter, filterarg */
1076 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */
1078 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */
1080 NULL, NULL, /* lockfunc, lockarg */
1081 &sc->jme_cdata.jme_ring_tag);
1083 device_printf(sc->jme_dev,
1084 "could not create parent ring DMA tag.\n");
1087 /* Create tag for Tx ring. */
1088 error = bus_dma_tag_create(sc->jme_cdata.jme_ring_tag,/* parent */
1089 JME_TX_RING_ALIGN, 0, /* algnmnt, boundary */
1090 BUS_SPACE_MAXADDR, /* lowaddr */
1091 BUS_SPACE_MAXADDR, /* highaddr */
1092 NULL, NULL, /* filter, filterarg */
1093 JME_TX_RING_SIZE, /* maxsize */
1095 JME_TX_RING_SIZE, /* maxsegsize */
1097 NULL, NULL, /* lockfunc, lockarg */
1098 &sc->jme_cdata.jme_tx_ring_tag);
1100 device_printf(sc->jme_dev,
1101 "could not allocate Tx ring DMA tag.\n");
1105 /* Create tag for Rx ring. */
1106 error = bus_dma_tag_create(sc->jme_cdata.jme_ring_tag,/* parent */
1107 JME_RX_RING_ALIGN, 0, /* algnmnt, boundary */
1108 lowaddr, /* lowaddr */
1109 BUS_SPACE_MAXADDR, /* highaddr */
1110 NULL, NULL, /* filter, filterarg */
1111 JME_RX_RING_SIZE, /* maxsize */
1113 JME_RX_RING_SIZE, /* maxsegsize */
1115 NULL, NULL, /* lockfunc, lockarg */
1116 &sc->jme_cdata.jme_rx_ring_tag);
1118 device_printf(sc->jme_dev,
1119 "could not allocate Rx ring DMA tag.\n");
1123 /* Allocate DMA'able memory and load the DMA map for Tx ring. */
1124 error = bus_dmamem_alloc(sc->jme_cdata.jme_tx_ring_tag,
1125 (void **)&sc->jme_rdata.jme_tx_ring,
1126 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT,
1127 &sc->jme_cdata.jme_tx_ring_map);
1129 device_printf(sc->jme_dev,
1130 "could not allocate DMA'able memory for Tx ring.\n");
1134 ctx.jme_busaddr = 0;
1135 error = bus_dmamap_load(sc->jme_cdata.jme_tx_ring_tag,
1136 sc->jme_cdata.jme_tx_ring_map, sc->jme_rdata.jme_tx_ring,
1137 JME_TX_RING_SIZE, jme_dmamap_cb, &ctx, BUS_DMA_NOWAIT);
1138 if (error != 0 || ctx.jme_busaddr == 0) {
1139 device_printf(sc->jme_dev,
1140 "could not load DMA'able memory for Tx ring.\n");
1143 sc->jme_rdata.jme_tx_ring_paddr = ctx.jme_busaddr;
1145 /* Allocate DMA'able memory and load the DMA map for Rx ring. */
1146 error = bus_dmamem_alloc(sc->jme_cdata.jme_rx_ring_tag,
1147 (void **)&sc->jme_rdata.jme_rx_ring,
1148 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT,
1149 &sc->jme_cdata.jme_rx_ring_map);
1151 device_printf(sc->jme_dev,
1152 "could not allocate DMA'able memory for Rx ring.\n");
1156 ctx.jme_busaddr = 0;
1157 error = bus_dmamap_load(sc->jme_cdata.jme_rx_ring_tag,
1158 sc->jme_cdata.jme_rx_ring_map, sc->jme_rdata.jme_rx_ring,
1159 JME_RX_RING_SIZE, jme_dmamap_cb, &ctx, BUS_DMA_NOWAIT);
1160 if (error != 0 || ctx.jme_busaddr == 0) {
1161 device_printf(sc->jme_dev,
1162 "could not load DMA'able memory for Rx ring.\n");
1165 sc->jme_rdata.jme_rx_ring_paddr = ctx.jme_busaddr;
1167 if (lowaddr != BUS_SPACE_MAXADDR_32BIT) {
1168 /* Tx/Rx descriptor queue should reside within 4GB boundary. */
1169 tx_ring_end = sc->jme_rdata.jme_tx_ring_paddr +
1171 rx_ring_end = sc->jme_rdata.jme_rx_ring_paddr +
1173 if ((JME_ADDR_HI(tx_ring_end) !=
1174 JME_ADDR_HI(sc->jme_rdata.jme_tx_ring_paddr)) ||
1175 (JME_ADDR_HI(rx_ring_end) !=
1176 JME_ADDR_HI(sc->jme_rdata.jme_rx_ring_paddr))) {
1177 device_printf(sc->jme_dev, "4GB boundary crossed, "
1178 "switching to 32bit DMA address mode.\n");
1180 /* Limit DMA address space to 32bit and try again. */
1181 lowaddr = BUS_SPACE_MAXADDR_32BIT;
1186 lowaddr = BUS_SPACE_MAXADDR;
1187 if ((sc->jme_flags & JME_FLAG_DMA32BIT) != 0)
1188 lowaddr = BUS_SPACE_MAXADDR_32BIT;
1189 /* Create parent buffer tag. */
1190 error = bus_dma_tag_create(bus_get_dma_tag(sc->jme_dev),/* parent */
1191 1, 0, /* algnmnt, boundary */
1192 lowaddr, /* lowaddr */
1193 BUS_SPACE_MAXADDR, /* highaddr */
1194 NULL, NULL, /* filter, filterarg */
1195 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */
1197 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */
1199 NULL, NULL, /* lockfunc, lockarg */
1200 &sc->jme_cdata.jme_buffer_tag);
1202 device_printf(sc->jme_dev,
1203 "could not create parent buffer DMA tag.\n");
1207 /* Create shadow status block tag. */
1208 error = bus_dma_tag_create(sc->jme_cdata.jme_buffer_tag,/* parent */
1209 JME_SSB_ALIGN, 0, /* algnmnt, boundary */
1210 BUS_SPACE_MAXADDR, /* lowaddr */
1211 BUS_SPACE_MAXADDR, /* highaddr */
1212 NULL, NULL, /* filter, filterarg */
1213 JME_SSB_SIZE, /* maxsize */
1215 JME_SSB_SIZE, /* maxsegsize */
1217 NULL, NULL, /* lockfunc, lockarg */
1218 &sc->jme_cdata.jme_ssb_tag);
1220 device_printf(sc->jme_dev,
1221 "could not create shared status block DMA tag.\n");
1225 /* Create tag for Tx buffers. */
1226 error = bus_dma_tag_create(sc->jme_cdata.jme_buffer_tag,/* parent */
1227 1, 0, /* algnmnt, boundary */
1228 BUS_SPACE_MAXADDR, /* lowaddr */
1229 BUS_SPACE_MAXADDR, /* highaddr */
1230 NULL, NULL, /* filter, filterarg */
1231 JME_TSO_MAXSIZE, /* maxsize */
1232 JME_MAXTXSEGS, /* nsegments */
1233 JME_TSO_MAXSEGSIZE, /* maxsegsize */
1235 NULL, NULL, /* lockfunc, lockarg */
1236 &sc->jme_cdata.jme_tx_tag);
1238 device_printf(sc->jme_dev, "could not create Tx DMA tag.\n");
1242 /* Create tag for Rx buffers. */
1243 error = bus_dma_tag_create(sc->jme_cdata.jme_buffer_tag,/* parent */
1244 JME_RX_BUF_ALIGN, 0, /* algnmnt, boundary */
1245 BUS_SPACE_MAXADDR, /* lowaddr */
1246 BUS_SPACE_MAXADDR, /* highaddr */
1247 NULL, NULL, /* filter, filterarg */
1248 MCLBYTES, /* maxsize */
1250 MCLBYTES, /* maxsegsize */
1252 NULL, NULL, /* lockfunc, lockarg */
1253 &sc->jme_cdata.jme_rx_tag);
1255 device_printf(sc->jme_dev, "could not create Rx DMA tag.\n");
1260 * Allocate DMA'able memory and load the DMA map for shared
1263 error = bus_dmamem_alloc(sc->jme_cdata.jme_ssb_tag,
1264 (void **)&sc->jme_rdata.jme_ssb_block,
1265 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT,
1266 &sc->jme_cdata.jme_ssb_map);
1268 device_printf(sc->jme_dev, "could not allocate DMA'able "
1269 "memory for shared status block.\n");
1273 ctx.jme_busaddr = 0;
1274 error = bus_dmamap_load(sc->jme_cdata.jme_ssb_tag,
1275 sc->jme_cdata.jme_ssb_map, sc->jme_rdata.jme_ssb_block,
1276 JME_SSB_SIZE, jme_dmamap_cb, &ctx, BUS_DMA_NOWAIT);
1277 if (error != 0 || ctx.jme_busaddr == 0) {
1278 device_printf(sc->jme_dev, "could not load DMA'able memory "
1279 "for shared status block.\n");
1282 sc->jme_rdata.jme_ssb_block_paddr = ctx.jme_busaddr;
1284 /* Create DMA maps for Tx buffers. */
1285 for (i = 0; i < JME_TX_RING_CNT; i++) {
1286 txd = &sc->jme_cdata.jme_txdesc[i];
1288 txd->tx_dmamap = NULL;
1289 error = bus_dmamap_create(sc->jme_cdata.jme_tx_tag, 0,
1292 device_printf(sc->jme_dev,
1293 "could not create Tx dmamap.\n");
1297 /* Create DMA maps for Rx buffers. */
1298 if ((error = bus_dmamap_create(sc->jme_cdata.jme_rx_tag, 0,
1299 &sc->jme_cdata.jme_rx_sparemap)) != 0) {
1300 device_printf(sc->jme_dev,
1301 "could not create spare Rx dmamap.\n");
1304 for (i = 0; i < JME_RX_RING_CNT; i++) {
1305 rxd = &sc->jme_cdata.jme_rxdesc[i];
1307 rxd->rx_dmamap = NULL;
1308 error = bus_dmamap_create(sc->jme_cdata.jme_rx_tag, 0,
1311 device_printf(sc->jme_dev,
1312 "could not create Rx dmamap.\n");
1322 jme_dma_free(struct jme_softc *sc)
1324 struct jme_txdesc *txd;
1325 struct jme_rxdesc *rxd;
1329 if (sc->jme_cdata.jme_tx_ring_tag != NULL) {
1330 if (sc->jme_cdata.jme_tx_ring_map)
1331 bus_dmamap_unload(sc->jme_cdata.jme_tx_ring_tag,
1332 sc->jme_cdata.jme_tx_ring_map);
1333 if (sc->jme_cdata.jme_tx_ring_map &&
1334 sc->jme_rdata.jme_tx_ring)
1335 bus_dmamem_free(sc->jme_cdata.jme_tx_ring_tag,
1336 sc->jme_rdata.jme_tx_ring,
1337 sc->jme_cdata.jme_tx_ring_map);
1338 sc->jme_rdata.jme_tx_ring = NULL;
1339 sc->jme_cdata.jme_tx_ring_map = NULL;
1340 bus_dma_tag_destroy(sc->jme_cdata.jme_tx_ring_tag);
1341 sc->jme_cdata.jme_tx_ring_tag = NULL;
1344 if (sc->jme_cdata.jme_rx_ring_tag != NULL) {
1345 if (sc->jme_cdata.jme_rx_ring_map)
1346 bus_dmamap_unload(sc->jme_cdata.jme_rx_ring_tag,
1347 sc->jme_cdata.jme_rx_ring_map);
1348 if (sc->jme_cdata.jme_rx_ring_map &&
1349 sc->jme_rdata.jme_rx_ring)
1350 bus_dmamem_free(sc->jme_cdata.jme_rx_ring_tag,
1351 sc->jme_rdata.jme_rx_ring,
1352 sc->jme_cdata.jme_rx_ring_map);
1353 sc->jme_rdata.jme_rx_ring = NULL;
1354 sc->jme_cdata.jme_rx_ring_map = NULL;
1355 bus_dma_tag_destroy(sc->jme_cdata.jme_rx_ring_tag);
1356 sc->jme_cdata.jme_rx_ring_tag = NULL;
1359 if (sc->jme_cdata.jme_tx_tag != NULL) {
1360 for (i = 0; i < JME_TX_RING_CNT; i++) {
1361 txd = &sc->jme_cdata.jme_txdesc[i];
1362 if (txd->tx_dmamap != NULL) {
1363 bus_dmamap_destroy(sc->jme_cdata.jme_tx_tag,
1365 txd->tx_dmamap = NULL;
1368 bus_dma_tag_destroy(sc->jme_cdata.jme_tx_tag);
1369 sc->jme_cdata.jme_tx_tag = NULL;
1372 if (sc->jme_cdata.jme_rx_tag != NULL) {
1373 for (i = 0; i < JME_RX_RING_CNT; i++) {
1374 rxd = &sc->jme_cdata.jme_rxdesc[i];
1375 if (rxd->rx_dmamap != NULL) {
1376 bus_dmamap_destroy(sc->jme_cdata.jme_rx_tag,
1378 rxd->rx_dmamap = NULL;
1381 if (sc->jme_cdata.jme_rx_sparemap != NULL) {
1382 bus_dmamap_destroy(sc->jme_cdata.jme_rx_tag,
1383 sc->jme_cdata.jme_rx_sparemap);
1384 sc->jme_cdata.jme_rx_sparemap = NULL;
1386 bus_dma_tag_destroy(sc->jme_cdata.jme_rx_tag);
1387 sc->jme_cdata.jme_rx_tag = NULL;
1390 /* Shared status block. */
1391 if (sc->jme_cdata.jme_ssb_tag != NULL) {
1392 if (sc->jme_cdata.jme_ssb_map)
1393 bus_dmamap_unload(sc->jme_cdata.jme_ssb_tag,
1394 sc->jme_cdata.jme_ssb_map);
1395 if (sc->jme_cdata.jme_ssb_map && sc->jme_rdata.jme_ssb_block)
1396 bus_dmamem_free(sc->jme_cdata.jme_ssb_tag,
1397 sc->jme_rdata.jme_ssb_block,
1398 sc->jme_cdata.jme_ssb_map);
1399 sc->jme_rdata.jme_ssb_block = NULL;
1400 sc->jme_cdata.jme_ssb_map = NULL;
1401 bus_dma_tag_destroy(sc->jme_cdata.jme_ssb_tag);
1402 sc->jme_cdata.jme_ssb_tag = NULL;
1405 if (sc->jme_cdata.jme_buffer_tag != NULL) {
1406 bus_dma_tag_destroy(sc->jme_cdata.jme_buffer_tag);
1407 sc->jme_cdata.jme_buffer_tag = NULL;
1409 if (sc->jme_cdata.jme_ring_tag != NULL) {
1410 bus_dma_tag_destroy(sc->jme_cdata.jme_ring_tag);
1411 sc->jme_cdata.jme_ring_tag = NULL;
1416 * Make sure the interface is stopped at reboot time.
1419 jme_shutdown(device_t dev)
1422 return (jme_suspend(dev));
1426 * Unlike other ethernet controllers, JMC250 requires
1427 * explicit resetting link speed to 10/100Mbps as gigabit
1428 * link will cunsume more power than 375mA.
1429 * Note, we reset the link speed to 10/100Mbps with
1430 * auto-negotiation but we don't know whether that operation
1431 * would succeed or not as we have no control after powering
1432 * off. If the renegotiation fail WOL may not work. Running
1433 * at 1Gbps draws more power than 375mA at 3.3V which is
1434 * specified in PCI specification and that would result in
1435 * complete shutdowning power to ethernet controller.
1438 * Save current negotiated media speed/duplex/flow-control
1439 * to softc and restore the same link again after resuming.
1440 * PHY handling such as power down/resetting to 100Mbps
1441 * may be better handled in suspend method in phy driver.
1444 jme_setlinkspeed(struct jme_softc *sc)
1446 struct mii_data *mii;
1449 JME_LOCK_ASSERT(sc);
1451 mii = device_get_softc(sc->jme_miibus);
1454 if ((mii->mii_media_status & IFM_AVALID) != 0) {
1455 switch IFM_SUBTYPE(mii->mii_media_active) {
1465 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, MII_100T2CR, 0);
1466 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, MII_ANAR,
1467 ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10 | ANAR_CSMA);
1468 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, MII_BMCR,
1469 BMCR_AUTOEN | BMCR_STARTNEG);
1472 /* Poll link state until jme(4) get a 10/100 link. */
1473 for (i = 0; i < MII_ANEGTICKS_GIGE; i++) {
1475 if ((mii->mii_media_status & IFM_AVALID) != 0) {
1476 switch (IFM_SUBTYPE(mii->mii_media_active)) {
1486 pause("jmelnk", hz);
1489 if (i == MII_ANEGTICKS_GIGE)
1490 device_printf(sc->jme_dev, "establishing link failed, "
1491 "WOL may not work!");
1494 * No link, force MAC to have 100Mbps, full-duplex link.
1495 * This is the last resort and may/may not work.
1497 mii->mii_media_status = IFM_AVALID | IFM_ACTIVE;
1498 mii->mii_media_active = IFM_ETHER | IFM_100_TX | IFM_FDX;
1503 jme_setwol(struct jme_softc *sc)
1510 JME_LOCK_ASSERT(sc);
1512 if (pci_find_extcap(sc->jme_dev, PCIY_PMG, &pmc) != 0) {
1513 /* Remove Tx MAC/offload clock to save more power. */
1514 if ((sc->jme_flags & JME_FLAG_TXCLK) != 0)
1515 CSR_WRITE_4(sc, JME_GHC, CSR_READ_4(sc, JME_GHC) &
1516 ~(GHC_TX_OFFLD_CLK_100 | GHC_TX_MAC_CLK_100 |
1517 GHC_TX_OFFLD_CLK_1000 | GHC_TX_MAC_CLK_1000));
1518 /* No PME capability, PHY power down. */
1519 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr,
1520 MII_BMCR, BMCR_PDOWN);
1525 gpr = CSR_READ_4(sc, JME_GPREG0) & ~GPREG0_PME_ENB;
1526 pmcs = CSR_READ_4(sc, JME_PMCS);
1527 pmcs &= ~PMCS_WOL_ENB_MASK;
1528 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) {
1529 pmcs |= PMCS_MAGIC_FRAME | PMCS_MAGIC_FRAME_ENB;
1530 /* Enable PME message. */
1531 gpr |= GPREG0_PME_ENB;
1532 /* For gigabit controllers, reset link speed to 10/100. */
1533 if ((sc->jme_flags & JME_FLAG_FASTETH) == 0)
1534 jme_setlinkspeed(sc);
1537 CSR_WRITE_4(sc, JME_PMCS, pmcs);
1538 CSR_WRITE_4(sc, JME_GPREG0, gpr);
1539 /* Remove Tx MAC/offload clock to save more power. */
1540 if ((sc->jme_flags & JME_FLAG_TXCLK) != 0)
1541 CSR_WRITE_4(sc, JME_GHC, CSR_READ_4(sc, JME_GHC) &
1542 ~(GHC_TX_OFFLD_CLK_100 | GHC_TX_MAC_CLK_100 |
1543 GHC_TX_OFFLD_CLK_1000 | GHC_TX_MAC_CLK_1000));
1545 pmstat = pci_read_config(sc->jme_dev, pmc + PCIR_POWER_STATUS, 2);
1546 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE);
1547 if ((ifp->if_capenable & IFCAP_WOL) != 0)
1548 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
1549 pci_write_config(sc->jme_dev, pmc + PCIR_POWER_STATUS, pmstat, 2);
1550 if ((ifp->if_capenable & IFCAP_WOL) == 0) {
1551 /* No WOL, PHY power down. */
1552 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr,
1553 MII_BMCR, BMCR_PDOWN);
1558 jme_suspend(device_t dev)
1560 struct jme_softc *sc;
1562 sc = device_get_softc(dev);
1573 jme_resume(device_t dev)
1575 struct jme_softc *sc;
1580 sc = device_get_softc(dev);
1583 if (pci_find_extcap(sc->jme_dev, PCIY_PMG, &pmc) != 0) {
1584 pmstat = pci_read_config(sc->jme_dev,
1585 pmc + PCIR_POWER_STATUS, 2);
1586 /* Disable PME clear PME status. */
1587 pmstat &= ~PCIM_PSTAT_PMEENABLE;
1588 pci_write_config(sc->jme_dev,
1589 pmc + PCIR_POWER_STATUS, pmstat, 2);
1592 if ((ifp->if_flags & IFF_UP) != 0) {
1593 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1594 jme_init_locked(sc);
1603 jme_encap(struct jme_softc *sc, struct mbuf **m_head)
1605 struct jme_txdesc *txd;
1606 struct jme_desc *desc;
1608 bus_dma_segment_t txsegs[JME_MAXTXSEGS];
1609 int error, i, nsegs, prod;
1610 uint32_t cflags, tso_segsz;
1612 JME_LOCK_ASSERT(sc);
1614 M_ASSERTPKTHDR((*m_head));
1616 if (((*m_head)->m_pkthdr.csum_flags & CSUM_TSO) != 0) {
1618 * Due to the adherence to NDIS specification JMC250
1619 * assumes upper stack computed TCP pseudo checksum
1620 * without including payload length. This breaks
1621 * checksum offload for TSO case so recompute TCP
1622 * pseudo checksum for JMC250. Hopefully this wouldn't
1623 * be much burden on modern CPUs.
1625 struct ether_header *eh;
1628 uint32_t ip_off, poff;
1630 if (M_WRITABLE(*m_head) == 0) {
1631 /* Get a writable copy. */
1632 m = m_dup(*m_head, M_DONTWAIT);
1640 ip_off = sizeof(struct ether_header);
1641 m = m_pullup(*m_head, ip_off);
1646 eh = mtod(m, struct ether_header *);
1647 /* Check the existence of VLAN tag. */
1648 if (eh->ether_type == htons(ETHERTYPE_VLAN)) {
1649 ip_off = sizeof(struct ether_vlan_header);
1650 m = m_pullup(m, ip_off);
1656 m = m_pullup(m, ip_off + sizeof(struct ip));
1661 ip = (struct ip *)(mtod(m, char *) + ip_off);
1662 poff = ip_off + (ip->ip_hl << 2);
1663 m = m_pullup(m, poff + sizeof(struct tcphdr));
1668 tcp = (struct tcphdr *)(mtod(m, char *) + poff);
1670 * Reset IP checksum and recompute TCP pseudo
1671 * checksum that NDIS specification requires.
1674 if (poff + (tcp->th_off << 2) == m->m_pkthdr.len) {
1675 tcp->th_sum = in_pseudo(ip->ip_src.s_addr,
1677 htons((tcp->th_off << 2) + IPPROTO_TCP));
1678 /* No need to TSO, force IP checksum offload. */
1679 (*m_head)->m_pkthdr.csum_flags &= ~CSUM_TSO;
1680 (*m_head)->m_pkthdr.csum_flags |= CSUM_IP;
1682 tcp->th_sum = in_pseudo(ip->ip_src.s_addr,
1683 ip->ip_dst.s_addr, htons(IPPROTO_TCP));
1687 prod = sc->jme_cdata.jme_tx_prod;
1688 txd = &sc->jme_cdata.jme_txdesc[prod];
1690 error = bus_dmamap_load_mbuf_sg(sc->jme_cdata.jme_tx_tag,
1691 txd->tx_dmamap, *m_head, txsegs, &nsegs, 0);
1692 if (error == EFBIG) {
1693 m = m_collapse(*m_head, M_DONTWAIT, JME_MAXTXSEGS);
1700 error = bus_dmamap_load_mbuf_sg(sc->jme_cdata.jme_tx_tag,
1701 txd->tx_dmamap, *m_head, txsegs, &nsegs, 0);
1707 } else if (error != 0)
1716 * Check descriptor overrun. Leave one free descriptor.
1717 * Since we always use 64bit address mode for transmitting,
1718 * each Tx request requires one more dummy descriptor.
1720 if (sc->jme_cdata.jme_tx_cnt + nsegs + 1 > JME_TX_RING_CNT - 1) {
1721 bus_dmamap_unload(sc->jme_cdata.jme_tx_tag, txd->tx_dmamap);
1728 /* Configure checksum offload and TSO. */
1729 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) {
1730 tso_segsz = (uint32_t)m->m_pkthdr.tso_segsz <<
1732 cflags |= JME_TD_TSO;
1734 if ((m->m_pkthdr.csum_flags & CSUM_IP) != 0)
1735 cflags |= JME_TD_IPCSUM;
1736 if ((m->m_pkthdr.csum_flags & CSUM_TCP) != 0)
1737 cflags |= JME_TD_TCPCSUM;
1738 if ((m->m_pkthdr.csum_flags & CSUM_UDP) != 0)
1739 cflags |= JME_TD_UDPCSUM;
1741 /* Configure VLAN. */
1742 if ((m->m_flags & M_VLANTAG) != 0) {
1743 cflags |= (m->m_pkthdr.ether_vtag & JME_TD_VLAN_MASK);
1744 cflags |= JME_TD_VLAN_TAG;
1747 desc = &sc->jme_rdata.jme_tx_ring[prod];
1748 desc->flags = htole32(cflags);
1749 desc->buflen = htole32(tso_segsz);
1750 desc->addr_hi = htole32(m->m_pkthdr.len);
1752 sc->jme_cdata.jme_tx_cnt++;
1753 JME_DESC_INC(prod, JME_TX_RING_CNT);
1754 for (i = 0; i < nsegs; i++) {
1755 desc = &sc->jme_rdata.jme_tx_ring[prod];
1756 desc->flags = htole32(JME_TD_OWN | JME_TD_64BIT);
1757 desc->buflen = htole32(txsegs[i].ds_len);
1758 desc->addr_hi = htole32(JME_ADDR_HI(txsegs[i].ds_addr));
1759 desc->addr_lo = htole32(JME_ADDR_LO(txsegs[i].ds_addr));
1760 sc->jme_cdata.jme_tx_cnt++;
1761 JME_DESC_INC(prod, JME_TX_RING_CNT);
1764 /* Update producer index. */
1765 sc->jme_cdata.jme_tx_prod = prod;
1767 * Finally request interrupt and give the first descriptor
1768 * owenership to hardware.
1770 desc = txd->tx_desc;
1771 desc->flags |= htole32(JME_TD_OWN | JME_TD_INTR);
1774 txd->tx_ndesc = nsegs + 1;
1776 /* Sync descriptors. */
1777 bus_dmamap_sync(sc->jme_cdata.jme_tx_tag, txd->tx_dmamap,
1778 BUS_DMASYNC_PREWRITE);
1779 bus_dmamap_sync(sc->jme_cdata.jme_tx_ring_tag,
1780 sc->jme_cdata.jme_tx_ring_map,
1781 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1787 jme_tx_task(void *arg, int pending)
1791 ifp = (struct ifnet *)arg;
1796 jme_start(struct ifnet *ifp)
1798 struct jme_softc *sc;
1799 struct mbuf *m_head;
1806 if (sc->jme_cdata.jme_tx_cnt >= JME_TX_DESC_HIWAT)
1809 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
1810 IFF_DRV_RUNNING || (sc->jme_flags & JME_FLAG_LINK) == 0) {
1815 for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd); ) {
1816 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
1820 * Pack the data into the transmit ring. If we
1821 * don't have room, set the OACTIVE flag and wait
1822 * for the NIC to drain the ring.
1824 if (jme_encap(sc, &m_head)) {
1827 IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
1828 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1834 * If there's a BPF listener, bounce a copy of this frame
1837 ETHER_BPF_MTAP(ifp, m_head);
1842 * Reading TXCSR takes very long time under heavy load
1843 * so cache TXCSR value and writes the ORed value with
1844 * the kick command to the TXCSR. This saves one register
1847 CSR_WRITE_4(sc, JME_TXCSR, sc->jme_txcsr | TXCSR_TX_ENB |
1848 TXCSR_TXQ_N_START(TXCSR_TXQ0));
1849 /* Set a timeout in case the chip goes out to lunch. */
1850 sc->jme_watchdog_timer = JME_TX_TIMEOUT;
1857 jme_watchdog(struct jme_softc *sc)
1861 JME_LOCK_ASSERT(sc);
1863 if (sc->jme_watchdog_timer == 0 || --sc->jme_watchdog_timer)
1867 if ((sc->jme_flags & JME_FLAG_LINK) == 0) {
1868 if_printf(sc->jme_ifp, "watchdog timeout (missed link)\n");
1870 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1871 jme_init_locked(sc);
1875 if (sc->jme_cdata.jme_tx_cnt == 0) {
1876 if_printf(sc->jme_ifp,
1877 "watchdog timeout (missed Tx interrupts) -- recovering\n");
1878 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1879 taskqueue_enqueue(sc->jme_tq, &sc->jme_tx_task);
1883 if_printf(sc->jme_ifp, "watchdog timeout\n");
1885 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1886 jme_init_locked(sc);
1887 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1888 taskqueue_enqueue(sc->jme_tq, &sc->jme_tx_task);
1892 jme_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
1894 struct jme_softc *sc;
1896 struct mii_data *mii;
1901 ifr = (struct ifreq *)data;
1905 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > JME_JUMBO_MTU ||
1906 ((sc->jme_flags & JME_FLAG_NOJUMBO) != 0 &&
1907 ifr->ifr_mtu > JME_MAX_MTU)) {
1912 if (ifp->if_mtu != ifr->ifr_mtu) {
1914 * No special configuration is required when interface
1915 * MTU is changed but availability of TSO/Tx checksum
1916 * offload should be chcked against new MTU size as
1917 * FIFO size is just 2K.
1920 if (ifr->ifr_mtu >= JME_TX_FIFO_SIZE) {
1921 ifp->if_capenable &=
1922 ~(IFCAP_TXCSUM | IFCAP_TSO4);
1924 ~(JME_CSUM_FEATURES | CSUM_TSO);
1925 VLAN_CAPABILITIES(ifp);
1927 ifp->if_mtu = ifr->ifr_mtu;
1928 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
1929 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1930 jme_init_locked(sc);
1937 if ((ifp->if_flags & IFF_UP) != 0) {
1938 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
1939 if (((ifp->if_flags ^ sc->jme_if_flags)
1940 & (IFF_PROMISC | IFF_ALLMULTI)) != 0)
1943 if ((sc->jme_flags & JME_FLAG_DETACH) == 0)
1944 jme_init_locked(sc);
1947 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
1950 sc->jme_if_flags = ifp->if_flags;
1956 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
1962 mii = device_get_softc(sc->jme_miibus);
1963 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd);
1967 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
1968 if ((mask & IFCAP_TXCSUM) != 0 &&
1969 ifp->if_mtu < JME_TX_FIFO_SIZE) {
1970 if ((IFCAP_TXCSUM & ifp->if_capabilities) != 0) {
1971 ifp->if_capenable ^= IFCAP_TXCSUM;
1972 if ((IFCAP_TXCSUM & ifp->if_capenable) != 0)
1973 ifp->if_hwassist |= JME_CSUM_FEATURES;
1975 ifp->if_hwassist &= ~JME_CSUM_FEATURES;
1978 if ((mask & IFCAP_RXCSUM) != 0 &&
1979 (IFCAP_RXCSUM & ifp->if_capabilities) != 0) {
1980 ifp->if_capenable ^= IFCAP_RXCSUM;
1981 reg = CSR_READ_4(sc, JME_RXMAC);
1982 reg &= ~RXMAC_CSUM_ENB;
1983 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0)
1984 reg |= RXMAC_CSUM_ENB;
1985 CSR_WRITE_4(sc, JME_RXMAC, reg);
1987 if ((mask & IFCAP_TSO4) != 0 &&
1988 ifp->if_mtu < JME_TX_FIFO_SIZE) {
1989 if ((IFCAP_TSO4 & ifp->if_capabilities) != 0) {
1990 ifp->if_capenable ^= IFCAP_TSO4;
1991 if ((IFCAP_TSO4 & ifp->if_capenable) != 0)
1992 ifp->if_hwassist |= CSUM_TSO;
1994 ifp->if_hwassist &= ~CSUM_TSO;
1997 if ((mask & IFCAP_WOL_MAGIC) != 0 &&
1998 (IFCAP_WOL_MAGIC & ifp->if_capabilities) != 0)
1999 ifp->if_capenable ^= IFCAP_WOL_MAGIC;
2000 if ((mask & IFCAP_VLAN_HWCSUM) != 0 &&
2001 (ifp->if_capabilities & IFCAP_VLAN_HWCSUM) != 0)
2002 ifp->if_capenable ^= IFCAP_VLAN_HWCSUM;
2003 if ((mask & IFCAP_VLAN_HWTSO) != 0 &&
2004 (ifp->if_capabilities & IFCAP_VLAN_HWTSO) != 0)
2005 ifp->if_capenable ^= IFCAP_VLAN_HWTSO;
2006 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 &&
2007 (IFCAP_VLAN_HWTAGGING & ifp->if_capabilities) != 0) {
2008 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
2012 VLAN_CAPABILITIES(ifp);
2015 error = ether_ioctl(ifp, cmd, data);
2023 jme_mac_config(struct jme_softc *sc)
2025 struct mii_data *mii;
2026 uint32_t ghc, gpreg, rxmac, txmac, txpause;
2029 JME_LOCK_ASSERT(sc);
2031 mii = device_get_softc(sc->jme_miibus);
2033 CSR_WRITE_4(sc, JME_GHC, GHC_RESET);
2035 CSR_WRITE_4(sc, JME_GHC, 0);
2038 rxmac = CSR_READ_4(sc, JME_RXMAC);
2039 rxmac &= ~RXMAC_FC_ENB;
2040 txmac = CSR_READ_4(sc, JME_TXMAC);
2041 txmac &= ~(TXMAC_CARRIER_EXT | TXMAC_FRAME_BURST);
2042 txpause = CSR_READ_4(sc, JME_TXPFC);
2043 txpause &= ~TXPFC_PAUSE_ENB;
2044 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) {
2045 ghc |= GHC_FULL_DUPLEX;
2046 rxmac &= ~RXMAC_COLL_DET_ENB;
2047 txmac &= ~(TXMAC_COLL_ENB | TXMAC_CARRIER_SENSE |
2048 TXMAC_BACKOFF | TXMAC_CARRIER_EXT |
2051 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0)
2052 txpause |= TXPFC_PAUSE_ENB;
2053 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0)
2054 rxmac |= RXMAC_FC_ENB;
2056 /* Disable retry transmit timer/retry limit. */
2057 CSR_WRITE_4(sc, JME_TXTRHD, CSR_READ_4(sc, JME_TXTRHD) &
2058 ~(TXTRHD_RT_PERIOD_ENB | TXTRHD_RT_LIMIT_ENB));
2060 rxmac |= RXMAC_COLL_DET_ENB;
2061 txmac |= TXMAC_COLL_ENB | TXMAC_CARRIER_SENSE | TXMAC_BACKOFF;
2062 /* Enable retry transmit timer/retry limit. */
2063 CSR_WRITE_4(sc, JME_TXTRHD, CSR_READ_4(sc, JME_TXTRHD) |
2064 TXTRHD_RT_PERIOD_ENB | TXTRHD_RT_LIMIT_ENB);
2066 /* Reprogram Tx/Rx MACs with resolved speed/duplex. */
2067 switch (IFM_SUBTYPE(mii->mii_media_active)) {
2069 ghc |= GHC_SPEED_10;
2070 txclk |= GHC_TX_OFFLD_CLK_100 | GHC_TX_MAC_CLK_100;
2073 ghc |= GHC_SPEED_100;
2074 txclk |= GHC_TX_OFFLD_CLK_100 | GHC_TX_MAC_CLK_100;
2077 if ((sc->jme_flags & JME_FLAG_FASTETH) != 0)
2079 ghc |= GHC_SPEED_1000;
2080 txclk |= GHC_TX_OFFLD_CLK_1000 | GHC_TX_MAC_CLK_1000;
2081 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) == 0)
2082 txmac |= TXMAC_CARRIER_EXT | TXMAC_FRAME_BURST;
2087 if (sc->jme_rev == DEVICEID_JMC250 &&
2088 sc->jme_chip_rev == DEVICEREVID_JMC250_A2) {
2090 * Workaround occasional packet loss issue of JMC250 A2
2091 * when it runs on half-duplex media.
2093 gpreg = CSR_READ_4(sc, JME_GPREG1);
2094 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0)
2095 gpreg &= ~GPREG1_HDPX_FIX;
2097 gpreg |= GPREG1_HDPX_FIX;
2098 CSR_WRITE_4(sc, JME_GPREG1, gpreg);
2099 /* Workaround CRC errors at 100Mbps on JMC250 A2. */
2100 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX) {
2101 /* Extend interface FIFO depth. */
2102 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr,
2105 /* Select default interface FIFO depth. */
2106 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr,
2110 if ((sc->jme_flags & JME_FLAG_TXCLK) != 0)
2112 CSR_WRITE_4(sc, JME_GHC, ghc);
2113 CSR_WRITE_4(sc, JME_RXMAC, rxmac);
2114 CSR_WRITE_4(sc, JME_TXMAC, txmac);
2115 CSR_WRITE_4(sc, JME_TXPFC, txpause);
2119 jme_link_task(void *arg, int pending)
2121 struct jme_softc *sc;
2122 struct mii_data *mii;
2124 struct jme_txdesc *txd;
2128 sc = (struct jme_softc *)arg;
2131 mii = device_get_softc(sc->jme_miibus);
2133 if (mii == NULL || ifp == NULL ||
2134 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
2139 sc->jme_flags &= ~JME_FLAG_LINK;
2140 if ((mii->mii_media_status & IFM_AVALID) != 0) {
2141 switch (IFM_SUBTYPE(mii->mii_media_active)) {
2144 sc->jme_flags |= JME_FLAG_LINK;
2147 if ((sc->jme_flags & JME_FLAG_FASTETH) != 0)
2149 sc->jme_flags |= JME_FLAG_LINK;
2157 * Disabling Rx/Tx MACs have a side-effect of resetting
2158 * JME_TXNDA/JME_RXNDA register to the first address of
2159 * Tx/Rx descriptor address. So driver should reset its
2160 * internal procucer/consumer pointer and reclaim any
2161 * allocated resources. Note, just saving the value of
2162 * JME_TXNDA and JME_RXNDA registers before stopping MAC
2163 * and restoring JME_TXNDA/JME_RXNDA register is not
2164 * sufficient to make sure correct MAC state because
2165 * stopping MAC operation can take a while and hardware
2166 * might have updated JME_TXNDA/JME_RXNDA registers
2167 * during the stop operation.
2169 /* Block execution of task. */
2170 taskqueue_block(sc->jme_tq);
2171 /* Disable interrupts and stop driver. */
2172 CSR_WRITE_4(sc, JME_INTR_MASK_CLR, JME_INTRS);
2173 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
2174 callout_stop(&sc->jme_tick_ch);
2175 sc->jme_watchdog_timer = 0;
2177 /* Stop receiver/transmitter. */
2181 /* XXX Drain all queued tasks. */
2183 taskqueue_drain(sc->jme_tq, &sc->jme_int_task);
2184 taskqueue_drain(sc->jme_tq, &sc->jme_tx_task);
2187 jme_rxintr(sc, JME_RX_RING_CNT);
2188 if (sc->jme_cdata.jme_rxhead != NULL)
2189 m_freem(sc->jme_cdata.jme_rxhead);
2190 JME_RXCHAIN_RESET(sc);
2192 if (sc->jme_cdata.jme_tx_cnt != 0) {
2193 /* Remove queued packets for transmit. */
2194 for (i = 0; i < JME_TX_RING_CNT; i++) {
2195 txd = &sc->jme_cdata.jme_txdesc[i];
2196 if (txd->tx_m != NULL) {
2198 sc->jme_cdata.jme_tx_tag,
2200 BUS_DMASYNC_POSTWRITE);
2202 sc->jme_cdata.jme_tx_tag,
2213 * Reuse configured Rx descriptors and reset
2214 * procuder/consumer index.
2216 sc->jme_cdata.jme_rx_cons = 0;
2217 atomic_set_int(&sc->jme_morework, 0);
2218 jme_init_tx_ring(sc);
2219 /* Initialize shadow status block. */
2222 /* Program MAC with resolved speed/duplex/flow-control. */
2223 if ((sc->jme_flags & JME_FLAG_LINK) != 0) {
2225 jme_stats_clear(sc);
2227 CSR_WRITE_4(sc, JME_RXCSR, sc->jme_rxcsr);
2228 CSR_WRITE_4(sc, JME_TXCSR, sc->jme_txcsr);
2230 /* Set Tx ring address to the hardware. */
2231 paddr = JME_TX_RING_ADDR(sc, 0);
2232 CSR_WRITE_4(sc, JME_TXDBA_HI, JME_ADDR_HI(paddr));
2233 CSR_WRITE_4(sc, JME_TXDBA_LO, JME_ADDR_LO(paddr));
2235 /* Set Rx ring address to the hardware. */
2236 paddr = JME_RX_RING_ADDR(sc, 0);
2237 CSR_WRITE_4(sc, JME_RXDBA_HI, JME_ADDR_HI(paddr));
2238 CSR_WRITE_4(sc, JME_RXDBA_LO, JME_ADDR_LO(paddr));
2240 /* Restart receiver/transmitter. */
2241 CSR_WRITE_4(sc, JME_RXCSR, sc->jme_rxcsr | RXCSR_RX_ENB |
2243 CSR_WRITE_4(sc, JME_TXCSR, sc->jme_txcsr | TXCSR_TX_ENB);
2246 ifp->if_drv_flags |= IFF_DRV_RUNNING;
2247 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2248 callout_reset(&sc->jme_tick_ch, hz, jme_tick, sc);
2249 /* Unblock execution of task. */
2250 taskqueue_unblock(sc->jme_tq);
2251 /* Reenable interrupts. */
2252 CSR_WRITE_4(sc, JME_INTR_MASK_SET, JME_INTRS);
2260 struct jme_softc *sc;
2263 sc = (struct jme_softc *)arg;
2265 status = CSR_READ_4(sc, JME_INTR_REQ_STATUS);
2266 if (status == 0 || status == 0xFFFFFFFF)
2267 return (FILTER_STRAY);
2268 /* Disable interrupts. */
2269 CSR_WRITE_4(sc, JME_INTR_MASK_CLR, JME_INTRS);
2270 taskqueue_enqueue(sc->jme_tq, &sc->jme_int_task);
2272 return (FILTER_HANDLED);
2276 jme_int_task(void *arg, int pending)
2278 struct jme_softc *sc;
2283 sc = (struct jme_softc *)arg;
2286 status = CSR_READ_4(sc, JME_INTR_STATUS);
2287 more = atomic_readandclear_int(&sc->jme_morework);
2289 status |= INTR_RXQ_COAL | INTR_RXQ_COAL_TO;
2292 if ((status & JME_INTRS) == 0 || status == 0xFFFFFFFF)
2294 /* Reset PCC counter/timer and Ack interrupts. */
2295 status &= ~(INTR_TXQ_COMP | INTR_RXQ_COMP);
2296 if ((status & (INTR_TXQ_COAL | INTR_TXQ_COAL_TO)) != 0)
2297 status |= INTR_TXQ_COAL | INTR_TXQ_COAL_TO | INTR_TXQ_COMP;
2298 if ((status & (INTR_RXQ_COAL | INTR_RXQ_COAL_TO)) != 0)
2299 status |= INTR_RXQ_COAL | INTR_RXQ_COAL_TO | INTR_RXQ_COMP;
2300 CSR_WRITE_4(sc, JME_INTR_STATUS, status);
2302 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
2303 if ((status & (INTR_RXQ_COAL | INTR_RXQ_COAL_TO)) != 0) {
2304 more = jme_rxintr(sc, sc->jme_process_limit);
2306 atomic_set_int(&sc->jme_morework, 1);
2308 if ((status & INTR_RXQ_DESC_EMPTY) != 0) {
2310 * Notify hardware availability of new Rx
2312 * Reading RXCSR takes very long time under
2313 * heavy load so cache RXCSR value and writes
2314 * the ORed value with the kick command to
2315 * the RXCSR. This saves one register access
2318 CSR_WRITE_4(sc, JME_RXCSR, sc->jme_rxcsr |
2319 RXCSR_RX_ENB | RXCSR_RXQ_START);
2322 * Reclaiming Tx buffers are deferred to make jme(4) run
2323 * without locks held.
2325 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
2326 taskqueue_enqueue(sc->jme_tq, &sc->jme_tx_task);
2329 if (more != 0 || (CSR_READ_4(sc, JME_INTR_STATUS) & JME_INTRS) != 0) {
2330 taskqueue_enqueue(sc->jme_tq, &sc->jme_int_task);
2334 /* Reenable interrupts. */
2335 CSR_WRITE_4(sc, JME_INTR_MASK_SET, JME_INTRS);
2339 jme_txeof(struct jme_softc *sc)
2342 struct jme_txdesc *txd;
2346 JME_LOCK_ASSERT(sc);
2350 cons = sc->jme_cdata.jme_tx_cons;
2351 if (cons == sc->jme_cdata.jme_tx_prod)
2354 bus_dmamap_sync(sc->jme_cdata.jme_tx_ring_tag,
2355 sc->jme_cdata.jme_tx_ring_map,
2356 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2359 * Go through our Tx list and free mbufs for those
2360 * frames which have been transmitted.
2362 for (; cons != sc->jme_cdata.jme_tx_prod;) {
2363 txd = &sc->jme_cdata.jme_txdesc[cons];
2364 status = le32toh(txd->tx_desc->flags);
2365 if ((status & JME_TD_OWN) == JME_TD_OWN)
2368 if ((status & (JME_TD_TMOUT | JME_TD_RETRY_EXP)) != 0)
2372 if ((status & JME_TD_COLLISION) != 0)
2373 ifp->if_collisions +=
2374 le32toh(txd->tx_desc->buflen) &
2375 JME_TD_BUF_LEN_MASK;
2378 * Only the first descriptor of multi-descriptor
2379 * transmission is updated so driver have to skip entire
2380 * chained buffers for the transmiited frame. In other
2381 * words, JME_TD_OWN bit is valid only at the first
2382 * descriptor of a multi-descriptor transmission.
2384 for (nsegs = 0; nsegs < txd->tx_ndesc; nsegs++) {
2385 sc->jme_rdata.jme_tx_ring[cons].flags = 0;
2386 JME_DESC_INC(cons, JME_TX_RING_CNT);
2389 /* Reclaim transferred mbufs. */
2390 bus_dmamap_sync(sc->jme_cdata.jme_tx_tag, txd->tx_dmamap,
2391 BUS_DMASYNC_POSTWRITE);
2392 bus_dmamap_unload(sc->jme_cdata.jme_tx_tag, txd->tx_dmamap);
2394 KASSERT(txd->tx_m != NULL,
2395 ("%s: freeing NULL mbuf!\n", __func__));
2398 sc->jme_cdata.jme_tx_cnt -= txd->tx_ndesc;
2399 KASSERT(sc->jme_cdata.jme_tx_cnt >= 0,
2400 ("%s: Active Tx desc counter was garbled\n", __func__));
2402 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2404 sc->jme_cdata.jme_tx_cons = cons;
2405 /* Unarm watchog timer when there is no pending descriptors in queue. */
2406 if (sc->jme_cdata.jme_tx_cnt == 0)
2407 sc->jme_watchdog_timer = 0;
2409 bus_dmamap_sync(sc->jme_cdata.jme_tx_ring_tag,
2410 sc->jme_cdata.jme_tx_ring_map,
2411 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2414 static __inline void
2415 jme_discard_rxbuf(struct jme_softc *sc, int cons)
2417 struct jme_desc *desc;
2419 desc = &sc->jme_rdata.jme_rx_ring[cons];
2420 desc->flags = htole32(JME_RD_OWN | JME_RD_INTR | JME_RD_64BIT);
2421 desc->buflen = htole32(MCLBYTES);
2424 /* Receive a frame. */
2426 jme_rxeof(struct jme_softc *sc)
2429 struct jme_desc *desc;
2430 struct jme_rxdesc *rxd;
2431 struct mbuf *mp, *m;
2432 uint32_t flags, status;
2433 int cons, count, nsegs;
2437 cons = sc->jme_cdata.jme_rx_cons;
2438 desc = &sc->jme_rdata.jme_rx_ring[cons];
2439 flags = le32toh(desc->flags);
2440 status = le32toh(desc->buflen);
2441 nsegs = JME_RX_NSEGS(status);
2442 sc->jme_cdata.jme_rxlen = JME_RX_BYTES(status) - JME_RX_PAD_BYTES;
2443 if ((status & JME_RX_ERR_STAT) != 0) {
2445 jme_discard_rxbuf(sc, sc->jme_cdata.jme_rx_cons);
2446 #ifdef JME_SHOW_ERRORS
2447 device_printf(sc->jme_dev, "%s : receive error = 0x%b\n",
2448 __func__, JME_RX_ERR(status), JME_RX_ERR_BITS);
2450 sc->jme_cdata.jme_rx_cons += nsegs;
2451 sc->jme_cdata.jme_rx_cons %= JME_RX_RING_CNT;
2455 for (count = 0; count < nsegs; count++,
2456 JME_DESC_INC(cons, JME_RX_RING_CNT)) {
2457 rxd = &sc->jme_cdata.jme_rxdesc[cons];
2459 /* Add a new receive buffer to the ring. */
2460 if (jme_newbuf(sc, rxd) != 0) {
2463 for (; count < nsegs; count++) {
2464 jme_discard_rxbuf(sc, cons);
2465 JME_DESC_INC(cons, JME_RX_RING_CNT);
2467 if (sc->jme_cdata.jme_rxhead != NULL) {
2468 m_freem(sc->jme_cdata.jme_rxhead);
2469 JME_RXCHAIN_RESET(sc);
2475 * Assume we've received a full sized frame.
2476 * Actual size is fixed when we encounter the end of
2477 * multi-segmented frame.
2479 mp->m_len = MCLBYTES;
2481 /* Chain received mbufs. */
2482 if (sc->jme_cdata.jme_rxhead == NULL) {
2483 sc->jme_cdata.jme_rxhead = mp;
2484 sc->jme_cdata.jme_rxtail = mp;
2487 * Receive processor can receive a maximum frame
2488 * size of 65535 bytes.
2490 mp->m_flags &= ~M_PKTHDR;
2491 sc->jme_cdata.jme_rxtail->m_next = mp;
2492 sc->jme_cdata.jme_rxtail = mp;
2495 if (count == nsegs - 1) {
2496 /* Last desc. for this frame. */
2497 m = sc->jme_cdata.jme_rxhead;
2498 m->m_flags |= M_PKTHDR;
2499 m->m_pkthdr.len = sc->jme_cdata.jme_rxlen;
2501 /* Set first mbuf size. */
2502 m->m_len = MCLBYTES - JME_RX_PAD_BYTES;
2503 /* Set last mbuf size. */
2504 mp->m_len = sc->jme_cdata.jme_rxlen -
2505 ((MCLBYTES - JME_RX_PAD_BYTES) +
2506 (MCLBYTES * (nsegs - 2)));
2508 m->m_len = sc->jme_cdata.jme_rxlen;
2509 m->m_pkthdr.rcvif = ifp;
2512 * Account for 10bytes auto padding which is used
2513 * to align IP header on 32bit boundary. Also note,
2514 * CRC bytes is automatically removed by the
2517 m->m_data += JME_RX_PAD_BYTES;
2519 /* Set checksum information. */
2520 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0 &&
2521 (flags & JME_RD_IPV4) != 0) {
2522 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
2523 if ((flags & JME_RD_IPCSUM) != 0)
2524 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
2525 if (((flags & JME_RD_MORE_FRAG) == 0) &&
2526 ((flags & (JME_RD_TCP | JME_RD_TCPCSUM)) ==
2527 (JME_RD_TCP | JME_RD_TCPCSUM) ||
2528 (flags & (JME_RD_UDP | JME_RD_UDPCSUM)) ==
2529 (JME_RD_UDP | JME_RD_UDPCSUM))) {
2530 m->m_pkthdr.csum_flags |=
2531 CSUM_DATA_VALID | CSUM_PSEUDO_HDR;
2532 m->m_pkthdr.csum_data = 0xffff;
2536 /* Check for VLAN tagged packets. */
2537 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0 &&
2538 (flags & JME_RD_VLAN_TAG) != 0) {
2539 m->m_pkthdr.ether_vtag =
2540 flags & JME_RD_VLAN_MASK;
2541 m->m_flags |= M_VLANTAG;
2546 (*ifp->if_input)(ifp, m);
2548 /* Reset mbuf chains. */
2549 JME_RXCHAIN_RESET(sc);
2553 sc->jme_cdata.jme_rx_cons += nsegs;
2554 sc->jme_cdata.jme_rx_cons %= JME_RX_RING_CNT;
2558 jme_rxintr(struct jme_softc *sc, int count)
2560 struct jme_desc *desc;
2561 int nsegs, prog, pktlen;
2563 bus_dmamap_sync(sc->jme_cdata.jme_rx_ring_tag,
2564 sc->jme_cdata.jme_rx_ring_map,
2565 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2567 for (prog = 0; count > 0; prog++) {
2568 desc = &sc->jme_rdata.jme_rx_ring[sc->jme_cdata.jme_rx_cons];
2569 if ((le32toh(desc->flags) & JME_RD_OWN) == JME_RD_OWN)
2571 if ((le32toh(desc->buflen) & JME_RD_VALID) == 0)
2573 nsegs = JME_RX_NSEGS(le32toh(desc->buflen));
2575 * Check number of segments against received bytes.
2576 * Non-matching value would indicate that hardware
2577 * is still trying to update Rx descriptors. I'm not
2578 * sure whether this check is needed.
2580 pktlen = JME_RX_BYTES(le32toh(desc->buflen));
2581 if (nsegs != ((pktlen + (MCLBYTES - 1)) / MCLBYTES))
2584 /* Received a frame. */
2590 bus_dmamap_sync(sc->jme_cdata.jme_rx_ring_tag,
2591 sc->jme_cdata.jme_rx_ring_map,
2592 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2594 return (count > 0 ? 0 : EAGAIN);
2600 struct jme_softc *sc;
2601 struct mii_data *mii;
2603 sc = (struct jme_softc *)arg;
2605 JME_LOCK_ASSERT(sc);
2607 mii = device_get_softc(sc->jme_miibus);
2610 * Reclaim Tx buffers that have been completed. It's not
2611 * needed here but it would release allocated mbuf chains
2612 * faster and limit the maximum delay to a hz.
2615 jme_stats_update(sc);
2617 callout_reset(&sc->jme_tick_ch, hz, jme_tick, sc);
2621 jme_reset(struct jme_softc *sc)
2624 /* Stop receiver, transmitter. */
2627 CSR_WRITE_4(sc, JME_GHC, GHC_RESET);
2629 CSR_WRITE_4(sc, JME_GHC, 0);
2635 struct jme_softc *sc;
2637 sc = (struct jme_softc *)xsc;
2639 jme_init_locked(sc);
2644 jme_init_locked(struct jme_softc *sc)
2647 struct mii_data *mii;
2648 uint8_t eaddr[ETHER_ADDR_LEN];
2653 JME_LOCK_ASSERT(sc);
2656 mii = device_get_softc(sc->jme_miibus);
2658 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
2661 * Cancel any pending I/O.
2666 * Reset the chip to a known state.
2670 /* Init descriptors. */
2671 error = jme_init_rx_ring(sc);
2673 device_printf(sc->jme_dev,
2674 "%s: initialization failed: no memory for Rx buffers.\n",
2679 jme_init_tx_ring(sc);
2680 /* Initialize shadow status block. */
2683 /* Reprogram the station address. */
2684 bcopy(IF_LLADDR(ifp), eaddr, ETHER_ADDR_LEN);
2685 CSR_WRITE_4(sc, JME_PAR0,
2686 eaddr[3] << 24 | eaddr[2] << 16 | eaddr[1] << 8 | eaddr[0]);
2687 CSR_WRITE_4(sc, JME_PAR1, eaddr[5] << 8 | eaddr[4]);
2690 * Configure Tx queue.
2691 * Tx priority queue weight value : 0
2692 * Tx FIFO threshold for processing next packet : 16QW
2693 * Maximum Tx DMA length : 512
2694 * Allow Tx DMA burst.
2696 sc->jme_txcsr = TXCSR_TXQ_N_SEL(TXCSR_TXQ0);
2697 sc->jme_txcsr |= TXCSR_TXQ_WEIGHT(TXCSR_TXQ_WEIGHT_MIN);
2698 sc->jme_txcsr |= TXCSR_FIFO_THRESH_16QW;
2699 sc->jme_txcsr |= sc->jme_tx_dma_size;
2700 sc->jme_txcsr |= TXCSR_DMA_BURST;
2701 CSR_WRITE_4(sc, JME_TXCSR, sc->jme_txcsr);
2703 /* Set Tx descriptor counter. */
2704 CSR_WRITE_4(sc, JME_TXQDC, JME_TX_RING_CNT);
2706 /* Set Tx ring address to the hardware. */
2707 paddr = JME_TX_RING_ADDR(sc, 0);
2708 CSR_WRITE_4(sc, JME_TXDBA_HI, JME_ADDR_HI(paddr));
2709 CSR_WRITE_4(sc, JME_TXDBA_LO, JME_ADDR_LO(paddr));
2711 /* Configure TxMAC parameters. */
2712 reg = TXMAC_IFG1_DEFAULT | TXMAC_IFG2_DEFAULT | TXMAC_IFG_ENB;
2713 reg |= TXMAC_THRESH_1_PKT;
2714 reg |= TXMAC_CRC_ENB | TXMAC_PAD_ENB;
2715 CSR_WRITE_4(sc, JME_TXMAC, reg);
2718 * Configure Rx queue.
2719 * FIFO full threshold for transmitting Tx pause packet : 128T
2720 * FIFO threshold for processing next packet : 128QW
2722 * Max Rx DMA length : 128
2723 * Rx descriptor retry : 32
2724 * Rx descriptor retry time gap : 256ns
2725 * Don't receive runt/bad frame.
2727 sc->jme_rxcsr = RXCSR_FIFO_FTHRESH_128T;
2729 * Since Rx FIFO size is 4K bytes, receiving frames larger
2730 * than 4K bytes will suffer from Rx FIFO overruns. So
2731 * decrease FIFO threshold to reduce the FIFO overruns for
2732 * frames larger than 4000 bytes.
2733 * For best performance of standard MTU sized frames use
2734 * maximum allowable FIFO threshold, 128QW. Note these do
2735 * not hold on chip full mask verion >=2. For these
2736 * controllers 64QW and 128QW are not valid value.
2738 if (CHIPMODE_REVFM(sc->jme_chip_rev) >= 2)
2739 sc->jme_rxcsr |= RXCSR_FIFO_THRESH_16QW;
2741 if ((ifp->if_mtu + ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN +
2742 ETHER_CRC_LEN) > JME_RX_FIFO_SIZE)
2743 sc->jme_rxcsr |= RXCSR_FIFO_THRESH_16QW;
2745 sc->jme_rxcsr |= RXCSR_FIFO_THRESH_128QW;
2747 sc->jme_rxcsr |= sc->jme_rx_dma_size | RXCSR_RXQ_N_SEL(RXCSR_RXQ0);
2748 sc->jme_rxcsr |= RXCSR_DESC_RT_CNT(RXCSR_DESC_RT_CNT_DEFAULT);
2749 sc->jme_rxcsr |= RXCSR_DESC_RT_GAP_256 & RXCSR_DESC_RT_GAP_MASK;
2750 CSR_WRITE_4(sc, JME_RXCSR, sc->jme_rxcsr);
2752 /* Set Rx descriptor counter. */
2753 CSR_WRITE_4(sc, JME_RXQDC, JME_RX_RING_CNT);
2755 /* Set Rx ring address to the hardware. */
2756 paddr = JME_RX_RING_ADDR(sc, 0);
2757 CSR_WRITE_4(sc, JME_RXDBA_HI, JME_ADDR_HI(paddr));
2758 CSR_WRITE_4(sc, JME_RXDBA_LO, JME_ADDR_LO(paddr));
2760 /* Clear receive filter. */
2761 CSR_WRITE_4(sc, JME_RXMAC, 0);
2762 /* Set up the receive filter. */
2767 * Disable all WOL bits as WOL can interfere normal Rx
2768 * operation. Also clear WOL detection status bits.
2770 reg = CSR_READ_4(sc, JME_PMCS);
2771 reg &= ~PMCS_WOL_ENB_MASK;
2772 CSR_WRITE_4(sc, JME_PMCS, reg);
2774 reg = CSR_READ_4(sc, JME_RXMAC);
2776 * Pad 10bytes right before received frame. This will greatly
2777 * help Rx performance on strict-alignment architectures as
2778 * it does not need to copy the frame to align the payload.
2780 reg |= RXMAC_PAD_10BYTES;
2781 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0)
2782 reg |= RXMAC_CSUM_ENB;
2783 CSR_WRITE_4(sc, JME_RXMAC, reg);
2785 /* Configure general purpose reg0 */
2786 reg = CSR_READ_4(sc, JME_GPREG0);
2787 reg &= ~GPREG0_PCC_UNIT_MASK;
2788 /* Set PCC timer resolution to micro-seconds unit. */
2789 reg |= GPREG0_PCC_UNIT_US;
2791 * Disable all shadow register posting as we have to read
2792 * JME_INTR_STATUS register in jme_int_task. Also it seems
2793 * that it's hard to synchronize interrupt status between
2794 * hardware and software with shadow posting due to
2795 * requirements of bus_dmamap_sync(9).
2797 reg |= GPREG0_SH_POST_DW7_DIS | GPREG0_SH_POST_DW6_DIS |
2798 GPREG0_SH_POST_DW5_DIS | GPREG0_SH_POST_DW4_DIS |
2799 GPREG0_SH_POST_DW3_DIS | GPREG0_SH_POST_DW2_DIS |
2800 GPREG0_SH_POST_DW1_DIS | GPREG0_SH_POST_DW0_DIS;
2801 /* Disable posting of DW0. */
2802 reg &= ~GPREG0_POST_DW0_ENB;
2803 /* Clear PME message. */
2804 reg &= ~GPREG0_PME_ENB;
2805 /* Set PHY address. */
2806 reg &= ~GPREG0_PHY_ADDR_MASK;
2807 reg |= sc->jme_phyaddr;
2808 CSR_WRITE_4(sc, JME_GPREG0, reg);
2810 /* Configure Tx queue 0 packet completion coalescing. */
2811 reg = (sc->jme_tx_coal_to << PCCTX_COAL_TO_SHIFT) &
2813 reg |= (sc->jme_tx_coal_pkt << PCCTX_COAL_PKT_SHIFT) &
2814 PCCTX_COAL_PKT_MASK;
2815 reg |= PCCTX_COAL_TXQ0;
2816 CSR_WRITE_4(sc, JME_PCCTX, reg);
2818 /* Configure Rx queue 0 packet completion coalescing. */
2819 reg = (sc->jme_rx_coal_to << PCCRX_COAL_TO_SHIFT) &
2821 reg |= (sc->jme_rx_coal_pkt << PCCRX_COAL_PKT_SHIFT) &
2822 PCCRX_COAL_PKT_MASK;
2823 CSR_WRITE_4(sc, JME_PCCRX0, reg);
2825 /* Configure shadow status block but don't enable posting. */
2826 paddr = sc->jme_rdata.jme_ssb_block_paddr;
2827 CSR_WRITE_4(sc, JME_SHBASE_ADDR_HI, JME_ADDR_HI(paddr));
2828 CSR_WRITE_4(sc, JME_SHBASE_ADDR_LO, JME_ADDR_LO(paddr));
2830 /* Disable Timer 1 and Timer 2. */
2831 CSR_WRITE_4(sc, JME_TIMER1, 0);
2832 CSR_WRITE_4(sc, JME_TIMER2, 0);
2834 /* Configure retry transmit period, retry limit value. */
2835 CSR_WRITE_4(sc, JME_TXTRHD,
2836 ((TXTRHD_RT_PERIOD_DEFAULT << TXTRHD_RT_PERIOD_SHIFT) &
2837 TXTRHD_RT_PERIOD_MASK) |
2838 ((TXTRHD_RT_LIMIT_DEFAULT << TXTRHD_RT_LIMIT_SHIFT) &
2839 TXTRHD_RT_LIMIT_SHIFT));
2842 CSR_WRITE_4(sc, JME_RSSC, RSSC_DIS_RSS);
2844 /* Initialize the interrupt mask. */
2845 CSR_WRITE_4(sc, JME_INTR_MASK_SET, JME_INTRS);
2846 CSR_WRITE_4(sc, JME_INTR_STATUS, 0xFFFFFFFF);
2849 * Enabling Tx/Rx DMA engines and Rx queue processing is
2850 * done after detection of valid link in jme_link_task.
2853 sc->jme_flags &= ~JME_FLAG_LINK;
2854 /* Set the current media. */
2857 callout_reset(&sc->jme_tick_ch, hz, jme_tick, sc);
2859 ifp->if_drv_flags |= IFF_DRV_RUNNING;
2860 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2864 jme_stop(struct jme_softc *sc)
2867 struct jme_txdesc *txd;
2868 struct jme_rxdesc *rxd;
2871 JME_LOCK_ASSERT(sc);
2873 * Mark the interface down and cancel the watchdog timer.
2876 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
2877 sc->jme_flags &= ~JME_FLAG_LINK;
2878 callout_stop(&sc->jme_tick_ch);
2879 sc->jme_watchdog_timer = 0;
2882 * Disable interrupts.
2884 CSR_WRITE_4(sc, JME_INTR_MASK_CLR, JME_INTRS);
2885 CSR_WRITE_4(sc, JME_INTR_STATUS, 0xFFFFFFFF);
2887 /* Disable updating shadow status block. */
2888 CSR_WRITE_4(sc, JME_SHBASE_ADDR_LO,
2889 CSR_READ_4(sc, JME_SHBASE_ADDR_LO) & ~SHBASE_POST_ENB);
2891 /* Stop receiver, transmitter. */
2895 /* Reclaim Rx/Tx buffers that have been completed. */
2896 jme_rxintr(sc, JME_RX_RING_CNT);
2897 if (sc->jme_cdata.jme_rxhead != NULL)
2898 m_freem(sc->jme_cdata.jme_rxhead);
2899 JME_RXCHAIN_RESET(sc);
2902 * Free RX and TX mbufs still in the queues.
2904 for (i = 0; i < JME_RX_RING_CNT; i++) {
2905 rxd = &sc->jme_cdata.jme_rxdesc[i];
2906 if (rxd->rx_m != NULL) {
2907 bus_dmamap_sync(sc->jme_cdata.jme_rx_tag,
2908 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD);
2909 bus_dmamap_unload(sc->jme_cdata.jme_rx_tag,
2915 for (i = 0; i < JME_TX_RING_CNT; i++) {
2916 txd = &sc->jme_cdata.jme_txdesc[i];
2917 if (txd->tx_m != NULL) {
2918 bus_dmamap_sync(sc->jme_cdata.jme_tx_tag,
2919 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE);
2920 bus_dmamap_unload(sc->jme_cdata.jme_tx_tag,
2927 jme_stats_update(sc);
2932 jme_stop_tx(struct jme_softc *sc)
2937 reg = CSR_READ_4(sc, JME_TXCSR);
2938 if ((reg & TXCSR_TX_ENB) == 0)
2940 reg &= ~TXCSR_TX_ENB;
2941 CSR_WRITE_4(sc, JME_TXCSR, reg);
2942 for (i = JME_TIMEOUT; i > 0; i--) {
2944 if ((CSR_READ_4(sc, JME_TXCSR) & TXCSR_TX_ENB) == 0)
2948 device_printf(sc->jme_dev, "stopping transmitter timeout!\n");
2952 jme_stop_rx(struct jme_softc *sc)
2957 reg = CSR_READ_4(sc, JME_RXCSR);
2958 if ((reg & RXCSR_RX_ENB) == 0)
2960 reg &= ~RXCSR_RX_ENB;
2961 CSR_WRITE_4(sc, JME_RXCSR, reg);
2962 for (i = JME_TIMEOUT; i > 0; i--) {
2964 if ((CSR_READ_4(sc, JME_RXCSR) & RXCSR_RX_ENB) == 0)
2968 device_printf(sc->jme_dev, "stopping recevier timeout!\n");
2972 jme_init_tx_ring(struct jme_softc *sc)
2974 struct jme_ring_data *rd;
2975 struct jme_txdesc *txd;
2978 sc->jme_cdata.jme_tx_prod = 0;
2979 sc->jme_cdata.jme_tx_cons = 0;
2980 sc->jme_cdata.jme_tx_cnt = 0;
2982 rd = &sc->jme_rdata;
2983 bzero(rd->jme_tx_ring, JME_TX_RING_SIZE);
2984 for (i = 0; i < JME_TX_RING_CNT; i++) {
2985 txd = &sc->jme_cdata.jme_txdesc[i];
2987 txd->tx_desc = &rd->jme_tx_ring[i];
2991 bus_dmamap_sync(sc->jme_cdata.jme_tx_ring_tag,
2992 sc->jme_cdata.jme_tx_ring_map,
2993 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2997 jme_init_ssb(struct jme_softc *sc)
2999 struct jme_ring_data *rd;
3001 rd = &sc->jme_rdata;
3002 bzero(rd->jme_ssb_block, JME_SSB_SIZE);
3003 bus_dmamap_sync(sc->jme_cdata.jme_ssb_tag, sc->jme_cdata.jme_ssb_map,
3004 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3008 jme_init_rx_ring(struct jme_softc *sc)
3010 struct jme_ring_data *rd;
3011 struct jme_rxdesc *rxd;
3014 sc->jme_cdata.jme_rx_cons = 0;
3015 JME_RXCHAIN_RESET(sc);
3016 atomic_set_int(&sc->jme_morework, 0);
3018 rd = &sc->jme_rdata;
3019 bzero(rd->jme_rx_ring, JME_RX_RING_SIZE);
3020 for (i = 0; i < JME_RX_RING_CNT; i++) {
3021 rxd = &sc->jme_cdata.jme_rxdesc[i];
3023 rxd->rx_desc = &rd->jme_rx_ring[i];
3024 if (jme_newbuf(sc, rxd) != 0)
3028 bus_dmamap_sync(sc->jme_cdata.jme_rx_ring_tag,
3029 sc->jme_cdata.jme_rx_ring_map,
3030 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3036 jme_newbuf(struct jme_softc *sc, struct jme_rxdesc *rxd)
3038 struct jme_desc *desc;
3040 bus_dma_segment_t segs[1];
3044 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
3048 * JMC250 has 64bit boundary alignment limitation so jme(4)
3049 * takes advantage of 10 bytes padding feature of hardware
3050 * in order not to copy entire frame to align IP header on
3053 m->m_len = m->m_pkthdr.len = MCLBYTES;
3055 if (bus_dmamap_load_mbuf_sg(sc->jme_cdata.jme_rx_tag,
3056 sc->jme_cdata.jme_rx_sparemap, m, segs, &nsegs, 0) != 0) {
3060 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
3062 if (rxd->rx_m != NULL) {
3063 bus_dmamap_sync(sc->jme_cdata.jme_rx_tag, rxd->rx_dmamap,
3064 BUS_DMASYNC_POSTREAD);
3065 bus_dmamap_unload(sc->jme_cdata.jme_rx_tag, rxd->rx_dmamap);
3067 map = rxd->rx_dmamap;
3068 rxd->rx_dmamap = sc->jme_cdata.jme_rx_sparemap;
3069 sc->jme_cdata.jme_rx_sparemap = map;
3070 bus_dmamap_sync(sc->jme_cdata.jme_rx_tag, rxd->rx_dmamap,
3071 BUS_DMASYNC_PREREAD);
3074 desc = rxd->rx_desc;
3075 desc->buflen = htole32(segs[0].ds_len);
3076 desc->addr_lo = htole32(JME_ADDR_LO(segs[0].ds_addr));
3077 desc->addr_hi = htole32(JME_ADDR_HI(segs[0].ds_addr));
3078 desc->flags = htole32(JME_RD_OWN | JME_RD_INTR | JME_RD_64BIT);
3084 jme_set_vlan(struct jme_softc *sc)
3089 JME_LOCK_ASSERT(sc);
3092 reg = CSR_READ_4(sc, JME_RXMAC);
3093 reg &= ~RXMAC_VLAN_ENB;
3094 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0)
3095 reg |= RXMAC_VLAN_ENB;
3096 CSR_WRITE_4(sc, JME_RXMAC, reg);
3100 jme_set_filter(struct jme_softc *sc)
3103 struct ifmultiaddr *ifma;
3108 JME_LOCK_ASSERT(sc);
3112 rxcfg = CSR_READ_4(sc, JME_RXMAC);
3113 rxcfg &= ~ (RXMAC_BROADCAST | RXMAC_PROMISC | RXMAC_MULTICAST |
3115 /* Always accept frames destined to our station address. */
3116 rxcfg |= RXMAC_UNICAST;
3117 if ((ifp->if_flags & IFF_BROADCAST) != 0)
3118 rxcfg |= RXMAC_BROADCAST;
3119 if ((ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) != 0) {
3120 if ((ifp->if_flags & IFF_PROMISC) != 0)
3121 rxcfg |= RXMAC_PROMISC;
3122 if ((ifp->if_flags & IFF_ALLMULTI) != 0)
3123 rxcfg |= RXMAC_ALLMULTI;
3124 CSR_WRITE_4(sc, JME_MAR0, 0xFFFFFFFF);
3125 CSR_WRITE_4(sc, JME_MAR1, 0xFFFFFFFF);
3126 CSR_WRITE_4(sc, JME_RXMAC, rxcfg);
3131 * Set up the multicast address filter by passing all multicast
3132 * addresses through a CRC generator, and then using the low-order
3133 * 6 bits as an index into the 64 bit multicast hash table. The
3134 * high order bits select the register, while the rest of the bits
3135 * select the bit within the register.
3137 rxcfg |= RXMAC_MULTICAST;
3138 bzero(mchash, sizeof(mchash));
3140 if_maddr_rlock(ifp);
3141 TAILQ_FOREACH(ifma, &sc->jme_ifp->if_multiaddrs, ifma_link) {
3142 if (ifma->ifma_addr->sa_family != AF_LINK)
3144 crc = ether_crc32_be(LLADDR((struct sockaddr_dl *)
3145 ifma->ifma_addr), ETHER_ADDR_LEN);
3147 /* Just want the 6 least significant bits. */
3150 /* Set the corresponding bit in the hash table. */
3151 mchash[crc >> 5] |= 1 << (crc & 0x1f);
3153 if_maddr_runlock(ifp);
3155 CSR_WRITE_4(sc, JME_MAR0, mchash[0]);
3156 CSR_WRITE_4(sc, JME_MAR1, mchash[1]);
3157 CSR_WRITE_4(sc, JME_RXMAC, rxcfg);
3161 jme_stats_clear(struct jme_softc *sc)
3164 JME_LOCK_ASSERT(sc);
3166 if ((sc->jme_flags & JME_FLAG_HWMIB) == 0)
3169 /* Disable and clear counters. */
3170 CSR_WRITE_4(sc, JME_STATCSR, 0xFFFFFFFF);
3171 /* Activate hw counters. */
3172 CSR_WRITE_4(sc, JME_STATCSR, 0);
3173 CSR_READ_4(sc, JME_STATCSR);
3174 bzero(&sc->jme_stats, sizeof(struct jme_hw_stats));
3178 jme_stats_save(struct jme_softc *sc)
3181 JME_LOCK_ASSERT(sc);
3183 if ((sc->jme_flags & JME_FLAG_HWMIB) == 0)
3185 /* Save current counters. */
3186 bcopy(&sc->jme_stats, &sc->jme_ostats, sizeof(struct jme_hw_stats));
3187 /* Disable and clear counters. */
3188 CSR_WRITE_4(sc, JME_STATCSR, 0xFFFFFFFF);
3192 jme_stats_update(struct jme_softc *sc)
3194 struct jme_hw_stats *stat, *ostat;
3197 JME_LOCK_ASSERT(sc);
3199 if ((sc->jme_flags & JME_FLAG_HWMIB) == 0)
3201 stat = &sc->jme_stats;
3202 ostat = &sc->jme_ostats;
3203 stat->tx_good_frames = CSR_READ_4(sc, JME_STAT_TXGOOD);
3204 stat->rx_good_frames = CSR_READ_4(sc, JME_STAT_RXGOOD);
3205 reg = CSR_READ_4(sc, JME_STAT_CRCMII);
3206 stat->rx_crc_errs = (reg & STAT_RX_CRC_ERR_MASK) >>
3207 STAT_RX_CRC_ERR_SHIFT;
3208 stat->rx_mii_errs = (reg & STAT_RX_MII_ERR_MASK) >>
3209 STAT_RX_MII_ERR_SHIFT;
3210 reg = CSR_READ_4(sc, JME_STAT_RXERR);
3211 stat->rx_fifo_oflows = (reg & STAT_RXERR_OFLOW_MASK) >>
3212 STAT_RXERR_OFLOW_SHIFT;
3213 stat->rx_desc_empty = (reg & STAT_RXERR_MPTY_MASK) >>
3214 STAT_RXERR_MPTY_SHIFT;
3215 reg = CSR_READ_4(sc, JME_STAT_FAIL);
3216 stat->rx_bad_frames = (reg & STAT_FAIL_RX_MASK) >> STAT_FAIL_RX_SHIFT;
3217 stat->tx_bad_frames = (reg & STAT_FAIL_TX_MASK) >> STAT_FAIL_TX_SHIFT;
3219 /* Account for previous counters. */
3220 stat->rx_good_frames += ostat->rx_good_frames;
3221 stat->rx_crc_errs += ostat->rx_crc_errs;
3222 stat->rx_mii_errs += ostat->rx_mii_errs;
3223 stat->rx_fifo_oflows += ostat->rx_fifo_oflows;
3224 stat->rx_desc_empty += ostat->rx_desc_empty;
3225 stat->rx_bad_frames += ostat->rx_bad_frames;
3226 stat->tx_good_frames += ostat->tx_good_frames;
3227 stat->tx_bad_frames += ostat->tx_bad_frames;
3231 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high)
3237 value = *(int *)arg1;
3238 error = sysctl_handle_int(oidp, &value, 0, req);
3239 if (error || req->newptr == NULL)
3241 if (value < low || value > high)
3243 *(int *)arg1 = value;
3249 sysctl_hw_jme_tx_coal_to(SYSCTL_HANDLER_ARGS)
3251 return (sysctl_int_range(oidp, arg1, arg2, req,
3252 PCCTX_COAL_TO_MIN, PCCTX_COAL_TO_MAX));
3256 sysctl_hw_jme_tx_coal_pkt(SYSCTL_HANDLER_ARGS)
3258 return (sysctl_int_range(oidp, arg1, arg2, req,
3259 PCCTX_COAL_PKT_MIN, PCCTX_COAL_PKT_MAX));
3263 sysctl_hw_jme_rx_coal_to(SYSCTL_HANDLER_ARGS)
3265 return (sysctl_int_range(oidp, arg1, arg2, req,
3266 PCCRX_COAL_TO_MIN, PCCRX_COAL_TO_MAX));
3270 sysctl_hw_jme_rx_coal_pkt(SYSCTL_HANDLER_ARGS)
3272 return (sysctl_int_range(oidp, arg1, arg2, req,
3273 PCCRX_COAL_PKT_MIN, PCCRX_COAL_PKT_MAX));
3277 sysctl_hw_jme_proc_limit(SYSCTL_HANDLER_ARGS)
3279 return (sysctl_int_range(oidp, arg1, arg2, req,
3280 JME_PROC_MIN, JME_PROC_MAX));