sys/dev/mii/brgphy.c

   1 /*-
   2  * Copyright (c) 2000
   3  *      Bill Paul <wpaul@ee.columbia.edu>.  All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  * 1. Redistributions of source code must retain the above copyright
   9  *    notice, this list of conditions and the following disclaimer.
  10  * 2. Redistributions in binary form must reproduce the above copyright
  11  *    notice, this list of conditions and the following disclaimer in the
  12  *    documentation and/or other materials provided with the distribution.
  13  * 3. All advertising materials mentioning features or use of this software
  14  *    must display the following acknowledgement:
  15  *      This product includes software developed by Bill Paul.
  16  * 4. Neither the name of the author nor the names of any co-contributors
  17  *    may be used to endorse or promote products derived from this software
  18  *    without specific prior written permission.
  19  *
  20  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
  21  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
  24  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  30  * THE POSSIBILITY OF SUCH DAMAGE.
  31  */
  32
  33 #include <sys/cdefs.h>
  34 __FBSDID("$FreeBSD$");
  35
  36 /*
  37  * Driver for the Broadcom BCM54xx/57xx 1000baseTX PHY.
  38  */
  39
  40 #include <sys/param.h>
  41 #include <sys/systm.h>
  42 #include <sys/kernel.h>
  43 #include <sys/module.h>
  44 #include <sys/socket.h>
  45 #include <sys/bus.h>
  46
  47 #include <net/if.h>
  48 #include <net/ethernet.h>
  49 #include <net/if_media.h>
  50
  51 #include <dev/mii/mii.h>
  52 #include <dev/mii/miivar.h>
  53 #include "miidevs.h"
  54
  55 #include <dev/mii/brgphyreg.h>
  56 #include <net/if_arp.h>
  57 #include <machine/bus.h>
  58 #include <dev/bge/if_bgereg.h>
  59 #include <dev/bce/if_bcereg.h>
  60
  61 #include <dev/pci/pcireg.h>
  62 #include <dev/pci/pcivar.h>
  63
  64 #include "miibus_if.h"
  65
  66 static int brgphy_probe(device_t);
  67 static int brgphy_attach(device_t);
  68
  69 struct brgphy_softc {
  70         struct mii_softc mii_sc;
  71         int mii_oui;
  72         int mii_model;
  73         int mii_rev;
  74         int serdes_flags;       /* Keeps track of the serdes type used */
  75 #define BRGPHY_5706S            0x0001
  76 #define BRGPHY_5708S            0x0002
  77 #define BRGPHY_NOANWAIT         0x0004
  78 #define BRGPHY_5709S            0x0008
  79         int bce_phy_flags;      /* PHY flags transferred from the MAC driver */
  80 };
  81
  82 static device_method_t brgphy_methods[] = {
  83         /* device interface */
  84         DEVMETHOD(device_probe,         brgphy_probe),
  85         DEVMETHOD(device_attach,        brgphy_attach),
  86         DEVMETHOD(device_detach,        mii_phy_detach),
  87         DEVMETHOD(device_shutdown,      bus_generic_shutdown),
  88         { 0, 0 }
  89 };
  90
  91 static devclass_t brgphy_devclass;
  92
  93 static driver_t brgphy_driver = {
  94         "brgphy",
  95         brgphy_methods,
  96         sizeof(struct brgphy_softc)
  97 };
  98
  99 DRIVER_MODULE(brgphy, miibus, brgphy_driver, brgphy_devclass, 0, 0);
 100
 101 static int      brgphy_service(struct mii_softc *, struct mii_data *, int);
 102 static void     brgphy_setmedia(struct mii_softc *, int, int);
 103 static void     brgphy_status(struct mii_softc *);
 104 static void     brgphy_mii_phy_auto(struct mii_softc *);
 105 static void     brgphy_reset(struct mii_softc *);
 106 static void     brgphy_enable_loopback(struct mii_softc *);
 107 static void     bcm5401_load_dspcode(struct mii_softc *);
 108 static void     bcm5411_load_dspcode(struct mii_softc *);
 109 static void     bcm54k2_load_dspcode(struct mii_softc *);
 110 static void     brgphy_fixup_5704_a0_bug(struct mii_softc *);
 111 static void     brgphy_fixup_adc_bug(struct mii_softc *);
 112 static void     brgphy_fixup_adjust_trim(struct mii_softc *);
 113 static void     brgphy_fixup_ber_bug(struct mii_softc *);
 114 static void     brgphy_fixup_crc_bug(struct mii_softc *);
 115 static void     brgphy_fixup_jitter_bug(struct mii_softc *);
 116 static void     brgphy_ethernet_wirespeed(struct mii_softc *);
 117 static void     brgphy_jumbo_settings(struct mii_softc *, u_long);
 118
 119 static const struct mii_phydesc brgphys[] = {
 120         MII_PHY_DESC(xxBROADCOM, BCM5400),
 121         MII_PHY_DESC(xxBROADCOM, BCM5401),
 122         MII_PHY_DESC(xxBROADCOM, BCM5411),
 123         MII_PHY_DESC(xxBROADCOM, BCM54K2),
 124         MII_PHY_DESC(xxBROADCOM, BCM5701),
 125         MII_PHY_DESC(xxBROADCOM, BCM5703),
 126         MII_PHY_DESC(xxBROADCOM, BCM5704),
 127         MII_PHY_DESC(xxBROADCOM, BCM5705),
 128         MII_PHY_DESC(xxBROADCOM, BCM5706),
 129         MII_PHY_DESC(xxBROADCOM, BCM5714),
 130         MII_PHY_DESC(xxBROADCOM, BCM5750),
 131         MII_PHY_DESC(xxBROADCOM, BCM5752),
 132         MII_PHY_DESC(xxBROADCOM, BCM5754),
 133         MII_PHY_DESC(xxBROADCOM, BCM5780),
 134         MII_PHY_DESC(xxBROADCOM, BCM5708C),
 135         MII_PHY_DESC(xxBROADCOM_ALT1, BCM5755),
 136         MII_PHY_DESC(xxBROADCOM_ALT1, BCM5787),
 137         MII_PHY_DESC(xxBROADCOM_ALT1, BCM5708S),
 138         MII_PHY_DESC(xxBROADCOM_ALT1, BCM5709CAX),
 139         MII_PHY_DESC(xxBROADCOM_ALT1, BCM5722),
 140         MII_PHY_DESC(xxBROADCOM_ALT1, BCM5784),
 141         MII_PHY_DESC(xxBROADCOM_ALT1, BCM5709C),
 142         MII_PHY_DESC(xxBROADCOM_ALT1, BCM5761),
 143     MII_PHY_DESC(xxBROADCOM_ALT1, BCM5709S),
 144         MII_PHY_DESC(BROADCOM2, BCM5906),
 145         MII_PHY_END
 146 };
 147
 148 #define HS21_PRODUCT_ID "IBM eServer BladeCenter HS21"
 149 #define HS21_BCM_CHIPID 0x57081021
 150
 151 static int
 152 detect_hs21(struct bce_softc *bce_sc)
 153 {
 154         char *sysenv;
 155
 156         if (bce_sc->bce_chipid != HS21_BCM_CHIPID)
 157                 return (0);
 158         sysenv = getenv("smbios.system.product");
 159         if (sysenv == NULL)
 160                 return (0);
 161         if (strncmp(sysenv, HS21_PRODUCT_ID, strlen(HS21_PRODUCT_ID)) != 0)
 162                 return (0);
 163         return (1);
 164 }
 165
 166 /* Search for our PHY in the list of known PHYs */
 167 static int
 168 brgphy_probe(device_t dev)
 169 {
 170         return (mii_phy_dev_probe(dev, brgphys, BUS_PROBE_DEFAULT));
 171 }
 172
 173 /* Attach the PHY to the MII bus */
 174 static int
 175 brgphy_attach(device_t dev)
 176 {
 177         struct brgphy_softc *bsc;
 178         struct bge_softc *bge_sc = NULL;
 179         struct bce_softc *bce_sc = NULL;
 180         struct mii_softc *sc;
 181         struct mii_attach_args *ma;
 182         struct mii_data *mii;
 183         struct ifnet *ifp;
 184         int fast_ether;
 185
 186         bsc = device_get_softc(dev);
 187         sc = &bsc->mii_sc;
 188         ma = device_get_ivars(dev);
 189         sc->mii_dev = device_get_parent(dev);
 190         mii = device_get_softc(sc->mii_dev);
 191         LIST_INSERT_HEAD(&mii->mii_phys, sc, mii_list);
 192
 193         /* Initialize mii_softc structure */
 194         sc->mii_inst = mii->mii_instance;
 195         sc->mii_phy = ma->mii_phyno;
 196         sc->mii_service = brgphy_service;
 197         sc->mii_pdata = mii;
 198         sc->mii_anegticks = MII_ANEGTICKS_GIGE;
 199         sc->mii_flags |= MIIF_NOISOLATE | MIIF_NOLOOP;
 200         mii->mii_instance++;
 201
 202         /* Initialize brgphy_softc structure */
 203         bsc->mii_oui = MII_OUI(ma->mii_id1, ma->mii_id2);
 204         bsc->mii_model = MII_MODEL(ma->mii_id2);
 205         bsc->mii_rev = MII_REV(ma->mii_id2);
 206         bsc->serdes_flags = 0;
 207
 208         fast_ether = 0;
 209
 210         if (bootverbose)
 211                 device_printf(dev, "OUI 0x%06x, model 0x%04x, rev. %d\n",
 212                     bsc->mii_oui, bsc->mii_model, bsc->mii_rev);
 213
 214         /* Handle any special cases based on the PHY ID */
 215         switch (bsc->mii_oui) {
 216         case MII_OUI_BROADCOM:
 217         case MII_OUI_BROADCOM2:
 218                 break;
 219         case MII_OUI_xxBROADCOM:
 220                 switch (bsc->mii_model) {
 221                 case MII_MODEL_xxBROADCOM_BCM5706:
 222                 case MII_MODEL_xxBROADCOM_BCM5714:
 223                         /*
 224                          * The 5464 PHY used in the 5706 supports both copper
 225                          * and fiber interfaces over GMII.  Need to check the
 226                          * shadow registers to see which mode is actually
 227                          * in effect, and therefore whether we have 5706C or
 228                          * 5706S.
 229                          */
 230                         PHY_WRITE(sc, BRGPHY_MII_SHADOW_1C,
 231                                 BRGPHY_SHADOW_1C_MODE_CTRL);
 232                         if (PHY_READ(sc, BRGPHY_MII_SHADOW_1C) &
 233                                 BRGPHY_SHADOW_1C_ENA_1000X) {
 234                                 bsc->serdes_flags |= BRGPHY_5706S;
 235                                 sc->mii_flags |= MIIF_HAVEFIBER;
 236                         }
 237                         break;
 238                 } break;
 239         case MII_OUI_xxBROADCOM_ALT1:
 240                 switch (bsc->mii_model) {
 241                 case MII_MODEL_xxBROADCOM_ALT1_BCM5708S:
 242                         bsc->serdes_flags |= BRGPHY_5708S;
 243                         sc->mii_flags |= MIIF_HAVEFIBER;
 244                         break;
 245         case MII_MODEL_xxBROADCOM_ALT1_BCM5709S:
 246             bsc->serdes_flags |= BRGPHY_5709S;
 247             sc->mii_flags |= MIIF_HAVEFIBER;
 248             break;
 249                 } break;
 250         default:
 251                 device_printf(dev, "Unrecognized OUI for PHY!\n");
 252         }
 253
 254         ifp = sc->mii_pdata->mii_ifp;
 255
 256         /* Find the MAC driver associated with this PHY. */
 257         if (strcmp(ifp->if_dname, "bge") == 0)  {
 258                 bge_sc = ifp->if_softc;
 259         } else if (strcmp(ifp->if_dname, "bce") == 0) {
 260                 bce_sc = ifp->if_softc;
 261         }
 262
 263         /* Todo: Need to add additional controllers such as 5906 & 5787F */
 264         /* The 590x chips are 10/100 only. */
 265         if (bge_sc &&
 266             pci_get_vendor(bge_sc->bge_dev) == BCOM_VENDORID &&
 267             (pci_get_device(bge_sc->bge_dev) == BCOM_DEVICEID_BCM5901 ||
 268             pci_get_device(bge_sc->bge_dev) == BCOM_DEVICEID_BCM5901A2 ||
 269             pci_get_device(bge_sc->bge_dev) == BCOM_DEVICEID_BCM5906 ||
 270             pci_get_device(bge_sc->bge_dev) == BCOM_DEVICEID_BCM5906M)) {
 271                 fast_ether = 1;
 272                 sc->mii_anegticks = MII_ANEGTICKS;
 273         }
 274
 275         brgphy_reset(sc);
 276
 277         /* Read the PHY's capabilities. */
 278         sc->mii_capabilities = PHY_READ(sc, MII_BMSR) & ma->mii_capmask;
 279         if (sc->mii_capabilities & BMSR_EXTSTAT)
 280                 sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR);
 281         device_printf(dev, " ");
 282
 283 #define ADD(m, c)       ifmedia_add(&mii->mii_media, (m), (c), NULL)
 284
 285         /* Create an instance of Ethernet media. */
 286         ADD(IFM_MAKEWORD(IFM_ETHER, IFM_NONE, 0, sc->mii_inst), BMCR_ISO);
 287
 288         /* Add the supported media types */
 289         if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) {
 290                 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_10_T, 0, sc->mii_inst),
 291                         BRGPHY_S10);
 292                 printf("10baseT, ");
 293                 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_10_T, IFM_FDX, sc->mii_inst),
 294                         BRGPHY_S10 | BRGPHY_BMCR_FDX);
 295                 printf("10baseT-FDX, ");
 296                 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_100_TX, 0, sc->mii_inst),
 297                         BRGPHY_S100);
 298                 printf("100baseTX, ");
 299                 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_100_TX, IFM_FDX, sc->mii_inst),
 300                         BRGPHY_S100 | BRGPHY_BMCR_FDX);
 301                 printf("100baseTX-FDX, ");
 302                 if (fast_ether == 0) {
 303                         ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_T, 0, sc->mii_inst),
 304                                 BRGPHY_S1000);
 305                         printf("1000baseT, ");
 306                         ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_T, IFM_FDX, sc->mii_inst),
 307                                 BRGPHY_S1000 | BRGPHY_BMCR_FDX);
 308                         printf("1000baseT-FDX, ");
 309                 }
 310         } else {
 311                 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_SX, IFM_FDX, sc->mii_inst),
 312                         BRGPHY_S1000 | BRGPHY_BMCR_FDX);
 313                 printf("1000baseSX-FDX, ");
 314                 /* 2.5G support is a software enabled feature on the 5708S and 5709S. */
 315                 if (bce_sc && (bce_sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG)) {
 316                         ADD(IFM_MAKEWORD(IFM_ETHER, IFM_2500_SX, IFM_FDX, sc->mii_inst), 0);
 317                         printf("2500baseSX-FDX, ");
 318                 } else if ((bsc->serdes_flags & BRGPHY_5708S) && bce_sc &&
 319                     (detect_hs21(bce_sc) != 0)) {
 320                         /*
 321                          * There appears to be certain silicon revision
 322                          * in IBM HS21 blades that is having issues with
 323                          * this driver wating for the auto-negotiation to
 324                          * complete. This happens with a specific chip id
 325                          * only and when the 1000baseSX-FDX is the only
 326                          * mode. Workaround this issue since it's unlikely
 327                          * to be ever addressed.
 328                          */
 329                         printf("auto-neg workaround, ");
 330                         bsc->serdes_flags |= BRGPHY_NOANWAIT;
 331                 }
 332         }
 333
 334         ADD(IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, sc->mii_inst), 0);
 335         printf("auto\n");
 336
 337 #undef ADD
 338         MIIBUS_MEDIAINIT(sc->mii_dev);
 339         return (0);
 340 }
 341
 342 static int
 343 brgphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd)
 344 {
 345         struct brgphy_softc *bsc = (struct brgphy_softc *)sc;
 346         struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
 347         int error = 0;
 348         int val;
 349
 350         switch (cmd) {
 351         case MII_POLLSTAT:
 352                 /* If we're not polling our PHY instance, just return. */
 353                 if (IFM_INST(ife->ifm_media) != sc->mii_inst)
 354                         goto brgphy_service_exit;
 355                 break;
 356         case MII_MEDIACHG:
 357                 /*
 358                  * If the media indicates a different PHY instance,
 359                  * isolate ourselves.
 360                  */
 361                 if (IFM_INST(ife->ifm_media) != sc->mii_inst) {
 362                         PHY_WRITE(sc, MII_BMCR,
 363                             PHY_READ(sc, MII_BMCR) | BMCR_ISO);
 364                         goto brgphy_service_exit;
 365                 }
 366
 367                 /* If the interface is not up, don't do anything. */
 368                 if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
 369                         break;
 370
 371                 /* Todo: Why is this here?  Is it really needed? */
 372                 brgphy_reset(sc);       /* XXX hardware bug work-around */
 373
 374                 switch (IFM_SUBTYPE(ife->ifm_media)) {
 375                 case IFM_AUTO:
 376                         brgphy_mii_phy_auto(sc);
 377                         break;
 378                 case IFM_2500_SX:
 379                 case IFM_1000_SX:
 380                 case IFM_1000_T:
 381                 case IFM_100_TX:
 382                 case IFM_10_T:
 383                         brgphy_setmedia(sc, ife->ifm_media,
 384                             mii->mii_ifp->if_flags & IFF_LINK0);
 385                         break;
 386                 default:
 387                         error = EINVAL;
 388                         goto brgphy_service_exit;
 389                 }
 390                 break;
 391         case MII_TICK:
 392                 /* Bail if we're not currently selected. */
 393                 if (IFM_INST(ife->ifm_media) != sc->mii_inst)
 394                         goto brgphy_service_exit;
 395
 396                 /* Bail if the interface isn't up. */
 397                 if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
 398                         goto brgphy_service_exit;
 399
 400
 401                 /* Bail if autoneg isn't in process. */
 402                 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) {
 403                         sc->mii_ticks = 0;
 404                         break;
 405                 }
 406
 407                 /*
 408                  * Check to see if we have link.  If we do, we don't
 409                  * need to restart the autonegotiation process.
 410                  */
 411                 val     = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR);
 412                 if (val & BMSR_LINK) {
 413                         sc->mii_ticks = 0;      /* Reset autoneg timer. */
 414                         break;
 415                 }
 416
 417                 /* Announce link loss right after it happens. */
 418                 if (sc->mii_ticks++ == 0)
 419                         break;
 420
 421                 /* Only retry autonegotiation every mii_anegticks seconds. */
 422                 if (sc->mii_ticks <= sc->mii_anegticks)
 423                         break;
 424
 425
 426                 /* Retry autonegotiation */
 427                 sc->mii_ticks = 0;
 428                 brgphy_mii_phy_auto(sc);
 429                 break;
 430         }
 431
 432         /* Update the media status. */
 433         brgphy_status(sc);
 434
 435         /*
 436          * Callback if something changed. Note that we need to poke
 437          * the DSP on the Broadcom PHYs if the media changes.
 438          */
 439         if (sc->mii_media_active != mii->mii_media_active ||
 440             sc->mii_media_status != mii->mii_media_status ||
 441             cmd == MII_MEDIACHG) {
 442                 switch (bsc->mii_oui) {
 443                 case MII_OUI_BROADCOM:
 444                         break;
 445                 case MII_OUI_xxBROADCOM:
 446                         switch (bsc->mii_model) {
 447                         case MII_MODEL_xxBROADCOM_BCM5400:
 448                                 bcm5401_load_dspcode(sc);
 449                                 break;
 450                         case MII_MODEL_xxBROADCOM_BCM5401:
 451                                 if (bsc->mii_rev == 1 || bsc->mii_rev == 3)
 452                                         bcm5401_load_dspcode(sc);
 453                                 break;
 454                         case MII_MODEL_xxBROADCOM_BCM5411:
 455                                 bcm5411_load_dspcode(sc);
 456                                 break;
 457                         case MII_MODEL_xxBROADCOM_BCM54K2:
 458                                 bcm54k2_load_dspcode(sc);
 459                                 break;
 460                         }
 461                         break;
 462                 case MII_OUI_xxBROADCOM_ALT1:
 463                         break;
 464                 }
 465         }
 466         mii_phy_update(sc, cmd);
 467 brgphy_service_exit:
 468         return (error);
 469 }
 470
 471
 472 /****************************************************************************/
 473 /* Sets the PHY link speed.                                                 */
 474 /*                                                                          */
 475 /* Returns:                                                                 */
 476 /*   None                                                                   */
 477 /****************************************************************************/
 478 static void
 479 brgphy_setmedia(struct mii_softc *sc, int media, int master)
 480 {
 481         struct brgphy_softc *bsc = (struct brgphy_softc *)sc;
 482         int bmcr = 0, gig;
 483
 484         /* Calculate the value for the BMCR register. */
 485         switch (IFM_SUBTYPE(media)) {
 486         case IFM_2500_SX:
 487                 break;
 488         case IFM_1000_SX:
 489         case IFM_1000_T:
 490                 bmcr = BRGPHY_S1000;
 491                 break;
 492         case IFM_100_TX:
 493                 bmcr = BRGPHY_S100;
 494                 break;
 495         case IFM_10_T:
 496         default:
 497                 bmcr = BRGPHY_S10;
 498                 break;
 499         }
 500
 501         /* Calculate duplex settings for 1000BasetT/1000BaseX. */
 502         if ((media & IFM_GMASK) == IFM_FDX) {
 503                 bmcr |= BRGPHY_BMCR_FDX;
 504                 gig = BRGPHY_1000CTL_AFD;
 505         } else {
 506                 gig = BRGPHY_1000CTL_AHD;
 507         }
 508
 509         /* Force loopback to disconnect PHY for Ethernet medium. */
 510         brgphy_enable_loopback(sc);
 511
 512         /* Disable 1000BaseT advertisements. */
 513         PHY_WRITE(sc, BRGPHY_MII_1000CTL, 0);
 514         /* Disable 10/100 advertisements. */
 515         PHY_WRITE(sc, BRGPHY_MII_ANAR, BRGPHY_SEL_TYPE);
 516         /* Write forced link speed. */
 517         PHY_WRITE(sc, BRGPHY_MII_BMCR, bmcr);
 518
 519         /* If 10/100 only then configuration is complete. */
 520         if ((IFM_SUBTYPE(media) != IFM_1000_T) && (IFM_SUBTYPE(media) != IFM_1000_SX))
 521                 goto brgphy_setmedia_exit;
 522
 523         /* Set duplex speed advertisement for 1000BaseT/1000BaseX. */
 524         PHY_WRITE(sc, BRGPHY_MII_1000CTL, gig);
 525         /* Restart auto-negotiation for 1000BaseT/1000BaseX. */
 526         PHY_WRITE(sc, BRGPHY_MII_BMCR,
 527             bmcr | BRGPHY_BMCR_AUTOEN | BRGPHY_BMCR_STARTNEG);
 528
 529         /* If not 5701 PHY then configuration is complete. */
 530         if (bsc->mii_model != MII_MODEL_xxBROADCOM_BCM5701)
 531                 goto brgphy_setmedia_exit;
 532
 533         /*
 534          * When setting the link manually, one side must be the master and
 535          * the other the slave. However ifmedia doesn't give us a good way
 536          * to specify this, so we fake it by using one of the LINK flags.
 537          * If LINK0 is set, we program the PHY to be a master, otherwise
 538          * it's a slave.
 539          */
 540         if (master) {
 541                 PHY_WRITE(sc, BRGPHY_MII_1000CTL,
 542                     gig | BRGPHY_1000CTL_MSE | BRGPHY_1000CTL_MSC);
 543         } else {
 544                 PHY_WRITE(sc, BRGPHY_MII_1000CTL,
 545                     gig | BRGPHY_1000CTL_MSE);
 546         }
 547
 548 brgphy_setmedia_exit:
 549         return;
 550 }
 551
 552 /****************************************************************************/
 553 /* Set the media status based on the PHY settings.                          */
 554 /* IFM_FLAG0 = 0 (RX flow control disabled) | 1 (enabled)                   */
 555 /* IFM_FLAG1 = 0 (TX flow control disabled) | 1 (enabled)                   */
 556 /*                                                                          */
 557 /* Returns:                                                                 */
 558 /*   None                                                                   */
 559 /****************************************************************************/
 560 static void
 561 brgphy_status(struct mii_softc *sc)
 562 {
 563         struct brgphy_softc *bsc = (struct brgphy_softc *)sc;
 564         struct mii_data *mii = sc->mii_pdata;
 565         int aux, bmcr, bmsr, anar, anlpar, xstat, val;
 566
 567
 568         mii->mii_media_status = IFM_AVALID;
 569         mii->mii_media_active = IFM_ETHER;
 570
 571         bmsr = PHY_READ(sc, BRGPHY_MII_BMSR) | PHY_READ(sc, BRGPHY_MII_BMSR);
 572         bmcr = PHY_READ(sc, BRGPHY_MII_BMCR);
 573         anar = PHY_READ(sc, BRGPHY_MII_ANAR);
 574         anlpar = PHY_READ(sc, BRGPHY_MII_ANLPAR);
 575
 576         /* Loopback is enabled. */
 577         if (bmcr & BRGPHY_BMCR_LOOP) {
 578
 579                 mii->mii_media_active |= IFM_LOOP;
 580         }
 581
 582         /* Autoneg is still in progress. */
 583         if ((bmcr & BRGPHY_BMCR_AUTOEN) &&
 584             (bmsr & BRGPHY_BMSR_ACOMP) == 0 &&
 585             (bsc->serdes_flags & BRGPHY_NOANWAIT) == 0) {
 586                 /* Erg, still trying, I guess... */
 587                 mii->mii_media_active |= IFM_NONE;
 588                 goto brgphy_status_exit;
 589         }
 590
 591         /* Autoneg is enabled and complete, link should be up. */
 592         if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) {
 593                 aux = PHY_READ(sc, BRGPHY_MII_AUXSTS);
 594
 595                 /* If copper link is up, get the negotiated speed/duplex. */
 596                 if (aux & BRGPHY_AUXSTS_LINK) {
 597                         mii->mii_media_status |= IFM_ACTIVE;
 598                         switch (aux & BRGPHY_AUXSTS_AN_RES) {
 599                         case BRGPHY_RES_1000FD:
 600                                 mii->mii_media_active |= IFM_1000_T | IFM_FDX;  break;
 601                         case BRGPHY_RES_1000HD:
 602                                 mii->mii_media_active |= IFM_1000_T | IFM_HDX;  break;
 603                         case BRGPHY_RES_100FD:
 604                                 mii->mii_media_active |= IFM_100_TX | IFM_FDX; break;
 605                         case BRGPHY_RES_100T4:
 606                                 mii->mii_media_active |= IFM_100_T4; break;
 607                         case BRGPHY_RES_100HD:
 608                                 mii->mii_media_active |= IFM_100_TX | IFM_HDX;  break;
 609                         case BRGPHY_RES_10FD:
 610                                 mii->mii_media_active |= IFM_10_T | IFM_FDX; break;
 611                         case BRGPHY_RES_10HD:
 612                                 mii->mii_media_active |= IFM_10_T | IFM_HDX; break;
 613                         default:
 614                                 mii->mii_media_active |= IFM_NONE; break;
 615                         }
 616                 }
 617         } else {
 618                 /* If serdes link is up, get the negotiated speed/duplex. */
 619                 if (bmsr & BRGPHY_BMSR_LINK) {
 620                         mii->mii_media_status |= IFM_ACTIVE;
 621                 }
 622
 623                 /* Check the link speed/duplex based on the PHY type. */
 624                 if (bsc->serdes_flags & BRGPHY_5706S) {
 625                         mii->mii_media_active |= IFM_1000_SX;
 626
 627                         /* If autoneg enabled, read negotiated duplex settings */
 628                         if (bmcr & BRGPHY_BMCR_AUTOEN) {
 629                                 val = PHY_READ(sc, BRGPHY_SERDES_ANAR) & PHY_READ(sc, BRGPHY_SERDES_ANLPAR);
 630                                 if (val & BRGPHY_SERDES_ANAR_FDX)
 631                                         mii->mii_media_active |= IFM_FDX;
 632                                 else
 633                                         mii->mii_media_active |= IFM_HDX;
 634                         }
 635
 636                 } else if (bsc->serdes_flags & BRGPHY_5708S) {
 637                         PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, BRGPHY_5708S_DIG_PG0);
 638                         xstat = PHY_READ(sc, BRGPHY_5708S_PG0_1000X_STAT1);
 639
 640             /* Check for MRBE auto-negotiated speed results. */
 641                         switch (xstat & BRGPHY_5708S_PG0_1000X_STAT1_SPEED_MASK) {
 642                         case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_10:
 643                                 mii->mii_media_active |= IFM_10_FL; break;
 644                         case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_100:
 645                                 mii->mii_media_active |= IFM_100_FX; break;
 646                         case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_1G:
 647                                 mii->mii_media_active |= IFM_1000_SX; break;
 648                         case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_25G:
 649                                 mii->mii_media_active |= IFM_2500_SX; break;
 650                         }
 651
 652             /* Check for MRBE auto-negotiated duplex results. */
 653                         if (xstat & BRGPHY_5708S_PG0_1000X_STAT1_FDX)
 654                                 mii->mii_media_active |= IFM_FDX;
 655                         else
 656                                 mii->mii_media_active |= IFM_HDX;
 657
 658         } else if (bsc->serdes_flags & BRGPHY_5709S) {
 659
 660             /* Select GP Status Block of the AN MMD, get autoneg results. */
 661             PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_GP_STATUS);
 662                         xstat = PHY_READ(sc, BRGPHY_GP_STATUS_TOP_ANEG_STATUS);
 663
 664             /* Restore IEEE0 block (assumed in all brgphy(4) code). */
 665             PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_COMBO_IEEE0);
 666
 667             /* Check for MRBE auto-negotiated speed results. */
 668             switch (xstat & BRGPHY_GP_STATUS_TOP_ANEG_SPEED_MASK) {
 669                         case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_10:
 670                                 mii->mii_media_active |= IFM_10_FL; break;
 671                         case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_100:
 672                                 mii->mii_media_active |= IFM_100_FX; break;
 673                         case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_1G:
 674                                 mii->mii_media_active |= IFM_1000_SX; break;
 675                         case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_25G:
 676                                 mii->mii_media_active |= IFM_2500_SX; break;
 677                         }
 678
 679             /* Check for MRBE auto-negotiated duplex results. */
 680                         if (xstat & BRGPHY_GP_STATUS_TOP_ANEG_FDX)
 681                                 mii->mii_media_active |= IFM_FDX;
 682                         else
 683                                 mii->mii_media_active |= IFM_HDX;
 684         }
 685
 686         }
 687
 688 #if 0
 689         /* Todo: Change bge/bce to use these settings. */
 690
 691         /* Fetch flow control settings from the PHY */
 692         if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) {
 693                 /* Set FLAG0 is RX is enabled and FLAG1 if TX is enabled */
 694                 if ((anar & BRGPHY_ANAR_PC) && (anlpar & BRGPHY_ANLPAR_PC)) {
 695                         mii->mii_media_active |= IFM_FLAG0 | IFM_FLAG1;
 696                 } else if (!(anar & BRGPHY_ANAR_PC) && (anlpar & BRGPHY_ANAR_ASP) &&
 697                     (anlpar & BRPHY_ANLPAR_PC) && (anlpar & BRGPHY_ANLPAR_ASP)) {
 698                         mii->mii_media_active |= IFM_FLAG1;
 699                 } else if ((anar & BRGPHY_ANAR_PC) && (anar & BRGPHY_ANAR_ASP) &&
 700                     !(anlpar & BRGPHY_ANLPAR_PC) && (anlpar & BRGPHY_ANLPAR_ASP)) {
 701                         mii->mii_media_active |= IFM_FLAG0;
 702                 }
 703         }
 704
 705         /* Todo: Add support for fiber settings too. */
 706 #endif
 707
 708
 709 brgphy_status_exit:
 710         return;
 711 }
 712
 713 static void
 714 brgphy_mii_phy_auto(struct mii_softc *sc)
 715 {
 716         struct brgphy_softc *bsc = (struct brgphy_softc *)sc;
 717         int ktcr = 0;
 718
 719         brgphy_reset(sc);
 720
 721         /* Enable flow control in the advertisement register. */
 722         if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) {
 723                 /* Pause capability advertisement (pause capable & asymmetric) */
 724                 PHY_WRITE(sc, BRGPHY_MII_ANAR,
 725                 BMSR_MEDIA_TO_ANAR(sc->mii_capabilities) | ANAR_CSMA |
 726                 BRGPHY_ANAR_ASP | BRGPHY_ANAR_PC);
 727         } else {
 728                 PHY_WRITE(sc, BRGPHY_SERDES_ANAR, BRGPHY_SERDES_ANAR_FDX |
 729                         BRGPHY_SERDES_ANAR_HDX | BRGPHY_SERDES_ANAR_BOTH_PAUSE);
 730         }
 731
 732         /* Enable speed in the 1000baseT control register */
 733         ktcr = BRGPHY_1000CTL_AFD | BRGPHY_1000CTL_AHD;
 734         if (bsc->mii_model == MII_MODEL_xxBROADCOM_BCM5701)
 735                 ktcr |= BRGPHY_1000CTL_MSE | BRGPHY_1000CTL_MSC;
 736         PHY_WRITE(sc, BRGPHY_MII_1000CTL, ktcr);
 737         ktcr = PHY_READ(sc, BRGPHY_MII_1000CTL);
 738
 739         /* Start autonegotiation */
 740         PHY_WRITE(sc, BRGPHY_MII_BMCR,BRGPHY_BMCR_AUTOEN | BRGPHY_BMCR_STARTNEG);
 741         PHY_WRITE(sc, BRGPHY_MII_IMR, 0xFF00);
 742
 743 }
 744
 745
 746 /* Enable loopback to force the link down. */
 747 static void
 748 brgphy_enable_loopback(struct mii_softc *sc)
 749 {
 750         int i;
 751
 752         PHY_WRITE(sc, BRGPHY_MII_BMCR, BRGPHY_BMCR_LOOP);
 753         for (i = 0; i < 15000; i++) {
 754                 if (!(PHY_READ(sc, BRGPHY_MII_BMSR) & BRGPHY_BMSR_LINK))
 755                         break;
 756                 DELAY(10);
 757         }
 758 }
 759
 760 /* Turn off tap power management on 5401. */
 761 static void
 762 bcm5401_load_dspcode(struct mii_softc *sc)
 763 {
 764         static const struct {
 765                 int             reg;
 766                 uint16_t        val;
 767         } dspcode[] = {
 768                 { BRGPHY_MII_AUXCTL,            0x0c20 },
 769                 { BRGPHY_MII_DSP_ADDR_REG,      0x0012 },
 770                 { BRGPHY_MII_DSP_RW_PORT,       0x1804 },
 771                 { BRGPHY_MII_DSP_ADDR_REG,      0x0013 },
 772                 { BRGPHY_MII_DSP_RW_PORT,       0x1204 },
 773                 { BRGPHY_MII_DSP_ADDR_REG,      0x8006 },
 774                 { BRGPHY_MII_DSP_RW_PORT,       0x0132 },
 775                 { BRGPHY_MII_DSP_ADDR_REG,      0x8006 },
 776                 { BRGPHY_MII_DSP_RW_PORT,       0x0232 },
 777                 { BRGPHY_MII_DSP_ADDR_REG,      0x201f },
 778                 { BRGPHY_MII_DSP_RW_PORT,       0x0a20 },
 779                 { 0,                            0 },
 780         };
 781         int i;
 782
 783         for (i = 0; dspcode[i].reg != 0; i++)
 784                 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
 785         DELAY(40);
 786 }
 787
 788 static void
 789 bcm5411_load_dspcode(struct mii_softc *sc)
 790 {
 791         static const struct {
 792                 int             reg;
 793                 uint16_t        val;
 794         } dspcode[] = {
 795                 { 0x1c,                         0x8c23 },
 796                 { 0x1c,                         0x8ca3 },
 797                 { 0x1c,                         0x8c23 },
 798                 { 0,                            0 },
 799         };
 800         int i;
 801
 802         for (i = 0; dspcode[i].reg != 0; i++)
 803                 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
 804 }
 805
 806 void
 807 bcm54k2_load_dspcode(struct mii_softc *sc)
 808 {
 809         static const struct {
 810                 int             reg;
 811                 uint16_t        val;
 812         } dspcode[] = {
 813                 { 4,                            0x01e1 },
 814                 { 9,                            0x0300 },
 815                 { 0,                            0 },
 816         };
 817         int i;
 818
 819         for (i = 0; dspcode[i].reg != 0; i++)
 820                 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
 821
 822 }
 823
 824 static void
 825 brgphy_fixup_5704_a0_bug(struct mii_softc *sc)
 826 {
 827         static const struct {
 828                 int             reg;
 829                 uint16_t        val;
 830         } dspcode[] = {
 831                 { 0x1c,                         0x8d68 },
 832                 { 0x1c,                         0x8d68 },
 833                 { 0,                            0 },
 834         };
 835         int i;
 836
 837         for (i = 0; dspcode[i].reg != 0; i++)
 838                 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
 839 }
 840
 841 static void
 842 brgphy_fixup_adc_bug(struct mii_softc *sc)
 843 {
 844         static const struct {
 845                 int             reg;
 846                 uint16_t        val;
 847         } dspcode[] = {
 848                 { BRGPHY_MII_AUXCTL,            0x0c00 },
 849                 { BRGPHY_MII_DSP_ADDR_REG,      0x201f },
 850                 { BRGPHY_MII_DSP_RW_PORT,       0x2aaa },
 851                 { 0,                            0 },
 852         };
 853         int i;
 854
 855         for (i = 0; dspcode[i].reg != 0; i++)
 856                 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
 857 }
 858
 859 static void
 860 brgphy_fixup_adjust_trim(struct mii_softc *sc)
 861 {
 862         static const struct {
 863                 int             reg;
 864                 uint16_t        val;
 865         } dspcode[] = {
 866                 { BRGPHY_MII_AUXCTL,            0x0c00 },
 867                 { BRGPHY_MII_DSP_ADDR_REG,      0x000a },
 868                 { BRGPHY_MII_DSP_RW_PORT,       0x110b },
 869                 { BRGPHY_MII_TEST1,                     0x0014 },
 870                 { BRGPHY_MII_AUXCTL,            0x0400 },
 871                 { 0,                            0 },
 872         };
 873         int i;
 874
 875         for (i = 0; dspcode[i].reg != 0; i++)
 876                 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
 877 }
 878
 879 static void
 880 brgphy_fixup_ber_bug(struct mii_softc *sc)
 881 {
 882         static const struct {
 883                 int             reg;
 884                 uint16_t        val;
 885         } dspcode[] = {
 886                 { BRGPHY_MII_AUXCTL,            0x0c00 },
 887                 { BRGPHY_MII_DSP_ADDR_REG,      0x000a },
 888                 { BRGPHY_MII_DSP_RW_PORT,       0x310b },
 889                 { BRGPHY_MII_DSP_ADDR_REG,      0x201f },
 890                 { BRGPHY_MII_DSP_RW_PORT,       0x9506 },
 891                 { BRGPHY_MII_DSP_ADDR_REG,      0x401f },
 892                 { BRGPHY_MII_DSP_RW_PORT,       0x14e2 },
 893                 { BRGPHY_MII_AUXCTL,            0x0400 },
 894                 { 0,                            0 },
 895         };
 896         int i;
 897
 898         for (i = 0; dspcode[i].reg != 0; i++)
 899                 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
 900 }
 901
 902 static void
 903 brgphy_fixup_crc_bug(struct mii_softc *sc)
 904 {
 905         static const struct {
 906                 int             reg;
 907                 uint16_t        val;
 908         } dspcode[] = {
 909                 { BRGPHY_MII_DSP_RW_PORT,       0x0a75 },
 910                 { 0x1c,                         0x8c68 },
 911                 { 0x1c,                         0x8d68 },
 912                 { 0x1c,                         0x8c68 },
 913                 { 0,                            0 },
 914         };
 915         int i;
 916
 917         for (i = 0; dspcode[i].reg != 0; i++)
 918                 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
 919 }
 920
 921 static void
 922 brgphy_fixup_jitter_bug(struct mii_softc *sc)
 923 {
 924         static const struct {
 925                 int             reg;
 926                 uint16_t        val;
 927         } dspcode[] = {
 928                 { BRGPHY_MII_AUXCTL,            0x0c00 },
 929                 { BRGPHY_MII_DSP_ADDR_REG,      0x000a },
 930                 { BRGPHY_MII_DSP_RW_PORT,       0x010b },
 931                 { BRGPHY_MII_AUXCTL,            0x0400 },
 932                 { 0,                            0 },
 933         };
 934         int i;
 935
 936         for (i = 0; dspcode[i].reg != 0; i++)
 937                 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
 938 }
 939
 940
 941 static void
 942 brgphy_fixup_disable_early_dac(struct mii_softc *sc)
 943 {
 944         uint32_t val;
 945
 946         PHY_WRITE(sc, BRGPHY_MII_DSP_ADDR_REG, 0x0f08);
 947         val = PHY_READ(sc, BRGPHY_MII_DSP_RW_PORT);
 948         val &= ~(1 << 8);
 949         PHY_WRITE(sc, BRGPHY_MII_DSP_RW_PORT, val);
 950
 951 }
 952
 953
 954 static void
 955 brgphy_ethernet_wirespeed(struct mii_softc *sc)
 956 {
 957         uint32_t        val;
 958
 959         /* Enable Ethernet@WireSpeed. */
 960         PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7007);
 961         val = PHY_READ(sc, BRGPHY_MII_AUXCTL);
 962         PHY_WRITE(sc, BRGPHY_MII_AUXCTL, val | (1 << 15) | (1 << 4));
 963 }
 964
 965
 966 static void
 967 brgphy_jumbo_settings(struct mii_softc *sc, u_long mtu)
 968 {
 969         struct brgphy_softc *bsc = (struct brgphy_softc *)sc;
 970         uint32_t        val;
 971
 972         /* Set or clear jumbo frame settings in the PHY. */
 973         if (mtu > ETHER_MAX_LEN) {
 974                 if (bsc->mii_model == MII_MODEL_xxBROADCOM_BCM5401) {
 975                         /* BCM5401 PHY cannot read-modify-write. */
 976                         PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x4c20);
 977                 } else {
 978                         PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7);
 979                         val = PHY_READ(sc, BRGPHY_MII_AUXCTL);
 980                         PHY_WRITE(sc, BRGPHY_MII_AUXCTL,
 981                             val | BRGPHY_AUXCTL_LONG_PKT);
 982                 }
 983
 984                 val = PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL);
 985                 PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL,
 986                     val | BRGPHY_PHY_EXTCTL_HIGH_LA);
 987         } else {
 988                 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7);
 989                 val = PHY_READ(sc, BRGPHY_MII_AUXCTL);
 990                 PHY_WRITE(sc, BRGPHY_MII_AUXCTL,
 991                     val & ~(BRGPHY_AUXCTL_LONG_PKT | 0x7));
 992
 993                 val = PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL);
 994                 PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL,
 995                         val & ~BRGPHY_PHY_EXTCTL_HIGH_LA);
 996         }
 997 }
 998
 999 static void
1000 brgphy_reset(struct mii_softc *sc)
1001 {
1002         struct brgphy_softc *bsc = (struct brgphy_softc *)sc;
1003         struct bge_softc *bge_sc = NULL;
1004         struct bce_softc *bce_sc = NULL;
1005         struct ifnet *ifp;
1006     int val;
1007
1008         /* Perform a standard PHY reset. */
1009         mii_phy_reset(sc);
1010
1011         /* Handle any PHY specific procedures following the reset. */
1012         switch (bsc->mii_oui) {
1013         case MII_OUI_BROADCOM:
1014                 break;
1015         case MII_OUI_xxBROADCOM:
1016                 switch (bsc->mii_model) {
1017                 case MII_MODEL_xxBROADCOM_BCM5400:
1018                         bcm5401_load_dspcode(sc);
1019                         break;
1020                 case MII_MODEL_xxBROADCOM_BCM5401:
1021                         if (bsc->mii_rev == 1 || bsc->mii_rev == 3)
1022                                 bcm5401_load_dspcode(sc);
1023                         break;
1024                 case MII_MODEL_xxBROADCOM_BCM5411:
1025                         bcm5411_load_dspcode(sc);
1026                         break;
1027                 case MII_MODEL_xxBROADCOM_BCM54K2:
1028                         bcm54k2_load_dspcode(sc);
1029                         break;
1030                 }
1031                 break;
1032         case MII_OUI_xxBROADCOM_ALT1:
1033                 break;
1034         }
1035
1036         ifp = sc->mii_pdata->mii_ifp;
1037
1038         /* Find the driver associated with this PHY. */
1039         if (strcmp(ifp->if_dname, "bge") == 0)  {
1040                 bge_sc = ifp->if_softc;
1041         } else if (strcmp(ifp->if_dname, "bce") == 0) {
1042                 bce_sc = ifp->if_softc;
1043         }
1044
1045         /* Handle any bge (NetXtreme/NetLink) workarounds. */
1046         if (bge_sc) {
1047                 /* Fix up various bugs */
1048                 if (bge_sc->bge_flags & BGE_FLAG_5704_A0_BUG)
1049                         brgphy_fixup_5704_a0_bug(sc);
1050                 if (bge_sc->bge_flags & BGE_FLAG_ADC_BUG)
1051                         brgphy_fixup_adc_bug(sc);
1052                 if (bge_sc->bge_flags & BGE_FLAG_ADJUST_TRIM)
1053                         brgphy_fixup_adjust_trim(sc);
1054                 if (bge_sc->bge_flags & BGE_FLAG_BER_BUG)
1055                         brgphy_fixup_ber_bug(sc);
1056                 if (bge_sc->bge_flags & BGE_FLAG_CRC_BUG)
1057                         brgphy_fixup_crc_bug(sc);
1058                 if (bge_sc->bge_flags & BGE_FLAG_JITTER_BUG)
1059                         brgphy_fixup_jitter_bug(sc);
1060
1061                 brgphy_jumbo_settings(sc, ifp->if_mtu);
1062
1063                 if (bge_sc->bge_flags & BGE_FLAG_WIRESPEED)
1064                         brgphy_ethernet_wirespeed(sc);
1065
1066                 /* Enable Link LED on Dell boxes */
1067                 if (bge_sc->bge_flags & BGE_FLAG_NO_3LED) {
1068                         PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL,
1069                             PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL) &
1070                             ~BRGPHY_PHY_EXTCTL_3_LED);
1071                 }
1072
1073                 /* Adjust output voltage (From Linux driver) */
1074                 if (bge_sc->bge_asicrev == BGE_ASICREV_BCM5906)
1075                         PHY_WRITE(sc, BRGPHY_MII_EPHY_PTEST, 0x12);
1076
1077         /* Handle any bce (NetXtreme II) workarounds. */
1078         } else if (bce_sc) {
1079
1080                 if (BCE_CHIP_NUM(bce_sc) == BCE_CHIP_NUM_5708 &&
1081                         (bce_sc->bce_phy_flags & BCE_PHY_SERDES_FLAG)) {
1082
1083                         /* Store autoneg capabilities/results in digital block (Page 0) */
1084                         PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, BRGPHY_5708S_DIG3_PG2);
1085                         PHY_WRITE(sc, BRGPHY_5708S_PG2_DIGCTL_3_0,
1086                                 BRGPHY_5708S_PG2_DIGCTL_3_0_USE_IEEE);
1087                         PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, BRGPHY_5708S_DIG_PG0);
1088
1089                         /* Enable fiber mode and autodetection */
1090                         PHY_WRITE(sc, BRGPHY_5708S_PG0_1000X_CTL1,
1091                                 PHY_READ(sc, BRGPHY_5708S_PG0_1000X_CTL1) |
1092                                 BRGPHY_5708S_PG0_1000X_CTL1_AUTODET_EN |
1093                                 BRGPHY_5708S_PG0_1000X_CTL1_FIBER_MODE);
1094
1095                         /* Enable parallel detection */
1096                         PHY_WRITE(sc, BRGPHY_5708S_PG0_1000X_CTL2,
1097                                 PHY_READ(sc, BRGPHY_5708S_PG0_1000X_CTL2) |
1098                                 BRGPHY_5708S_PG0_1000X_CTL2_PAR_DET_EN);
1099
1100                         /* Advertise 2.5G support through next page during autoneg */
1101                         if (bce_sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG)
1102                                 PHY_WRITE(sc, BRGPHY_5708S_ANEG_NXT_PG_XMIT1,
1103                                         PHY_READ(sc, BRGPHY_5708S_ANEG_NXT_PG_XMIT1) |
1104                                         BRGPHY_5708S_ANEG_NXT_PG_XMIT1_25G);
1105
1106                         /* Increase TX signal amplitude */
1107                         if ((BCE_CHIP_ID(bce_sc) == BCE_CHIP_ID_5708_A0) ||
1108                             (BCE_CHIP_ID(bce_sc) == BCE_CHIP_ID_5708_B0) ||
1109                             (BCE_CHIP_ID(bce_sc) == BCE_CHIP_ID_5708_B1)) {
1110                                 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR,
1111                                         BRGPHY_5708S_TX_MISC_PG5);
1112                                 PHY_WRITE(sc, BRGPHY_5708S_PG5_TXACTL1,
1113                                         PHY_READ(sc, BRGPHY_5708S_PG5_TXACTL1) & ~0x30);
1114                                 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR,
1115                                         BRGPHY_5708S_DIG_PG0);
1116                         }
1117
1118                         /* Backplanes use special driver/pre-driver/pre-emphasis values. */
1119                         if ((bce_sc->bce_shared_hw_cfg & BCE_SHARED_HW_CFG_PHY_BACKPLANE) &&
1120                                 (bce_sc->bce_port_hw_cfg & BCE_PORT_HW_CFG_CFG_TXCTL3_MASK)) {
1121                                         PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR,
1122                                                 BRGPHY_5708S_TX_MISC_PG5);
1123                                         PHY_WRITE(sc, BRGPHY_5708S_PG5_TXACTL3,
1124                                                 bce_sc->bce_port_hw_cfg &
1125                                                 BCE_PORT_HW_CFG_CFG_TXCTL3_MASK);
1126                                         PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR,
1127                                                 BRGPHY_5708S_DIG_PG0);
1128                         }
1129                 } else if (BCE_CHIP_NUM(bce_sc) == BCE_CHIP_NUM_5709 &&
1130                         (bce_sc->bce_phy_flags & BCE_PHY_SERDES_FLAG)) {
1131
1132             /* Select the SerDes Digital block of the AN MMD. */
1133             PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_SERDES_DIG);
1134                         val = PHY_READ(sc, BRGPHY_SERDES_DIG_1000X_CTL1);
1135                         val &= ~BRGPHY_SD_DIG_1000X_CTL1_AUTODET;
1136                         val |= BRGPHY_SD_DIG_1000X_CTL1_FIBER;
1137                         PHY_WRITE(sc, BRGPHY_SERDES_DIG_1000X_CTL1, val);
1138
1139             /* Select the Over 1G block of the AN MMD. */
1140                         PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_OVER_1G);
1141
1142             /* Enable autoneg "Next Page" to advertise 2.5G support. */
1143             val = PHY_READ(sc, BRGPHY_OVER_1G_UNFORMAT_PG1);
1144                         if (bce_sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG)
1145                                 val |= BRGPHY_5708S_ANEG_NXT_PG_XMIT1_25G;
1146                         else
1147                                 val &= ~BRGPHY_5708S_ANEG_NXT_PG_XMIT1_25G;
1148                         PHY_WRITE(sc, BRGPHY_OVER_1G_UNFORMAT_PG1, val);
1149
1150             /* Select the Multi-Rate Backplane Ethernet block of the AN MMD. */
1151                         PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_MRBE);
1152
1153             /* Enable MRBE speed autoneg. */
1154             val = PHY_READ(sc, BRGPHY_MRBE_MSG_PG5_NP);
1155                         val |= BRGPHY_MRBE_MSG_PG5_NP_MBRE |
1156                             BRGPHY_MRBE_MSG_PG5_NP_T2;
1157                         PHY_WRITE(sc, BRGPHY_MRBE_MSG_PG5_NP, val);
1158
1159             /* Select the Clause 73 User B0 block of the AN MMD. */
1160             PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_CL73_USER_B0);
1161
1162             /* Enable MRBE speed autoneg. */
1163                         PHY_WRITE(sc, BRGPHY_CL73_USER_B0_MBRE_CTL1,
1164                             BRGPHY_CL73_USER_B0_MBRE_CTL1_NP_AFT_BP |
1165                             BRGPHY_CL73_USER_B0_MBRE_CTL1_STA_MGR |
1166                             BRGPHY_CL73_USER_B0_MBRE_CTL1_ANEG);
1167
1168             /* Restore IEEE0 block (assumed in all brgphy(4) code). */
1169             PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_COMBO_IEEE0);
1170
1171         } else if (BCE_CHIP_NUM(bce_sc) == BCE_CHIP_NUM_5709) {
1172                         if ((BCE_CHIP_REV(bce_sc) == BCE_CHIP_REV_Ax) ||
1173                                 (BCE_CHIP_REV(bce_sc) == BCE_CHIP_REV_Bx))
1174                                 brgphy_fixup_disable_early_dac(sc);
1175
1176                         brgphy_jumbo_settings(sc, ifp->if_mtu);
1177                         brgphy_ethernet_wirespeed(sc);
1178                 } else {
1179                         brgphy_fixup_ber_bug(sc);
1180                         brgphy_jumbo_settings(sc, ifp->if_mtu);
1181                         brgphy_ethernet_wirespeed(sc);
1182                 }
1183
1184         }
1185 }
1186