2 * Principal Author: Parag Patel
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice unmodified, this list of conditions, and the following
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * Additonal Copyright (c) 2001 by Traakan Software under same licence.
29 * Secondary Author: Matthew Jacob
32 #include <sys/cdefs.h>
33 __FBSDID("$FreeBSD$");
36 * driver for the Marvell 88E1000 series external 1000/100/10-BT PHY.
40 * Support added for the Marvell 88E1011 (Alaska) 1000/100/10baseTX and
42 * Nathan Binkert <nate@openbsd.org>
43 * Jung-uk Kim <jkim@niksun.com>
46 #include <sys/param.h>
47 #include <sys/systm.h>
48 #include <sys/kernel.h>
49 #include <sys/module.h>
50 #include <sys/socket.h>
55 #include <net/if_media.h>
57 #include <dev/mii/mii.h>
58 #include <dev/mii/miivar.h>
61 #include <dev/mii/e1000phyreg.h>
63 #include <machine/bus.h>
64 #include <dev/msk/if_mskreg.h>
66 #include "miibus_if.h"
68 static int e1000phy_probe(device_t);
69 static int e1000phy_attach(device_t);
71 struct e1000phy_softc {
72 struct mii_softc mii_sc;
74 struct msk_mii_data *mmd;
77 static device_method_t e1000phy_methods[] = {
78 /* device interface */
79 DEVMETHOD(device_probe, e1000phy_probe),
80 DEVMETHOD(device_attach, e1000phy_attach),
81 DEVMETHOD(device_detach, mii_phy_detach),
82 DEVMETHOD(device_shutdown, bus_generic_shutdown),
86 static devclass_t e1000phy_devclass;
87 static driver_t e1000phy_driver = {
90 sizeof(struct e1000phy_softc)
93 DRIVER_MODULE(e1000phy, miibus, e1000phy_driver, e1000phy_devclass, 0, 0);
95 static int e1000phy_service(struct mii_softc *, struct mii_data *, int);
96 static void e1000phy_status(struct mii_softc *);
97 static void e1000phy_reset(struct mii_softc *);
98 static int e1000phy_mii_phy_auto(struct e1000phy_softc *);
100 static const struct mii_phydesc e1000phys[] = {
101 MII_PHY_DESC(MARVELL, E1000),
102 MII_PHY_DESC(MARVELL, E1011),
103 MII_PHY_DESC(MARVELL, E1000_3),
104 MII_PHY_DESC(MARVELL, E1000S),
105 MII_PHY_DESC(MARVELL, E1000_5),
106 MII_PHY_DESC(MARVELL, E1000_6),
107 MII_PHY_DESC(MARVELL, E3082),
108 MII_PHY_DESC(MARVELL, E1112),
109 MII_PHY_DESC(MARVELL, E1149),
110 MII_PHY_DESC(MARVELL, E1111),
111 MII_PHY_DESC(MARVELL, E1116),
112 MII_PHY_DESC(MARVELL, E1116R),
113 MII_PHY_DESC(MARVELL, E1118),
114 MII_PHY_DESC(MARVELL, E3016),
115 MII_PHY_DESC(MARVELL, PHYG65G),
116 MII_PHY_DESC(xxMARVELL, E1000),
117 MII_PHY_DESC(xxMARVELL, E1011),
118 MII_PHY_DESC(xxMARVELL, E1000_3),
119 MII_PHY_DESC(xxMARVELL, E1000_5),
120 MII_PHY_DESC(xxMARVELL, E1111),
125 e1000phy_probe(device_t dev)
128 return (mii_phy_dev_probe(dev, e1000phys, BUS_PROBE_DEFAULT));
132 e1000phy_attach(device_t dev)
134 struct e1000phy_softc *esc;
135 struct mii_softc *sc;
136 struct mii_attach_args *ma;
137 struct mii_data *mii;
140 esc = device_get_softc(dev);
142 ma = device_get_ivars(dev);
143 sc->mii_dev = device_get_parent(dev);
144 mii = device_get_softc(sc->mii_dev);
145 LIST_INSERT_HEAD(&mii->mii_phys, sc, mii_list);
147 sc->mii_inst = mii->mii_instance;
148 sc->mii_phy = ma->mii_phyno;
149 sc->mii_service = e1000phy_service;
153 esc->mii_model = MII_MODEL(ma->mii_id2);
154 ifp = sc->mii_pdata->mii_ifp;
155 if (strcmp(ifp->if_dname, "msk") == 0) {
157 esc->mmd = device_get_ivars(
158 device_get_parent(device_get_parent(dev)));
159 if (esc->mmd != NULL &&
160 (esc->mmd->mii_flags & MIIF_HAVEFIBER) != 0)
161 sc->mii_flags |= MIIF_HAVEFIBER;
164 switch (esc->mii_model) {
165 case MII_MODEL_MARVELL_E1011:
166 case MII_MODEL_MARVELL_E1112:
167 if (PHY_READ(sc, E1000_ESSR) & E1000_ESSR_FIBER_LINK)
168 sc->mii_flags |= MIIF_HAVEFIBER;
170 case MII_MODEL_MARVELL_E1149:
172 * Some 88E1149 PHY's page select is initialized to
173 * point to other bank instead of copper/fiber bank
174 * which in turn resulted in wrong registers were
175 * accessed during PHY operation. It is believed that
176 * page 0 should be used for copper PHY so reinitialize
177 * E1000_EADR to select default copper PHY. If parent
178 * device know the type of PHY(either copper or fiber),
179 * that information should be used to select default
182 PHY_WRITE(sc, E1000_EADR, 0);
188 sc->mii_capabilities = PHY_READ(sc, MII_BMSR) & ma->mii_capmask;
189 if (sc->mii_capabilities & BMSR_EXTSTAT)
190 sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR);
191 device_printf(dev, " ");
192 mii_phy_add_media(sc);
195 MIIBUS_MEDIAINIT(sc->mii_dev);
200 e1000phy_reset(struct mii_softc *sc)
202 struct e1000phy_softc *esc;
205 esc = (struct e1000phy_softc *)sc;
206 reg = PHY_READ(sc, E1000_SCR);
207 if ((sc->mii_flags & MIIF_HAVEFIBER) != 0) {
208 reg &= ~E1000_SCR_AUTO_X_MODE;
209 PHY_WRITE(sc, E1000_SCR, reg);
210 if (esc->mii_model == MII_MODEL_MARVELL_E1112) {
211 /* Select 1000BASE-X only mode. */
212 page = PHY_READ(sc, E1000_EADR);
213 PHY_WRITE(sc, E1000_EADR, 2);
214 reg = PHY_READ(sc, E1000_SCR);
215 reg &= ~E1000_SCR_MODE_MASK;
216 reg |= E1000_SCR_MODE_1000BX;
217 PHY_WRITE(sc, E1000_SCR, reg);
218 if (esc->mmd != NULL && esc->mmd->pmd == 'P') {
219 /* Set SIGDET polarity low for SFP module. */
220 PHY_WRITE(sc, E1000_EADR, 1);
221 reg = PHY_READ(sc, E1000_SCR);
222 reg |= E1000_SCR_FIB_SIGDET_POLARITY;
223 PHY_WRITE(sc, E1000_SCR, reg);
225 PHY_WRITE(sc, E1000_EADR, page);
228 switch (esc->mii_model) {
229 case MII_MODEL_MARVELL_E1111:
230 case MII_MODEL_MARVELL_E1112:
231 case MII_MODEL_MARVELL_E1116:
232 case MII_MODEL_MARVELL_E1118:
233 case MII_MODEL_MARVELL_E1149:
234 case MII_MODEL_MARVELL_PHYG65G:
235 /* Disable energy detect mode. */
236 reg &= ~E1000_SCR_EN_DETECT_MASK;
237 reg |= E1000_SCR_AUTO_X_MODE;
238 if (esc->mii_model == MII_MODEL_MARVELL_E1116)
239 reg &= ~E1000_SCR_POWER_DOWN;
240 reg |= E1000_SCR_ASSERT_CRS_ON_TX;
242 case MII_MODEL_MARVELL_E3082:
243 reg |= (E1000_SCR_AUTO_X_MODE >> 1);
244 reg |= E1000_SCR_ASSERT_CRS_ON_TX;
246 case MII_MODEL_MARVELL_E3016:
247 reg |= E1000_SCR_AUTO_MDIX;
248 reg &= ~(E1000_SCR_EN_DETECT |
249 E1000_SCR_SCRAMBLER_DISABLE);
250 reg |= E1000_SCR_LPNP;
251 /* XXX Enable class A driver for Yukon FE+ A0. */
252 PHY_WRITE(sc, 0x1C, PHY_READ(sc, 0x1C) | 0x0001);
255 reg &= ~E1000_SCR_AUTO_X_MODE;
256 reg |= E1000_SCR_ASSERT_CRS_ON_TX;
259 if (esc->mii_model != MII_MODEL_MARVELL_E3016) {
260 /* Auto correction for reversed cable polarity. */
261 reg &= ~E1000_SCR_POLARITY_REVERSAL;
263 PHY_WRITE(sc, E1000_SCR, reg);
265 if (esc->mii_model == MII_MODEL_MARVELL_E1116 ||
266 esc->mii_model == MII_MODEL_MARVELL_E1149) {
267 PHY_WRITE(sc, E1000_EADR, 2);
268 reg = PHY_READ(sc, E1000_SCR);
269 reg |= E1000_SCR_RGMII_POWER_UP;
270 PHY_WRITE(sc, E1000_SCR, reg);
271 PHY_WRITE(sc, E1000_EADR, 0);
275 switch (esc->mii_model) {
276 case MII_MODEL_MARVELL_E3082:
277 case MII_MODEL_MARVELL_E1112:
278 case MII_MODEL_MARVELL_E1118:
280 case MII_MODEL_MARVELL_E1116:
281 page = PHY_READ(sc, E1000_EADR);
282 /* Select page 3, LED control register. */
283 PHY_WRITE(sc, E1000_EADR, 3);
284 PHY_WRITE(sc, E1000_SCR,
285 E1000_SCR_LED_LOS(1) | /* Link/Act */
286 E1000_SCR_LED_INIT(8) | /* 10Mbps */
287 E1000_SCR_LED_STAT1(7) | /* 100Mbps */
288 E1000_SCR_LED_STAT0(7)); /* 1000Mbps */
289 /* Set blink rate. */
290 PHY_WRITE(sc, E1000_IER, E1000_PULSE_DUR(E1000_PULSE_170MS) |
291 E1000_BLINK_RATE(E1000_BLINK_84MS));
292 PHY_WRITE(sc, E1000_EADR, page);
294 case MII_MODEL_MARVELL_E3016:
295 /* LED2 -> ACT, LED1 -> LINK, LED0 -> SPEED. */
296 PHY_WRITE(sc, 0x16, 0x0B << 8 | 0x05 << 4 | 0x04);
297 /* Integrated register calibration workaround. */
298 PHY_WRITE(sc, 0x1D, 17);
299 PHY_WRITE(sc, 0x1E, 0x3F60);
302 /* Force TX_CLK to 25MHz clock. */
303 reg = PHY_READ(sc, E1000_ESCR);
304 reg |= E1000_ESCR_TX_CLK_25;
305 PHY_WRITE(sc, E1000_ESCR, reg);
309 /* Reset the PHY so all changes take effect. */
310 reg = PHY_READ(sc, E1000_CR);
311 reg |= E1000_CR_RESET;
312 PHY_WRITE(sc, E1000_CR, reg);
316 e1000phy_service(struct mii_softc *sc, struct mii_data *mii, int cmd)
318 struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
319 struct e1000phy_softc *esc = (struct e1000phy_softc *)sc;
326 * If we're not polling our PHY instance, just return.
328 if (IFM_INST(ife->ifm_media) != sc->mii_inst)
334 * If the media indicates a different PHY instance,
337 if (IFM_INST(ife->ifm_media) != sc->mii_inst) {
338 reg = PHY_READ(sc, E1000_CR);
339 PHY_WRITE(sc, E1000_CR, reg | E1000_CR_ISOLATE);
344 * If the interface is not up, don't do anything.
346 if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
349 if (IFM_SUBTYPE(ife->ifm_media) == IFM_AUTO) {
350 e1000phy_mii_phy_auto(esc);
355 switch (IFM_SUBTYPE(ife->ifm_media)) {
357 if ((sc->mii_extcapabilities &
358 (EXTSR_1000TFDX | EXTSR_1000THDX)) == 0)
360 speed = E1000_CR_SPEED_1000;
363 if ((sc->mii_extcapabilities &
364 (EXTSR_1000XFDX | EXTSR_1000XHDX)) == 0)
366 speed = E1000_CR_SPEED_1000;
369 speed = E1000_CR_SPEED_100;
372 speed = E1000_CR_SPEED_10;
375 reg = PHY_READ(sc, E1000_CR);
376 PHY_WRITE(sc, E1000_CR,
377 reg | E1000_CR_ISOLATE | E1000_CR_POWER_DOWN);
383 if (((ife->ifm_media & IFM_GMASK) & IFM_FDX) != 0) {
384 speed |= E1000_CR_FULL_DUPLEX;
385 gig = E1000_1GCR_1000T_FD;
387 gig = E1000_1GCR_1000T;
389 reg = PHY_READ(sc, E1000_CR);
390 reg &= ~E1000_CR_AUTO_NEG_ENABLE;
391 PHY_WRITE(sc, E1000_CR, reg | E1000_CR_RESET);
394 * When setting the link manually, one side must
395 * be the master and the other the slave. However
396 * ifmedia doesn't give us a good way to specify
397 * this, so we fake it by using one of the LINK
398 * flags. If LINK0 is set, we program the PHY to
399 * be a master, otherwise it's a slave.
401 if (IFM_SUBTYPE(ife->ifm_media) == IFM_1000_T ||
402 (IFM_SUBTYPE(ife->ifm_media) == IFM_1000_SX)) {
403 if ((mii->mii_ifp->if_flags & IFF_LINK0))
404 PHY_WRITE(sc, E1000_1GCR, gig |
405 E1000_1GCR_MS_ENABLE | E1000_1GCR_MS_VALUE);
407 PHY_WRITE(sc, E1000_1GCR, gig |
408 E1000_1GCR_MS_ENABLE);
410 if ((sc->mii_extcapabilities &
411 (EXTSR_1000TFDX | EXTSR_1000THDX)) != 0)
412 PHY_WRITE(sc, E1000_1GCR, 0);
414 PHY_WRITE(sc, E1000_AR, E1000_AR_SELECTOR_FIELD);
415 PHY_WRITE(sc, E1000_CR, speed | E1000_CR_RESET);
420 * If we're not currently selected, just return.
422 if (IFM_INST(ife->ifm_media) != sc->mii_inst)
426 * Is the interface even up?
428 if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
432 * Only used for autonegotiation.
434 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) {
441 * Read the status register twice; BMSR_LINK is latch-low.
443 reg = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR);
444 if (reg & BMSR_LINK) {
449 /* Announce link loss right after it happens. */
450 if (sc->mii_ticks++ == 0)
452 if (sc->mii_ticks <= sc->mii_anegticks)
457 e1000phy_mii_phy_auto(esc);
461 /* Update the media status. */
464 /* Callback if something changed. */
465 mii_phy_update(sc, cmd);
470 e1000phy_status(struct mii_softc *sc)
472 struct mii_data *mii = sc->mii_pdata;
473 int bmcr, bmsr, gsr, ssr, ar, lpar;
475 mii->mii_media_status = IFM_AVALID;
476 mii->mii_media_active = IFM_ETHER;
478 bmsr = PHY_READ(sc, E1000_SR) | PHY_READ(sc, E1000_SR);
479 bmcr = PHY_READ(sc, E1000_CR);
480 ssr = PHY_READ(sc, E1000_SSR);
482 if (bmsr & E1000_SR_LINK_STATUS)
483 mii->mii_media_status |= IFM_ACTIVE;
485 if (bmcr & E1000_CR_LOOPBACK)
486 mii->mii_media_active |= IFM_LOOP;
488 if ((bmcr & E1000_CR_AUTO_NEG_ENABLE) != 0 &&
489 (ssr & E1000_SSR_SPD_DPLX_RESOLVED) == 0) {
490 /* Erg, still trying, I guess... */
491 mii->mii_media_active |= IFM_NONE;
495 if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) {
496 switch (ssr & E1000_SSR_SPEED) {
497 case E1000_SSR_1000MBS:
498 mii->mii_media_active |= IFM_1000_T;
500 case E1000_SSR_100MBS:
501 mii->mii_media_active |= IFM_100_TX;
503 case E1000_SSR_10MBS:
504 mii->mii_media_active |= IFM_10_T;
507 mii->mii_media_active |= IFM_NONE;
512 * Some fiber PHY(88E1112) does not seem to set resolved
513 * speed so always assume we've got IFM_1000_SX.
515 mii->mii_media_active |= IFM_1000_SX;
518 if (ssr & E1000_SSR_DUPLEX)
519 mii->mii_media_active |= IFM_FDX;
521 mii->mii_media_active |= IFM_HDX;
523 if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) {
524 ar = PHY_READ(sc, E1000_AR);
525 lpar = PHY_READ(sc, E1000_LPAR);
526 /* FLAG0==rx-flow-control FLAG1==tx-flow-control */
527 if ((ar & E1000_AR_PAUSE) && (lpar & E1000_LPAR_PAUSE)) {
528 mii->mii_media_active |= IFM_FLAG0 | IFM_FLAG1;
529 } else if (!(ar & E1000_AR_PAUSE) && (ar & E1000_AR_ASM_DIR) &&
530 (lpar & E1000_LPAR_PAUSE) && (lpar & E1000_LPAR_ASM_DIR)) {
531 mii->mii_media_active |= IFM_FLAG1;
532 } else if ((ar & E1000_AR_PAUSE) && (ar & E1000_AR_ASM_DIR) &&
533 !(lpar & E1000_LPAR_PAUSE) && (lpar & E1000_LPAR_ASM_DIR)) {
534 mii->mii_media_active |= IFM_FLAG0;
538 /* FLAG2 : local PHY resolved to MASTER */
539 if ((IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) ||
540 (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX)) {
541 PHY_READ(sc, E1000_1GSR);
542 gsr = PHY_READ(sc, E1000_1GSR);
543 if ((gsr & E1000_1GSR_MS_CONFIG_RES) != 0)
544 mii->mii_media_active |= IFM_FLAG2;
549 e1000phy_mii_phy_auto(struct e1000phy_softc *esc)
551 struct mii_softc *sc;
555 if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) {
556 reg = PHY_READ(sc, E1000_AR);
557 reg |= E1000_AR_10T | E1000_AR_10T_FD |
558 E1000_AR_100TX | E1000_AR_100TX_FD |
559 E1000_AR_PAUSE | E1000_AR_ASM_DIR;
560 PHY_WRITE(sc, E1000_AR, reg | E1000_AR_SELECTOR_FIELD);
562 PHY_WRITE(sc, E1000_AR, E1000_FA_1000X_FD | E1000_FA_1000X |
563 E1000_FA_SYM_PAUSE | E1000_FA_ASYM_PAUSE);
564 if ((sc->mii_extcapabilities & (EXTSR_1000TFDX | EXTSR_1000THDX)) != 0)
565 PHY_WRITE(sc, E1000_1GCR,
566 E1000_1GCR_1000T_FD | E1000_1GCR_1000T);
567 PHY_WRITE(sc, E1000_CR,
568 E1000_CR_AUTO_NEG_ENABLE | E1000_CR_RESTART_AUTO_NEG);
570 return (EJUSTRETURN);