1 /******************************************************************************
3 Copyright (c) 2006-2009, Myricom Inc.
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Neither the name of the Myricom Inc, nor the names of its
13 contributors may be used to endorse or promote products derived from
14 this software without specific prior written permission.
16 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
17 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
20 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
21 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
23 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
24 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
25 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
26 POSSIBILITY OF SUCH DAMAGE.
28 ***************************************************************************/
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD$");
33 #include <sys/param.h>
34 #include <sys/systm.h>
35 #include <sys/linker.h>
36 #include <sys/firmware.h>
37 #include <sys/endian.h>
38 #include <sys/sockio.h>
40 #include <sys/malloc.h>
42 #include <sys/kernel.h>
44 #include <sys/module.h>
45 #include <sys/socket.h>
46 #include <sys/sysctl.h>
48 #include <sys/taskqueue.h>
50 /* count xmits ourselves, rather than via drbr */
53 #include <net/if_arp.h>
54 #include <net/ethernet.h>
55 #include <net/if_dl.h>
56 #include <net/if_media.h>
60 #include <net/if_types.h>
61 #include <net/if_vlan_var.h>
64 #include <netinet/in_systm.h>
65 #include <netinet/in.h>
66 #include <netinet/ip.h>
67 #include <netinet/tcp.h>
69 #include <machine/bus.h>
70 #include <machine/in_cksum.h>
71 #include <machine/resource.h>
76 #include <dev/pci/pcireg.h>
77 #include <dev/pci/pcivar.h>
78 #include <dev/pci/pci_private.h> /* XXX for pci_cfg_restore */
80 #include <vm/vm.h> /* for pmap_mapdev() */
83 #if defined(__i386) || defined(__amd64)
84 #include <machine/specialreg.h>
87 #include <dev/mxge/mxge_mcp.h>
88 #include <dev/mxge/mcp_gen_header.h>
89 /*#define MXGE_FAKE_IFP*/
90 #include <dev/mxge/if_mxge_var.h>
92 #include <sys/buf_ring.h>
98 static int mxge_nvidia_ecrc_enable = 1;
99 static int mxge_force_firmware = 0;
100 static int mxge_intr_coal_delay = 30;
101 static int mxge_deassert_wait = 1;
102 static int mxge_flow_control = 1;
103 static int mxge_verbose = 0;
104 static int mxge_lro_cnt = 8;
105 static int mxge_ticks;
106 static int mxge_max_slices = 1;
107 static int mxge_rss_hash_type = MXGEFW_RSS_HASH_TYPE_SRC_DST_PORT;
108 static int mxge_always_promisc = 0;
109 static int mxge_initial_mtu = ETHERMTU_JUMBO;
110 static int mxge_throttle = 0;
111 static char *mxge_fw_unaligned = "mxge_ethp_z8e";
112 static char *mxge_fw_aligned = "mxge_eth_z8e";
113 static char *mxge_fw_rss_aligned = "mxge_rss_eth_z8e";
114 static char *mxge_fw_rss_unaligned = "mxge_rss_ethp_z8e";
116 static int mxge_probe(device_t dev);
117 static int mxge_attach(device_t dev);
118 static int mxge_detach(device_t dev);
119 static int mxge_shutdown(device_t dev);
120 static void mxge_intr(void *arg);
122 static device_method_t mxge_methods[] =
124 /* Device interface */
125 DEVMETHOD(device_probe, mxge_probe),
126 DEVMETHOD(device_attach, mxge_attach),
127 DEVMETHOD(device_detach, mxge_detach),
128 DEVMETHOD(device_shutdown, mxge_shutdown),
132 static driver_t mxge_driver =
136 sizeof(mxge_softc_t),
139 static devclass_t mxge_devclass;
141 /* Declare ourselves to be a child of the PCI bus.*/
142 DRIVER_MODULE(mxge, pci, mxge_driver, mxge_devclass, 0, 0);
143 MODULE_DEPEND(mxge, firmware, 1, 1, 1);
144 MODULE_DEPEND(mxge, zlib, 1, 1, 1);
146 static int mxge_load_firmware(mxge_softc_t *sc, int adopt);
147 static int mxge_send_cmd(mxge_softc_t *sc, uint32_t cmd, mxge_cmd_t *data);
148 static int mxge_close(mxge_softc_t *sc, int down);
149 static int mxge_open(mxge_softc_t *sc);
150 static void mxge_tick(void *arg);
153 mxge_probe(device_t dev)
158 if ((pci_get_vendor(dev) == MXGE_PCI_VENDOR_MYRICOM) &&
159 ((pci_get_device(dev) == MXGE_PCI_DEVICE_Z8E) ||
160 (pci_get_device(dev) == MXGE_PCI_DEVICE_Z8E_9))) {
161 rev = pci_get_revid(dev);
163 case MXGE_PCI_REV_Z8E:
164 device_set_desc(dev, "Myri10G-PCIE-8A");
166 case MXGE_PCI_REV_Z8ES:
167 device_set_desc(dev, "Myri10G-PCIE-8B");
170 device_set_desc(dev, "Myri10G-PCIE-8??");
171 device_printf(dev, "Unrecognized rev %d NIC\n",
181 mxge_enable_wc(mxge_softc_t *sc)
183 #if defined(__i386) || defined(__amd64)
188 len = rman_get_size(sc->mem_res);
189 err = pmap_change_attr((vm_offset_t) sc->sram,
190 len, PAT_WRITE_COMBINING);
192 device_printf(sc->dev, "pmap_change_attr failed, %d\n",
200 /* callback to get our DMA address */
202 mxge_dmamap_callback(void *arg, bus_dma_segment_t *segs, int nsegs,
206 *(bus_addr_t *) arg = segs->ds_addr;
211 mxge_dma_alloc(mxge_softc_t *sc, mxge_dma_t *dma, size_t bytes,
212 bus_size_t alignment)
215 device_t dev = sc->dev;
216 bus_size_t boundary, maxsegsize;
218 if (bytes > 4096 && alignment == 4096) {
226 /* allocate DMAable memory tags */
227 err = bus_dma_tag_create(sc->parent_dmat, /* parent */
228 alignment, /* alignment */
229 boundary, /* boundary */
230 BUS_SPACE_MAXADDR, /* low */
231 BUS_SPACE_MAXADDR, /* high */
232 NULL, NULL, /* filter */
235 maxsegsize, /* maxsegsize */
236 BUS_DMA_COHERENT, /* flags */
237 NULL, NULL, /* lock */
238 &dma->dmat); /* tag */
240 device_printf(dev, "couldn't alloc tag (err = %d)\n", err);
244 /* allocate DMAable memory & map */
245 err = bus_dmamem_alloc(dma->dmat, &dma->addr,
246 (BUS_DMA_WAITOK | BUS_DMA_COHERENT
247 | BUS_DMA_ZERO), &dma->map);
249 device_printf(dev, "couldn't alloc mem (err = %d)\n", err);
250 goto abort_with_dmat;
253 /* load the memory */
254 err = bus_dmamap_load(dma->dmat, dma->map, dma->addr, bytes,
255 mxge_dmamap_callback,
256 (void *)&dma->bus_addr, 0);
258 device_printf(dev, "couldn't load map (err = %d)\n", err);
264 bus_dmamem_free(dma->dmat, dma->addr, dma->map);
266 (void)bus_dma_tag_destroy(dma->dmat);
272 mxge_dma_free(mxge_dma_t *dma)
274 bus_dmamap_unload(dma->dmat, dma->map);
275 bus_dmamem_free(dma->dmat, dma->addr, dma->map);
276 (void)bus_dma_tag_destroy(dma->dmat);
280 * The eeprom strings on the lanaiX have the format
287 mxge_parse_strings(mxge_softc_t *sc)
289 #define MXGE_NEXT_STRING(p) while(ptr < limit && *ptr++)
294 ptr = sc->eeprom_strings;
295 limit = sc->eeprom_strings + MXGE_EEPROM_STRINGS_SIZE;
297 while (ptr < limit && *ptr != '\0') {
298 if (memcmp(ptr, "MAC=", 4) == 0) {
300 sc->mac_addr_string = ptr;
301 for (i = 0; i < 6; i++) {
303 if ((ptr + 2) > limit)
305 sc->mac_addr[i] = strtoul(ptr, NULL, 16);
308 } else if (memcmp(ptr, "PC=", 3) == 0) {
310 strncpy(sc->product_code_string, ptr,
311 sizeof (sc->product_code_string) - 1);
312 } else if (memcmp(ptr, "SN=", 3) == 0) {
314 strncpy(sc->serial_number_string, ptr,
315 sizeof (sc->serial_number_string) - 1);
317 MXGE_NEXT_STRING(ptr);
324 device_printf(sc->dev, "failed to parse eeprom_strings\n");
329 #if defined __i386 || defined i386 || defined __i386__ || defined __x86_64__
331 mxge_enable_nvidia_ecrc(mxge_softc_t *sc)
334 unsigned long base, off;
336 device_t pdev, mcp55;
337 uint16_t vendor_id, device_id, word;
338 uintptr_t bus, slot, func, ivend, idev;
342 if (!mxge_nvidia_ecrc_enable)
345 pdev = device_get_parent(device_get_parent(sc->dev));
347 device_printf(sc->dev, "could not find parent?\n");
350 vendor_id = pci_read_config(pdev, PCIR_VENDOR, 2);
351 device_id = pci_read_config(pdev, PCIR_DEVICE, 2);
353 if (vendor_id != 0x10de)
358 if (device_id == 0x005d) {
359 /* ck804, base address is magic */
361 } else if (device_id >= 0x0374 && device_id <= 0x378) {
362 /* mcp55, base address stored in chipset */
363 mcp55 = pci_find_bsf(0, 0, 0);
365 0x10de == pci_read_config(mcp55, PCIR_VENDOR, 2) &&
366 0x0369 == pci_read_config(mcp55, PCIR_DEVICE, 2)) {
367 word = pci_read_config(mcp55, 0x90, 2);
368 base = ((unsigned long)word & 0x7ffeU) << 25;
375 Test below is commented because it is believed that doing
376 config read/write beyond 0xff will access the config space
377 for the next larger function. Uncomment this and remove
378 the hacky pmap_mapdev() way of accessing config space when
379 FreeBSD grows support for extended pcie config space access
382 /* See if we can, by some miracle, access the extended
384 val = pci_read_config(pdev, 0x178, 4);
385 if (val != 0xffffffff) {
387 pci_write_config(pdev, 0x178, val, 4);
391 /* Rather than using normal pci config space writes, we must
392 * map the Nvidia config space ourselves. This is because on
393 * opteron/nvidia class machine the 0xe000000 mapping is
394 * handled by the nvidia chipset, that means the internal PCI
395 * device (the on-chip northbridge), or the amd-8131 bridge
396 * and things behind them are not visible by this method.
399 BUS_READ_IVAR(device_get_parent(pdev), pdev,
401 BUS_READ_IVAR(device_get_parent(pdev), pdev,
402 PCI_IVAR_SLOT, &slot);
403 BUS_READ_IVAR(device_get_parent(pdev), pdev,
404 PCI_IVAR_FUNCTION, &func);
405 BUS_READ_IVAR(device_get_parent(pdev), pdev,
406 PCI_IVAR_VENDOR, &ivend);
407 BUS_READ_IVAR(device_get_parent(pdev), pdev,
408 PCI_IVAR_DEVICE, &idev);
411 + 0x00100000UL * (unsigned long)bus
412 + 0x00001000UL * (unsigned long)(func
415 /* map it into the kernel */
416 va = pmap_mapdev(trunc_page((vm_paddr_t)off), PAGE_SIZE);
420 device_printf(sc->dev, "pmap_kenter_temporary didn't\n");
423 /* get a pointer to the config space mapped into the kernel */
424 cfgptr = va + (off & PAGE_MASK);
426 /* make sure that we can really access it */
427 vendor_id = *(uint16_t *)(cfgptr + PCIR_VENDOR);
428 device_id = *(uint16_t *)(cfgptr + PCIR_DEVICE);
429 if (! (vendor_id == ivend && device_id == idev)) {
430 device_printf(sc->dev, "mapping failed: 0x%x:0x%x\n",
431 vendor_id, device_id);
432 pmap_unmapdev((vm_offset_t)va, PAGE_SIZE);
436 ptr32 = (uint32_t*)(cfgptr + 0x178);
439 if (val == 0xffffffff) {
440 device_printf(sc->dev, "extended mapping failed\n");
441 pmap_unmapdev((vm_offset_t)va, PAGE_SIZE);
445 pmap_unmapdev((vm_offset_t)va, PAGE_SIZE);
447 device_printf(sc->dev,
448 "Enabled ECRC on upstream Nvidia bridge "
450 (int)bus, (int)slot, (int)func);
455 mxge_enable_nvidia_ecrc(mxge_softc_t *sc)
457 device_printf(sc->dev,
458 "Nforce 4 chipset on non-x86/amd64!?!?!\n");
465 mxge_dma_test(mxge_softc_t *sc, int test_type)
468 bus_addr_t dmatest_bus = sc->dmabench_dma.bus_addr;
474 /* Run a small DMA test.
475 * The magic multipliers to the length tell the firmware
476 * to do DMA read, write, or read+write tests. The
477 * results are returned in cmd.data0. The upper 16
478 * bits of the return is the number of transfers completed.
479 * The lower 16 bits is the time in 0.5us ticks that the
480 * transfers took to complete.
483 len = sc->tx_boundary;
485 cmd.data0 = MXGE_LOWPART_TO_U32(dmatest_bus);
486 cmd.data1 = MXGE_HIGHPART_TO_U32(dmatest_bus);
487 cmd.data2 = len * 0x10000;
488 status = mxge_send_cmd(sc, test_type, &cmd);
493 sc->read_dma = ((cmd.data0>>16) * len * 2) /
494 (cmd.data0 & 0xffff);
495 cmd.data0 = MXGE_LOWPART_TO_U32(dmatest_bus);
496 cmd.data1 = MXGE_HIGHPART_TO_U32(dmatest_bus);
497 cmd.data2 = len * 0x1;
498 status = mxge_send_cmd(sc, test_type, &cmd);
503 sc->write_dma = ((cmd.data0>>16) * len * 2) /
504 (cmd.data0 & 0xffff);
506 cmd.data0 = MXGE_LOWPART_TO_U32(dmatest_bus);
507 cmd.data1 = MXGE_HIGHPART_TO_U32(dmatest_bus);
508 cmd.data2 = len * 0x10001;
509 status = mxge_send_cmd(sc, test_type, &cmd);
514 sc->read_write_dma = ((cmd.data0>>16) * len * 2 * 2) /
515 (cmd.data0 & 0xffff);
518 if (status != 0 && test_type != MXGEFW_CMD_UNALIGNED_TEST)
519 device_printf(sc->dev, "DMA %s benchmark failed: %d\n",
526 * The Lanai Z8E PCI-E interface achieves higher Read-DMA throughput
527 * when the PCI-E Completion packets are aligned on an 8-byte
528 * boundary. Some PCI-E chip sets always align Completion packets; on
529 * the ones that do not, the alignment can be enforced by enabling
530 * ECRC generation (if supported).
532 * When PCI-E Completion packets are not aligned, it is actually more
533 * efficient to limit Read-DMA transactions to 2KB, rather than 4KB.
535 * If the driver can neither enable ECRC nor verify that it has
536 * already been enabled, then it must use a firmware image which works
537 * around unaligned completion packets (ethp_z8e.dat), and it should
538 * also ensure that it never gives the device a Read-DMA which is
539 * larger than 2KB by setting the tx_boundary to 2KB. If ECRC is
540 * enabled, then the driver should use the aligned (eth_z8e.dat)
541 * firmware image, and set tx_boundary to 4KB.
545 mxge_firmware_probe(mxge_softc_t *sc)
547 device_t dev = sc->dev;
551 sc->tx_boundary = 4096;
553 * Verify the max read request size was set to 4KB
554 * before trying the test with 4KB.
556 if (pci_find_extcap(dev, PCIY_EXPRESS, ®) == 0) {
557 pectl = pci_read_config(dev, reg + 0x8, 2);
558 if ((pectl & (5 << 12)) != (5 << 12)) {
559 device_printf(dev, "Max Read Req. size != 4k (0x%x\n",
561 sc->tx_boundary = 2048;
566 * load the optimized firmware (which assumes aligned PCIe
567 * completions) in order to see if it works on this host.
569 sc->fw_name = mxge_fw_aligned;
570 status = mxge_load_firmware(sc, 1);
576 * Enable ECRC if possible
578 mxge_enable_nvidia_ecrc(sc);
581 * Run a DMA test which watches for unaligned completions and
582 * aborts on the first one seen.
585 status = mxge_dma_test(sc, MXGEFW_CMD_UNALIGNED_TEST);
587 return 0; /* keep the aligned firmware */
590 device_printf(dev, "DMA test failed: %d\n", status);
591 if (status == ENOSYS)
592 device_printf(dev, "Falling back to ethp! "
593 "Please install up to date fw\n");
598 mxge_select_firmware(mxge_softc_t *sc)
601 int force_firmware = mxge_force_firmware;
604 force_firmware = sc->throttle;
606 if (force_firmware != 0) {
607 if (force_firmware == 1)
612 device_printf(sc->dev,
613 "Assuming %s completions (forced)\n",
614 aligned ? "aligned" : "unaligned");
618 /* if the PCIe link width is 4 or less, we can use the aligned
619 firmware and skip any checks */
620 if (sc->link_width != 0 && sc->link_width <= 4) {
621 device_printf(sc->dev,
622 "PCIe x%d Link, expect reduced performance\n",
628 if (0 == mxge_firmware_probe(sc))
633 sc->fw_name = mxge_fw_aligned;
634 sc->tx_boundary = 4096;
636 sc->fw_name = mxge_fw_unaligned;
637 sc->tx_boundary = 2048;
639 return (mxge_load_firmware(sc, 0));
649 mxge_validate_firmware(mxge_softc_t *sc, const mcp_gen_header_t *hdr)
653 if (be32toh(hdr->mcp_type) != MCP_TYPE_ETH) {
654 device_printf(sc->dev, "Bad firmware type: 0x%x\n",
655 be32toh(hdr->mcp_type));
659 /* save firmware version for sysctl */
660 strncpy(sc->fw_version, hdr->version, sizeof (sc->fw_version));
662 device_printf(sc->dev, "firmware id: %s\n", hdr->version);
664 sscanf(sc->fw_version, "%d.%d.%d", &sc->fw_ver_major,
665 &sc->fw_ver_minor, &sc->fw_ver_tiny);
667 if (!(sc->fw_ver_major == MXGEFW_VERSION_MAJOR
668 && sc->fw_ver_minor == MXGEFW_VERSION_MINOR)) {
669 device_printf(sc->dev, "Found firmware version %s\n",
671 device_printf(sc->dev, "Driver needs %d.%d\n",
672 MXGEFW_VERSION_MAJOR, MXGEFW_VERSION_MINOR);
680 z_alloc(void *nil, u_int items, u_int size)
684 ptr = malloc(items * size, M_TEMP, M_NOWAIT);
689 z_free(void *nil, void *ptr)
696 mxge_load_firmware_helper(mxge_softc_t *sc, uint32_t *limit)
699 char *inflate_buffer;
700 const struct firmware *fw;
701 const mcp_gen_header_t *hdr;
708 fw = firmware_get(sc->fw_name);
710 device_printf(sc->dev, "Could not find firmware image %s\n",
717 /* setup zlib and decompress f/w */
718 bzero(&zs, sizeof (zs));
721 status = inflateInit(&zs);
722 if (status != Z_OK) {
727 /* the uncompressed size is stored as the firmware version,
728 which would otherwise go unused */
729 fw_len = (size_t) fw->version;
730 inflate_buffer = malloc(fw_len, M_TEMP, M_NOWAIT);
731 if (inflate_buffer == NULL)
733 zs.avail_in = fw->datasize;
734 zs.next_in = __DECONST(char *, fw->data);
735 zs.avail_out = fw_len;
736 zs.next_out = inflate_buffer;
737 status = inflate(&zs, Z_FINISH);
738 if (status != Z_STREAM_END) {
739 device_printf(sc->dev, "zlib %d\n", status);
741 goto abort_with_buffer;
745 hdr_offset = htobe32(*(const uint32_t *)
746 (inflate_buffer + MCP_HEADER_PTR_OFFSET));
747 if ((hdr_offset & 3) || hdr_offset + sizeof(*hdr) > fw_len) {
748 device_printf(sc->dev, "Bad firmware file");
750 goto abort_with_buffer;
752 hdr = (const void*)(inflate_buffer + hdr_offset);
754 status = mxge_validate_firmware(sc, hdr);
756 goto abort_with_buffer;
758 /* Copy the inflated firmware to NIC SRAM. */
759 for (i = 0; i < fw_len; i += 256) {
760 mxge_pio_copy(sc->sram + MXGE_FW_OFFSET + i,
762 min(256U, (unsigned)(fw_len - i)));
771 free(inflate_buffer, M_TEMP);
775 firmware_put(fw, FIRMWARE_UNLOAD);
780 * Enable or disable periodic RDMAs from the host to make certain
781 * chipsets resend dropped PCIe messages
785 mxge_dummy_rdma(mxge_softc_t *sc, int enable)
788 volatile uint32_t *confirm;
789 volatile char *submit;
790 uint32_t *buf, dma_low, dma_high;
793 buf = (uint32_t *)((unsigned long)(buf_bytes + 7) & ~7UL);
795 /* clear confirmation addr */
796 confirm = (volatile uint32_t *)sc->cmd;
800 /* send an rdma command to the PCIe engine, and wait for the
801 response in the confirmation address. The firmware should
802 write a -1 there to indicate it is alive and well
805 dma_low = MXGE_LOWPART_TO_U32(sc->cmd_dma.bus_addr);
806 dma_high = MXGE_HIGHPART_TO_U32(sc->cmd_dma.bus_addr);
807 buf[0] = htobe32(dma_high); /* confirm addr MSW */
808 buf[1] = htobe32(dma_low); /* confirm addr LSW */
809 buf[2] = htobe32(0xffffffff); /* confirm data */
810 dma_low = MXGE_LOWPART_TO_U32(sc->zeropad_dma.bus_addr);
811 dma_high = MXGE_HIGHPART_TO_U32(sc->zeropad_dma.bus_addr);
812 buf[3] = htobe32(dma_high); /* dummy addr MSW */
813 buf[4] = htobe32(dma_low); /* dummy addr LSW */
814 buf[5] = htobe32(enable); /* enable? */
817 submit = (volatile char *)(sc->sram + MXGEFW_BOOT_DUMMY_RDMA);
819 mxge_pio_copy(submit, buf, 64);
824 while (*confirm != 0xffffffff && i < 20) {
828 if (*confirm != 0xffffffff) {
829 device_printf(sc->dev, "dummy rdma %s failed (%p = 0x%x)",
830 (enable ? "enable" : "disable"), confirm,
837 mxge_send_cmd(mxge_softc_t *sc, uint32_t cmd, mxge_cmd_t *data)
840 char buf_bytes[sizeof(*buf) + 8];
841 volatile mcp_cmd_response_t *response = sc->cmd;
842 volatile char *cmd_addr = sc->sram + MXGEFW_ETH_CMD;
843 uint32_t dma_low, dma_high;
844 int err, sleep_total = 0;
846 /* ensure buf is aligned to 8 bytes */
847 buf = (mcp_cmd_t *)((unsigned long)(buf_bytes + 7) & ~7UL);
849 buf->data0 = htobe32(data->data0);
850 buf->data1 = htobe32(data->data1);
851 buf->data2 = htobe32(data->data2);
852 buf->cmd = htobe32(cmd);
853 dma_low = MXGE_LOWPART_TO_U32(sc->cmd_dma.bus_addr);
854 dma_high = MXGE_HIGHPART_TO_U32(sc->cmd_dma.bus_addr);
856 buf->response_addr.low = htobe32(dma_low);
857 buf->response_addr.high = htobe32(dma_high);
858 mtx_lock(&sc->cmd_mtx);
859 response->result = 0xffffffff;
861 mxge_pio_copy((volatile void *)cmd_addr, buf, sizeof (*buf));
863 /* wait up to 20ms */
865 for (sleep_total = 0; sleep_total < 20; sleep_total++) {
866 bus_dmamap_sync(sc->cmd_dma.dmat,
867 sc->cmd_dma.map, BUS_DMASYNC_POSTREAD);
869 switch (be32toh(response->result)) {
871 data->data0 = be32toh(response->data);
877 case MXGEFW_CMD_UNKNOWN:
880 case MXGEFW_CMD_ERROR_UNALIGNED:
883 case MXGEFW_CMD_ERROR_BUSY:
886 case MXGEFW_CMD_ERROR_I2C_ABSENT:
890 device_printf(sc->dev,
892 "failed, result = %d\n",
893 cmd, be32toh(response->result));
901 device_printf(sc->dev, "mxge: command %d timed out"
903 cmd, be32toh(response->result));
904 mtx_unlock(&sc->cmd_mtx);
909 mxge_adopt_running_firmware(mxge_softc_t *sc)
911 struct mcp_gen_header *hdr;
912 const size_t bytes = sizeof (struct mcp_gen_header);
916 /* find running firmware header */
917 hdr_offset = htobe32(*(volatile uint32_t *)
918 (sc->sram + MCP_HEADER_PTR_OFFSET));
920 if ((hdr_offset & 3) || hdr_offset + sizeof(*hdr) > sc->sram_size) {
921 device_printf(sc->dev,
922 "Running firmware has bad header offset (%d)\n",
927 /* copy header of running firmware from SRAM to host memory to
928 * validate firmware */
929 hdr = malloc(bytes, M_DEVBUF, M_NOWAIT);
931 device_printf(sc->dev, "could not malloc firmware hdr\n");
934 bus_space_read_region_1(rman_get_bustag(sc->mem_res),
935 rman_get_bushandle(sc->mem_res),
936 hdr_offset, (char *)hdr, bytes);
937 status = mxge_validate_firmware(sc, hdr);
941 * check to see if adopted firmware has bug where adopting
942 * it will cause broadcasts to be filtered unless the NIC
943 * is kept in ALLMULTI mode
945 if (sc->fw_ver_major == 1 && sc->fw_ver_minor == 4 &&
946 sc->fw_ver_tiny >= 4 && sc->fw_ver_tiny <= 11) {
947 sc->adopted_rx_filter_bug = 1;
948 device_printf(sc->dev, "Adopting fw %d.%d.%d: "
949 "working around rx filter bug\n",
950 sc->fw_ver_major, sc->fw_ver_minor,
959 mxge_load_firmware(mxge_softc_t *sc, int adopt)
961 volatile uint32_t *confirm;
962 volatile char *submit;
964 uint32_t *buf, size, dma_low, dma_high;
967 buf = (uint32_t *)((unsigned long)(buf_bytes + 7) & ~7UL);
969 size = sc->sram_size;
970 status = mxge_load_firmware_helper(sc, &size);
974 /* Try to use the currently running firmware, if
976 status = mxge_adopt_running_firmware(sc);
978 device_printf(sc->dev,
979 "failed to adopt running firmware\n");
982 device_printf(sc->dev,
983 "Successfully adopted running firmware\n");
984 if (sc->tx_boundary == 4096) {
985 device_printf(sc->dev,
986 "Using firmware currently running on NIC"
988 device_printf(sc->dev,
989 "performance consider loading optimized "
992 sc->fw_name = mxge_fw_unaligned;
993 sc->tx_boundary = 2048;
996 /* clear confirmation addr */
997 confirm = (volatile uint32_t *)sc->cmd;
1000 /* send a reload command to the bootstrap MCP, and wait for the
1001 response in the confirmation address. The firmware should
1002 write a -1 there to indicate it is alive and well
1005 dma_low = MXGE_LOWPART_TO_U32(sc->cmd_dma.bus_addr);
1006 dma_high = MXGE_HIGHPART_TO_U32(sc->cmd_dma.bus_addr);
1008 buf[0] = htobe32(dma_high); /* confirm addr MSW */
1009 buf[1] = htobe32(dma_low); /* confirm addr LSW */
1010 buf[2] = htobe32(0xffffffff); /* confirm data */
1012 /* FIX: All newest firmware should un-protect the bottom of
1013 the sram before handoff. However, the very first interfaces
1014 do not. Therefore the handoff copy must skip the first 8 bytes
1016 /* where the code starts*/
1017 buf[3] = htobe32(MXGE_FW_OFFSET + 8);
1018 buf[4] = htobe32(size - 8); /* length of code */
1019 buf[5] = htobe32(8); /* where to copy to */
1020 buf[6] = htobe32(0); /* where to jump to */
1022 submit = (volatile char *)(sc->sram + MXGEFW_BOOT_HANDOFF);
1023 mxge_pio_copy(submit, buf, 64);
1028 while (*confirm != 0xffffffff && i < 20) {
1031 bus_dmamap_sync(sc->cmd_dma.dmat,
1032 sc->cmd_dma.map, BUS_DMASYNC_POSTREAD);
1034 if (*confirm != 0xffffffff) {
1035 device_printf(sc->dev,"handoff failed (%p = 0x%x)",
1044 mxge_update_mac_address(mxge_softc_t *sc)
1047 uint8_t *addr = sc->mac_addr;
1051 cmd.data0 = ((addr[0] << 24) | (addr[1] << 16)
1052 | (addr[2] << 8) | addr[3]);
1054 cmd.data1 = ((addr[4] << 8) | (addr[5]));
1056 status = mxge_send_cmd(sc, MXGEFW_SET_MAC_ADDRESS, &cmd);
1061 mxge_change_pause(mxge_softc_t *sc, int pause)
1067 status = mxge_send_cmd(sc, MXGEFW_ENABLE_FLOW_CONTROL,
1070 status = mxge_send_cmd(sc, MXGEFW_DISABLE_FLOW_CONTROL,
1074 device_printf(sc->dev, "Failed to set flow control mode\n");
1082 mxge_change_promisc(mxge_softc_t *sc, int promisc)
1087 if (mxge_always_promisc)
1091 status = mxge_send_cmd(sc, MXGEFW_ENABLE_PROMISC,
1094 status = mxge_send_cmd(sc, MXGEFW_DISABLE_PROMISC,
1098 device_printf(sc->dev, "Failed to set promisc mode\n");
1103 mxge_set_multicast_list(mxge_softc_t *sc)
1106 struct ifmultiaddr *ifma;
1107 struct ifnet *ifp = sc->ifp;
1110 /* This firmware is known to not support multicast */
1111 if (!sc->fw_multicast_support)
1114 /* Disable multicast filtering while we play with the lists*/
1115 err = mxge_send_cmd(sc, MXGEFW_ENABLE_ALLMULTI, &cmd);
1117 device_printf(sc->dev, "Failed MXGEFW_ENABLE_ALLMULTI,"
1118 " error status: %d\n", err);
1122 if (sc->adopted_rx_filter_bug)
1125 if (ifp->if_flags & IFF_ALLMULTI)
1126 /* request to disable multicast filtering, so quit here */
1129 /* Flush all the filters */
1131 err = mxge_send_cmd(sc, MXGEFW_LEAVE_ALL_MULTICAST_GROUPS, &cmd);
1133 device_printf(sc->dev,
1134 "Failed MXGEFW_LEAVE_ALL_MULTICAST_GROUPS"
1135 ", error status: %d\n", err);
1139 /* Walk the multicast list, and add each address */
1141 if_maddr_rlock(ifp);
1142 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1143 if (ifma->ifma_addr->sa_family != AF_LINK)
1145 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
1147 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr) + 4,
1149 cmd.data0 = htonl(cmd.data0);
1150 cmd.data1 = htonl(cmd.data1);
1151 err = mxge_send_cmd(sc, MXGEFW_JOIN_MULTICAST_GROUP, &cmd);
1153 device_printf(sc->dev, "Failed "
1154 "MXGEFW_JOIN_MULTICAST_GROUP, error status:"
1156 /* abort, leaving multicast filtering off */
1157 if_maddr_runlock(ifp);
1161 if_maddr_runlock(ifp);
1162 /* Enable multicast filtering */
1163 err = mxge_send_cmd(sc, MXGEFW_DISABLE_ALLMULTI, &cmd);
1165 device_printf(sc->dev, "Failed MXGEFW_DISABLE_ALLMULTI"
1166 ", error status: %d\n", err);
1171 mxge_max_mtu(mxge_softc_t *sc)
1176 if (MJUMPAGESIZE - MXGEFW_PAD > MXGEFW_MAX_MTU)
1177 return MXGEFW_MAX_MTU - MXGEFW_PAD;
1179 /* try to set nbufs to see if it we can
1180 use virtually contiguous jumbos */
1182 status = mxge_send_cmd(sc, MXGEFW_CMD_ALWAYS_USE_N_BIG_BUFFERS,
1185 return MXGEFW_MAX_MTU - MXGEFW_PAD;
1187 /* otherwise, we're limited to MJUMPAGESIZE */
1188 return MJUMPAGESIZE - MXGEFW_PAD;
1192 mxge_reset(mxge_softc_t *sc, int interrupts_setup)
1194 struct mxge_slice_state *ss;
1195 mxge_rx_done_t *rx_done;
1196 volatile uint32_t *irq_claim;
1200 /* try to send a reset command to the card to see if it
1202 memset(&cmd, 0, sizeof (cmd));
1203 status = mxge_send_cmd(sc, MXGEFW_CMD_RESET, &cmd);
1205 device_printf(sc->dev, "failed reset\n");
1209 mxge_dummy_rdma(sc, 1);
1212 /* set the intrq size */
1213 cmd.data0 = sc->rx_ring_size;
1214 status = mxge_send_cmd(sc, MXGEFW_CMD_SET_INTRQ_SIZE, &cmd);
1217 * Even though we already know how many slices are supported
1218 * via mxge_slice_probe(), MXGEFW_CMD_GET_MAX_RSS_QUEUES
1219 * has magic side effects, and must be called after a reset.
1220 * It must be called prior to calling any RSS related cmds,
1221 * including assigning an interrupt queue for anything but
1222 * slice 0. It must also be called *after*
1223 * MXGEFW_CMD_SET_INTRQ_SIZE, since the intrq size is used by
1224 * the firmware to compute offsets.
1227 if (sc->num_slices > 1) {
1228 /* ask the maximum number of slices it supports */
1229 status = mxge_send_cmd(sc, MXGEFW_CMD_GET_MAX_RSS_QUEUES,
1232 device_printf(sc->dev,
1233 "failed to get number of slices\n");
1237 * MXGEFW_CMD_ENABLE_RSS_QUEUES must be called prior
1238 * to setting up the interrupt queue DMA
1240 cmd.data0 = sc->num_slices;
1241 cmd.data1 = MXGEFW_SLICE_INTR_MODE_ONE_PER_SLICE;
1242 #ifdef IFNET_BUF_RING
1243 cmd.data1 |= MXGEFW_SLICE_ENABLE_MULTIPLE_TX_QUEUES;
1245 status = mxge_send_cmd(sc, MXGEFW_CMD_ENABLE_RSS_QUEUES,
1248 device_printf(sc->dev,
1249 "failed to set number of slices\n");
1255 if (interrupts_setup) {
1256 /* Now exchange information about interrupts */
1257 for (slice = 0; slice < sc->num_slices; slice++) {
1258 rx_done = &sc->ss[slice].rx_done;
1259 memset(rx_done->entry, 0, sc->rx_ring_size);
1260 cmd.data0 = MXGE_LOWPART_TO_U32(rx_done->dma.bus_addr);
1261 cmd.data1 = MXGE_HIGHPART_TO_U32(rx_done->dma.bus_addr);
1263 status |= mxge_send_cmd(sc,
1264 MXGEFW_CMD_SET_INTRQ_DMA,
1269 status |= mxge_send_cmd(sc,
1270 MXGEFW_CMD_GET_INTR_COAL_DELAY_OFFSET, &cmd);
1273 sc->intr_coal_delay_ptr = (volatile uint32_t *)(sc->sram + cmd.data0);
1275 status |= mxge_send_cmd(sc, MXGEFW_CMD_GET_IRQ_ACK_OFFSET, &cmd);
1276 irq_claim = (volatile uint32_t *)(sc->sram + cmd.data0);
1279 status |= mxge_send_cmd(sc, MXGEFW_CMD_GET_IRQ_DEASSERT_OFFSET,
1281 sc->irq_deassert = (volatile uint32_t *)(sc->sram + cmd.data0);
1283 device_printf(sc->dev, "failed set interrupt parameters\n");
1288 *sc->intr_coal_delay_ptr = htobe32(sc->intr_coal_delay);
1291 /* run a DMA benchmark */
1292 (void) mxge_dma_test(sc, MXGEFW_DMA_TEST);
1294 for (slice = 0; slice < sc->num_slices; slice++) {
1295 ss = &sc->ss[slice];
1297 ss->irq_claim = irq_claim + (2 * slice);
1298 /* reset mcp/driver shared state back to 0 */
1299 ss->rx_done.idx = 0;
1300 ss->rx_done.cnt = 0;
1303 ss->tx.pkt_done = 0;
1304 ss->tx.queue_active = 0;
1305 ss->tx.activate = 0;
1306 ss->tx.deactivate = 0;
1311 ss->rx_small.cnt = 0;
1312 ss->lro_bad_csum = 0;
1314 ss->lro_flushed = 0;
1315 if (ss->fw_stats != NULL) {
1316 bzero(ss->fw_stats, sizeof *ss->fw_stats);
1319 sc->rdma_tags_available = 15;
1320 status = mxge_update_mac_address(sc);
1321 mxge_change_promisc(sc, sc->ifp->if_flags & IFF_PROMISC);
1322 mxge_change_pause(sc, sc->pause);
1323 mxge_set_multicast_list(sc);
1325 cmd.data0 = sc->throttle;
1326 if (mxge_send_cmd(sc, MXGEFW_CMD_SET_THROTTLE_FACTOR,
1328 device_printf(sc->dev,
1329 "can't enable throttle\n");
1336 mxge_change_throttle(SYSCTL_HANDLER_ARGS)
1341 unsigned int throttle;
1344 throttle = sc->throttle;
1345 err = sysctl_handle_int(oidp, &throttle, arg2, req);
1350 if (throttle == sc->throttle)
1353 if (throttle < MXGE_MIN_THROTTLE || throttle > MXGE_MAX_THROTTLE)
1356 mtx_lock(&sc->driver_mtx);
1357 cmd.data0 = throttle;
1358 err = mxge_send_cmd(sc, MXGEFW_CMD_SET_THROTTLE_FACTOR, &cmd);
1360 sc->throttle = throttle;
1361 mtx_unlock(&sc->driver_mtx);
1366 mxge_change_intr_coal(SYSCTL_HANDLER_ARGS)
1369 unsigned int intr_coal_delay;
1373 intr_coal_delay = sc->intr_coal_delay;
1374 err = sysctl_handle_int(oidp, &intr_coal_delay, arg2, req);
1378 if (intr_coal_delay == sc->intr_coal_delay)
1381 if (intr_coal_delay == 0 || intr_coal_delay > 1000*1000)
1384 mtx_lock(&sc->driver_mtx);
1385 *sc->intr_coal_delay_ptr = htobe32(intr_coal_delay);
1386 sc->intr_coal_delay = intr_coal_delay;
1388 mtx_unlock(&sc->driver_mtx);
1393 mxge_change_flow_control(SYSCTL_HANDLER_ARGS)
1396 unsigned int enabled;
1400 enabled = sc->pause;
1401 err = sysctl_handle_int(oidp, &enabled, arg2, req);
1405 if (enabled == sc->pause)
1408 mtx_lock(&sc->driver_mtx);
1409 err = mxge_change_pause(sc, enabled);
1410 mtx_unlock(&sc->driver_mtx);
1415 mxge_change_lro_locked(mxge_softc_t *sc, int lro_cnt)
1422 ifp->if_capenable &= ~IFCAP_LRO;
1424 ifp->if_capenable |= IFCAP_LRO;
1425 sc->lro_cnt = lro_cnt;
1426 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
1428 err = mxge_open(sc);
1434 mxge_change_lro(SYSCTL_HANDLER_ARGS)
1437 unsigned int lro_cnt;
1441 lro_cnt = sc->lro_cnt;
1442 err = sysctl_handle_int(oidp, &lro_cnt, arg2, req);
1446 if (lro_cnt == sc->lro_cnt)
1452 mtx_lock(&sc->driver_mtx);
1453 err = mxge_change_lro_locked(sc, lro_cnt);
1454 mtx_unlock(&sc->driver_mtx);
1459 mxge_handle_be32(SYSCTL_HANDLER_ARGS)
1465 arg2 = be32toh(*(int *)arg1);
1467 err = sysctl_handle_int(oidp, arg1, arg2, req);
1473 mxge_rem_sysctls(mxge_softc_t *sc)
1475 struct mxge_slice_state *ss;
1478 if (sc->slice_sysctl_tree == NULL)
1481 for (slice = 0; slice < sc->num_slices; slice++) {
1482 ss = &sc->ss[slice];
1483 if (ss == NULL || ss->sysctl_tree == NULL)
1485 sysctl_ctx_free(&ss->sysctl_ctx);
1486 ss->sysctl_tree = NULL;
1488 sysctl_ctx_free(&sc->slice_sysctl_ctx);
1489 sc->slice_sysctl_tree = NULL;
1493 mxge_add_sysctls(mxge_softc_t *sc)
1495 struct sysctl_ctx_list *ctx;
1496 struct sysctl_oid_list *children;
1498 struct mxge_slice_state *ss;
1502 ctx = device_get_sysctl_ctx(sc->dev);
1503 children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev));
1504 fw = sc->ss[0].fw_stats;
1506 /* random information */
1507 SYSCTL_ADD_STRING(ctx, children, OID_AUTO,
1509 CTLFLAG_RD, &sc->fw_version,
1510 0, "firmware version");
1511 SYSCTL_ADD_STRING(ctx, children, OID_AUTO,
1513 CTLFLAG_RD, &sc->serial_number_string,
1514 0, "serial number");
1515 SYSCTL_ADD_STRING(ctx, children, OID_AUTO,
1517 CTLFLAG_RD, &sc->product_code_string,
1519 SYSCTL_ADD_INT(ctx, children, OID_AUTO,
1521 CTLFLAG_RD, &sc->link_width,
1523 SYSCTL_ADD_INT(ctx, children, OID_AUTO,
1525 CTLFLAG_RD, &sc->tx_boundary,
1527 SYSCTL_ADD_INT(ctx, children, OID_AUTO,
1529 CTLFLAG_RD, &sc->wc,
1530 0, "write combining PIO?");
1531 SYSCTL_ADD_INT(ctx, children, OID_AUTO,
1533 CTLFLAG_RD, &sc->read_dma,
1534 0, "DMA Read speed in MB/s");
1535 SYSCTL_ADD_INT(ctx, children, OID_AUTO,
1537 CTLFLAG_RD, &sc->write_dma,
1538 0, "DMA Write speed in MB/s");
1539 SYSCTL_ADD_INT(ctx, children, OID_AUTO,
1540 "read_write_dma_MBs",
1541 CTLFLAG_RD, &sc->read_write_dma,
1542 0, "DMA concurrent Read/Write speed in MB/s");
1543 SYSCTL_ADD_INT(ctx, children, OID_AUTO,
1545 CTLFLAG_RD, &sc->watchdog_resets,
1546 0, "Number of times NIC was reset");
1549 /* performance related tunables */
1550 SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
1552 CTLTYPE_INT|CTLFLAG_RW, sc,
1553 0, mxge_change_intr_coal,
1554 "I", "interrupt coalescing delay in usecs");
1556 SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
1558 CTLTYPE_INT|CTLFLAG_RW, sc,
1559 0, mxge_change_throttle,
1560 "I", "transmit throttling");
1562 SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
1563 "flow_control_enabled",
1564 CTLTYPE_INT|CTLFLAG_RW, sc,
1565 0, mxge_change_flow_control,
1566 "I", "interrupt coalescing delay in usecs");
1568 SYSCTL_ADD_INT(ctx, children, OID_AUTO,
1570 CTLFLAG_RW, &mxge_deassert_wait,
1571 0, "Wait for IRQ line to go low in ihandler");
1573 /* stats block from firmware is in network byte order.
1575 SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
1577 CTLTYPE_INT|CTLFLAG_RD, &fw->link_up,
1578 0, mxge_handle_be32,
1580 SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
1581 "rdma_tags_available",
1582 CTLTYPE_INT|CTLFLAG_RD, &fw->rdma_tags_available,
1583 0, mxge_handle_be32,
1584 "I", "rdma_tags_available");
1585 SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
1586 "dropped_bad_crc32",
1587 CTLTYPE_INT|CTLFLAG_RD,
1588 &fw->dropped_bad_crc32,
1589 0, mxge_handle_be32,
1590 "I", "dropped_bad_crc32");
1591 SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
1593 CTLTYPE_INT|CTLFLAG_RD,
1594 &fw->dropped_bad_phy,
1595 0, mxge_handle_be32,
1596 "I", "dropped_bad_phy");
1597 SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
1598 "dropped_link_error_or_filtered",
1599 CTLTYPE_INT|CTLFLAG_RD,
1600 &fw->dropped_link_error_or_filtered,
1601 0, mxge_handle_be32,
1602 "I", "dropped_link_error_or_filtered");
1603 SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
1604 "dropped_link_overflow",
1605 CTLTYPE_INT|CTLFLAG_RD, &fw->dropped_link_overflow,
1606 0, mxge_handle_be32,
1607 "I", "dropped_link_overflow");
1608 SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
1609 "dropped_multicast_filtered",
1610 CTLTYPE_INT|CTLFLAG_RD,
1611 &fw->dropped_multicast_filtered,
1612 0, mxge_handle_be32,
1613 "I", "dropped_multicast_filtered");
1614 SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
1615 "dropped_no_big_buffer",
1616 CTLTYPE_INT|CTLFLAG_RD, &fw->dropped_no_big_buffer,
1617 0, mxge_handle_be32,
1618 "I", "dropped_no_big_buffer");
1619 SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
1620 "dropped_no_small_buffer",
1621 CTLTYPE_INT|CTLFLAG_RD,
1622 &fw->dropped_no_small_buffer,
1623 0, mxge_handle_be32,
1624 "I", "dropped_no_small_buffer");
1625 SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
1627 CTLTYPE_INT|CTLFLAG_RD, &fw->dropped_overrun,
1628 0, mxge_handle_be32,
1629 "I", "dropped_overrun");
1630 SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
1632 CTLTYPE_INT|CTLFLAG_RD,
1634 0, mxge_handle_be32,
1635 "I", "dropped_pause");
1636 SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
1638 CTLTYPE_INT|CTLFLAG_RD, &fw->dropped_runt,
1639 0, mxge_handle_be32,
1640 "I", "dropped_runt");
1642 SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
1643 "dropped_unicast_filtered",
1644 CTLTYPE_INT|CTLFLAG_RD, &fw->dropped_unicast_filtered,
1645 0, mxge_handle_be32,
1646 "I", "dropped_unicast_filtered");
1648 /* verbose printing? */
1649 SYSCTL_ADD_INT(ctx, children, OID_AUTO,
1651 CTLFLAG_RW, &mxge_verbose,
1652 0, "verbose printing");
1655 SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
1657 CTLTYPE_INT|CTLFLAG_RW, sc,
1659 "I", "number of lro merge queues");
1662 /* add counters exported for debugging from all slices */
1663 sysctl_ctx_init(&sc->slice_sysctl_ctx);
1664 sc->slice_sysctl_tree =
1665 SYSCTL_ADD_NODE(&sc->slice_sysctl_ctx, children, OID_AUTO,
1666 "slice", CTLFLAG_RD, 0, "");
1668 for (slice = 0; slice < sc->num_slices; slice++) {
1669 ss = &sc->ss[slice];
1670 sysctl_ctx_init(&ss->sysctl_ctx);
1671 ctx = &ss->sysctl_ctx;
1672 children = SYSCTL_CHILDREN(sc->slice_sysctl_tree);
1673 sprintf(slice_num, "%d", slice);
1675 SYSCTL_ADD_NODE(ctx, children, OID_AUTO, slice_num,
1677 children = SYSCTL_CHILDREN(ss->sysctl_tree);
1678 SYSCTL_ADD_INT(ctx, children, OID_AUTO,
1680 CTLFLAG_RD, &ss->rx_small.cnt,
1682 SYSCTL_ADD_INT(ctx, children, OID_AUTO,
1684 CTLFLAG_RD, &ss->rx_big.cnt,
1686 SYSCTL_ADD_INT(ctx, children, OID_AUTO,
1687 "lro_flushed", CTLFLAG_RD, &ss->lro_flushed,
1688 0, "number of lro merge queues flushed");
1690 SYSCTL_ADD_INT(ctx, children, OID_AUTO,
1691 "lro_queued", CTLFLAG_RD, &ss->lro_queued,
1692 0, "number of frames appended to lro merge"
1695 #ifndef IFNET_BUF_RING
1696 /* only transmit from slice 0 for now */
1700 SYSCTL_ADD_INT(ctx, children, OID_AUTO,
1702 CTLFLAG_RD, &ss->tx.req,
1705 SYSCTL_ADD_INT(ctx, children, OID_AUTO,
1707 CTLFLAG_RD, &ss->tx.done,
1709 SYSCTL_ADD_INT(ctx, children, OID_AUTO,
1711 CTLFLAG_RD, &ss->tx.pkt_done,
1713 SYSCTL_ADD_INT(ctx, children, OID_AUTO,
1715 CTLFLAG_RD, &ss->tx.stall,
1717 SYSCTL_ADD_INT(ctx, children, OID_AUTO,
1719 CTLFLAG_RD, &ss->tx.wake,
1721 SYSCTL_ADD_INT(ctx, children, OID_AUTO,
1723 CTLFLAG_RD, &ss->tx.defrag,
1725 SYSCTL_ADD_INT(ctx, children, OID_AUTO,
1727 CTLFLAG_RD, &ss->tx.queue_active,
1728 0, "tx_queue_active");
1729 SYSCTL_ADD_INT(ctx, children, OID_AUTO,
1731 CTLFLAG_RD, &ss->tx.activate,
1733 SYSCTL_ADD_INT(ctx, children, OID_AUTO,
1735 CTLFLAG_RD, &ss->tx.deactivate,
1736 0, "tx_deactivate");
1740 /* copy an array of mcp_kreq_ether_send_t's to the mcp. Copy
1741 backwards one at a time and handle ring wraps */
1744 mxge_submit_req_backwards(mxge_tx_ring_t *tx,
1745 mcp_kreq_ether_send_t *src, int cnt)
1747 int idx, starting_slot;
1748 starting_slot = tx->req;
1751 idx = (starting_slot + cnt) & tx->mask;
1752 mxge_pio_copy(&tx->lanai[idx],
1753 &src[cnt], sizeof(*src));
1759 * copy an array of mcp_kreq_ether_send_t's to the mcp. Copy
1760 * at most 32 bytes at a time, so as to avoid involving the software
1761 * pio handler in the nic. We re-write the first segment's flags
1762 * to mark them valid only after writing the entire chain
1766 mxge_submit_req(mxge_tx_ring_t *tx, mcp_kreq_ether_send_t *src,
1771 volatile uint32_t *dst_ints;
1772 mcp_kreq_ether_send_t *srcp;
1773 volatile mcp_kreq_ether_send_t *dstp, *dst;
1776 idx = tx->req & tx->mask;
1778 last_flags = src->flags;
1781 dst = dstp = &tx->lanai[idx];
1784 if ((idx + cnt) < tx->mask) {
1785 for (i = 0; i < (cnt - 1); i += 2) {
1786 mxge_pio_copy(dstp, srcp, 2 * sizeof(*src));
1787 wmb(); /* force write every 32 bytes */
1792 /* submit all but the first request, and ensure
1793 that it is submitted below */
1794 mxge_submit_req_backwards(tx, src, cnt);
1798 /* submit the first request */
1799 mxge_pio_copy(dstp, srcp, sizeof(*src));
1800 wmb(); /* barrier before setting valid flag */
1803 /* re-write the last 32-bits with the valid flags */
1804 src->flags = last_flags;
1805 src_ints = (uint32_t *)src;
1807 dst_ints = (volatile uint32_t *)dst;
1809 *dst_ints = *src_ints;
1817 mxge_encap_tso(struct mxge_slice_state *ss, struct mbuf *m,
1818 int busdma_seg_cnt, int ip_off)
1821 mcp_kreq_ether_send_t *req;
1822 bus_dma_segment_t *seg;
1825 uint32_t low, high_swapped;
1826 int len, seglen, cum_len, cum_len_next;
1827 int next_is_first, chop, cnt, rdma_count, small;
1828 uint16_t pseudo_hdr_offset, cksum_offset, mss;
1829 uint8_t flags, flags_next;
1832 mss = m->m_pkthdr.tso_segsz;
1834 /* negative cum_len signifies to the
1835 * send loop that we are still in the
1836 * header portion of the TSO packet.
1839 /* ensure we have the ethernet, IP and TCP
1840 header together in the first mbuf, copy
1841 it to a scratch buffer if not */
1842 if (__predict_false(m->m_len < ip_off + sizeof (*ip))) {
1843 m_copydata(m, 0, ip_off + sizeof (*ip),
1845 ip = (struct ip *)(ss->scratch + ip_off);
1847 ip = (struct ip *)(mtod(m, char *) + ip_off);
1849 if (__predict_false(m->m_len < ip_off + (ip->ip_hl << 2)
1851 m_copydata(m, 0, ip_off + (ip->ip_hl << 2)
1852 + sizeof (*tcp), ss->scratch);
1853 ip = (struct ip *)(mtod(m, char *) + ip_off);
1856 tcp = (struct tcphdr *)((char *)ip + (ip->ip_hl << 2));
1857 cum_len = -(ip_off + ((ip->ip_hl + tcp->th_off) << 2));
1859 /* TSO implies checksum offload on this hardware */
1860 cksum_offset = ip_off + (ip->ip_hl << 2);
1861 flags = MXGEFW_FLAGS_TSO_HDR | MXGEFW_FLAGS_FIRST;
1864 /* for TSO, pseudo_hdr_offset holds mss.
1865 * The firmware figures out where to put
1866 * the checksum by parsing the header. */
1867 pseudo_hdr_offset = htobe16(mss);
1874 /* "rdma_count" is the number of RDMAs belonging to the
1875 * current packet BEFORE the current send request. For
1876 * non-TSO packets, this is equal to "count".
1877 * For TSO packets, rdma_count needs to be reset
1878 * to 0 after a segment cut.
1880 * The rdma_count field of the send request is
1881 * the number of RDMAs of the packet starting at
1882 * that request. For TSO send requests with one ore more cuts
1883 * in the middle, this is the number of RDMAs starting
1884 * after the last cut in the request. All previous
1885 * segments before the last cut implicitly have 1 RDMA.
1887 * Since the number of RDMAs is not known beforehand,
1888 * it must be filled-in retroactively - after each
1889 * segmentation cut or at the end of the entire packet.
1892 while (busdma_seg_cnt) {
1893 /* Break the busdma segment up into pieces*/
1894 low = MXGE_LOWPART_TO_U32(seg->ds_addr);
1895 high_swapped = htobe32(MXGE_HIGHPART_TO_U32(seg->ds_addr));
1899 flags_next = flags & ~MXGEFW_FLAGS_FIRST;
1901 cum_len_next = cum_len + seglen;
1902 (req-rdma_count)->rdma_count = rdma_count + 1;
1903 if (__predict_true(cum_len >= 0)) {
1905 chop = (cum_len_next > mss);
1906 cum_len_next = cum_len_next % mss;
1907 next_is_first = (cum_len_next == 0);
1908 flags |= chop * MXGEFW_FLAGS_TSO_CHOP;
1909 flags_next |= next_is_first *
1911 rdma_count |= -(chop | next_is_first);
1912 rdma_count += chop & !next_is_first;
1913 } else if (cum_len_next >= 0) {
1918 small = (mss <= MXGEFW_SEND_SMALL_SIZE);
1919 flags_next = MXGEFW_FLAGS_TSO_PLD |
1920 MXGEFW_FLAGS_FIRST |
1921 (small * MXGEFW_FLAGS_SMALL);
1924 req->addr_high = high_swapped;
1925 req->addr_low = htobe32(low);
1926 req->pseudo_hdr_offset = pseudo_hdr_offset;
1928 req->rdma_count = 1;
1929 req->length = htobe16(seglen);
1930 req->cksum_offset = cksum_offset;
1931 req->flags = flags | ((cum_len & 1) *
1932 MXGEFW_FLAGS_ALIGN_ODD);
1935 cum_len = cum_len_next;
1940 if (__predict_false(cksum_offset > seglen))
1941 cksum_offset -= seglen;
1944 if (__predict_false(cnt > tx->max_desc))
1950 (req-rdma_count)->rdma_count = rdma_count;
1954 req->flags |= MXGEFW_FLAGS_TSO_LAST;
1955 } while (!(req->flags & (MXGEFW_FLAGS_TSO_CHOP | MXGEFW_FLAGS_FIRST)));
1957 tx->info[((cnt - 1) + tx->req) & tx->mask].flag = 1;
1958 mxge_submit_req(tx, tx->req_list, cnt);
1959 #ifdef IFNET_BUF_RING
1960 if ((ss->sc->num_slices > 1) && tx->queue_active == 0) {
1961 /* tell the NIC to start polling this slice */
1963 tx->queue_active = 1;
1971 bus_dmamap_unload(tx->dmat, tx->info[tx->req & tx->mask].map);
1975 printf("tx->max_desc exceeded via TSO!\n");
1976 printf("mss = %d, %ld, %d!\n", mss,
1977 (long)seg - (long)tx->seg_list, tx->max_desc);
1984 #endif /* IFCAP_TSO4 */
1986 #ifdef MXGE_NEW_VLAN_API
1988 * We reproduce the software vlan tag insertion from
1989 * net/if_vlan.c:vlan_start() here so that we can advertise "hardware"
1990 * vlan tag insertion. We need to advertise this in order to have the
1991 * vlan interface respect our csum offload flags.
1993 static struct mbuf *
1994 mxge_vlan_tag_insert(struct mbuf *m)
1996 struct ether_vlan_header *evl;
1998 M_PREPEND(m, ETHER_VLAN_ENCAP_LEN, M_DONTWAIT);
1999 if (__predict_false(m == NULL))
2001 if (m->m_len < sizeof(*evl)) {
2002 m = m_pullup(m, sizeof(*evl));
2003 if (__predict_false(m == NULL))
2007 * Transform the Ethernet header into an Ethernet header
2008 * with 802.1Q encapsulation.
2010 evl = mtod(m, struct ether_vlan_header *);
2011 bcopy((char *)evl + ETHER_VLAN_ENCAP_LEN,
2012 (char *)evl, ETHER_HDR_LEN - ETHER_TYPE_LEN);
2013 evl->evl_encap_proto = htons(ETHERTYPE_VLAN);
2014 evl->evl_tag = htons(m->m_pkthdr.ether_vtag);
2015 m->m_flags &= ~M_VLANTAG;
2018 #endif /* MXGE_NEW_VLAN_API */
2021 mxge_encap(struct mxge_slice_state *ss, struct mbuf *m)
2024 mcp_kreq_ether_send_t *req;
2025 bus_dma_segment_t *seg;
2030 int cnt, cum_len, err, i, idx, odd_flag, ip_off;
2031 uint16_t pseudo_hdr_offset;
2032 uint8_t flags, cksum_offset;
2039 ip_off = sizeof (struct ether_header);
2040 #ifdef MXGE_NEW_VLAN_API
2041 if (m->m_flags & M_VLANTAG) {
2042 m = mxge_vlan_tag_insert(m);
2043 if (__predict_false(m == NULL))
2045 ip_off += ETHER_VLAN_ENCAP_LEN;
2048 /* (try to) map the frame for DMA */
2049 idx = tx->req & tx->mask;
2050 err = bus_dmamap_load_mbuf_sg(tx->dmat, tx->info[idx].map,
2051 m, tx->seg_list, &cnt,
2053 if (__predict_false(err == EFBIG)) {
2054 /* Too many segments in the chain. Try
2056 m_tmp = m_defrag(m, M_NOWAIT);
2057 if (m_tmp == NULL) {
2062 err = bus_dmamap_load_mbuf_sg(tx->dmat,
2064 m, tx->seg_list, &cnt,
2067 if (__predict_false(err != 0)) {
2068 device_printf(sc->dev, "bus_dmamap_load_mbuf_sg returned %d"
2069 " packet len = %d\n", err, m->m_pkthdr.len);
2072 bus_dmamap_sync(tx->dmat, tx->info[idx].map,
2073 BUS_DMASYNC_PREWRITE);
2074 tx->info[idx].m = m;
2077 /* TSO is different enough, we handle it in another routine */
2078 if (m->m_pkthdr.csum_flags & (CSUM_TSO)) {
2079 mxge_encap_tso(ss, m, cnt, ip_off);
2086 pseudo_hdr_offset = 0;
2087 flags = MXGEFW_FLAGS_NO_TSO;
2089 /* checksum offloading? */
2090 if (m->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) {
2091 /* ensure ip header is in first mbuf, copy
2092 it to a scratch buffer if not */
2093 if (__predict_false(m->m_len < ip_off + sizeof (*ip))) {
2094 m_copydata(m, 0, ip_off + sizeof (*ip),
2096 ip = (struct ip *)(ss->scratch + ip_off);
2098 ip = (struct ip *)(mtod(m, char *) + ip_off);
2100 cksum_offset = ip_off + (ip->ip_hl << 2);
2101 pseudo_hdr_offset = cksum_offset + m->m_pkthdr.csum_data;
2102 pseudo_hdr_offset = htobe16(pseudo_hdr_offset);
2103 req->cksum_offset = cksum_offset;
2104 flags |= MXGEFW_FLAGS_CKSUM;
2105 odd_flag = MXGEFW_FLAGS_ALIGN_ODD;
2109 if (m->m_pkthdr.len < MXGEFW_SEND_SMALL_SIZE)
2110 flags |= MXGEFW_FLAGS_SMALL;
2112 /* convert segments into a request list */
2115 req->flags = MXGEFW_FLAGS_FIRST;
2116 for (i = 0; i < cnt; i++) {
2118 htobe32(MXGE_LOWPART_TO_U32(seg->ds_addr));
2120 htobe32(MXGE_HIGHPART_TO_U32(seg->ds_addr));
2121 req->length = htobe16(seg->ds_len);
2122 req->cksum_offset = cksum_offset;
2123 if (cksum_offset > seg->ds_len)
2124 cksum_offset -= seg->ds_len;
2127 req->pseudo_hdr_offset = pseudo_hdr_offset;
2128 req->pad = 0; /* complete solid 16-byte block */
2129 req->rdma_count = 1;
2130 req->flags |= flags | ((cum_len & 1) * odd_flag);
2131 cum_len += seg->ds_len;
2137 /* pad runts to 60 bytes */
2141 htobe32(MXGE_LOWPART_TO_U32(sc->zeropad_dma.bus_addr));
2143 htobe32(MXGE_HIGHPART_TO_U32(sc->zeropad_dma.bus_addr));
2144 req->length = htobe16(60 - cum_len);
2145 req->cksum_offset = 0;
2146 req->pseudo_hdr_offset = pseudo_hdr_offset;
2147 req->pad = 0; /* complete solid 16-byte block */
2148 req->rdma_count = 1;
2149 req->flags |= flags | ((cum_len & 1) * odd_flag);
2153 tx->req_list[0].rdma_count = cnt;
2155 /* print what the firmware will see */
2156 for (i = 0; i < cnt; i++) {
2157 printf("%d: addr: 0x%x 0x%x len:%d pso%d,"
2158 "cso:%d, flags:0x%x, rdma:%d\n",
2159 i, (int)ntohl(tx->req_list[i].addr_high),
2160 (int)ntohl(tx->req_list[i].addr_low),
2161 (int)ntohs(tx->req_list[i].length),
2162 (int)ntohs(tx->req_list[i].pseudo_hdr_offset),
2163 tx->req_list[i].cksum_offset, tx->req_list[i].flags,
2164 tx->req_list[i].rdma_count);
2166 printf("--------------\n");
2168 tx->info[((cnt - 1) + tx->req) & tx->mask].flag = 1;
2169 mxge_submit_req(tx, tx->req_list, cnt);
2170 #ifdef IFNET_BUF_RING
2171 if ((ss->sc->num_slices > 1) && tx->queue_active == 0) {
2172 /* tell the NIC to start polling this slice */
2174 tx->queue_active = 1;
2187 #ifdef IFNET_BUF_RING
2189 mxge_qflush(struct ifnet *ifp)
2191 mxge_softc_t *sc = ifp->if_softc;
2196 for (slice = 0; slice < sc->num_slices; slice++) {
2197 tx = &sc->ss[slice].tx;
2199 while ((m = buf_ring_dequeue_sc(tx->br)) != NULL)
2201 mtx_unlock(&tx->mtx);
2207 mxge_start_locked(struct mxge_slice_state *ss)
2218 while ((tx->mask - (tx->req - tx->done)) > tx->max_desc) {
2219 m = drbr_dequeue(ifp, tx->br);
2223 /* let BPF see it */
2226 /* give it to the nic */
2229 /* ran out of transmit slots */
2230 if (((ss->if_drv_flags & IFF_DRV_OACTIVE) == 0)
2231 && (!drbr_empty(ifp, tx->br))) {
2232 ss->if_drv_flags |= IFF_DRV_OACTIVE;
2238 mxge_transmit_locked(struct mxge_slice_state *ss, struct mbuf *m)
2249 if ((ss->if_drv_flags & (IFF_DRV_RUNNING|IFF_DRV_OACTIVE)) !=
2251 err = drbr_enqueue(ifp, tx->br, m);
2255 if (!drbr_needs_enqueue(ifp, tx->br) &&
2256 ((tx->mask - (tx->req - tx->done)) > tx->max_desc)) {
2257 /* let BPF see it */
2259 /* give it to the nic */
2261 } else if ((err = drbr_enqueue(ifp, tx->br, m)) != 0) {
2264 if (!drbr_empty(ifp, tx->br))
2265 mxge_start_locked(ss);
2270 mxge_transmit(struct ifnet *ifp, struct mbuf *m)
2272 mxge_softc_t *sc = ifp->if_softc;
2273 struct mxge_slice_state *ss;
2278 slice = m->m_pkthdr.flowid;
2279 slice &= (sc->num_slices - 1); /* num_slices always power of 2 */
2281 ss = &sc->ss[slice];
2284 if (mtx_trylock(&tx->mtx)) {
2285 err = mxge_transmit_locked(ss, m);
2286 mtx_unlock(&tx->mtx);
2288 err = drbr_enqueue(ifp, tx->br, m);
2297 mxge_start_locked(struct mxge_slice_state *ss)
2307 while ((tx->mask - (tx->req - tx->done)) > tx->max_desc) {
2308 IFQ_DRV_DEQUEUE(&ifp->if_snd, m);
2312 /* let BPF see it */
2315 /* give it to the nic */
2318 /* ran out of transmit slots */
2319 if ((sc->ifp->if_drv_flags & IFF_DRV_OACTIVE) == 0) {
2320 sc->ifp->if_drv_flags |= IFF_DRV_OACTIVE;
2326 mxge_start(struct ifnet *ifp)
2328 mxge_softc_t *sc = ifp->if_softc;
2329 struct mxge_slice_state *ss;
2331 /* only use the first slice for now */
2333 mtx_lock(&ss->tx.mtx);
2334 mxge_start_locked(ss);
2335 mtx_unlock(&ss->tx.mtx);
2339 * copy an array of mcp_kreq_ether_recv_t's to the mcp. Copy
2340 * at most 32 bytes at a time, so as to avoid involving the software
2341 * pio handler in the nic. We re-write the first segment's low
2342 * DMA address to mark it valid only after we write the entire chunk
2346 mxge_submit_8rx(volatile mcp_kreq_ether_recv_t *dst,
2347 mcp_kreq_ether_recv_t *src)
2351 low = src->addr_low;
2352 src->addr_low = 0xffffffff;
2353 mxge_pio_copy(dst, src, 4 * sizeof (*src));
2355 mxge_pio_copy(dst + 4, src + 4, 4 * sizeof (*src));
2357 src->addr_low = low;
2358 dst->addr_low = low;
2363 mxge_get_buf_small(struct mxge_slice_state *ss, bus_dmamap_t map, int idx)
2365 bus_dma_segment_t seg;
2367 mxge_rx_ring_t *rx = &ss->rx_small;
2370 m = m_gethdr(M_DONTWAIT, MT_DATA);
2377 err = bus_dmamap_load_mbuf_sg(rx->dmat, map, m,
2378 &seg, &cnt, BUS_DMA_NOWAIT);
2383 rx->info[idx].m = m;
2384 rx->shadow[idx].addr_low =
2385 htobe32(MXGE_LOWPART_TO_U32(seg.ds_addr));
2386 rx->shadow[idx].addr_high =
2387 htobe32(MXGE_HIGHPART_TO_U32(seg.ds_addr));
2391 mxge_submit_8rx(&rx->lanai[idx - 7], &rx->shadow[idx - 7]);
2396 mxge_get_buf_big(struct mxge_slice_state *ss, bus_dmamap_t map, int idx)
2398 bus_dma_segment_t seg[3];
2400 mxge_rx_ring_t *rx = &ss->rx_big;
2403 if (rx->cl_size == MCLBYTES)
2404 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
2406 m = m_getjcl(M_DONTWAIT, MT_DATA, M_PKTHDR, rx->cl_size);
2412 m->m_len = rx->mlen;
2413 err = bus_dmamap_load_mbuf_sg(rx->dmat, map, m,
2414 seg, &cnt, BUS_DMA_NOWAIT);
2419 rx->info[idx].m = m;
2420 rx->shadow[idx].addr_low =
2421 htobe32(MXGE_LOWPART_TO_U32(seg->ds_addr));
2422 rx->shadow[idx].addr_high =
2423 htobe32(MXGE_HIGHPART_TO_U32(seg->ds_addr));
2425 #if MXGE_VIRT_JUMBOS
2426 for (i = 1; i < cnt; i++) {
2427 rx->shadow[idx + i].addr_low =
2428 htobe32(MXGE_LOWPART_TO_U32(seg[i].ds_addr));
2429 rx->shadow[idx + i].addr_high =
2430 htobe32(MXGE_HIGHPART_TO_U32(seg[i].ds_addr));
2435 for (i = 0; i < rx->nbufs; i++) {
2436 if ((idx & 7) == 7) {
2437 mxge_submit_8rx(&rx->lanai[idx - 7],
2438 &rx->shadow[idx - 7]);
2446 * Myri10GE hardware checksums are not valid if the sender
2447 * padded the frame with non-zero padding. This is because
2448 * the firmware just does a simple 16-bit 1s complement
2449 * checksum across the entire frame, excluding the first 14
2450 * bytes. It is best to simply to check the checksum and
2451 * tell the stack about it only if the checksum is good
2454 static inline uint16_t
2455 mxge_rx_csum(struct mbuf *m, int csum)
2457 struct ether_header *eh;
2461 eh = mtod(m, struct ether_header *);
2463 /* only deal with IPv4 TCP & UDP for now */
2464 if (__predict_false(eh->ether_type != htons(ETHERTYPE_IP)))
2466 ip = (struct ip *)(eh + 1);
2467 if (__predict_false(ip->ip_p != IPPROTO_TCP &&
2468 ip->ip_p != IPPROTO_UDP))
2471 c = in_pseudo(ip->ip_src.s_addr, ip->ip_dst.s_addr,
2472 htonl(ntohs(csum) + ntohs(ip->ip_len) +
2473 - (ip->ip_hl << 2) + ip->ip_p));
2482 mxge_vlan_tag_remove(struct mbuf *m, uint32_t *csum)
2484 struct ether_vlan_header *evl;
2485 struct ether_header *eh;
2488 evl = mtod(m, struct ether_vlan_header *);
2489 eh = mtod(m, struct ether_header *);
2492 * fix checksum by subtracting ETHER_VLAN_ENCAP_LEN bytes
2493 * after what the firmware thought was the end of the ethernet
2497 /* put checksum into host byte order */
2498 *csum = ntohs(*csum);
2499 partial = ntohl(*(uint32_t *)(mtod(m, char *) + ETHER_HDR_LEN));
2500 (*csum) += ~partial;
2501 (*csum) += ((*csum) < ~partial);
2502 (*csum) = ((*csum) >> 16) + ((*csum) & 0xFFFF);
2503 (*csum) = ((*csum) >> 16) + ((*csum) & 0xFFFF);
2505 /* restore checksum to network byte order;
2506 later consumers expect this */
2507 *csum = htons(*csum);
2510 #ifdef MXGE_NEW_VLAN_API
2511 m->m_pkthdr.ether_vtag = ntohs(evl->evl_tag);
2515 mtag = m_tag_alloc(MTAG_VLAN, MTAG_VLAN_TAG, sizeof(u_int),
2519 VLAN_TAG_VALUE(mtag) = ntohs(evl->evl_tag);
2520 m_tag_prepend(m, mtag);
2524 m->m_flags |= M_VLANTAG;
2527 * Remove the 802.1q header by copying the Ethernet
2528 * addresses over it and adjusting the beginning of
2529 * the data in the mbuf. The encapsulated Ethernet
2530 * type field is already in place.
2532 bcopy((char *)evl, (char *)evl + ETHER_VLAN_ENCAP_LEN,
2533 ETHER_HDR_LEN - ETHER_TYPE_LEN);
2534 m_adj(m, ETHER_VLAN_ENCAP_LEN);
2539 mxge_rx_done_big(struct mxge_slice_state *ss, uint32_t len, uint32_t csum)
2544 struct ether_header *eh;
2546 bus_dmamap_t old_map;
2548 uint16_t tcpudp_csum;
2553 idx = rx->cnt & rx->mask;
2554 rx->cnt += rx->nbufs;
2555 /* save a pointer to the received mbuf */
2556 m = rx->info[idx].m;
2557 /* try to replace the received mbuf */
2558 if (mxge_get_buf_big(ss, rx->extra_map, idx)) {
2559 /* drop the frame -- the old mbuf is re-cycled */
2564 /* unmap the received buffer */
2565 old_map = rx->info[idx].map;
2566 bus_dmamap_sync(rx->dmat, old_map, BUS_DMASYNC_POSTREAD);
2567 bus_dmamap_unload(rx->dmat, old_map);
2569 /* swap the bus_dmamap_t's */
2570 rx->info[idx].map = rx->extra_map;
2571 rx->extra_map = old_map;
2573 /* mcp implicitly skips 1st 2 bytes so that packet is properly
2575 m->m_data += MXGEFW_PAD;
2577 m->m_pkthdr.rcvif = ifp;
2578 m->m_len = m->m_pkthdr.len = len;
2580 eh = mtod(m, struct ether_header *);
2581 if (eh->ether_type == htons(ETHERTYPE_VLAN)) {
2582 mxge_vlan_tag_remove(m, &csum);
2584 /* if the checksum is valid, mark it in the mbuf header */
2585 if (sc->csum_flag && (0 == (tcpudp_csum = mxge_rx_csum(m, csum)))) {
2586 if (sc->lro_cnt && (0 == mxge_lro_rx(ss, m, csum)))
2588 /* otherwise, it was a UDP frame, or a TCP frame which
2589 we could not do LRO on. Tell the stack that the
2591 m->m_pkthdr.csum_data = 0xffff;
2592 m->m_pkthdr.csum_flags = CSUM_PSEUDO_HDR | CSUM_DATA_VALID;
2594 /* flowid only valid if RSS hashing is enabled */
2595 if (sc->num_slices > 1) {
2596 m->m_pkthdr.flowid = (ss - sc->ss);
2597 m->m_flags |= M_FLOWID;
2599 /* pass the frame up the stack */
2600 (*ifp->if_input)(ifp, m);
2604 mxge_rx_done_small(struct mxge_slice_state *ss, uint32_t len, uint32_t csum)
2608 struct ether_header *eh;
2611 bus_dmamap_t old_map;
2613 uint16_t tcpudp_csum;
2618 idx = rx->cnt & rx->mask;
2620 /* save a pointer to the received mbuf */
2621 m = rx->info[idx].m;
2622 /* try to replace the received mbuf */
2623 if (mxge_get_buf_small(ss, rx->extra_map, idx)) {
2624 /* drop the frame -- the old mbuf is re-cycled */
2629 /* unmap the received buffer */
2630 old_map = rx->info[idx].map;
2631 bus_dmamap_sync(rx->dmat, old_map, BUS_DMASYNC_POSTREAD);
2632 bus_dmamap_unload(rx->dmat, old_map);
2634 /* swap the bus_dmamap_t's */
2635 rx->info[idx].map = rx->extra_map;
2636 rx->extra_map = old_map;
2638 /* mcp implicitly skips 1st 2 bytes so that packet is properly
2640 m->m_data += MXGEFW_PAD;
2642 m->m_pkthdr.rcvif = ifp;
2643 m->m_len = m->m_pkthdr.len = len;
2645 eh = mtod(m, struct ether_header *);
2646 if (eh->ether_type == htons(ETHERTYPE_VLAN)) {
2647 mxge_vlan_tag_remove(m, &csum);
2649 /* if the checksum is valid, mark it in the mbuf header */
2650 if (sc->csum_flag && (0 == (tcpudp_csum = mxge_rx_csum(m, csum)))) {
2651 if (sc->lro_cnt && (0 == mxge_lro_rx(ss, m, csum)))
2653 /* otherwise, it was a UDP frame, or a TCP frame which
2654 we could not do LRO on. Tell the stack that the
2656 m->m_pkthdr.csum_data = 0xffff;
2657 m->m_pkthdr.csum_flags = CSUM_PSEUDO_HDR | CSUM_DATA_VALID;
2659 /* flowid only valid if RSS hashing is enabled */
2660 if (sc->num_slices > 1) {
2661 m->m_pkthdr.flowid = (ss - sc->ss);
2662 m->m_flags |= M_FLOWID;
2664 /* pass the frame up the stack */
2665 (*ifp->if_input)(ifp, m);
2669 mxge_clean_rx_done(struct mxge_slice_state *ss)
2671 mxge_rx_done_t *rx_done = &ss->rx_done;
2677 while (rx_done->entry[rx_done->idx].length != 0) {
2678 length = ntohs(rx_done->entry[rx_done->idx].length);
2679 rx_done->entry[rx_done->idx].length = 0;
2680 checksum = rx_done->entry[rx_done->idx].checksum;
2681 if (length <= (MHLEN - MXGEFW_PAD))
2682 mxge_rx_done_small(ss, length, checksum);
2684 mxge_rx_done_big(ss, length, checksum);
2686 rx_done->idx = rx_done->cnt & rx_done->mask;
2688 /* limit potential for livelock */
2689 if (__predict_false(++limit > rx_done->mask / 2))
2693 while (!SLIST_EMPTY(&ss->lro_active)) {
2694 struct lro_entry *lro = SLIST_FIRST(&ss->lro_active);
2695 SLIST_REMOVE_HEAD(&ss->lro_active, next);
2696 mxge_lro_flush(ss, lro);
2703 mxge_tx_done(struct mxge_slice_state *ss, uint32_t mcp_idx)
2714 while (tx->pkt_done != mcp_idx) {
2715 idx = tx->done & tx->mask;
2717 m = tx->info[idx].m;
2718 /* mbuf and DMA map only attached to the first
2721 ss->obytes += m->m_pkthdr.len;
2722 if (m->m_flags & M_MCAST)
2725 tx->info[idx].m = NULL;
2726 map = tx->info[idx].map;
2727 bus_dmamap_unload(tx->dmat, map);
2730 if (tx->info[idx].flag) {
2731 tx->info[idx].flag = 0;
2736 /* If we have space, clear IFF_OACTIVE to tell the stack that
2737 its OK to send packets */
2738 #ifdef IFNET_BUF_RING
2739 flags = &ss->if_drv_flags;
2741 flags = &ifp->if_drv_flags;
2743 mtx_lock(&ss->tx.mtx);
2744 if ((*flags) & IFF_DRV_OACTIVE &&
2745 tx->req - tx->done < (tx->mask + 1)/4) {
2746 *(flags) &= ~IFF_DRV_OACTIVE;
2748 mxge_start_locked(ss);
2750 #ifdef IFNET_BUF_RING
2751 if ((ss->sc->num_slices > 1) && (tx->req == tx->done)) {
2752 /* let the NIC stop polling this queue, since there
2753 * are no more transmits pending */
2754 if (tx->req == tx->done) {
2756 tx->queue_active = 0;
2762 mtx_unlock(&ss->tx.mtx);
2766 static struct mxge_media_type mxge_xfp_media_types[] =
2768 {IFM_10G_CX4, 0x7f, "10GBASE-CX4 (module)"},
2769 {IFM_10G_SR, (1 << 7), "10GBASE-SR"},
2770 {IFM_10G_LR, (1 << 6), "10GBASE-LR"},
2771 {0, (1 << 5), "10GBASE-ER"},
2772 {IFM_10G_LRM, (1 << 4), "10GBASE-LRM"},
2773 {0, (1 << 3), "10GBASE-SW"},
2774 {0, (1 << 2), "10GBASE-LW"},
2775 {0, (1 << 1), "10GBASE-EW"},
2776 {0, (1 << 0), "Reserved"}
2778 static struct mxge_media_type mxge_sfp_media_types[] =
2780 {IFM_10G_TWINAX, 0, "10GBASE-Twinax"},
2781 {0, (1 << 7), "Reserved"},
2782 {IFM_10G_LRM, (1 << 6), "10GBASE-LRM"},
2783 {IFM_10G_LR, (1 << 5), "10GBASE-LR"},
2784 {IFM_10G_SR, (1 << 4), "10GBASE-SR"},
2785 {IFM_10G_TWINAX,(1 << 0), "10GBASE-Twinax"}
2789 mxge_media_set(mxge_softc_t *sc, int media_type)
2793 ifmedia_add(&sc->media, IFM_ETHER | IFM_FDX | media_type,
2795 ifmedia_set(&sc->media, IFM_ETHER | IFM_FDX | media_type);
2796 sc->current_media = media_type;
2797 sc->media.ifm_media = sc->media.ifm_cur->ifm_media;
2801 mxge_media_init(mxge_softc_t *sc)
2806 ifmedia_removeall(&sc->media);
2807 mxge_media_set(sc, IFM_AUTO);
2810 * parse the product code to deterimine the interface type
2811 * (CX4, XFP, Quad Ribbon Fiber) by looking at the character
2812 * after the 3rd dash in the driver's cached copy of the
2813 * EEPROM's product code string.
2815 ptr = sc->product_code_string;
2817 device_printf(sc->dev, "Missing product code\n");
2821 for (i = 0; i < 3; i++, ptr++) {
2822 ptr = index(ptr, '-');
2824 device_printf(sc->dev,
2825 "only %d dashes in PC?!?\n", i);
2831 sc->connector = MXGE_CX4;
2832 mxge_media_set(sc, IFM_10G_CX4);
2833 } else if (*ptr == 'Q') {
2834 /* -Q is Quad Ribbon Fiber */
2835 sc->connector = MXGE_QRF;
2836 device_printf(sc->dev, "Quad Ribbon Fiber Media\n");
2837 /* FreeBSD has no media type for Quad ribbon fiber */
2838 } else if (*ptr == 'R') {
2840 sc->connector = MXGE_XFP;
2841 } else if (*ptr == 'S' || *(ptr +1) == 'S') {
2842 /* -S or -2S is SFP+ */
2843 sc->connector = MXGE_SFP;
2845 device_printf(sc->dev, "Unknown media type: %c\n", *ptr);
2850 * Determine the media type for a NIC. Some XFPs will identify
2851 * themselves only when their link is up, so this is initiated via a
2852 * link up interrupt. However, this can potentially take up to
2853 * several milliseconds, so it is run via the watchdog routine, rather
2854 * than in the interrupt handler itself.
2857 mxge_media_probe(mxge_softc_t *sc)
2862 struct mxge_media_type *mxge_media_types = NULL;
2863 int i, err, ms, mxge_media_type_entries;
2866 sc->need_media_probe = 0;
2868 if (sc->connector == MXGE_XFP) {
2870 mxge_media_types = mxge_xfp_media_types;
2871 mxge_media_type_entries =
2872 sizeof (mxge_xfp_media_types) /
2873 sizeof (mxge_xfp_media_types[0]);
2874 byte = MXGE_XFP_COMPLIANCE_BYTE;
2876 } else if (sc->connector == MXGE_SFP) {
2877 /* -S or -2S is SFP+ */
2878 mxge_media_types = mxge_sfp_media_types;
2879 mxge_media_type_entries =
2880 sizeof (mxge_sfp_media_types) /
2881 sizeof (mxge_sfp_media_types[0]);
2885 /* nothing to do; media type cannot change */
2890 * At this point we know the NIC has an XFP cage, so now we
2891 * try to determine what is in the cage by using the
2892 * firmware's XFP I2C commands to read the XFP 10GbE compilance
2893 * register. We read just one byte, which may take over
2897 cmd.data0 = 0; /* just fetch 1 byte, not all 256 */
2899 err = mxge_send_cmd(sc, MXGEFW_CMD_I2C_READ, &cmd);
2900 if (err == MXGEFW_CMD_ERROR_I2C_FAILURE) {
2901 device_printf(sc->dev, "failed to read XFP\n");
2903 if (err == MXGEFW_CMD_ERROR_I2C_ABSENT) {
2904 device_printf(sc->dev, "Type R/S with no XFP!?!?\n");
2906 if (err != MXGEFW_CMD_OK) {
2910 /* now we wait for the data to be cached */
2912 err = mxge_send_cmd(sc, MXGEFW_CMD_I2C_BYTE, &cmd);
2913 for (ms = 0; (err == EBUSY) && (ms < 50); ms++) {
2916 err = mxge_send_cmd(sc, MXGEFW_CMD_I2C_BYTE, &cmd);
2918 if (err != MXGEFW_CMD_OK) {
2919 device_printf(sc->dev, "failed to read %s (%d, %dms)\n",
2920 cage_type, err, ms);
2924 if (cmd.data0 == mxge_media_types[0].bitmask) {
2926 device_printf(sc->dev, "%s:%s\n", cage_type,
2927 mxge_media_types[0].name);
2928 if (sc->current_media != mxge_media_types[0].flag) {
2929 mxge_media_init(sc);
2930 mxge_media_set(sc, mxge_media_types[0].flag);
2934 for (i = 1; i < mxge_media_type_entries; i++) {
2935 if (cmd.data0 & mxge_media_types[i].bitmask) {
2937 device_printf(sc->dev, "%s:%s\n",
2939 mxge_media_types[i].name);
2941 if (sc->current_media != mxge_media_types[i].flag) {
2942 mxge_media_init(sc);
2943 mxge_media_set(sc, mxge_media_types[i].flag);
2949 device_printf(sc->dev, "%s media 0x%x unknown\n",
2950 cage_type, cmd.data0);
2956 mxge_intr(void *arg)
2958 struct mxge_slice_state *ss = arg;
2959 mxge_softc_t *sc = ss->sc;
2960 mcp_irq_data_t *stats = ss->fw_stats;
2961 mxge_tx_ring_t *tx = &ss->tx;
2962 mxge_rx_done_t *rx_done = &ss->rx_done;
2963 uint32_t send_done_count;
2967 #ifndef IFNET_BUF_RING
2968 /* an interrupt on a non-zero slice is implicitly valid
2969 since MSI-X irqs are not shared */
2971 mxge_clean_rx_done(ss);
2972 *ss->irq_claim = be32toh(3);
2977 /* make sure the DMA has finished */
2978 if (!stats->valid) {
2981 valid = stats->valid;
2983 if (sc->legacy_irq) {
2984 /* lower legacy IRQ */
2985 *sc->irq_deassert = 0;
2986 if (!mxge_deassert_wait)
2987 /* don't wait for conf. that irq is low */
2993 /* loop while waiting for legacy irq deassertion */
2995 /* check for transmit completes and receives */
2996 send_done_count = be32toh(stats->send_done_count);
2997 while ((send_done_count != tx->pkt_done) ||
2998 (rx_done->entry[rx_done->idx].length != 0)) {
2999 if (send_done_count != tx->pkt_done)
3000 mxge_tx_done(ss, (int)send_done_count);
3001 mxge_clean_rx_done(ss);
3002 send_done_count = be32toh(stats->send_done_count);
3004 if (sc->legacy_irq && mxge_deassert_wait)
3006 } while (*((volatile uint8_t *) &stats->valid));
3008 /* fw link & error stats meaningful only on the first slice */
3009 if (__predict_false((ss == sc->ss) && stats->stats_updated)) {
3010 if (sc->link_state != stats->link_up) {
3011 sc->link_state = stats->link_up;
3012 if (sc->link_state) {
3013 if_link_state_change(sc->ifp, LINK_STATE_UP);
3014 sc->ifp->if_baudrate = IF_Gbps(10UL);
3016 device_printf(sc->dev, "link up\n");
3018 if_link_state_change(sc->ifp, LINK_STATE_DOWN);
3019 sc->ifp->if_baudrate = 0;
3021 device_printf(sc->dev, "link down\n");
3023 sc->need_media_probe = 1;
3025 if (sc->rdma_tags_available !=
3026 be32toh(stats->rdma_tags_available)) {
3027 sc->rdma_tags_available =
3028 be32toh(stats->rdma_tags_available);
3029 device_printf(sc->dev, "RDMA timed out! %d tags "
3030 "left\n", sc->rdma_tags_available);
3033 if (stats->link_down) {
3034 sc->down_cnt += stats->link_down;
3036 if_link_state_change(sc->ifp, LINK_STATE_DOWN);
3040 /* check to see if we have rx token to pass back */
3042 *ss->irq_claim = be32toh(3);
3043 *(ss->irq_claim + 1) = be32toh(3);
3047 mxge_init(void *arg)
3054 mxge_free_slice_mbufs(struct mxge_slice_state *ss)
3056 struct lro_entry *lro_entry;
3059 while (!SLIST_EMPTY(&ss->lro_free)) {
3060 lro_entry = SLIST_FIRST(&ss->lro_free);
3061 SLIST_REMOVE_HEAD(&ss->lro_free, next);
3062 free(lro_entry, M_DEVBUF);
3065 for (i = 0; i <= ss->rx_big.mask; i++) {
3066 if (ss->rx_big.info[i].m == NULL)
3068 bus_dmamap_unload(ss->rx_big.dmat,
3069 ss->rx_big.info[i].map);
3070 m_freem(ss->rx_big.info[i].m);
3071 ss->rx_big.info[i].m = NULL;
3074 for (i = 0; i <= ss->rx_small.mask; i++) {
3075 if (ss->rx_small.info[i].m == NULL)
3077 bus_dmamap_unload(ss->rx_small.dmat,
3078 ss->rx_small.info[i].map);
3079 m_freem(ss->rx_small.info[i].m);
3080 ss->rx_small.info[i].m = NULL;
3083 /* transmit ring used only on the first slice */
3084 if (ss->tx.info == NULL)
3087 for (i = 0; i <= ss->tx.mask; i++) {
3088 ss->tx.info[i].flag = 0;
3089 if (ss->tx.info[i].m == NULL)
3091 bus_dmamap_unload(ss->tx.dmat,
3092 ss->tx.info[i].map);
3093 m_freem(ss->tx.info[i].m);
3094 ss->tx.info[i].m = NULL;
3099 mxge_free_mbufs(mxge_softc_t *sc)
3103 for (slice = 0; slice < sc->num_slices; slice++)
3104 mxge_free_slice_mbufs(&sc->ss[slice]);
3108 mxge_free_slice_rings(struct mxge_slice_state *ss)
3113 if (ss->rx_done.entry != NULL)
3114 mxge_dma_free(&ss->rx_done.dma);
3115 ss->rx_done.entry = NULL;
3117 if (ss->tx.req_bytes != NULL)
3118 free(ss->tx.req_bytes, M_DEVBUF);
3119 ss->tx.req_bytes = NULL;
3121 if (ss->tx.seg_list != NULL)
3122 free(ss->tx.seg_list, M_DEVBUF);
3123 ss->tx.seg_list = NULL;
3125 if (ss->rx_small.shadow != NULL)
3126 free(ss->rx_small.shadow, M_DEVBUF);
3127 ss->rx_small.shadow = NULL;
3129 if (ss->rx_big.shadow != NULL)
3130 free(ss->rx_big.shadow, M_DEVBUF);
3131 ss->rx_big.shadow = NULL;
3133 if (ss->tx.info != NULL) {
3134 if (ss->tx.dmat != NULL) {
3135 for (i = 0; i <= ss->tx.mask; i++) {
3136 bus_dmamap_destroy(ss->tx.dmat,
3137 ss->tx.info[i].map);
3139 bus_dma_tag_destroy(ss->tx.dmat);
3141 free(ss->tx.info, M_DEVBUF);
3145 if (ss->rx_small.info != NULL) {
3146 if (ss->rx_small.dmat != NULL) {
3147 for (i = 0; i <= ss->rx_small.mask; i++) {
3148 bus_dmamap_destroy(ss->rx_small.dmat,
3149 ss->rx_small.info[i].map);
3151 bus_dmamap_destroy(ss->rx_small.dmat,
3152 ss->rx_small.extra_map);
3153 bus_dma_tag_destroy(ss->rx_small.dmat);
3155 free(ss->rx_small.info, M_DEVBUF);
3157 ss->rx_small.info = NULL;
3159 if (ss->rx_big.info != NULL) {
3160 if (ss->rx_big.dmat != NULL) {
3161 for (i = 0; i <= ss->rx_big.mask; i++) {
3162 bus_dmamap_destroy(ss->rx_big.dmat,
3163 ss->rx_big.info[i].map);
3165 bus_dmamap_destroy(ss->rx_big.dmat,
3166 ss->rx_big.extra_map);
3167 bus_dma_tag_destroy(ss->rx_big.dmat);
3169 free(ss->rx_big.info, M_DEVBUF);
3171 ss->rx_big.info = NULL;
3175 mxge_free_rings(mxge_softc_t *sc)
3179 for (slice = 0; slice < sc->num_slices; slice++)
3180 mxge_free_slice_rings(&sc->ss[slice]);
3184 mxge_alloc_slice_rings(struct mxge_slice_state *ss, int rx_ring_entries,
3185 int tx_ring_entries)
3187 mxge_softc_t *sc = ss->sc;
3193 /* allocate per-slice receive resources */
3195 ss->rx_small.mask = ss->rx_big.mask = rx_ring_entries - 1;
3196 ss->rx_done.mask = (2 * rx_ring_entries) - 1;
3198 /* allocate the rx shadow rings */
3199 bytes = rx_ring_entries * sizeof (*ss->rx_small.shadow);
3200 ss->rx_small.shadow = malloc(bytes, M_DEVBUF, M_ZERO|M_WAITOK);
3201 if (ss->rx_small.shadow == NULL)
3204 bytes = rx_ring_entries * sizeof (*ss->rx_big.shadow);
3205 ss->rx_big.shadow = malloc(bytes, M_DEVBUF, M_ZERO|M_WAITOK);
3206 if (ss->rx_big.shadow == NULL)
3209 /* allocate the rx host info rings */
3210 bytes = rx_ring_entries * sizeof (*ss->rx_small.info);
3211 ss->rx_small.info = malloc(bytes, M_DEVBUF, M_ZERO|M_WAITOK);
3212 if (ss->rx_small.info == NULL)
3215 bytes = rx_ring_entries * sizeof (*ss->rx_big.info);
3216 ss->rx_big.info = malloc(bytes, M_DEVBUF, M_ZERO|M_WAITOK);
3217 if (ss->rx_big.info == NULL)
3220 /* allocate the rx busdma resources */
3221 err = bus_dma_tag_create(sc->parent_dmat, /* parent */
3223 4096, /* boundary */
3224 BUS_SPACE_MAXADDR, /* low */
3225 BUS_SPACE_MAXADDR, /* high */
3226 NULL, NULL, /* filter */
3227 MHLEN, /* maxsize */
3229 MHLEN, /* maxsegsize */
3230 BUS_DMA_ALLOCNOW, /* flags */
3231 NULL, NULL, /* lock */
3232 &ss->rx_small.dmat); /* tag */
3234 device_printf(sc->dev, "Err %d allocating rx_small dmat\n",
3239 err = bus_dma_tag_create(sc->parent_dmat, /* parent */
3241 #if MXGE_VIRT_JUMBOS
3242 4096, /* boundary */
3246 BUS_SPACE_MAXADDR, /* low */
3247 BUS_SPACE_MAXADDR, /* high */
3248 NULL, NULL, /* filter */
3249 3*4096, /* maxsize */
3250 #if MXGE_VIRT_JUMBOS
3252 4096, /* maxsegsize*/
3255 MJUM9BYTES, /* maxsegsize*/
3257 BUS_DMA_ALLOCNOW, /* flags */
3258 NULL, NULL, /* lock */
3259 &ss->rx_big.dmat); /* tag */
3261 device_printf(sc->dev, "Err %d allocating rx_big dmat\n",
3265 for (i = 0; i <= ss->rx_small.mask; i++) {
3266 err = bus_dmamap_create(ss->rx_small.dmat, 0,
3267 &ss->rx_small.info[i].map);
3269 device_printf(sc->dev, "Err %d rx_small dmamap\n",
3274 err = bus_dmamap_create(ss->rx_small.dmat, 0,
3275 &ss->rx_small.extra_map);
3277 device_printf(sc->dev, "Err %d extra rx_small dmamap\n",
3282 for (i = 0; i <= ss->rx_big.mask; i++) {
3283 err = bus_dmamap_create(ss->rx_big.dmat, 0,
3284 &ss->rx_big.info[i].map);
3286 device_printf(sc->dev, "Err %d rx_big dmamap\n",
3291 err = bus_dmamap_create(ss->rx_big.dmat, 0,
3292 &ss->rx_big.extra_map);
3294 device_printf(sc->dev, "Err %d extra rx_big dmamap\n",
3299 /* now allocate TX resouces */
3301 #ifndef IFNET_BUF_RING
3302 /* only use a single TX ring for now */
3303 if (ss != ss->sc->ss)
3307 ss->tx.mask = tx_ring_entries - 1;
3308 ss->tx.max_desc = MIN(MXGE_MAX_SEND_DESC, tx_ring_entries / 4);
3311 /* allocate the tx request copy block */
3313 sizeof (*ss->tx.req_list) * (ss->tx.max_desc + 4);
3314 ss->tx.req_bytes = malloc(bytes, M_DEVBUF, M_WAITOK);
3315 if (ss->tx.req_bytes == NULL)
3317 /* ensure req_list entries are aligned to 8 bytes */
3318 ss->tx.req_list = (mcp_kreq_ether_send_t *)
3319 ((unsigned long)(ss->tx.req_bytes + 7) & ~7UL);
3321 /* allocate the tx busdma segment list */
3322 bytes = sizeof (*ss->tx.seg_list) * ss->tx.max_desc;
3323 ss->tx.seg_list = (bus_dma_segment_t *)
3324 malloc(bytes, M_DEVBUF, M_WAITOK);
3325 if (ss->tx.seg_list == NULL)
3328 /* allocate the tx host info ring */
3329 bytes = tx_ring_entries * sizeof (*ss->tx.info);
3330 ss->tx.info = malloc(bytes, M_DEVBUF, M_ZERO|M_WAITOK);
3331 if (ss->tx.info == NULL)
3334 /* allocate the tx busdma resources */
3335 err = bus_dma_tag_create(sc->parent_dmat, /* parent */
3337 sc->tx_boundary, /* boundary */
3338 BUS_SPACE_MAXADDR, /* low */
3339 BUS_SPACE_MAXADDR, /* high */
3340 NULL, NULL, /* filter */
3341 65536 + 256, /* maxsize */
3342 ss->tx.max_desc - 2, /* num segs */
3343 sc->tx_boundary, /* maxsegsz */
3344 BUS_DMA_ALLOCNOW, /* flags */
3345 NULL, NULL, /* lock */
3346 &ss->tx.dmat); /* tag */
3349 device_printf(sc->dev, "Err %d allocating tx dmat\n",
3354 /* now use these tags to setup dmamaps for each slot
3356 for (i = 0; i <= ss->tx.mask; i++) {
3357 err = bus_dmamap_create(ss->tx.dmat, 0,
3358 &ss->tx.info[i].map);
3360 device_printf(sc->dev, "Err %d tx dmamap\n",
3370 mxge_alloc_rings(mxge_softc_t *sc)
3374 int tx_ring_entries, rx_ring_entries;
3377 /* get ring sizes */
3378 err = mxge_send_cmd(sc, MXGEFW_CMD_GET_SEND_RING_SIZE, &cmd);
3379 tx_ring_size = cmd.data0;
3381 device_printf(sc->dev, "Cannot determine tx ring sizes\n");
3385 tx_ring_entries = tx_ring_size / sizeof (mcp_kreq_ether_send_t);
3386 rx_ring_entries = sc->rx_ring_size / sizeof (mcp_dma_addr_t);
3387 IFQ_SET_MAXLEN(&sc->ifp->if_snd, tx_ring_entries - 1);
3388 sc->ifp->if_snd.ifq_drv_maxlen = sc->ifp->if_snd.ifq_maxlen;
3389 IFQ_SET_READY(&sc->ifp->if_snd);
3391 for (slice = 0; slice < sc->num_slices; slice++) {
3392 err = mxge_alloc_slice_rings(&sc->ss[slice],
3401 mxge_free_rings(sc);
3408 mxge_choose_params(int mtu, int *big_buf_size, int *cl_size, int *nbufs)
3410 int bufsize = mtu + ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + MXGEFW_PAD;
3412 if (bufsize < MCLBYTES) {
3413 /* easy, everything fits in a single buffer */
3414 *big_buf_size = MCLBYTES;
3415 *cl_size = MCLBYTES;
3420 if (bufsize < MJUMPAGESIZE) {
3421 /* still easy, everything still fits in a single buffer */
3422 *big_buf_size = MJUMPAGESIZE;
3423 *cl_size = MJUMPAGESIZE;
3427 #if MXGE_VIRT_JUMBOS
3428 /* now we need to use virtually contiguous buffers */
3429 *cl_size = MJUM9BYTES;
3430 *big_buf_size = 4096;
3431 *nbufs = mtu / 4096 + 1;
3432 /* needs to be a power of two, so round up */
3436 *cl_size = MJUM9BYTES;
3437 *big_buf_size = MJUM9BYTES;
3443 mxge_slice_open(struct mxge_slice_state *ss, int nbufs, int cl_size)
3448 struct lro_entry *lro_entry;
3453 slice = ss - sc->ss;
3455 SLIST_INIT(&ss->lro_free);
3456 SLIST_INIT(&ss->lro_active);
3458 for (i = 0; i < sc->lro_cnt; i++) {
3459 lro_entry = (struct lro_entry *)
3460 malloc(sizeof (*lro_entry), M_DEVBUF,
3462 if (lro_entry == NULL) {
3466 SLIST_INSERT_HEAD(&ss->lro_free, lro_entry, next);
3468 /* get the lanai pointers to the send and receive rings */
3471 #ifndef IFNET_BUF_RING
3472 /* We currently only send from the first slice */
3476 err = mxge_send_cmd(sc, MXGEFW_CMD_GET_SEND_OFFSET, &cmd);
3478 (volatile mcp_kreq_ether_send_t *)(sc->sram + cmd.data0);
3479 ss->tx.send_go = (volatile uint32_t *)
3480 (sc->sram + MXGEFW_ETH_SEND_GO + 64 * slice);
3481 ss->tx.send_stop = (volatile uint32_t *)
3482 (sc->sram + MXGEFW_ETH_SEND_STOP + 64 * slice);
3483 #ifndef IFNET_BUF_RING
3487 err |= mxge_send_cmd(sc,
3488 MXGEFW_CMD_GET_SMALL_RX_OFFSET, &cmd);
3489 ss->rx_small.lanai =
3490 (volatile mcp_kreq_ether_recv_t *)(sc->sram + cmd.data0);
3492 err |= mxge_send_cmd(sc, MXGEFW_CMD_GET_BIG_RX_OFFSET, &cmd);
3494 (volatile mcp_kreq_ether_recv_t *)(sc->sram + cmd.data0);
3497 device_printf(sc->dev,
3498 "failed to get ring sizes or locations\n");
3502 /* stock receive rings */
3503 for (i = 0; i <= ss->rx_small.mask; i++) {
3504 map = ss->rx_small.info[i].map;
3505 err = mxge_get_buf_small(ss, map, i);
3507 device_printf(sc->dev, "alloced %d/%d smalls\n",
3508 i, ss->rx_small.mask + 1);
3512 for (i = 0; i <= ss->rx_big.mask; i++) {
3513 ss->rx_big.shadow[i].addr_low = 0xffffffff;
3514 ss->rx_big.shadow[i].addr_high = 0xffffffff;
3516 ss->rx_big.nbufs = nbufs;
3517 ss->rx_big.cl_size = cl_size;
3518 ss->rx_big.mlen = ss->sc->ifp->if_mtu + ETHER_HDR_LEN +
3519 ETHER_VLAN_ENCAP_LEN + MXGEFW_PAD;
3520 for (i = 0; i <= ss->rx_big.mask; i += ss->rx_big.nbufs) {
3521 map = ss->rx_big.info[i].map;
3522 err = mxge_get_buf_big(ss, map, i);
3524 device_printf(sc->dev, "alloced %d/%d bigs\n",
3525 i, ss->rx_big.mask + 1);
3533 mxge_open(mxge_softc_t *sc)
3536 int err, big_bytes, nbufs, slice, cl_size, i;
3538 volatile uint8_t *itable;
3539 struct mxge_slice_state *ss;
3541 /* Copy the MAC address in case it was overridden */
3542 bcopy(IF_LLADDR(sc->ifp), sc->mac_addr, ETHER_ADDR_LEN);
3544 err = mxge_reset(sc, 1);
3546 device_printf(sc->dev, "failed to reset\n");
3550 if (sc->num_slices > 1) {
3551 /* setup the indirection table */
3552 cmd.data0 = sc->num_slices;
3553 err = mxge_send_cmd(sc, MXGEFW_CMD_SET_RSS_TABLE_SIZE,
3556 err |= mxge_send_cmd(sc, MXGEFW_CMD_GET_RSS_TABLE_OFFSET,
3559 device_printf(sc->dev,
3560 "failed to setup rss tables\n");
3564 /* just enable an identity mapping */
3565 itable = sc->sram + cmd.data0;
3566 for (i = 0; i < sc->num_slices; i++)
3567 itable[i] = (uint8_t)i;
3570 cmd.data1 = mxge_rss_hash_type;
3571 err = mxge_send_cmd(sc, MXGEFW_CMD_SET_RSS_ENABLE, &cmd);
3573 device_printf(sc->dev, "failed to enable slices\n");
3579 mxge_choose_params(sc->ifp->if_mtu, &big_bytes, &cl_size, &nbufs);
3582 err = mxge_send_cmd(sc, MXGEFW_CMD_ALWAYS_USE_N_BIG_BUFFERS,
3584 /* error is only meaningful if we're trying to set
3585 MXGEFW_CMD_ALWAYS_USE_N_BIG_BUFFERS > 1 */
3586 if (err && nbufs > 1) {
3587 device_printf(sc->dev,
3588 "Failed to set alway-use-n to %d\n",
3592 /* Give the firmware the mtu and the big and small buffer
3593 sizes. The firmware wants the big buf size to be a power
3594 of two. Luckily, FreeBSD's clusters are powers of two */
3595 cmd.data0 = sc->ifp->if_mtu + ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN;
3596 err = mxge_send_cmd(sc, MXGEFW_CMD_SET_MTU, &cmd);
3597 cmd.data0 = MHLEN - MXGEFW_PAD;
3598 err |= mxge_send_cmd(sc, MXGEFW_CMD_SET_SMALL_BUFFER_SIZE,
3600 cmd.data0 = big_bytes;
3601 err |= mxge_send_cmd(sc, MXGEFW_CMD_SET_BIG_BUFFER_SIZE, &cmd);
3604 device_printf(sc->dev, "failed to setup params\n");
3608 /* Now give him the pointer to the stats block */
3610 #ifdef IFNET_BUF_RING
3611 slice < sc->num_slices;
3616 ss = &sc->ss[slice];
3618 MXGE_LOWPART_TO_U32(ss->fw_stats_dma.bus_addr);
3620 MXGE_HIGHPART_TO_U32(ss->fw_stats_dma.bus_addr);
3621 cmd.data2 = sizeof(struct mcp_irq_data);
3622 cmd.data2 |= (slice << 16);
3623 err |= mxge_send_cmd(sc, MXGEFW_CMD_SET_STATS_DMA_V2, &cmd);
3627 bus = sc->ss->fw_stats_dma.bus_addr;
3628 bus += offsetof(struct mcp_irq_data, send_done_count);
3629 cmd.data0 = MXGE_LOWPART_TO_U32(bus);
3630 cmd.data1 = MXGE_HIGHPART_TO_U32(bus);
3631 err = mxge_send_cmd(sc,
3632 MXGEFW_CMD_SET_STATS_DMA_OBSOLETE,
3634 /* Firmware cannot support multicast without STATS_DMA_V2 */
3635 sc->fw_multicast_support = 0;
3637 sc->fw_multicast_support = 1;
3641 device_printf(sc->dev, "failed to setup params\n");
3645 for (slice = 0; slice < sc->num_slices; slice++) {
3646 err = mxge_slice_open(&sc->ss[slice], nbufs, cl_size);
3648 device_printf(sc->dev, "couldn't open slice %d\n",
3654 /* Finally, start the firmware running */
3655 err = mxge_send_cmd(sc, MXGEFW_CMD_ETHERNET_UP, &cmd);
3657 device_printf(sc->dev, "Couldn't bring up link\n");
3660 #ifdef IFNET_BUF_RING
3661 for (slice = 0; slice < sc->num_slices; slice++) {
3662 ss = &sc->ss[slice];
3663 ss->if_drv_flags |= IFF_DRV_RUNNING;
3664 ss->if_drv_flags &= ~IFF_DRV_OACTIVE;
3667 sc->ifp->if_drv_flags |= IFF_DRV_RUNNING;
3668 sc->ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
3674 mxge_free_mbufs(sc);
3680 mxge_close(mxge_softc_t *sc, int down)
3683 int err, old_down_cnt;
3684 #ifdef IFNET_BUF_RING
3685 struct mxge_slice_state *ss;
3689 #ifdef IFNET_BUF_RING
3690 for (slice = 0; slice < sc->num_slices; slice++) {
3691 ss = &sc->ss[slice];
3692 ss->if_drv_flags &= ~IFF_DRV_RUNNING;
3695 sc->ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
3697 old_down_cnt = sc->down_cnt;
3699 err = mxge_send_cmd(sc, MXGEFW_CMD_ETHERNET_DOWN, &cmd);
3701 device_printf(sc->dev,
3702 "Couldn't bring down link\n");
3704 if (old_down_cnt == sc->down_cnt) {
3705 /* wait for down irq */
3706 DELAY(10 * sc->intr_coal_delay);
3709 if (old_down_cnt == sc->down_cnt) {
3710 device_printf(sc->dev, "never got down irq\n");
3713 mxge_free_mbufs(sc);
3719 mxge_setup_cfg_space(mxge_softc_t *sc)
3721 device_t dev = sc->dev;
3723 uint16_t cmd, lnk, pectl;
3725 /* find the PCIe link width and set max read request to 4KB*/
3726 if (pci_find_extcap(dev, PCIY_EXPRESS, ®) == 0) {
3727 lnk = pci_read_config(dev, reg + 0x12, 2);
3728 sc->link_width = (lnk >> 4) & 0x3f;
3730 if (sc->pectl == 0) {
3731 pectl = pci_read_config(dev, reg + 0x8, 2);
3732 pectl = (pectl & ~0x7000) | (5 << 12);
3733 pci_write_config(dev, reg + 0x8, pectl, 2);
3736 /* restore saved pectl after watchdog reset */
3737 pci_write_config(dev, reg + 0x8, sc->pectl, 2);
3741 /* Enable DMA and Memory space access */
3742 pci_enable_busmaster(dev);
3743 cmd = pci_read_config(dev, PCIR_COMMAND, 2);
3744 cmd |= PCIM_CMD_MEMEN;
3745 pci_write_config(dev, PCIR_COMMAND, cmd, 2);
3749 mxge_read_reboot(mxge_softc_t *sc)
3751 device_t dev = sc->dev;
3754 /* find the vendor specific offset */
3755 if (pci_find_extcap(dev, PCIY_VENDOR, &vs) != 0) {
3756 device_printf(sc->dev,
3757 "could not find vendor specific offset\n");
3758 return (uint32_t)-1;
3760 /* enable read32 mode */
3761 pci_write_config(dev, vs + 0x10, 0x3, 1);
3762 /* tell NIC which register to read */
3763 pci_write_config(dev, vs + 0x18, 0xfffffff0, 4);
3764 return (pci_read_config(dev, vs + 0x14, 4));
3768 mxge_watchdog_reset(mxge_softc_t *sc)
3770 struct pci_devinfo *dinfo;
3771 struct mxge_slice_state *ss;
3772 int err, running, s, num_tx_slices = 1;
3778 device_printf(sc->dev, "Watchdog reset!\n");
3781 * check to see if the NIC rebooted. If it did, then all of
3782 * PCI config space has been reset, and things like the
3783 * busmaster bit will be zero. If this is the case, then we
3784 * must restore PCI config space before the NIC can be used
3787 cmd = pci_read_config(sc->dev, PCIR_COMMAND, 2);
3788 if (cmd == 0xffff) {
3790 * maybe the watchdog caught the NIC rebooting; wait
3791 * up to 100ms for it to finish. If it does not come
3792 * back, then give up
3795 cmd = pci_read_config(sc->dev, PCIR_COMMAND, 2);
3796 if (cmd == 0xffff) {
3797 device_printf(sc->dev, "NIC disappeared!\n");
3800 if ((cmd & PCIM_CMD_BUSMASTEREN) == 0) {
3801 /* print the reboot status */
3802 reboot = mxge_read_reboot(sc);
3803 device_printf(sc->dev, "NIC rebooted, status = 0x%x\n",
3805 running = sc->ifp->if_drv_flags & IFF_DRV_RUNNING;
3809 * quiesce NIC so that TX routines will not try to
3810 * xmit after restoration of BAR
3813 /* Mark the link as down */
3814 if (sc->link_state) {
3816 if_link_state_change(sc->ifp,
3819 #ifdef IFNET_BUF_RING
3820 num_tx_slices = sc->num_slices;
3822 /* grab all TX locks to ensure no tx */
3823 for (s = 0; s < num_tx_slices; s++) {
3825 mtx_lock(&ss->tx.mtx);
3829 /* restore PCI configuration space */
3830 dinfo = device_get_ivars(sc->dev);
3831 pci_cfg_restore(sc->dev, dinfo);
3833 /* and redo any changes we made to our config space */
3834 mxge_setup_cfg_space(sc);
3837 err = mxge_load_firmware(sc, 0);
3839 device_printf(sc->dev,
3840 "Unable to re-load f/w\n");
3844 err = mxge_open(sc);
3845 /* release all TX locks */
3846 for (s = 0; s < num_tx_slices; s++) {
3848 #ifdef IFNET_BUF_RING
3849 mxge_start_locked(ss);
3851 mtx_unlock(&ss->tx.mtx);
3854 sc->watchdog_resets++;
3856 device_printf(sc->dev,
3857 "NIC did not reboot, not resetting\n");
3861 device_printf(sc->dev, "watchdog reset failed\n");
3865 callout_reset(&sc->co_hdl, mxge_ticks, mxge_tick, sc);
3870 mxge_watchdog_task(void *arg, int pending)
3872 mxge_softc_t *sc = arg;
3875 mtx_lock(&sc->driver_mtx);
3876 mxge_watchdog_reset(sc);
3877 mtx_unlock(&sc->driver_mtx);
3881 mxge_warn_stuck(mxge_softc_t *sc, mxge_tx_ring_t *tx, int slice)
3883 tx = &sc->ss[slice].tx;
3884 device_printf(sc->dev, "slice %d struck? ring state:\n", slice);
3885 device_printf(sc->dev,
3886 "tx.req=%d tx.done=%d, tx.queue_active=%d\n",
3887 tx->req, tx->done, tx->queue_active);
3888 device_printf(sc->dev, "tx.activate=%d tx.deactivate=%d\n",
3889 tx->activate, tx->deactivate);
3890 device_printf(sc->dev, "pkt_done=%d fw=%d\n",
3892 be32toh(sc->ss->fw_stats->send_done_count));
3896 mxge_watchdog(mxge_softc_t *sc)
3899 uint32_t rx_pause = be32toh(sc->ss->fw_stats->dropped_pause);
3902 /* see if we have outstanding transmits, which
3903 have been pending for more than mxge_ticks */
3905 #ifdef IFNET_BUF_RING
3906 (i < sc->num_slices) && (err == 0);
3908 (i < 1) && (err == 0);
3912 if (tx->req != tx->done &&
3913 tx->watchdog_req != tx->watchdog_done &&
3914 tx->done == tx->watchdog_done) {
3915 /* check for pause blocking before resetting */
3916 if (tx->watchdog_rx_pause == rx_pause) {
3917 mxge_warn_stuck(sc, tx, i);
3918 taskqueue_enqueue(sc->tq, &sc->watchdog_task);
3922 device_printf(sc->dev, "Flow control blocking "
3923 "xmits, check link partner\n");
3926 tx->watchdog_req = tx->req;
3927 tx->watchdog_done = tx->done;
3928 tx->watchdog_rx_pause = rx_pause;
3931 if (sc->need_media_probe)
3932 mxge_media_probe(sc);
3937 mxge_update_stats(mxge_softc_t *sc)
3939 struct mxge_slice_state *ss;
3941 u_long ipackets = 0;
3942 u_long opackets = 0;
3943 #ifdef IFNET_BUF_RING
3951 for (slice = 0; slice < sc->num_slices; slice++) {
3952 ss = &sc->ss[slice];
3953 ipackets += ss->ipackets;
3954 opackets += ss->opackets;
3955 #ifdef IFNET_BUF_RING
3956 obytes += ss->obytes;
3957 omcasts += ss->omcasts;
3958 odrops += ss->tx.br->br_drops;
3960 oerrors += ss->oerrors;
3962 pkts = (ipackets - sc->ifp->if_ipackets);
3963 pkts += (opackets - sc->ifp->if_opackets);
3964 sc->ifp->if_ipackets = ipackets;
3965 sc->ifp->if_opackets = opackets;
3966 #ifdef IFNET_BUF_RING
3967 sc->ifp->if_obytes = obytes;
3968 sc->ifp->if_omcasts = omcasts;
3969 sc->ifp->if_snd.ifq_drops = odrops;
3971 sc->ifp->if_oerrors = oerrors;
3976 mxge_tick(void *arg)
3978 mxge_softc_t *sc = arg;
3985 running = sc->ifp->if_drv_flags & IFF_DRV_RUNNING;
3987 /* aggregate stats from different slices */
3988 pkts = mxge_update_stats(sc);
3989 if (!sc->watchdog_countdown) {
3990 err = mxge_watchdog(sc);
3991 sc->watchdog_countdown = 4;
3993 sc->watchdog_countdown--;
3996 /* ensure NIC did not suffer h/w fault while idle */
3997 cmd = pci_read_config(sc->dev, PCIR_COMMAND, 2);
3998 if ((cmd & PCIM_CMD_BUSMASTEREN) == 0) {
4000 taskqueue_enqueue(sc->tq, &sc->watchdog_task);
4003 /* look less often if NIC is idle */
4008 callout_reset(&sc->co_hdl, ticks, mxge_tick, sc);
4013 mxge_media_change(struct ifnet *ifp)
4019 mxge_change_mtu(mxge_softc_t *sc, int mtu)
4021 struct ifnet *ifp = sc->ifp;
4022 int real_mtu, old_mtu;
4026 real_mtu = mtu + ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN;
4027 if ((real_mtu > sc->max_mtu) || real_mtu < 60)
4029 mtx_lock(&sc->driver_mtx);
4030 old_mtu = ifp->if_mtu;
4032 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
4034 err = mxge_open(sc);
4036 ifp->if_mtu = old_mtu;
4038 (void) mxge_open(sc);
4041 mtx_unlock(&sc->driver_mtx);
4046 mxge_media_status(struct ifnet *ifp, struct ifmediareq *ifmr)
4048 mxge_softc_t *sc = ifp->if_softc;
4053 ifmr->ifm_status = IFM_AVALID;
4054 ifmr->ifm_active = IFM_ETHER | IFM_FDX;
4055 ifmr->ifm_status |= sc->link_state ? IFM_ACTIVE : 0;
4056 ifmr->ifm_active |= sc->current_media;
4060 mxge_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
4062 mxge_softc_t *sc = ifp->if_softc;
4063 struct ifreq *ifr = (struct ifreq *)data;
4070 err = ether_ioctl(ifp, command, data);
4074 err = mxge_change_mtu(sc, ifr->ifr_mtu);
4078 mtx_lock(&sc->driver_mtx);
4080 mtx_unlock(&sc->driver_mtx);
4083 if (ifp->if_flags & IFF_UP) {
4084 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) {
4085 err = mxge_open(sc);
4087 /* take care of promis can allmulti
4089 mxge_change_promisc(sc,
4090 ifp->if_flags & IFF_PROMISC);
4091 mxge_set_multicast_list(sc);
4094 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
4098 mtx_unlock(&sc->driver_mtx);
4103 mtx_lock(&sc->driver_mtx);
4104 mxge_set_multicast_list(sc);
4105 mtx_unlock(&sc->driver_mtx);
4109 mtx_lock(&sc->driver_mtx);
4110 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
4111 if (mask & IFCAP_TXCSUM) {
4112 if (IFCAP_TXCSUM & ifp->if_capenable) {
4113 ifp->if_capenable &= ~(IFCAP_TXCSUM|IFCAP_TSO4);
4114 ifp->if_hwassist &= ~(CSUM_TCP | CSUM_UDP
4117 ifp->if_capenable |= IFCAP_TXCSUM;
4118 ifp->if_hwassist |= (CSUM_TCP | CSUM_UDP);
4120 } else if (mask & IFCAP_RXCSUM) {
4121 if (IFCAP_RXCSUM & ifp->if_capenable) {
4122 ifp->if_capenable &= ~IFCAP_RXCSUM;
4125 ifp->if_capenable |= IFCAP_RXCSUM;
4129 if (mask & IFCAP_TSO4) {
4130 if (IFCAP_TSO4 & ifp->if_capenable) {
4131 ifp->if_capenable &= ~IFCAP_TSO4;
4132 ifp->if_hwassist &= ~CSUM_TSO;
4133 } else if (IFCAP_TXCSUM & ifp->if_capenable) {
4134 ifp->if_capenable |= IFCAP_TSO4;
4135 ifp->if_hwassist |= CSUM_TSO;
4137 printf("mxge requires tx checksum offload"
4138 " be enabled to use TSO\n");
4142 if (mask & IFCAP_LRO) {
4143 if (IFCAP_LRO & ifp->if_capenable)
4144 err = mxge_change_lro_locked(sc, 0);
4146 err = mxge_change_lro_locked(sc, mxge_lro_cnt);
4148 if (mask & IFCAP_VLAN_HWTAGGING)
4149 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
4150 if (mask & IFCAP_VLAN_HWTSO)
4151 ifp->if_capenable ^= IFCAP_VLAN_HWTSO;
4153 if (!(ifp->if_capabilities & IFCAP_VLAN_HWTSO) ||
4154 !(ifp->if_capenable & IFCAP_VLAN_HWTAGGING))
4155 ifp->if_capenable &= ~IFCAP_VLAN_HWTSO;
4157 mtx_unlock(&sc->driver_mtx);
4158 VLAN_CAPABILITIES(ifp);
4163 mtx_lock(&sc->driver_mtx);
4164 mxge_media_probe(sc);
4165 mtx_unlock(&sc->driver_mtx);
4166 err = ifmedia_ioctl(ifp, (struct ifreq *)data,
4167 &sc->media, command);
4178 mxge_fetch_tunables(mxge_softc_t *sc)
4181 TUNABLE_INT_FETCH("hw.mxge.max_slices", &mxge_max_slices);
4182 TUNABLE_INT_FETCH("hw.mxge.flow_control_enabled",
4183 &mxge_flow_control);
4184 TUNABLE_INT_FETCH("hw.mxge.intr_coal_delay",
4185 &mxge_intr_coal_delay);
4186 TUNABLE_INT_FETCH("hw.mxge.nvidia_ecrc_enable",
4187 &mxge_nvidia_ecrc_enable);
4188 TUNABLE_INT_FETCH("hw.mxge.force_firmware",
4189 &mxge_force_firmware);
4190 TUNABLE_INT_FETCH("hw.mxge.deassert_wait",
4191 &mxge_deassert_wait);
4192 TUNABLE_INT_FETCH("hw.mxge.verbose",
4194 TUNABLE_INT_FETCH("hw.mxge.ticks", &mxge_ticks);
4195 TUNABLE_INT_FETCH("hw.mxge.lro_cnt", &sc->lro_cnt);
4196 TUNABLE_INT_FETCH("hw.mxge.always_promisc", &mxge_always_promisc);
4197 TUNABLE_INT_FETCH("hw.mxge.rss_hash_type", &mxge_rss_hash_type);
4198 TUNABLE_INT_FETCH("hw.mxge.rss_hashtype", &mxge_rss_hash_type);
4199 TUNABLE_INT_FETCH("hw.mxge.initial_mtu", &mxge_initial_mtu);
4200 TUNABLE_INT_FETCH("hw.mxge.throttle", &mxge_throttle);
4201 if (sc->lro_cnt != 0)
4202 mxge_lro_cnt = sc->lro_cnt;
4206 if (mxge_intr_coal_delay < 0 || mxge_intr_coal_delay > 10*1000)
4207 mxge_intr_coal_delay = 30;
4208 if (mxge_ticks == 0)
4209 mxge_ticks = hz / 2;
4210 sc->pause = mxge_flow_control;
4211 if (mxge_rss_hash_type < MXGEFW_RSS_HASH_TYPE_IPV4
4212 || mxge_rss_hash_type > MXGEFW_RSS_HASH_TYPE_MAX) {
4213 mxge_rss_hash_type = MXGEFW_RSS_HASH_TYPE_SRC_DST_PORT;
4215 if (mxge_initial_mtu > ETHERMTU_JUMBO ||
4216 mxge_initial_mtu < ETHER_MIN_LEN)
4217 mxge_initial_mtu = ETHERMTU_JUMBO;
4219 if (mxge_throttle && mxge_throttle > MXGE_MAX_THROTTLE)
4220 mxge_throttle = MXGE_MAX_THROTTLE;
4221 if (mxge_throttle && mxge_throttle < MXGE_MIN_THROTTLE)
4222 mxge_throttle = MXGE_MIN_THROTTLE;
4223 sc->throttle = mxge_throttle;
4228 mxge_free_slices(mxge_softc_t *sc)
4230 struct mxge_slice_state *ss;
4237 for (i = 0; i < sc->num_slices; i++) {
4239 if (ss->fw_stats != NULL) {
4240 mxge_dma_free(&ss->fw_stats_dma);
4241 ss->fw_stats = NULL;
4242 #ifdef IFNET_BUF_RING
4243 if (ss->tx.br != NULL) {
4244 drbr_free(ss->tx.br, M_DEVBUF);
4248 mtx_destroy(&ss->tx.mtx);
4250 if (ss->rx_done.entry != NULL) {
4251 mxge_dma_free(&ss->rx_done.dma);
4252 ss->rx_done.entry = NULL;
4255 free(sc->ss, M_DEVBUF);
4260 mxge_alloc_slices(mxge_softc_t *sc)
4263 struct mxge_slice_state *ss;
4265 int err, i, max_intr_slots;
4267 err = mxge_send_cmd(sc, MXGEFW_CMD_GET_RX_RING_SIZE, &cmd);
4269 device_printf(sc->dev, "Cannot determine rx ring size\n");
4272 sc->rx_ring_size = cmd.data0;
4273 max_intr_slots = 2 * (sc->rx_ring_size / sizeof (mcp_dma_addr_t));
4275 bytes = sizeof (*sc->ss) * sc->num_slices;
4276 sc->ss = malloc(bytes, M_DEVBUF, M_NOWAIT | M_ZERO);
4279 for (i = 0; i < sc->num_slices; i++) {
4284 /* allocate per-slice rx interrupt queues */
4286 bytes = max_intr_slots * sizeof (*ss->rx_done.entry);
4287 err = mxge_dma_alloc(sc, &ss->rx_done.dma, bytes, 4096);
4290 ss->rx_done.entry = ss->rx_done.dma.addr;
4291 bzero(ss->rx_done.entry, bytes);
4294 * allocate the per-slice firmware stats; stats
4295 * (including tx) are used used only on the first
4298 #ifndef IFNET_BUF_RING
4303 bytes = sizeof (*ss->fw_stats);
4304 err = mxge_dma_alloc(sc, &ss->fw_stats_dma,
4305 sizeof (*ss->fw_stats), 64);
4308 ss->fw_stats = (mcp_irq_data_t *)ss->fw_stats_dma.addr;
4309 snprintf(ss->tx.mtx_name, sizeof(ss->tx.mtx_name),
4310 "%s:tx(%d)", device_get_nameunit(sc->dev), i);
4311 mtx_init(&ss->tx.mtx, ss->tx.mtx_name, NULL, MTX_DEF);
4312 #ifdef IFNET_BUF_RING
4313 ss->tx.br = buf_ring_alloc(2048, M_DEVBUF, M_WAITOK,
4321 mxge_free_slices(sc);
4326 mxge_slice_probe(mxge_softc_t *sc)
4330 int msix_cnt, status, max_intr_slots;
4334 * don't enable multiple slices if they are not enabled,
4335 * or if this is not an SMP system
4338 if (mxge_max_slices == 0 || mxge_max_slices == 1 || mp_ncpus < 2)
4341 /* see how many MSI-X interrupts are available */
4342 msix_cnt = pci_msix_count(sc->dev);
4346 /* now load the slice aware firmware see what it supports */
4347 old_fw = sc->fw_name;
4348 if (old_fw == mxge_fw_aligned)
4349 sc->fw_name = mxge_fw_rss_aligned;
4351 sc->fw_name = mxge_fw_rss_unaligned;
4352 status = mxge_load_firmware(sc, 0);
4354 device_printf(sc->dev, "Falling back to a single slice\n");
4358 /* try to send a reset command to the card to see if it
4360 memset(&cmd, 0, sizeof (cmd));
4361 status = mxge_send_cmd(sc, MXGEFW_CMD_RESET, &cmd);
4363 device_printf(sc->dev, "failed reset\n");
4367 /* get rx ring size */
4368 status = mxge_send_cmd(sc, MXGEFW_CMD_GET_RX_RING_SIZE, &cmd);
4370 device_printf(sc->dev, "Cannot determine rx ring size\n");
4373 max_intr_slots = 2 * (cmd.data0 / sizeof (mcp_dma_addr_t));
4375 /* tell it the size of the interrupt queues */
4376 cmd.data0 = max_intr_slots * sizeof (struct mcp_slot);
4377 status = mxge_send_cmd(sc, MXGEFW_CMD_SET_INTRQ_SIZE, &cmd);
4379 device_printf(sc->dev, "failed MXGEFW_CMD_SET_INTRQ_SIZE\n");
4383 /* ask the maximum number of slices it supports */
4384 status = mxge_send_cmd(sc, MXGEFW_CMD_GET_MAX_RSS_QUEUES, &cmd);
4386 device_printf(sc->dev,
4387 "failed MXGEFW_CMD_GET_MAX_RSS_QUEUES\n");
4390 sc->num_slices = cmd.data0;
4391 if (sc->num_slices > msix_cnt)
4392 sc->num_slices = msix_cnt;
4394 if (mxge_max_slices == -1) {
4395 /* cap to number of CPUs in system */
4396 if (sc->num_slices > mp_ncpus)
4397 sc->num_slices = mp_ncpus;
4399 if (sc->num_slices > mxge_max_slices)
4400 sc->num_slices = mxge_max_slices;
4402 /* make sure it is a power of two */
4403 while (sc->num_slices & (sc->num_slices - 1))
4407 device_printf(sc->dev, "using %d slices\n",
4413 sc->fw_name = old_fw;
4414 (void) mxge_load_firmware(sc, 0);
4418 mxge_add_msix_irqs(mxge_softc_t *sc)
4421 int count, err, i, rid;
4424 sc->msix_table_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY,
4427 if (sc->msix_table_res == NULL) {
4428 device_printf(sc->dev, "couldn't alloc MSIX table res\n");
4432 count = sc->num_slices;
4433 err = pci_alloc_msix(sc->dev, &count);
4435 device_printf(sc->dev, "pci_alloc_msix: failed, wanted %d"
4436 "err = %d \n", sc->num_slices, err);
4437 goto abort_with_msix_table;
4439 if (count < sc->num_slices) {
4440 device_printf(sc->dev, "pci_alloc_msix: need %d, got %d\n",
4441 count, sc->num_slices);
4442 device_printf(sc->dev,
4443 "Try setting hw.mxge.max_slices to %d\n",
4446 goto abort_with_msix;
4448 bytes = sizeof (*sc->msix_irq_res) * sc->num_slices;
4449 sc->msix_irq_res = malloc(bytes, M_DEVBUF, M_NOWAIT|M_ZERO);
4450 if (sc->msix_irq_res == NULL) {
4452 goto abort_with_msix;
4455 for (i = 0; i < sc->num_slices; i++) {
4457 sc->msix_irq_res[i] = bus_alloc_resource_any(sc->dev,
4460 if (sc->msix_irq_res[i] == NULL) {
4461 device_printf(sc->dev, "couldn't allocate IRQ res"
4462 " for message %d\n", i);
4464 goto abort_with_res;
4468 bytes = sizeof (*sc->msix_ih) * sc->num_slices;
4469 sc->msix_ih = malloc(bytes, M_DEVBUF, M_NOWAIT|M_ZERO);
4471 for (i = 0; i < sc->num_slices; i++) {
4472 err = bus_setup_intr(sc->dev, sc->msix_irq_res[i],
4473 INTR_TYPE_NET | INTR_MPSAFE,
4474 #if __FreeBSD_version > 700030
4477 mxge_intr, &sc->ss[i], &sc->msix_ih[i]);
4479 device_printf(sc->dev, "couldn't setup intr for "
4481 goto abort_with_intr;
4483 bus_describe_intr(sc->dev, sc->msix_irq_res[i],
4484 sc->msix_ih[i], "s%d", i);
4488 device_printf(sc->dev, "using %d msix IRQs:",
4490 for (i = 0; i < sc->num_slices; i++)
4491 printf(" %ld", rman_get_start(sc->msix_irq_res[i]));
4497 for (i = 0; i < sc->num_slices; i++) {
4498 if (sc->msix_ih[i] != NULL) {
4499 bus_teardown_intr(sc->dev, sc->msix_irq_res[i],
4501 sc->msix_ih[i] = NULL;
4504 free(sc->msix_ih, M_DEVBUF);
4508 for (i = 0; i < sc->num_slices; i++) {
4510 if (sc->msix_irq_res[i] != NULL)
4511 bus_release_resource(sc->dev, SYS_RES_IRQ, rid,
4512 sc->msix_irq_res[i]);
4513 sc->msix_irq_res[i] = NULL;
4515 free(sc->msix_irq_res, M_DEVBUF);
4519 pci_release_msi(sc->dev);
4521 abort_with_msix_table:
4522 bus_release_resource(sc->dev, SYS_RES_MEMORY, PCIR_BAR(2),
4523 sc->msix_table_res);
4529 mxge_add_single_irq(mxge_softc_t *sc)
4531 int count, err, rid;
4533 count = pci_msi_count(sc->dev);
4534 if (count == 1 && pci_alloc_msi(sc->dev, &count) == 0) {
4540 sc->irq_res = bus_alloc_resource(sc->dev, SYS_RES_IRQ, &rid, 0, ~0,
4541 1, RF_SHAREABLE | RF_ACTIVE);
4542 if (sc->irq_res == NULL) {
4543 device_printf(sc->dev, "could not alloc interrupt\n");
4547 device_printf(sc->dev, "using %s irq %ld\n",
4548 sc->legacy_irq ? "INTx" : "MSI",
4549 rman_get_start(sc->irq_res));
4550 err = bus_setup_intr(sc->dev, sc->irq_res,
4551 INTR_TYPE_NET | INTR_MPSAFE,
4552 #if __FreeBSD_version > 700030
4555 mxge_intr, &sc->ss[0], &sc->ih);
4557 bus_release_resource(sc->dev, SYS_RES_IRQ,
4558 sc->legacy_irq ? 0 : 1, sc->irq_res);
4559 if (!sc->legacy_irq)
4560 pci_release_msi(sc->dev);
4566 mxge_rem_msix_irqs(mxge_softc_t *sc)
4570 for (i = 0; i < sc->num_slices; i++) {
4571 if (sc->msix_ih[i] != NULL) {
4572 bus_teardown_intr(sc->dev, sc->msix_irq_res[i],
4574 sc->msix_ih[i] = NULL;
4577 free(sc->msix_ih, M_DEVBUF);
4579 for (i = 0; i < sc->num_slices; i++) {
4581 if (sc->msix_irq_res[i] != NULL)
4582 bus_release_resource(sc->dev, SYS_RES_IRQ, rid,
4583 sc->msix_irq_res[i]);
4584 sc->msix_irq_res[i] = NULL;
4586 free(sc->msix_irq_res, M_DEVBUF);
4588 bus_release_resource(sc->dev, SYS_RES_MEMORY, PCIR_BAR(2),
4589 sc->msix_table_res);
4591 pci_release_msi(sc->dev);
4596 mxge_rem_single_irq(mxge_softc_t *sc)
4598 bus_teardown_intr(sc->dev, sc->irq_res, sc->ih);
4599 bus_release_resource(sc->dev, SYS_RES_IRQ,
4600 sc->legacy_irq ? 0 : 1, sc->irq_res);
4601 if (!sc->legacy_irq)
4602 pci_release_msi(sc->dev);
4606 mxge_rem_irq(mxge_softc_t *sc)
4608 if (sc->num_slices > 1)
4609 mxge_rem_msix_irqs(sc);
4611 mxge_rem_single_irq(sc);
4615 mxge_add_irq(mxge_softc_t *sc)
4619 if (sc->num_slices > 1)
4620 err = mxge_add_msix_irqs(sc);
4622 err = mxge_add_single_irq(sc);
4624 if (0 && err == 0 && sc->num_slices > 1) {
4625 mxge_rem_msix_irqs(sc);
4626 err = mxge_add_msix_irqs(sc);
4633 mxge_attach(device_t dev)
4635 mxge_softc_t *sc = device_get_softc(dev);
4640 mxge_fetch_tunables(sc);
4642 TASK_INIT(&sc->watchdog_task, 1, mxge_watchdog_task, sc);
4643 sc->tq = taskqueue_create_fast("mxge_taskq", M_WAITOK,
4644 taskqueue_thread_enqueue,
4646 if (sc->tq == NULL) {
4648 goto abort_with_nothing;
4651 err = bus_dma_tag_create(NULL, /* parent */
4654 BUS_SPACE_MAXADDR, /* low */
4655 BUS_SPACE_MAXADDR, /* high */
4656 NULL, NULL, /* filter */
4657 65536 + 256, /* maxsize */
4658 MXGE_MAX_SEND_DESC, /* num segs */
4659 65536, /* maxsegsize */
4661 NULL, NULL, /* lock */
4662 &sc->parent_dmat); /* tag */
4665 device_printf(sc->dev, "Err %d allocating parent dmat\n",
4670 ifp = sc->ifp = if_alloc(IFT_ETHER);
4672 device_printf(dev, "can not if_alloc()\n");
4674 goto abort_with_parent_dmat;
4676 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
4678 snprintf(sc->cmd_mtx_name, sizeof(sc->cmd_mtx_name), "%s:cmd",
4679 device_get_nameunit(dev));
4680 mtx_init(&sc->cmd_mtx, sc->cmd_mtx_name, NULL, MTX_DEF);
4681 snprintf(sc->driver_mtx_name, sizeof(sc->driver_mtx_name),
4682 "%s:drv", device_get_nameunit(dev));
4683 mtx_init(&sc->driver_mtx, sc->driver_mtx_name,
4684 MTX_NETWORK_LOCK, MTX_DEF);
4686 callout_init_mtx(&sc->co_hdl, &sc->driver_mtx, 0);
4688 mxge_setup_cfg_space(sc);
4690 /* Map the board into the kernel */
4692 sc->mem_res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, 0,
4694 if (sc->mem_res == NULL) {
4695 device_printf(dev, "could not map memory\n");
4697 goto abort_with_lock;
4699 sc->sram = rman_get_virtual(sc->mem_res);
4700 sc->sram_size = 2*1024*1024 - (2*(48*1024)+(32*1024)) - 0x100;
4701 if (sc->sram_size > rman_get_size(sc->mem_res)) {
4702 device_printf(dev, "impossible memory region size %ld\n",
4703 rman_get_size(sc->mem_res));
4705 goto abort_with_mem_res;
4708 /* make NULL terminated copy of the EEPROM strings section of
4710 bzero(sc->eeprom_strings, MXGE_EEPROM_STRINGS_SIZE);
4711 bus_space_read_region_1(rman_get_bustag(sc->mem_res),
4712 rman_get_bushandle(sc->mem_res),
4713 sc->sram_size - MXGE_EEPROM_STRINGS_SIZE,
4715 MXGE_EEPROM_STRINGS_SIZE - 2);
4716 err = mxge_parse_strings(sc);
4718 goto abort_with_mem_res;
4720 /* Enable write combining for efficient use of PCIe bus */
4723 /* Allocate the out of band dma memory */
4724 err = mxge_dma_alloc(sc, &sc->cmd_dma,
4725 sizeof (mxge_cmd_t), 64);
4727 goto abort_with_mem_res;
4728 sc->cmd = (mcp_cmd_response_t *) sc->cmd_dma.addr;
4729 err = mxge_dma_alloc(sc, &sc->zeropad_dma, 64, 64);
4731 goto abort_with_cmd_dma;
4733 err = mxge_dma_alloc(sc, &sc->dmabench_dma, 4096, 4096);
4735 goto abort_with_zeropad_dma;
4737 /* select & load the firmware */
4738 err = mxge_select_firmware(sc);
4740 goto abort_with_dmabench;
4741 sc->intr_coal_delay = mxge_intr_coal_delay;
4743 mxge_slice_probe(sc);
4744 err = mxge_alloc_slices(sc);
4746 goto abort_with_dmabench;
4748 err = mxge_reset(sc, 0);
4750 goto abort_with_slices;
4752 err = mxge_alloc_rings(sc);
4754 device_printf(sc->dev, "failed to allocate rings\n");
4755 goto abort_with_slices;
4758 err = mxge_add_irq(sc);
4760 device_printf(sc->dev, "failed to add irq\n");
4761 goto abort_with_rings;
4764 ifp->if_baudrate = IF_Gbps(10UL);
4765 ifp->if_capabilities = IFCAP_RXCSUM | IFCAP_TXCSUM | IFCAP_TSO4 |
4768 ifp->if_capabilities |= IFCAP_LRO;
4771 #ifdef MXGE_NEW_VLAN_API
4772 ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_HWCSUM;
4774 /* Only FW 1.4.32 and newer can do TSO over vlans */
4775 if (sc->fw_ver_major == 1 && sc->fw_ver_minor == 4 &&
4776 sc->fw_ver_tiny >= 32)
4777 ifp->if_capabilities |= IFCAP_VLAN_HWTSO;
4780 sc->max_mtu = mxge_max_mtu(sc);
4781 if (sc->max_mtu >= 9000)
4782 ifp->if_capabilities |= IFCAP_JUMBO_MTU;
4784 device_printf(dev, "MTU limited to %d. Install "
4785 "latest firmware for 9000 byte jumbo support\n",
4786 sc->max_mtu - ETHER_HDR_LEN);
4787 ifp->if_hwassist = CSUM_TCP | CSUM_UDP | CSUM_TSO;
4788 ifp->if_capenable = ifp->if_capabilities;
4789 if (sc->lro_cnt == 0)
4790 ifp->if_capenable &= ~IFCAP_LRO;
4792 ifp->if_init = mxge_init;
4794 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
4795 ifp->if_ioctl = mxge_ioctl;
4796 ifp->if_start = mxge_start;
4797 /* Initialise the ifmedia structure */
4798 ifmedia_init(&sc->media, 0, mxge_media_change,
4800 mxge_media_init(sc);
4801 mxge_media_probe(sc);
4803 ether_ifattach(ifp, sc->mac_addr);
4804 /* ether_ifattach sets mtu to ETHERMTU */
4805 if (mxge_initial_mtu != ETHERMTU)
4806 mxge_change_mtu(sc, mxge_initial_mtu);
4808 mxge_add_sysctls(sc);
4809 #ifdef IFNET_BUF_RING
4810 ifp->if_transmit = mxge_transmit;
4811 ifp->if_qflush = mxge_qflush;
4813 taskqueue_start_threads(&sc->tq, 1, PI_NET, "%s taskq",
4814 device_get_nameunit(sc->dev));
4815 callout_reset(&sc->co_hdl, mxge_ticks, mxge_tick, sc);
4819 mxge_free_rings(sc);
4821 mxge_free_slices(sc);
4822 abort_with_dmabench:
4823 mxge_dma_free(&sc->dmabench_dma);
4824 abort_with_zeropad_dma:
4825 mxge_dma_free(&sc->zeropad_dma);
4827 mxge_dma_free(&sc->cmd_dma);
4829 bus_release_resource(dev, SYS_RES_MEMORY, PCIR_BARS, sc->mem_res);
4831 pci_disable_busmaster(dev);
4832 mtx_destroy(&sc->cmd_mtx);
4833 mtx_destroy(&sc->driver_mtx);
4835 abort_with_parent_dmat:
4836 bus_dma_tag_destroy(sc->parent_dmat);
4838 if (sc->tq != NULL) {
4839 taskqueue_drain(sc->tq, &sc->watchdog_task);
4840 taskqueue_free(sc->tq);
4848 mxge_detach(device_t dev)
4850 mxge_softc_t *sc = device_get_softc(dev);
4852 if (mxge_vlans_active(sc)) {
4853 device_printf(sc->dev,
4854 "Detach vlans before removing module\n");
4857 mtx_lock(&sc->driver_mtx);
4859 if (sc->ifp->if_drv_flags & IFF_DRV_RUNNING)
4861 mtx_unlock(&sc->driver_mtx);
4862 ether_ifdetach(sc->ifp);
4863 if (sc->tq != NULL) {
4864 taskqueue_drain(sc->tq, &sc->watchdog_task);
4865 taskqueue_free(sc->tq);
4868 callout_drain(&sc->co_hdl);
4869 ifmedia_removeall(&sc->media);
4870 mxge_dummy_rdma(sc, 0);
4871 mxge_rem_sysctls(sc);
4873 mxge_free_rings(sc);
4874 mxge_free_slices(sc);
4875 mxge_dma_free(&sc->dmabench_dma);
4876 mxge_dma_free(&sc->zeropad_dma);
4877 mxge_dma_free(&sc->cmd_dma);
4878 bus_release_resource(dev, SYS_RES_MEMORY, PCIR_BARS, sc->mem_res);
4879 pci_disable_busmaster(dev);
4880 mtx_destroy(&sc->cmd_mtx);
4881 mtx_destroy(&sc->driver_mtx);
4883 bus_dma_tag_destroy(sc->parent_dmat);
4888 mxge_shutdown(device_t dev)
4894 This file uses Myri10GE driver indentation.
4897 c-file-style:"linux"