2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org>
3 * Copyright (c) 2000, Michael Smith <msmith@freebsd.org>
4 * Copyright (c) 2000, BSDi
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice unmodified, this list of conditions, and the following
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 #include <sys/cdefs.h>
30 __FBSDID("$FreeBSD$");
34 #include <sys/param.h>
35 #include <sys/systm.h>
36 #include <sys/malloc.h>
37 #include <sys/module.h>
38 #include <sys/linker.h>
39 #include <sys/fcntl.h>
41 #include <sys/kernel.h>
42 #include <sys/queue.h>
43 #include <sys/sysctl.h>
44 #include <sys/endian.h>
48 #include <vm/vm_extern.h>
51 #include <machine/bus.h>
53 #include <machine/resource.h>
54 #include <machine/stdarg.h>
56 #if defined(__i386__) || defined(__amd64__) || defined(__powerpc__)
57 #include <machine/intr_machdep.h>
60 #include <sys/pciio.h>
61 #include <dev/pci/pcireg.h>
62 #include <dev/pci/pcivar.h>
63 #include <dev/pci/pci_private.h>
65 #include <dev/usb/controller/ehcireg.h>
66 #include <dev/usb/controller/ohcireg.h>
67 #include <dev/usb/controller/uhcireg.h>
73 #include <contrib/dev/acpica/include/acpi.h>
76 #define ACPI_PWR_FOR_SLEEP(x, y, z)
79 static pci_addr_t pci_mapbase(uint64_t mapreg);
80 static const char *pci_maptype(uint64_t mapreg);
81 static int pci_mapsize(uint64_t testval);
82 static int pci_maprange(uint64_t mapreg);
83 static void pci_fixancient(pcicfgregs *cfg);
84 static int pci_printf(pcicfgregs *cfg, const char *fmt, ...);
86 static int pci_porten(device_t dev);
87 static int pci_memen(device_t dev);
88 static void pci_assign_interrupt(device_t bus, device_t dev,
90 static int pci_add_map(device_t bus, device_t dev, int reg,
91 struct resource_list *rl, int force, int prefetch);
92 static int pci_probe(device_t dev);
93 static int pci_attach(device_t dev);
94 static void pci_load_vendor_data(void);
95 static int pci_describe_parse_line(char **ptr, int *vendor,
96 int *device, char **desc);
97 static char *pci_describe_device(device_t dev);
98 static int pci_modevent(module_t mod, int what, void *arg);
99 static void pci_hdrtypedata(device_t pcib, int b, int s, int f,
101 static void pci_read_extcap(device_t pcib, pcicfgregs *cfg);
102 static int pci_read_vpd_reg(device_t pcib, pcicfgregs *cfg,
103 int reg, uint32_t *data);
105 static int pci_write_vpd_reg(device_t pcib, pcicfgregs *cfg,
106 int reg, uint32_t data);
108 static void pci_read_vpd(device_t pcib, pcicfgregs *cfg);
109 static void pci_disable_msi(device_t dev);
110 static void pci_enable_msi(device_t dev, uint64_t address,
112 static void pci_enable_msix(device_t dev, u_int index,
113 uint64_t address, uint32_t data);
114 static void pci_mask_msix(device_t dev, u_int index);
115 static void pci_unmask_msix(device_t dev, u_int index);
116 static int pci_msi_blacklisted(void);
117 static void pci_resume_msi(device_t dev);
118 static void pci_resume_msix(device_t dev);
120 static device_method_t pci_methods[] = {
121 /* Device interface */
122 DEVMETHOD(device_probe, pci_probe),
123 DEVMETHOD(device_attach, pci_attach),
124 DEVMETHOD(device_detach, bus_generic_detach),
125 DEVMETHOD(device_shutdown, bus_generic_shutdown),
126 DEVMETHOD(device_suspend, pci_suspend),
127 DEVMETHOD(device_resume, pci_resume),
130 DEVMETHOD(bus_print_child, pci_print_child),
131 DEVMETHOD(bus_probe_nomatch, pci_probe_nomatch),
132 DEVMETHOD(bus_read_ivar, pci_read_ivar),
133 DEVMETHOD(bus_write_ivar, pci_write_ivar),
134 DEVMETHOD(bus_driver_added, pci_driver_added),
135 DEVMETHOD(bus_setup_intr, pci_setup_intr),
136 DEVMETHOD(bus_teardown_intr, pci_teardown_intr),
138 DEVMETHOD(bus_get_resource_list,pci_get_resource_list),
139 DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource),
140 DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource),
141 DEVMETHOD(bus_delete_resource, pci_delete_resource),
142 DEVMETHOD(bus_alloc_resource, pci_alloc_resource),
143 DEVMETHOD(bus_release_resource, bus_generic_rl_release_resource),
144 DEVMETHOD(bus_activate_resource, pci_activate_resource),
145 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
146 DEVMETHOD(bus_child_pnpinfo_str, pci_child_pnpinfo_str_method),
147 DEVMETHOD(bus_child_location_str, pci_child_location_str_method),
150 DEVMETHOD(pci_read_config, pci_read_config_method),
151 DEVMETHOD(pci_write_config, pci_write_config_method),
152 DEVMETHOD(pci_enable_busmaster, pci_enable_busmaster_method),
153 DEVMETHOD(pci_disable_busmaster, pci_disable_busmaster_method),
154 DEVMETHOD(pci_enable_io, pci_enable_io_method),
155 DEVMETHOD(pci_disable_io, pci_disable_io_method),
156 DEVMETHOD(pci_get_vpd_ident, pci_get_vpd_ident_method),
157 DEVMETHOD(pci_get_vpd_readonly, pci_get_vpd_readonly_method),
158 DEVMETHOD(pci_get_powerstate, pci_get_powerstate_method),
159 DEVMETHOD(pci_set_powerstate, pci_set_powerstate_method),
160 DEVMETHOD(pci_assign_interrupt, pci_assign_interrupt_method),
161 DEVMETHOD(pci_find_extcap, pci_find_extcap_method),
162 DEVMETHOD(pci_alloc_msi, pci_alloc_msi_method),
163 DEVMETHOD(pci_alloc_msix, pci_alloc_msix_method),
164 DEVMETHOD(pci_remap_msix, pci_remap_msix_method),
165 DEVMETHOD(pci_release_msi, pci_release_msi_method),
166 DEVMETHOD(pci_msi_count, pci_msi_count_method),
167 DEVMETHOD(pci_msix_count, pci_msix_count_method),
172 DEFINE_CLASS_0(pci, pci_driver, pci_methods, 0);
174 static devclass_t pci_devclass;
175 DRIVER_MODULE(pci, pcib, pci_driver, pci_devclass, pci_modevent, 0);
176 MODULE_VERSION(pci, 1);
178 static char *pci_vendordata;
179 static size_t pci_vendordata_size;
183 uint32_t devid; /* Vendor/device of the card */
185 #define PCI_QUIRK_MAP_REG 1 /* PCI map register in weird place */
186 #define PCI_QUIRK_DISABLE_MSI 2 /* MSI/MSI-X doesn't work */
191 struct pci_quirk pci_quirks[] = {
192 /* The Intel 82371AB and 82443MX has a map register at offset 0x90. */
193 { 0x71138086, PCI_QUIRK_MAP_REG, 0x90, 0 },
194 { 0x719b8086, PCI_QUIRK_MAP_REG, 0x90, 0 },
195 /* As does the Serverworks OSB4 (the SMBus mapping register) */
196 { 0x02001166, PCI_QUIRK_MAP_REG, 0x90, 0 },
199 * MSI doesn't work with the ServerWorks CNB20-HE Host Bridge
200 * or the CMIC-SL (AKA ServerWorks GC_LE).
202 { 0x00141166, PCI_QUIRK_DISABLE_MSI, 0, 0 },
203 { 0x00171166, PCI_QUIRK_DISABLE_MSI, 0, 0 },
206 * MSI doesn't work on earlier Intel chipsets including
207 * E7500, E7501, E7505, 845, 865, 875/E7210, and 855.
209 { 0x25408086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
210 { 0x254c8086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
211 { 0x25508086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
212 { 0x25608086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
213 { 0x25708086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
214 { 0x25788086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
215 { 0x35808086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
218 * MSI doesn't work with devices behind the AMD 8131 HT-PCIX
221 { 0x74501022, PCI_QUIRK_DISABLE_MSI, 0, 0 },
226 /* map register information */
227 #define PCI_MAPMEM 0x01 /* memory map */
228 #define PCI_MAPMEMP 0x02 /* prefetchable memory map */
229 #define PCI_MAPPORT 0x04 /* port map */
231 struct devlist pci_devq;
232 uint32_t pci_generation;
233 uint32_t pci_numdevs = 0;
234 static int pcie_chipset, pcix_chipset;
237 SYSCTL_NODE(_hw, OID_AUTO, pci, CTLFLAG_RD, 0, "PCI bus tuning parameters");
239 static int pci_enable_io_modes = 1;
240 TUNABLE_INT("hw.pci.enable_io_modes", &pci_enable_io_modes);
241 SYSCTL_INT(_hw_pci, OID_AUTO, enable_io_modes, CTLFLAG_RW,
242 &pci_enable_io_modes, 1,
243 "Enable I/O and memory bits in the config register. Some BIOSes do not\n\
244 enable these bits correctly. We'd like to do this all the time, but there\n\
245 are some peripherals that this causes problems with.");
247 static int pci_do_power_nodriver = 0;
248 TUNABLE_INT("hw.pci.do_power_nodriver", &pci_do_power_nodriver);
249 SYSCTL_INT(_hw_pci, OID_AUTO, do_power_nodriver, CTLFLAG_RW,
250 &pci_do_power_nodriver, 0,
251 "Place a function into D3 state when no driver attaches to it. 0 means\n\
252 disable. 1 means conservatively place devices into D3 state. 2 means\n\
253 agressively place devices into D3 state. 3 means put absolutely everything\n\
256 static int pci_do_power_resume = 1;
257 TUNABLE_INT("hw.pci.do_power_resume", &pci_do_power_resume);
258 SYSCTL_INT(_hw_pci, OID_AUTO, do_power_resume, CTLFLAG_RW,
259 &pci_do_power_resume, 1,
260 "Transition from D3 -> D0 on resume.");
262 static int pci_do_msi = 1;
263 TUNABLE_INT("hw.pci.enable_msi", &pci_do_msi);
264 SYSCTL_INT(_hw_pci, OID_AUTO, enable_msi, CTLFLAG_RW, &pci_do_msi, 1,
265 "Enable support for MSI interrupts");
267 static int pci_do_msix = 1;
268 TUNABLE_INT("hw.pci.enable_msix", &pci_do_msix);
269 SYSCTL_INT(_hw_pci, OID_AUTO, enable_msix, CTLFLAG_RW, &pci_do_msix, 1,
270 "Enable support for MSI-X interrupts");
272 static int pci_honor_msi_blacklist = 1;
273 TUNABLE_INT("hw.pci.honor_msi_blacklist", &pci_honor_msi_blacklist);
274 SYSCTL_INT(_hw_pci, OID_AUTO, honor_msi_blacklist, CTLFLAG_RD,
275 &pci_honor_msi_blacklist, 1, "Honor chipset blacklist for MSI");
277 #if defined(__i386__) || defined(__amd64__)
278 static int pci_usb_takeover = 1;
280 static int pci_usb_takeover = 0;
282 TUNABLE_INT("hw.pci.usb_early_takeover", &pci_usb_takeover);
283 SYSCTL_INT(_hw_pci, OID_AUTO, usb_early_takeover, CTLFLAG_RD | CTLFLAG_TUN,
284 &pci_usb_takeover, 1, "Enable early takeover of USB controllers.\n\
285 Disable this if you depend on BIOS emulation of USB devices, that is\n\
286 you use USB devices (like keyboard or mouse) but do not load USB drivers");
288 /* Find a device_t by bus/slot/function in domain 0 */
291 pci_find_bsf(uint8_t bus, uint8_t slot, uint8_t func)
294 return (pci_find_dbsf(0, bus, slot, func));
297 /* Find a device_t by domain/bus/slot/function */
300 pci_find_dbsf(uint32_t domain, uint8_t bus, uint8_t slot, uint8_t func)
302 struct pci_devinfo *dinfo;
304 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) {
305 if ((dinfo->cfg.domain == domain) &&
306 (dinfo->cfg.bus == bus) &&
307 (dinfo->cfg.slot == slot) &&
308 (dinfo->cfg.func == func)) {
309 return (dinfo->cfg.dev);
316 /* Find a device_t by vendor/device ID */
319 pci_find_device(uint16_t vendor, uint16_t device)
321 struct pci_devinfo *dinfo;
323 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) {
324 if ((dinfo->cfg.vendor == vendor) &&
325 (dinfo->cfg.device == device)) {
326 return (dinfo->cfg.dev);
334 pci_printf(pcicfgregs *cfg, const char *fmt, ...)
339 retval = printf("pci%d:%d:%d:%d: ", cfg->domain, cfg->bus, cfg->slot,
342 retval += vprintf(fmt, ap);
347 /* return base address of memory or port map */
350 pci_mapbase(uint64_t mapreg)
353 if (PCI_BAR_MEM(mapreg))
354 return (mapreg & PCIM_BAR_MEM_BASE);
356 return (mapreg & PCIM_BAR_IO_BASE);
359 /* return map type of memory or port map */
362 pci_maptype(uint64_t mapreg)
365 if (PCI_BAR_IO(mapreg))
367 if (mapreg & PCIM_BAR_MEM_PREFETCH)
368 return ("Prefetchable Memory");
372 /* return log2 of map size decoded for memory or port map */
375 pci_mapsize(uint64_t testval)
379 testval = pci_mapbase(testval);
382 while ((testval & 1) == 0)
391 /* return log2 of address range supported by map register */
394 pci_maprange(uint64_t mapreg)
398 if (PCI_BAR_IO(mapreg))
401 switch (mapreg & PCIM_BAR_MEM_TYPE) {
402 case PCIM_BAR_MEM_32:
405 case PCIM_BAR_MEM_1MB:
408 case PCIM_BAR_MEM_64:
415 /* adjust some values from PCI 1.0 devices to match 2.0 standards ... */
418 pci_fixancient(pcicfgregs *cfg)
420 if (cfg->hdrtype != 0)
423 /* PCI to PCI bridges use header type 1 */
424 if (cfg->baseclass == PCIC_BRIDGE && cfg->subclass == PCIS_BRIDGE_PCI)
428 /* extract header type specific config data */
431 pci_hdrtypedata(device_t pcib, int b, int s, int f, pcicfgregs *cfg)
433 #define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w)
434 switch (cfg->hdrtype) {
436 cfg->subvendor = REG(PCIR_SUBVEND_0, 2);
437 cfg->subdevice = REG(PCIR_SUBDEV_0, 2);
438 cfg->nummaps = PCI_MAXMAPS_0;
441 cfg->nummaps = PCI_MAXMAPS_1;
444 cfg->subvendor = REG(PCIR_SUBVEND_2, 2);
445 cfg->subdevice = REG(PCIR_SUBDEV_2, 2);
446 cfg->nummaps = PCI_MAXMAPS_2;
452 /* read configuration header into pcicfgregs structure */
454 pci_read_device(device_t pcib, int d, int b, int s, int f, size_t size)
456 #define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w)
457 pcicfgregs *cfg = NULL;
458 struct pci_devinfo *devlist_entry;
459 struct devlist *devlist_head;
461 devlist_head = &pci_devq;
463 devlist_entry = NULL;
465 if (REG(PCIR_DEVVENDOR, 4) != 0xfffffffful) {
466 devlist_entry = malloc(size, M_DEVBUF, M_WAITOK | M_ZERO);
467 if (devlist_entry == NULL)
470 cfg = &devlist_entry->cfg;
476 cfg->vendor = REG(PCIR_VENDOR, 2);
477 cfg->device = REG(PCIR_DEVICE, 2);
478 cfg->cmdreg = REG(PCIR_COMMAND, 2);
479 cfg->statreg = REG(PCIR_STATUS, 2);
480 cfg->baseclass = REG(PCIR_CLASS, 1);
481 cfg->subclass = REG(PCIR_SUBCLASS, 1);
482 cfg->progif = REG(PCIR_PROGIF, 1);
483 cfg->revid = REG(PCIR_REVID, 1);
484 cfg->hdrtype = REG(PCIR_HDRTYPE, 1);
485 cfg->cachelnsz = REG(PCIR_CACHELNSZ, 1);
486 cfg->lattimer = REG(PCIR_LATTIMER, 1);
487 cfg->intpin = REG(PCIR_INTPIN, 1);
488 cfg->intline = REG(PCIR_INTLINE, 1);
490 cfg->mingnt = REG(PCIR_MINGNT, 1);
491 cfg->maxlat = REG(PCIR_MAXLAT, 1);
493 cfg->mfdev = (cfg->hdrtype & PCIM_MFDEV) != 0;
494 cfg->hdrtype &= ~PCIM_MFDEV;
497 pci_hdrtypedata(pcib, b, s, f, cfg);
499 if (REG(PCIR_STATUS, 2) & PCIM_STATUS_CAPPRESENT)
500 pci_read_extcap(pcib, cfg);
502 STAILQ_INSERT_TAIL(devlist_head, devlist_entry, pci_links);
504 devlist_entry->conf.pc_sel.pc_domain = cfg->domain;
505 devlist_entry->conf.pc_sel.pc_bus = cfg->bus;
506 devlist_entry->conf.pc_sel.pc_dev = cfg->slot;
507 devlist_entry->conf.pc_sel.pc_func = cfg->func;
508 devlist_entry->conf.pc_hdr = cfg->hdrtype;
510 devlist_entry->conf.pc_subvendor = cfg->subvendor;
511 devlist_entry->conf.pc_subdevice = cfg->subdevice;
512 devlist_entry->conf.pc_vendor = cfg->vendor;
513 devlist_entry->conf.pc_device = cfg->device;
515 devlist_entry->conf.pc_class = cfg->baseclass;
516 devlist_entry->conf.pc_subclass = cfg->subclass;
517 devlist_entry->conf.pc_progif = cfg->progif;
518 devlist_entry->conf.pc_revid = cfg->revid;
523 return (devlist_entry);
528 pci_read_extcap(device_t pcib, pcicfgregs *cfg)
530 #define REG(n, w) PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w)
531 #define WREG(n, v, w) PCIB_WRITE_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, v, w)
532 #if defined(__i386__) || defined(__amd64__) || defined(__powerpc__)
536 int ptr, nextptr, ptrptr;
538 switch (cfg->hdrtype & PCIM_HDRTYPE) {
541 ptrptr = PCIR_CAP_PTR;
544 ptrptr = PCIR_CAP_PTR_2; /* cardbus capabilities ptr */
547 return; /* no extended capabilities support */
549 nextptr = REG(ptrptr, 1); /* sanity check? */
552 * Read capability entries.
554 while (nextptr != 0) {
557 printf("illegal PCI extended capability offset %d\n",
561 /* Find the next entry */
563 nextptr = REG(ptr + PCICAP_NEXTPTR, 1);
565 /* Process this entry */
566 switch (REG(ptr + PCICAP_ID, 1)) {
567 case PCIY_PMG: /* PCI power management */
568 if (cfg->pp.pp_cap == 0) {
569 cfg->pp.pp_cap = REG(ptr + PCIR_POWER_CAP, 2);
570 cfg->pp.pp_status = ptr + PCIR_POWER_STATUS;
571 cfg->pp.pp_pmcsr = ptr + PCIR_POWER_PMCSR;
572 if ((nextptr - ptr) > PCIR_POWER_DATA)
573 cfg->pp.pp_data = ptr + PCIR_POWER_DATA;
576 #if defined(__i386__) || defined(__amd64__) || defined(__powerpc__)
577 case PCIY_HT: /* HyperTransport */
578 /* Determine HT-specific capability type. */
579 val = REG(ptr + PCIR_HT_COMMAND, 2);
580 switch (val & PCIM_HTCMD_CAP_MASK) {
581 case PCIM_HTCAP_MSI_MAPPING:
582 if (!(val & PCIM_HTCMD_MSI_FIXED)) {
583 /* Sanity check the mapping window. */
584 addr = REG(ptr + PCIR_HTMSI_ADDRESS_HI,
587 addr |= REG(ptr + PCIR_HTMSI_ADDRESS_LO,
589 if (addr != MSI_INTEL_ADDR_BASE)
591 "HT Bridge at pci%d:%d:%d:%d has non-default MSI window 0x%llx\n",
592 cfg->domain, cfg->bus,
593 cfg->slot, cfg->func,
596 addr = MSI_INTEL_ADDR_BASE;
598 cfg->ht.ht_msimap = ptr;
599 cfg->ht.ht_msictrl = val;
600 cfg->ht.ht_msiaddr = addr;
605 case PCIY_MSI: /* PCI MSI */
606 cfg->msi.msi_location = ptr;
607 cfg->msi.msi_ctrl = REG(ptr + PCIR_MSI_CTRL, 2);
608 cfg->msi.msi_msgnum = 1 << ((cfg->msi.msi_ctrl &
609 PCIM_MSICTRL_MMC_MASK)>>1);
611 case PCIY_MSIX: /* PCI MSI-X */
612 cfg->msix.msix_location = ptr;
613 cfg->msix.msix_ctrl = REG(ptr + PCIR_MSIX_CTRL, 2);
614 cfg->msix.msix_msgnum = (cfg->msix.msix_ctrl &
615 PCIM_MSIXCTRL_TABLE_SIZE) + 1;
616 val = REG(ptr + PCIR_MSIX_TABLE, 4);
617 cfg->msix.msix_table_bar = PCIR_BAR(val &
619 cfg->msix.msix_table_offset = val & ~PCIM_MSIX_BIR_MASK;
620 val = REG(ptr + PCIR_MSIX_PBA, 4);
621 cfg->msix.msix_pba_bar = PCIR_BAR(val &
623 cfg->msix.msix_pba_offset = val & ~PCIM_MSIX_BIR_MASK;
625 case PCIY_VPD: /* PCI Vital Product Data */
626 cfg->vpd.vpd_reg = ptr;
629 /* Should always be true. */
630 if ((cfg->hdrtype & PCIM_HDRTYPE) == 1) {
631 val = REG(ptr + PCIR_SUBVENDCAP_ID, 4);
632 cfg->subvendor = val & 0xffff;
633 cfg->subdevice = val >> 16;
636 case PCIY_PCIX: /* PCI-X */
638 * Assume we have a PCI-X chipset if we have
639 * at least one PCI-PCI bridge with a PCI-X
640 * capability. Note that some systems with
641 * PCI-express or HT chipsets might match on
642 * this check as well.
644 if ((cfg->hdrtype & PCIM_HDRTYPE) == 1)
647 case PCIY_EXPRESS: /* PCI-express */
649 * Assume we have a PCI-express chipset if we have
650 * at least one PCI-express device.
658 /* REG and WREG use carry through to next functions */
662 * PCI Vital Product Data
665 #define PCI_VPD_TIMEOUT 1000000
668 pci_read_vpd_reg(device_t pcib, pcicfgregs *cfg, int reg, uint32_t *data)
670 int count = PCI_VPD_TIMEOUT;
672 KASSERT((reg & 3) == 0, ("VPD register must by 4 byte aligned"));
674 WREG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, reg, 2);
676 while ((REG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, 2) & 0x8000) != 0x8000) {
679 DELAY(1); /* limit looping */
681 *data = (REG(cfg->vpd.vpd_reg + PCIR_VPD_DATA, 4));
688 pci_write_vpd_reg(device_t pcib, pcicfgregs *cfg, int reg, uint32_t data)
690 int count = PCI_VPD_TIMEOUT;
692 KASSERT((reg & 3) == 0, ("VPD register must by 4 byte aligned"));
694 WREG(cfg->vpd.vpd_reg + PCIR_VPD_DATA, data, 4);
695 WREG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, reg | 0x8000, 2);
696 while ((REG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, 2) & 0x8000) == 0x8000) {
699 DELAY(1); /* limit looping */
706 #undef PCI_VPD_TIMEOUT
708 struct vpd_readstate {
718 vpd_nextbyte(struct vpd_readstate *vrs, uint8_t *data)
723 if (vrs->bytesinval == 0) {
724 if (pci_read_vpd_reg(vrs->pcib, vrs->cfg, vrs->off, ®))
726 vrs->val = le32toh(reg);
728 byte = vrs->val & 0xff;
731 vrs->val = vrs->val >> 8;
732 byte = vrs->val & 0xff;
742 pci_read_vpd(device_t pcib, pcicfgregs *cfg)
744 struct vpd_readstate vrs;
749 int alloc, off; /* alloc/off for RO/W arrays */
755 /* init vpd reader */
763 name = remain = i = 0; /* shut up stupid gcc */
764 alloc = off = 0; /* shut up stupid gcc */
765 dflen = 0; /* shut up stupid gcc */
768 if (vpd_nextbyte(&vrs, &byte)) {
773 printf("vpd: val: %#x, off: %d, bytesinval: %d, byte: %#hhx, " \
774 "state: %d, remain: %d, name: %#x, i: %d\n", vrs.val,
775 vrs.off, vrs.bytesinval, byte, state, remain, name, i);
778 case 0: /* item name */
780 if (vpd_nextbyte(&vrs, &byte2)) {
785 if (vpd_nextbyte(&vrs, &byte2)) {
789 remain |= byte2 << 8;
790 if (remain > (0x7f*4 - vrs.off)) {
793 "pci%d:%d:%d:%d: invalid VPD data, remain %#x\n",
794 cfg->domain, cfg->bus, cfg->slot,
800 name = (byte >> 3) & 0xf;
803 case 0x2: /* String */
804 cfg->vpd.vpd_ident = malloc(remain + 1,
812 case 0x10: /* VPD-R */
815 cfg->vpd.vpd_ros = malloc(alloc *
816 sizeof(*cfg->vpd.vpd_ros), M_DEVBUF,
820 case 0x11: /* VPD-W */
823 cfg->vpd.vpd_w = malloc(alloc *
824 sizeof(*cfg->vpd.vpd_w), M_DEVBUF,
828 default: /* Invalid data, abort */
834 case 1: /* Identifier String */
835 cfg->vpd.vpd_ident[i++] = byte;
838 cfg->vpd.vpd_ident[i] = '\0';
843 case 2: /* VPD-R Keyword Header */
845 cfg->vpd.vpd_ros = reallocf(cfg->vpd.vpd_ros,
846 (alloc *= 2) * sizeof(*cfg->vpd.vpd_ros),
847 M_DEVBUF, M_WAITOK | M_ZERO);
849 cfg->vpd.vpd_ros[off].keyword[0] = byte;
850 if (vpd_nextbyte(&vrs, &byte2)) {
854 cfg->vpd.vpd_ros[off].keyword[1] = byte2;
855 if (vpd_nextbyte(&vrs, &byte2)) {
861 strncmp(cfg->vpd.vpd_ros[off].keyword, "RV",
864 * if this happens, we can't trust the rest
868 "pci%d:%d:%d:%d: bad keyword length: %d\n",
869 cfg->domain, cfg->bus, cfg->slot,
874 } else if (dflen == 0) {
875 cfg->vpd.vpd_ros[off].value = malloc(1 *
876 sizeof(*cfg->vpd.vpd_ros[off].value),
878 cfg->vpd.vpd_ros[off].value[0] = '\x00';
880 cfg->vpd.vpd_ros[off].value = malloc(
882 sizeof(*cfg->vpd.vpd_ros[off].value),
886 /* keep in sync w/ state 3's transistions */
887 if (dflen == 0 && remain == 0)
895 case 3: /* VPD-R Keyword Value */
896 cfg->vpd.vpd_ros[off].value[i++] = byte;
897 if (strncmp(cfg->vpd.vpd_ros[off].keyword,
898 "RV", 2) == 0 && cksumvalid == -1) {
904 "pci%d:%d:%d:%d: bad VPD cksum, remain %hhu\n",
905 cfg->domain, cfg->bus,
906 cfg->slot, cfg->func,
915 /* keep in sync w/ state 2's transistions */
917 cfg->vpd.vpd_ros[off++].value[i++] = '\0';
918 if (dflen == 0 && remain == 0) {
919 cfg->vpd.vpd_rocnt = off;
920 cfg->vpd.vpd_ros = reallocf(cfg->vpd.vpd_ros,
921 off * sizeof(*cfg->vpd.vpd_ros),
922 M_DEVBUF, M_WAITOK | M_ZERO);
924 } else if (dflen == 0)
934 case 5: /* VPD-W Keyword Header */
936 cfg->vpd.vpd_w = reallocf(cfg->vpd.vpd_w,
937 (alloc *= 2) * sizeof(*cfg->vpd.vpd_w),
938 M_DEVBUF, M_WAITOK | M_ZERO);
940 cfg->vpd.vpd_w[off].keyword[0] = byte;
941 if (vpd_nextbyte(&vrs, &byte2)) {
945 cfg->vpd.vpd_w[off].keyword[1] = byte2;
946 if (vpd_nextbyte(&vrs, &byte2)) {
950 cfg->vpd.vpd_w[off].len = dflen = byte2;
951 cfg->vpd.vpd_w[off].start = vrs.off - vrs.bytesinval;
952 cfg->vpd.vpd_w[off].value = malloc((dflen + 1) *
953 sizeof(*cfg->vpd.vpd_w[off].value),
957 /* keep in sync w/ state 6's transistions */
958 if (dflen == 0 && remain == 0)
966 case 6: /* VPD-W Keyword Value */
967 cfg->vpd.vpd_w[off].value[i++] = byte;
970 /* keep in sync w/ state 5's transistions */
972 cfg->vpd.vpd_w[off++].value[i++] = '\0';
973 if (dflen == 0 && remain == 0) {
974 cfg->vpd.vpd_wcnt = off;
975 cfg->vpd.vpd_w = reallocf(cfg->vpd.vpd_w,
976 off * sizeof(*cfg->vpd.vpd_w),
977 M_DEVBUF, M_WAITOK | M_ZERO);
979 } else if (dflen == 0)
984 printf("pci%d:%d:%d:%d: invalid state: %d\n",
985 cfg->domain, cfg->bus, cfg->slot, cfg->func,
992 if (cksumvalid == 0 || state < -1) {
993 /* read-only data bad, clean up */
994 if (cfg->vpd.vpd_ros != NULL) {
995 for (off = 0; cfg->vpd.vpd_ros[off].value; off++)
996 free(cfg->vpd.vpd_ros[off].value, M_DEVBUF);
997 free(cfg->vpd.vpd_ros, M_DEVBUF);
998 cfg->vpd.vpd_ros = NULL;
1002 /* I/O error, clean up */
1003 printf("pci%d:%d:%d:%d: failed to read VPD data.\n",
1004 cfg->domain, cfg->bus, cfg->slot, cfg->func);
1005 if (cfg->vpd.vpd_ident != NULL) {
1006 free(cfg->vpd.vpd_ident, M_DEVBUF);
1007 cfg->vpd.vpd_ident = NULL;
1009 if (cfg->vpd.vpd_w != NULL) {
1010 for (off = 0; cfg->vpd.vpd_w[off].value; off++)
1011 free(cfg->vpd.vpd_w[off].value, M_DEVBUF);
1012 free(cfg->vpd.vpd_w, M_DEVBUF);
1013 cfg->vpd.vpd_w = NULL;
1016 cfg->vpd.vpd_cached = 1;
1022 pci_get_vpd_ident_method(device_t dev, device_t child, const char **identptr)
1024 struct pci_devinfo *dinfo = device_get_ivars(child);
1025 pcicfgregs *cfg = &dinfo->cfg;
1027 if (!cfg->vpd.vpd_cached && cfg->vpd.vpd_reg != 0)
1028 pci_read_vpd(device_get_parent(dev), cfg);
1030 *identptr = cfg->vpd.vpd_ident;
1032 if (*identptr == NULL)
1039 pci_get_vpd_readonly_method(device_t dev, device_t child, const char *kw,
1042 struct pci_devinfo *dinfo = device_get_ivars(child);
1043 pcicfgregs *cfg = &dinfo->cfg;
1046 if (!cfg->vpd.vpd_cached && cfg->vpd.vpd_reg != 0)
1047 pci_read_vpd(device_get_parent(dev), cfg);
1049 for (i = 0; i < cfg->vpd.vpd_rocnt; i++)
1050 if (memcmp(kw, cfg->vpd.vpd_ros[i].keyword,
1051 sizeof(cfg->vpd.vpd_ros[i].keyword)) == 0) {
1052 *vptr = cfg->vpd.vpd_ros[i].value;
1055 if (i != cfg->vpd.vpd_rocnt)
1063 * Find the requested extended capability and return the offset in
1064 * configuration space via the pointer provided. The function returns
1065 * 0 on success and error code otherwise.
1068 pci_find_extcap_method(device_t dev, device_t child, int capability,
1071 struct pci_devinfo *dinfo = device_get_ivars(child);
1072 pcicfgregs *cfg = &dinfo->cfg;
1077 * Check the CAP_LIST bit of the PCI status register first.
1079 status = pci_read_config(child, PCIR_STATUS, 2);
1080 if (!(status & PCIM_STATUS_CAPPRESENT))
1084 * Determine the start pointer of the capabilities list.
1086 switch (cfg->hdrtype & PCIM_HDRTYPE) {
1092 ptr = PCIR_CAP_PTR_2;
1096 return (ENXIO); /* no extended capabilities support */
1098 ptr = pci_read_config(child, ptr, 1);
1101 * Traverse the capabilities list.
1104 if (pci_read_config(child, ptr + PCICAP_ID, 1) == capability) {
1109 ptr = pci_read_config(child, ptr + PCICAP_NEXTPTR, 1);
1116 * Support for MSI-X message interrupts.
1119 pci_enable_msix(device_t dev, u_int index, uint64_t address, uint32_t data)
1121 struct pci_devinfo *dinfo = device_get_ivars(dev);
1122 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1125 KASSERT(msix->msix_table_len > index, ("bogus index"));
1126 offset = msix->msix_table_offset + index * 16;
1127 bus_write_4(msix->msix_table_res, offset, address & 0xffffffff);
1128 bus_write_4(msix->msix_table_res, offset + 4, address >> 32);
1129 bus_write_4(msix->msix_table_res, offset + 8, data);
1131 /* Enable MSI -> HT mapping. */
1132 pci_ht_map_msi(dev, address);
1136 pci_mask_msix(device_t dev, u_int index)
1138 struct pci_devinfo *dinfo = device_get_ivars(dev);
1139 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1140 uint32_t offset, val;
1142 KASSERT(msix->msix_msgnum > index, ("bogus index"));
1143 offset = msix->msix_table_offset + index * 16 + 12;
1144 val = bus_read_4(msix->msix_table_res, offset);
1145 if (!(val & PCIM_MSIX_VCTRL_MASK)) {
1146 val |= PCIM_MSIX_VCTRL_MASK;
1147 bus_write_4(msix->msix_table_res, offset, val);
1152 pci_unmask_msix(device_t dev, u_int index)
1154 struct pci_devinfo *dinfo = device_get_ivars(dev);
1155 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1156 uint32_t offset, val;
1158 KASSERT(msix->msix_table_len > index, ("bogus index"));
1159 offset = msix->msix_table_offset + index * 16 + 12;
1160 val = bus_read_4(msix->msix_table_res, offset);
1161 if (val & PCIM_MSIX_VCTRL_MASK) {
1162 val &= ~PCIM_MSIX_VCTRL_MASK;
1163 bus_write_4(msix->msix_table_res, offset, val);
1168 pci_pending_msix(device_t dev, u_int index)
1170 struct pci_devinfo *dinfo = device_get_ivars(dev);
1171 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1172 uint32_t offset, bit;
1174 KASSERT(msix->msix_table_len > index, ("bogus index"));
1175 offset = msix->msix_pba_offset + (index / 32) * 4;
1176 bit = 1 << index % 32;
1177 return (bus_read_4(msix->msix_pba_res, offset) & bit);
1181 * Restore MSI-X registers and table during resume. If MSI-X is
1182 * enabled then walk the virtual table to restore the actual MSI-X
1186 pci_resume_msix(device_t dev)
1188 struct pci_devinfo *dinfo = device_get_ivars(dev);
1189 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1190 struct msix_table_entry *mte;
1191 struct msix_vector *mv;
1194 if (msix->msix_alloc > 0) {
1195 /* First, mask all vectors. */
1196 for (i = 0; i < msix->msix_msgnum; i++)
1197 pci_mask_msix(dev, i);
1199 /* Second, program any messages with at least one handler. */
1200 for (i = 0; i < msix->msix_table_len; i++) {
1201 mte = &msix->msix_table[i];
1202 if (mte->mte_vector == 0 || mte->mte_handlers == 0)
1204 mv = &msix->msix_vectors[mte->mte_vector - 1];
1205 pci_enable_msix(dev, i, mv->mv_address, mv->mv_data);
1206 pci_unmask_msix(dev, i);
1209 pci_write_config(dev, msix->msix_location + PCIR_MSIX_CTRL,
1210 msix->msix_ctrl, 2);
1214 * Attempt to allocate *count MSI-X messages. The actual number allocated is
1215 * returned in *count. After this function returns, each message will be
1216 * available to the driver as SYS_RES_IRQ resources starting at rid 1.
1219 pci_alloc_msix_method(device_t dev, device_t child, int *count)
1221 struct pci_devinfo *dinfo = device_get_ivars(child);
1222 pcicfgregs *cfg = &dinfo->cfg;
1223 struct resource_list_entry *rle;
1224 int actual, error, i, irq, max;
1226 /* Don't let count == 0 get us into trouble. */
1230 /* If rid 0 is allocated, then fail. */
1231 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 0);
1232 if (rle != NULL && rle->res != NULL)
1235 /* Already have allocated messages? */
1236 if (cfg->msi.msi_alloc != 0 || cfg->msix.msix_alloc != 0)
1239 /* If MSI is blacklisted for this system, fail. */
1240 if (pci_msi_blacklisted())
1243 /* MSI-X capability present? */
1244 if (cfg->msix.msix_location == 0 || !pci_do_msix)
1247 /* Make sure the appropriate BARs are mapped. */
1248 rle = resource_list_find(&dinfo->resources, SYS_RES_MEMORY,
1249 cfg->msix.msix_table_bar);
1250 if (rle == NULL || rle->res == NULL ||
1251 !(rman_get_flags(rle->res) & RF_ACTIVE))
1253 cfg->msix.msix_table_res = rle->res;
1254 if (cfg->msix.msix_pba_bar != cfg->msix.msix_table_bar) {
1255 rle = resource_list_find(&dinfo->resources, SYS_RES_MEMORY,
1256 cfg->msix.msix_pba_bar);
1257 if (rle == NULL || rle->res == NULL ||
1258 !(rman_get_flags(rle->res) & RF_ACTIVE))
1261 cfg->msix.msix_pba_res = rle->res;
1264 device_printf(child,
1265 "attempting to allocate %d MSI-X vectors (%d supported)\n",
1266 *count, cfg->msix.msix_msgnum);
1267 max = min(*count, cfg->msix.msix_msgnum);
1268 for (i = 0; i < max; i++) {
1269 /* Allocate a message. */
1270 error = PCIB_ALLOC_MSIX(device_get_parent(dev), child, &irq);
1273 resource_list_add(&dinfo->resources, SYS_RES_IRQ, i + 1, irq,
1279 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 1);
1281 device_printf(child, "using IRQ %lu for MSI-X\n",
1287 * Be fancy and try to print contiguous runs of
1288 * IRQ values as ranges. 'irq' is the previous IRQ.
1289 * 'run' is true if we are in a range.
1291 device_printf(child, "using IRQs %lu", rle->start);
1294 for (i = 1; i < actual; i++) {
1295 rle = resource_list_find(&dinfo->resources,
1296 SYS_RES_IRQ, i + 1);
1298 /* Still in a run? */
1299 if (rle->start == irq + 1) {
1305 /* Finish previous range. */
1311 /* Start new range. */
1312 printf(",%lu", rle->start);
1316 /* Unfinished range? */
1319 printf(" for MSI-X\n");
1323 /* Mask all vectors. */
1324 for (i = 0; i < cfg->msix.msix_msgnum; i++)
1325 pci_mask_msix(child, i);
1327 /* Allocate and initialize vector data and virtual table. */
1328 cfg->msix.msix_vectors = malloc(sizeof(struct msix_vector) * actual,
1329 M_DEVBUF, M_WAITOK | M_ZERO);
1330 cfg->msix.msix_table = malloc(sizeof(struct msix_table_entry) * actual,
1331 M_DEVBUF, M_WAITOK | M_ZERO);
1332 for (i = 0; i < actual; i++) {
1333 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1);
1334 cfg->msix.msix_vectors[i].mv_irq = rle->start;
1335 cfg->msix.msix_table[i].mte_vector = i + 1;
1338 /* Update control register to enable MSI-X. */
1339 cfg->msix.msix_ctrl |= PCIM_MSIXCTRL_MSIX_ENABLE;
1340 pci_write_config(child, cfg->msix.msix_location + PCIR_MSIX_CTRL,
1341 cfg->msix.msix_ctrl, 2);
1343 /* Update counts of alloc'd messages. */
1344 cfg->msix.msix_alloc = actual;
1345 cfg->msix.msix_table_len = actual;
1351 * By default, pci_alloc_msix() will assign the allocated IRQ
1352 * resources consecutively to the first N messages in the MSI-X table.
1353 * However, device drivers may want to use different layouts if they
1354 * either receive fewer messages than they asked for, or they wish to
1355 * populate the MSI-X table sparsely. This method allows the driver
1356 * to specify what layout it wants. It must be called after a
1357 * successful pci_alloc_msix() but before any of the associated
1358 * SYS_RES_IRQ resources are allocated via bus_alloc_resource().
1360 * The 'vectors' array contains 'count' message vectors. The array
1361 * maps directly to the MSI-X table in that index 0 in the array
1362 * specifies the vector for the first message in the MSI-X table, etc.
1363 * The vector value in each array index can either be 0 to indicate
1364 * that no vector should be assigned to a message slot, or it can be a
1365 * number from 1 to N (where N is the count returned from a
1366 * succcessful call to pci_alloc_msix()) to indicate which message
1367 * vector (IRQ) to be used for the corresponding message.
1369 * On successful return, each message with a non-zero vector will have
1370 * an associated SYS_RES_IRQ whose rid is equal to the array index +
1371 * 1. Additionally, if any of the IRQs allocated via the previous
1372 * call to pci_alloc_msix() are not used in the mapping, those IRQs
1373 * will be freed back to the system automatically.
1375 * For example, suppose a driver has a MSI-X table with 6 messages and
1376 * asks for 6 messages, but pci_alloc_msix() only returns a count of
1377 * 3. Call the three vectors allocated by pci_alloc_msix() A, B, and
1378 * C. After the call to pci_alloc_msix(), the device will be setup to
1379 * have an MSI-X table of ABC--- (where - means no vector assigned).
1380 * If the driver ten passes a vector array of { 1, 0, 1, 2, 0, 2 },
1381 * then the MSI-X table will look like A-AB-B, and the 'C' vector will
1382 * be freed back to the system. This device will also have valid
1383 * SYS_RES_IRQ rids of 1, 3, 4, and 6.
1385 * In any case, the SYS_RES_IRQ rid X will always map to the message
1386 * at MSI-X table index X - 1 and will only be valid if a vector is
1387 * assigned to that table entry.
1390 pci_remap_msix_method(device_t dev, device_t child, int count,
1391 const u_int *vectors)
1393 struct pci_devinfo *dinfo = device_get_ivars(child);
1394 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1395 struct resource_list_entry *rle;
1396 int i, irq, j, *used;
1399 * Have to have at least one message in the table but the
1400 * table can't be bigger than the actual MSI-X table in the
1403 if (count == 0 || count > msix->msix_msgnum)
1406 /* Sanity check the vectors. */
1407 for (i = 0; i < count; i++)
1408 if (vectors[i] > msix->msix_alloc)
1412 * Make sure there aren't any holes in the vectors to be used.
1413 * It's a big pain to support it, and it doesn't really make
1414 * sense anyway. Also, at least one vector must be used.
1416 used = malloc(sizeof(int) * msix->msix_alloc, M_DEVBUF, M_WAITOK |
1418 for (i = 0; i < count; i++)
1419 if (vectors[i] != 0)
1420 used[vectors[i] - 1] = 1;
1421 for (i = 0; i < msix->msix_alloc - 1; i++)
1422 if (used[i] == 0 && used[i + 1] == 1) {
1423 free(used, M_DEVBUF);
1427 free(used, M_DEVBUF);
1431 /* Make sure none of the resources are allocated. */
1432 for (i = 0; i < msix->msix_table_len; i++) {
1433 if (msix->msix_table[i].mte_vector == 0)
1435 if (msix->msix_table[i].mte_handlers > 0)
1437 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1);
1438 KASSERT(rle != NULL, ("missing resource"));
1439 if (rle->res != NULL)
1443 /* Free the existing resource list entries. */
1444 for (i = 0; i < msix->msix_table_len; i++) {
1445 if (msix->msix_table[i].mte_vector == 0)
1447 resource_list_delete(&dinfo->resources, SYS_RES_IRQ, i + 1);
1451 * Build the new virtual table keeping track of which vectors are
1454 free(msix->msix_table, M_DEVBUF);
1455 msix->msix_table = malloc(sizeof(struct msix_table_entry) * count,
1456 M_DEVBUF, M_WAITOK | M_ZERO);
1457 for (i = 0; i < count; i++)
1458 msix->msix_table[i].mte_vector = vectors[i];
1459 msix->msix_table_len = count;
1461 /* Free any unused IRQs and resize the vectors array if necessary. */
1462 j = msix->msix_alloc - 1;
1464 struct msix_vector *vec;
1466 while (used[j] == 0) {
1467 PCIB_RELEASE_MSIX(device_get_parent(dev), child,
1468 msix->msix_vectors[j].mv_irq);
1471 vec = malloc(sizeof(struct msix_vector) * (j + 1), M_DEVBUF,
1473 bcopy(msix->msix_vectors, vec, sizeof(struct msix_vector) *
1475 free(msix->msix_vectors, M_DEVBUF);
1476 msix->msix_vectors = vec;
1477 msix->msix_alloc = j + 1;
1479 free(used, M_DEVBUF);
1481 /* Map the IRQs onto the rids. */
1482 for (i = 0; i < count; i++) {
1483 if (vectors[i] == 0)
1485 irq = msix->msix_vectors[vectors[i]].mv_irq;
1486 resource_list_add(&dinfo->resources, SYS_RES_IRQ, i + 1, irq,
1491 device_printf(child, "Remapped MSI-X IRQs as: ");
1492 for (i = 0; i < count; i++) {
1495 if (vectors[i] == 0)
1499 msix->msix_vectors[vectors[i]].mv_irq);
1508 pci_release_msix(device_t dev, device_t child)
1510 struct pci_devinfo *dinfo = device_get_ivars(child);
1511 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1512 struct resource_list_entry *rle;
1515 /* Do we have any messages to release? */
1516 if (msix->msix_alloc == 0)
1519 /* Make sure none of the resources are allocated. */
1520 for (i = 0; i < msix->msix_table_len; i++) {
1521 if (msix->msix_table[i].mte_vector == 0)
1523 if (msix->msix_table[i].mte_handlers > 0)
1525 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1);
1526 KASSERT(rle != NULL, ("missing resource"));
1527 if (rle->res != NULL)
1531 /* Update control register to disable MSI-X. */
1532 msix->msix_ctrl &= ~PCIM_MSIXCTRL_MSIX_ENABLE;
1533 pci_write_config(child, msix->msix_location + PCIR_MSIX_CTRL,
1534 msix->msix_ctrl, 2);
1536 /* Free the resource list entries. */
1537 for (i = 0; i < msix->msix_table_len; i++) {
1538 if (msix->msix_table[i].mte_vector == 0)
1540 resource_list_delete(&dinfo->resources, SYS_RES_IRQ, i + 1);
1542 free(msix->msix_table, M_DEVBUF);
1543 msix->msix_table_len = 0;
1545 /* Release the IRQs. */
1546 for (i = 0; i < msix->msix_alloc; i++)
1547 PCIB_RELEASE_MSIX(device_get_parent(dev), child,
1548 msix->msix_vectors[i].mv_irq);
1549 free(msix->msix_vectors, M_DEVBUF);
1550 msix->msix_alloc = 0;
1555 * Return the max supported MSI-X messages this device supports.
1556 * Basically, assuming the MD code can alloc messages, this function
1557 * should return the maximum value that pci_alloc_msix() can return.
1558 * Thus, it is subject to the tunables, etc.
1561 pci_msix_count_method(device_t dev, device_t child)
1563 struct pci_devinfo *dinfo = device_get_ivars(child);
1564 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1566 if (pci_do_msix && msix->msix_location != 0)
1567 return (msix->msix_msgnum);
1572 * HyperTransport MSI mapping control
1575 pci_ht_map_msi(device_t dev, uint64_t addr)
1577 struct pci_devinfo *dinfo = device_get_ivars(dev);
1578 struct pcicfg_ht *ht = &dinfo->cfg.ht;
1583 if (addr && !(ht->ht_msictrl & PCIM_HTCMD_MSI_ENABLE) &&
1584 ht->ht_msiaddr >> 20 == addr >> 20) {
1585 /* Enable MSI -> HT mapping. */
1586 ht->ht_msictrl |= PCIM_HTCMD_MSI_ENABLE;
1587 pci_write_config(dev, ht->ht_msimap + PCIR_HT_COMMAND,
1591 if (!addr && ht->ht_msictrl & PCIM_HTCMD_MSI_ENABLE) {
1592 /* Disable MSI -> HT mapping. */
1593 ht->ht_msictrl &= ~PCIM_HTCMD_MSI_ENABLE;
1594 pci_write_config(dev, ht->ht_msimap + PCIR_HT_COMMAND,
1600 pci_get_max_read_req(device_t dev)
1605 if (pci_find_extcap(dev, PCIY_EXPRESS, &cap) != 0)
1607 val = pci_read_config(dev, cap + PCIR_EXPRESS_DEVICE_CTL, 2);
1608 val &= PCIM_EXP_CTL_MAX_READ_REQUEST;
1610 return (1 << (val + 7));
1614 pci_set_max_read_req(device_t dev, int size)
1619 if (pci_find_extcap(dev, PCIY_EXPRESS, &cap) != 0)
1625 size = (1 << (fls(size) - 1));
1626 val = pci_read_config(dev, cap + PCIR_EXPRESS_DEVICE_CTL, 2);
1627 val &= ~PCIM_EXP_CTL_MAX_READ_REQUEST;
1628 val |= (fls(size) - 8) << 12;
1629 pci_write_config(dev, cap + PCIR_EXPRESS_DEVICE_CTL, val, 2);
1634 * Support for MSI message signalled interrupts.
1637 pci_enable_msi(device_t dev, uint64_t address, uint16_t data)
1639 struct pci_devinfo *dinfo = device_get_ivars(dev);
1640 struct pcicfg_msi *msi = &dinfo->cfg.msi;
1642 /* Write data and address values. */
1643 pci_write_config(dev, msi->msi_location + PCIR_MSI_ADDR,
1644 address & 0xffffffff, 4);
1645 if (msi->msi_ctrl & PCIM_MSICTRL_64BIT) {
1646 pci_write_config(dev, msi->msi_location + PCIR_MSI_ADDR_HIGH,
1648 pci_write_config(dev, msi->msi_location + PCIR_MSI_DATA_64BIT,
1651 pci_write_config(dev, msi->msi_location + PCIR_MSI_DATA, data,
1654 /* Enable MSI in the control register. */
1655 msi->msi_ctrl |= PCIM_MSICTRL_MSI_ENABLE;
1656 pci_write_config(dev, msi->msi_location + PCIR_MSI_CTRL, msi->msi_ctrl,
1659 /* Enable MSI -> HT mapping. */
1660 pci_ht_map_msi(dev, address);
1664 pci_disable_msi(device_t dev)
1666 struct pci_devinfo *dinfo = device_get_ivars(dev);
1667 struct pcicfg_msi *msi = &dinfo->cfg.msi;
1669 /* Disable MSI -> HT mapping. */
1670 pci_ht_map_msi(dev, 0);
1672 /* Disable MSI in the control register. */
1673 msi->msi_ctrl &= ~PCIM_MSICTRL_MSI_ENABLE;
1674 pci_write_config(dev, msi->msi_location + PCIR_MSI_CTRL, msi->msi_ctrl,
1679 * Restore MSI registers during resume. If MSI is enabled then
1680 * restore the data and address registers in addition to the control
1684 pci_resume_msi(device_t dev)
1686 struct pci_devinfo *dinfo = device_get_ivars(dev);
1687 struct pcicfg_msi *msi = &dinfo->cfg.msi;
1691 if (msi->msi_ctrl & PCIM_MSICTRL_MSI_ENABLE) {
1692 address = msi->msi_addr;
1693 data = msi->msi_data;
1694 pci_write_config(dev, msi->msi_location + PCIR_MSI_ADDR,
1695 address & 0xffffffff, 4);
1696 if (msi->msi_ctrl & PCIM_MSICTRL_64BIT) {
1697 pci_write_config(dev, msi->msi_location +
1698 PCIR_MSI_ADDR_HIGH, address >> 32, 4);
1699 pci_write_config(dev, msi->msi_location +
1700 PCIR_MSI_DATA_64BIT, data, 2);
1702 pci_write_config(dev, msi->msi_location + PCIR_MSI_DATA,
1705 pci_write_config(dev, msi->msi_location + PCIR_MSI_CTRL, msi->msi_ctrl,
1710 pci_remap_msi_irq(device_t dev, u_int irq)
1712 struct pci_devinfo *dinfo = device_get_ivars(dev);
1713 pcicfgregs *cfg = &dinfo->cfg;
1714 struct resource_list_entry *rle;
1715 struct msix_table_entry *mte;
1716 struct msix_vector *mv;
1722 bus = device_get_parent(dev);
1725 * Handle MSI first. We try to find this IRQ among our list
1726 * of MSI IRQs. If we find it, we request updated address and
1727 * data registers and apply the results.
1729 if (cfg->msi.msi_alloc > 0) {
1731 /* If we don't have any active handlers, nothing to do. */
1732 if (cfg->msi.msi_handlers == 0)
1734 for (i = 0; i < cfg->msi.msi_alloc; i++) {
1735 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ,
1737 if (rle->start == irq) {
1738 error = PCIB_MAP_MSI(device_get_parent(bus),
1739 dev, irq, &addr, &data);
1742 pci_disable_msi(dev);
1743 dinfo->cfg.msi.msi_addr = addr;
1744 dinfo->cfg.msi.msi_data = data;
1745 pci_enable_msi(dev, addr, data);
1753 * For MSI-X, we check to see if we have this IRQ. If we do,
1754 * we request the updated mapping info. If that works, we go
1755 * through all the slots that use this IRQ and update them.
1757 if (cfg->msix.msix_alloc > 0) {
1758 for (i = 0; i < cfg->msix.msix_alloc; i++) {
1759 mv = &cfg->msix.msix_vectors[i];
1760 if (mv->mv_irq == irq) {
1761 error = PCIB_MAP_MSI(device_get_parent(bus),
1762 dev, irq, &addr, &data);
1765 mv->mv_address = addr;
1767 for (j = 0; j < cfg->msix.msix_table_len; j++) {
1768 mte = &cfg->msix.msix_table[j];
1769 if (mte->mte_vector != i + 1)
1771 if (mte->mte_handlers == 0)
1773 pci_mask_msix(dev, j);
1774 pci_enable_msix(dev, j, addr, data);
1775 pci_unmask_msix(dev, j);
1786 * Returns true if the specified device is blacklisted because MSI
1790 pci_msi_device_blacklisted(device_t dev)
1792 struct pci_quirk *q;
1794 if (!pci_honor_msi_blacklist)
1797 for (q = &pci_quirks[0]; q->devid; q++) {
1798 if (q->devid == pci_get_devid(dev) &&
1799 q->type == PCI_QUIRK_DISABLE_MSI)
1806 * Determine if MSI is blacklisted globally on this sytem. Currently,
1807 * we just check for blacklisted chipsets as represented by the
1808 * host-PCI bridge at device 0:0:0. In the future, it may become
1809 * necessary to check other system attributes, such as the kenv values
1810 * that give the motherboard manufacturer and model number.
1813 pci_msi_blacklisted(void)
1817 if (!pci_honor_msi_blacklist)
1820 /* Blacklist all non-PCI-express and non-PCI-X chipsets. */
1821 if (!(pcie_chipset || pcix_chipset))
1824 dev = pci_find_bsf(0, 0, 0);
1826 return (pci_msi_device_blacklisted(dev));
1831 * Attempt to allocate *count MSI messages. The actual number allocated is
1832 * returned in *count. After this function returns, each message will be
1833 * available to the driver as SYS_RES_IRQ resources starting at a rid 1.
1836 pci_alloc_msi_method(device_t dev, device_t child, int *count)
1838 struct pci_devinfo *dinfo = device_get_ivars(child);
1839 pcicfgregs *cfg = &dinfo->cfg;
1840 struct resource_list_entry *rle;
1841 int actual, error, i, irqs[32];
1844 /* Don't let count == 0 get us into trouble. */
1848 /* If rid 0 is allocated, then fail. */
1849 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 0);
1850 if (rle != NULL && rle->res != NULL)
1853 /* Already have allocated messages? */
1854 if (cfg->msi.msi_alloc != 0 || cfg->msix.msix_alloc != 0)
1857 /* If MSI is blacklisted for this system, fail. */
1858 if (pci_msi_blacklisted())
1861 /* MSI capability present? */
1862 if (cfg->msi.msi_location == 0 || !pci_do_msi)
1866 device_printf(child,
1867 "attempting to allocate %d MSI vectors (%d supported)\n",
1868 *count, cfg->msi.msi_msgnum);
1870 /* Don't ask for more than the device supports. */
1871 actual = min(*count, cfg->msi.msi_msgnum);
1873 /* Don't ask for more than 32 messages. */
1874 actual = min(actual, 32);
1876 /* MSI requires power of 2 number of messages. */
1877 if (!powerof2(actual))
1881 /* Try to allocate N messages. */
1882 error = PCIB_ALLOC_MSI(device_get_parent(dev), child, actual,
1883 cfg->msi.msi_msgnum, irqs);
1894 * We now have N actual messages mapped onto SYS_RES_IRQ
1895 * resources in the irqs[] array, so add new resources
1896 * starting at rid 1.
1898 for (i = 0; i < actual; i++)
1899 resource_list_add(&dinfo->resources, SYS_RES_IRQ, i + 1,
1900 irqs[i], irqs[i], 1);
1904 device_printf(child, "using IRQ %d for MSI\n", irqs[0]);
1909 * Be fancy and try to print contiguous runs
1910 * of IRQ values as ranges. 'run' is true if
1911 * we are in a range.
1913 device_printf(child, "using IRQs %d", irqs[0]);
1915 for (i = 1; i < actual; i++) {
1917 /* Still in a run? */
1918 if (irqs[i] == irqs[i - 1] + 1) {
1923 /* Finish previous range. */
1925 printf("-%d", irqs[i - 1]);
1929 /* Start new range. */
1930 printf(",%d", irqs[i]);
1933 /* Unfinished range? */
1935 printf("-%d", irqs[actual - 1]);
1936 printf(" for MSI\n");
1940 /* Update control register with actual count. */
1941 ctrl = cfg->msi.msi_ctrl;
1942 ctrl &= ~PCIM_MSICTRL_MME_MASK;
1943 ctrl |= (ffs(actual) - 1) << 4;
1944 cfg->msi.msi_ctrl = ctrl;
1945 pci_write_config(child, cfg->msi.msi_location + PCIR_MSI_CTRL, ctrl, 2);
1947 /* Update counts of alloc'd messages. */
1948 cfg->msi.msi_alloc = actual;
1949 cfg->msi.msi_handlers = 0;
1954 /* Release the MSI messages associated with this device. */
1956 pci_release_msi_method(device_t dev, device_t child)
1958 struct pci_devinfo *dinfo = device_get_ivars(child);
1959 struct pcicfg_msi *msi = &dinfo->cfg.msi;
1960 struct resource_list_entry *rle;
1961 int error, i, irqs[32];
1963 /* Try MSI-X first. */
1964 error = pci_release_msix(dev, child);
1965 if (error != ENODEV)
1968 /* Do we have any messages to release? */
1969 if (msi->msi_alloc == 0)
1971 KASSERT(msi->msi_alloc <= 32, ("more than 32 alloc'd messages"));
1973 /* Make sure none of the resources are allocated. */
1974 if (msi->msi_handlers > 0)
1976 for (i = 0; i < msi->msi_alloc; i++) {
1977 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1);
1978 KASSERT(rle != NULL, ("missing MSI resource"));
1979 if (rle->res != NULL)
1981 irqs[i] = rle->start;
1984 /* Update control register with 0 count. */
1985 KASSERT(!(msi->msi_ctrl & PCIM_MSICTRL_MSI_ENABLE),
1986 ("%s: MSI still enabled", __func__));
1987 msi->msi_ctrl &= ~PCIM_MSICTRL_MME_MASK;
1988 pci_write_config(child, msi->msi_location + PCIR_MSI_CTRL,
1991 /* Release the messages. */
1992 PCIB_RELEASE_MSI(device_get_parent(dev), child, msi->msi_alloc, irqs);
1993 for (i = 0; i < msi->msi_alloc; i++)
1994 resource_list_delete(&dinfo->resources, SYS_RES_IRQ, i + 1);
1996 /* Update alloc count. */
2004 * Return the max supported MSI messages this device supports.
2005 * Basically, assuming the MD code can alloc messages, this function
2006 * should return the maximum value that pci_alloc_msi() can return.
2007 * Thus, it is subject to the tunables, etc.
2010 pci_msi_count_method(device_t dev, device_t child)
2012 struct pci_devinfo *dinfo = device_get_ivars(child);
2013 struct pcicfg_msi *msi = &dinfo->cfg.msi;
2015 if (pci_do_msi && msi->msi_location != 0)
2016 return (msi->msi_msgnum);
2020 /* free pcicfgregs structure and all depending data structures */
2023 pci_freecfg(struct pci_devinfo *dinfo)
2025 struct devlist *devlist_head;
2028 devlist_head = &pci_devq;
2030 if (dinfo->cfg.vpd.vpd_reg) {
2031 free(dinfo->cfg.vpd.vpd_ident, M_DEVBUF);
2032 for (i = 0; i < dinfo->cfg.vpd.vpd_rocnt; i++)
2033 free(dinfo->cfg.vpd.vpd_ros[i].value, M_DEVBUF);
2034 free(dinfo->cfg.vpd.vpd_ros, M_DEVBUF);
2035 for (i = 0; i < dinfo->cfg.vpd.vpd_wcnt; i++)
2036 free(dinfo->cfg.vpd.vpd_w[i].value, M_DEVBUF);
2037 free(dinfo->cfg.vpd.vpd_w, M_DEVBUF);
2039 STAILQ_REMOVE(devlist_head, dinfo, pci_devinfo, pci_links);
2040 free(dinfo, M_DEVBUF);
2042 /* increment the generation count */
2045 /* we're losing one device */
2051 * PCI power manangement
2054 pci_set_powerstate_method(device_t dev, device_t child, int state)
2056 struct pci_devinfo *dinfo = device_get_ivars(child);
2057 pcicfgregs *cfg = &dinfo->cfg;
2059 int result, oldstate, highest, delay;
2061 if (cfg->pp.pp_cap == 0)
2062 return (EOPNOTSUPP);
2065 * Optimize a no state change request away. While it would be OK to
2066 * write to the hardware in theory, some devices have shown odd
2067 * behavior when going from D3 -> D3.
2069 oldstate = pci_get_powerstate(child);
2070 if (oldstate == state)
2074 * The PCI power management specification states that after a state
2075 * transition between PCI power states, system software must
2076 * guarantee a minimal delay before the function accesses the device.
2077 * Compute the worst case delay that we need to guarantee before we
2078 * access the device. Many devices will be responsive much more
2079 * quickly than this delay, but there are some that don't respond
2080 * instantly to state changes. Transitions to/from D3 state require
2081 * 10ms, while D2 requires 200us, and D0/1 require none. The delay
2082 * is done below with DELAY rather than a sleeper function because
2083 * this function can be called from contexts where we cannot sleep.
2085 highest = (oldstate > state) ? oldstate : state;
2086 if (highest == PCI_POWERSTATE_D3)
2088 else if (highest == PCI_POWERSTATE_D2)
2092 status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_status, 2)
2093 & ~PCIM_PSTAT_DMASK;
2096 case PCI_POWERSTATE_D0:
2097 status |= PCIM_PSTAT_D0;
2099 case PCI_POWERSTATE_D1:
2100 if ((cfg->pp.pp_cap & PCIM_PCAP_D1SUPP) == 0)
2101 return (EOPNOTSUPP);
2102 status |= PCIM_PSTAT_D1;
2104 case PCI_POWERSTATE_D2:
2105 if ((cfg->pp.pp_cap & PCIM_PCAP_D2SUPP) == 0)
2106 return (EOPNOTSUPP);
2107 status |= PCIM_PSTAT_D2;
2109 case PCI_POWERSTATE_D3:
2110 status |= PCIM_PSTAT_D3;
2117 pci_printf(cfg, "Transition from D%d to D%d\n", oldstate,
2120 PCI_WRITE_CONFIG(dev, child, cfg->pp.pp_status, status, 2);
2127 pci_get_powerstate_method(device_t dev, device_t child)
2129 struct pci_devinfo *dinfo = device_get_ivars(child);
2130 pcicfgregs *cfg = &dinfo->cfg;
2134 if (cfg->pp.pp_cap != 0) {
2135 status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_status, 2);
2136 switch (status & PCIM_PSTAT_DMASK) {
2138 result = PCI_POWERSTATE_D0;
2141 result = PCI_POWERSTATE_D1;
2144 result = PCI_POWERSTATE_D2;
2147 result = PCI_POWERSTATE_D3;
2150 result = PCI_POWERSTATE_UNKNOWN;
2154 /* No support, device is always at D0 */
2155 result = PCI_POWERSTATE_D0;
2161 * Some convenience functions for PCI device drivers.
2164 static __inline void
2165 pci_set_command_bit(device_t dev, device_t child, uint16_t bit)
2169 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
2171 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2);
2174 static __inline void
2175 pci_clear_command_bit(device_t dev, device_t child, uint16_t bit)
2179 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
2181 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2);
2185 pci_enable_busmaster_method(device_t dev, device_t child)
2187 pci_set_command_bit(dev, child, PCIM_CMD_BUSMASTEREN);
2192 pci_disable_busmaster_method(device_t dev, device_t child)
2194 pci_clear_command_bit(dev, child, PCIM_CMD_BUSMASTEREN);
2199 pci_enable_io_method(device_t dev, device_t child, int space)
2204 case SYS_RES_IOPORT:
2205 bit = PCIM_CMD_PORTEN;
2207 case SYS_RES_MEMORY:
2208 bit = PCIM_CMD_MEMEN;
2213 pci_set_command_bit(dev, child, bit);
2218 pci_disable_io_method(device_t dev, device_t child, int space)
2223 case SYS_RES_IOPORT:
2224 bit = PCIM_CMD_PORTEN;
2226 case SYS_RES_MEMORY:
2227 bit = PCIM_CMD_MEMEN;
2232 pci_clear_command_bit(dev, child, bit);
2237 * New style pci driver. Parent device is either a pci-host-bridge or a
2238 * pci-pci-bridge. Both kinds are represented by instances of pcib.
2242 pci_print_verbose(struct pci_devinfo *dinfo)
2246 pcicfgregs *cfg = &dinfo->cfg;
2248 printf("found->\tvendor=0x%04x, dev=0x%04x, revid=0x%02x\n",
2249 cfg->vendor, cfg->device, cfg->revid);
2250 printf("\tdomain=%d, bus=%d, slot=%d, func=%d\n",
2251 cfg->domain, cfg->bus, cfg->slot, cfg->func);
2252 printf("\tclass=%02x-%02x-%02x, hdrtype=0x%02x, mfdev=%d\n",
2253 cfg->baseclass, cfg->subclass, cfg->progif, cfg->hdrtype,
2255 printf("\tcmdreg=0x%04x, statreg=0x%04x, cachelnsz=%d (dwords)\n",
2256 cfg->cmdreg, cfg->statreg, cfg->cachelnsz);
2257 printf("\tlattimer=0x%02x (%d ns), mingnt=0x%02x (%d ns), maxlat=0x%02x (%d ns)\n",
2258 cfg->lattimer, cfg->lattimer * 30, cfg->mingnt,
2259 cfg->mingnt * 250, cfg->maxlat, cfg->maxlat * 250);
2260 if (cfg->intpin > 0)
2261 printf("\tintpin=%c, irq=%d\n",
2262 cfg->intpin +'a' -1, cfg->intline);
2263 if (cfg->pp.pp_cap) {
2266 status = pci_read_config(cfg->dev, cfg->pp.pp_status, 2);
2267 printf("\tpowerspec %d supports D0%s%s D3 current D%d\n",
2268 cfg->pp.pp_cap & PCIM_PCAP_SPEC,
2269 cfg->pp.pp_cap & PCIM_PCAP_D1SUPP ? " D1" : "",
2270 cfg->pp.pp_cap & PCIM_PCAP_D2SUPP ? " D2" : "",
2271 status & PCIM_PSTAT_DMASK);
2273 if (cfg->msi.msi_location) {
2276 ctrl = cfg->msi.msi_ctrl;
2277 printf("\tMSI supports %d message%s%s%s\n",
2278 cfg->msi.msi_msgnum,
2279 (cfg->msi.msi_msgnum == 1) ? "" : "s",
2280 (ctrl & PCIM_MSICTRL_64BIT) ? ", 64 bit" : "",
2281 (ctrl & PCIM_MSICTRL_VECTOR) ? ", vector masks":"");
2283 if (cfg->msix.msix_location) {
2284 printf("\tMSI-X supports %d message%s ",
2285 cfg->msix.msix_msgnum,
2286 (cfg->msix.msix_msgnum == 1) ? "" : "s");
2287 if (cfg->msix.msix_table_bar == cfg->msix.msix_pba_bar)
2288 printf("in map 0x%x\n",
2289 cfg->msix.msix_table_bar);
2291 printf("in maps 0x%x and 0x%x\n",
2292 cfg->msix.msix_table_bar,
2293 cfg->msix.msix_pba_bar);
2299 pci_porten(device_t dev)
2301 return (pci_read_config(dev, PCIR_COMMAND, 2) & PCIM_CMD_PORTEN) != 0;
2305 pci_memen(device_t dev)
2307 return (pci_read_config(dev, PCIR_COMMAND, 2) & PCIM_CMD_MEMEN) != 0;
2311 pci_read_bar(device_t dev, int reg, pci_addr_t *mapp, pci_addr_t *testvalp)
2313 pci_addr_t map, testval;
2317 map = pci_read_config(dev, reg, 4);
2318 ln2range = pci_maprange(map);
2320 map |= (pci_addr_t)pci_read_config(dev, reg + 4, 4) << 32;
2323 * Disable decoding via the command register before
2324 * determining the BAR's length since we will be placing it in
2327 cmd = pci_read_config(dev, PCIR_COMMAND, 2);
2328 pci_write_config(dev, PCIR_COMMAND,
2329 cmd & ~(PCI_BAR_MEM(map) ? PCIM_CMD_MEMEN : PCIM_CMD_PORTEN), 2);
2332 * Determine the BAR's length by writing all 1's. The bottom
2333 * log_2(size) bits of the BAR will stick as 0 when we read
2336 pci_write_config(dev, reg, 0xffffffff, 4);
2337 testval = pci_read_config(dev, reg, 4);
2338 if (ln2range == 64) {
2339 pci_write_config(dev, reg + 4, 0xffffffff, 4);
2340 testval |= (pci_addr_t)pci_read_config(dev, reg + 4, 4) << 32;
2344 * Restore the original value of the BAR. We may have reprogrammed
2345 * the BAR of the low-level console device and when booting verbose,
2346 * we need the console device addressable.
2348 pci_write_config(dev, reg, map, 4);
2350 pci_write_config(dev, reg + 4, map >> 32, 4);
2351 pci_write_config(dev, PCIR_COMMAND, cmd, 2);
2354 *testvalp = testval;
2358 pci_write_bar(device_t dev, int reg, pci_addr_t base)
2363 map = pci_read_config(dev, reg, 4);
2364 ln2range = pci_maprange(map);
2365 pci_write_config(dev, reg, base, 4);
2367 pci_write_config(dev, reg + 4, base >> 32, 4);
2371 * Add a resource based on a pci map register. Return 1 if the map
2372 * register is a 32bit map register or 2 if it is a 64bit register.
2375 pci_add_map(device_t bus, device_t dev, int reg, struct resource_list *rl,
2376 int force, int prefetch)
2378 pci_addr_t base, map, testval;
2379 pci_addr_t start, end, count;
2380 int barlen, basezero, maprange, mapsize, type;
2382 struct resource *res;
2384 pci_read_bar(dev, reg, &map, &testval);
2385 if (PCI_BAR_MEM(map)) {
2386 type = SYS_RES_MEMORY;
2387 if (map & PCIM_BAR_MEM_PREFETCH)
2390 type = SYS_RES_IOPORT;
2391 mapsize = pci_mapsize(testval);
2392 base = pci_mapbase(map);
2393 #ifdef __PCI_BAR_ZERO_VALID
2396 basezero = base == 0;
2398 maprange = pci_maprange(map);
2399 barlen = maprange == 64 ? 2 : 1;
2402 * For I/O registers, if bottom bit is set, and the next bit up
2403 * isn't clear, we know we have a BAR that doesn't conform to the
2404 * spec, so ignore it. Also, sanity check the size of the data
2405 * areas to the type of memory involved. Memory must be at least
2406 * 16 bytes in size, while I/O ranges must be at least 4.
2408 if (PCI_BAR_IO(testval) && (testval & PCIM_BAR_IO_RESERVED) != 0)
2410 if ((type == SYS_RES_MEMORY && mapsize < 4) ||
2411 (type == SYS_RES_IOPORT && mapsize < 2))
2415 printf("\tmap[%02x]: type %s, range %2d, base %#jx, size %2d",
2416 reg, pci_maptype(map), maprange, (uintmax_t)base, mapsize);
2417 if (type == SYS_RES_IOPORT && !pci_porten(dev))
2418 printf(", port disabled\n");
2419 else if (type == SYS_RES_MEMORY && !pci_memen(dev))
2420 printf(", memory disabled\n");
2422 printf(", enabled\n");
2426 * If base is 0, then we have problems if this architecture does
2427 * not allow that. It is best to ignore such entries for the
2428 * moment. These will be allocated later if the driver specifically
2429 * requests them. However, some removable busses look better when
2430 * all resources are allocated, so allow '0' to be overriden.
2432 * Similarly treat maps whose values is the same as the test value
2433 * read back. These maps have had all f's written to them by the
2434 * BIOS in an attempt to disable the resources.
2436 if (!force && (basezero || map == testval))
2438 if ((u_long)base != base) {
2440 "pci%d:%d:%d:%d bar %#x too many address bits",
2441 pci_get_domain(dev), pci_get_bus(dev), pci_get_slot(dev),
2442 pci_get_function(dev), reg);
2447 * This code theoretically does the right thing, but has
2448 * undesirable side effects in some cases where peripherals
2449 * respond oddly to having these bits enabled. Let the user
2450 * be able to turn them off (since pci_enable_io_modes is 1 by
2453 if (pci_enable_io_modes) {
2454 /* Turn on resources that have been left off by a lazy BIOS */
2455 if (type == SYS_RES_IOPORT && !pci_porten(dev)) {
2456 cmd = pci_read_config(dev, PCIR_COMMAND, 2);
2457 cmd |= PCIM_CMD_PORTEN;
2458 pci_write_config(dev, PCIR_COMMAND, cmd, 2);
2460 if (type == SYS_RES_MEMORY && !pci_memen(dev)) {
2461 cmd = pci_read_config(dev, PCIR_COMMAND, 2);
2462 cmd |= PCIM_CMD_MEMEN;
2463 pci_write_config(dev, PCIR_COMMAND, cmd, 2);
2466 if (type == SYS_RES_IOPORT && !pci_porten(dev))
2468 if (type == SYS_RES_MEMORY && !pci_memen(dev))
2472 count = 1 << mapsize;
2473 if (basezero || base == pci_mapbase(testval)) {
2474 start = 0; /* Let the parent decide. */
2478 end = base + (1 << mapsize) - 1;
2480 resource_list_add(rl, type, reg, start, end, count);
2483 * Try to allocate the resource for this BAR from our parent
2484 * so that this resource range is already reserved. The
2485 * driver for this device will later inherit this resource in
2486 * pci_alloc_resource().
2488 res = resource_list_alloc(rl, bus, dev, type, ®, start, end, count,
2489 prefetch ? RF_PREFETCHABLE : 0);
2492 * If the allocation fails, clear the BAR and delete
2493 * the resource list entry to force
2494 * pci_alloc_resource() to allocate resources from the
2497 resource_list_delete(rl, type, reg);
2500 start = rman_get_start(res);
2501 rman_set_device(res, bus);
2503 pci_write_bar(dev, reg, start);
2508 * For ATA devices we need to decide early what addressing mode to use.
2509 * Legacy demands that the primary and secondary ATA ports sits on the
2510 * same addresses that old ISA hardware did. This dictates that we use
2511 * those addresses and ignore the BAR's if we cannot set PCI native
2515 pci_ata_maps(device_t bus, device_t dev, struct resource_list *rl, int force,
2516 uint32_t prefetchmask)
2519 int rid, type, progif;
2521 /* if this device supports PCI native addressing use it */
2522 progif = pci_read_config(dev, PCIR_PROGIF, 1);
2523 if ((progif & 0x8a) == 0x8a) {
2524 if (pci_mapbase(pci_read_config(dev, PCIR_BAR(0), 4)) &&
2525 pci_mapbase(pci_read_config(dev, PCIR_BAR(2), 4))) {
2526 printf("Trying ATA native PCI addressing mode\n");
2527 pci_write_config(dev, PCIR_PROGIF, progif | 0x05, 1);
2531 progif = pci_read_config(dev, PCIR_PROGIF, 1);
2532 type = SYS_RES_IOPORT;
2533 if (progif & PCIP_STORAGE_IDE_MODEPRIM) {
2534 pci_add_map(bus, dev, PCIR_BAR(0), rl, force,
2535 prefetchmask & (1 << 0));
2536 pci_add_map(bus, dev, PCIR_BAR(1), rl, force,
2537 prefetchmask & (1 << 1));
2540 resource_list_add(rl, type, rid, 0x1f0, 0x1f7, 8);
2541 r = resource_list_alloc(rl, bus, dev, type, &rid, 0x1f0, 0x1f7,
2543 rman_set_device(r, bus);
2545 resource_list_add(rl, type, rid, 0x3f6, 0x3f6, 1);
2546 r = resource_list_alloc(rl, bus, dev, type, &rid, 0x3f6, 0x3f6,
2548 rman_set_device(r, bus);
2550 if (progif & PCIP_STORAGE_IDE_MODESEC) {
2551 pci_add_map(bus, dev, PCIR_BAR(2), rl, force,
2552 prefetchmask & (1 << 2));
2553 pci_add_map(bus, dev, PCIR_BAR(3), rl, force,
2554 prefetchmask & (1 << 3));
2557 resource_list_add(rl, type, rid, 0x170, 0x177, 8);
2558 r = resource_list_alloc(rl, bus, dev, type, &rid, 0x170, 0x177,
2560 rman_set_device(r, bus);
2562 resource_list_add(rl, type, rid, 0x376, 0x376, 1);
2563 r = resource_list_alloc(rl, bus, dev, type, &rid, 0x376, 0x376,
2565 rman_set_device(r, bus);
2567 pci_add_map(bus, dev, PCIR_BAR(4), rl, force,
2568 prefetchmask & (1 << 4));
2569 pci_add_map(bus, dev, PCIR_BAR(5), rl, force,
2570 prefetchmask & (1 << 5));
2574 pci_assign_interrupt(device_t bus, device_t dev, int force_route)
2576 struct pci_devinfo *dinfo = device_get_ivars(dev);
2577 pcicfgregs *cfg = &dinfo->cfg;
2578 char tunable_name[64];
2581 /* Has to have an intpin to have an interrupt. */
2582 if (cfg->intpin == 0)
2585 /* Let the user override the IRQ with a tunable. */
2586 irq = PCI_INVALID_IRQ;
2587 snprintf(tunable_name, sizeof(tunable_name),
2588 "hw.pci%d.%d.%d.INT%c.irq",
2589 cfg->domain, cfg->bus, cfg->slot, cfg->intpin + 'A' - 1);
2590 if (TUNABLE_INT_FETCH(tunable_name, &irq) && (irq >= 255 || irq <= 0))
2591 irq = PCI_INVALID_IRQ;
2594 * If we didn't get an IRQ via the tunable, then we either use the
2595 * IRQ value in the intline register or we ask the bus to route an
2596 * interrupt for us. If force_route is true, then we only use the
2597 * value in the intline register if the bus was unable to assign an
2600 if (!PCI_INTERRUPT_VALID(irq)) {
2601 if (!PCI_INTERRUPT_VALID(cfg->intline) || force_route)
2602 irq = PCI_ASSIGN_INTERRUPT(bus, dev);
2603 if (!PCI_INTERRUPT_VALID(irq))
2607 /* If after all that we don't have an IRQ, just bail. */
2608 if (!PCI_INTERRUPT_VALID(irq))
2611 /* Update the config register if it changed. */
2612 if (irq != cfg->intline) {
2614 pci_write_config(dev, PCIR_INTLINE, irq, 1);
2617 /* Add this IRQ as rid 0 interrupt resource. */
2618 resource_list_add(&dinfo->resources, SYS_RES_IRQ, 0, irq, irq, 1);
2621 /* Perform early OHCI takeover from SMM. */
2623 ohci_early_takeover(device_t self)
2625 struct resource *res;
2631 res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &rid, RF_ACTIVE);
2635 ctl = bus_read_4(res, OHCI_CONTROL);
2636 if (ctl & OHCI_IR) {
2638 printf("ohci early: "
2639 "SMM active, request owner change\n");
2640 bus_write_4(res, OHCI_COMMAND_STATUS, OHCI_OCR);
2641 for (i = 0; (i < 100) && (ctl & OHCI_IR); i++) {
2643 ctl = bus_read_4(res, OHCI_CONTROL);
2645 if (ctl & OHCI_IR) {
2647 printf("ohci early: "
2648 "SMM does not respond, resetting\n");
2649 bus_write_4(res, OHCI_CONTROL, OHCI_HCFS_RESET);
2651 /* Disable interrupts */
2652 bus_write_4(res, OHCI_INTERRUPT_DISABLE, OHCI_ALL_INTRS);
2655 bus_release_resource(self, SYS_RES_MEMORY, rid, res);
2658 /* Perform early UHCI takeover from SMM. */
2660 uhci_early_takeover(device_t self)
2662 struct resource *res;
2666 * Set the PIRQD enable bit and switch off all the others. We don't
2667 * want legacy support to interfere with us XXX Does this also mean
2668 * that the BIOS won't touch the keyboard anymore if it is connected
2669 * to the ports of the root hub?
2671 pci_write_config(self, PCI_LEGSUP, PCI_LEGSUP_USBPIRQDEN, 2);
2673 /* Disable interrupts */
2674 rid = PCI_UHCI_BASE_REG;
2675 res = bus_alloc_resource_any(self, SYS_RES_IOPORT, &rid, RF_ACTIVE);
2677 bus_write_2(res, UHCI_INTR, 0);
2678 bus_release_resource(self, SYS_RES_IOPORT, rid, res);
2682 /* Perform early EHCI takeover from SMM. */
2684 ehci_early_takeover(device_t self)
2686 struct resource *res;
2696 res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &rid, RF_ACTIVE);
2700 cparams = bus_read_4(res, EHCI_HCCPARAMS);
2702 /* Synchronise with the BIOS if it owns the controller. */
2703 for (eecp = EHCI_HCC_EECP(cparams); eecp != 0;
2704 eecp = EHCI_EECP_NEXT(eec)) {
2705 eec = pci_read_config(self, eecp, 4);
2706 if (EHCI_EECP_ID(eec) != EHCI_EC_LEGSUP) {
2709 bios_sem = pci_read_config(self, eecp +
2710 EHCI_LEGSUP_BIOS_SEM, 1);
2711 if (bios_sem == 0) {
2715 printf("ehci early: "
2716 "SMM active, request owner change\n");
2718 pci_write_config(self, eecp + EHCI_LEGSUP_OS_SEM, 1, 1);
2720 for (i = 0; (i < 100) && (bios_sem != 0); i++) {
2722 bios_sem = pci_read_config(self, eecp +
2723 EHCI_LEGSUP_BIOS_SEM, 1);
2726 if (bios_sem != 0) {
2728 printf("ehci early: "
2729 "SMM does not respond\n");
2731 /* Disable interrupts */
2732 offs = bus_read_1(res, EHCI_CAPLENGTH);
2733 bus_write_4(res, offs + EHCI_USBINTR, 0);
2735 bus_release_resource(self, SYS_RES_MEMORY, rid, res);
2739 pci_add_resources(device_t bus, device_t dev, int force, uint32_t prefetchmask)
2741 struct pci_devinfo *dinfo = device_get_ivars(dev);
2742 pcicfgregs *cfg = &dinfo->cfg;
2743 struct resource_list *rl = &dinfo->resources;
2744 struct pci_quirk *q;
2747 /* ATA devices needs special map treatment */
2748 if ((pci_get_class(dev) == PCIC_STORAGE) &&
2749 (pci_get_subclass(dev) == PCIS_STORAGE_IDE) &&
2750 ((pci_get_progif(dev) & PCIP_STORAGE_IDE_MASTERDEV) ||
2751 (!pci_read_config(dev, PCIR_BAR(0), 4) &&
2752 !pci_read_config(dev, PCIR_BAR(2), 4))) )
2753 pci_ata_maps(bus, dev, rl, force, prefetchmask);
2755 for (i = 0; i < cfg->nummaps;)
2756 i += pci_add_map(bus, dev, PCIR_BAR(i), rl, force,
2757 prefetchmask & (1 << i));
2760 * Add additional, quirked resources.
2762 for (q = &pci_quirks[0]; q->devid; q++) {
2763 if (q->devid == ((cfg->device << 16) | cfg->vendor)
2764 && q->type == PCI_QUIRK_MAP_REG)
2765 pci_add_map(bus, dev, q->arg1, rl, force, 0);
2768 if (cfg->intpin > 0 && PCI_INTERRUPT_VALID(cfg->intline)) {
2769 #ifdef __PCI_REROUTE_INTERRUPT
2771 * Try to re-route interrupts. Sometimes the BIOS or
2772 * firmware may leave bogus values in these registers.
2773 * If the re-route fails, then just stick with what we
2776 pci_assign_interrupt(bus, dev, 1);
2778 pci_assign_interrupt(bus, dev, 0);
2782 if (pci_usb_takeover && pci_get_class(dev) == PCIC_SERIALBUS &&
2783 pci_get_subclass(dev) == PCIS_SERIALBUS_USB) {
2784 if (pci_get_progif(dev) == PCIP_SERIALBUS_USB_EHCI)
2785 ehci_early_takeover(dev);
2786 else if (pci_get_progif(dev) == PCIP_SERIALBUS_USB_OHCI)
2787 ohci_early_takeover(dev);
2788 else if (pci_get_progif(dev) == PCIP_SERIALBUS_USB_UHCI)
2789 uhci_early_takeover(dev);
2794 pci_add_children(device_t dev, int domain, int busno, size_t dinfo_size)
2796 #define REG(n, w) PCIB_READ_CONFIG(pcib, busno, s, f, n, w)
2797 device_t pcib = device_get_parent(dev);
2798 struct pci_devinfo *dinfo;
2800 int s, f, pcifunchigh;
2803 KASSERT(dinfo_size >= sizeof(struct pci_devinfo),
2804 ("dinfo_size too small"));
2805 maxslots = PCIB_MAXSLOTS(pcib);
2806 for (s = 0; s <= maxslots; s++) {
2810 hdrtype = REG(PCIR_HDRTYPE, 1);
2811 if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE)
2813 if (hdrtype & PCIM_MFDEV)
2814 pcifunchigh = PCI_FUNCMAX;
2815 for (f = 0; f <= pcifunchigh; f++) {
2816 dinfo = pci_read_device(pcib, domain, busno, s, f,
2818 if (dinfo != NULL) {
2819 pci_add_child(dev, dinfo);
2827 pci_add_child(device_t bus, struct pci_devinfo *dinfo)
2829 dinfo->cfg.dev = device_add_child(bus, NULL, -1);
2830 device_set_ivars(dinfo->cfg.dev, dinfo);
2831 resource_list_init(&dinfo->resources);
2832 pci_cfg_save(dinfo->cfg.dev, dinfo, 0);
2833 pci_cfg_restore(dinfo->cfg.dev, dinfo);
2834 pci_print_verbose(dinfo);
2835 pci_add_resources(bus, dinfo->cfg.dev, 0, 0);
2839 pci_probe(device_t dev)
2842 device_set_desc(dev, "PCI bus");
2844 /* Allow other subclasses to override this driver. */
2845 return (BUS_PROBE_GENERIC);
2849 pci_attach(device_t dev)
2854 * Since there can be multiple independantly numbered PCI
2855 * busses on systems with multiple PCI domains, we can't use
2856 * the unit number to decide which bus we are probing. We ask
2857 * the parent pcib what our domain and bus numbers are.
2859 domain = pcib_get_domain(dev);
2860 busno = pcib_get_bus(dev);
2862 device_printf(dev, "domain=%d, physical bus=%d\n",
2864 pci_add_children(dev, domain, busno, sizeof(struct pci_devinfo));
2865 return (bus_generic_attach(dev));
2869 pci_suspend(device_t dev)
2871 int dstate, error, i, numdevs;
2872 device_t acpi_dev, child, *devlist;
2873 struct pci_devinfo *dinfo;
2876 * Save the PCI configuration space for each child and set the
2877 * device in the appropriate power state for this sleep state.
2880 if (pci_do_power_resume)
2881 acpi_dev = devclass_get_device(devclass_find("acpi"), 0);
2882 if ((error = device_get_children(dev, &devlist, &numdevs)) != 0)
2884 for (i = 0; i < numdevs; i++) {
2886 dinfo = (struct pci_devinfo *) device_get_ivars(child);
2887 pci_cfg_save(child, dinfo, 0);
2890 /* Suspend devices before potentially powering them down. */
2891 error = bus_generic_suspend(dev);
2893 free(devlist, M_TEMP);
2898 * Always set the device to D3. If ACPI suggests a different
2899 * power state, use it instead. If ACPI is not present, the
2900 * firmware is responsible for managing device power. Skip
2901 * children who aren't attached since they are powered down
2902 * separately. Only manage type 0 devices for now.
2904 for (i = 0; acpi_dev && i < numdevs; i++) {
2906 dinfo = (struct pci_devinfo *) device_get_ivars(child);
2907 if (device_is_attached(child) && dinfo->cfg.hdrtype == 0) {
2908 dstate = PCI_POWERSTATE_D3;
2909 ACPI_PWR_FOR_SLEEP(acpi_dev, child, &dstate);
2910 pci_set_powerstate(child, dstate);
2913 free(devlist, M_TEMP);
2918 pci_resume(device_t dev)
2920 int i, numdevs, error;
2921 device_t acpi_dev, child, *devlist;
2922 struct pci_devinfo *dinfo;
2925 * Set each child to D0 and restore its PCI configuration space.
2928 if (pci_do_power_resume)
2929 acpi_dev = devclass_get_device(devclass_find("acpi"), 0);
2930 if ((error = device_get_children(dev, &devlist, &numdevs)) != 0)
2932 for (i = 0; i < numdevs; i++) {
2934 * Notify ACPI we're going to D0 but ignore the result. If
2935 * ACPI is not present, the firmware is responsible for
2936 * managing device power. Only manage type 0 devices for now.
2939 dinfo = (struct pci_devinfo *) device_get_ivars(child);
2940 if (acpi_dev && device_is_attached(child) &&
2941 dinfo->cfg.hdrtype == 0) {
2942 ACPI_PWR_FOR_SLEEP(acpi_dev, child, NULL);
2943 pci_set_powerstate(child, PCI_POWERSTATE_D0);
2946 /* Now the device is powered up, restore its config space. */
2947 pci_cfg_restore(child, dinfo);
2949 free(devlist, M_TEMP);
2950 return (bus_generic_resume(dev));
2954 pci_load_vendor_data(void)
2956 caddr_t vendordata, info;
2958 if ((vendordata = preload_search_by_type("pci_vendor_data")) != NULL) {
2959 info = preload_search_info(vendordata, MODINFO_ADDR);
2960 pci_vendordata = *(char **)info;
2961 info = preload_search_info(vendordata, MODINFO_SIZE);
2962 pci_vendordata_size = *(size_t *)info;
2963 /* terminate the database */
2964 pci_vendordata[pci_vendordata_size] = '\n';
2969 pci_driver_added(device_t dev, driver_t *driver)
2974 struct pci_devinfo *dinfo;
2978 device_printf(dev, "driver added\n");
2979 DEVICE_IDENTIFY(driver, dev);
2980 if (device_get_children(dev, &devlist, &numdevs) != 0)
2982 for (i = 0; i < numdevs; i++) {
2984 if (device_get_state(child) != DS_NOTPRESENT)
2986 dinfo = device_get_ivars(child);
2987 pci_print_verbose(dinfo);
2989 pci_printf(&dinfo->cfg, "reprobing on driver added\n");
2990 pci_cfg_restore(child, dinfo);
2991 if (device_probe_and_attach(child) != 0)
2992 pci_cfg_save(child, dinfo, 1);
2994 free(devlist, M_TEMP);
2998 pci_setup_intr(device_t dev, device_t child, struct resource *irq, int flags,
2999 driver_filter_t *filter, driver_intr_t *intr, void *arg, void **cookiep)
3001 struct pci_devinfo *dinfo;
3002 struct msix_table_entry *mte;
3003 struct msix_vector *mv;
3009 error = bus_generic_setup_intr(dev, child, irq, flags, filter, intr,
3014 /* If this is not a direct child, just bail out. */
3015 if (device_get_parent(child) != dev) {
3020 rid = rman_get_rid(irq);
3022 /* Make sure that INTx is enabled */
3023 pci_clear_command_bit(dev, child, PCIM_CMD_INTxDIS);
3026 * Check to see if the interrupt is MSI or MSI-X.
3027 * Ask our parent to map the MSI and give
3028 * us the address and data register values.
3029 * If we fail for some reason, teardown the
3030 * interrupt handler.
3032 dinfo = device_get_ivars(child);
3033 if (dinfo->cfg.msi.msi_alloc > 0) {
3034 if (dinfo->cfg.msi.msi_addr == 0) {
3035 KASSERT(dinfo->cfg.msi.msi_handlers == 0,
3036 ("MSI has handlers, but vectors not mapped"));
3037 error = PCIB_MAP_MSI(device_get_parent(dev),
3038 child, rman_get_start(irq), &addr, &data);
3041 dinfo->cfg.msi.msi_addr = addr;
3042 dinfo->cfg.msi.msi_data = data;
3044 if (dinfo->cfg.msi.msi_handlers == 0)
3045 pci_enable_msi(child, dinfo->cfg.msi.msi_addr,
3046 dinfo->cfg.msi.msi_data);
3047 dinfo->cfg.msi.msi_handlers++;
3049 KASSERT(dinfo->cfg.msix.msix_alloc > 0,
3050 ("No MSI or MSI-X interrupts allocated"));
3051 KASSERT(rid <= dinfo->cfg.msix.msix_table_len,
3052 ("MSI-X index too high"));
3053 mte = &dinfo->cfg.msix.msix_table[rid - 1];
3054 KASSERT(mte->mte_vector != 0, ("no message vector"));
3055 mv = &dinfo->cfg.msix.msix_vectors[mte->mte_vector - 1];
3056 KASSERT(mv->mv_irq == rman_get_start(irq),
3058 if (mv->mv_address == 0) {
3059 KASSERT(mte->mte_handlers == 0,
3060 ("MSI-X table entry has handlers, but vector not mapped"));
3061 error = PCIB_MAP_MSI(device_get_parent(dev),
3062 child, rman_get_start(irq), &addr, &data);
3065 mv->mv_address = addr;
3068 if (mte->mte_handlers == 0) {
3069 pci_enable_msix(child, rid - 1, mv->mv_address,
3071 pci_unmask_msix(child, rid - 1);
3073 mte->mte_handlers++;
3076 /* Make sure that INTx is disabled if we are using MSI/MSIX */
3077 pci_set_command_bit(dev, child, PCIM_CMD_INTxDIS);
3080 (void)bus_generic_teardown_intr(dev, child, irq,
3090 pci_teardown_intr(device_t dev, device_t child, struct resource *irq,
3093 struct msix_table_entry *mte;
3094 struct resource_list_entry *rle;
3095 struct pci_devinfo *dinfo;
3098 if (irq == NULL || !(rman_get_flags(irq) & RF_ACTIVE))
3101 /* If this isn't a direct child, just bail out */
3102 if (device_get_parent(child) != dev)
3103 return(bus_generic_teardown_intr(dev, child, irq, cookie));
3105 rid = rman_get_rid(irq);
3108 pci_set_command_bit(dev, child, PCIM_CMD_INTxDIS);
3111 * Check to see if the interrupt is MSI or MSI-X. If so,
3112 * decrement the appropriate handlers count and mask the
3113 * MSI-X message, or disable MSI messages if the count
3116 dinfo = device_get_ivars(child);
3117 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, rid);
3118 if (rle->res != irq)
3120 if (dinfo->cfg.msi.msi_alloc > 0) {
3121 KASSERT(rid <= dinfo->cfg.msi.msi_alloc,
3122 ("MSI-X index too high"));
3123 if (dinfo->cfg.msi.msi_handlers == 0)
3125 dinfo->cfg.msi.msi_handlers--;
3126 if (dinfo->cfg.msi.msi_handlers == 0)
3127 pci_disable_msi(child);
3129 KASSERT(dinfo->cfg.msix.msix_alloc > 0,
3130 ("No MSI or MSI-X interrupts allocated"));
3131 KASSERT(rid <= dinfo->cfg.msix.msix_table_len,
3132 ("MSI-X index too high"));
3133 mte = &dinfo->cfg.msix.msix_table[rid - 1];
3134 if (mte->mte_handlers == 0)
3136 mte->mte_handlers--;
3137 if (mte->mte_handlers == 0)
3138 pci_mask_msix(child, rid - 1);
3141 error = bus_generic_teardown_intr(dev, child, irq, cookie);
3144 ("%s: generic teardown failed for MSI/MSI-X", __func__));
3149 pci_print_child(device_t dev, device_t child)
3151 struct pci_devinfo *dinfo;
3152 struct resource_list *rl;
3155 dinfo = device_get_ivars(child);
3156 rl = &dinfo->resources;
3158 retval += bus_print_child_header(dev, child);
3160 retval += resource_list_print_type(rl, "port", SYS_RES_IOPORT, "%#lx");
3161 retval += resource_list_print_type(rl, "mem", SYS_RES_MEMORY, "%#lx");
3162 retval += resource_list_print_type(rl, "irq", SYS_RES_IRQ, "%ld");
3163 if (device_get_flags(dev))
3164 retval += printf(" flags %#x", device_get_flags(dev));
3166 retval += printf(" at device %d.%d", pci_get_slot(child),
3167 pci_get_function(child));
3169 retval += bus_print_child_footer(dev, child);
3179 } pci_nomatch_tab[] = {
3180 {PCIC_OLD, -1, "old"},
3181 {PCIC_OLD, PCIS_OLD_NONVGA, "non-VGA display device"},
3182 {PCIC_OLD, PCIS_OLD_VGA, "VGA-compatible display device"},
3183 {PCIC_STORAGE, -1, "mass storage"},
3184 {PCIC_STORAGE, PCIS_STORAGE_SCSI, "SCSI"},
3185 {PCIC_STORAGE, PCIS_STORAGE_IDE, "ATA"},
3186 {PCIC_STORAGE, PCIS_STORAGE_FLOPPY, "floppy disk"},
3187 {PCIC_STORAGE, PCIS_STORAGE_IPI, "IPI"},
3188 {PCIC_STORAGE, PCIS_STORAGE_RAID, "RAID"},
3189 {PCIC_STORAGE, PCIS_STORAGE_ATA_ADMA, "ATA (ADMA)"},
3190 {PCIC_STORAGE, PCIS_STORAGE_SATA, "SATA"},
3191 {PCIC_STORAGE, PCIS_STORAGE_SAS, "SAS"},
3192 {PCIC_NETWORK, -1, "network"},
3193 {PCIC_NETWORK, PCIS_NETWORK_ETHERNET, "ethernet"},
3194 {PCIC_NETWORK, PCIS_NETWORK_TOKENRING, "token ring"},
3195 {PCIC_NETWORK, PCIS_NETWORK_FDDI, "fddi"},
3196 {PCIC_NETWORK, PCIS_NETWORK_ATM, "ATM"},
3197 {PCIC_NETWORK, PCIS_NETWORK_ISDN, "ISDN"},
3198 {PCIC_DISPLAY, -1, "display"},
3199 {PCIC_DISPLAY, PCIS_DISPLAY_VGA, "VGA"},
3200 {PCIC_DISPLAY, PCIS_DISPLAY_XGA, "XGA"},
3201 {PCIC_DISPLAY, PCIS_DISPLAY_3D, "3D"},
3202 {PCIC_MULTIMEDIA, -1, "multimedia"},
3203 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_VIDEO, "video"},
3204 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_AUDIO, "audio"},
3205 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_TELE, "telephony"},
3206 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_HDA, "HDA"},
3207 {PCIC_MEMORY, -1, "memory"},
3208 {PCIC_MEMORY, PCIS_MEMORY_RAM, "RAM"},
3209 {PCIC_MEMORY, PCIS_MEMORY_FLASH, "flash"},
3210 {PCIC_BRIDGE, -1, "bridge"},
3211 {PCIC_BRIDGE, PCIS_BRIDGE_HOST, "HOST-PCI"},
3212 {PCIC_BRIDGE, PCIS_BRIDGE_ISA, "PCI-ISA"},
3213 {PCIC_BRIDGE, PCIS_BRIDGE_EISA, "PCI-EISA"},
3214 {PCIC_BRIDGE, PCIS_BRIDGE_MCA, "PCI-MCA"},
3215 {PCIC_BRIDGE, PCIS_BRIDGE_PCI, "PCI-PCI"},
3216 {PCIC_BRIDGE, PCIS_BRIDGE_PCMCIA, "PCI-PCMCIA"},
3217 {PCIC_BRIDGE, PCIS_BRIDGE_NUBUS, "PCI-NuBus"},
3218 {PCIC_BRIDGE, PCIS_BRIDGE_CARDBUS, "PCI-CardBus"},
3219 {PCIC_BRIDGE, PCIS_BRIDGE_RACEWAY, "PCI-RACEway"},
3220 {PCIC_SIMPLECOMM, -1, "simple comms"},
3221 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_UART, "UART"}, /* could detect 16550 */
3222 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_PAR, "parallel port"},
3223 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_MULSER, "multiport serial"},
3224 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_MODEM, "generic modem"},
3225 {PCIC_BASEPERIPH, -1, "base peripheral"},
3226 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_PIC, "interrupt controller"},
3227 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_DMA, "DMA controller"},
3228 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_TIMER, "timer"},
3229 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_RTC, "realtime clock"},
3230 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_PCIHOT, "PCI hot-plug controller"},
3231 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_SDHC, "SD host controller"},
3232 {PCIC_INPUTDEV, -1, "input device"},
3233 {PCIC_INPUTDEV, PCIS_INPUTDEV_KEYBOARD, "keyboard"},
3234 {PCIC_INPUTDEV, PCIS_INPUTDEV_DIGITIZER,"digitizer"},
3235 {PCIC_INPUTDEV, PCIS_INPUTDEV_MOUSE, "mouse"},
3236 {PCIC_INPUTDEV, PCIS_INPUTDEV_SCANNER, "scanner"},
3237 {PCIC_INPUTDEV, PCIS_INPUTDEV_GAMEPORT, "gameport"},
3238 {PCIC_DOCKING, -1, "docking station"},
3239 {PCIC_PROCESSOR, -1, "processor"},
3240 {PCIC_SERIALBUS, -1, "serial bus"},
3241 {PCIC_SERIALBUS, PCIS_SERIALBUS_FW, "FireWire"},
3242 {PCIC_SERIALBUS, PCIS_SERIALBUS_ACCESS, "AccessBus"},
3243 {PCIC_SERIALBUS, PCIS_SERIALBUS_SSA, "SSA"},
3244 {PCIC_SERIALBUS, PCIS_SERIALBUS_USB, "USB"},
3245 {PCIC_SERIALBUS, PCIS_SERIALBUS_FC, "Fibre Channel"},
3246 {PCIC_SERIALBUS, PCIS_SERIALBUS_SMBUS, "SMBus"},
3247 {PCIC_WIRELESS, -1, "wireless controller"},
3248 {PCIC_WIRELESS, PCIS_WIRELESS_IRDA, "iRDA"},
3249 {PCIC_WIRELESS, PCIS_WIRELESS_IR, "IR"},
3250 {PCIC_WIRELESS, PCIS_WIRELESS_RF, "RF"},
3251 {PCIC_INTELLIIO, -1, "intelligent I/O controller"},
3252 {PCIC_INTELLIIO, PCIS_INTELLIIO_I2O, "I2O"},
3253 {PCIC_SATCOM, -1, "satellite communication"},
3254 {PCIC_SATCOM, PCIS_SATCOM_TV, "sat TV"},
3255 {PCIC_SATCOM, PCIS_SATCOM_AUDIO, "sat audio"},
3256 {PCIC_SATCOM, PCIS_SATCOM_VOICE, "sat voice"},
3257 {PCIC_SATCOM, PCIS_SATCOM_DATA, "sat data"},
3258 {PCIC_CRYPTO, -1, "encrypt/decrypt"},
3259 {PCIC_CRYPTO, PCIS_CRYPTO_NETCOMP, "network/computer crypto"},
3260 {PCIC_CRYPTO, PCIS_CRYPTO_ENTERTAIN, "entertainment crypto"},
3261 {PCIC_DASP, -1, "dasp"},
3262 {PCIC_DASP, PCIS_DASP_DPIO, "DPIO module"},
3267 pci_probe_nomatch(device_t dev, device_t child)
3270 char *cp, *scp, *device;
3273 * Look for a listing for this device in a loaded device database.
3275 if ((device = pci_describe_device(child)) != NULL) {
3276 device_printf(dev, "<%s>", device);
3277 free(device, M_DEVBUF);
3280 * Scan the class/subclass descriptions for a general
3285 for (i = 0; pci_nomatch_tab[i].desc != NULL; i++) {
3286 if (pci_nomatch_tab[i].class == pci_get_class(child)) {
3287 if (pci_nomatch_tab[i].subclass == -1) {
3288 cp = pci_nomatch_tab[i].desc;
3289 } else if (pci_nomatch_tab[i].subclass ==
3290 pci_get_subclass(child)) {
3291 scp = pci_nomatch_tab[i].desc;
3295 device_printf(dev, "<%s%s%s>",
3297 ((cp != NULL) && (scp != NULL)) ? ", " : "",
3300 printf(" at device %d.%d (no driver attached)\n",
3301 pci_get_slot(child), pci_get_function(child));
3302 pci_cfg_save(child, (struct pci_devinfo *)device_get_ivars(child), 1);
3307 * Parse the PCI device database, if loaded, and return a pointer to a
3308 * description of the device.
3310 * The database is flat text formatted as follows:
3312 * Any line not in a valid format is ignored.
3313 * Lines are terminated with newline '\n' characters.
3315 * A VENDOR line consists of the 4 digit (hex) vendor code, a TAB, then
3318 * A DEVICE line is entered immediately below the corresponding VENDOR ID.
3319 * - devices cannot be listed without a corresponding VENDOR line.
3320 * A DEVICE line consists of a TAB, the 4 digit (hex) device code,
3321 * another TAB, then the device name.
3325 * Assuming (ptr) points to the beginning of a line in the database,
3326 * return the vendor or device and description of the next entry.
3327 * The value of (vendor) or (device) inappropriate for the entry type
3328 * is set to -1. Returns nonzero at the end of the database.
3330 * Note that this is slightly unrobust in the face of corrupt data;
3331 * we attempt to safeguard against this by spamming the end of the
3332 * database with a newline when we initialise.
3335 pci_describe_parse_line(char **ptr, int *vendor, int *device, char **desc)
3344 left = pci_vendordata_size - (cp - pci_vendordata);
3352 sscanf(cp, "%x\t%80[^\n]", vendor, *desc) == 2)
3356 sscanf(cp, "%x\t%80[^\n]", device, *desc) == 2)
3359 /* skip to next line */
3360 while (*cp != '\n' && left > 0) {
3369 /* skip to next line */
3370 while (*cp != '\n' && left > 0) {
3374 if (*cp == '\n' && left > 0)
3381 pci_describe_device(device_t dev)
3384 char *desc, *vp, *dp, *line;
3386 desc = vp = dp = NULL;
3389 * If we have no vendor data, we can't do anything.
3391 if (pci_vendordata == NULL)
3395 * Scan the vendor data looking for this device
3397 line = pci_vendordata;
3398 if ((vp = malloc(80, M_DEVBUF, M_NOWAIT)) == NULL)
3401 if (pci_describe_parse_line(&line, &vendor, &device, &vp))
3403 if (vendor == pci_get_vendor(dev))
3406 if ((dp = malloc(80, M_DEVBUF, M_NOWAIT)) == NULL)
3409 if (pci_describe_parse_line(&line, &vendor, &device, &dp)) {
3417 if (device == pci_get_device(dev))
3421 snprintf(dp, 80, "0x%x", pci_get_device(dev));
3422 if ((desc = malloc(strlen(vp) + strlen(dp) + 3, M_DEVBUF, M_NOWAIT)) !=
3424 sprintf(desc, "%s, %s", vp, dp);
3434 pci_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
3436 struct pci_devinfo *dinfo;
3439 dinfo = device_get_ivars(child);
3443 case PCI_IVAR_ETHADDR:
3445 * The generic accessor doesn't deal with failure, so
3446 * we set the return value, then return an error.
3448 *((uint8_t **) result) = NULL;
3450 case PCI_IVAR_SUBVENDOR:
3451 *result = cfg->subvendor;
3453 case PCI_IVAR_SUBDEVICE:
3454 *result = cfg->subdevice;
3456 case PCI_IVAR_VENDOR:
3457 *result = cfg->vendor;
3459 case PCI_IVAR_DEVICE:
3460 *result = cfg->device;
3462 case PCI_IVAR_DEVID:
3463 *result = (cfg->device << 16) | cfg->vendor;
3465 case PCI_IVAR_CLASS:
3466 *result = cfg->baseclass;
3468 case PCI_IVAR_SUBCLASS:
3469 *result = cfg->subclass;
3471 case PCI_IVAR_PROGIF:
3472 *result = cfg->progif;
3474 case PCI_IVAR_REVID:
3475 *result = cfg->revid;
3477 case PCI_IVAR_INTPIN:
3478 *result = cfg->intpin;
3481 *result = cfg->intline;
3483 case PCI_IVAR_DOMAIN:
3484 *result = cfg->domain;
3490 *result = cfg->slot;
3492 case PCI_IVAR_FUNCTION:
3493 *result = cfg->func;
3495 case PCI_IVAR_CMDREG:
3496 *result = cfg->cmdreg;
3498 case PCI_IVAR_CACHELNSZ:
3499 *result = cfg->cachelnsz;
3501 case PCI_IVAR_MINGNT:
3502 *result = cfg->mingnt;
3504 case PCI_IVAR_MAXLAT:
3505 *result = cfg->maxlat;
3507 case PCI_IVAR_LATTIMER:
3508 *result = cfg->lattimer;
3517 pci_write_ivar(device_t dev, device_t child, int which, uintptr_t value)
3519 struct pci_devinfo *dinfo;
3521 dinfo = device_get_ivars(child);
3524 case PCI_IVAR_INTPIN:
3525 dinfo->cfg.intpin = value;
3527 case PCI_IVAR_ETHADDR:
3528 case PCI_IVAR_SUBVENDOR:
3529 case PCI_IVAR_SUBDEVICE:
3530 case PCI_IVAR_VENDOR:
3531 case PCI_IVAR_DEVICE:
3532 case PCI_IVAR_DEVID:
3533 case PCI_IVAR_CLASS:
3534 case PCI_IVAR_SUBCLASS:
3535 case PCI_IVAR_PROGIF:
3536 case PCI_IVAR_REVID:
3538 case PCI_IVAR_DOMAIN:
3541 case PCI_IVAR_FUNCTION:
3542 return (EINVAL); /* disallow for now */
3550 #include "opt_ddb.h"
3552 #include <ddb/ddb.h>
3553 #include <sys/cons.h>
3556 * List resources based on pci map registers, used for within ddb
3559 DB_SHOW_COMMAND(pciregs, db_pci_dump)
3561 struct pci_devinfo *dinfo;
3562 struct devlist *devlist_head;
3565 int i, error, none_count;
3568 /* get the head of the device queue */
3569 devlist_head = &pci_devq;
3572 * Go through the list of devices and print out devices
3574 for (error = 0, i = 0,
3575 dinfo = STAILQ_FIRST(devlist_head);
3576 (dinfo != NULL) && (error == 0) && (i < pci_numdevs) && !db_pager_quit;
3577 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) {
3579 /* Populate pd_name and pd_unit */
3582 name = device_get_name(dinfo->cfg.dev);
3585 db_printf("%s%d@pci%d:%d:%d:%d:\tclass=0x%06x card=0x%08x "
3586 "chip=0x%08x rev=0x%02x hdr=0x%02x\n",
3587 (name && *name) ? name : "none",
3588 (name && *name) ? (int)device_get_unit(dinfo->cfg.dev) :
3590 p->pc_sel.pc_domain, p->pc_sel.pc_bus, p->pc_sel.pc_dev,
3591 p->pc_sel.pc_func, (p->pc_class << 16) |
3592 (p->pc_subclass << 8) | p->pc_progif,
3593 (p->pc_subdevice << 16) | p->pc_subvendor,
3594 (p->pc_device << 16) | p->pc_vendor,
3595 p->pc_revid, p->pc_hdr);
3600 static struct resource *
3601 pci_alloc_map(device_t dev, device_t child, int type, int *rid,
3602 u_long start, u_long end, u_long count, u_int flags)
3604 struct pci_devinfo *dinfo = device_get_ivars(child);
3605 struct resource_list *rl = &dinfo->resources;
3606 struct resource_list_entry *rle;
3607 struct resource *res;
3608 pci_addr_t map, testval;
3612 * Weed out the bogons, and figure out how large the BAR/map
3613 * is. Bars that read back 0 here are bogus and unimplemented.
3614 * Note: atapci in legacy mode are special and handled elsewhere
3615 * in the code. If you have a atapci device in legacy mode and
3616 * it fails here, that other code is broken.
3619 pci_read_bar(child, *rid, &map, &testval);
3621 /* Ignore a BAR with a base of 0. */
3622 if (pci_mapbase(testval) == 0)
3625 if (PCI_BAR_MEM(testval)) {
3626 if (type != SYS_RES_MEMORY) {
3629 "child %s requested type %d for rid %#x,"
3630 " but the BAR says it is an memio\n",
3631 device_get_nameunit(child), type, *rid);
3635 if (type != SYS_RES_IOPORT) {
3638 "child %s requested type %d for rid %#x,"
3639 " but the BAR says it is an ioport\n",
3640 device_get_nameunit(child), type, *rid);
3646 * For real BARs, we need to override the size that
3647 * the driver requests, because that's what the BAR
3648 * actually uses and we would otherwise have a
3649 * situation where we might allocate the excess to
3650 * another driver, which won't work.
3652 mapsize = pci_mapsize(testval);
3653 count = 1UL << mapsize;
3654 if (RF_ALIGNMENT(flags) < mapsize)
3655 flags = (flags & ~RF_ALIGNMENT_MASK) | RF_ALIGNMENT_LOG2(mapsize);
3656 if (PCI_BAR_MEM(testval) && (testval & PCIM_BAR_MEM_PREFETCH))
3657 flags |= RF_PREFETCHABLE;
3660 * Allocate enough resource, and then write back the
3661 * appropriate bar for that resource.
3663 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), child, type, rid,
3664 start, end, count, flags & ~RF_ACTIVE);
3666 device_printf(child,
3667 "%#lx bytes of rid %#x res %d failed (%#lx, %#lx).\n",
3668 count, *rid, type, start, end);
3671 rman_set_device(res, dev);
3672 resource_list_add(rl, type, *rid, start, end, count);
3673 rle = resource_list_find(rl, type, *rid);
3675 panic("pci_alloc_map: unexpectedly can't find resource.");
3677 rle->start = rman_get_start(res);
3678 rle->end = rman_get_end(res);
3681 device_printf(child,
3682 "Lazy allocation of %#lx bytes rid %#x type %d at %#lx\n",
3683 count, *rid, type, rman_get_start(res));
3684 map = rman_get_start(res);
3685 pci_write_bar(child, *rid, map);
3692 pci_alloc_resource(device_t dev, device_t child, int type, int *rid,
3693 u_long start, u_long end, u_long count, u_int flags)
3695 struct pci_devinfo *dinfo = device_get_ivars(child);
3696 struct resource_list *rl = &dinfo->resources;
3697 struct resource_list_entry *rle;
3698 struct resource *res;
3699 pcicfgregs *cfg = &dinfo->cfg;
3701 if (device_get_parent(child) != dev)
3702 return (BUS_ALLOC_RESOURCE(device_get_parent(dev), child,
3703 type, rid, start, end, count, flags));
3706 * Perform lazy resource allocation
3711 * Can't alloc legacy interrupt once MSI messages have
3714 if (*rid == 0 && (cfg->msi.msi_alloc > 0 ||
3715 cfg->msix.msix_alloc > 0))
3719 * If the child device doesn't have an interrupt
3720 * routed and is deserving of an interrupt, try to
3723 if (*rid == 0 && !PCI_INTERRUPT_VALID(cfg->intline) &&
3725 pci_assign_interrupt(dev, child, 0);
3727 case SYS_RES_IOPORT:
3728 case SYS_RES_MEMORY:
3729 /* Allocate resources for this BAR if needed. */
3730 rle = resource_list_find(rl, type, *rid);
3732 res = pci_alloc_map(dev, child, type, rid, start, end,
3736 rle = resource_list_find(rl, type, *rid);
3740 * If the resource belongs to the bus, then give it to
3741 * the child. We need to activate it if requested
3742 * since the bus always allocates inactive resources.
3744 if (rle != NULL && rle->res != NULL &&
3745 rman_get_device(rle->res) == dev) {
3747 device_printf(child,
3748 "Reserved %#lx bytes for rid %#x type %d at %#lx\n",
3749 rman_get_size(rle->res), *rid, type,
3750 rman_get_start(rle->res));
3751 rman_set_device(rle->res, child);
3752 if ((flags & RF_ACTIVE) &&
3753 bus_activate_resource(child, type, *rid,
3759 return (resource_list_alloc(rl, dev, child, type, rid,
3760 start, end, count, flags));
3764 pci_release_resource(device_t dev, device_t child, int type, int rid,
3769 if (device_get_parent(child) != dev)
3770 return (BUS_RELEASE_RESOURCE(device_get_parent(dev), child,
3774 * For BARs we don't actually want to release the resource.
3775 * Instead, we deactivate the resource if needed and then give
3776 * ownership of the BAR back to the bus.
3779 case SYS_RES_IOPORT:
3780 case SYS_RES_MEMORY:
3781 if (rman_get_device(r) != child)
3783 if (rman_get_flags(r) & RF_ACTIVE) {
3784 error = bus_deactivate_resource(child, type, rid, r);
3788 rman_set_device(r, dev);
3791 return (bus_generic_rl_release_resource(dev, child, type, rid, r));
3795 pci_activate_resource(device_t dev, device_t child, int type, int rid,
3800 error = bus_generic_activate_resource(dev, child, type, rid, r);
3804 /* Enable decoding in the command register when activating BARs. */
3805 if (device_get_parent(child) == dev) {
3807 case SYS_RES_IOPORT:
3808 case SYS_RES_MEMORY:
3809 error = PCI_ENABLE_IO(dev, child, type);
3817 pci_delete_resource(device_t dev, device_t child, int type, int rid)
3819 struct pci_devinfo *dinfo;
3820 struct resource_list *rl;
3821 struct resource_list_entry *rle;
3823 if (device_get_parent(child) != dev)
3826 dinfo = device_get_ivars(child);
3827 rl = &dinfo->resources;
3828 rle = resource_list_find(rl, type, rid);
3833 if (rman_get_device(rle->res) != dev ||
3834 rman_get_flags(rle->res) & RF_ACTIVE) {
3835 device_printf(dev, "delete_resource: "
3836 "Resource still owned by child, oops. "
3837 "(type=%d, rid=%d, addr=%lx)\n",
3838 rle->type, rle->rid,
3839 rman_get_start(rle->res));
3843 #ifndef __PCI_BAR_ZERO_VALID
3845 * If this is a BAR, clear the BAR so it stops
3846 * decoding before releasing the resource.
3849 case SYS_RES_IOPORT:
3850 case SYS_RES_MEMORY:
3851 pci_write_bar(child, rid, 0);
3855 bus_release_resource(dev, type, rid, rle->res);
3857 resource_list_delete(rl, type, rid);
3860 struct resource_list *
3861 pci_get_resource_list (device_t dev, device_t child)
3863 struct pci_devinfo *dinfo = device_get_ivars(child);
3865 return (&dinfo->resources);
3869 pci_read_config_method(device_t dev, device_t child, int reg, int width)
3871 struct pci_devinfo *dinfo = device_get_ivars(child);
3872 pcicfgregs *cfg = &dinfo->cfg;
3874 return (PCIB_READ_CONFIG(device_get_parent(dev),
3875 cfg->bus, cfg->slot, cfg->func, reg, width));
3879 pci_write_config_method(device_t dev, device_t child, int reg,
3880 uint32_t val, int width)
3882 struct pci_devinfo *dinfo = device_get_ivars(child);
3883 pcicfgregs *cfg = &dinfo->cfg;
3885 PCIB_WRITE_CONFIG(device_get_parent(dev),
3886 cfg->bus, cfg->slot, cfg->func, reg, val, width);
3890 pci_child_location_str_method(device_t dev, device_t child, char *buf,
3894 snprintf(buf, buflen, "slot=%d function=%d", pci_get_slot(child),
3895 pci_get_function(child));
3900 pci_child_pnpinfo_str_method(device_t dev, device_t child, char *buf,
3903 struct pci_devinfo *dinfo;
3906 dinfo = device_get_ivars(child);
3908 snprintf(buf, buflen, "vendor=0x%04x device=0x%04x subvendor=0x%04x "
3909 "subdevice=0x%04x class=0x%02x%02x%02x", cfg->vendor, cfg->device,
3910 cfg->subvendor, cfg->subdevice, cfg->baseclass, cfg->subclass,
3916 pci_assign_interrupt_method(device_t dev, device_t child)
3918 struct pci_devinfo *dinfo = device_get_ivars(child);
3919 pcicfgregs *cfg = &dinfo->cfg;
3921 return (PCIB_ROUTE_INTERRUPT(device_get_parent(dev), child,
3926 pci_modevent(module_t mod, int what, void *arg)
3928 static struct cdev *pci_cdev;
3932 STAILQ_INIT(&pci_devq);
3934 pci_cdev = make_dev(&pcicdev, 0, UID_ROOT, GID_WHEEL, 0644,
3936 pci_load_vendor_data();
3940 destroy_dev(pci_cdev);
3948 pci_cfg_restore(device_t dev, struct pci_devinfo *dinfo)
3953 * Only do header type 0 devices. Type 1 devices are bridges,
3954 * which we know need special treatment. Type 2 devices are
3955 * cardbus bridges which also require special treatment.
3956 * Other types are unknown, and we err on the side of safety
3959 if (dinfo->cfg.hdrtype != 0)
3963 * Restore the device to full power mode. We must do this
3964 * before we restore the registers because moving from D3 to
3965 * D0 will cause the chip's BARs and some other registers to
3966 * be reset to some unknown power on reset values. Cut down
3967 * the noise on boot by doing nothing if we are already in
3970 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
3971 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
3973 for (i = 0; i < dinfo->cfg.nummaps; i++)
3974 pci_write_config(dev, PCIR_BAR(i), dinfo->cfg.bar[i], 4);
3975 pci_write_config(dev, PCIR_BIOS, dinfo->cfg.bios, 4);
3976 pci_write_config(dev, PCIR_COMMAND, dinfo->cfg.cmdreg, 2);
3977 pci_write_config(dev, PCIR_INTLINE, dinfo->cfg.intline, 1);
3978 pci_write_config(dev, PCIR_INTPIN, dinfo->cfg.intpin, 1);
3979 pci_write_config(dev, PCIR_MINGNT, dinfo->cfg.mingnt, 1);
3980 pci_write_config(dev, PCIR_MAXLAT, dinfo->cfg.maxlat, 1);
3981 pci_write_config(dev, PCIR_CACHELNSZ, dinfo->cfg.cachelnsz, 1);
3982 pci_write_config(dev, PCIR_LATTIMER, dinfo->cfg.lattimer, 1);
3983 pci_write_config(dev, PCIR_PROGIF, dinfo->cfg.progif, 1);
3984 pci_write_config(dev, PCIR_REVID, dinfo->cfg.revid, 1);
3986 /* Restore MSI and MSI-X configurations if they are present. */
3987 if (dinfo->cfg.msi.msi_location != 0)
3988 pci_resume_msi(dev);
3989 if (dinfo->cfg.msix.msix_location != 0)
3990 pci_resume_msix(dev);
3994 pci_cfg_save(device_t dev, struct pci_devinfo *dinfo, int setstate)
4001 * Only do header type 0 devices. Type 1 devices are bridges, which
4002 * we know need special treatment. Type 2 devices are cardbus bridges
4003 * which also require special treatment. Other types are unknown, and
4004 * we err on the side of safety by ignoring them. Powering down
4005 * bridges should not be undertaken lightly.
4007 if (dinfo->cfg.hdrtype != 0)
4009 for (i = 0; i < dinfo->cfg.nummaps; i++)
4010 dinfo->cfg.bar[i] = pci_read_config(dev, PCIR_BAR(i), 4);
4011 dinfo->cfg.bios = pci_read_config(dev, PCIR_BIOS, 4);
4014 * Some drivers apparently write to these registers w/o updating our
4015 * cached copy. No harm happens if we update the copy, so do so here
4016 * so we can restore them. The COMMAND register is modified by the
4017 * bus w/o updating the cache. This should represent the normally
4018 * writable portion of the 'defined' part of type 0 headers. In
4019 * theory we also need to save/restore the PCI capability structures
4020 * we know about, but apart from power we don't know any that are
4023 dinfo->cfg.subvendor = pci_read_config(dev, PCIR_SUBVEND_0, 2);
4024 dinfo->cfg.subdevice = pci_read_config(dev, PCIR_SUBDEV_0, 2);
4025 dinfo->cfg.vendor = pci_read_config(dev, PCIR_VENDOR, 2);
4026 dinfo->cfg.device = pci_read_config(dev, PCIR_DEVICE, 2);
4027 dinfo->cfg.cmdreg = pci_read_config(dev, PCIR_COMMAND, 2);
4028 dinfo->cfg.intline = pci_read_config(dev, PCIR_INTLINE, 1);
4029 dinfo->cfg.intpin = pci_read_config(dev, PCIR_INTPIN, 1);
4030 dinfo->cfg.mingnt = pci_read_config(dev, PCIR_MINGNT, 1);
4031 dinfo->cfg.maxlat = pci_read_config(dev, PCIR_MAXLAT, 1);
4032 dinfo->cfg.cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1);
4033 dinfo->cfg.lattimer = pci_read_config(dev, PCIR_LATTIMER, 1);
4034 dinfo->cfg.baseclass = pci_read_config(dev, PCIR_CLASS, 1);
4035 dinfo->cfg.subclass = pci_read_config(dev, PCIR_SUBCLASS, 1);
4036 dinfo->cfg.progif = pci_read_config(dev, PCIR_PROGIF, 1);
4037 dinfo->cfg.revid = pci_read_config(dev, PCIR_REVID, 1);
4040 * don't set the state for display devices, base peripherals and
4041 * memory devices since bad things happen when they are powered down.
4042 * We should (a) have drivers that can easily detach and (b) use
4043 * generic drivers for these devices so that some device actually
4044 * attaches. We need to make sure that when we implement (a) we don't
4045 * power the device down on a reattach.
4047 cls = pci_get_class(dev);
4050 switch (pci_do_power_nodriver)
4052 case 0: /* NO powerdown at all */
4054 case 1: /* Conservative about what to power down */
4055 if (cls == PCIC_STORAGE)
4058 case 2: /* Agressive about what to power down */
4059 if (cls == PCIC_DISPLAY || cls == PCIC_MEMORY ||
4060 cls == PCIC_BASEPERIPH)
4063 case 3: /* Power down everything */
4067 * PCI spec says we can only go into D3 state from D0 state.
4068 * Transition from D[12] into D0 before going to D3 state.
4070 ps = pci_get_powerstate(dev);
4071 if (ps != PCI_POWERSTATE_D0 && ps != PCI_POWERSTATE_D3)
4072 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
4073 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D3)
4074 pci_set_powerstate(dev, PCI_POWERSTATE_D3);