1 /* $NetBSD: if_stge.c,v 1.32 2005/12/11 12:22:49 christos Exp $ */
4 * Copyright (c) 2001 The NetBSD Foundation, Inc.
7 * This code is derived from software contributed to The NetBSD Foundation
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 * 3. All advertising materials mentioning features or use of this software
19 * must display the following acknowledgement:
20 * This product includes software developed by the NetBSD
21 * Foundation, Inc. and its contributors.
22 * 4. Neither the name of The NetBSD Foundation nor the names of its
23 * contributors may be used to endorse or promote products derived
24 * from this software without specific prior written permission.
26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
36 * POSSIBILITY OF SUCH DAMAGE.
40 * Device driver for the Sundance Tech. TC9021 10/100/1000
41 * Ethernet controller.
44 #include <sys/cdefs.h>
45 __FBSDID("$FreeBSD$");
47 #ifdef HAVE_KERNEL_OPTION_HEADERS
48 #include "opt_device_polling.h"
51 #include <sys/param.h>
52 #include <sys/systm.h>
53 #include <sys/endian.h>
55 #include <sys/malloc.h>
56 #include <sys/kernel.h>
57 #include <sys/module.h>
58 #include <sys/socket.h>
59 #include <sys/sockio.h>
60 #include <sys/sysctl.h>
61 #include <sys/taskqueue.h>
64 #include <net/ethernet.h>
66 #include <net/if_dl.h>
67 #include <net/if_media.h>
68 #include <net/if_types.h>
69 #include <net/if_vlan_var.h>
71 #include <machine/bus.h>
72 #include <machine/resource.h>
76 #include <dev/mii/mii.h>
77 #include <dev/mii/miivar.h>
79 #include <dev/pci/pcireg.h>
80 #include <dev/pci/pcivar.h>
82 #include <dev/stge/if_stgereg.h>
84 #define STGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
86 MODULE_DEPEND(stge, pci, 1, 1, 1);
87 MODULE_DEPEND(stge, ether, 1, 1, 1);
88 MODULE_DEPEND(stge, miibus, 1, 1, 1);
90 /* "device miibus" required. See GENERIC if you get errors here. */
91 #include "miibus_if.h"
94 * Devices supported by this driver.
96 static struct stge_product {
97 uint16_t stge_vendorid;
98 uint16_t stge_deviceid;
99 const char *stge_name;
100 } stge_products[] = {
101 { VENDOR_SUNDANCETI, DEVICEID_SUNDANCETI_ST1023,
102 "Sundance ST-1023 Gigabit Ethernet" },
104 { VENDOR_SUNDANCETI, DEVICEID_SUNDANCETI_ST2021,
105 "Sundance ST-2021 Gigabit Ethernet" },
107 { VENDOR_TAMARACK, DEVICEID_TAMARACK_TC9021,
108 "Tamarack TC9021 Gigabit Ethernet" },
110 { VENDOR_TAMARACK, DEVICEID_TAMARACK_TC9021_ALT,
111 "Tamarack TC9021 Gigabit Ethernet" },
114 * The Sundance sample boards use the Sundance vendor ID,
115 * but the Tamarack product ID.
117 { VENDOR_SUNDANCETI, DEVICEID_TAMARACK_TC9021,
118 "Sundance TC9021 Gigabit Ethernet" },
120 { VENDOR_SUNDANCETI, DEVICEID_TAMARACK_TC9021_ALT,
121 "Sundance TC9021 Gigabit Ethernet" },
123 { VENDOR_DLINK, DEVICEID_DLINK_DL4000,
124 "D-Link DL-4000 Gigabit Ethernet" },
126 { VENDOR_ANTARES, DEVICEID_ANTARES_TC9021,
127 "Antares Gigabit Ethernet" }
130 static int stge_probe(device_t);
131 static int stge_attach(device_t);
132 static int stge_detach(device_t);
133 static int stge_shutdown(device_t);
134 static int stge_suspend(device_t);
135 static int stge_resume(device_t);
137 static int stge_encap(struct stge_softc *, struct mbuf **);
138 static void stge_start(struct ifnet *);
139 static void stge_start_locked(struct ifnet *);
140 static void stge_watchdog(struct stge_softc *);
141 static int stge_ioctl(struct ifnet *, u_long, caddr_t);
142 static void stge_init(void *);
143 static void stge_init_locked(struct stge_softc *);
144 static void stge_vlan_setup(struct stge_softc *);
145 static void stge_stop(struct stge_softc *);
146 static void stge_start_tx(struct stge_softc *);
147 static void stge_start_rx(struct stge_softc *);
148 static void stge_stop_tx(struct stge_softc *);
149 static void stge_stop_rx(struct stge_softc *);
151 static void stge_reset(struct stge_softc *, uint32_t);
152 static int stge_eeprom_wait(struct stge_softc *);
153 static void stge_read_eeprom(struct stge_softc *, int, uint16_t *);
154 static void stge_tick(void *);
155 static void stge_stats_update(struct stge_softc *);
156 static void stge_set_filter(struct stge_softc *);
157 static void stge_set_multi(struct stge_softc *);
159 static void stge_link_task(void *, int);
160 static void stge_intr(void *);
161 static __inline int stge_tx_error(struct stge_softc *);
162 static void stge_txeof(struct stge_softc *);
163 static int stge_rxeof(struct stge_softc *);
164 static __inline void stge_discard_rxbuf(struct stge_softc *, int);
165 static int stge_newbuf(struct stge_softc *, int);
166 #ifndef __NO_STRICT_ALIGNMENT
167 static __inline struct mbuf *stge_fixup_rx(struct stge_softc *, struct mbuf *);
170 static void stge_mii_sync(struct stge_softc *);
171 static void stge_mii_send(struct stge_softc *, uint32_t, int);
172 static int stge_mii_readreg(struct stge_softc *, struct stge_mii_frame *);
173 static int stge_mii_writereg(struct stge_softc *, struct stge_mii_frame *);
174 static int stge_miibus_readreg(device_t, int, int);
175 static int stge_miibus_writereg(device_t, int, int, int);
176 static void stge_miibus_statchg(device_t);
177 static int stge_mediachange(struct ifnet *);
178 static void stge_mediastatus(struct ifnet *, struct ifmediareq *);
180 static void stge_dmamap_cb(void *, bus_dma_segment_t *, int, int);
181 static int stge_dma_alloc(struct stge_softc *);
182 static void stge_dma_free(struct stge_softc *);
183 static void stge_dma_wait(struct stge_softc *);
184 static void stge_init_tx_ring(struct stge_softc *);
185 static int stge_init_rx_ring(struct stge_softc *);
186 #ifdef DEVICE_POLLING
187 static int stge_poll(struct ifnet *, enum poll_cmd, int);
190 static void stge_setwol(struct stge_softc *);
191 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int);
192 static int sysctl_hw_stge_rxint_nframe(SYSCTL_HANDLER_ARGS);
193 static int sysctl_hw_stge_rxint_dmawait(SYSCTL_HANDLER_ARGS);
195 static device_method_t stge_methods[] = {
196 /* Device interface */
197 DEVMETHOD(device_probe, stge_probe),
198 DEVMETHOD(device_attach, stge_attach),
199 DEVMETHOD(device_detach, stge_detach),
200 DEVMETHOD(device_shutdown, stge_shutdown),
201 DEVMETHOD(device_suspend, stge_suspend),
202 DEVMETHOD(device_resume, stge_resume),
205 DEVMETHOD(miibus_readreg, stge_miibus_readreg),
206 DEVMETHOD(miibus_writereg, stge_miibus_writereg),
207 DEVMETHOD(miibus_statchg, stge_miibus_statchg),
213 static driver_t stge_driver = {
216 sizeof(struct stge_softc)
219 static devclass_t stge_devclass;
221 DRIVER_MODULE(stge, pci, stge_driver, stge_devclass, 0, 0);
222 DRIVER_MODULE(miibus, stge, miibus_driver, miibus_devclass, 0, 0);
224 static struct resource_spec stge_res_spec_io[] = {
225 { SYS_RES_IOPORT, PCIR_BAR(0), RF_ACTIVE },
226 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE },
230 static struct resource_spec stge_res_spec_mem[] = {
231 { SYS_RES_MEMORY, PCIR_BAR(1), RF_ACTIVE },
232 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE },
237 CSR_WRITE_1(sc, STGE_PhyCtrl, CSR_READ_1(sc, STGE_PhyCtrl) | (x))
239 CSR_WRITE_1(sc, STGE_PhyCtrl, CSR_READ_1(sc, STGE_PhyCtrl) & ~(x))
242 * Sync the PHYs by setting data bit and strobing the clock 32 times.
245 stge_mii_sync(struct stge_softc *sc)
249 MII_SET(PC_MgmtDir | PC_MgmtData);
251 for (i = 0; i < 32; i++) {
260 * Clock a series of bits through the MII.
263 stge_mii_send(struct stge_softc *sc, uint32_t bits, int cnt)
269 for (i = (0x1 << (cnt - 1)); i; i >>= 1) {
271 MII_SET(PC_MgmtData);
273 MII_CLR(PC_MgmtData);
282 * Read an PHY register through the MII.
285 stge_mii_readreg(struct stge_softc *sc, struct stge_mii_frame *frame)
290 * Set up frame for RX.
292 frame->mii_stdelim = STGE_MII_STARTDELIM;
293 frame->mii_opcode = STGE_MII_READOP;
294 frame->mii_turnaround = 0;
297 CSR_WRITE_1(sc, STGE_PhyCtrl, 0 | sc->sc_PhyCtrl);
306 * Send command/address info.
308 stge_mii_send(sc, frame->mii_stdelim, 2);
309 stge_mii_send(sc, frame->mii_opcode, 2);
310 stge_mii_send(sc, frame->mii_phyaddr, 5);
311 stge_mii_send(sc, frame->mii_regaddr, 5);
317 MII_CLR((PC_MgmtClk | PC_MgmtData));
325 ack = CSR_READ_1(sc, STGE_PhyCtrl) & PC_MgmtData;
330 * Now try reading data bits. If the ack failed, we still
331 * need to clock through 16 cycles to keep the PHY(s) in sync.
334 for(i = 0; i < 16; i++) {
343 for (i = 0x8000; i; i >>= 1) {
347 if (CSR_READ_1(sc, STGE_PhyCtrl) & PC_MgmtData)
348 frame->mii_data |= i;
367 * Write to a PHY register through the MII.
370 stge_mii_writereg(struct stge_softc *sc, struct stge_mii_frame *frame)
374 * Set up frame for TX.
376 frame->mii_stdelim = STGE_MII_STARTDELIM;
377 frame->mii_opcode = STGE_MII_WRITEOP;
378 frame->mii_turnaround = STGE_MII_TURNAROUND;
381 * Turn on data output.
387 stge_mii_send(sc, frame->mii_stdelim, 2);
388 stge_mii_send(sc, frame->mii_opcode, 2);
389 stge_mii_send(sc, frame->mii_phyaddr, 5);
390 stge_mii_send(sc, frame->mii_regaddr, 5);
391 stge_mii_send(sc, frame->mii_turnaround, 2);
392 stge_mii_send(sc, frame->mii_data, 16);
409 * sc_miibus_readreg: [mii interface function]
411 * Read a PHY register on the MII of the TC9021.
414 stge_miibus_readreg(device_t dev, int phy, int reg)
416 struct stge_softc *sc;
417 struct stge_mii_frame frame;
420 sc = device_get_softc(dev);
422 if (reg == STGE_PhyCtrl) {
423 /* XXX allow ip1000phy read STGE_PhyCtrl register. */
425 error = CSR_READ_1(sc, STGE_PhyCtrl);
429 bzero(&frame, sizeof(frame));
430 frame.mii_phyaddr = phy;
431 frame.mii_regaddr = reg;
434 error = stge_mii_readreg(sc, &frame);
438 /* Don't show errors for PHY probe request */
440 device_printf(sc->sc_dev, "phy read fail\n");
443 return (frame.mii_data);
447 * stge_miibus_writereg: [mii interface function]
449 * Write a PHY register on the MII of the TC9021.
452 stge_miibus_writereg(device_t dev, int phy, int reg, int val)
454 struct stge_softc *sc;
455 struct stge_mii_frame frame;
458 sc = device_get_softc(dev);
460 bzero(&frame, sizeof(frame));
461 frame.mii_phyaddr = phy;
462 frame.mii_regaddr = reg;
463 frame.mii_data = val;
466 error = stge_mii_writereg(sc, &frame);
470 device_printf(sc->sc_dev, "phy write fail\n");
475 * stge_miibus_statchg: [mii interface function]
477 * Callback from MII layer when media changes.
480 stge_miibus_statchg(device_t dev)
482 struct stge_softc *sc;
484 sc = device_get_softc(dev);
485 taskqueue_enqueue(taskqueue_swi, &sc->sc_link_task);
489 * stge_mediastatus: [ifmedia interface function]
491 * Get the current interface media status.
494 stge_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr)
496 struct stge_softc *sc;
497 struct mii_data *mii;
500 mii = device_get_softc(sc->sc_miibus);
503 ifmr->ifm_status = mii->mii_media_status;
504 ifmr->ifm_active = mii->mii_media_active;
508 * stge_mediachange: [ifmedia interface function]
510 * Set hardware to newly-selected media.
513 stge_mediachange(struct ifnet *ifp)
515 struct stge_softc *sc;
516 struct mii_data *mii;
519 mii = device_get_softc(sc->sc_miibus);
526 stge_eeprom_wait(struct stge_softc *sc)
530 for (i = 0; i < STGE_TIMEOUT; i++) {
532 if ((CSR_READ_2(sc, STGE_EepromCtrl) & EC_EepromBusy) == 0)
541 * Read data from the serial EEPROM.
544 stge_read_eeprom(struct stge_softc *sc, int offset, uint16_t *data)
547 if (stge_eeprom_wait(sc))
548 device_printf(sc->sc_dev, "EEPROM failed to come ready\n");
550 CSR_WRITE_2(sc, STGE_EepromCtrl,
551 EC_EepromAddress(offset) | EC_EepromOpcode(EC_OP_RR));
552 if (stge_eeprom_wait(sc))
553 device_printf(sc->sc_dev, "EEPROM read timed out\n");
554 *data = CSR_READ_2(sc, STGE_EepromData);
559 stge_probe(device_t dev)
561 struct stge_product *sp;
563 uint16_t vendor, devid;
565 vendor = pci_get_vendor(dev);
566 devid = pci_get_device(dev);
568 for (i = 0; i < sizeof(stge_products)/sizeof(stge_products[0]);
570 if (vendor == sp->stge_vendorid &&
571 devid == sp->stge_deviceid) {
572 device_set_desc(dev, sp->stge_name);
573 return (BUS_PROBE_DEFAULT);
581 stge_attach(device_t dev)
583 struct stge_softc *sc;
585 uint8_t enaddr[ETHER_ADDR_LEN];
591 sc = device_get_softc(dev);
594 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
596 mtx_init(&sc->sc_mii_mtx, "stge_mii_mutex", NULL, MTX_DEF);
597 callout_init_mtx(&sc->sc_tick_ch, &sc->sc_mtx, 0);
598 TASK_INIT(&sc->sc_link_task, 0, stge_link_task, sc);
603 pci_enable_busmaster(dev);
604 cmd = pci_read_config(dev, PCIR_COMMAND, 2);
605 val = pci_read_config(dev, PCIR_BAR(1), 4);
606 if ((val & 0x01) != 0)
607 sc->sc_spec = stge_res_spec_mem;
609 val = pci_read_config(dev, PCIR_BAR(0), 4);
610 if ((val & 0x01) == 0) {
611 device_printf(sc->sc_dev, "couldn't locate IO BAR\n");
615 sc->sc_spec = stge_res_spec_io;
617 error = bus_alloc_resources(dev, sc->sc_spec, sc->sc_res);
619 device_printf(dev, "couldn't allocate %s resources\n",
620 sc->sc_spec == stge_res_spec_mem ? "memory" : "I/O");
623 sc->sc_rev = pci_get_revid(dev);
625 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
626 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO,
627 "rxint_nframe", CTLTYPE_INT|CTLFLAG_RW, &sc->sc_rxint_nframe, 0,
628 sysctl_hw_stge_rxint_nframe, "I", "stge rx interrupt nframe");
630 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
631 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO,
632 "rxint_dmawait", CTLTYPE_INT|CTLFLAG_RW, &sc->sc_rxint_dmawait, 0,
633 sysctl_hw_stge_rxint_dmawait, "I", "stge rx interrupt dmawait");
635 /* Pull in device tunables. */
636 sc->sc_rxint_nframe = STGE_RXINT_NFRAME_DEFAULT;
637 error = resource_int_value(device_get_name(dev), device_get_unit(dev),
638 "rxint_nframe", &sc->sc_rxint_nframe);
640 if (sc->sc_rxint_nframe < STGE_RXINT_NFRAME_MIN ||
641 sc->sc_rxint_nframe > STGE_RXINT_NFRAME_MAX) {
642 device_printf(dev, "rxint_nframe value out of range; "
643 "using default: %d\n", STGE_RXINT_NFRAME_DEFAULT);
644 sc->sc_rxint_nframe = STGE_RXINT_NFRAME_DEFAULT;
648 sc->sc_rxint_dmawait = STGE_RXINT_DMAWAIT_DEFAULT;
649 error = resource_int_value(device_get_name(dev), device_get_unit(dev),
650 "rxint_dmawait", &sc->sc_rxint_dmawait);
652 if (sc->sc_rxint_dmawait < STGE_RXINT_DMAWAIT_MIN ||
653 sc->sc_rxint_dmawait > STGE_RXINT_DMAWAIT_MAX) {
654 device_printf(dev, "rxint_dmawait value out of range; "
655 "using default: %d\n", STGE_RXINT_DMAWAIT_DEFAULT);
656 sc->sc_rxint_dmawait = STGE_RXINT_DMAWAIT_DEFAULT;
660 if ((error = stge_dma_alloc(sc) != 0))
664 * Determine if we're copper or fiber. It affects how we
667 if (CSR_READ_4(sc, STGE_AsicCtrl) & AC_PhyMedia)
672 /* Load LED configuration from EEPROM. */
673 stge_read_eeprom(sc, STGE_EEPROM_LEDMode, &sc->sc_led);
676 * Reset the chip to a known state.
679 stge_reset(sc, STGE_RESET_FULL);
683 * Reading the station address from the EEPROM doesn't seem
684 * to work, at least on my sample boards. Instead, since
685 * the reset sequence does AutoInit, read it from the station
686 * address registers. For Sundance 1023 you can only read it
689 if (pci_get_device(dev) != DEVICEID_SUNDANCETI_ST1023) {
692 v = CSR_READ_2(sc, STGE_StationAddress0);
693 enaddr[0] = v & 0xff;
695 v = CSR_READ_2(sc, STGE_StationAddress1);
696 enaddr[2] = v & 0xff;
698 v = CSR_READ_2(sc, STGE_StationAddress2);
699 enaddr[4] = v & 0xff;
703 uint16_t myaddr[ETHER_ADDR_LEN / 2];
704 for (i = 0; i <ETHER_ADDR_LEN / 2; i++) {
705 stge_read_eeprom(sc, STGE_EEPROM_StationAddress0 + i,
707 myaddr[i] = le16toh(myaddr[i]);
709 bcopy(myaddr, enaddr, sizeof(enaddr));
713 ifp = sc->sc_ifp = if_alloc(IFT_ETHER);
715 device_printf(sc->sc_dev, "failed to if_alloc()\n");
721 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
722 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
723 ifp->if_ioctl = stge_ioctl;
724 ifp->if_start = stge_start;
726 ifp->if_watchdog = NULL;
727 ifp->if_init = stge_init;
728 ifp->if_mtu = ETHERMTU;
729 ifp->if_snd.ifq_drv_maxlen = STGE_TX_RING_CNT - 1;
730 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen);
731 IFQ_SET_READY(&ifp->if_snd);
732 /* Revision B3 and earlier chips have checksum bug. */
733 if (sc->sc_rev >= 0x0c) {
734 ifp->if_hwassist = STGE_CSUM_FEATURES;
735 ifp->if_capabilities = IFCAP_HWCSUM;
737 ifp->if_hwassist = 0;
738 ifp->if_capabilities = 0;
740 ifp->if_capabilities |= IFCAP_WOL_MAGIC;
741 ifp->if_capenable = ifp->if_capabilities;
744 * Read some important bits from the PhyCtrl register.
746 sc->sc_PhyCtrl = CSR_READ_1(sc, STGE_PhyCtrl) &
747 (PC_PhyDuplexPolarity | PC_PhyLnkPolarity);
749 /* Set up MII bus. */
750 if ((error = mii_phy_probe(sc->sc_dev, &sc->sc_miibus, stge_mediachange,
751 stge_mediastatus)) != 0) {
752 device_printf(sc->sc_dev, "no PHY found!\n");
756 ether_ifattach(ifp, enaddr);
758 /* VLAN capability setup */
759 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING;
760 if (sc->sc_rev >= 0x0c)
761 ifp->if_capabilities |= IFCAP_VLAN_HWCSUM;
762 ifp->if_capenable = ifp->if_capabilities;
763 #ifdef DEVICE_POLLING
764 ifp->if_capabilities |= IFCAP_POLLING;
767 * Tell the upper layer(s) we support long frames.
768 * Must appear after the call to ether_ifattach() because
769 * ether_ifattach() sets ifi_hdrlen to the default value.
771 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
774 * The manual recommends disabling early transmit, so we
775 * do. It's disabled anyway, if using IP checksumming,
776 * since the entire packet must be in the FIFO in order
777 * for the chip to perform the checksum.
779 sc->sc_txthresh = 0x0fff;
782 * Disable MWI if the PCI layer tells us to.
785 if ((cmd & PCIM_CMD_MWRICEN) == 0)
786 sc->sc_DMACtrl |= DMAC_MWIDisable;
791 error = bus_setup_intr(dev, sc->sc_res[1], INTR_TYPE_NET | INTR_MPSAFE,
792 NULL, stge_intr, sc, &sc->sc_ih);
795 device_printf(sc->sc_dev, "couldn't set up IRQ\n");
808 stge_detach(device_t dev)
810 struct stge_softc *sc;
813 sc = device_get_softc(dev);
816 #ifdef DEVICE_POLLING
817 if (ifp && ifp->if_capenable & IFCAP_POLLING)
818 ether_poll_deregister(ifp);
820 if (device_is_attached(dev)) {
826 callout_drain(&sc->sc_tick_ch);
827 taskqueue_drain(taskqueue_swi, &sc->sc_link_task);
831 if (sc->sc_miibus != NULL) {
832 device_delete_child(dev, sc->sc_miibus);
833 sc->sc_miibus = NULL;
835 bus_generic_detach(dev);
844 bus_teardown_intr(dev, sc->sc_res[1], sc->sc_ih);
847 bus_release_resources(dev, sc->sc_spec, sc->sc_res);
849 mtx_destroy(&sc->sc_mii_mtx);
850 mtx_destroy(&sc->sc_mtx);
855 struct stge_dmamap_arg {
856 bus_addr_t stge_busaddr;
860 stge_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
862 struct stge_dmamap_arg *ctx;
867 ctx = (struct stge_dmamap_arg *)arg;
868 ctx->stge_busaddr = segs[0].ds_addr;
872 stge_dma_alloc(struct stge_softc *sc)
874 struct stge_dmamap_arg ctx;
875 struct stge_txdesc *txd;
876 struct stge_rxdesc *rxd;
879 /* create parent tag. */
880 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev),/* parent */
881 1, 0, /* algnmnt, boundary */
882 STGE_DMA_MAXADDR, /* lowaddr */
883 BUS_SPACE_MAXADDR, /* highaddr */
884 NULL, NULL, /* filter, filterarg */
885 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */
887 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */
889 NULL, NULL, /* lockfunc, lockarg */
890 &sc->sc_cdata.stge_parent_tag);
892 device_printf(sc->sc_dev, "failed to create parent DMA tag\n");
895 /* create tag for Tx ring. */
896 error = bus_dma_tag_create(sc->sc_cdata.stge_parent_tag,/* parent */
897 STGE_RING_ALIGN, 0, /* algnmnt, boundary */
898 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
899 BUS_SPACE_MAXADDR, /* highaddr */
900 NULL, NULL, /* filter, filterarg */
901 STGE_TX_RING_SZ, /* maxsize */
903 STGE_TX_RING_SZ, /* maxsegsize */
905 NULL, NULL, /* lockfunc, lockarg */
906 &sc->sc_cdata.stge_tx_ring_tag);
908 device_printf(sc->sc_dev,
909 "failed to allocate Tx ring DMA tag\n");
913 /* create tag for Rx ring. */
914 error = bus_dma_tag_create(sc->sc_cdata.stge_parent_tag,/* parent */
915 STGE_RING_ALIGN, 0, /* algnmnt, boundary */
916 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
917 BUS_SPACE_MAXADDR, /* highaddr */
918 NULL, NULL, /* filter, filterarg */
919 STGE_RX_RING_SZ, /* maxsize */
921 STGE_RX_RING_SZ, /* maxsegsize */
923 NULL, NULL, /* lockfunc, lockarg */
924 &sc->sc_cdata.stge_rx_ring_tag);
926 device_printf(sc->sc_dev,
927 "failed to allocate Rx ring DMA tag\n");
931 /* create tag for Tx buffers. */
932 error = bus_dma_tag_create(sc->sc_cdata.stge_parent_tag,/* parent */
933 1, 0, /* algnmnt, boundary */
934 BUS_SPACE_MAXADDR, /* lowaddr */
935 BUS_SPACE_MAXADDR, /* highaddr */
936 NULL, NULL, /* filter, filterarg */
937 MCLBYTES * STGE_MAXTXSEGS, /* maxsize */
938 STGE_MAXTXSEGS, /* nsegments */
939 MCLBYTES, /* maxsegsize */
941 NULL, NULL, /* lockfunc, lockarg */
942 &sc->sc_cdata.stge_tx_tag);
944 device_printf(sc->sc_dev, "failed to allocate Tx DMA tag\n");
948 /* create tag for Rx buffers. */
949 error = bus_dma_tag_create(sc->sc_cdata.stge_parent_tag,/* parent */
950 1, 0, /* algnmnt, boundary */
951 BUS_SPACE_MAXADDR, /* lowaddr */
952 BUS_SPACE_MAXADDR, /* highaddr */
953 NULL, NULL, /* filter, filterarg */
954 MCLBYTES, /* maxsize */
956 MCLBYTES, /* maxsegsize */
958 NULL, NULL, /* lockfunc, lockarg */
959 &sc->sc_cdata.stge_rx_tag);
961 device_printf(sc->sc_dev, "failed to allocate Rx DMA tag\n");
965 /* allocate DMA'able memory and load the DMA map for Tx ring. */
966 error = bus_dmamem_alloc(sc->sc_cdata.stge_tx_ring_tag,
967 (void **)&sc->sc_rdata.stge_tx_ring, BUS_DMA_NOWAIT | BUS_DMA_ZERO,
968 &sc->sc_cdata.stge_tx_ring_map);
970 device_printf(sc->sc_dev,
971 "failed to allocate DMA'able memory for Tx ring\n");
975 ctx.stge_busaddr = 0;
976 error = bus_dmamap_load(sc->sc_cdata.stge_tx_ring_tag,
977 sc->sc_cdata.stge_tx_ring_map, sc->sc_rdata.stge_tx_ring,
978 STGE_TX_RING_SZ, stge_dmamap_cb, &ctx, BUS_DMA_NOWAIT);
979 if (error != 0 || ctx.stge_busaddr == 0) {
980 device_printf(sc->sc_dev,
981 "failed to load DMA'able memory for Tx ring\n");
984 sc->sc_rdata.stge_tx_ring_paddr = ctx.stge_busaddr;
986 /* allocate DMA'able memory and load the DMA map for Rx ring. */
987 error = bus_dmamem_alloc(sc->sc_cdata.stge_rx_ring_tag,
988 (void **)&sc->sc_rdata.stge_rx_ring, BUS_DMA_NOWAIT | BUS_DMA_ZERO,
989 &sc->sc_cdata.stge_rx_ring_map);
991 device_printf(sc->sc_dev,
992 "failed to allocate DMA'able memory for Rx ring\n");
996 ctx.stge_busaddr = 0;
997 error = bus_dmamap_load(sc->sc_cdata.stge_rx_ring_tag,
998 sc->sc_cdata.stge_rx_ring_map, sc->sc_rdata.stge_rx_ring,
999 STGE_RX_RING_SZ, stge_dmamap_cb, &ctx, BUS_DMA_NOWAIT);
1000 if (error != 0 || ctx.stge_busaddr == 0) {
1001 device_printf(sc->sc_dev,
1002 "failed to load DMA'able memory for Rx ring\n");
1005 sc->sc_rdata.stge_rx_ring_paddr = ctx.stge_busaddr;
1007 /* create DMA maps for Tx buffers. */
1008 for (i = 0; i < STGE_TX_RING_CNT; i++) {
1009 txd = &sc->sc_cdata.stge_txdesc[i];
1012 error = bus_dmamap_create(sc->sc_cdata.stge_tx_tag, 0,
1015 device_printf(sc->sc_dev,
1016 "failed to create Tx dmamap\n");
1020 /* create DMA maps for Rx buffers. */
1021 if ((error = bus_dmamap_create(sc->sc_cdata.stge_rx_tag, 0,
1022 &sc->sc_cdata.stge_rx_sparemap)) != 0) {
1023 device_printf(sc->sc_dev, "failed to create spare Rx dmamap\n");
1026 for (i = 0; i < STGE_RX_RING_CNT; i++) {
1027 rxd = &sc->sc_cdata.stge_rxdesc[i];
1030 error = bus_dmamap_create(sc->sc_cdata.stge_rx_tag, 0,
1033 device_printf(sc->sc_dev,
1034 "failed to create Rx dmamap\n");
1044 stge_dma_free(struct stge_softc *sc)
1046 struct stge_txdesc *txd;
1047 struct stge_rxdesc *rxd;
1051 if (sc->sc_cdata.stge_tx_ring_tag) {
1052 if (sc->sc_cdata.stge_tx_ring_map)
1053 bus_dmamap_unload(sc->sc_cdata.stge_tx_ring_tag,
1054 sc->sc_cdata.stge_tx_ring_map);
1055 if (sc->sc_cdata.stge_tx_ring_map &&
1056 sc->sc_rdata.stge_tx_ring)
1057 bus_dmamem_free(sc->sc_cdata.stge_tx_ring_tag,
1058 sc->sc_rdata.stge_tx_ring,
1059 sc->sc_cdata.stge_tx_ring_map);
1060 sc->sc_rdata.stge_tx_ring = NULL;
1061 sc->sc_cdata.stge_tx_ring_map = 0;
1062 bus_dma_tag_destroy(sc->sc_cdata.stge_tx_ring_tag);
1063 sc->sc_cdata.stge_tx_ring_tag = NULL;
1066 if (sc->sc_cdata.stge_rx_ring_tag) {
1067 if (sc->sc_cdata.stge_rx_ring_map)
1068 bus_dmamap_unload(sc->sc_cdata.stge_rx_ring_tag,
1069 sc->sc_cdata.stge_rx_ring_map);
1070 if (sc->sc_cdata.stge_rx_ring_map &&
1071 sc->sc_rdata.stge_rx_ring)
1072 bus_dmamem_free(sc->sc_cdata.stge_rx_ring_tag,
1073 sc->sc_rdata.stge_rx_ring,
1074 sc->sc_cdata.stge_rx_ring_map);
1075 sc->sc_rdata.stge_rx_ring = NULL;
1076 sc->sc_cdata.stge_rx_ring_map = 0;
1077 bus_dma_tag_destroy(sc->sc_cdata.stge_rx_ring_tag);
1078 sc->sc_cdata.stge_rx_ring_tag = NULL;
1081 if (sc->sc_cdata.stge_tx_tag) {
1082 for (i = 0; i < STGE_TX_RING_CNT; i++) {
1083 txd = &sc->sc_cdata.stge_txdesc[i];
1084 if (txd->tx_dmamap) {
1085 bus_dmamap_destroy(sc->sc_cdata.stge_tx_tag,
1090 bus_dma_tag_destroy(sc->sc_cdata.stge_tx_tag);
1091 sc->sc_cdata.stge_tx_tag = NULL;
1094 if (sc->sc_cdata.stge_rx_tag) {
1095 for (i = 0; i < STGE_RX_RING_CNT; i++) {
1096 rxd = &sc->sc_cdata.stge_rxdesc[i];
1097 if (rxd->rx_dmamap) {
1098 bus_dmamap_destroy(sc->sc_cdata.stge_rx_tag,
1103 if (sc->sc_cdata.stge_rx_sparemap) {
1104 bus_dmamap_destroy(sc->sc_cdata.stge_rx_tag,
1105 sc->sc_cdata.stge_rx_sparemap);
1106 sc->sc_cdata.stge_rx_sparemap = 0;
1108 bus_dma_tag_destroy(sc->sc_cdata.stge_rx_tag);
1109 sc->sc_cdata.stge_rx_tag = NULL;
1112 if (sc->sc_cdata.stge_parent_tag) {
1113 bus_dma_tag_destroy(sc->sc_cdata.stge_parent_tag);
1114 sc->sc_cdata.stge_parent_tag = NULL;
1121 * Make sure the interface is stopped at reboot time.
1124 stge_shutdown(device_t dev)
1127 return (stge_suspend(dev));
1131 stge_setwol(struct stge_softc *sc)
1136 STGE_LOCK_ASSERT(sc);
1139 v = CSR_READ_1(sc, STGE_WakeEvent);
1140 /* Disable all WOL bits. */
1141 v &= ~(WE_WakePktEnable | WE_MagicPktEnable | WE_LinkEventEnable |
1142 WE_WakeOnLanEnable);
1143 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0)
1144 v |= WE_MagicPktEnable | WE_WakeOnLanEnable;
1145 CSR_WRITE_1(sc, STGE_WakeEvent, v);
1146 /* Reset Tx and prevent transmission. */
1147 CSR_WRITE_4(sc, STGE_AsicCtrl,
1148 CSR_READ_4(sc, STGE_AsicCtrl) | AC_TxReset);
1150 * TC9021 automatically reset link speed to 100Mbps when it's put
1151 * into sleep so there is no need to try to resetting link speed.
1156 stge_suspend(device_t dev)
1158 struct stge_softc *sc;
1160 sc = device_get_softc(dev);
1164 sc->sc_suspended = 1;
1172 stge_resume(device_t dev)
1174 struct stge_softc *sc;
1178 sc = device_get_softc(dev);
1182 * Clear WOL bits, so special frames wouldn't interfere
1183 * normal Rx operation anymore.
1185 v = CSR_READ_1(sc, STGE_WakeEvent);
1186 v &= ~(WE_WakePktEnable | WE_MagicPktEnable | WE_LinkEventEnable |
1187 WE_WakeOnLanEnable);
1188 CSR_WRITE_1(sc, STGE_WakeEvent, v);
1190 if (ifp->if_flags & IFF_UP)
1191 stge_init_locked(sc);
1193 sc->sc_suspended = 0;
1200 stge_dma_wait(struct stge_softc *sc)
1204 for (i = 0; i < STGE_TIMEOUT; i++) {
1206 if ((CSR_READ_4(sc, STGE_DMACtrl) & DMAC_TxDMAInProg) == 0)
1210 if (i == STGE_TIMEOUT)
1211 device_printf(sc->sc_dev, "DMA wait timed out\n");
1215 stge_encap(struct stge_softc *sc, struct mbuf **m_head)
1217 struct stge_txdesc *txd;
1218 struct stge_tfd *tfd;
1220 bus_dma_segment_t txsegs[STGE_MAXTXSEGS];
1221 int error, i, nsegs, si;
1222 uint64_t csum_flags, tfc;
1224 STGE_LOCK_ASSERT(sc);
1226 if ((txd = STAILQ_FIRST(&sc->sc_cdata.stge_txfreeq)) == NULL)
1229 error = bus_dmamap_load_mbuf_sg(sc->sc_cdata.stge_tx_tag,
1230 txd->tx_dmamap, *m_head, txsegs, &nsegs, 0);
1231 if (error == EFBIG) {
1232 m = m_collapse(*m_head, M_DONTWAIT, STGE_MAXTXSEGS);
1239 error = bus_dmamap_load_mbuf_sg(sc->sc_cdata.stge_tx_tag,
1240 txd->tx_dmamap, *m_head, txsegs, &nsegs, 0);
1246 } else if (error != 0)
1256 if ((m->m_pkthdr.csum_flags & STGE_CSUM_FEATURES) != 0) {
1257 if (m->m_pkthdr.csum_flags & CSUM_IP)
1258 csum_flags |= TFD_IPChecksumEnable;
1259 if (m->m_pkthdr.csum_flags & CSUM_TCP)
1260 csum_flags |= TFD_TCPChecksumEnable;
1261 else if (m->m_pkthdr.csum_flags & CSUM_UDP)
1262 csum_flags |= TFD_UDPChecksumEnable;
1265 si = sc->sc_cdata.stge_tx_prod;
1266 tfd = &sc->sc_rdata.stge_tx_ring[si];
1267 for (i = 0; i < nsegs; i++)
1268 tfd->tfd_frags[i].frag_word0 =
1269 htole64(FRAG_ADDR(txsegs[i].ds_addr) |
1270 FRAG_LEN(txsegs[i].ds_len));
1271 sc->sc_cdata.stge_tx_cnt++;
1273 tfc = TFD_FrameId(si) | TFD_WordAlign(TFD_WordAlign_disable) |
1274 TFD_FragCount(nsegs) | csum_flags;
1275 if (sc->sc_cdata.stge_tx_cnt >= STGE_TX_HIWAT)
1276 tfc |= TFD_TxDMAIndicate;
1278 /* Update producer index. */
1279 sc->sc_cdata.stge_tx_prod = (si + 1) % STGE_TX_RING_CNT;
1281 /* Check if we have a VLAN tag to insert. */
1282 if (m->m_flags & M_VLANTAG)
1283 tfc |= (TFD_VLANTagInsert | TFD_VID(m->m_pkthdr.ether_vtag));
1284 tfd->tfd_control = htole64(tfc);
1286 /* Update Tx Queue. */
1287 STAILQ_REMOVE_HEAD(&sc->sc_cdata.stge_txfreeq, tx_q);
1288 STAILQ_INSERT_TAIL(&sc->sc_cdata.stge_txbusyq, txd, tx_q);
1291 /* Sync descriptors. */
1292 bus_dmamap_sync(sc->sc_cdata.stge_tx_tag, txd->tx_dmamap,
1293 BUS_DMASYNC_PREWRITE);
1294 bus_dmamap_sync(sc->sc_cdata.stge_tx_ring_tag,
1295 sc->sc_cdata.stge_tx_ring_map,
1296 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1302 * stge_start: [ifnet interface function]
1304 * Start packet transmission on the interface.
1307 stge_start(struct ifnet *ifp)
1309 struct stge_softc *sc;
1313 stge_start_locked(ifp);
1318 stge_start_locked(struct ifnet *ifp)
1320 struct stge_softc *sc;
1321 struct mbuf *m_head;
1326 STGE_LOCK_ASSERT(sc);
1328 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING|IFF_DRV_OACTIVE)) !=
1329 IFF_DRV_RUNNING || sc->sc_link == 0)
1332 for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd); ) {
1333 if (sc->sc_cdata.stge_tx_cnt >= STGE_TX_HIWAT) {
1334 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1338 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
1342 * Pack the data into the transmit ring. If we
1343 * don't have room, set the OACTIVE flag and wait
1344 * for the NIC to drain the ring.
1346 if (stge_encap(sc, &m_head)) {
1349 IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
1350 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1356 * If there's a BPF listener, bounce a copy of this frame
1359 ETHER_BPF_MTAP(ifp, m_head);
1364 CSR_WRITE_4(sc, STGE_DMACtrl, DMAC_TxDMAPollNow);
1366 /* Set a timeout in case the chip goes out to lunch. */
1367 sc->sc_watchdog_timer = 5;
1374 * Watchdog timer handler.
1377 stge_watchdog(struct stge_softc *sc)
1381 STGE_LOCK_ASSERT(sc);
1383 if (sc->sc_watchdog_timer == 0 || --sc->sc_watchdog_timer)
1387 if_printf(sc->sc_ifp, "device timeout\n");
1389 stge_init_locked(sc);
1390 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1391 stge_start_locked(ifp);
1395 * stge_ioctl: [ifnet interface function]
1397 * Handle control requests from the operator.
1400 stge_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
1402 struct stge_softc *sc;
1404 struct mii_data *mii;
1408 ifr = (struct ifreq *)data;
1412 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > STGE_JUMBO_MTU)
1414 else if (ifp->if_mtu != ifr->ifr_mtu) {
1415 ifp->if_mtu = ifr->ifr_mtu;
1417 stge_init_locked(sc);
1423 if ((ifp->if_flags & IFF_UP) != 0) {
1424 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
1425 if (((ifp->if_flags ^ sc->sc_if_flags)
1426 & IFF_PROMISC) != 0)
1427 stge_set_filter(sc);
1429 if (sc->sc_detach == 0)
1430 stge_init_locked(sc);
1433 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
1436 sc->sc_if_flags = ifp->if_flags;
1442 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
1448 mii = device_get_softc(sc->sc_miibus);
1449 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd);
1452 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
1453 #ifdef DEVICE_POLLING
1454 if ((mask & IFCAP_POLLING) != 0) {
1455 if ((ifr->ifr_reqcap & IFCAP_POLLING) != 0) {
1456 error = ether_poll_register(stge_poll, ifp);
1460 CSR_WRITE_2(sc, STGE_IntEnable, 0);
1461 ifp->if_capenable |= IFCAP_POLLING;
1464 error = ether_poll_deregister(ifp);
1468 CSR_WRITE_2(sc, STGE_IntEnable,
1470 ifp->if_capenable &= ~IFCAP_POLLING;
1475 if ((mask & IFCAP_HWCSUM) != 0) {
1476 ifp->if_capenable ^= IFCAP_HWCSUM;
1477 if ((IFCAP_HWCSUM & ifp->if_capenable) != 0 &&
1478 (IFCAP_HWCSUM & ifp->if_capabilities) != 0)
1479 ifp->if_hwassist = STGE_CSUM_FEATURES;
1481 ifp->if_hwassist = 0;
1483 if ((mask & IFCAP_WOL) != 0 &&
1484 (ifp->if_capabilities & IFCAP_WOL) != 0) {
1485 if ((mask & IFCAP_WOL_MAGIC) != 0)
1486 ifp->if_capenable ^= IFCAP_WOL_MAGIC;
1488 if ((mask & IFCAP_VLAN_HWTAGGING) != 0) {
1489 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
1490 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
1492 stge_vlan_setup(sc);
1496 VLAN_CAPABILITIES(ifp);
1499 error = ether_ioctl(ifp, cmd, data);
1507 stge_link_task(void *arg, int pending)
1509 struct stge_softc *sc;
1510 struct mii_data *mii;
1514 sc = (struct stge_softc *)arg;
1517 mii = device_get_softc(sc->sc_miibus);
1518 if (mii->mii_media_status & IFM_ACTIVE) {
1519 if (IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE)
1525 if (((mii->mii_media_active & IFM_GMASK) & IFM_FDX) != 0)
1526 sc->sc_MACCtrl |= MC_DuplexSelect;
1527 if (((mii->mii_media_active & IFM_GMASK) & IFM_FLAG0) != 0)
1528 sc->sc_MACCtrl |= MC_RxFlowControlEnable;
1529 if (((mii->mii_media_active & IFM_GMASK) & IFM_FLAG1) != 0)
1530 sc->sc_MACCtrl |= MC_TxFlowControlEnable;
1532 * Update STGE_MACCtrl register depending on link status.
1533 * (duplex, flow control etc)
1535 v = ac = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK;
1536 v &= ~(MC_DuplexSelect|MC_RxFlowControlEnable|MC_TxFlowControlEnable);
1537 v |= sc->sc_MACCtrl;
1538 CSR_WRITE_4(sc, STGE_MACCtrl, v);
1539 if (((ac ^ sc->sc_MACCtrl) & MC_DuplexSelect) != 0) {
1540 /* Duplex setting changed, reset Tx/Rx functions. */
1541 ac = CSR_READ_4(sc, STGE_AsicCtrl);
1542 ac |= AC_TxReset | AC_RxReset;
1543 CSR_WRITE_4(sc, STGE_AsicCtrl, ac);
1544 for (i = 0; i < STGE_TIMEOUT; i++) {
1546 if ((CSR_READ_4(sc, STGE_AsicCtrl) & AC_ResetBusy) == 0)
1549 if (i == STGE_TIMEOUT)
1550 device_printf(sc->sc_dev, "reset failed to complete\n");
1556 stge_tx_error(struct stge_softc *sc)
1562 txstat = CSR_READ_4(sc, STGE_TxStatus);
1563 if ((txstat & TS_TxComplete) == 0)
1566 if ((txstat & TS_TxUnderrun) != 0) {
1569 * There should be a more better way to recover
1570 * from Tx underrun instead of a full reset.
1572 if (sc->sc_nerr++ < STGE_MAXERR)
1573 device_printf(sc->sc_dev, "Tx underrun, "
1575 if (sc->sc_nerr == STGE_MAXERR)
1576 device_printf(sc->sc_dev, "too many errors; "
1577 "not reporting any more\n");
1581 /* Maximum/Late collisions, Re-enable Tx MAC. */
1582 if ((txstat & (TS_MaxCollisions|TS_LateCollision)) != 0)
1583 CSR_WRITE_4(sc, STGE_MACCtrl,
1584 (CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK) |
1594 * Interrupt service routine.
1597 stge_intr(void *arg)
1599 struct stge_softc *sc;
1604 sc = (struct stge_softc *)arg;
1609 #ifdef DEVICE_POLLING
1610 if ((ifp->if_capenable & IFCAP_POLLING) != 0)
1613 status = CSR_READ_2(sc, STGE_IntStatus);
1614 if (sc->sc_suspended || (status & IS_InterruptStatus) == 0)
1617 /* Disable interrupts. */
1618 for (reinit = 0;;) {
1619 status = CSR_READ_2(sc, STGE_IntStatusAck);
1620 status &= sc->sc_IntEnable;
1623 /* Host interface errors. */
1624 if ((status & IS_HostError) != 0) {
1625 device_printf(sc->sc_dev,
1626 "Host interface error, resetting...\n");
1631 /* Receive interrupts. */
1632 if ((status & IS_RxDMAComplete) != 0) {
1634 if ((status & IS_RFDListEnd) != 0)
1635 CSR_WRITE_4(sc, STGE_DMACtrl,
1639 /* Transmit interrupts. */
1640 if ((status & (IS_TxDMAComplete | IS_TxComplete)) != 0)
1643 /* Transmission errors.*/
1644 if ((status & IS_TxComplete) != 0) {
1645 if ((reinit = stge_tx_error(sc)) != 0)
1652 stge_init_locked(sc);
1654 /* Re-enable interrupts. */
1655 CSR_WRITE_2(sc, STGE_IntEnable, sc->sc_IntEnable);
1657 /* Try to get more packets going. */
1658 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1659 stge_start_locked(ifp);
1668 * Helper; handle transmit interrupts.
1671 stge_txeof(struct stge_softc *sc)
1674 struct stge_txdesc *txd;
1678 STGE_LOCK_ASSERT(sc);
1682 txd = STAILQ_FIRST(&sc->sc_cdata.stge_txbusyq);
1685 bus_dmamap_sync(sc->sc_cdata.stge_tx_ring_tag,
1686 sc->sc_cdata.stge_tx_ring_map, BUS_DMASYNC_POSTREAD);
1689 * Go through our Tx list and free mbufs for those
1690 * frames which have been transmitted.
1692 for (cons = sc->sc_cdata.stge_tx_cons;;
1693 cons = (cons + 1) % STGE_TX_RING_CNT) {
1694 if (sc->sc_cdata.stge_tx_cnt <= 0)
1696 control = le64toh(sc->sc_rdata.stge_tx_ring[cons].tfd_control);
1697 if ((control & TFD_TFDDone) == 0)
1699 sc->sc_cdata.stge_tx_cnt--;
1700 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1702 bus_dmamap_sync(sc->sc_cdata.stge_tx_tag, txd->tx_dmamap,
1703 BUS_DMASYNC_POSTWRITE);
1704 bus_dmamap_unload(sc->sc_cdata.stge_tx_tag, txd->tx_dmamap);
1706 /* Output counter is updated with statistics register */
1709 STAILQ_REMOVE_HEAD(&sc->sc_cdata.stge_txbusyq, tx_q);
1710 STAILQ_INSERT_TAIL(&sc->sc_cdata.stge_txfreeq, txd, tx_q);
1711 txd = STAILQ_FIRST(&sc->sc_cdata.stge_txbusyq);
1713 sc->sc_cdata.stge_tx_cons = cons;
1714 if (sc->sc_cdata.stge_tx_cnt == 0)
1715 sc->sc_watchdog_timer = 0;
1717 bus_dmamap_sync(sc->sc_cdata.stge_tx_ring_tag,
1718 sc->sc_cdata.stge_tx_ring_map,
1719 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1722 static __inline void
1723 stge_discard_rxbuf(struct stge_softc *sc, int idx)
1725 struct stge_rfd *rfd;
1727 rfd = &sc->sc_rdata.stge_rx_ring[idx];
1728 rfd->rfd_status = 0;
1731 #ifndef __NO_STRICT_ALIGNMENT
1733 * It seems that TC9021's DMA engine has alignment restrictions in
1734 * DMA scatter operations. The first DMA segment has no address
1735 * alignment restrictins but the rest should be aligned on 4(?) bytes
1736 * boundary. Otherwise it would corrupt random memory. Since we don't
1737 * know which one is used for the first segment in advance we simply
1738 * don't align at all.
1739 * To avoid copying over an entire frame to align, we allocate a new
1740 * mbuf and copy ethernet header to the new mbuf. The new mbuf is
1741 * prepended into the existing mbuf chain.
1743 static __inline struct mbuf *
1744 stge_fixup_rx(struct stge_softc *sc, struct mbuf *m)
1749 if (m->m_len <= (MCLBYTES - ETHER_HDR_LEN)) {
1750 bcopy(m->m_data, m->m_data + ETHER_HDR_LEN, m->m_len);
1751 m->m_data += ETHER_HDR_LEN;
1754 MGETHDR(n, M_DONTWAIT, MT_DATA);
1756 bcopy(m->m_data, n->m_data, ETHER_HDR_LEN);
1757 m->m_data += ETHER_HDR_LEN;
1758 m->m_len -= ETHER_HDR_LEN;
1759 n->m_len = ETHER_HDR_LEN;
1760 M_MOVE_PKTHDR(n, m);
1773 * Helper; handle receive interrupts.
1776 stge_rxeof(struct stge_softc *sc)
1779 struct stge_rxdesc *rxd;
1780 struct mbuf *mp, *m;
1783 int cons, prog, rx_npkts;
1785 STGE_LOCK_ASSERT(sc);
1790 bus_dmamap_sync(sc->sc_cdata.stge_rx_ring_tag,
1791 sc->sc_cdata.stge_rx_ring_map, BUS_DMASYNC_POSTREAD);
1794 for (cons = sc->sc_cdata.stge_rx_cons; prog < STGE_RX_RING_CNT;
1795 prog++, cons = (cons + 1) % STGE_RX_RING_CNT) {
1796 status64 = le64toh(sc->sc_rdata.stge_rx_ring[cons].rfd_status);
1797 status = RFD_RxStatus(status64);
1798 if ((status & RFD_RFDDone) == 0)
1800 #ifdef DEVICE_POLLING
1801 if (ifp->if_capenable & IFCAP_POLLING) {
1802 if (sc->sc_cdata.stge_rxcycles <= 0)
1804 sc->sc_cdata.stge_rxcycles--;
1808 rxd = &sc->sc_cdata.stge_rxdesc[cons];
1812 * If the packet had an error, drop it. Note we count
1813 * the error later in the periodic stats update.
1815 if ((status & RFD_FrameEnd) != 0 && (status &
1816 (RFD_RxFIFOOverrun | RFD_RxRuntFrame |
1817 RFD_RxAlignmentError | RFD_RxFCSError |
1818 RFD_RxLengthError)) != 0) {
1819 stge_discard_rxbuf(sc, cons);
1820 if (sc->sc_cdata.stge_rxhead != NULL) {
1821 m_freem(sc->sc_cdata.stge_rxhead);
1822 STGE_RXCHAIN_RESET(sc);
1827 * Add a new receive buffer to the ring.
1829 if (stge_newbuf(sc, cons) != 0) {
1831 stge_discard_rxbuf(sc, cons);
1832 if (sc->sc_cdata.stge_rxhead != NULL) {
1833 m_freem(sc->sc_cdata.stge_rxhead);
1834 STGE_RXCHAIN_RESET(sc);
1839 if ((status & RFD_FrameEnd) != 0)
1840 mp->m_len = RFD_RxDMAFrameLen(status) -
1841 sc->sc_cdata.stge_rxlen;
1842 sc->sc_cdata.stge_rxlen += mp->m_len;
1845 if (sc->sc_cdata.stge_rxhead == NULL) {
1846 sc->sc_cdata.stge_rxhead = mp;
1847 sc->sc_cdata.stge_rxtail = mp;
1849 mp->m_flags &= ~M_PKTHDR;
1850 sc->sc_cdata.stge_rxtail->m_next = mp;
1851 sc->sc_cdata.stge_rxtail = mp;
1854 if ((status & RFD_FrameEnd) != 0) {
1855 m = sc->sc_cdata.stge_rxhead;
1856 m->m_pkthdr.rcvif = ifp;
1857 m->m_pkthdr.len = sc->sc_cdata.stge_rxlen;
1859 if (m->m_pkthdr.len > sc->sc_if_framesize) {
1861 STGE_RXCHAIN_RESET(sc);
1865 * Set the incoming checksum information for
1868 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) {
1869 if ((status & RFD_IPDetected) != 0) {
1870 m->m_pkthdr.csum_flags |=
1872 if ((status & RFD_IPError) == 0)
1873 m->m_pkthdr.csum_flags |=
1876 if (((status & RFD_TCPDetected) != 0 &&
1877 (status & RFD_TCPError) == 0) ||
1878 ((status & RFD_UDPDetected) != 0 &&
1879 (status & RFD_UDPError) == 0)) {
1880 m->m_pkthdr.csum_flags |=
1881 (CSUM_DATA_VALID | CSUM_PSEUDO_HDR);
1882 m->m_pkthdr.csum_data = 0xffff;
1886 #ifndef __NO_STRICT_ALIGNMENT
1887 if (sc->sc_if_framesize > (MCLBYTES - ETHER_ALIGN)) {
1888 if ((m = stge_fixup_rx(sc, m)) == NULL) {
1889 STGE_RXCHAIN_RESET(sc);
1894 /* Check for VLAN tagged packets. */
1895 if ((status & RFD_VLANDetected) != 0 &&
1896 (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) {
1897 m->m_pkthdr.ether_vtag = RFD_TCI(status64);
1898 m->m_flags |= M_VLANTAG;
1903 (*ifp->if_input)(ifp, m);
1907 STGE_RXCHAIN_RESET(sc);
1912 /* Update the consumer index. */
1913 sc->sc_cdata.stge_rx_cons = cons;
1914 bus_dmamap_sync(sc->sc_cdata.stge_rx_ring_tag,
1915 sc->sc_cdata.stge_rx_ring_map,
1916 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1921 #ifdef DEVICE_POLLING
1923 stge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
1925 struct stge_softc *sc;
1932 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
1937 sc->sc_cdata.stge_rxcycles = count;
1938 rx_npkts = stge_rxeof(sc);
1941 if (cmd == POLL_AND_CHECK_STATUS) {
1942 status = CSR_READ_2(sc, STGE_IntStatus);
1943 status &= sc->sc_IntEnable;
1945 if ((status & IS_HostError) != 0) {
1946 device_printf(sc->sc_dev,
1947 "Host interface error, resetting...\n");
1948 stge_init_locked(sc);
1950 if ((status & IS_TxComplete) != 0) {
1951 if (stge_tx_error(sc) != 0)
1952 stge_init_locked(sc);
1958 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1959 stge_start_locked(ifp);
1964 #endif /* DEVICE_POLLING */
1969 * One second timer, used to tick the MII.
1972 stge_tick(void *arg)
1974 struct stge_softc *sc;
1975 struct mii_data *mii;
1977 sc = (struct stge_softc *)arg;
1979 STGE_LOCK_ASSERT(sc);
1981 mii = device_get_softc(sc->sc_miibus);
1984 /* Update statistics counters. */
1985 stge_stats_update(sc);
1988 * Relcaim any pending Tx descriptors to release mbufs in a
1989 * timely manner as we don't generate Tx completion interrupts
1990 * for every frame. This limits the delay to a maximum of one
1993 if (sc->sc_cdata.stge_tx_cnt != 0)
1998 callout_reset(&sc->sc_tick_ch, hz, stge_tick, sc);
2002 * stge_stats_update:
2004 * Read the TC9021 statistics counters.
2007 stge_stats_update(struct stge_softc *sc)
2011 STGE_LOCK_ASSERT(sc);
2015 CSR_READ_4(sc,STGE_OctetRcvOk);
2017 ifp->if_ipackets += CSR_READ_4(sc, STGE_FramesRcvdOk);
2019 ifp->if_ierrors += CSR_READ_2(sc, STGE_FramesLostRxErrors);
2021 CSR_READ_4(sc, STGE_OctetXmtdOk);
2023 ifp->if_opackets += CSR_READ_4(sc, STGE_FramesXmtdOk);
2025 ifp->if_collisions +=
2026 CSR_READ_4(sc, STGE_LateCollisions) +
2027 CSR_READ_4(sc, STGE_MultiColFrames) +
2028 CSR_READ_4(sc, STGE_SingleColFrames);
2031 CSR_READ_2(sc, STGE_FramesAbortXSColls) +
2032 CSR_READ_2(sc, STGE_FramesWEXDeferal);
2038 * Perform a soft reset on the TC9021.
2041 stge_reset(struct stge_softc *sc, uint32_t how)
2047 STGE_LOCK_ASSERT(sc);
2050 ac = CSR_READ_4(sc, STGE_AsicCtrl);
2053 ac |= AC_TxReset | AC_FIFO;
2057 ac |= AC_RxReset | AC_FIFO;
2060 case STGE_RESET_FULL:
2063 * Only assert RstOut if we're fiber. We need GMII clocks
2064 * to be present in order for the reset to complete on fiber
2067 ac |= AC_GlobalReset | AC_RxReset | AC_TxReset |
2068 AC_DMA | AC_FIFO | AC_Network | AC_Host | AC_AutoInit |
2069 (sc->sc_usefiber ? AC_RstOut : 0);
2073 CSR_WRITE_4(sc, STGE_AsicCtrl, ac);
2075 /* Account for reset problem at 10Mbps. */
2078 for (i = 0; i < STGE_TIMEOUT; i++) {
2079 if ((CSR_READ_4(sc, STGE_AsicCtrl) & AC_ResetBusy) == 0)
2084 if (i == STGE_TIMEOUT)
2085 device_printf(sc->sc_dev, "reset failed to complete\n");
2087 /* Set LED, from Linux IPG driver. */
2088 ac = CSR_READ_4(sc, STGE_AsicCtrl);
2089 ac &= ~(AC_LEDMode | AC_LEDSpeed | AC_LEDModeBit1);
2090 if ((sc->sc_led & 0x01) != 0)
2092 if ((sc->sc_led & 0x03) != 0)
2093 ac |= AC_LEDModeBit1;
2094 if ((sc->sc_led & 0x08) != 0)
2096 CSR_WRITE_4(sc, STGE_AsicCtrl, ac);
2098 /* Set PHY, from Linux IPG driver */
2099 v = CSR_READ_1(sc, STGE_PhySet);
2100 v &= ~(PS_MemLenb9b | PS_MemLen | PS_NonCompdet);
2101 v |= ((sc->sc_led & 0x70) >> 4);
2102 CSR_WRITE_1(sc, STGE_PhySet, v);
2106 * stge_init: [ ifnet interface function ]
2108 * Initialize the interface.
2111 stge_init(void *xsc)
2113 struct stge_softc *sc;
2115 sc = (struct stge_softc *)xsc;
2117 stge_init_locked(sc);
2122 stge_init_locked(struct stge_softc *sc)
2125 struct mii_data *mii;
2130 STGE_LOCK_ASSERT(sc);
2133 mii = device_get_softc(sc->sc_miibus);
2136 * Cancel any pending I/O.
2141 * Reset the chip to a known state.
2143 stge_reset(sc, STGE_RESET_FULL);
2145 /* Init descriptors. */
2146 error = stge_init_rx_ring(sc);
2148 device_printf(sc->sc_dev,
2149 "initialization failed: no memory for rx buffers\n");
2153 stge_init_tx_ring(sc);
2155 /* Set the station address. */
2156 bcopy(IF_LLADDR(ifp), eaddr, ETHER_ADDR_LEN);
2157 CSR_WRITE_2(sc, STGE_StationAddress0, htole16(eaddr[0]));
2158 CSR_WRITE_2(sc, STGE_StationAddress1, htole16(eaddr[1]));
2159 CSR_WRITE_2(sc, STGE_StationAddress2, htole16(eaddr[2]));
2162 * Set the statistics masks. Disable all the RMON stats,
2163 * and disable selected stats in the non-RMON stats registers.
2165 CSR_WRITE_4(sc, STGE_RMONStatisticsMask, 0xffffffff);
2166 CSR_WRITE_4(sc, STGE_StatisticsMask,
2167 (1U << 1) | (1U << 2) | (1U << 3) | (1U << 4) | (1U << 5) |
2168 (1U << 6) | (1U << 7) | (1U << 8) | (1U << 9) | (1U << 10) |
2169 (1U << 13) | (1U << 14) | (1U << 15) | (1U << 19) | (1U << 20) |
2172 /* Set up the receive filter. */
2173 stge_set_filter(sc);
2174 /* Program multicast filter. */
2178 * Give the transmit and receive ring to the chip.
2180 CSR_WRITE_4(sc, STGE_TFDListPtrHi,
2181 STGE_ADDR_HI(STGE_TX_RING_ADDR(sc, 0)));
2182 CSR_WRITE_4(sc, STGE_TFDListPtrLo,
2183 STGE_ADDR_LO(STGE_TX_RING_ADDR(sc, 0)));
2185 CSR_WRITE_4(sc, STGE_RFDListPtrHi,
2186 STGE_ADDR_HI(STGE_RX_RING_ADDR(sc, 0)));
2187 CSR_WRITE_4(sc, STGE_RFDListPtrLo,
2188 STGE_ADDR_LO(STGE_RX_RING_ADDR(sc, 0)));
2191 * Initialize the Tx auto-poll period. It's OK to make this number
2192 * large (255 is the max, but we use 127) -- we explicitly kick the
2193 * transmit engine when there's actually a packet.
2195 CSR_WRITE_1(sc, STGE_TxDMAPollPeriod, 127);
2197 /* ..and the Rx auto-poll period. */
2198 CSR_WRITE_1(sc, STGE_RxDMAPollPeriod, 1);
2200 /* Initialize the Tx start threshold. */
2201 CSR_WRITE_2(sc, STGE_TxStartThresh, sc->sc_txthresh);
2203 /* Rx DMA thresholds, from Linux */
2204 CSR_WRITE_1(sc, STGE_RxDMABurstThresh, 0x30);
2205 CSR_WRITE_1(sc, STGE_RxDMAUrgentThresh, 0x30);
2207 /* Rx early threhold, from Linux */
2208 CSR_WRITE_2(sc, STGE_RxEarlyThresh, 0x7ff);
2210 /* Tx DMA thresholds, from Linux */
2211 CSR_WRITE_1(sc, STGE_TxDMABurstThresh, 0x30);
2212 CSR_WRITE_1(sc, STGE_TxDMAUrgentThresh, 0x04);
2215 * Initialize the Rx DMA interrupt control register. We
2216 * request an interrupt after every incoming packet, but
2217 * defer it for sc_rxint_dmawait us. When the number of
2218 * interrupts pending reaches STGE_RXINT_NFRAME, we stop
2219 * deferring the interrupt, and signal it immediately.
2221 CSR_WRITE_4(sc, STGE_RxDMAIntCtrl,
2222 RDIC_RxFrameCount(sc->sc_rxint_nframe) |
2223 RDIC_RxDMAWaitTime(STGE_RXINT_USECS2TICK(sc->sc_rxint_dmawait)));
2226 * Initialize the interrupt mask.
2228 sc->sc_IntEnable = IS_HostError | IS_TxComplete |
2229 IS_TxDMAComplete | IS_RxDMAComplete | IS_RFDListEnd;
2230 #ifdef DEVICE_POLLING
2231 /* Disable interrupts if we are polling. */
2232 if ((ifp->if_capenable & IFCAP_POLLING) != 0)
2233 CSR_WRITE_2(sc, STGE_IntEnable, 0);
2236 CSR_WRITE_2(sc, STGE_IntEnable, sc->sc_IntEnable);
2239 * Configure the DMA engine.
2240 * XXX Should auto-tune TxBurstLimit.
2242 CSR_WRITE_4(sc, STGE_DMACtrl, sc->sc_DMACtrl | DMAC_TxBurstLimit(3));
2245 * Send a PAUSE frame when we reach 29,696 bytes in the Rx
2246 * FIFO, and send an un-PAUSE frame when we reach 3056 bytes
2249 CSR_WRITE_2(sc, STGE_FlowOnTresh, 29696 / 16);
2250 CSR_WRITE_2(sc, STGE_FlowOffThresh, 3056 / 16);
2253 * Set the maximum frame size.
2255 sc->sc_if_framesize = ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
2256 CSR_WRITE_2(sc, STGE_MaxFrameSize, sc->sc_if_framesize);
2259 * Initialize MacCtrl -- do it before setting the media,
2260 * as setting the media will actually program the register.
2262 * Note: We have to poke the IFS value before poking
2265 /* Tx/Rx MAC should be disabled before programming IFS.*/
2266 CSR_WRITE_4(sc, STGE_MACCtrl, MC_IFSSelect(MC_IFS96bit));
2268 stge_vlan_setup(sc);
2270 if (sc->sc_rev >= 6) { /* >= B.2 */
2271 /* Multi-frag frame bug work-around. */
2272 CSR_WRITE_2(sc, STGE_DebugCtrl,
2273 CSR_READ_2(sc, STGE_DebugCtrl) | 0x0200);
2275 /* Tx Poll Now bug work-around. */
2276 CSR_WRITE_2(sc, STGE_DebugCtrl,
2277 CSR_READ_2(sc, STGE_DebugCtrl) | 0x0010);
2278 /* Tx Poll Now bug work-around. */
2279 CSR_WRITE_2(sc, STGE_DebugCtrl,
2280 CSR_READ_2(sc, STGE_DebugCtrl) | 0x0020);
2283 v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK;
2284 v |= MC_StatisticsEnable | MC_TxEnable | MC_RxEnable;
2285 CSR_WRITE_4(sc, STGE_MACCtrl, v);
2287 * It seems that transmitting frames without checking the state of
2288 * Rx/Tx MAC wedge the hardware.
2295 * Set the current media.
2300 * Start the one second MII clock.
2302 callout_reset(&sc->sc_tick_ch, hz, stge_tick, sc);
2307 ifp->if_drv_flags |= IFF_DRV_RUNNING;
2308 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2312 device_printf(sc->sc_dev, "interface not running\n");
2316 stge_vlan_setup(struct stge_softc *sc)
2323 * The NIC always copy a VLAN tag regardless of STGE_MACCtrl
2324 * MC_AutoVLANuntagging bit.
2325 * MC_AutoVLANtagging bit selects which VLAN source to use
2326 * between STGE_VLANTag and TFC. However TFC TFD_VLANTagInsert
2327 * bit has priority over MC_AutoVLANtagging bit. So we always
2328 * use TFC instead of STGE_VLANTag register.
2330 v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK;
2331 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0)
2332 v |= MC_AutoVLANuntagging;
2334 v &= ~MC_AutoVLANuntagging;
2335 CSR_WRITE_4(sc, STGE_MACCtrl, v);
2339 * Stop transmission on the interface.
2342 stge_stop(struct stge_softc *sc)
2345 struct stge_txdesc *txd;
2346 struct stge_rxdesc *rxd;
2350 STGE_LOCK_ASSERT(sc);
2352 * Stop the one second clock.
2354 callout_stop(&sc->sc_tick_ch);
2355 sc->sc_watchdog_timer = 0;
2358 * Disable interrupts.
2360 CSR_WRITE_2(sc, STGE_IntEnable, 0);
2363 * Stop receiver, transmitter, and stats update.
2367 v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK;
2368 v |= MC_StatisticsDisable;
2369 CSR_WRITE_4(sc, STGE_MACCtrl, v);
2372 * Stop the transmit and receive DMA.
2375 CSR_WRITE_4(sc, STGE_TFDListPtrHi, 0);
2376 CSR_WRITE_4(sc, STGE_TFDListPtrLo, 0);
2377 CSR_WRITE_4(sc, STGE_RFDListPtrHi, 0);
2378 CSR_WRITE_4(sc, STGE_RFDListPtrLo, 0);
2381 * Free RX and TX mbufs still in the queues.
2383 for (i = 0; i < STGE_RX_RING_CNT; i++) {
2384 rxd = &sc->sc_cdata.stge_rxdesc[i];
2385 if (rxd->rx_m != NULL) {
2386 bus_dmamap_sync(sc->sc_cdata.stge_rx_tag,
2387 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD);
2388 bus_dmamap_unload(sc->sc_cdata.stge_rx_tag,
2394 for (i = 0; i < STGE_TX_RING_CNT; i++) {
2395 txd = &sc->sc_cdata.stge_txdesc[i];
2396 if (txd->tx_m != NULL) {
2397 bus_dmamap_sync(sc->sc_cdata.stge_tx_tag,
2398 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE);
2399 bus_dmamap_unload(sc->sc_cdata.stge_tx_tag,
2407 * Mark the interface down and cancel the watchdog timer.
2410 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
2415 stge_start_tx(struct stge_softc *sc)
2420 v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK;
2421 if ((v & MC_TxEnabled) != 0)
2424 CSR_WRITE_4(sc, STGE_MACCtrl, v);
2425 CSR_WRITE_1(sc, STGE_TxDMAPollPeriod, 127);
2426 for (i = STGE_TIMEOUT; i > 0; i--) {
2428 v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK;
2429 if ((v & MC_TxEnabled) != 0)
2433 device_printf(sc->sc_dev, "Starting Tx MAC timed out\n");
2437 stge_start_rx(struct stge_softc *sc)
2442 v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK;
2443 if ((v & MC_RxEnabled) != 0)
2446 CSR_WRITE_4(sc, STGE_MACCtrl, v);
2447 CSR_WRITE_1(sc, STGE_RxDMAPollPeriod, 1);
2448 for (i = STGE_TIMEOUT; i > 0; i--) {
2450 v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK;
2451 if ((v & MC_RxEnabled) != 0)
2455 device_printf(sc->sc_dev, "Starting Rx MAC timed out\n");
2459 stge_stop_tx(struct stge_softc *sc)
2464 v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK;
2465 if ((v & MC_TxEnabled) == 0)
2468 CSR_WRITE_4(sc, STGE_MACCtrl, v);
2469 for (i = STGE_TIMEOUT; i > 0; i--) {
2471 v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK;
2472 if ((v & MC_TxEnabled) == 0)
2476 device_printf(sc->sc_dev, "Stopping Tx MAC timed out\n");
2480 stge_stop_rx(struct stge_softc *sc)
2485 v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK;
2486 if ((v & MC_RxEnabled) == 0)
2489 CSR_WRITE_4(sc, STGE_MACCtrl, v);
2490 for (i = STGE_TIMEOUT; i > 0; i--) {
2492 v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK;
2493 if ((v & MC_RxEnabled) == 0)
2497 device_printf(sc->sc_dev, "Stopping Rx MAC timed out\n");
2501 stge_init_tx_ring(struct stge_softc *sc)
2503 struct stge_ring_data *rd;
2504 struct stge_txdesc *txd;
2508 STAILQ_INIT(&sc->sc_cdata.stge_txfreeq);
2509 STAILQ_INIT(&sc->sc_cdata.stge_txbusyq);
2511 sc->sc_cdata.stge_tx_prod = 0;
2512 sc->sc_cdata.stge_tx_cons = 0;
2513 sc->sc_cdata.stge_tx_cnt = 0;
2516 bzero(rd->stge_tx_ring, STGE_TX_RING_SZ);
2517 for (i = 0; i < STGE_TX_RING_CNT; i++) {
2518 if (i == (STGE_TX_RING_CNT - 1))
2519 addr = STGE_TX_RING_ADDR(sc, 0);
2521 addr = STGE_TX_RING_ADDR(sc, i + 1);
2522 rd->stge_tx_ring[i].tfd_next = htole64(addr);
2523 rd->stge_tx_ring[i].tfd_control = htole64(TFD_TFDDone);
2524 txd = &sc->sc_cdata.stge_txdesc[i];
2525 STAILQ_INSERT_TAIL(&sc->sc_cdata.stge_txfreeq, txd, tx_q);
2528 bus_dmamap_sync(sc->sc_cdata.stge_tx_ring_tag,
2529 sc->sc_cdata.stge_tx_ring_map,
2530 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2535 stge_init_rx_ring(struct stge_softc *sc)
2537 struct stge_ring_data *rd;
2541 sc->sc_cdata.stge_rx_cons = 0;
2542 STGE_RXCHAIN_RESET(sc);
2545 bzero(rd->stge_rx_ring, STGE_RX_RING_SZ);
2546 for (i = 0; i < STGE_RX_RING_CNT; i++) {
2547 if (stge_newbuf(sc, i) != 0)
2549 if (i == (STGE_RX_RING_CNT - 1))
2550 addr = STGE_RX_RING_ADDR(sc, 0);
2552 addr = STGE_RX_RING_ADDR(sc, i + 1);
2553 rd->stge_rx_ring[i].rfd_next = htole64(addr);
2554 rd->stge_rx_ring[i].rfd_status = 0;
2557 bus_dmamap_sync(sc->sc_cdata.stge_rx_ring_tag,
2558 sc->sc_cdata.stge_rx_ring_map,
2559 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2567 * Add a receive buffer to the indicated descriptor.
2570 stge_newbuf(struct stge_softc *sc, int idx)
2572 struct stge_rxdesc *rxd;
2573 struct stge_rfd *rfd;
2575 bus_dma_segment_t segs[1];
2579 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
2582 m->m_len = m->m_pkthdr.len = MCLBYTES;
2584 * The hardware requires 4bytes aligned DMA address when JUMBO
2587 if (sc->sc_if_framesize <= (MCLBYTES - ETHER_ALIGN))
2588 m_adj(m, ETHER_ALIGN);
2590 if (bus_dmamap_load_mbuf_sg(sc->sc_cdata.stge_rx_tag,
2591 sc->sc_cdata.stge_rx_sparemap, m, segs, &nsegs, 0) != 0) {
2595 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
2597 rxd = &sc->sc_cdata.stge_rxdesc[idx];
2598 if (rxd->rx_m != NULL) {
2599 bus_dmamap_sync(sc->sc_cdata.stge_rx_tag, rxd->rx_dmamap,
2600 BUS_DMASYNC_POSTREAD);
2601 bus_dmamap_unload(sc->sc_cdata.stge_rx_tag, rxd->rx_dmamap);
2603 map = rxd->rx_dmamap;
2604 rxd->rx_dmamap = sc->sc_cdata.stge_rx_sparemap;
2605 sc->sc_cdata.stge_rx_sparemap = map;
2606 bus_dmamap_sync(sc->sc_cdata.stge_rx_tag, rxd->rx_dmamap,
2607 BUS_DMASYNC_PREREAD);
2610 rfd = &sc->sc_rdata.stge_rx_ring[idx];
2611 rfd->rfd_frag.frag_word0 =
2612 htole64(FRAG_ADDR(segs[0].ds_addr) | FRAG_LEN(segs[0].ds_len));
2613 rfd->rfd_status = 0;
2621 * Set up the receive filter.
2624 stge_set_filter(struct stge_softc *sc)
2629 STGE_LOCK_ASSERT(sc);
2633 mode = CSR_READ_2(sc, STGE_ReceiveMode);
2634 mode |= RM_ReceiveUnicast;
2635 if ((ifp->if_flags & IFF_BROADCAST) != 0)
2636 mode |= RM_ReceiveBroadcast;
2638 mode &= ~RM_ReceiveBroadcast;
2639 if ((ifp->if_flags & IFF_PROMISC) != 0)
2640 mode |= RM_ReceiveAllFrames;
2642 mode &= ~RM_ReceiveAllFrames;
2644 CSR_WRITE_2(sc, STGE_ReceiveMode, mode);
2648 stge_set_multi(struct stge_softc *sc)
2651 struct ifmultiaddr *ifma;
2657 STGE_LOCK_ASSERT(sc);
2661 mode = CSR_READ_2(sc, STGE_ReceiveMode);
2662 if ((ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) != 0) {
2663 if ((ifp->if_flags & IFF_PROMISC) != 0)
2664 mode |= RM_ReceiveAllFrames;
2665 else if ((ifp->if_flags & IFF_ALLMULTI) != 0)
2666 mode |= RM_ReceiveMulticast;
2667 CSR_WRITE_2(sc, STGE_ReceiveMode, mode);
2671 /* clear existing filters. */
2672 CSR_WRITE_4(sc, STGE_HashTable0, 0);
2673 CSR_WRITE_4(sc, STGE_HashTable1, 0);
2676 * Set up the multicast address filter by passing all multicast
2677 * addresses through a CRC generator, and then using the low-order
2678 * 6 bits as an index into the 64 bit multicast hash table. The
2679 * high order bits select the register, while the rest of the bits
2680 * select the bit within the register.
2683 bzero(mchash, sizeof(mchash));
2686 if_maddr_rlock(sc->sc_ifp);
2687 TAILQ_FOREACH(ifma, &sc->sc_ifp->if_multiaddrs, ifma_link) {
2688 if (ifma->ifma_addr->sa_family != AF_LINK)
2690 crc = ether_crc32_be(LLADDR((struct sockaddr_dl *)
2691 ifma->ifma_addr), ETHER_ADDR_LEN);
2693 /* Just want the 6 least significant bits. */
2696 /* Set the corresponding bit in the hash table. */
2697 mchash[crc >> 5] |= 1 << (crc & 0x1f);
2700 if_maddr_runlock(ifp);
2702 mode &= ~(RM_ReceiveMulticast | RM_ReceiveAllFrames);
2704 mode |= RM_ReceiveMulticastHash;
2706 mode &= ~RM_ReceiveMulticastHash;
2708 CSR_WRITE_4(sc, STGE_HashTable0, mchash[0]);
2709 CSR_WRITE_4(sc, STGE_HashTable1, mchash[1]);
2710 CSR_WRITE_2(sc, STGE_ReceiveMode, mode);
2714 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high)
2720 value = *(int *)arg1;
2721 error = sysctl_handle_int(oidp, &value, 0, req);
2722 if (error || !req->newptr)
2724 if (value < low || value > high)
2726 *(int *)arg1 = value;
2732 sysctl_hw_stge_rxint_nframe(SYSCTL_HANDLER_ARGS)
2734 return (sysctl_int_range(oidp, arg1, arg2, req,
2735 STGE_RXINT_NFRAME_MIN, STGE_RXINT_NFRAME_MAX));
2739 sysctl_hw_stge_rxint_dmawait(SYSCTL_HANDLER_ARGS)
2741 return (sysctl_int_range(oidp, arg1, arg2, req,
2742 STGE_RXINT_DMAWAIT_MIN, STGE_RXINT_DMAWAIT_MAX));