2 * Copyright (c) 2003 Marcel Moolenaar
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
30 #include <sys/param.h>
31 #include <sys/systm.h>
34 #include <machine/bus.h>
36 #include <dev/uart/uart.h>
37 #include <dev/uart/uart_cpu.h>
38 #include <dev/uart/uart_bus.h>
40 #include <dev/ic/ns16550.h>
44 #define DEFAULT_RCLK 1843200
47 * Clear pending interrupts. THRE is cleared by reading IIR. Data
48 * that may have been received gets lost here.
51 ns8250_clrint(struct uart_bas *bas)
55 iir = uart_getreg(bas, REG_IIR);
56 while ((iir & IIR_NOPEND) == 0) {
59 lsr = uart_getreg(bas, REG_LSR);
60 if (lsr & (LSR_BI|LSR_FE|LSR_PE))
61 (void)uart_getreg(bas, REG_DATA);
62 } else if (iir == IIR_RXRDY || iir == IIR_RXTOUT)
63 (void)uart_getreg(bas, REG_DATA);
64 else if (iir == IIR_MLSC)
65 (void)uart_getreg(bas, REG_MSR);
67 iir = uart_getreg(bas, REG_IIR);
72 ns8250_delay(struct uart_bas *bas)
77 lcr = uart_getreg(bas, REG_LCR);
78 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB);
80 divisor = uart_getreg(bas, REG_DLL) | (uart_getreg(bas, REG_DLH) << 8);
82 uart_setreg(bas, REG_LCR, lcr);
85 /* 1/10th the time to transmit 1 character (estimate). */
87 return (16000000 * divisor / bas->rclk);
88 return (16000 * divisor / (bas->rclk / 1000));
92 ns8250_divisor(int rclk, int baudrate)
94 int actual_baud, divisor;
100 divisor = (rclk / (baudrate << 3) + 1) >> 1;
101 if (divisor == 0 || divisor >= 65536)
103 actual_baud = rclk / (divisor << 4);
105 /* 10 times error in percent: */
106 error = ((actual_baud - baudrate) * 2000 / baudrate + 1) >> 1;
108 /* 3.0% maximum error tolerance: */
109 if (error < -30 || error > 30)
116 ns8250_drain(struct uart_bas *bas, int what)
120 delay = ns8250_delay(bas);
122 if (what & UART_DRAIN_TRANSMITTER) {
124 * Pick an arbitrary high limit to avoid getting stuck in
125 * an infinite loop when the hardware is broken. Make the
126 * limit high enough to handle large FIFOs.
129 while ((uart_getreg(bas, REG_LSR) & LSR_TEMT) == 0 && --limit)
132 /* printf("ns8250: transmitter appears stuck... "); */
137 if (what & UART_DRAIN_RECEIVER) {
139 * Pick an arbitrary high limit to avoid getting stuck in
140 * an infinite loop when the hardware is broken. Make the
141 * limit high enough to handle large FIFOs and integrated
142 * UARTs. The HP rx2600 for example has 3 UARTs on the
143 * management board that tend to get a lot of data send
144 * to it when the UART is first activated.
147 while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) && --limit) {
148 (void)uart_getreg(bas, REG_DATA);
153 /* printf("ns8250: receiver appears broken... "); */
162 * We can only flush UARTs with FIFOs. UARTs without FIFOs should be
163 * drained. WARNING: this function clobbers the FIFO setting!
166 ns8250_flush(struct uart_bas *bas, int what)
171 if (what & UART_FLUSH_TRANSMITTER)
173 if (what & UART_FLUSH_RECEIVER)
175 uart_setreg(bas, REG_FCR, fcr);
180 ns8250_param(struct uart_bas *bas, int baudrate, int databits, int stopbits,
189 else if (databits == 7)
191 else if (databits == 6)
201 divisor = ns8250_divisor(bas->rclk, baudrate);
204 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB);
206 uart_setreg(bas, REG_DLL, divisor & 0xff);
207 uart_setreg(bas, REG_DLH, (divisor >> 8) & 0xff);
211 /* Set LCR and clear DLAB. */
212 uart_setreg(bas, REG_LCR, lcr);
218 * Low-level UART interface.
220 static int ns8250_probe(struct uart_bas *bas);
221 static void ns8250_init(struct uart_bas *bas, int, int, int, int);
222 static void ns8250_term(struct uart_bas *bas);
223 static void ns8250_putc(struct uart_bas *bas, int);
224 static int ns8250_rxready(struct uart_bas *bas);
225 static int ns8250_getc(struct uart_bas *bas, struct mtx *);
227 static struct uart_ops uart_ns8250_ops = {
228 .probe = ns8250_probe,
232 .rxready = ns8250_rxready,
237 ns8250_probe(struct uart_bas *bas)
241 /* Check known 0 bits that don't depend on DLAB. */
242 val = uart_getreg(bas, REG_IIR);
245 val = uart_getreg(bas, REG_MCR);
253 ns8250_init(struct uart_bas *bas, int baudrate, int databits, int stopbits,
259 bas->rclk = DEFAULT_RCLK;
260 ns8250_param(bas, baudrate, databits, stopbits, parity);
262 /* Disable all interrupt sources. */
264 * We use 0xe0 instead of 0xf0 as the mask because the XScale PXA
265 * UARTs split the receive time-out interrupt bit out separately as
266 * 0x10. This gets handled by ier_mask and ier_rxbits below.
268 ier = uart_getreg(bas, REG_IER) & 0xe0;
269 uart_setreg(bas, REG_IER, ier);
272 /* Disable the FIFO (if present). */
273 uart_setreg(bas, REG_FCR, 0);
277 uart_setreg(bas, REG_MCR, MCR_IE | MCR_RTS | MCR_DTR);
284 ns8250_term(struct uart_bas *bas)
287 /* Clear RTS & DTR. */
288 uart_setreg(bas, REG_MCR, MCR_IE);
293 ns8250_putc(struct uart_bas *bas, int c)
298 while ((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0 && --limit)
300 uart_setreg(bas, REG_DATA, c);
303 while ((uart_getreg(bas, REG_LSR) & LSR_TEMT) == 0 && --limit)
308 ns8250_rxready(struct uart_bas *bas)
311 return ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) != 0 ? 1 : 0);
315 ns8250_getc(struct uart_bas *bas, struct mtx *hwmtx)
321 while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) == 0) {
327 c = uart_getreg(bas, REG_DATA);
335 * High-level UART interface.
337 struct ns8250_softc {
338 struct uart_softc base;
347 static int ns8250_bus_attach(struct uart_softc *);
348 static int ns8250_bus_detach(struct uart_softc *);
349 static int ns8250_bus_flush(struct uart_softc *, int);
350 static int ns8250_bus_getsig(struct uart_softc *);
351 static int ns8250_bus_ioctl(struct uart_softc *, int, intptr_t);
352 static int ns8250_bus_ipend(struct uart_softc *);
353 static int ns8250_bus_param(struct uart_softc *, int, int, int, int);
354 static int ns8250_bus_probe(struct uart_softc *);
355 static int ns8250_bus_receive(struct uart_softc *);
356 static int ns8250_bus_setsig(struct uart_softc *, int);
357 static int ns8250_bus_transmit(struct uart_softc *);
359 static kobj_method_t ns8250_methods[] = {
360 KOBJMETHOD(uart_attach, ns8250_bus_attach),
361 KOBJMETHOD(uart_detach, ns8250_bus_detach),
362 KOBJMETHOD(uart_flush, ns8250_bus_flush),
363 KOBJMETHOD(uart_getsig, ns8250_bus_getsig),
364 KOBJMETHOD(uart_ioctl, ns8250_bus_ioctl),
365 KOBJMETHOD(uart_ipend, ns8250_bus_ipend),
366 KOBJMETHOD(uart_param, ns8250_bus_param),
367 KOBJMETHOD(uart_probe, ns8250_bus_probe),
368 KOBJMETHOD(uart_receive, ns8250_bus_receive),
369 KOBJMETHOD(uart_setsig, ns8250_bus_setsig),
370 KOBJMETHOD(uart_transmit, ns8250_bus_transmit),
374 struct uart_class uart_ns8250_class = {
377 sizeof(struct ns8250_softc),
378 .uc_ops = &uart_ns8250_ops,
380 .uc_rclk = DEFAULT_RCLK
383 #define SIGCHG(c, i, s, d) \
385 i |= (i & s) ? s : s | d; \
387 i = (i & s) ? (i & ~s) | d : i; \
391 ns8250_bus_attach(struct uart_softc *sc)
393 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc;
394 struct uart_bas *bas;
399 ns8250->mcr = uart_getreg(bas, REG_MCR);
400 ns8250->fcr = FCR_ENABLE;
401 if (!resource_int_value("uart", device_get_unit(sc->sc_dev), "flags",
403 if (UART_FLAGS_FCR_RX_LOW(ivar))
404 ns8250->fcr |= FCR_RX_LOW;
405 else if (UART_FLAGS_FCR_RX_MEDL(ivar))
406 ns8250->fcr |= FCR_RX_MEDL;
407 else if (UART_FLAGS_FCR_RX_HIGH(ivar))
408 ns8250->fcr |= FCR_RX_HIGH;
410 ns8250->fcr |= FCR_RX_MEDH;
412 ns8250->fcr |= FCR_RX_MEDH;
416 resource_int_value("uart", device_get_unit(sc->sc_dev), "ier_mask",
418 ns8250->ier_mask = (uint8_t)(ivar & 0xff);
420 /* Get IER RX interrupt bits */
421 ivar = IER_EMSC | IER_ERLS | IER_ERXRDY;
422 resource_int_value("uart", device_get_unit(sc->sc_dev), "ier_rxbits",
424 ns8250->ier_rxbits = (uint8_t)(ivar & 0xff);
426 uart_setreg(bas, REG_FCR, ns8250->fcr);
428 ns8250_bus_flush(sc, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER);
430 if (ns8250->mcr & MCR_DTR)
431 sc->sc_hwsig |= SER_DTR;
432 if (ns8250->mcr & MCR_RTS)
433 sc->sc_hwsig |= SER_RTS;
434 ns8250_bus_getsig(sc);
437 ns8250->ier = uart_getreg(bas, REG_IER) & ns8250->ier_mask;
438 ns8250->ier |= ns8250->ier_rxbits;
439 uart_setreg(bas, REG_IER, ns8250->ier);
446 ns8250_bus_detach(struct uart_softc *sc)
448 struct ns8250_softc *ns8250;
449 struct uart_bas *bas;
452 ns8250 = (struct ns8250_softc *)sc;
454 ier = uart_getreg(bas, REG_IER) & ns8250->ier_mask;
455 uart_setreg(bas, REG_IER, ier);
462 ns8250_bus_flush(struct uart_softc *sc, int what)
464 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc;
465 struct uart_bas *bas;
469 uart_lock(sc->sc_hwmtx);
470 if (sc->sc_rxfifosz > 1) {
471 ns8250_flush(bas, what);
472 uart_setreg(bas, REG_FCR, ns8250->fcr);
476 error = ns8250_drain(bas, what);
477 uart_unlock(sc->sc_hwmtx);
482 ns8250_bus_getsig(struct uart_softc *sc)
484 uint32_t new, old, sig;
490 uart_lock(sc->sc_hwmtx);
491 msr = uart_getreg(&sc->sc_bas, REG_MSR);
492 uart_unlock(sc->sc_hwmtx);
493 SIGCHG(msr & MSR_DSR, sig, SER_DSR, SER_DDSR);
494 SIGCHG(msr & MSR_CTS, sig, SER_CTS, SER_DCTS);
495 SIGCHG(msr & MSR_DCD, sig, SER_DCD, SER_DDCD);
496 SIGCHG(msr & MSR_RI, sig, SER_RI, SER_DRI);
497 new = sig & ~SER_MASK_DELTA;
498 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new));
503 ns8250_bus_ioctl(struct uart_softc *sc, int request, intptr_t data)
505 struct uart_bas *bas;
506 int baudrate, divisor, error;
511 uart_lock(sc->sc_hwmtx);
513 case UART_IOCTL_BREAK:
514 lcr = uart_getreg(bas, REG_LCR);
519 uart_setreg(bas, REG_LCR, lcr);
522 case UART_IOCTL_IFLOW:
523 lcr = uart_getreg(bas, REG_LCR);
525 uart_setreg(bas, REG_LCR, 0xbf);
527 efr = uart_getreg(bas, REG_EFR);
532 uart_setreg(bas, REG_EFR, efr);
534 uart_setreg(bas, REG_LCR, lcr);
537 case UART_IOCTL_OFLOW:
538 lcr = uart_getreg(bas, REG_LCR);
540 uart_setreg(bas, REG_LCR, 0xbf);
542 efr = uart_getreg(bas, REG_EFR);
547 uart_setreg(bas, REG_EFR, efr);
549 uart_setreg(bas, REG_LCR, lcr);
552 case UART_IOCTL_BAUD:
553 lcr = uart_getreg(bas, REG_LCR);
554 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB);
556 divisor = uart_getreg(bas, REG_DLL) |
557 (uart_getreg(bas, REG_DLH) << 8);
559 uart_setreg(bas, REG_LCR, lcr);
561 baudrate = (divisor > 0) ? bas->rclk / divisor / 16 : 0;
563 *(int*)data = baudrate;
571 uart_unlock(sc->sc_hwmtx);
576 ns8250_bus_ipend(struct uart_softc *sc)
578 struct uart_bas *bas;
583 uart_lock(sc->sc_hwmtx);
584 iir = uart_getreg(bas, REG_IIR);
585 if (iir & IIR_NOPEND) {
586 uart_unlock(sc->sc_hwmtx);
590 if (iir & IIR_RXRDY) {
591 lsr = uart_getreg(bas, REG_LSR);
593 ipend |= SER_INT_OVERRUN;
595 ipend |= SER_INT_BREAK;
597 ipend |= SER_INT_RXREADY;
600 ipend |= SER_INT_TXIDLE;
602 ipend |= SER_INT_SIGCHG;
606 uart_unlock(sc->sc_hwmtx);
611 ns8250_bus_param(struct uart_softc *sc, int baudrate, int databits,
612 int stopbits, int parity)
614 struct uart_bas *bas;
618 uart_lock(sc->sc_hwmtx);
619 error = ns8250_param(bas, baudrate, databits, stopbits, parity);
620 uart_unlock(sc->sc_hwmtx);
625 ns8250_bus_probe(struct uart_softc *sc)
627 struct ns8250_softc *ns8250;
628 struct uart_bas *bas;
629 int count, delay, error, limit;
630 uint8_t lsr, mcr, ier;
632 ns8250 = (struct ns8250_softc *)sc;
635 error = ns8250_probe(bas);
640 if (sc->sc_sysdev == NULL) {
641 /* By using ns8250_init() we also set DTR and RTS. */
642 ns8250_init(bas, 115200, 8, 1, UART_PARITY_NONE);
644 mcr |= MCR_DTR | MCR_RTS;
646 error = ns8250_drain(bas, UART_DRAIN_TRANSMITTER);
651 * Set loopback mode. This avoids having garbage on the wire and
652 * also allows us send and receive data. We set DTR and RTS to
653 * avoid the possibility that automatic flow-control prevents
654 * any data from being sent.
656 uart_setreg(bas, REG_MCR, MCR_LOOPBACK | MCR_IE | MCR_DTR | MCR_RTS);
660 * Enable FIFOs. And check that the UART has them. If not, we're
661 * done. Since this is the first time we enable the FIFOs, we reset
664 uart_setreg(bas, REG_FCR, FCR_ENABLE);
666 if (!(uart_getreg(bas, REG_IIR) & IIR_FIFO_MASK)) {
668 * NS16450 or INS8250. We don't bother to differentiate
669 * between them. They're too old to be interesting.
671 uart_setreg(bas, REG_MCR, mcr);
673 sc->sc_rxfifosz = sc->sc_txfifosz = 1;
674 device_set_desc(sc->sc_dev, "8250 or 16450 or compatible");
678 uart_setreg(bas, REG_FCR, FCR_ENABLE | FCR_XMT_RST | FCR_RCV_RST);
682 delay = ns8250_delay(bas);
684 /* We have FIFOs. Drain the transmitter and receiver. */
685 error = ns8250_drain(bas, UART_DRAIN_RECEIVER|UART_DRAIN_TRANSMITTER);
687 uart_setreg(bas, REG_MCR, mcr);
688 uart_setreg(bas, REG_FCR, 0);
694 * We should have a sufficiently clean "pipe" to determine the
695 * size of the FIFOs. We send as much characters as is reasonable
696 * and wait for the the overflow bit in the LSR register to be
697 * asserted, counting the characters as we send them. Based on
698 * that count we know the FIFO size.
701 uart_setreg(bas, REG_DATA, 0);
708 * LSR bits are cleared upon read, so we must accumulate
709 * them to be able to test LSR_OE below.
711 while (((lsr |= uart_getreg(bas, REG_LSR)) & LSR_TEMT) == 0 &&
715 ier = uart_getreg(bas, REG_IER) & ns8250->ier_mask;
716 uart_setreg(bas, REG_IER, ier);
717 uart_setreg(bas, REG_MCR, mcr);
718 uart_setreg(bas, REG_FCR, 0);
723 } while ((lsr & LSR_OE) == 0 && count < 130);
726 uart_setreg(bas, REG_MCR, mcr);
729 ns8250_flush(bas, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER);
732 if (count >= 14 && count <= 16) {
733 sc->sc_rxfifosz = 16;
734 device_set_desc(sc->sc_dev, "16550 or compatible");
735 } else if (count >= 28 && count <= 32) {
736 sc->sc_rxfifosz = 32;
737 device_set_desc(sc->sc_dev, "16650 or compatible");
738 } else if (count >= 56 && count <= 64) {
739 sc->sc_rxfifosz = 64;
740 device_set_desc(sc->sc_dev, "16750 or compatible");
741 } else if (count >= 112 && count <= 128) {
742 sc->sc_rxfifosz = 128;
743 device_set_desc(sc->sc_dev, "16950 or compatible");
745 sc->sc_rxfifosz = 16;
746 device_set_desc(sc->sc_dev,
747 "Non-standard ns8250 class UART with FIFOs");
751 * Force the Tx FIFO size to 16 bytes for now. We don't program the
752 * Tx trigger. Also, we assume that all data has been sent when the
755 sc->sc_txfifosz = 16;
759 * XXX there are some issues related to hardware flow control and
760 * it's likely that uart(4) is the cause. This basicly needs more
761 * investigation, but we avoid using for hardware flow control
764 /* 16650s or higher have automatic flow control. */
765 if (sc->sc_rxfifosz > 16) {
775 ns8250_bus_receive(struct uart_softc *sc)
777 struct uart_bas *bas;
782 uart_lock(sc->sc_hwmtx);
783 lsr = uart_getreg(bas, REG_LSR);
784 while (lsr & LSR_RXRDY) {
785 if (uart_rx_full(sc)) {
786 sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN;
789 xc = uart_getreg(bas, REG_DATA);
791 xc |= UART_STAT_FRAMERR;
793 xc |= UART_STAT_PARERR;
795 lsr = uart_getreg(bas, REG_LSR);
797 /* Discard everything left in the Rx FIFO. */
798 while (lsr & LSR_RXRDY) {
799 (void)uart_getreg(bas, REG_DATA);
801 lsr = uart_getreg(bas, REG_LSR);
803 uart_unlock(sc->sc_hwmtx);
808 ns8250_bus_setsig(struct uart_softc *sc, int sig)
810 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc;
811 struct uart_bas *bas;
818 if (sig & SER_DDTR) {
819 SIGCHG(sig & SER_DTR, new, SER_DTR,
822 if (sig & SER_DRTS) {
823 SIGCHG(sig & SER_RTS, new, SER_RTS,
826 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new));
827 uart_lock(sc->sc_hwmtx);
828 ns8250->mcr &= ~(MCR_DTR|MCR_RTS);
830 ns8250->mcr |= MCR_DTR;
832 ns8250->mcr |= MCR_RTS;
833 uart_setreg(bas, REG_MCR, ns8250->mcr);
835 uart_unlock(sc->sc_hwmtx);
840 ns8250_bus_transmit(struct uart_softc *sc)
842 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc;
843 struct uart_bas *bas;
847 uart_lock(sc->sc_hwmtx);
848 while ((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0)
850 uart_setreg(bas, REG_IER, ns8250->ier | IER_ETXRDY);
852 for (i = 0; i < sc->sc_txdatasz; i++) {
853 uart_setreg(bas, REG_DATA, sc->sc_txbuf[i]);
857 uart_unlock(sc->sc_hwmtx);