sys/dev/usb/controller/atmegadci.c

   1 #include <sys/cdefs.h>
   2 __FBSDID("$FreeBSD$");
   3
   4 /*-
   5  * Copyright (c) 2009 Hans Petter Selasky. All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice, this list of conditions and the following disclaimer.
  12  * 2. Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the distribution.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  17  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  19  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  20  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  21  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  22  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  23  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  24  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  25  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  26  * SUCH DAMAGE.
  27  */
  28
  29 /*
  30  * This file contains the driver for the ATMEGA series USB OTG Controller. This
  31  * driver currently only supports the DCI mode of the USB hardware.
  32  */
  33
  34 /*
  35  * NOTE: When the chip detects BUS-reset it will also reset the
  36  * endpoints, Function-address and more.
  37  */
  38
  39 #include <sys/stdint.h>
  40 #include <sys/stddef.h>
  41 #include <sys/param.h>
  42 #include <sys/queue.h>
  43 #include <sys/types.h>
  44 #include <sys/systm.h>
  45 #include <sys/kernel.h>
  46 #include <sys/bus.h>
  47 #include <sys/linker_set.h>
  48 #include <sys/module.h>
  49 #include <sys/lock.h>
  50 #include <sys/mutex.h>
  51 #include <sys/condvar.h>
  52 #include <sys/sysctl.h>
  53 #include <sys/sx.h>
  54 #include <sys/unistd.h>
  55 #include <sys/callout.h>
  56 #include <sys/malloc.h>
  57 #include <sys/priv.h>
  58
  59 #include <dev/usb/usb.h>
  60 #include <dev/usb/usbdi.h>
  61
  62 #define USB_DEBUG_VAR atmegadci_debug
  63
  64 #include <dev/usb/usb_core.h>
  65 #include <dev/usb/usb_debug.h>
  66 #include <dev/usb/usb_busdma.h>
  67 #include <dev/usb/usb_process.h>
  68 #include <dev/usb/usb_transfer.h>
  69 #include <dev/usb/usb_device.h>
  70 #include <dev/usb/usb_hub.h>
  71 #include <dev/usb/usb_util.h>
  72
  73 #include <dev/usb/usb_controller.h>
  74 #include <dev/usb/usb_bus.h>
  75 #include <dev/usb/controller/atmegadci.h>
  76
  77 #define ATMEGA_BUS2SC(bus) \
  78    ((struct atmegadci_softc *)(((uint8_t *)(bus)) - \
  79     ((uint8_t *)&(((struct atmegadci_softc *)0)->sc_bus))))
  80
  81 #define ATMEGA_PC2SC(pc) \
  82    ATMEGA_BUS2SC(USB_DMATAG_TO_XROOT((pc)->tag_parent)->bus)
  83
  84 #ifdef USB_DEBUG
  85 static int atmegadci_debug = 0;
  86
  87 SYSCTL_NODE(_hw_usb, OID_AUTO, atmegadci, CTLFLAG_RW, 0, "USB ATMEGA DCI");
  88 SYSCTL_INT(_hw_usb_atmegadci, OID_AUTO, debug, CTLFLAG_RW,
  89     &atmegadci_debug, 0, "ATMEGA DCI debug level");
  90 #endif
  91
  92 #define ATMEGA_INTR_ENDPT 1
  93
  94 /* prototypes */
  95
  96 struct usb_bus_methods atmegadci_bus_methods;
  97 struct usb_pipe_methods atmegadci_device_non_isoc_methods;
  98 struct usb_pipe_methods atmegadci_device_isoc_fs_methods;
  99
 100 static atmegadci_cmd_t atmegadci_setup_rx;
 101 static atmegadci_cmd_t atmegadci_data_rx;
 102 static atmegadci_cmd_t atmegadci_data_tx;
 103 static atmegadci_cmd_t atmegadci_data_tx_sync;
 104 static void atmegadci_device_done(struct usb_xfer *, usb_error_t);
 105 static void atmegadci_do_poll(struct usb_bus *);
 106 static void atmegadci_standard_done(struct usb_xfer *);
 107 static void atmegadci_root_intr(struct atmegadci_softc *sc);
 108
 109 /*
 110  * Here is a list of what the chip supports:
 111  */
 112 static const struct usb_hw_ep_profile
 113         atmegadci_ep_profile[2] = {
 114
 115         [0] = {
 116                 .max_in_frame_size = 64,
 117                 .max_out_frame_size = 64,
 118                 .is_simplex = 1,
 119                 .support_control = 1,
 120         },
 121         [1] = {
 122                 .max_in_frame_size = 64,
 123                 .max_out_frame_size = 64,
 124                 .is_simplex = 1,
 125                 .support_bulk = 1,
 126                 .support_interrupt = 1,
 127                 .support_isochronous = 1,
 128                 .support_in = 1,
 129                 .support_out = 1,
 130         },
 131 };
 132
 133 static void
 134 atmegadci_get_hw_ep_profile(struct usb_device *udev,
 135     const struct usb_hw_ep_profile **ppf, uint8_t ep_addr)
 136 {
 137         if (ep_addr == 0)
 138                 *ppf = atmegadci_ep_profile;
 139         else if (ep_addr < ATMEGA_EP_MAX)
 140                 *ppf = atmegadci_ep_profile + 1;
 141         else
 142                 *ppf = NULL;
 143 }
 144
 145 static void
 146 atmegadci_clocks_on(struct atmegadci_softc *sc)
 147 {
 148         if (sc->sc_flags.clocks_off &&
 149             sc->sc_flags.port_powered) {
 150
 151                 DPRINTFN(5, "\n");
 152
 153                 /* turn on clocks */
 154                 (sc->sc_clocks_on) (&sc->sc_bus);
 155
 156                 ATMEGA_WRITE_1(sc, ATMEGA_USBCON,
 157                     ATMEGA_USBCON_USBE |
 158                     ATMEGA_USBCON_OTGPADE |
 159                     ATMEGA_USBCON_VBUSTE);
 160
 161                 sc->sc_flags.clocks_off = 0;
 162
 163                 /* enable transceiver ? */
 164         }
 165 }
 166
 167 static void
 168 atmegadci_clocks_off(struct atmegadci_softc *sc)
 169 {
 170         if (!sc->sc_flags.clocks_off) {
 171
 172                 DPRINTFN(5, "\n");
 173
 174                 /* disable Transceiver ? */
 175
 176                 ATMEGA_WRITE_1(sc, ATMEGA_USBCON,
 177                     ATMEGA_USBCON_USBE |
 178                     ATMEGA_USBCON_OTGPADE |
 179                     ATMEGA_USBCON_FRZCLK |
 180                     ATMEGA_USBCON_VBUSTE);
 181
 182                 /* turn clocks off */
 183                 (sc->sc_clocks_off) (&sc->sc_bus);
 184
 185                 sc->sc_flags.clocks_off = 1;
 186         }
 187 }
 188
 189 static void
 190 atmegadci_pull_up(struct atmegadci_softc *sc)
 191 {
 192         /* pullup D+, if possible */
 193
 194         if (!sc->sc_flags.d_pulled_up &&
 195             sc->sc_flags.port_powered) {
 196                 sc->sc_flags.d_pulled_up = 1;
 197                 ATMEGA_WRITE_1(sc, ATMEGA_UDCON, 0);
 198         }
 199 }
 200
 201 static void
 202 atmegadci_pull_down(struct atmegadci_softc *sc)
 203 {
 204         /* pulldown D+, if possible */
 205
 206         if (sc->sc_flags.d_pulled_up) {
 207                 sc->sc_flags.d_pulled_up = 0;
 208                 ATMEGA_WRITE_1(sc, ATMEGA_UDCON, ATMEGA_UDCON_DETACH);
 209         }
 210 }
 211
 212 static void
 213 atmegadci_wakeup_peer(struct atmegadci_softc *sc)
 214 {
 215         uint8_t temp;
 216
 217         if (!sc->sc_flags.status_suspend) {
 218                 return;
 219         }
 220
 221         temp = ATMEGA_READ_1(sc, ATMEGA_UDCON);
 222         ATMEGA_WRITE_1(sc, ATMEGA_UDCON, temp | ATMEGA_UDCON_RMWKUP);
 223
 224         /* wait 8 milliseconds */
 225         /* Wait for reset to complete. */
 226         usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 125);
 227
 228         /* hardware should have cleared RMWKUP bit */
 229 }
 230
 231 static void
 232 atmegadci_set_address(struct atmegadci_softc *sc, uint8_t addr)
 233 {
 234         DPRINTFN(5, "addr=%d\n", addr);
 235
 236         addr |= ATMEGA_UDADDR_ADDEN;
 237
 238         ATMEGA_WRITE_1(sc, ATMEGA_UDADDR, addr);
 239 }
 240
 241 static uint8_t
 242 atmegadci_setup_rx(struct atmegadci_td *td)
 243 {
 244         struct atmegadci_softc *sc;
 245         struct usb_device_request req;
 246         uint16_t count;
 247         uint8_t temp;
 248
 249         /* get pointer to softc */
 250         sc = ATMEGA_PC2SC(td->pc);
 251
 252         /* select endpoint number */
 253         ATMEGA_WRITE_1(sc, ATMEGA_UENUM, td->ep_no);
 254
 255         /* check endpoint status */
 256         temp = ATMEGA_READ_1(sc, ATMEGA_UEINTX);
 257
 258         DPRINTFN(5, "UEINTX=0x%02x\n", temp);
 259
 260         if (!(temp & ATMEGA_UEINTX_RXSTPI)) {
 261                 goto not_complete;
 262         }
 263         /* clear did stall */
 264         td->did_stall = 0;
 265         /* get the packet byte count */
 266         count =
 267             (ATMEGA_READ_1(sc, ATMEGA_UEBCHX) << 8) |
 268             (ATMEGA_READ_1(sc, ATMEGA_UEBCLX));
 269
 270         /* mask away undefined bits */
 271         count &= 0x7FF;
 272
 273         /* verify data length */
 274         if (count != td->remainder) {
 275                 DPRINTFN(0, "Invalid SETUP packet "
 276                     "length, %d bytes\n", count);
 277                 goto not_complete;
 278         }
 279         if (count != sizeof(req)) {
 280                 DPRINTFN(0, "Unsupported SETUP packet "
 281                     "length, %d bytes\n", count);
 282                 goto not_complete;
 283         }
 284         /* receive data */
 285         ATMEGA_READ_MULTI_1(sc, ATMEGA_UEDATX,
 286             (void *)&req, sizeof(req));
 287
 288         /* copy data into real buffer */
 289         usbd_copy_in(td->pc, 0, &req, sizeof(req));
 290
 291         td->offset = sizeof(req);
 292         td->remainder = 0;
 293
 294         /* sneak peek the set address */
 295         if ((req.bmRequestType == UT_WRITE_DEVICE) &&
 296             (req.bRequest == UR_SET_ADDRESS)) {
 297                 sc->sc_dv_addr = req.wValue[0] & 0x7F;
 298                 /* must write address before ZLP */
 299                 ATMEGA_WRITE_1(sc, ATMEGA_UDADDR, sc->sc_dv_addr);
 300         } else {
 301                 sc->sc_dv_addr = 0xFF;
 302         }
 303
 304         /* Clear SETUP packet interrupt and all other previous interrupts */
 305         ATMEGA_WRITE_1(sc, ATMEGA_UEINTX, 0);
 306         return (0);                     /* complete */
 307
 308 not_complete:
 309         /* abort any ongoing transfer */
 310         if (!td->did_stall) {
 311                 DPRINTFN(5, "stalling\n");
 312                 ATMEGA_WRITE_1(sc, ATMEGA_UECONX,
 313                     ATMEGA_UECONX_EPEN |
 314                     ATMEGA_UECONX_STALLRQ);
 315                 td->did_stall = 1;
 316         }
 317         if (temp & ATMEGA_UEINTX_RXSTPI) {
 318                 /* clear SETUP packet interrupt */
 319                 ATMEGA_WRITE_1(sc, ATMEGA_UEINTX, ~ATMEGA_UEINTX_RXSTPI);
 320         }
 321         /* we only want to know if there is a SETUP packet */
 322         ATMEGA_WRITE_1(sc, ATMEGA_UEIENX, ATMEGA_UEIENX_RXSTPE);
 323         return (1);                     /* not complete */
 324 }
 325
 326 static uint8_t
 327 atmegadci_data_rx(struct atmegadci_td *td)
 328 {
 329         struct atmegadci_softc *sc;
 330         struct usb_page_search buf_res;
 331         uint16_t count;
 332         uint8_t temp;
 333         uint8_t to;
 334         uint8_t got_short;
 335
 336         to = 3;                         /* don't loop forever! */
 337         got_short = 0;
 338
 339         /* get pointer to softc */
 340         sc = ATMEGA_PC2SC(td->pc);
 341
 342         /* select endpoint number */
 343         ATMEGA_WRITE_1(sc, ATMEGA_UENUM, td->ep_no);
 344
 345 repeat:
 346         /* check if any of the FIFO banks have data */
 347         /* check endpoint status */
 348         temp = ATMEGA_READ_1(sc, ATMEGA_UEINTX);
 349
 350         DPRINTFN(5, "temp=0x%02x rem=%u\n", temp, td->remainder);
 351
 352         if (temp & ATMEGA_UEINTX_RXSTPI) {
 353                 if (td->remainder == 0) {
 354                         /*
 355                          * We are actually complete and have
 356                          * received the next SETUP
 357                          */
 358                         DPRINTFN(5, "faking complete\n");
 359                         return (0);     /* complete */
 360                 }
 361                 /*
 362                  * USB Host Aborted the transfer.
 363                  */
 364                 td->error = 1;
 365                 return (0);             /* complete */
 366         }
 367         /* check status */
 368         if (!(temp & (ATMEGA_UEINTX_FIFOCON |
 369             ATMEGA_UEINTX_RXOUTI))) {
 370                 /* no data */
 371                 goto not_complete;
 372         }
 373         /* get the packet byte count */
 374         count =
 375             (ATMEGA_READ_1(sc, ATMEGA_UEBCHX) << 8) |
 376             (ATMEGA_READ_1(sc, ATMEGA_UEBCLX));
 377
 378         /* mask away undefined bits */
 379         count &= 0x7FF;
 380
 381         /* verify the packet byte count */
 382         if (count != td->max_packet_size) {
 383                 if (count < td->max_packet_size) {
 384                         /* we have a short packet */
 385                         td->short_pkt = 1;
 386                         got_short = 1;
 387                 } else {
 388                         /* invalid USB packet */
 389                         td->error = 1;
 390                         return (0);     /* we are complete */
 391                 }
 392         }
 393         /* verify the packet byte count */
 394         if (count > td->remainder) {
 395                 /* invalid USB packet */
 396                 td->error = 1;
 397                 return (0);             /* we are complete */
 398         }
 399         while (count > 0) {
 400                 usbd_get_page(td->pc, td->offset, &buf_res);
 401
 402                 /* get correct length */
 403                 if (buf_res.length > count) {
 404                         buf_res.length = count;
 405                 }
 406                 /* receive data */
 407                 ATMEGA_READ_MULTI_1(sc, ATMEGA_UEDATX,
 408                     buf_res.buffer, buf_res.length);
 409
 410                 /* update counters */
 411                 count -= buf_res.length;
 412                 td->offset += buf_res.length;
 413                 td->remainder -= buf_res.length;
 414         }
 415
 416         /* clear OUT packet interrupt */
 417         ATMEGA_WRITE_1(sc, ATMEGA_UEINTX, ATMEGA_UEINTX_RXOUTI ^ 0xFF);
 418
 419         /* release FIFO bank */
 420         ATMEGA_WRITE_1(sc, ATMEGA_UEINTX, ATMEGA_UEINTX_FIFOCON ^ 0xFF);
 421
 422         /* check if we are complete */
 423         if ((td->remainder == 0) || got_short) {
 424                 if (td->short_pkt) {
 425                         /* we are complete */
 426                         return (0);
 427                 }
 428                 /* else need to receive a zero length packet */
 429         }
 430         if (--to) {
 431                 goto repeat;
 432         }
 433 not_complete:
 434         /* we only want to know if there is a SETUP packet or OUT packet */
 435         ATMEGA_WRITE_1(sc, ATMEGA_UEIENX,
 436             ATMEGA_UEIENX_RXSTPE | ATMEGA_UEIENX_RXOUTE);
 437         return (1);                     /* not complete */
 438 }
 439
 440 static uint8_t
 441 atmegadci_data_tx(struct atmegadci_td *td)
 442 {
 443         struct atmegadci_softc *sc;
 444         struct usb_page_search buf_res;
 445         uint16_t count;
 446         uint8_t to;
 447         uint8_t temp;
 448
 449         to = 3;                         /* don't loop forever! */
 450
 451         /* get pointer to softc */
 452         sc = ATMEGA_PC2SC(td->pc);
 453
 454         /* select endpoint number */
 455         ATMEGA_WRITE_1(sc, ATMEGA_UENUM, td->ep_no);
 456
 457 repeat:
 458
 459         /* check endpoint status */
 460         temp = ATMEGA_READ_1(sc, ATMEGA_UEINTX);
 461
 462         DPRINTFN(5, "temp=0x%02x rem=%u\n", temp, td->remainder);
 463
 464         if (temp & ATMEGA_UEINTX_RXSTPI) {
 465                 /*
 466                  * The current transfer was aborted
 467                  * by the USB Host
 468                  */
 469                 td->error = 1;
 470                 return (0);             /* complete */
 471         }
 472
 473         temp = ATMEGA_READ_1(sc, ATMEGA_UESTA0X);
 474         if (temp & 3) {
 475                 /* cannot write any data - a bank is busy */
 476                 goto not_complete;
 477         }
 478
 479         count = td->max_packet_size;
 480         if (td->remainder < count) {
 481                 /* we have a short packet */
 482                 td->short_pkt = 1;
 483                 count = td->remainder;
 484         }
 485         while (count > 0) {
 486
 487                 usbd_get_page(td->pc, td->offset, &buf_res);
 488
 489                 /* get correct length */
 490                 if (buf_res.length > count) {
 491                         buf_res.length = count;
 492                 }
 493                 /* transmit data */
 494                 ATMEGA_WRITE_MULTI_1(sc, ATMEGA_UEDATX,
 495                     buf_res.buffer, buf_res.length);
 496
 497                 /* update counters */
 498                 count -= buf_res.length;
 499                 td->offset += buf_res.length;
 500                 td->remainder -= buf_res.length;
 501         }
 502
 503         /* clear IN packet interrupt */
 504         ATMEGA_WRITE_1(sc, ATMEGA_UEINTX, 0xFF ^ ATMEGA_UEINTX_TXINI);
 505
 506         /* allocate FIFO bank */
 507         ATMEGA_WRITE_1(sc, ATMEGA_UEINTX, 0xFF ^ ATMEGA_UEINTX_FIFOCON);
 508
 509         /* check remainder */
 510         if (td->remainder == 0) {
 511                 if (td->short_pkt) {
 512                         return (0);     /* complete */
 513                 }
 514                 /* else we need to transmit a short packet */
 515         }
 516         if (--to) {
 517                 goto repeat;
 518         }
 519 not_complete:
 520         /* we only want to know if there is a SETUP packet or free IN packet */
 521         ATMEGA_WRITE_1(sc, ATMEGA_UEIENX,
 522             ATMEGA_UEIENX_RXSTPE | ATMEGA_UEIENX_TXINE);
 523         return (1);                     /* not complete */
 524 }
 525
 526 static uint8_t
 527 atmegadci_data_tx_sync(struct atmegadci_td *td)
 528 {
 529         struct atmegadci_softc *sc;
 530         uint8_t temp;
 531
 532         /* get pointer to softc */
 533         sc = ATMEGA_PC2SC(td->pc);
 534
 535         /* select endpoint number */
 536         ATMEGA_WRITE_1(sc, ATMEGA_UENUM, td->ep_no);
 537
 538         /* check endpoint status */
 539         temp = ATMEGA_READ_1(sc, ATMEGA_UEINTX);
 540
 541         DPRINTFN(5, "temp=0x%02x\n", temp);
 542
 543         if (temp & ATMEGA_UEINTX_RXSTPI) {
 544                 DPRINTFN(5, "faking complete\n");
 545                 /* Race condition */
 546                 return (0);             /* complete */
 547         }
 548         /*
 549          * The control endpoint has only got one bank, so if that bank
 550          * is free the packet has been transferred!
 551          */
 552         temp = ATMEGA_READ_1(sc, ATMEGA_UESTA0X);
 553         if (temp & 3) {
 554                 /* cannot write any data - a bank is busy */
 555                 goto not_complete;
 556         }
 557         if (sc->sc_dv_addr != 0xFF) {
 558                 /* set new address */
 559                 atmegadci_set_address(sc, sc->sc_dv_addr);
 560         }
 561         return (0);                     /* complete */
 562
 563 not_complete:
 564         /* we only want to know if there is a SETUP packet or free IN packet */
 565         ATMEGA_WRITE_1(sc, ATMEGA_UEIENX,
 566             ATMEGA_UEIENX_RXSTPE | ATMEGA_UEIENX_TXINE);
 567         return (1);                     /* not complete */
 568 }
 569
 570 static uint8_t
 571 atmegadci_xfer_do_fifo(struct usb_xfer *xfer)
 572 {
 573         struct atmegadci_td *td;
 574
 575         DPRINTFN(9, "\n");
 576
 577         td = xfer->td_transfer_cache;
 578         while (1) {
 579                 if ((td->func) (td)) {
 580                         /* operation in progress */
 581                         break;
 582                 }
 583                 if (((void *)td) == xfer->td_transfer_last) {
 584                         goto done;
 585                 }
 586                 if (td->error) {
 587                         goto done;
 588                 } else if (td->remainder > 0) {
 589                         /*
 590                          * We had a short transfer. If there is no alternate
 591                          * next, stop processing !
 592                          */
 593                         if (!td->alt_next) {
 594                                 goto done;
 595                         }
 596                 }
 597                 /*
 598                  * Fetch the next transfer descriptor and transfer
 599                  * some flags to the next transfer descriptor
 600                  */
 601                 td = td->obj_next;
 602                 xfer->td_transfer_cache = td;
 603         }
 604         return (1);                     /* not complete */
 605
 606 done:
 607         /* compute all actual lengths */
 608
 609         atmegadci_standard_done(xfer);
 610         return (0);                     /* complete */
 611 }
 612
 613 static void
 614 atmegadci_interrupt_poll(struct atmegadci_softc *sc)
 615 {
 616         struct usb_xfer *xfer;
 617
 618 repeat:
 619         TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) {
 620                 if (!atmegadci_xfer_do_fifo(xfer)) {
 621                         /* queue has been modified */
 622                         goto repeat;
 623                 }
 624         }
 625 }
 626
 627 static void
 628 atmegadci_vbus_interrupt(struct atmegadci_softc *sc, uint8_t is_on)
 629 {
 630         DPRINTFN(5, "vbus = %u\n", is_on);
 631
 632         if (is_on) {
 633                 if (!sc->sc_flags.status_vbus) {
 634                         sc->sc_flags.status_vbus = 1;
 635
 636                         /* complete root HUB interrupt endpoint */
 637
 638                         atmegadci_root_intr(sc);
 639                 }
 640         } else {
 641                 if (sc->sc_flags.status_vbus) {
 642                         sc->sc_flags.status_vbus = 0;
 643                         sc->sc_flags.status_bus_reset = 0;
 644                         sc->sc_flags.status_suspend = 0;
 645                         sc->sc_flags.change_suspend = 0;
 646                         sc->sc_flags.change_connect = 1;
 647
 648                         /* complete root HUB interrupt endpoint */
 649
 650                         atmegadci_root_intr(sc);
 651                 }
 652         }
 653 }
 654
 655 void
 656 atmegadci_interrupt(struct atmegadci_softc *sc)
 657 {
 658         uint8_t status;
 659
 660         USB_BUS_LOCK(&sc->sc_bus);
 661
 662         /* read interrupt status */
 663         status = ATMEGA_READ_1(sc, ATMEGA_UDINT);
 664
 665         /* clear all set interrupts */
 666         ATMEGA_WRITE_1(sc, ATMEGA_UDINT, (~status) & 0x7D);
 667
 668         DPRINTFN(14, "UDINT=0x%02x\n", status);
 669
 670         /* check for any bus state change interrupts */
 671         if (status & ATMEGA_UDINT_EORSTI) {
 672
 673                 DPRINTFN(5, "end of reset\n");
 674
 675                 /* set correct state */
 676                 sc->sc_flags.status_bus_reset = 1;
 677                 sc->sc_flags.status_suspend = 0;
 678                 sc->sc_flags.change_suspend = 0;
 679                 sc->sc_flags.change_connect = 1;
 680
 681                 /* disable resume interrupt */
 682                 ATMEGA_WRITE_1(sc, ATMEGA_UDIEN,
 683                     ATMEGA_UDINT_SUSPE |
 684                     ATMEGA_UDINT_EORSTE);
 685
 686                 /* complete root HUB interrupt endpoint */
 687                 atmegadci_root_intr(sc);
 688         }
 689         /*
 690          * If resume and suspend is set at the same time we interpret
 691          * that like RESUME. Resume is set when there is at least 3
 692          * milliseconds of inactivity on the USB BUS.
 693          */
 694         if (status & ATMEGA_UDINT_WAKEUPI) {
 695
 696                 DPRINTFN(5, "resume interrupt\n");
 697
 698                 if (sc->sc_flags.status_suspend) {
 699                         /* update status bits */
 700                         sc->sc_flags.status_suspend = 0;
 701                         sc->sc_flags.change_suspend = 1;
 702
 703                         /* disable resume interrupt */
 704                         ATMEGA_WRITE_1(sc, ATMEGA_UDIEN,
 705                             ATMEGA_UDINT_SUSPE |
 706                             ATMEGA_UDINT_EORSTE);
 707
 708                         /* complete root HUB interrupt endpoint */
 709                         atmegadci_root_intr(sc);
 710                 }
 711         } else if (status & ATMEGA_UDINT_SUSPI) {
 712
 713                 DPRINTFN(5, "suspend interrupt\n");
 714
 715                 if (!sc->sc_flags.status_suspend) {
 716                         /* update status bits */
 717                         sc->sc_flags.status_suspend = 1;
 718                         sc->sc_flags.change_suspend = 1;
 719
 720                         /* disable suspend interrupt */
 721                         ATMEGA_WRITE_1(sc, ATMEGA_UDIEN,
 722                             ATMEGA_UDINT_WAKEUPE |
 723                             ATMEGA_UDINT_EORSTE);
 724
 725                         /* complete root HUB interrupt endpoint */
 726                         atmegadci_root_intr(sc);
 727                 }
 728         }
 729         /* check VBUS */
 730         status = ATMEGA_READ_1(sc, ATMEGA_USBINT);
 731
 732         /* clear all set interrupts */
 733         ATMEGA_WRITE_1(sc, ATMEGA_USBINT, (~status) & 0x03);
 734
 735         if (status & ATMEGA_USBINT_VBUSTI) {
 736                 uint8_t temp;
 737
 738                 DPRINTFN(5, "USBINT=0x%02x\n", status);
 739
 740                 temp = ATMEGA_READ_1(sc, ATMEGA_USBSTA);
 741                 atmegadci_vbus_interrupt(sc, temp & ATMEGA_USBSTA_VBUS);
 742         }
 743         /* check for any endpoint interrupts */
 744         status = ATMEGA_READ_1(sc, ATMEGA_UEINT);
 745         /* the hardware will clear the UEINT bits automatically */
 746         if (status) {
 747
 748                 DPRINTFN(5, "real endpoint interrupt UEINT=0x%02x\n", status);
 749
 750                 atmegadci_interrupt_poll(sc);
 751         }
 752         USB_BUS_UNLOCK(&sc->sc_bus);
 753 }
 754
 755 static void
 756 atmegadci_setup_standard_chain_sub(struct atmegadci_std_temp *temp)
 757 {
 758         struct atmegadci_td *td;
 759
 760         /* get current Transfer Descriptor */
 761         td = temp->td_next;
 762         temp->td = td;
 763
 764         /* prepare for next TD */
 765         temp->td_next = td->obj_next;
 766
 767         /* fill out the Transfer Descriptor */
 768         td->func = temp->func;
 769         td->pc = temp->pc;
 770         td->offset = temp->offset;
 771         td->remainder = temp->len;
 772         td->error = 0;
 773         td->did_stall = temp->did_stall;
 774         td->short_pkt = temp->short_pkt;
 775         td->alt_next = temp->setup_alt_next;
 776 }
 777
 778 static void
 779 atmegadci_setup_standard_chain(struct usb_xfer *xfer)
 780 {
 781         struct atmegadci_std_temp temp;
 782         struct atmegadci_softc *sc;
 783         struct atmegadci_td *td;
 784         uint32_t x;
 785         uint8_t ep_no;
 786         uint8_t need_sync;
 787
 788         DPRINTFN(9, "addr=%d endpt=%d sumlen=%d speed=%d\n",
 789             xfer->address, UE_GET_ADDR(xfer->endpointno),
 790             xfer->sumlen, usbd_get_speed(xfer->xroot->udev));
 791
 792         temp.max_frame_size = xfer->max_frame_size;
 793
 794         td = xfer->td_start[0];
 795         xfer->td_transfer_first = td;
 796         xfer->td_transfer_cache = td;
 797
 798         /* setup temp */
 799
 800         temp.pc = NULL;
 801         temp.td = NULL;
 802         temp.td_next = xfer->td_start[0];
 803         temp.offset = 0;
 804         temp.setup_alt_next = xfer->flags_int.short_frames_ok;
 805         temp.did_stall = !xfer->flags_int.control_stall;
 806
 807         sc = ATMEGA_BUS2SC(xfer->xroot->bus);
 808         ep_no = (xfer->endpointno & UE_ADDR);
 809
 810         /* check if we should prepend a setup message */
 811
 812         if (xfer->flags_int.control_xfr) {
 813                 if (xfer->flags_int.control_hdr) {
 814
 815                         temp.func = &atmegadci_setup_rx;
 816                         temp.len = xfer->frlengths[0];
 817                         temp.pc = xfer->frbuffers + 0;
 818                         temp.short_pkt = temp.len ? 1 : 0;
 819                         /* check for last frame */
 820                         if (xfer->nframes == 1) {
 821                                 /* no STATUS stage yet, SETUP is last */
 822                                 if (xfer->flags_int.control_act)
 823                                         temp.setup_alt_next = 0;
 824                         }
 825
 826                         atmegadci_setup_standard_chain_sub(&temp);
 827                 }
 828                 x = 1;
 829         } else {
 830                 x = 0;
 831         }
 832
 833         if (x != xfer->nframes) {
 834                 if (xfer->endpointno & UE_DIR_IN) {
 835                         temp.func = &atmegadci_data_tx;
 836                         need_sync = 1;
 837                 } else {
 838                         temp.func = &atmegadci_data_rx;
 839                         need_sync = 0;
 840                 }
 841
 842                 /* setup "pc" pointer */
 843                 temp.pc = xfer->frbuffers + x;
 844         } else {
 845                 need_sync = 0;
 846         }
 847         while (x != xfer->nframes) {
 848
 849                 /* DATA0 / DATA1 message */
 850
 851                 temp.len = xfer->frlengths[x];
 852
 853                 x++;
 854
 855                 if (x == xfer->nframes) {
 856                         if (xfer->flags_int.control_xfr) {
 857                                 if (xfer->flags_int.control_act) {
 858                                         temp.setup_alt_next = 0;
 859                                 }
 860                         } else {
 861                                 temp.setup_alt_next = 0;
 862                         }
 863                 }
 864                 if (temp.len == 0) {
 865
 866                         /* make sure that we send an USB packet */
 867
 868                         temp.short_pkt = 0;
 869
 870                 } else {
 871
 872                         /* regular data transfer */
 873
 874                         temp.short_pkt = (xfer->flags.force_short_xfer) ? 0 : 1;
 875                 }
 876
 877                 atmegadci_setup_standard_chain_sub(&temp);
 878
 879                 if (xfer->flags_int.isochronous_xfr) {
 880                         temp.offset += temp.len;
 881                 } else {
 882                         /* get next Page Cache pointer */
 883                         temp.pc = xfer->frbuffers + x;
 884                 }
 885         }
 886
 887         if (xfer->flags_int.control_xfr) {
 888
 889                 /* always setup a valid "pc" pointer for status and sync */
 890                 temp.pc = xfer->frbuffers + 0;
 891                 temp.len = 0;
 892                 temp.short_pkt = 0;
 893                 temp.setup_alt_next = 0;
 894
 895                 /* check if we need to sync */
 896                 if (need_sync) {
 897                         /* we need a SYNC point after TX */
 898                         temp.func = &atmegadci_data_tx_sync;
 899                         atmegadci_setup_standard_chain_sub(&temp);
 900                 }
 901
 902                 /* check if we should append a status stage */
 903                 if (!xfer->flags_int.control_act) {
 904
 905                         /*
 906                          * Send a DATA1 message and invert the current
 907                          * endpoint direction.
 908                          */
 909                         if (xfer->endpointno & UE_DIR_IN) {
 910                                 temp.func = &atmegadci_data_rx;
 911                                 need_sync = 0;
 912                         } else {
 913                                 temp.func = &atmegadci_data_tx;
 914                                 need_sync = 1;
 915                         }
 916
 917                         atmegadci_setup_standard_chain_sub(&temp);
 918                         if (need_sync) {
 919                                 /* we need a SYNC point after TX */
 920                                 temp.func = &atmegadci_data_tx_sync;
 921                                 atmegadci_setup_standard_chain_sub(&temp);
 922                         }
 923                 }
 924         }
 925         /* must have at least one frame! */
 926         td = temp.td;
 927         xfer->td_transfer_last = td;
 928 }
 929
 930 static void
 931 atmegadci_timeout(void *arg)
 932 {
 933         struct usb_xfer *xfer = arg;
 934
 935         DPRINTF("xfer=%p\n", xfer);
 936
 937         USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED);
 938
 939         /* transfer is transferred */
 940         atmegadci_device_done(xfer, USB_ERR_TIMEOUT);
 941 }
 942
 943 static void
 944 atmegadci_start_standard_chain(struct usb_xfer *xfer)
 945 {
 946         DPRINTFN(9, "\n");
 947
 948         /* poll one time - will turn on interrupts */
 949         if (atmegadci_xfer_do_fifo(xfer)) {
 950
 951                 /* put transfer on interrupt queue */
 952                 usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer);
 953
 954                 /* start timeout, if any */
 955                 if (xfer->timeout != 0) {
 956                         usbd_transfer_timeout_ms(xfer,
 957                             &atmegadci_timeout, xfer->timeout);
 958                 }
 959         }
 960 }
 961
 962 static void
 963 atmegadci_root_intr(struct atmegadci_softc *sc)
 964 {
 965         DPRINTFN(9, "\n");
 966
 967         USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
 968
 969         /* set port bit */
 970         sc->sc_hub_idata[0] = 0x02;     /* we only have one port */
 971
 972         uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata,
 973             sizeof(sc->sc_hub_idata));
 974  }
 975
 976 static usb_error_t
 977 atmegadci_standard_done_sub(struct usb_xfer *xfer)
 978 {
 979         struct atmegadci_td *td;
 980         uint32_t len;
 981         uint8_t error;
 982
 983         DPRINTFN(9, "\n");
 984
 985         td = xfer->td_transfer_cache;
 986
 987         do {
 988                 len = td->remainder;
 989
 990                 if (xfer->aframes != xfer->nframes) {
 991                         /*
 992                          * Verify the length and subtract
 993                          * the remainder from "frlengths[]":
 994                          */
 995                         if (len > xfer->frlengths[xfer->aframes]) {
 996                                 td->error = 1;
 997                         } else {
 998                                 xfer->frlengths[xfer->aframes] -= len;
 999                         }
1000                 }
1001                 /* Check for transfer error */
1002                 if (td->error) {
1003                         /* the transfer is finished */
1004                         error = 1;
1005                         td = NULL;
1006                         break;
1007                 }
1008                 /* Check for short transfer */
1009                 if (len > 0) {
1010                         if (xfer->flags_int.short_frames_ok) {
1011                                 /* follow alt next */
1012                                 if (td->alt_next) {
1013                                         td = td->obj_next;
1014                                 } else {
1015                                         td = NULL;
1016                                 }
1017                         } else {
1018                                 /* the transfer is finished */
1019                                 td = NULL;
1020                         }
1021                         error = 0;
1022                         break;
1023                 }
1024                 td = td->obj_next;
1025
1026                 /* this USB frame is complete */
1027                 error = 0;
1028                 break;
1029
1030         } while (0);
1031
1032         /* update transfer cache */
1033
1034         xfer->td_transfer_cache = td;
1035
1036         return (error ?
1037             USB_ERR_STALLED : USB_ERR_NORMAL_COMPLETION);
1038 }
1039
1040 static void
1041 atmegadci_standard_done(struct usb_xfer *xfer)
1042 {
1043         usb_error_t err = 0;
1044
1045         DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n",
1046             xfer, xfer->endpoint);
1047
1048         /* reset scanner */
1049
1050         xfer->td_transfer_cache = xfer->td_transfer_first;
1051
1052         if (xfer->flags_int.control_xfr) {
1053
1054                 if (xfer->flags_int.control_hdr) {
1055
1056                         err = atmegadci_standard_done_sub(xfer);
1057                 }
1058                 xfer->aframes = 1;
1059
1060                 if (xfer->td_transfer_cache == NULL) {
1061                         goto done;
1062                 }
1063         }
1064         while (xfer->aframes != xfer->nframes) {
1065
1066                 err = atmegadci_standard_done_sub(xfer);
1067                 xfer->aframes++;
1068
1069                 if (xfer->td_transfer_cache == NULL) {
1070                         goto done;
1071                 }
1072         }
1073
1074         if (xfer->flags_int.control_xfr &&
1075             !xfer->flags_int.control_act) {
1076
1077                 err = atmegadci_standard_done_sub(xfer);
1078         }
1079 done:
1080         atmegadci_device_done(xfer, err);
1081 }
1082
1083 /*------------------------------------------------------------------------*
1084  *      atmegadci_device_done
1085  *
1086  * NOTE: this function can be called more than one time on the
1087  * same USB transfer!
1088  *------------------------------------------------------------------------*/
1089 static void
1090 atmegadci_device_done(struct usb_xfer *xfer, usb_error_t error)
1091 {
1092         struct atmegadci_softc *sc = ATMEGA_BUS2SC(xfer->xroot->bus);
1093         uint8_t ep_no;
1094
1095         USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
1096
1097         DPRINTFN(9, "xfer=%p, endpoint=%p, error=%d\n",
1098             xfer, xfer->endpoint, error);
1099
1100         if (xfer->flags_int.usb_mode == USB_MODE_DEVICE) {
1101                 ep_no = (xfer->endpointno & UE_ADDR);
1102
1103                 /* select endpoint number */
1104                 ATMEGA_WRITE_1(sc, ATMEGA_UENUM, ep_no);
1105
1106                 /* disable endpoint interrupt */
1107                 ATMEGA_WRITE_1(sc, ATMEGA_UEIENX, 0);
1108
1109                 DPRINTFN(15, "disabled interrupts!\n");
1110         }
1111         /* dequeue transfer and start next transfer */
1112         usbd_transfer_done(xfer, error);
1113 }
1114
1115 static void
1116 atmegadci_set_stall(struct usb_device *udev, struct usb_xfer *xfer,
1117     struct usb_endpoint *ep, uint8_t *did_stall)
1118 {
1119         struct atmegadci_softc *sc;
1120         uint8_t ep_no;
1121
1122         USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED);
1123
1124         DPRINTFN(5, "endpoint=%p\n", ep);
1125
1126         if (xfer) {
1127                 /* cancel any ongoing transfers */
1128                 atmegadci_device_done(xfer, USB_ERR_STALLED);
1129         }
1130         sc = ATMEGA_BUS2SC(udev->bus);
1131         /* get endpoint number */
1132         ep_no = (ep->edesc->bEndpointAddress & UE_ADDR);
1133         /* select endpoint number */
1134         ATMEGA_WRITE_1(sc, ATMEGA_UENUM, ep_no);
1135         /* set stall */
1136         ATMEGA_WRITE_1(sc, ATMEGA_UECONX,
1137             ATMEGA_UECONX_EPEN |
1138             ATMEGA_UECONX_STALLRQ);
1139 }
1140
1141 static void
1142 atmegadci_clear_stall_sub(struct atmegadci_softc *sc, uint8_t ep_no,
1143     uint8_t ep_type, uint8_t ep_dir)
1144 {
1145         uint8_t temp;
1146
1147         if (ep_type == UE_CONTROL) {
1148                 /* clearing stall is not needed */
1149                 return;
1150         }
1151         /* select endpoint number */
1152         ATMEGA_WRITE_1(sc, ATMEGA_UENUM, ep_no);
1153
1154         /* set endpoint reset */
1155         ATMEGA_WRITE_1(sc, ATMEGA_UERST, ATMEGA_UERST_MASK(ep_no));
1156
1157         /* clear endpoint reset */
1158         ATMEGA_WRITE_1(sc, ATMEGA_UERST, 0);
1159
1160         /* set stall */
1161         ATMEGA_WRITE_1(sc, ATMEGA_UECONX,
1162             ATMEGA_UECONX_EPEN |
1163             ATMEGA_UECONX_STALLRQ);
1164
1165         /* reset data toggle */
1166         ATMEGA_WRITE_1(sc, ATMEGA_UECONX,
1167             ATMEGA_UECONX_EPEN |
1168             ATMEGA_UECONX_RSTDT);
1169
1170         /* clear stall */
1171         ATMEGA_WRITE_1(sc, ATMEGA_UECONX,
1172             ATMEGA_UECONX_EPEN |
1173             ATMEGA_UECONX_STALLRQC);
1174
1175         do {
1176                 if (ep_type == UE_BULK) {
1177                         temp = ATMEGA_UECFG0X_EPTYPE2;
1178                 } else if (ep_type == UE_INTERRUPT) {
1179                         temp = ATMEGA_UECFG0X_EPTYPE3;
1180                 } else {
1181                         temp = ATMEGA_UECFG0X_EPTYPE1;
1182                 }
1183                 if (ep_dir & UE_DIR_IN) {
1184                         temp |= ATMEGA_UECFG0X_EPDIR;
1185                 }
1186                 /* two banks, 64-bytes wMaxPacket */
1187                 ATMEGA_WRITE_1(sc, ATMEGA_UECFG0X, temp);
1188                 ATMEGA_WRITE_1(sc, ATMEGA_UECFG1X,
1189                     ATMEGA_UECFG1X_ALLOC |
1190                     ATMEGA_UECFG1X_EPBK0 |      /* one bank */
1191                     ATMEGA_UECFG1X_EPSIZE(3));
1192
1193                 temp = ATMEGA_READ_1(sc, ATMEGA_UESTA0X);
1194                 if (!(temp & ATMEGA_UESTA0X_CFGOK)) {
1195                         device_printf(sc->sc_bus.bdev,
1196                             "Chip rejected configuration\n");
1197                 }
1198         } while (0);
1199 }
1200
1201 static void
1202 atmegadci_clear_stall(struct usb_device *udev, struct usb_endpoint *ep)
1203 {
1204         struct atmegadci_softc *sc;
1205         struct usb_endpoint_descriptor *ed;
1206
1207         DPRINTFN(5, "endpoint=%p\n", ep);
1208
1209         USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED);
1210
1211         /* check mode */
1212         if (udev->flags.usb_mode != USB_MODE_DEVICE) {
1213                 /* not supported */
1214                 return;
1215         }
1216         /* get softc */
1217         sc = ATMEGA_BUS2SC(udev->bus);
1218
1219         /* get endpoint descriptor */
1220         ed = ep->edesc;
1221
1222         /* reset endpoint */
1223         atmegadci_clear_stall_sub(sc,
1224             (ed->bEndpointAddress & UE_ADDR),
1225             (ed->bmAttributes & UE_XFERTYPE),
1226             (ed->bEndpointAddress & (UE_DIR_IN | UE_DIR_OUT)));
1227 }
1228
1229 usb_error_t
1230 atmegadci_init(struct atmegadci_softc *sc)
1231 {
1232         uint8_t n;
1233
1234         DPRINTF("start\n");
1235
1236         /* set up the bus structure */
1237         sc->sc_bus.usbrev = USB_REV_1_1;
1238         sc->sc_bus.methods = &atmegadci_bus_methods;
1239
1240         USB_BUS_LOCK(&sc->sc_bus);
1241
1242         /* make sure USB is enabled */
1243         ATMEGA_WRITE_1(sc, ATMEGA_USBCON,
1244             ATMEGA_USBCON_USBE |
1245             ATMEGA_USBCON_FRZCLK);
1246
1247         /* enable USB PAD regulator */
1248         ATMEGA_WRITE_1(sc, ATMEGA_UHWCON,
1249             ATMEGA_UHWCON_UVREGE |
1250             ATMEGA_UHWCON_UIMOD);
1251
1252         /* the following register sets up the USB PLL, assuming 16MHz X-tal */
1253         ATMEGA_WRITE_1(sc, 0x49 /* PLLCSR */, 0x14 | 0x02);
1254
1255         /* wait for PLL to lock */
1256         for (n = 0; n != 20; n++) {
1257                 if (ATMEGA_READ_1(sc, 0x49) & 0x01)
1258                         break;
1259                 /* wait a little bit for PLL to start */
1260                 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 100);
1261         }
1262
1263         /* make sure USB is enabled */
1264         ATMEGA_WRITE_1(sc, ATMEGA_USBCON,
1265             ATMEGA_USBCON_USBE |
1266             ATMEGA_USBCON_OTGPADE |
1267             ATMEGA_USBCON_VBUSTE);
1268
1269         /* turn on clocks */
1270         (sc->sc_clocks_on) (&sc->sc_bus);
1271
1272         /* make sure device is re-enumerated */
1273         ATMEGA_WRITE_1(sc, ATMEGA_UDCON, ATMEGA_UDCON_DETACH);
1274
1275         /* wait a little for things to stabilise */
1276         usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 20);
1277
1278         /* enable interrupts */
1279         ATMEGA_WRITE_1(sc, ATMEGA_UDIEN,
1280             ATMEGA_UDINT_SUSPE |
1281             ATMEGA_UDINT_EORSTE);
1282
1283         /* reset all endpoints */
1284         ATMEGA_WRITE_1(sc, ATMEGA_UERST,
1285             (1 << ATMEGA_EP_MAX) - 1);
1286
1287         /* disable reset */
1288         ATMEGA_WRITE_1(sc, ATMEGA_UERST, 0);
1289
1290         /* disable all endpoints */
1291         for (n = 0; n != ATMEGA_EP_MAX; n++) {
1292
1293                 /* select endpoint */
1294                 ATMEGA_WRITE_1(sc, ATMEGA_UENUM, n);
1295
1296                 /* disable endpoint interrupt */
1297                 ATMEGA_WRITE_1(sc, ATMEGA_UEIENX, 0);
1298
1299                 /* disable endpoint */
1300                 ATMEGA_WRITE_1(sc, ATMEGA_UECONX, 0);
1301         }
1302
1303         /* turn off clocks */
1304
1305         atmegadci_clocks_off(sc);
1306
1307         /* read initial VBUS state */
1308
1309         n = ATMEGA_READ_1(sc, ATMEGA_USBSTA);
1310         atmegadci_vbus_interrupt(sc, n & ATMEGA_USBSTA_VBUS);
1311
1312         USB_BUS_UNLOCK(&sc->sc_bus);
1313
1314         /* catch any lost interrupts */
1315
1316         atmegadci_do_poll(&sc->sc_bus);
1317
1318         return (0);                     /* success */
1319 }
1320
1321 void
1322 atmegadci_uninit(struct atmegadci_softc *sc)
1323 {
1324         USB_BUS_LOCK(&sc->sc_bus);
1325
1326         /* turn on clocks */
1327         (sc->sc_clocks_on) (&sc->sc_bus);
1328
1329         /* disable interrupts */
1330         ATMEGA_WRITE_1(sc, ATMEGA_UDIEN, 0);
1331
1332         /* reset all endpoints */
1333         ATMEGA_WRITE_1(sc, ATMEGA_UERST,
1334             (1 << ATMEGA_EP_MAX) - 1);
1335
1336         /* disable reset */
1337         ATMEGA_WRITE_1(sc, ATMEGA_UERST, 0);
1338
1339         sc->sc_flags.port_powered = 0;
1340         sc->sc_flags.status_vbus = 0;
1341         sc->sc_flags.status_bus_reset = 0;
1342         sc->sc_flags.status_suspend = 0;
1343         sc->sc_flags.change_suspend = 0;
1344         sc->sc_flags.change_connect = 1;
1345
1346         atmegadci_pull_down(sc);
1347         atmegadci_clocks_off(sc);
1348
1349         /* disable USB PAD regulator */
1350         ATMEGA_WRITE_1(sc, ATMEGA_UHWCON, 0);
1351
1352         USB_BUS_UNLOCK(&sc->sc_bus);
1353 }
1354
1355 void
1356 atmegadci_suspend(struct atmegadci_softc *sc)
1357 {
1358         return;
1359 }
1360
1361 void
1362 atmegadci_resume(struct atmegadci_softc *sc)
1363 {
1364         return;
1365 }
1366
1367 static void
1368 atmegadci_do_poll(struct usb_bus *bus)
1369 {
1370         struct atmegadci_softc *sc = ATMEGA_BUS2SC(bus);
1371
1372         USB_BUS_LOCK(&sc->sc_bus);
1373         atmegadci_interrupt_poll(sc);
1374         USB_BUS_UNLOCK(&sc->sc_bus);
1375 }
1376
1377 /*------------------------------------------------------------------------*
1378  * at91dci bulk support
1379  * at91dci control support
1380  * at91dci interrupt support
1381  *------------------------------------------------------------------------*/
1382 static void
1383 atmegadci_device_non_isoc_open(struct usb_xfer *xfer)
1384 {
1385         return;
1386 }
1387
1388 static void
1389 atmegadci_device_non_isoc_close(struct usb_xfer *xfer)
1390 {
1391         atmegadci_device_done(xfer, USB_ERR_CANCELLED);
1392 }
1393
1394 static void
1395 atmegadci_device_non_isoc_enter(struct usb_xfer *xfer)
1396 {
1397         return;
1398 }
1399
1400 static void
1401 atmegadci_device_non_isoc_start(struct usb_xfer *xfer)
1402 {
1403         /* setup TDs */
1404         atmegadci_setup_standard_chain(xfer);
1405         atmegadci_start_standard_chain(xfer);
1406 }
1407
1408 struct usb_pipe_methods atmegadci_device_non_isoc_methods =
1409 {
1410         .open = atmegadci_device_non_isoc_open,
1411         .close = atmegadci_device_non_isoc_close,
1412         .enter = atmegadci_device_non_isoc_enter,
1413         .start = atmegadci_device_non_isoc_start,
1414 };
1415
1416 /*------------------------------------------------------------------------*
1417  * at91dci full speed isochronous support
1418  *------------------------------------------------------------------------*/
1419 static void
1420 atmegadci_device_isoc_fs_open(struct usb_xfer *xfer)
1421 {
1422         return;
1423 }
1424
1425 static void
1426 atmegadci_device_isoc_fs_close(struct usb_xfer *xfer)
1427 {
1428         atmegadci_device_done(xfer, USB_ERR_CANCELLED);
1429 }
1430
1431 static void
1432 atmegadci_device_isoc_fs_enter(struct usb_xfer *xfer)
1433 {
1434         struct atmegadci_softc *sc = ATMEGA_BUS2SC(xfer->xroot->bus);
1435         uint32_t temp;
1436         uint32_t nframes;
1437
1438         DPRINTFN(6, "xfer=%p next=%d nframes=%d\n",
1439             xfer, xfer->endpoint->isoc_next, xfer->nframes);
1440
1441         /* get the current frame index */
1442
1443         nframes =
1444             (ATMEGA_READ_1(sc, ATMEGA_UDFNUMH) << 8) |
1445             (ATMEGA_READ_1(sc, ATMEGA_UDFNUML));
1446
1447         nframes &= ATMEGA_FRAME_MASK;
1448
1449         /*
1450          * check if the frame index is within the window where the frames
1451          * will be inserted
1452          */
1453         temp = (nframes - xfer->endpoint->isoc_next) & ATMEGA_FRAME_MASK;
1454
1455         if ((xfer->endpoint->is_synced == 0) ||
1456             (temp < xfer->nframes)) {
1457                 /*
1458                  * If there is data underflow or the pipe queue is
1459                  * empty we schedule the transfer a few frames ahead
1460                  * of the current frame position. Else two isochronous
1461                  * transfers might overlap.
1462                  */
1463                 xfer->endpoint->isoc_next = (nframes + 3) & ATMEGA_FRAME_MASK;
1464                 xfer->endpoint->is_synced = 1;
1465                 DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next);
1466         }
1467         /*
1468          * compute how many milliseconds the insertion is ahead of the
1469          * current frame position:
1470          */
1471         temp = (xfer->endpoint->isoc_next - nframes) & ATMEGA_FRAME_MASK;
1472
1473         /*
1474          * pre-compute when the isochronous transfer will be finished:
1475          */
1476         xfer->isoc_time_complete =
1477             usb_isoc_time_expand(&sc->sc_bus, nframes) + temp +
1478             xfer->nframes;
1479
1480         /* compute frame number for next insertion */
1481         xfer->endpoint->isoc_next += xfer->nframes;
1482
1483         /* setup TDs */
1484         atmegadci_setup_standard_chain(xfer);
1485 }
1486
1487 static void
1488 atmegadci_device_isoc_fs_start(struct usb_xfer *xfer)
1489 {
1490         /* start TD chain */
1491         atmegadci_start_standard_chain(xfer);
1492 }
1493
1494 struct usb_pipe_methods atmegadci_device_isoc_fs_methods =
1495 {
1496         .open = atmegadci_device_isoc_fs_open,
1497         .close = atmegadci_device_isoc_fs_close,
1498         .enter = atmegadci_device_isoc_fs_enter,
1499         .start = atmegadci_device_isoc_fs_start,
1500 };
1501
1502 /*------------------------------------------------------------------------*
1503  * at91dci root control support
1504  *------------------------------------------------------------------------*
1505  * Simulate a hardware HUB by handling all the necessary requests.
1506  *------------------------------------------------------------------------*/
1507
1508 static const struct usb_device_descriptor atmegadci_devd = {
1509         .bLength = sizeof(struct usb_device_descriptor),
1510         .bDescriptorType = UDESC_DEVICE,
1511         .bcdUSB = {0x00, 0x02},
1512         .bDeviceClass = UDCLASS_HUB,
1513         .bDeviceSubClass = UDSUBCLASS_HUB,
1514         .bDeviceProtocol = UDPROTO_HSHUBSTT,
1515         .bMaxPacketSize = 64,
1516         .bcdDevice = {0x00, 0x01},
1517         .iManufacturer = 1,
1518         .iProduct = 2,
1519         .bNumConfigurations = 1,
1520 };
1521
1522 static const struct usb_device_qualifier atmegadci_odevd = {
1523         .bLength = sizeof(struct usb_device_qualifier),
1524         .bDescriptorType = UDESC_DEVICE_QUALIFIER,
1525         .bcdUSB = {0x00, 0x02},
1526         .bDeviceClass = UDCLASS_HUB,
1527         .bDeviceSubClass = UDSUBCLASS_HUB,
1528         .bDeviceProtocol = UDPROTO_FSHUB,
1529         .bMaxPacketSize0 = 0,
1530         .bNumConfigurations = 0,
1531 };
1532
1533 static const struct atmegadci_config_desc atmegadci_confd = {
1534         .confd = {
1535                 .bLength = sizeof(struct usb_config_descriptor),
1536                 .bDescriptorType = UDESC_CONFIG,
1537                 .wTotalLength[0] = sizeof(atmegadci_confd),
1538                 .bNumInterface = 1,
1539                 .bConfigurationValue = 1,
1540                 .iConfiguration = 0,
1541                 .bmAttributes = UC_SELF_POWERED,
1542                 .bMaxPower = 0,
1543         },
1544         .ifcd = {
1545                 .bLength = sizeof(struct usb_interface_descriptor),
1546                 .bDescriptorType = UDESC_INTERFACE,
1547                 .bNumEndpoints = 1,
1548                 .bInterfaceClass = UICLASS_HUB,
1549                 .bInterfaceSubClass = UISUBCLASS_HUB,
1550                 .bInterfaceProtocol = UIPROTO_HSHUBSTT,
1551         },
1552         .endpd = {
1553                 .bLength = sizeof(struct usb_endpoint_descriptor),
1554                 .bDescriptorType = UDESC_ENDPOINT,
1555                 .bEndpointAddress = (UE_DIR_IN | ATMEGA_INTR_ENDPT),
1556                 .bmAttributes = UE_INTERRUPT,
1557                 .wMaxPacketSize[0] = 8,
1558                 .bInterval = 255,
1559         },
1560 };
1561
1562 static const struct usb_hub_descriptor_min atmegadci_hubd = {
1563         .bDescLength = sizeof(atmegadci_hubd),
1564         .bDescriptorType = UDESC_HUB,
1565         .bNbrPorts = 1,
1566         .wHubCharacteristics[0] =
1567         (UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL) & 0xFF,
1568         .wHubCharacteristics[1] =
1569         (UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL) >> 8,
1570         .bPwrOn2PwrGood = 50,
1571         .bHubContrCurrent = 0,
1572         .DeviceRemovable = {0},         /* port is removable */
1573 };
1574
1575 #define STRING_LANG \
1576   0x09, 0x04,                           /* American English */
1577
1578 #define STRING_VENDOR \
1579   'A', 0, 'T', 0, 'M', 0, 'E', 0, 'G', 0, 'A', 0
1580
1581 #define STRING_PRODUCT \
1582   'D', 0, 'C', 0, 'I', 0, ' ', 0, 'R', 0, \
1583   'o', 0, 'o', 0, 't', 0, ' ', 0, 'H', 0, \
1584   'U', 0, 'B', 0,
1585
1586 USB_MAKE_STRING_DESC(STRING_LANG, atmegadci_langtab);
1587 USB_MAKE_STRING_DESC(STRING_VENDOR, atmegadci_vendor);
1588 USB_MAKE_STRING_DESC(STRING_PRODUCT, atmegadci_product);
1589
1590 static usb_error_t
1591 atmegadci_roothub_exec(struct usb_device *udev,
1592     struct usb_device_request *req, const void **pptr, uint16_t *plength)
1593 {
1594         struct atmegadci_softc *sc = ATMEGA_BUS2SC(udev->bus);
1595         const void *ptr;
1596         uint16_t len;
1597         uint16_t value;
1598         uint16_t index;
1599         uint8_t temp;
1600         usb_error_t err;
1601
1602         USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
1603
1604         /* buffer reset */
1605         ptr = (const void *)&sc->sc_hub_temp;
1606         len = 0;
1607         err = 0;
1608
1609         value = UGETW(req->wValue);
1610         index = UGETW(req->wIndex);
1611
1612         /* demultiplex the control request */
1613
1614         switch (req->bmRequestType) {
1615         case UT_READ_DEVICE:
1616                 switch (req->bRequest) {
1617                 case UR_GET_DESCRIPTOR:
1618                         goto tr_handle_get_descriptor;
1619                 case UR_GET_CONFIG:
1620                         goto tr_handle_get_config;
1621                 case UR_GET_STATUS:
1622                         goto tr_handle_get_status;
1623                 default:
1624                         goto tr_stalled;
1625                 }
1626                 break;
1627
1628         case UT_WRITE_DEVICE:
1629                 switch (req->bRequest) {
1630                 case UR_SET_ADDRESS:
1631                         goto tr_handle_set_address;
1632                 case UR_SET_CONFIG:
1633                         goto tr_handle_set_config;
1634                 case UR_CLEAR_FEATURE:
1635                         goto tr_valid;  /* nop */
1636                 case UR_SET_DESCRIPTOR:
1637                         goto tr_valid;  /* nop */
1638                 case UR_SET_FEATURE:
1639                 default:
1640                         goto tr_stalled;
1641                 }
1642                 break;
1643
1644         case UT_WRITE_ENDPOINT:
1645                 switch (req->bRequest) {
1646                 case UR_CLEAR_FEATURE:
1647                         switch (UGETW(req->wValue)) {
1648                         case UF_ENDPOINT_HALT:
1649                                 goto tr_handle_clear_halt;
1650                         case UF_DEVICE_REMOTE_WAKEUP:
1651                                 goto tr_handle_clear_wakeup;
1652                         default:
1653                                 goto tr_stalled;
1654                         }
1655                         break;
1656                 case UR_SET_FEATURE:
1657                         switch (UGETW(req->wValue)) {
1658                         case UF_ENDPOINT_HALT:
1659                                 goto tr_handle_set_halt;
1660                         case UF_DEVICE_REMOTE_WAKEUP:
1661                                 goto tr_handle_set_wakeup;
1662                         default:
1663                                 goto tr_stalled;
1664                         }
1665                         break;
1666                 case UR_SYNCH_FRAME:
1667                         goto tr_valid;  /* nop */
1668                 default:
1669                         goto tr_stalled;
1670                 }
1671                 break;
1672
1673         case UT_READ_ENDPOINT:
1674                 switch (req->bRequest) {
1675                 case UR_GET_STATUS:
1676                         goto tr_handle_get_ep_status;
1677                 default:
1678                         goto tr_stalled;
1679                 }
1680                 break;
1681
1682         case UT_WRITE_INTERFACE:
1683                 switch (req->bRequest) {
1684                 case UR_SET_INTERFACE:
1685                         goto tr_handle_set_interface;
1686                 case UR_CLEAR_FEATURE:
1687                         goto tr_valid;  /* nop */
1688                 case UR_SET_FEATURE:
1689                 default:
1690                         goto tr_stalled;
1691                 }
1692                 break;
1693
1694         case UT_READ_INTERFACE:
1695                 switch (req->bRequest) {
1696                 case UR_GET_INTERFACE:
1697                         goto tr_handle_get_interface;
1698                 case UR_GET_STATUS:
1699                         goto tr_handle_get_iface_status;
1700                 default:
1701                         goto tr_stalled;
1702                 }
1703                 break;
1704
1705         case UT_WRITE_CLASS_INTERFACE:
1706         case UT_WRITE_VENDOR_INTERFACE:
1707                 /* XXX forward */
1708                 break;
1709
1710         case UT_READ_CLASS_INTERFACE:
1711         case UT_READ_VENDOR_INTERFACE:
1712                 /* XXX forward */
1713                 break;
1714
1715         case UT_WRITE_CLASS_DEVICE:
1716                 switch (req->bRequest) {
1717                 case UR_CLEAR_FEATURE:
1718                         goto tr_valid;
1719                 case UR_SET_DESCRIPTOR:
1720                 case UR_SET_FEATURE:
1721                         break;
1722                 default:
1723                         goto tr_stalled;
1724                 }
1725                 break;
1726
1727         case UT_WRITE_CLASS_OTHER:
1728                 switch (req->bRequest) {
1729                 case UR_CLEAR_FEATURE:
1730                         goto tr_handle_clear_port_feature;
1731                 case UR_SET_FEATURE:
1732                         goto tr_handle_set_port_feature;
1733                 case UR_CLEAR_TT_BUFFER:
1734                 case UR_RESET_TT:
1735                 case UR_STOP_TT:
1736                         goto tr_valid;
1737
1738                 default:
1739                         goto tr_stalled;
1740                 }
1741                 break;
1742
1743         case UT_READ_CLASS_OTHER:
1744                 switch (req->bRequest) {
1745                 case UR_GET_TT_STATE:
1746                         goto tr_handle_get_tt_state;
1747                 case UR_GET_STATUS:
1748                         goto tr_handle_get_port_status;
1749                 default:
1750                         goto tr_stalled;
1751                 }
1752                 break;
1753
1754         case UT_READ_CLASS_DEVICE:
1755                 switch (req->bRequest) {
1756                 case UR_GET_DESCRIPTOR:
1757                         goto tr_handle_get_class_descriptor;
1758                 case UR_GET_STATUS:
1759                         goto tr_handle_get_class_status;
1760
1761                 default:
1762                         goto tr_stalled;
1763                 }
1764                 break;
1765         default:
1766                 goto tr_stalled;
1767         }
1768         goto tr_valid;
1769
1770 tr_handle_get_descriptor:
1771         switch (value >> 8) {
1772         case UDESC_DEVICE:
1773                 if (value & 0xff) {
1774                         goto tr_stalled;
1775                 }
1776                 len = sizeof(atmegadci_devd);
1777                 ptr = (const void *)&atmegadci_devd;
1778                 goto tr_valid;
1779         case UDESC_CONFIG:
1780                 if (value & 0xff) {
1781                         goto tr_stalled;
1782                 }
1783                 len = sizeof(atmegadci_confd);
1784                 ptr = (const void *)&atmegadci_confd;
1785                 goto tr_valid;
1786         case UDESC_STRING:
1787                 switch (value & 0xff) {
1788                 case 0:         /* Language table */
1789                         len = sizeof(atmegadci_langtab);
1790                         ptr = (const void *)&atmegadci_langtab;
1791                         goto tr_valid;
1792
1793                 case 1:         /* Vendor */
1794                         len = sizeof(atmegadci_vendor);
1795                         ptr = (const void *)&atmegadci_vendor;
1796                         goto tr_valid;
1797
1798                 case 2:         /* Product */
1799                         len = sizeof(atmegadci_product);
1800                         ptr = (const void *)&atmegadci_product;
1801                         goto tr_valid;
1802                 default:
1803                         break;
1804                 }
1805                 break;
1806         default:
1807                 goto tr_stalled;
1808         }
1809         goto tr_stalled;
1810
1811 tr_handle_get_config:
1812         len = 1;
1813         sc->sc_hub_temp.wValue[0] = sc->sc_conf;
1814         goto tr_valid;
1815
1816 tr_handle_get_status:
1817         len = 2;
1818         USETW(sc->sc_hub_temp.wValue, UDS_SELF_POWERED);
1819         goto tr_valid;
1820
1821 tr_handle_set_address:
1822         if (value & 0xFF00) {
1823                 goto tr_stalled;
1824         }
1825         sc->sc_rt_addr = value;
1826         goto tr_valid;
1827
1828 tr_handle_set_config:
1829         if (value >= 2) {
1830                 goto tr_stalled;
1831         }
1832         sc->sc_conf = value;
1833         goto tr_valid;
1834
1835 tr_handle_get_interface:
1836         len = 1;
1837         sc->sc_hub_temp.wValue[0] = 0;
1838         goto tr_valid;
1839
1840 tr_handle_get_tt_state:
1841 tr_handle_get_class_status:
1842 tr_handle_get_iface_status:
1843 tr_handle_get_ep_status:
1844         len = 2;
1845         USETW(sc->sc_hub_temp.wValue, 0);
1846         goto tr_valid;
1847
1848 tr_handle_set_halt:
1849 tr_handle_set_interface:
1850 tr_handle_set_wakeup:
1851 tr_handle_clear_wakeup:
1852 tr_handle_clear_halt:
1853         goto tr_valid;
1854
1855 tr_handle_clear_port_feature:
1856         if (index != 1) {
1857                 goto tr_stalled;
1858         }
1859         DPRINTFN(9, "UR_CLEAR_PORT_FEATURE on port %d\n", index);
1860
1861         switch (value) {
1862         case UHF_PORT_SUSPEND:
1863                 atmegadci_wakeup_peer(sc);
1864                 break;
1865
1866         case UHF_PORT_ENABLE:
1867                 sc->sc_flags.port_enabled = 0;
1868                 break;
1869
1870         case UHF_PORT_TEST:
1871         case UHF_PORT_INDICATOR:
1872         case UHF_C_PORT_ENABLE:
1873         case UHF_C_PORT_OVER_CURRENT:
1874         case UHF_C_PORT_RESET:
1875                 /* nops */
1876                 break;
1877         case UHF_PORT_POWER:
1878                 sc->sc_flags.port_powered = 0;
1879                 atmegadci_pull_down(sc);
1880                 atmegadci_clocks_off(sc);
1881                 break;
1882         case UHF_C_PORT_CONNECTION:
1883                 /* clear connect change flag */
1884                 sc->sc_flags.change_connect = 0;
1885
1886                 if (!sc->sc_flags.status_bus_reset) {
1887                         /* we are not connected */
1888                         break;
1889                 }
1890
1891                 /* configure the control endpoint */
1892
1893                 /* select endpoint number */
1894                 ATMEGA_WRITE_1(sc, ATMEGA_UENUM, 0);
1895
1896                 /* set endpoint reset */
1897                 ATMEGA_WRITE_1(sc, ATMEGA_UERST, ATMEGA_UERST_MASK(0));
1898
1899                 /* clear endpoint reset */
1900                 ATMEGA_WRITE_1(sc, ATMEGA_UERST, 0);
1901
1902                 /* enable and stall endpoint */
1903                 ATMEGA_WRITE_1(sc, ATMEGA_UECONX,
1904                     ATMEGA_UECONX_EPEN |
1905                     ATMEGA_UECONX_STALLRQ);
1906
1907                 /* one bank, 64-bytes wMaxPacket */
1908                 ATMEGA_WRITE_1(sc, ATMEGA_UECFG0X,
1909                     ATMEGA_UECFG0X_EPTYPE0);
1910                 ATMEGA_WRITE_1(sc, ATMEGA_UECFG1X,
1911                     ATMEGA_UECFG1X_ALLOC |
1912                     ATMEGA_UECFG1X_EPBK0 |
1913                     ATMEGA_UECFG1X_EPSIZE(3));
1914
1915                 /* check valid config */
1916                 temp = ATMEGA_READ_1(sc, ATMEGA_UESTA0X);
1917                 if (!(temp & ATMEGA_UESTA0X_CFGOK)) {
1918                         device_printf(sc->sc_bus.bdev,
1919                             "Chip rejected EP0 configuration\n");
1920                 }
1921                 break;
1922         case UHF_C_PORT_SUSPEND:
1923                 sc->sc_flags.change_suspend = 0;
1924                 break;
1925         default:
1926                 err = USB_ERR_IOERROR;
1927                 goto done;
1928         }
1929         goto tr_valid;
1930
1931 tr_handle_set_port_feature:
1932         if (index != 1) {
1933                 goto tr_stalled;
1934         }
1935         DPRINTFN(9, "UR_SET_PORT_FEATURE\n");
1936
1937         switch (value) {
1938         case UHF_PORT_ENABLE:
1939                 sc->sc_flags.port_enabled = 1;
1940                 break;
1941         case UHF_PORT_SUSPEND:
1942         case UHF_PORT_RESET:
1943         case UHF_PORT_TEST:
1944         case UHF_PORT_INDICATOR:
1945                 /* nops */
1946                 break;
1947         case UHF_PORT_POWER:
1948                 sc->sc_flags.port_powered = 1;
1949                 break;
1950         default:
1951                 err = USB_ERR_IOERROR;
1952                 goto done;
1953         }
1954         goto tr_valid;
1955
1956 tr_handle_get_port_status:
1957
1958         DPRINTFN(9, "UR_GET_PORT_STATUS\n");
1959
1960         if (index != 1) {
1961                 goto tr_stalled;
1962         }
1963         if (sc->sc_flags.status_vbus) {
1964                 atmegadci_clocks_on(sc);
1965                 atmegadci_pull_up(sc);
1966         } else {
1967                 atmegadci_pull_down(sc);
1968                 atmegadci_clocks_off(sc);
1969         }
1970
1971         /* Select FULL-speed and Device Side Mode */
1972
1973         value = UPS_PORT_MODE_DEVICE;
1974
1975         if (sc->sc_flags.port_powered) {
1976                 value |= UPS_PORT_POWER;
1977         }
1978         if (sc->sc_flags.port_enabled) {
1979                 value |= UPS_PORT_ENABLED;
1980         }
1981         if (sc->sc_flags.status_vbus &&
1982             sc->sc_flags.status_bus_reset) {
1983                 value |= UPS_CURRENT_CONNECT_STATUS;
1984         }
1985         if (sc->sc_flags.status_suspend) {
1986                 value |= UPS_SUSPEND;
1987         }
1988         USETW(sc->sc_hub_temp.ps.wPortStatus, value);
1989
1990         value = 0;
1991
1992         if (sc->sc_flags.change_connect) {
1993                 value |= UPS_C_CONNECT_STATUS;
1994         }
1995         if (sc->sc_flags.change_suspend) {
1996                 value |= UPS_C_SUSPEND;
1997         }
1998         USETW(sc->sc_hub_temp.ps.wPortChange, value);
1999         len = sizeof(sc->sc_hub_temp.ps);
2000         goto tr_valid;
2001
2002 tr_handle_get_class_descriptor:
2003         if (value & 0xFF) {
2004                 goto tr_stalled;
2005         }
2006         ptr = (const void *)&atmegadci_hubd;
2007         len = sizeof(atmegadci_hubd);
2008         goto tr_valid;
2009
2010 tr_stalled:
2011         err = USB_ERR_STALLED;
2012 tr_valid:
2013 done:
2014         *plength = len;
2015         *pptr = ptr;
2016         return (err);
2017 }
2018
2019 static void
2020 atmegadci_xfer_setup(struct usb_setup_params *parm)
2021 {
2022         const struct usb_hw_ep_profile *pf;
2023         struct atmegadci_softc *sc;
2024         struct usb_xfer *xfer;
2025         void *last_obj;
2026         uint32_t ntd;
2027         uint32_t n;
2028         uint8_t ep_no;
2029
2030         sc = ATMEGA_BUS2SC(parm->udev->bus);
2031         xfer = parm->curr_xfer;
2032
2033         /*
2034          * NOTE: This driver does not use any of the parameters that
2035          * are computed from the following values. Just set some
2036          * reasonable dummies:
2037          */
2038         parm->hc_max_packet_size = 0x500;
2039         parm->hc_max_packet_count = 1;
2040         parm->hc_max_frame_size = 0x500;
2041
2042         usbd_transfer_setup_sub(parm);
2043
2044         /*
2045          * compute maximum number of TDs
2046          */
2047         if ((xfer->endpoint->edesc->bmAttributes & UE_XFERTYPE) == UE_CONTROL) {
2048
2049                 ntd = xfer->nframes + 1 /* STATUS */ + 1 /* SYNC 1 */
2050                     + 1 /* SYNC 2 */ ;
2051         } else {
2052
2053                 ntd = xfer->nframes + 1 /* SYNC */ ;
2054         }
2055
2056         /*
2057          * check if "usbd_transfer_setup_sub" set an error
2058          */
2059         if (parm->err)
2060                 return;
2061
2062         /*
2063          * allocate transfer descriptors
2064          */
2065         last_obj = NULL;
2066
2067         /*
2068          * get profile stuff
2069          */
2070         ep_no = xfer->endpointno & UE_ADDR;
2071         atmegadci_get_hw_ep_profile(parm->udev, &pf, ep_no);
2072
2073         if (pf == NULL) {
2074                 /* should not happen */
2075                 parm->err = USB_ERR_INVAL;
2076                 return;
2077         }
2078
2079         /* align data */
2080         parm->size[0] += ((-parm->size[0]) & (USB_HOST_ALIGN - 1));
2081
2082         for (n = 0; n != ntd; n++) {
2083
2084                 struct atmegadci_td *td;
2085
2086                 if (parm->buf) {
2087
2088                         td = USB_ADD_BYTES(parm->buf, parm->size[0]);
2089
2090                         /* init TD */
2091                         td->max_packet_size = xfer->max_packet_size;
2092                         td->ep_no = ep_no;
2093                         if (pf->support_multi_buffer) {
2094                                 td->support_multi_buffer = 1;
2095                         }
2096                         td->obj_next = last_obj;
2097
2098                         last_obj = td;
2099                 }
2100                 parm->size[0] += sizeof(*td);
2101         }
2102
2103         xfer->td_start[0] = last_obj;
2104 }
2105
2106 static void
2107 atmegadci_xfer_unsetup(struct usb_xfer *xfer)
2108 {
2109         return;
2110 }
2111
2112 static void
2113 atmegadci_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc,
2114     struct usb_endpoint *ep)
2115 {
2116         struct atmegadci_softc *sc = ATMEGA_BUS2SC(udev->bus);
2117
2118         DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d (%d,%d)\n",
2119             ep, udev->address,
2120             edesc->bEndpointAddress, udev->flags.usb_mode,
2121             sc->sc_rt_addr, udev->device_index);
2122
2123         if (udev->device_index != sc->sc_rt_addr) {
2124
2125                 if (udev->flags.usb_mode != USB_MODE_DEVICE) {
2126                         /* not supported */
2127                         return;
2128                 }
2129                 if (udev->speed != USB_SPEED_FULL) {
2130                         /* not supported */
2131                         return;
2132                 }
2133                 if ((edesc->bmAttributes & UE_XFERTYPE) == UE_ISOCHRONOUS)
2134                         ep->methods = &atmegadci_device_isoc_fs_methods;
2135                 else
2136                         ep->methods = &atmegadci_device_non_isoc_methods;
2137         }
2138 }
2139
2140 struct usb_bus_methods atmegadci_bus_methods =
2141 {
2142         .endpoint_init = &atmegadci_ep_init,
2143         .xfer_setup = &atmegadci_xfer_setup,
2144         .xfer_unsetup = &atmegadci_xfer_unsetup,
2145         .get_hw_ep_profile = &atmegadci_get_hw_ep_profile,
2146         .set_stall = &atmegadci_set_stall,
2147         .clear_stall = &atmegadci_clear_stall,
2148         .roothub_exec = &atmegadci_roothub_exec,
2149         .xfer_poll = &atmegadci_do_poll,
2150 };