2 * Copyright (c) 1992 Terrence R. Lambert.
3 * Copyright (c) 1982, 1987, 1990 The Regents of the University of California.
4 * Copyright (c) 1997 KATO Takenori.
7 * This code is derived from software contributed to Berkeley by
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 * 3. All advertising materials mentioning features or use of this software
19 * must display the following acknowledgement:
20 * This product includes software developed by the University of
21 * California, Berkeley and its contributors.
22 * 4. Neither the name of the University nor the names of its contributors
23 * may be used to endorse or promote products derived from this software
24 * without specific prior written permission.
26 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
29 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
30 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
38 * from: Id: machdep.c,v 1.193 1996/06/18 01:22:04 bde Exp
41 #include <sys/cdefs.h>
42 __FBSDID("$FreeBSD$");
46 #include <sys/param.h>
49 #include <sys/eventhandler.h>
50 #include <sys/systm.h>
51 #include <sys/kernel.h>
52 #include <sys/sysctl.h>
53 #include <sys/power.h>
55 #include <machine/asmacros.h>
56 #include <machine/clock.h>
57 #include <machine/cputypes.h>
58 #include <machine/intr_machdep.h>
59 #include <machine/md_var.h>
60 #include <machine/segments.h>
61 #include <machine/specialreg.h>
63 #define IDENTBLUE_CYRIX486 0
64 #define IDENTBLUE_IBMCPU 1
65 #define IDENTBLUE_CYRIXM2 2
67 /* XXX - should be in header file: */
68 void printcpuinfo(void);
69 void finishidentcpu(void);
70 void earlysetcpuclass(void);
71 #if defined(I586_CPU) && defined(CPU_WT_ALLOC)
72 void enable_K5_wt_alloc(void);
73 void enable_K6_wt_alloc(void);
74 void enable_K6_2_wt_alloc(void);
76 void panicifcpuunsupported(void);
78 static void identifycyrix(void);
79 static void init_exthigh(void);
80 static u_int find_cpu_vendor_id(void);
81 static void print_AMD_info(void);
82 static void print_INTEL_info(void);
83 static void print_INTEL_TLB(u_int data);
84 static void print_AMD_assoc(int i);
85 static void print_transmeta_info(void);
86 static void print_via_padlock_info(void);
89 u_int cpu_exthigh; /* Highest arg to extended CPUID */
90 u_int cyrix_did; /* Device ID of Cyrix CPU */
91 char machine[] = MACHINE;
92 SYSCTL_STRING(_hw, HW_MACHINE, machine, CTLFLAG_RD,
93 machine, 0, "Machine class");
95 static char cpu_model[128];
96 SYSCTL_STRING(_hw, HW_MODEL, model, CTLFLAG_RD,
97 cpu_model, 0, "Machine model");
99 static int hw_clockrate;
100 SYSCTL_INT(_hw, OID_AUTO, clockrate, CTLFLAG_RD,
101 &hw_clockrate, 0, "CPU instruction clock rate");
103 static char cpu_brand[48];
105 #define MAX_BRAND_INDEX 8
107 static const char *cpu_brandtable[MAX_BRAND_INDEX + 1] = {
111 "Intel Pentium III Xeon",
123 { "Intel 80286", CPUCLASS_286 }, /* CPU_286 */
124 { "i386SX", CPUCLASS_386 }, /* CPU_386SX */
125 { "i386DX", CPUCLASS_386 }, /* CPU_386 */
126 { "i486SX", CPUCLASS_486 }, /* CPU_486SX */
127 { "i486DX", CPUCLASS_486 }, /* CPU_486 */
128 { "Pentium", CPUCLASS_586 }, /* CPU_586 */
129 { "Cyrix 486", CPUCLASS_486 }, /* CPU_486DLC */
130 { "Pentium Pro", CPUCLASS_686 }, /* CPU_686 */
131 { "Cyrix 5x86", CPUCLASS_486 }, /* CPU_M1SC */
132 { "Cyrix 6x86", CPUCLASS_486 }, /* CPU_M1 */
133 { "Blue Lightning", CPUCLASS_486 }, /* CPU_BLUE */
134 { "Cyrix 6x86MX", CPUCLASS_686 }, /* CPU_M2 */
135 { "NexGen 586", CPUCLASS_386 }, /* CPU_NX586 (XXX) */
136 { "Cyrix 486S/DX", CPUCLASS_486 }, /* CPU_CY486DX */
137 { "Pentium II", CPUCLASS_686 }, /* CPU_PII */
138 { "Pentium III", CPUCLASS_686 }, /* CPU_PIII */
139 { "Pentium 4", CPUCLASS_686 }, /* CPU_P4 */
146 { INTEL_VENDOR_ID, CPU_VENDOR_INTEL }, /* GenuineIntel */
147 { AMD_VENDOR_ID, CPU_VENDOR_AMD }, /* AuthenticAMD */
148 { CENTAUR_VENDOR_ID, CPU_VENDOR_CENTAUR }, /* CentaurHauls */
149 { NSC_VENDOR_ID, CPU_VENDOR_NSC }, /* Geode by NSC */
150 { CYRIX_VENDOR_ID, CPU_VENDOR_CYRIX }, /* CyrixInstead */
151 { TRANSMETA_VENDOR_ID, CPU_VENDOR_TRANSMETA }, /* GenuineTMx86 */
152 { SIS_VENDOR_ID, CPU_VENDOR_SIS }, /* SiS SiS SiS */
153 { UMC_VENDOR_ID, CPU_VENDOR_UMC }, /* UMC UMC UMC */
154 { NEXGEN_VENDOR_ID, CPU_VENDOR_NEXGEN }, /* NexGenDriven */
155 { RISE_VENDOR_ID, CPU_VENDOR_RISE }, /* RiseRiseRise */
157 /* XXX CPUID 8000_0000h and 8086_0000h, not 0000_0000h */
158 { "TransmetaCPU", CPU_VENDOR_TRANSMETA },
162 #if defined(I586_CPU) && !defined(NO_F00F_HACK)
163 int has_f00f_bug = 0; /* Initialized so that it can be patched. */
174 (cpu_vendor_id == CPU_VENDOR_INTEL ||
175 cpu_vendor_id == CPU_VENDOR_AMD ||
176 cpu_vendor_id == CPU_VENDOR_TRANSMETA ||
177 cpu_vendor_id == CPU_VENDOR_CENTAUR ||
178 cpu_vendor_id == CPU_VENDOR_NSC)) {
179 do_cpuid(0x80000000, regs);
180 if (regs[0] >= 0x80000000)
181 cpu_exthigh = regs[0];
194 cpu_class = i386_cpus[cpu].cpu_class;
196 strncpy(cpu_model, i386_cpus[cpu].cpu_name, sizeof (cpu_model));
198 /* Check for extended CPUID information and a processor name. */
200 if (cpu_exthigh >= 0x80000004) {
202 for (i = 0x80000002; i < 0x80000005; i++) {
204 memcpy(brand, regs, sizeof(regs));
205 brand += sizeof(regs);
209 if (cpu_vendor_id == CPU_VENDOR_INTEL) {
210 if ((cpu_id & 0xf00) > 0x300) {
215 switch (cpu_id & 0x3000) {
217 strcpy(cpu_model, "Overdrive ");
220 strcpy(cpu_model, "Dual ");
224 switch (cpu_id & 0xf00) {
226 strcat(cpu_model, "i486 ");
227 /* Check the particular flavor of 486 */
228 switch (cpu_id & 0xf0) {
231 strcat(cpu_model, "DX");
234 strcat(cpu_model, "SX");
237 strcat(cpu_model, "DX2");
240 strcat(cpu_model, "SL");
243 strcat(cpu_model, "SX2");
247 "DX2 Write-Back Enhanced");
250 strcat(cpu_model, "DX4");
255 /* Check the particular flavor of 586 */
256 strcat(cpu_model, "Pentium");
257 switch (cpu_id & 0xf0) {
259 strcat(cpu_model, " A-step");
262 strcat(cpu_model, "/P5");
265 strcat(cpu_model, "/P54C");
268 strcat(cpu_model, "/P24T");
271 strcat(cpu_model, "/P55C");
274 strcat(cpu_model, "/P54C");
277 strcat(cpu_model, "/P55C (quarter-micron)");
283 #if defined(I586_CPU) && !defined(NO_F00F_HACK)
285 * XXX - If/when Intel fixes the bug, this
286 * should also check the version of the
287 * CPU, not just that it's a Pentium.
293 /* Check the particular flavor of 686 */
294 switch (cpu_id & 0xf0) {
296 strcat(cpu_model, "Pentium Pro A-step");
299 strcat(cpu_model, "Pentium Pro");
305 "Pentium II/Pentium II Xeon/Celeron");
313 "Pentium III/Pentium III Xeon/Celeron");
317 strcat(cpu_model, "Unknown 80686");
322 strcat(cpu_model, "Pentium 4");
326 strcat(cpu_model, "unknown");
331 * If we didn't get a brand name from the extended
332 * CPUID, try to look it up in the brand table.
334 if (cpu_high > 0 && *cpu_brand == '\0') {
335 brand_index = cpu_procinfo & CPUID_BRAND_INDEX;
336 if (brand_index <= MAX_BRAND_INDEX &&
337 cpu_brandtable[brand_index] != NULL)
339 cpu_brandtable[brand_index]);
342 } else if (cpu_vendor_id == CPU_VENDOR_AMD) {
344 * Values taken from AMD Processor Recognition
345 * http://www.amd.com/K6/k6docs/pdf/20734g.pdf
346 * (also describes ``Features'' encodings.
348 strcpy(cpu_model, "AMD ");
349 switch (cpu_id & 0xFF0) {
351 strcat(cpu_model, "Standard Am486DX");
354 strcat(cpu_model, "Enhanced Am486DX2 Write-Through");
357 strcat(cpu_model, "Enhanced Am486DX2 Write-Back");
360 strcat(cpu_model, "Enhanced Am486DX4/Am5x86 Write-Through");
363 strcat(cpu_model, "Enhanced Am486DX4/Am5x86 Write-Back");
366 strcat(cpu_model, "Am5x86 Write-Through");
369 strcat(cpu_model, "Am5x86 Write-Back");
372 strcat(cpu_model, "K5 model 0");
376 strcat(cpu_model, "K5 model 1");
379 strcat(cpu_model, "K5 PR166 (model 2)");
382 strcat(cpu_model, "K5 PR200 (model 3)");
385 strcat(cpu_model, "K6");
388 strcat(cpu_model, "K6 266 (model 1)");
391 strcat(cpu_model, "K6-2");
394 strcat(cpu_model, "K6-III");
397 strcat(cpu_model, "Geode LX");
399 * Make sure the TSC runs through suspension,
400 * otherwise we can't use it as timecounter
402 wrmsr(0x1900, rdmsr(0x1900) | 0x20ULL);
405 strcat(cpu_model, "Unknown");
408 #if defined(I586_CPU) && defined(CPU_WT_ALLOC)
409 if ((cpu_id & 0xf00) == 0x500) {
410 if (((cpu_id & 0x0f0) > 0)
411 && ((cpu_id & 0x0f0) < 0x60)
412 && ((cpu_id & 0x00f) > 3))
413 enable_K5_wt_alloc();
414 else if (((cpu_id & 0x0f0) > 0x80)
415 || (((cpu_id & 0x0f0) == 0x80)
416 && (cpu_id & 0x00f) > 0x07))
417 enable_K6_2_wt_alloc();
418 else if ((cpu_id & 0x0f0) > 0x50)
419 enable_K6_wt_alloc();
422 } else if (cpu_vendor_id == CPU_VENDOR_CYRIX) {
423 strcpy(cpu_model, "Cyrix ");
424 switch (cpu_id & 0xff0) {
426 strcat(cpu_model, "MediaGX");
429 strcat(cpu_model, "6x86");
432 cpu_class = CPUCLASS_586;
433 strcat(cpu_model, "GXm");
436 strcat(cpu_model, "6x86MX");
440 * Even though CPU supports the cpuid
441 * instruction, it can be disabled.
442 * Therefore, this routine supports all Cyrix
445 switch (cyrix_did & 0xf0) {
447 switch (cyrix_did & 0x0f) {
449 strcat(cpu_model, "486SLC");
452 strcat(cpu_model, "486DLC");
455 strcat(cpu_model, "486SLC2");
458 strcat(cpu_model, "486DLC2");
461 strcat(cpu_model, "486SRx");
464 strcat(cpu_model, "486DRx");
467 strcat(cpu_model, "486SRx2");
470 strcat(cpu_model, "486DRx2");
473 strcat(cpu_model, "486SRu");
476 strcat(cpu_model, "486DRu");
479 strcat(cpu_model, "486SRu2");
482 strcat(cpu_model, "486DRu2");
485 strcat(cpu_model, "Unknown");
490 switch (cyrix_did & 0x0f) {
492 strcat(cpu_model, "486S");
495 strcat(cpu_model, "486S2");
498 strcat(cpu_model, "486Se");
501 strcat(cpu_model, "486S2e");
504 strcat(cpu_model, "486DX");
507 strcat(cpu_model, "486DX2");
510 strcat(cpu_model, "486DX4");
513 strcat(cpu_model, "Unknown");
518 if ((cyrix_did & 0x0f) < 8)
519 strcat(cpu_model, "6x86"); /* Where did you get it? */
521 strcat(cpu_model, "5x86");
524 strcat(cpu_model, "6x86");
527 if ((cyrix_did & 0xf000) == 0x3000) {
528 cpu_class = CPUCLASS_586;
529 strcat(cpu_model, "GXm");
531 strcat(cpu_model, "MediaGX");
534 strcat(cpu_model, "6x86MX");
537 switch (cyrix_did & 0x0f) {
539 strcat(cpu_model, "Overdrive CPU");
542 strcpy(cpu_model, "Texas Instruments 486SXL");
545 strcat(cpu_model, "486SLC/DLC");
548 strcat(cpu_model, "Unknown");
553 strcat(cpu_model, "Unknown");
558 } else if (cpu_vendor_id == CPU_VENDOR_RISE) {
559 strcpy(cpu_model, "Rise ");
560 switch (cpu_id & 0xff0) {
562 strcat(cpu_model, "mP6");
565 strcat(cpu_model, "Unknown");
567 } else if (cpu_vendor_id == CPU_VENDOR_CENTAUR) {
568 switch (cpu_id & 0xff0) {
570 strcpy(cpu_model, "IDT WinChip C6");
574 strcpy(cpu_model, "IDT WinChip 2");
577 strcpy(cpu_model, "VIA C3 Samuel");
581 strcpy(cpu_model, "VIA C3 Ezra");
583 strcpy(cpu_model, "VIA C3 Samuel 2");
586 strcpy(cpu_model, "VIA C3 Ezra-T");
589 strcpy(cpu_model, "VIA C3 Nehemiah");
593 strcpy(cpu_model, "VIA C7 Esther");
596 strcpy(cpu_model, "VIA Nano");
599 strcpy(cpu_model, "VIA/IDT Unknown");
601 } else if (cpu_vendor_id == CPU_VENDOR_IBM) {
602 strcpy(cpu_model, "Blue Lightning CPU");
603 } else if (cpu_vendor_id == CPU_VENDOR_NSC) {
604 switch (cpu_id & 0xfff) {
606 strcpy(cpu_model, "Geode SC1100");
611 strcpy(cpu_model, "Geode/NSC unknown");
617 * Replace cpu_model with cpu_brand minus leading spaces if
621 while (*brand == ' ')
624 strcpy(cpu_model, brand);
626 printf("%s (", cpu_model);
634 #if defined(I486_CPU)
637 bzero_vector = i486_bzero;
640 #if defined(I586_CPU)
642 hw_clockrate = (tsc_freq + 5000) / 1000000;
643 printf("%jd.%02d-MHz ",
644 (intmax_t)(tsc_freq + 4999) / 1000000,
645 (u_int)((tsc_freq + 4999) / 10000) % 100);
649 #if defined(I686_CPU)
651 hw_clockrate = (tsc_freq + 5000) / 1000000;
652 printf("%jd.%02d-MHz ",
653 (intmax_t)(tsc_freq + 4999) / 1000000,
654 (u_int)((tsc_freq + 4999) / 10000) % 100);
659 printf("Unknown"); /* will panic below... */
661 printf("-class CPU)\n");
663 printf(" Origin = \"%s\"",cpu_vendor);
665 printf(" Id = 0x%x", cpu_id);
667 if (cpu_vendor_id == CPU_VENDOR_INTEL ||
668 cpu_vendor_id == CPU_VENDOR_AMD ||
669 cpu_vendor_id == CPU_VENDOR_TRANSMETA ||
670 cpu_vendor_id == CPU_VENDOR_RISE ||
671 cpu_vendor_id == CPU_VENDOR_CENTAUR ||
672 cpu_vendor_id == CPU_VENDOR_NSC ||
673 (cpu_vendor_id == CPU_VENDOR_CYRIX &&
674 ((cpu_id & 0xf00) > 0x500))) {
675 printf(" Family = %x", CPUID_TO_FAMILY(cpu_id));
676 printf(" Model = %x", CPUID_TO_MODEL(cpu_id));
677 printf(" Stepping = %u", cpu_id & CPUID_STEPPING);
678 if (cpu_vendor_id == CPU_VENDOR_CYRIX)
679 printf("\n DIR=0x%04x", cyrix_did);
683 * Here we should probably set up flags indicating
684 * whether or not various features are available.
685 * The interesting ones are probably VME, PSE, PAE,
686 * and PGE. The code already assumes without bothering
687 * to check that all CPUs >= Pentium have a TSC and
690 printf("\n Features=0x%b", cpu_feature,
692 "\001FPU" /* Integral FPU */
693 "\002VME" /* Extended VM86 mode support */
694 "\003DE" /* Debugging Extensions (CR4.DE) */
695 "\004PSE" /* 4MByte page tables */
696 "\005TSC" /* Timestamp counter */
697 "\006MSR" /* Machine specific registers */
698 "\007PAE" /* Physical address extension */
699 "\010MCE" /* Machine Check support */
700 "\011CX8" /* CMPEXCH8 instruction */
701 "\012APIC" /* SMP local APIC */
702 "\013oldMTRR" /* Previous implementation of MTRR */
703 "\014SEP" /* Fast System Call */
704 "\015MTRR" /* Memory Type Range Registers */
705 "\016PGE" /* PG_G (global bit) support */
706 "\017MCA" /* Machine Check Architecture */
707 "\020CMOV" /* CMOV instruction */
708 "\021PAT" /* Page attributes table */
709 "\022PSE36" /* 36 bit address space support */
710 "\023PN" /* Processor Serial number */
711 "\024CLFLUSH" /* Has the CLFLUSH instruction */
713 "\026DTS" /* Debug Trace Store */
714 "\027ACPI" /* ACPI support */
715 "\030MMX" /* MMX instructions */
716 "\031FXSR" /* FXSAVE/FXRSTOR */
717 "\032SSE" /* Streaming SIMD Extensions */
718 "\033SSE2" /* Streaming SIMD Extensions #2 */
719 "\034SS" /* Self snoop */
720 "\035HTT" /* Hyperthreading (see EBX bit 16-23) */
721 "\036TM" /* Thermal Monitor clock slowdown */
722 "\037IA64" /* CPU can execute IA64 instructions */
723 "\040PBE" /* Pending Break Enable */
726 if (cpu_feature2 != 0) {
727 printf("\n Features2=0x%b", cpu_feature2,
729 "\001SSE3" /* SSE3 */
730 "\002PCLMULQDQ" /* Carry-Less Mul Quadword */
731 "\003DTES64" /* 64-bit Debug Trace */
732 "\004MON" /* MONITOR/MWAIT Instructions */
733 "\005DS_CPL" /* CPL Qualified Debug Store */
734 "\006VMX" /* Virtual Machine Extensions */
735 "\007SMX" /* Safer Mode Extensions */
736 "\010EST" /* Enhanced SpeedStep */
737 "\011TM2" /* Thermal Monitor 2 */
738 "\012SSSE3" /* SSSE3 */
739 "\013CNXT-ID" /* L1 context ID available */
742 "\016CX16" /* CMPXCHG16B Instruction */
743 "\017xTPR" /* Send Task Priority Messages*/
744 "\020PDCM" /* Perf/Debug Capability MSR */
747 "\023DCA" /* Direct Cache Access */
750 "\026x2APIC" /* xAPIC Extensions */
754 "\032AESNI" /* AES Crypto*/
765 * AMD64 Architecture Programmer's Manual Volume 3:
766 * General-Purpose and System Instructions
767 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/24594.pdf
769 * IA-32 Intel Architecture Software Developer's Manual,
770 * Volume 2A: Instruction Set Reference, A-M
771 * ftp://download.intel.com/design/Pentium4/manuals/25366617.pdf
773 if (amd_feature != 0) {
774 printf("\n AMD Features=0x%b", amd_feature,
776 "\001<s0>" /* Same */
777 "\002<s1>" /* Same */
778 "\003<s2>" /* Same */
779 "\004<s3>" /* Same */
780 "\005<s4>" /* Same */
781 "\006<s5>" /* Same */
782 "\007<s6>" /* Same */
783 "\010<s7>" /* Same */
784 "\011<s8>" /* Same */
785 "\012<s9>" /* Same */
786 "\013<b10>" /* Undefined */
787 "\014SYSCALL" /* Have SYSCALL/SYSRET */
788 "\015<s12>" /* Same */
789 "\016<s13>" /* Same */
790 "\017<s14>" /* Same */
791 "\020<s15>" /* Same */
792 "\021<s16>" /* Same */
793 "\022<s17>" /* Same */
794 "\023<b18>" /* Reserved, unknown */
795 "\024MP" /* Multiprocessor Capable */
796 "\025NX" /* Has EFER.NXE, NX */
797 "\026<b21>" /* Undefined */
798 "\027MMX+" /* AMD MMX Extensions */
799 "\030<s23>" /* Same */
800 "\031<s24>" /* Same */
801 "\032FFXSR" /* Fast FXSAVE/FXRSTOR */
802 "\033Page1GB" /* 1-GB large page support */
803 "\034RDTSCP" /* RDTSCP */
804 "\035<b28>" /* Undefined */
805 "\036LM" /* 64 bit long mode */
806 "\0373DNow!+" /* AMD 3DNow! Extensions */
807 "\0403DNow!" /* AMD 3DNow! */
811 if (amd_feature2 != 0) {
812 printf("\n AMD Features2=0x%b", amd_feature2,
814 "\001LAHF" /* LAHF/SAHF in long mode */
815 "\002CMP" /* CMP legacy */
816 "\003SVM" /* Secure Virtual Mode */
817 "\004ExtAPIC" /* Extended APIC register */
818 "\005CR8" /* CR8 in legacy mode */
819 "\006ABM" /* LZCNT instruction */
820 "\007SSE4A" /* SSE4A */
821 "\010MAS" /* Misaligned SSE mode */
822 "\011Prefetch" /* 3DNow! Prefetch/PrefetchW */
823 "\012OSVW" /* OS visible workaround */
824 "\013IBS" /* Instruction based sampling */
825 "\014SSE5" /* SSE5 */
826 "\015SKINIT" /* SKINIT/STGI */
827 "\016WDT" /* Watchdog timer */
849 if (cpu_vendor_id == CPU_VENDOR_CENTAUR)
850 print_via_padlock_info();
852 if ((cpu_feature & CPUID_HTT) &&
853 cpu_vendor_id == CPU_VENDOR_AMD)
854 cpu_feature &= ~CPUID_HTT;
857 * If this CPU supports P-state invariant TSC then
858 * mention the capability.
860 switch (cpu_vendor_id) {
862 if ((amd_pminfo & AMDPM_TSC_INVARIANT) ||
863 CPUID_TO_FAMILY(cpu_id) >= 0x10 ||
865 tsc_is_invariant = 1;
867 case CPU_VENDOR_INTEL:
868 if ((amd_pminfo & AMDPM_TSC_INVARIANT) ||
869 (CPUID_TO_FAMILY(cpu_id) == 0x6 &&
870 CPUID_TO_MODEL(cpu_id) >= 0xe) ||
871 (CPUID_TO_FAMILY(cpu_id) == 0xf &&
872 CPUID_TO_MODEL(cpu_id) >= 0x3))
873 tsc_is_invariant = 1;
875 case CPU_VENDOR_CENTAUR:
876 if (CPUID_TO_FAMILY(cpu_id) == 0x6 &&
877 CPUID_TO_MODEL(cpu_id) >= 0xf &&
878 (rdmsr(0x1203) & 0x100000000ULL) == 0)
879 tsc_is_invariant = 1;
882 if (tsc_is_invariant)
883 printf("\n TSC: P-state invariant");
886 } else if (cpu_vendor_id == CPU_VENDOR_CYRIX) {
887 printf(" DIR=0x%04x", cyrix_did);
888 printf(" Stepping=%u", (cyrix_did & 0xf000) >> 12);
889 printf(" Revision=%u", (cyrix_did & 0x0f00) >> 8);
890 #ifndef CYRIX_CACHE_REALLY_WORKS
891 if (cpu == CPU_M1 && (cyrix_did & 0xff00) < 0x1700)
892 printf("\n CPU cache: write-through mode");
896 /* Avoid ugly blank lines: only print newline when we have to. */
897 if (*cpu_vendor || cpu_id)
903 if (cpu_vendor_id == CPU_VENDOR_AMD)
905 else if (cpu_vendor_id == CPU_VENDOR_INTEL)
907 else if (cpu_vendor_id == CPU_VENDOR_TRANSMETA)
908 print_transmeta_info();
912 panicifcpuunsupported(void)
916 #if !defined(I486_CPU) && !defined(I586_CPU) && !defined(I686_CPU)
917 #error This kernel is not configured for one of the supported CPUs
922 * Now that we have told the user what they have,
923 * let them know if that machine type isn't configured.
926 case CPUCLASS_286: /* a 286 should not make it this far, anyway */
928 #if !defined(I486_CPU)
931 #if !defined(I586_CPU)
934 #if !defined(I686_CPU)
937 panic("CPU class not configured");
944 static volatile u_int trap_by_rdmsr;
947 * Special exception 6 handler.
948 * The rdmsr instruction generates invalid opcodes fault on 486-class
949 * Cyrix CPU. Stacked eip register points the rdmsr instruction in the
950 * function identblue() when this handler is called. Stacked eip should
954 #ifdef __GNUCLIKE_ASM
959 .type " __XSTRING(CNAME(bluetrap6)) ",@function \n\
960 " __XSTRING(CNAME(bluetrap6)) ": \n\
962 movl $0xa8c1d," __XSTRING(CNAME(trap_by_rdmsr)) " \n\
963 addl $2, (%esp) /* rdmsr is a 2-byte instruction */ \n\
969 * Special exception 13 handler.
970 * Accessing non-existent MSR generates general protection fault.
972 inthand_t bluetrap13;
973 #ifdef __GNUCLIKE_ASM
978 .type " __XSTRING(CNAME(bluetrap13)) ",@function \n\
979 " __XSTRING(CNAME(bluetrap13)) ": \n\
981 movl $0xa89c4," __XSTRING(CNAME(trap_by_rdmsr)) " \n\
982 popl %eax /* discard error code */ \n\
983 addl $2, (%esp) /* rdmsr is a 2-byte instruction */ \n\
989 * Distinguish IBM Blue Lightning CPU from Cyrix CPUs that does not
990 * support cpuid instruction. This function should be called after
991 * loading interrupt descriptor table register.
993 * I don't like this method that handles fault, but I couldn't get
994 * information for any other methods. Does blue giant know?
1003 * Cyrix 486-class CPU does not support rdmsr instruction.
1004 * The rdmsr instruction generates invalid opcode fault, and exception
1005 * will be trapped by bluetrap6() on Cyrix 486-class CPU. The
1006 * bluetrap6() set the magic number to trap_by_rdmsr.
1008 setidt(IDT_UD, bluetrap6, SDT_SYS386TGT, SEL_KPL,
1009 GSEL(GCODE_SEL, SEL_KPL));
1012 * Certain BIOS disables cpuid instruction of Cyrix 6x86MX CPU.
1013 * In this case, rdmsr generates general protection fault, and
1014 * exception will be trapped by bluetrap13().
1016 setidt(IDT_GP, bluetrap13, SDT_SYS386TGT, SEL_KPL,
1017 GSEL(GCODE_SEL, SEL_KPL));
1019 rdmsr(0x1002); /* Cyrix CPU generates fault. */
1021 if (trap_by_rdmsr == 0xa8c1d)
1022 return IDENTBLUE_CYRIX486;
1023 else if (trap_by_rdmsr == 0xa89c4)
1024 return IDENTBLUE_CYRIXM2;
1025 return IDENTBLUE_IBMCPU;
1030 * identifycyrix() set lower 16 bits of cyrix_did as follows:
1032 * F E D C B A 9 8 7 6 5 4 3 2 1 0
1033 * +-------+-------+---------------+
1034 * | SID | RID | Device ID |
1035 * | (DIR 1) | (DIR 0) |
1036 * +-------+-------+---------------+
1042 int ccr2_test = 0, dir_test = 0;
1045 eflags = read_eflags();
1048 ccr2 = read_cyrix_reg(CCR2);
1049 write_cyrix_reg(CCR2, ccr2 ^ CCR2_LOCK_NW);
1050 read_cyrix_reg(CCR2);
1051 if (read_cyrix_reg(CCR2) != ccr2)
1053 write_cyrix_reg(CCR2, ccr2);
1055 ccr3 = read_cyrix_reg(CCR3);
1056 write_cyrix_reg(CCR3, ccr3 ^ CCR3_MAPEN3);
1057 read_cyrix_reg(CCR3);
1058 if (read_cyrix_reg(CCR3) != ccr3)
1059 dir_test = 1; /* CPU supports DIRs. */
1060 write_cyrix_reg(CCR3, ccr3);
1063 /* Device ID registers are available. */
1064 cyrix_did = read_cyrix_reg(DIR1) << 8;
1065 cyrix_did += read_cyrix_reg(DIR0);
1066 } else if (ccr2_test)
1067 cyrix_did = 0x0010; /* 486S A-step */
1069 cyrix_did = 0x00ff; /* Old 486SLC/DLC and TI486SXLC/SXL */
1071 write_eflags(eflags);
1074 /* Update TSC freq with the value indicated by the caller. */
1076 tsc_freq_changed(void *arg, const struct cf_level *level, int status)
1079 * If there was an error during the transition or
1080 * TSC is P-state invariant, don't do anything.
1082 if (status != 0 || tsc_is_invariant)
1085 /* Total setting for this level gives the new frequency in MHz. */
1086 hw_clockrate = level->total_set.freq;
1089 EVENTHANDLER_DEFINE(cpufreq_post_change, tsc_freq_changed, NULL,
1090 EVENTHANDLER_PRI_ANY);
1093 * Final stage of CPU identification. -- Should I check TI?
1096 finishidentcpu(void)
1102 cpu_vendor_id = find_cpu_vendor_id();
1105 * Clear "Limit CPUID Maxval" bit and get the largest standard CPUID
1106 * function number again if it is set from BIOS. It is necessary
1107 * for probing correct CPU topology later.
1108 * XXX This is only done on the BSP package.
1110 if (cpu_vendor_id == CPU_VENDOR_INTEL && cpu_high > 0 && cpu_high < 4 &&
1111 ((CPUID_TO_FAMILY(cpu_id) == 0xf && CPUID_TO_MODEL(cpu_id) >= 0x3) ||
1112 (CPUID_TO_FAMILY(cpu_id) == 0x6 && CPUID_TO_MODEL(cpu_id) >= 0xe))) {
1114 msr = rdmsr(MSR_IA32_MISC_ENABLE);
1115 if ((msr & 0x400000ULL) != 0) {
1116 wrmsr(MSR_IA32_MISC_ENABLE, msr & ~0x400000ULL);
1122 /* Detect AMD features (PTE no-execute bit, 3dnow, 64 bit mode etc) */
1123 if (cpu_vendor_id == CPU_VENDOR_INTEL ||
1124 cpu_vendor_id == CPU_VENDOR_AMD) {
1126 if (cpu_exthigh >= 0x80000001) {
1127 do_cpuid(0x80000001, regs);
1128 amd_feature = regs[3] & ~(cpu_feature & 0x0183f3ff);
1129 amd_feature2 = regs[2];
1131 if (cpu_exthigh >= 0x80000007) {
1132 do_cpuid(0x80000007, regs);
1133 amd_pminfo = regs[3];
1135 if (cpu_exthigh >= 0x80000008) {
1136 do_cpuid(0x80000008, regs);
1137 cpu_procinfo2 = regs[2];
1139 } else if (cpu_vendor_id == CPU_VENDOR_CYRIX) {
1140 if (cpu == CPU_486) {
1142 * These conditions are equivalent to:
1143 * - CPU does not support cpuid instruction.
1144 * - Cyrix/IBM CPU is detected.
1146 isblue = identblue();
1147 if (isblue == IDENTBLUE_IBMCPU) {
1148 strcpy(cpu_vendor, "IBM");
1149 cpu_vendor_id = CPU_VENDOR_IBM;
1154 switch (cpu_id & 0xf00) {
1157 * Cyrix's datasheet does not describe DIRs.
1158 * Therefor, I assume it does not have them
1159 * and use the result of the cpuid instruction.
1160 * XXX they seem to have it for now at least. -Peter
1168 * This routine contains a trick.
1169 * Don't check (cpu_id & 0x00f0) == 0x50 to detect M2, now.
1171 switch (cyrix_did & 0x00f0) {
1180 if ((cyrix_did & 0x000f) < 8)
1193 /* M2 and later CPUs are treated as M2. */
1197 * enable cpuid instruction.
1199 ccr3 = read_cyrix_reg(CCR3);
1200 write_cyrix_reg(CCR3, CCR3_MAPEN0);
1201 write_cyrix_reg(CCR4, read_cyrix_reg(CCR4) | CCR4_CPUID);
1202 write_cyrix_reg(CCR3, ccr3);
1205 cpu_high = regs[0]; /* eax */
1207 cpu_id = regs[0]; /* eax */
1208 cpu_feature = regs[3]; /* edx */
1212 } else if (cpu == CPU_486 && *cpu_vendor == '\0') {
1214 * There are BlueLightning CPUs that do not change
1215 * undefined flags by dividing 5 by 2. In this case,
1216 * the CPU identification routine in locore.s leaves
1217 * cpu_vendor null string and puts CPU_486 into the
1220 isblue = identblue();
1221 if (isblue == IDENTBLUE_IBMCPU) {
1222 strcpy(cpu_vendor, "IBM");
1223 cpu_vendor_id = CPU_VENDOR_IBM;
1231 find_cpu_vendor_id(void)
1235 for (i = 0; i < sizeof(cpu_vendors) / sizeof(cpu_vendors[0]); i++)
1236 if (strcmp(cpu_vendor, cpu_vendors[i].vendor) == 0)
1237 return (cpu_vendors[i].vendor_id);
1242 print_AMD_assoc(int i)
1245 printf(", fully associative\n");
1247 printf(", %d-way associative\n", i);
1251 print_AMD_info(void)
1255 if (cpu_exthigh >= 0x80000005) {
1258 do_cpuid(0x80000005, regs);
1259 printf("Data TLB: %d entries", (regs[1] >> 16) & 0xff);
1260 print_AMD_assoc(regs[1] >> 24);
1261 printf("Instruction TLB: %d entries", regs[1] & 0xff);
1262 print_AMD_assoc((regs[1] >> 8) & 0xff);
1263 printf("L1 data cache: %d kbytes", regs[2] >> 24);
1264 printf(", %d bytes/line", regs[2] & 0xff);
1265 printf(", %d lines/tag", (regs[2] >> 8) & 0xff);
1266 print_AMD_assoc((regs[2] >> 16) & 0xff);
1267 printf("L1 instruction cache: %d kbytes", regs[3] >> 24);
1268 printf(", %d bytes/line", regs[3] & 0xff);
1269 printf(", %d lines/tag", (regs[3] >> 8) & 0xff);
1270 print_AMD_assoc((regs[3] >> 16) & 0xff);
1271 if (cpu_exthigh >= 0x80000006) { /* K6-III only */
1272 do_cpuid(0x80000006, regs);
1273 printf("L2 internal cache: %d kbytes", regs[2] >> 16);
1274 printf(", %d bytes/line", regs[2] & 0xff);
1275 printf(", %d lines/tag", (regs[2] >> 8) & 0x0f);
1276 print_AMD_assoc((regs[2] >> 12) & 0x0f);
1279 if (((cpu_id & 0xf00) == 0x500)
1280 && (((cpu_id & 0x0f0) > 0x80)
1281 || (((cpu_id & 0x0f0) == 0x80)
1282 && (cpu_id & 0x00f) > 0x07))) {
1283 /* K6-2(new core [Stepping 8-F]), K6-III or later */
1284 amd_whcr = rdmsr(0xc0000082);
1285 if (!(amd_whcr & (0x3ff << 22))) {
1286 printf("Write Allocate Disable\n");
1288 printf("Write Allocate Enable Limit: %dM bytes\n",
1289 (u_int32_t)((amd_whcr & (0x3ff << 22)) >> 22) * 4);
1290 printf("Write Allocate 15-16M bytes: %s\n",
1291 (amd_whcr & (1 << 16)) ? "Enable" : "Disable");
1293 } else if (((cpu_id & 0xf00) == 0x500)
1294 && ((cpu_id & 0x0f0) > 0x50)) {
1295 /* K6, K6-2(old core) */
1296 amd_whcr = rdmsr(0xc0000082);
1297 if (!(amd_whcr & (0x7f << 1))) {
1298 printf("Write Allocate Disable\n");
1300 printf("Write Allocate Enable Limit: %dM bytes\n",
1301 (u_int32_t)((amd_whcr & (0x7f << 1)) >> 1) * 4);
1302 printf("Write Allocate 15-16M bytes: %s\n",
1303 (amd_whcr & 0x0001) ? "Enable" : "Disable");
1304 printf("Hardware Write Allocate Control: %s\n",
1305 (amd_whcr & 0x0100) ? "Enable" : "Disable");
1310 * Opteron Rev E shows a bug as in very rare occasions a read memory
1311 * barrier is not performed as expected if it is followed by a
1312 * non-atomic read-modify-write instruction.
1313 * As long as that bug pops up very rarely (intensive machine usage
1314 * on other operating systems generally generates one unexplainable
1315 * crash any 2 months) and as long as a model specific fix would be
1316 * impratical at this stage, print out a warning string if the broken
1317 * model and family are identified.
1319 if (CPUID_TO_FAMILY(cpu_id) == 0xf && CPUID_TO_MODEL(cpu_id) >= 0x20 &&
1320 CPUID_TO_MODEL(cpu_id) <= 0x3f)
1321 printf("WARNING: This architecture revision has known SMP "
1322 "hardware bugs which may cause random instability\n");
1326 print_INTEL_info(void)
1329 u_int rounds, regnum;
1330 u_int nwaycode, nway;
1332 if (cpu_high >= 2) {
1335 do_cpuid(0x2, regs);
1336 if (rounds == 0 && (rounds = (regs[0] & 0xff)) == 0)
1337 break; /* we have a buggy CPU */
1339 for (regnum = 0; regnum <= 3; ++regnum) {
1340 if (regs[regnum] & (1<<31))
1343 print_INTEL_TLB(regs[regnum] & 0xff);
1344 print_INTEL_TLB((regs[regnum] >> 8) & 0xff);
1345 print_INTEL_TLB((regs[regnum] >> 16) & 0xff);
1346 print_INTEL_TLB((regs[regnum] >> 24) & 0xff);
1348 } while (--rounds > 0);
1351 if (cpu_exthigh >= 0x80000006) {
1352 do_cpuid(0x80000006, regs);
1353 nwaycode = (regs[2] >> 12) & 0x0f;
1354 if (nwaycode >= 0x02 && nwaycode <= 0x08)
1355 nway = 1 << (nwaycode / 2);
1358 printf("\nL2 cache: %u kbytes, %u-way associative, %u bytes/line",
1359 (regs[2] >> 16) & 0xffff, nway, regs[2] & 0xff);
1366 print_INTEL_TLB(u_int data)
1374 printf("\nInstruction TLB: 4 KB pages, 4-way set associative, 32 entries");
1377 printf("\nInstruction TLB: 4 MB pages, fully associative, 2 entries");
1380 printf("\nData TLB: 4 KB pages, 4-way set associative, 64 entries");
1383 printf("\nData TLB: 4 MB Pages, 4-way set associative, 8 entries");
1386 printf("\n1st-level instruction cache: 8 KB, 4-way set associative, 32 byte line size");
1389 printf("\n1st-level instruction cache: 16 KB, 4-way set associative, 32 byte line size");
1392 printf("\n1st-level data cache: 8 KB, 2-way set associative, 32 byte line size");
1395 printf("\n1st-level data cache: 16 KB, 4-way set associative, 32 byte line size");
1398 printf("\n3rd-level cache: 512 KB, 4-way set associative, sectored cache, 64 byte line size");
1401 printf("\n3rd-level cache: 1 MB, 8-way set associative, sectored cache, 64 byte line size");
1404 printf("\n3rd-level cache: 2 MB, 8-way set associative, sectored cache, 64 byte line size");
1407 printf("\n3rd-level cache: 4 MB, 8-way set associative, sectored cache, 64 byte line size");
1410 printf("\n1st-level data cache: 32 KB, 8-way set associative, 64 byte line size");
1413 printf("\n1st-level instruction cache: 32 KB, 8-way set associative, 64 byte line size");
1416 printf("\n2nd-level cache: 128 KB, 4-way set associative, sectored cache, 64 byte line size");
1419 printf("\n2nd-level cache: 128 KB, 2-way set associative, sectored cache, 64 byte line size");
1422 printf("\n2nd-level cache: 256 KB, 4-way set associative, sectored cache, 64 byte line size");
1425 printf("\n2nd-level cache: 128 KB, 4-way set associative, 32 byte line size");
1428 printf("\n2nd-level cache: 256 KB, 4-way set associative, 32 byte line size");
1431 printf("\n2nd-level cache: 512 KB, 4-way set associative, 32 byte line size");
1434 printf("\n2nd-level cache: 1 MB, 4-way set associative, 32 byte line size");
1437 printf("\n2nd-level cache: 2 MB, 4-way set associative, 32 byte line size");
1440 printf("\n3rd-level cache: 4 MB, 4-way set associative, 64 byte line size");
1443 printf("\n3rd-level cache: 8 MB, 8-way set associative, 64 byte line size");
1446 printf("\nInstruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 64 entries");
1449 printf("\nInstruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 128 entries");
1452 printf("\nInstruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 256 entries");
1455 printf("\nData TLB: 4 KB or 4 MB pages, fully associative, 64 entries");
1458 printf("\nData TLB: 4 KB or 4 MB pages, fully associative, 128 entries");
1461 printf("\nData TLB: 4 KB or 4 MB pages, fully associative, 256 entries");
1464 printf("\n1st-level data cache: 16 KB, 8-way set associative, sectored cache, 64 byte line size");
1467 printf("\n1st-level data cache: 8 KB, 4-way set associative, sectored cache, 64 byte line size");
1470 printf("\n1st-level data cache: 16 KB, 4-way set associative, sectored cache, 64 byte line size");
1473 printf("\n1st-level data cache: 32 KB, 4 way set associative, sectored cache, 64 byte line size");
1476 printf("\nTrace cache: 12K-uops, 8-way set associative");
1479 printf("\nTrace cache: 16K-uops, 8-way set associative");
1482 printf("\nTrace cache: 32K-uops, 8-way set associative");
1485 printf("\n2nd-level cache: 1 MB, 4-way set associative, 64-byte line size");
1488 printf("\n2nd-level cache: 128 KB, 8-way set associative, sectored cache, 64 byte line size");
1491 printf("\n2nd-level cache: 256 KB, 8-way set associative, sectored cache, 64 byte line size");
1494 printf("\n2nd-level cache: 512 KB, 8-way set associative, sectored cache, 64 byte line size");
1497 printf("\n2nd-level cache: 1 MB, 8-way set associative, sectored cache, 64 byte line size");
1500 printf("\n2nd-level cache: 2-MB, 8-way set associative, 64-byte line size");
1503 printf("\n2nd-level cache: 512-KB, 2-way set associative, 64-byte line size");
1506 printf("\n2nd-level cache: 256 KB, 8-way set associative, 32 byte line size");
1509 printf("\n2nd-level cache: 512 KB, 8-way set associative, 32 byte line size");
1512 printf("\n2nd-level cache: 1 MB, 8-way set associative, 32 byte line size");
1515 printf("\n2nd-level cache: 2 MB, 8-way set associative, 32 byte line size");
1518 printf("\n2nd-level cache: 512 KB, 4-way set associative, 64 byte line size");
1521 printf("\n2nd-level cache: 1 MB, 8-way set associative, 64 byte line size");
1524 printf("\nInstruction TLB: 4 KB Pages, 4-way set associative, 128 entries");
1527 printf("\nData TLB: 4 KB Pages, 4-way set associative, 128 entries");
1533 print_transmeta_info(void)
1535 u_int regs[4], nreg = 0;
1537 do_cpuid(0x80860000, regs);
1539 if (nreg >= 0x80860001) {
1540 do_cpuid(0x80860001, regs);
1541 printf(" Processor revision %u.%u.%u.%u\n",
1542 (regs[1] >> 24) & 0xff,
1543 (regs[1] >> 16) & 0xff,
1544 (regs[1] >> 8) & 0xff,
1547 if (nreg >= 0x80860002) {
1548 do_cpuid(0x80860002, regs);
1549 printf(" Code Morphing Software revision %u.%u.%u-%u-%u\n",
1550 (regs[1] >> 24) & 0xff,
1551 (regs[1] >> 16) & 0xff,
1552 (regs[1] >> 8) & 0xff,
1556 if (nreg >= 0x80860006) {
1558 do_cpuid(0x80860003, (u_int*) &info[0]);
1559 do_cpuid(0x80860004, (u_int*) &info[16]);
1560 do_cpuid(0x80860005, (u_int*) &info[32]);
1561 do_cpuid(0x80860006, (u_int*) &info[48]);
1563 printf(" %s\n", info);
1568 print_via_padlock_info(void)
1572 /* Check for supported models. */
1573 switch (cpu_id & 0xff0) {
1575 if ((cpu_id & 0xf) < 3)
1585 do_cpuid(0xc0000000, regs);
1586 if (regs[0] >= 0xc0000001)
1587 do_cpuid(0xc0000001, regs);
1591 printf("\n VIA Padlock Features=0x%b", regs[3],
1595 "\011AES-CTR" /* ACE2 */
1596 "\013SHA1,SHA256" /* PHE */