sys/ia64/ia64/exception.S

   1 /*-
   2  * Copyright (c) 2003,2004 Marcel Moolenaar
   3  * Copyright (c) 2000 Doug Rabson
   4  * All rights reserved.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions
   8  * are met:
   9  * 1. Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions and the following disclaimer.
  11  * 2. Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the distribution.
  14  *
  15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  16  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  17  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  18  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  19  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  20  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  21  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  22  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  23  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  24  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  25  * SUCH DAMAGE.
  26  */
  27
  28 #include <machine/asm.h>
  29 __FBSDID("$FreeBSD$");
  30
  31 #include "opt_xtrace.h"
  32
  33 #include <machine/pte.h>
  34 #include <assym.s>
  35
  36 /*
  37  * Nested TLB restart tokens. These are used by the
  38  * nested TLB handler for jumping back to the code
  39  * where the nested TLB was caused.
  40  */
  41 #define NTLBRT_SAVE     0x12c12c
  42 #define NTLBRT_RESTORE  0x12c12d
  43
  44 /*
  45  * ar.k7 = kernel memory stack
  46  * ar.k6 = kernel register stack
  47  * ar.k5 = EPC gateway page
  48  * ar.k4 = PCPU data
  49  */
  50
  51 #ifdef EXCEPTION_TRACING
  52
  53         .data
  54         .global xtrace, xhead
  55 xtrace: .space  1024*5*8
  56 xhead:  data8   xtrace
  57
  58 #define XTRACE(offset)                          \
  59 {       .mmi ;                                  \
  60         mov     r24=ar.itc ;                    \
  61         mov     r25=cr.iip ;                    \
  62         mov     r27=offset ;                    \
  63 } ;                                             \
  64 {       .mlx ;                                  \
  65         mov     r28=cr.ifa ;                    \
  66         movl    r29=xhead ;;                    \
  67 } ;                                             \
  68 {       .mmi ;                                  \
  69         ld8     r29=[r29] ;;                    \
  70         st8     [r29]=r24,8 ;                   \
  71         nop     0 ;;                            \
  72 } ;                                             \
  73 {       .mmi ;                                  \
  74         st8     [r29]=r27,8 ;;                  \
  75         mov     r24=cr.isr ;                    \
  76         add     r27=8,r29 ;;                    \
  77 } ;                                             \
  78 {       .mmi ;                                  \
  79         st8     [r29]=r25,16 ;;                 \
  80         st8     [r27]=r28,16 ;                  \
  81         mov     r25=pr ;;                       \
  82 } ;                                             \
  83 {       .mlx ;                                  \
  84         st8     [r29]=r24 ;                     \
  85         movl    r28=xhead ;;                    \
  86 } ;                                             \
  87 {       .mii ;                                  \
  88         cmp.eq  p15,p0=r27,r28 ;                \
  89         addl    r29=1024*5*8,r0 ;;              \
  90 (p15)   sub     r27=r28,r29 ;;                  \
  91 } ;                                             \
  92 {       .mmi ;                                  \
  93         st8     [r28]=r27 ;                     \
  94         nop     0 ;                             \
  95         mov     pr=r25,0x1ffff ;;               \
  96 }
  97
  98 #else
  99
 100 #define XTRACE(offset)
 101
 102 #endif
 103
 104         .text
 105
 106 /*
 107  * exception_save: save interrupted state
 108  *
 109  * Arguments:
 110  *      r16     address of bundle that contains the branch. The
 111  *              return address will be the next bundle.
 112  *      r17     the value to save as ifa in the trapframe. This
 113  *              normally is cr.ifa, but some interruptions set
 114  *              set cr.iim and not cr.ifa.
 115  *
 116  * Returns:
 117  *      p15     interrupted from user stack
 118  *      p14     interrupted from kernel stack
 119  *      p13     interrupted from user backing store
 120  *      p12     interrupted from kernel backing store
 121  *      p11     interrupts were enabled
 122  *      p10     interrupts were disabled
 123  */
 124 ENTRY_NOPROFILE(exception_save, 0)
 125 {       .mii
 126         mov             r20=ar.unat
 127         extr.u          r31=sp,61,3
 128         mov             r18=pr
 129         ;;
 130 }
 131 {       .mmi
 132         cmp.le          p14,p15=5,r31
 133         ;;
 134 (p15)   mov             r23=ar.k7               // kernel memory stack
 135 (p14)   mov             r23=sp
 136         ;;
 137 }
 138 {       .mii
 139         mov             r21=ar.rsc
 140         add             r30=-SIZEOF_TRAPFRAME,r23
 141         ;;
 142         dep             r30=0,r30,0,10
 143         ;;
 144 }
 145 {       .mmi
 146         mov             ar.rsc=0
 147         sub             r19=r23,r30
 148         add             r31=8,r30
 149         ;;
 150 }
 151 {       .mmi
 152         mov             r22=cr.iip
 153         nop             0
 154         addl            r29=NTLBRT_SAVE,r0      // 22-bit restart token.
 155         ;;
 156 }
 157
 158         /*
 159          * We have a 1KB aligned trapframe, pointed to by sp. If we write
 160          * to the trapframe, we may trigger a data nested TLB fault. By
 161          * aligning the trapframe on a 1KB boundary, we guarantee that if
 162          * we get a data nested TLB fault, it will be on the very first
 163          * write. Since the data nested TLB fault does not preserve any
 164          * state, we have to be careful what we clobber. Consequently, we
 165          * have to be careful what we use here. Below a list of registers
 166          * that are currently alive:
 167          *      r16,r17=arguments
 168          *      r18=pr, r19=length, r20=unat, r21=rsc, r22=iip, r23=TOS
 169          *      r29=restart point
 170          *      r30,r31=trapframe pointers
 171          *      p14,p15=memory stack switch
 172          */
 173 exception_save_restart:
 174 {       .mmi
 175         st8             [r30]=r19,16            // length
 176         st8             [r31]=r0,16             // flags
 177         add             r19=16,r19
 178         ;;
 179 }
 180 {       .mmi
 181         st8.spill       [r30]=sp,16             // sp
 182         st8             [r31]=r20,16            // unat
 183         sub             sp=r23,r19
 184         ;;
 185 }
 186 {       .mmi
 187         mov             r19=ar.rnat
 188         mov             r20=ar.bspstore
 189         mov             r23=rp
 190         ;;
 191 }
 192         // r18=pr, r19=rnat, r20=bspstore, r21=rsc, r22=iip, r23=rp
 193 {       .mmi
 194         st8             [r30]=r23,16            // rp
 195         st8             [r31]=r18,16            // pr
 196         mov             r24=ar.pfs
 197         ;;
 198 }
 199 {       .mmb
 200         st8             [r30]=r24,16            // pfs
 201         st8             [r31]=r20,16            // bspstore
 202         cover
 203         ;;
 204 }
 205 {       .mmi
 206         mov             r18=ar.fpsr
 207         mov             r23=cr.ipsr
 208         extr.u          r24=r20,61,3
 209         ;;
 210 }
 211         // r18=fpsr, r19=rnat, r20=bspstore, r21=rsc, r22=iip, r23=ipsr
 212 {       .mmi
 213         st8             [r30]=r19,16            // rnat
 214         st8             [r31]=r0,16             // __spare
 215         cmp.le          p12,p13=5,r24
 216         ;;
 217 }
 218 {       .mmi
 219         st8.spill       [r30]=r13,16            // tp
 220         st8             [r31]=r21,16            // rsc
 221         tbit.nz         p11,p10=r23,14          // p11=interrupts enabled
 222         ;;
 223 }
 224 {       .mmi
 225 (p13)   mov             r21=ar.k6               // kernel register stack
 226         ;;
 227         st8             [r30]=r18,16            // fpsr
 228 (p13)   dep             r20=r20,r21,0,9         // align dirty registers
 229         ;;
 230 }
 231         // r19=rnat, r20=bspstore, r22=iip, r23=ipsr
 232 {       .mmi
 233         st8             [r31]=r23,16            // psr
 234 (p13)   mov             ar.bspstore=r20
 235         nop             0
 236         ;;
 237 }
 238 {       .mmi
 239 (p13)   mov             ar.rnat=r19
 240         mov             r18=ar.bsp
 241         nop             0
 242         ;;
 243 }
 244 {       .mmi
 245         mov             r19=cr.ifs
 246         st8.spill       [r30]=gp,16             // gp
 247         sub             r18=r18,r20
 248         ;;
 249 }
 250         // r19=ifs, r22=iip
 251 {       .mmi
 252         st8             [r31]=r18,16            // ndirty
 253         st8             [r30]=r19,16            // cfm
 254         nop             0
 255         ;;
 256 }
 257 {       .mmi
 258         mov             r18=cr.isr
 259         st8             [r31]=r22,16            // iip
 260         add             r29=16,r30
 261         ;;
 262 }
 263 {       .mmi
 264         st8             [r30]=r17,24            // ifa
 265         st8             [r31]=r18,24            // isr
 266         nop             0
 267         ;;
 268 }
 269 {       .mmi
 270         .mem.offset     0,0
 271         st8.spill       [r30]=r2,16             // r2
 272         .mem.offset     8,0
 273         st8.spill       [r31]=r3,16             // r3
 274         add             r2=9*8,r29
 275         ;;
 276 }
 277 {       .mmi
 278         .mem.offset     0,0
 279         st8.spill       [r30]=r8,16             // r8
 280         .mem.offset     8,0
 281         st8.spill       [r31]=r9,16             // r9
 282         add             r3=8,r2
 283         ;;
 284 }
 285 {       .mmi
 286         .mem.offset     0,0
 287         st8.spill       [r30]=r10,16            // r10
 288         .mem.offset     8,0
 289         st8.spill       [r31]=r11,16            // r11
 290         add             r8=16,r16
 291         ;;
 292 }
 293 {       .mmi
 294         .mem.offset     0,0
 295         st8.spill       [r30]=r14               // r14
 296         .mem.offset     8,0
 297         st8.spill       [r31]=r15               // r15
 298         mov             r9=r29
 299 }
 300 {       .mmb
 301         mov             r10=ar.csd
 302         mov             r11=ar.ssd
 303         bsw.1
 304         ;;
 305 }
 306 {       .mmi
 307         .mem.offset     0,0
 308         st8.spill       [r2]=r16,16             // r16
 309         .mem.offset     8,0
 310         st8.spill       [r3]=r17,16             // r17
 311         mov             r14=b6
 312         ;;
 313 }
 314 {       .mmi
 315         .mem.offset     0,0
 316         st8.spill       [r2]=r18,16             // r18
 317         .mem.offset     8,0
 318         st8.spill       [r3]=r19,16             // r19
 319         mov             r15=b7
 320         ;;
 321 }
 322 {       .mmi
 323         .mem.offset     0,0
 324         st8.spill       [r2]=r20,16             // r20
 325         .mem.offset     8,0
 326         st8.spill       [r3]=r21,16             // r21
 327         mov             b7=r8
 328         ;;
 329 }
 330 {       .mmi
 331         .mem.offset     0,0
 332         st8.spill       [r2]=r22,16             // r22
 333         .mem.offset     8,0
 334         st8.spill       [r3]=r23,16             // r23
 335         ;;
 336 }
 337
 338         .mem.offset     0,0
 339         st8.spill       [r2]=r24,16             // r24
 340         .mem.offset     8,0
 341         st8.spill       [r3]=r25,16             // r25
 342         ;;
 343         .mem.offset     0,0
 344         st8.spill       [r2]=r26,16             // r26
 345         .mem.offset     8,0
 346         st8.spill       [r3]=r27,16             // r27
 347         ;;
 348         .mem.offset     0,0
 349         st8.spill       [r2]=r28,16             // r28
 350         .mem.offset     8,0
 351         st8.spill       [r3]=r29,16             // r29
 352         ;;
 353         .mem.offset     0,0
 354         st8.spill       [r2]=r30,16             // r30
 355         .mem.offset     8,0
 356         st8.spill       [r3]=r31,16             // r31
 357         ;;
 358
 359 {       .mmi
 360         st8             [r2]=r14,16             // b6
 361         mov             r17=ar.unat
 362         nop             0
 363         ;;
 364 }
 365 {       .mmi
 366         st8             [r3]=r15,16             // b7
 367         mov             r16=ar.ccv
 368         nop             0
 369         ;;
 370 }
 371 {       .mmi
 372         st8             [r2]=r16,16             // ccv
 373         st8             [r3]=r10,16             // csd
 374         nop             0
 375         ;;
 376 }
 377 {       .mmi
 378         st8             [r2]=r11,24             // ssd
 379         st8             [r9]=r17
 380         nop             0
 381         ;;
 382 }
 383
 384         stf.spill       [r3]=f6,32              // f6
 385         stf.spill       [r2]=f7,32              // f7
 386         ;;
 387         stf.spill       [r3]=f8,32              // f8
 388         stf.spill       [r2]=f9,32              // f9
 389         ;;
 390         stf.spill       [r3]=f10,32             // f10
 391         stf.spill       [r2]=f11,32             // f11
 392         ;;
 393         stf.spill       [r3]=f12,32             // f12
 394         stf.spill       [r2]=f13,32             // f13
 395         ;;
 396         stf.spill       [r3]=f14                // f14
 397         stf.spill       [r2]=f15                // f15
 398         ;;
 399 {       .mmi
 400         mov             ar.rsc=3
 401         mov             r13=ar.k4
 402         nop             0
 403         ;;
 404 }
 405 {       .mlx
 406         ssm             psr.ic|psr.dfh
 407         movl            gp=__gp
 408         ;;
 409 }
 410 {       .mib
 411         srlz.d
 412         nop             0
 413         br.sptk         b7
 414         ;;
 415 }
 416 END(exception_save)
 417
 418 /*
 419  * exception_restore:   restore interrupted state
 420  *
 421  * Arguments:
 422  *      sp+16   trapframe pointer
 423  */
 424 ENTRY_NOPROFILE(exception_restore, 0)
 425 {       .mmi
 426         rsm             psr.i
 427         add             r3=SIZEOF_TRAPFRAME-16,sp
 428         add             r2=SIZEOF_TRAPFRAME,sp
 429         ;;
 430 }
 431 {       .mmi
 432         srlz.d
 433         add             r8=SIZEOF_SPECIAL+32,sp
 434         nop             0
 435         ;;
 436 }
 437         // The next load can trap. Let it be...
 438         ldf.fill        f15=[r2],-32            // f15
 439         ldf.fill        f14=[r3],-32            // f14
 440         add             sp=16,sp
 441         ;;
 442         ldf.fill        f13=[r2],-32            // f13
 443         ldf.fill        f12=[r3],-32            // f12
 444         ;;
 445         ldf.fill        f11=[r2],-32            // f11
 446         ldf.fill        f10=[r3],-32            // f10
 447         ;;
 448         ldf.fill        f9=[r2],-32             // f9
 449         ldf.fill        f8=[r3],-32             // f8
 450         ;;
 451         ldf.fill        f7=[r2],-24             // f7
 452         ldf.fill        f6=[r3],-16             // f6
 453         ;;
 454
 455 {       .mmi
 456         ld8             r8=[r8]                 // unat (after)
 457         ;;
 458         mov             ar.unat=r8
 459         nop             0
 460         ;;
 461 }
 462
 463         ld8             r10=[r2],-16            // ssd
 464         ld8             r11=[r3],-16            // csd
 465         ;;
 466         mov             ar.ssd=r10
 467         mov             ar.csd=r11
 468
 469         ld8             r14=[r2],-16            // ccv
 470         ld8             r15=[r3],-16            // b7
 471         ;;
 472
 473 {       .mmi
 474         mov             ar.ccv=r14
 475         ld8             r8=[r2],-16             // b6
 476         mov             b7=r15
 477         ;;
 478 }
 479 {       .mmi
 480         ld8.fill        r31=[r3],-16            // r31
 481         ld8.fill        r30=[r2],-16            // r30
 482         mov             b6=r8
 483         ;;
 484 }
 485
 486         ld8.fill        r29=[r3],-16            // r29
 487         ld8.fill        r28=[r2],-16            // r28
 488         ;;
 489         ld8.fill        r27=[r3],-16            // r27
 490         ld8.fill        r26=[r2],-16            // r26
 491         ;;
 492         ld8.fill        r25=[r3],-16            // r25
 493         ld8.fill        r24=[r2],-16            // r24
 494         ;;
 495         ld8.fill        r23=[r3],-16            // r23
 496         ld8.fill        r22=[r2],-16            // r22
 497         ;;
 498         ld8.fill        r21=[r3],-16            // r21
 499         ld8.fill        r20=[r2],-16            // r20
 500         ;;
 501         ld8.fill        r19=[r3],-16            // r19
 502         ld8.fill        r18=[r2],-16            // r18
 503         ;;
 504
 505 {       .mmb
 506         ld8.fill        r17=[r3],-16            // r17
 507         ld8.fill        r16=[r2],-16            // r16
 508         bsw.0
 509         ;;
 510 }
 511 {       .mmi
 512         ld8.fill        r15=[r3],-16            // r15
 513         ld8.fill        r14=[r2],-16            // r14
 514         add             r31=16,sp
 515         ;;
 516 }
 517 {       .mmi
 518         ld8             r16=[sp]                // tf_length
 519         ld8.fill        r11=[r3],-16            // r11
 520         add             r30=24,sp
 521         ;;
 522 }
 523 {       .mmi
 524         ld8.fill        r10=[r2],-16            // r10
 525         ld8.fill        r9=[r3],-16             // r9
 526         add             r16=r16,sp              // ar.k7
 527         ;;
 528 }
 529 {       .mmi
 530         ld8.fill        r8=[r2],-16             // r8
 531         ld8.fill        r3=[r3]                 // r3
 532         ;;
 533 }
 534         // We want nested TLB faults from here on...
 535         rsm             psr.ic|psr.i
 536         ld8.fill        r2=[r2]                 // r2
 537         nop             0
 538         ;;
 539         srlz.d
 540         ld8.fill        sp=[r31],16             // sp
 541         nop             0
 542         ;;
 543
 544         ld8             r17=[r30],16            // unat
 545         ld8             r29=[r31],16            // rp
 546         ;;
 547         ld8             r18=[r30],16            // pr
 548         ld8             r28=[r31],16            // pfs
 549         mov             rp=r29
 550         ;;
 551         ld8             r20=[r30],24            // bspstore
 552         ld8             r21=[r31],24            // rnat
 553         mov             ar.pfs=r28
 554         ;;
 555         ld8.fill        r26=[r30],16            // tp
 556         ld8             r22=[r31],16            // rsc
 557         ;;
 558 {       .mmi
 559         ld8             r23=[r30],16            // fpsr
 560         ld8             r24=[r31],16            // psr
 561         extr.u          r28=r20,61,3
 562         ;;
 563 }
 564 {       .mmi
 565         ld8.fill        r1=[r30],16             // gp
 566         ld8             r27=[r31],16            // ndirty
 567         cmp.le          p14,p15=5,r28
 568         ;;
 569 }
 570 {       .mmi
 571         ld8             r25=[r30]               // cfm
 572         ld8             r19=[r31]               // ip
 573         nop             0
 574         ;;
 575 }
 576 {       .mii
 577         // Switch register stack
 578         alloc           r30=ar.pfs,0,0,0,0      // discard current frame
 579         shl             r31=r27,16              // value for ar.rsc
 580 (p15)   mov             r13=r26
 581         ;;
 582 }
 583         // The loadrs can fault if the backing store is not currently
 584         // mapped. We assured forward progress by getting everything we
 585         // need from the trapframe so that we don't care if the CPU
 586         // purges that translation when it needs to insert a new one for
 587         // the backing store.
 588 {       .mmi
 589         mov             ar.rsc=r31              // setup for loadrs
 590         mov             ar.k7=r16
 591         addl            r29=NTLBRT_RESTORE,r0   // 22-bit restart token
 592         ;;
 593 }
 594 exception_restore_restart:
 595 {       .mmi
 596         mov             r30=ar.bspstore
 597         ;;
 598         loadrs                                  // load user regs
 599         nop             0
 600         ;;
 601 }
 602 {       .mmi
 603         mov             r31=ar.bspstore
 604         ;;
 605         mov             ar.bspstore=r20
 606         dep             r31=0,r31,0,13          // 8KB aligned
 607         ;;
 608 }
 609 {       .mmi
 610         mov             ar.k6=r31
 611         mov             ar.rnat=r21
 612         nop             0
 613         ;;
 614 }
 615 {       .mmi
 616         mov             ar.unat=r17
 617         mov             cr.iip=r19
 618         nop             0
 619 }
 620 {       .mmi
 621         mov             cr.ipsr=r24
 622         mov             cr.ifs=r25
 623         mov             pr=r18,0x1ffff
 624         ;;
 625 }
 626 {       .mmb
 627         mov             ar.rsc=r22
 628         mov             ar.fpsr=r23
 629         rfi
 630         ;;
 631 }
 632 END(exception_restore)
 633
 634 /*
 635  * Call exception_save_regs to preserve the interrupted state in a
 636  * trapframe. Note that we don't use a call instruction because we
 637  * must be careful not to lose track of the RSE state. We then call
 638  * trap() with the value of _n_ as an argument to handle the
 639  * exception. We arrange for trap() to return to exception_restore
 640  * which will restore the interrupted state before executing an rfi to
 641  * resume it.
 642  */
 643 #define CALL(_func_, _n_, _ifa_)                \
 644 {       .mib ;                                  \
 645         mov             r17=_ifa_ ;             \
 646         mov             r16=ip ;                \
 647         br.sptk         exception_save ;;       \
 648 } ;                                             \
 649 {       .mmi ;                                  \
 650         alloc           r15=ar.pfs,0,0,2,0 ;;   \
 651 (p11)   ssm             psr.i ;                 \
 652         mov             out0=_n_ ;;             \
 653 } ;                                             \
 654 {       .mib ;                                  \
 655 (p11)   srlz.d ;                                \
 656         add             out1=16,sp ;            \
 657         br.call.sptk    rp=_func_ ;;            \
 658 } ;                                             \
 659 {       .mib ;                                  \
 660         nop             0 ;                     \
 661         nop             0 ;                     \
 662         br.sptk         exception_restore ;;    \
 663 }
 664
 665 #define IVT_ENTRY(name, offset)                 \
 666         .org    ia64_vector_table + offset;     \
 667         .global ivt_##name;                     \
 668         .proc   ivt_##name;                     \
 669         .prologue;                              \
 670         .unwabi @svr4, 'I';                     \
 671         .save   rp, r0;                         \
 672         .body;                                  \
 673 ivt_##name:                                     \
 674         XTRACE(offset)
 675
 676 #define IVT_END(name)                           \
 677         .endp   ivt_##name
 678
 679 #ifdef COMPAT_FREEBSD32
 680 #define IA32_TRAP       ia32_trap
 681 #else
 682 #define IA32_TRAP       trap
 683 #endif
 684
 685 /*
 686  * The IA64 Interrupt Vector Table (IVT) contains 20 slots with 64
 687  * bundles per vector and 48 slots with 16 bundles per vector.
 688  */
 689
 690         .section .text.ivt,"ax"
 691
 692         .align  32768
 693         .global ia64_vector_table
 694         .size   ia64_vector_table, 32768
 695 ia64_vector_table:
 696
 697 IVT_ENTRY(VHPT_Translation, 0x0000)
 698         CALL(trap, 0, cr.ifa)
 699 IVT_END(VHPT_Translation)
 700
 701 IVT_ENTRY(Instruction_TLB, 0x0400)
 702         mov     r16=cr.ifa
 703         mov     r17=pr
 704         ;;
 705         thash   r18=r16
 706         ttag    r19=r16
 707         ;;
 708         add     r21=16,r18              // tag
 709         add     r20=24,r18              // collision chain
 710         ;;
 711         ld8     r21=[r21]               // check VHPT tag
 712         ld8     r20=[r20]               // bucket head
 713         ;;
 714         cmp.ne  p15,p0=r21,r19
 715 (p15)   br.dpnt.few 1f
 716         ;;
 717         ld8     r21=[r18]               // read pte
 718         ;;
 719         itc.i   r21                     // insert pte
 720         mov     pr=r17,0x1ffff
 721         ;;
 722         rfi                             // done
 723         ;;
 724 1:      rsm     psr.dt                  // turn off data translations
 725         dep     r20=0,r20,61,3          // convert vhpt ptr to physical
 726         ;;
 727         srlz.d                          // serialize
 728         ld8     r20=[r20]               // first entry
 729         ;;
 730 2:      cmp.eq  p15,p0=r0,r20           // done?
 731 (p15)   br.cond.spnt.few 9f             // bail if done
 732         ;;
 733         add     r21=16,r20              // tag location
 734         ;;
 735         ld8     r21=[r21]               // read tag
 736         ;;
 737         cmp.ne  p15,p0=r21,r19          // compare tags
 738 (p15)   br.cond.sptk.few 3f             // if not, read next in chain
 739         ;;
 740         ld8     r21=[r20]               // read pte
 741         mov     r22=PTE_ACCESSED
 742         ;;
 743         or      r21=r21,r22
 744         ;;
 745         st8     [r20]=r21,8
 746         ;;
 747         ld8     r22=[r20]               // read rest of pte
 748         ;;
 749         dep     r18=0,r18,61,3          // convert vhpt ptr to physical
 750         ;;
 751         add     r20=16,r18              // address of tag
 752         ;;
 753         ld8.acq r23=[r20]               // read old tag
 754         ;;
 755         dep     r23=-1,r23,63,1         // set ti bit
 756         ;;
 757         st8.rel [r20]=r23               // store old tag + ti
 758         ;;
 759         mf                              // make sure everyone sees
 760         ;;
 761         st8     [r18]=r21,8             // store pte
 762         ;;
 763         st8     [r18]=r22,8
 764         ;;
 765         st8.rel [r18]=r19               // store new tag
 766         ;;
 767         itc.i   r21                     // and place in TLB
 768         ssm     psr.dt
 769         ;;
 770         srlz.d
 771         mov     pr=r17,0x1ffff          // restore predicates
 772         rfi
 773         ;;
 774 3:      add     r20=24,r20              // next in chain
 775         ;;
 776         ld8     r20=[r20]               // read chain
 777         br.cond.sptk.few 2b             // loop
 778         ;;
 779 9:      ssm     psr.dt
 780         mov     pr=r17,0x1ffff          // restore predicates
 781         ;;
 782         srlz.d
 783         ;;
 784         CALL(trap, 20, cr.ifa)          // Page Not Present trap
 785 IVT_END(Instruction_TLB)
 786
 787 IVT_ENTRY(Data_TLB, 0x0800)
 788         mov     r16=cr.ifa
 789         mov     r17=pr
 790         ;;
 791         thash   r18=r16
 792         ttag    r19=r16
 793         ;;
 794         add     r21=16,r18              // tag
 795         add     r20=24,r18              // collision chain
 796         ;;
 797         ld8     r21=[r21]               // check VHPT tag
 798         ld8     r20=[r20]               // bucket head
 799         ;;
 800         cmp.ne  p15,p0=r21,r19
 801 (p15)   br.dpnt.few 1f
 802         ;;
 803         ld8     r21=[r18]               // read pte
 804         ;;
 805         itc.d   r21                     // insert pte
 806         mov     pr=r17,0x1ffff
 807         ;;
 808         rfi                             // done
 809         ;;
 810 1:      rsm     psr.dt                  // turn off data translations
 811         dep     r20=0,r20,61,3          // convert vhpt ptr to physical
 812         ;;
 813         srlz.d                          // serialize
 814         ld8     r20=[r20]               // first entry
 815         ;;
 816 2:      cmp.eq  p15,p0=r0,r20           // done?
 817 (p15)   br.cond.spnt.few 9f             // bail if done
 818         ;;
 819         add     r21=16,r20              // tag location
 820         ;;
 821         ld8     r21=[r21]               // read tag
 822         ;;
 823         cmp.ne  p15,p0=r21,r19          // compare tags
 824 (p15)   br.cond.sptk.few 3f             // if not, read next in chain
 825         ;;
 826         ld8     r21=[r20]               // read pte
 827         mov     r22=PTE_ACCESSED
 828         ;;
 829         or      r21=r21,r22
 830         ;;
 831         st8     [r20]=r21,8
 832         ;;
 833         ld8     r22=[r20]               // read rest of pte
 834         ;;
 835         dep     r18=0,r18,61,3          // convert vhpt ptr to physical
 836         ;;
 837         add     r20=16,r18              // address of tag
 838         ;;
 839         ld8.acq r23=[r20]               // read old tag
 840         ;;
 841         dep     r23=-1,r23,63,1         // set ti bit
 842         ;;
 843         st8.rel [r20]=r23               // store old tag + ti
 844         ;;
 845         mf                              // make sure everyone sees
 846         ;;
 847         st8     [r18]=r21,8             // store pte
 848         ;;
 849         st8     [r18]=r22,8
 850         ;;
 851         st8.rel [r18]=r19               // store new tag
 852         ;;
 853         itc.d   r21                     // and place in TLB
 854         ssm     psr.dt
 855         ;;
 856         srlz.d
 857         mov     pr=r17,0x1ffff          // restore predicates
 858         rfi
 859         ;;
 860 3:      add     r20=24,r20              // next in chain
 861         ;;
 862         ld8     r20=[r20]               // read chain
 863         br.cond.sptk.few 2b             // loop
 864         ;;
 865 9:      ssm     psr.dt
 866         mov     pr=r17,0x1ffff          // restore predicates
 867         ;;
 868         srlz.d
 869         ;;
 870         CALL(trap, 20, cr.ifa)          // Page Not Present trap
 871 IVT_END(Data_TLB)
 872
 873 IVT_ENTRY(Alternate_Instruction_TLB, 0x0c00)
 874         mov     r16=cr.ifa              // where did it happen
 875         mov     r18=pr                  // save predicates
 876         ;;
 877         extr.u  r17=r16,61,3            // get region number
 878         ;;
 879         cmp.ge  p13,p0=5,r17            // RR0-RR5?
 880         cmp.eq  p15,p14=7,r17           // RR7->p15, RR6->p14
 881 (p13)   br.spnt 9f
 882         ;;
 883 (p15)   movl    r17=PTE_PRESENT+PTE_MA_WB+PTE_ACCESSED+PTE_DIRTY+PTE_PL_KERN+ \
 884                         PTE_AR_RX+PTE_ED
 885 (p14)   movl    r17=PTE_PRESENT+PTE_MA_UC+PTE_ACCESSED+PTE_DIRTY+PTE_PL_KERN+ \
 886                         PTE_AR_RX
 887         ;;
 888         dep     r16=0,r16,50,14         // clear bits above PPN
 889         ;;
 890         dep     r16=r17,r16,0,12        // put pte bits in 0..11
 891         ;;
 892         itc.i   r16
 893         mov     pr=r18,0x1ffff          // restore predicates
 894         ;;
 895         rfi
 896         ;;
 897 9:      mov     pr=r18,0x1ffff          // restore predicates
 898         CALL(trap, 3, cr.ifa)
 899 IVT_END(Alternate_Instruction_TLB)
 900
 901 IVT_ENTRY(Alternate_Data_TLB, 0x1000)
 902         mov     r16=cr.ifa              // where did it happen
 903         mov     r18=pr                  // save predicates
 904         ;;
 905         extr.u  r17=r16,61,3            // get region number
 906         ;;
 907         cmp.ge  p13,p0=5,r17            // RR0-RR5?
 908         cmp.eq  p15,p14=7,r17           // RR7->p15, RR6->p14
 909 (p13)   br.spnt 9f
 910         ;;
 911 (p15)   movl    r17=PTE_PRESENT+PTE_MA_WB+PTE_ACCESSED+PTE_DIRTY+PTE_PL_KERN+ \
 912                         PTE_AR_RW+PTE_ED
 913 (p14)   movl    r17=PTE_PRESENT+PTE_MA_UC+PTE_ACCESSED+PTE_DIRTY+PTE_PL_KERN+ \
 914                         PTE_AR_RW
 915         ;;
 916         dep     r16=0,r16,50,14         // clear bits above PPN
 917         ;;
 918         dep     r16=r17,r16,0,12        // put pte bits in 0..11
 919         ;;
 920         itc.d   r16
 921         mov     pr=r18,0x1ffff          // restore predicates
 922         ;;
 923         rfi
 924         ;;
 925 9:      mov     pr=r18,0x1ffff          // restore predicates
 926         CALL(trap, 4, cr.ifa)
 927 IVT_END(Alternate_Data_TLB)
 928
 929 IVT_ENTRY(Data_Nested_TLB, 0x1400)
 930         // See exception_save_restart and exception_restore_restart for the
 931         // contexts that may cause a data nested TLB. We can only use the
 932         // banked general registers and predicates, but don't use:
 933         //      p14 & p15       -       Set in exception save
 934         //      r16 & r17       -       Arguments to exception save
 935         //      r30             -       Faulting address (modulo page size)
 936         // We assume r30 has the virtual addresses that relate to the data
 937         // nested TLB fault. The address does not have to be exact, as long
 938         // as it's in the same page. We use physical addressing to avoid
 939         // double nested faults. Since all virtual addresses we encounter
 940         // here are direct mapped region 7 addresses, we have no problem
 941         // constructing physical addresses.
 942 {       .mlx
 943         rsm             psr.dt
 944         movl            r27=ia64_kptdir
 945         ;;
 946 }
 947 {       .mii
 948         srlz.d
 949         dep             r27=0,r27,61,3
 950         ;;
 951         extr.u          r28=r30,3*PAGE_SHIFT-8, PAGE_SHIFT-3    // dir L0 index
 952 }
 953 {       .mii
 954         ld8             r27=[r27]                               // dir L0 page
 955         extr.u          r26=r30,2*PAGE_SHIFT-5, PAGE_SHIFT-3    // dir L1 index
 956         ;;
 957         dep             r27=0,r27,61,3
 958         ;;
 959 }
 960 {       .mmi
 961         shladd          r27=r28,3,r27
 962         ;;
 963         ld8             r27=[r27]                               // dir L1 page
 964         extr.u          r28=r30,PAGE_SHIFT,PAGE_SHIFT-5         // pte index
 965         ;;
 966 }
 967 {       .mmi
 968         shladd          r27=r26,3,r27
 969         ;;
 970         mov             r26=rr[r30]
 971         dep             r27=0,r27,61,3
 972         ;;
 973 }
 974 {       .mii
 975         ld8             r27=[r27]                               // pte page
 976         shl             r28=r28,5
 977         dep             r26=0,r26,0,2
 978         ;;
 979 }
 980 {       .mmi
 981         add             r27=r28,r27
 982         ;;
 983         mov             cr.ifa=r30
 984         dep             r27=0,r27,61,3
 985         ;;
 986 }
 987 {       .mmi
 988         ld8             r28=[r27]               // pte
 989         ;;
 990         mov             cr.itir=r26
 991         or              r28=PTE_DIRTY+PTE_ACCESSED,r28
 992         ;;
 993 }
 994 {       .mmi
 995         st8             [r27]=r28
 996         ;;
 997         addl            r26=NTLBRT_SAVE,r0
 998         addl            r27=NTLBRT_RESTORE,r0
 999 }
1000 {       .mmi
1001         itc.d           r28
1002         ;;
1003         ssm             psr.dt
1004         cmp.eq          p12,p0=r29,r26
1005         ;;
1006 }
1007 {       .mib
1008         srlz.d
1009         cmp.eq          p13,p0=r29,r27
1010 (p12)   br.sptk         exception_save_restart
1011         ;;
1012 }
1013 {       .mib
1014         nop             0
1015         nop             0
1016 (p13)   br.sptk         exception_restore_restart
1017         ;;
1018 }
1019 {       .mlx
1020         mov             r26=ar.bsp
1021         movl            r27=kstack
1022         ;;
1023 }
1024 {       .mmi
1025         mov             r28=sp
1026         nop             0
1027         addl            r27=KSTACK_PAGES*PAGE_SIZE-16,r0
1028         ;;
1029 }
1030 {       .mmi
1031         mov             sp=r27
1032         ;;
1033         mov             r27=ar.bspstore
1034         nop             0
1035         ;;
1036 }
1037         CALL(trap, 5, r30)
1038 IVT_END(Data_Nested_TLB)
1039
1040 IVT_ENTRY(Instruction_Key_Miss, 0x1800)
1041         CALL(trap, 6, cr.ifa)
1042 IVT_END(Instruction_Key_Miss)
1043
1044 IVT_ENTRY(Data_Key_Miss, 0x1c00)
1045         CALL(trap, 7, cr.ifa)
1046 IVT_END(Data_Key_Miss)
1047
1048 IVT_ENTRY(Dirty_Bit, 0x2000)
1049         mov     r16=cr.ifa
1050         mov     r17=pr
1051         ;;
1052         thash   r18=r16
1053         ;;
1054         ttag    r19=r16
1055         add     r20=24,r18              // collision chain
1056         ;;
1057         ld8     r20=[r20]               // bucket head
1058         ;;
1059         rsm     psr.dt                  // turn off data translations
1060         dep     r20=0,r20,61,3          // convert vhpt ptr to physical
1061         ;;
1062         srlz.d                          // serialize
1063         ld8     r20=[r20]               // first entry
1064         ;;
1065 1:      cmp.eq  p15,p0=r0,r20           // done?
1066 (p15)   br.cond.spnt.few 9f             // bail if done
1067         ;;
1068         add     r21=16,r20              // tag location
1069         ;;
1070         ld8     r21=[r21]               // read tag
1071         ;;
1072         cmp.ne  p15,p0=r21,r19          // compare tags
1073 (p15)   br.cond.sptk.few 2f             // if not, read next in chain
1074         ;;
1075         ld8     r21=[r20]               // read pte
1076         mov     r22=PTE_DIRTY+PTE_ACCESSED
1077         ;;
1078         or      r21=r22,r21             // set dirty & access bit
1079         ;;
1080         st8     [r20]=r21,8             // store back
1081         ;;
1082         ld8     r22=[r20]               // read rest of pte
1083         ;;
1084         dep     r18=0,r18,61,3          // convert vhpt ptr to physical
1085         ;;
1086         add     r20=16,r18              // address of tag
1087         ;;
1088         ld8.acq r23=[r20]               // read old tag
1089         ;;
1090         dep     r23=-1,r23,63,1         // set ti bit
1091         ;;
1092         st8.rel [r20]=r23               // store old tag + ti
1093         ;;
1094         mf                              // make sure everyone sees
1095         ;;
1096         st8     [r18]=r21,8             // store pte
1097         ;;
1098         st8     [r18]=r22,8
1099         ;;
1100         st8.rel [r18]=r19               // store new tag
1101         ;;
1102         itc.d   r21                     // and place in TLB
1103         ssm     psr.dt
1104         ;;
1105         srlz.d
1106         mov     pr=r17,0x1ffff          // restore predicates
1107         rfi
1108         ;;
1109 2:      add     r20=24,r20              // next in chain
1110         ;;
1111         ld8     r20=[r20]               // read chain
1112         br.cond.sptk.few 1b             // loop
1113         ;;
1114 9:      ssm     psr.dt
1115         mov     pr=r17,0x1ffff          // restore predicates
1116         ;;
1117         srlz.d
1118         ;;
1119         CALL(trap, 8, cr.ifa)                   // die horribly
1120 IVT_END(Dirty_Bit)
1121
1122 IVT_ENTRY(Instruction_Access_Bit, 0x2400)
1123         mov     r16=cr.ifa
1124         mov     r17=pr
1125         ;;
1126         thash   r18=r16
1127         ;;
1128         ttag    r19=r16
1129         add     r20=24,r18              // collision chain
1130         ;;
1131         ld8     r20=[r20]               // bucket head
1132         ;;
1133         rsm     psr.dt                  // turn off data translations
1134         dep     r20=0,r20,61,3          // convert vhpt ptr to physical
1135         ;;
1136         srlz.d                          // serialize
1137         ld8     r20=[r20]               // first entry
1138         ;;
1139 1:      cmp.eq  p15,p0=r0,r20           // done?
1140 (p15)   br.cond.spnt.few 9f             // bail if done
1141         ;;
1142         add     r21=16,r20              // tag location
1143         ;;
1144         ld8     r21=[r21]               // read tag
1145         ;;
1146         cmp.ne  p15,p0=r21,r19          // compare tags
1147 (p15)   br.cond.sptk.few 2f             // if not, read next in chain
1148         ;;
1149         ld8     r21=[r20]               // read pte
1150         mov     r22=PTE_ACCESSED
1151         ;;
1152         or      r21=r22,r21             // set accessed bit
1153         ;;
1154         st8     [r20]=r21,8             // store back
1155         ;;
1156         ld8     r22=[r20]               // read rest of pte
1157         ;;
1158         dep     r18=0,r18,61,3          // convert vhpt ptr to physical
1159         ;;
1160         add     r20=16,r18              // address of tag
1161         ;;
1162         ld8.acq r23=[r20]               // read old tag
1163         ;;
1164         dep     r23=-1,r23,63,1         // set ti bit
1165         ;;
1166         st8.rel [r20]=r23               // store old tag + ti
1167         ;;
1168         mf                              // make sure everyone sees
1169         ;;
1170         st8     [r18]=r21,8             // store pte
1171         ;;
1172         st8     [r18]=r22,8
1173         ;;
1174         st8.rel [r18]=r19               // store new tag
1175         ;;
1176         itc.i   r21                     // and place in TLB
1177         ssm     psr.dt
1178         ;;
1179         srlz.d
1180         mov     pr=r17,0x1ffff          // restore predicates
1181         rfi                             // walker will retry the access
1182         ;;
1183 2:      add     r20=24,r20              // next in chain
1184         ;;
1185         ld8     r20=[r20]               // read chain
1186         br.cond.sptk.few 1b             // loop
1187         ;;
1188 9:      ssm     psr.dt
1189         mov     pr=r17,0x1ffff          // restore predicates
1190         ;;
1191         srlz.d
1192         ;;
1193         CALL(trap, 9, cr.ifa)
1194 IVT_END(Instruction_Access_Bit)
1195
1196 IVT_ENTRY(Data_Access_Bit, 0x2800)
1197         mov     r16=cr.ifa
1198         mov     r17=pr
1199         ;;
1200         thash   r18=r16
1201         ;;
1202         ttag    r19=r16
1203         add     r20=24,r18              // collision chain
1204         ;;
1205         ld8     r20=[r20]               // bucket head
1206         ;;
1207         rsm     psr.dt                  // turn off data translations
1208         dep     r20=0,r20,61,3          // convert vhpt ptr to physical
1209         ;;
1210         srlz.d                          // serialize
1211         ld8     r20=[r20]               // first entry
1212         ;;
1213 1:      cmp.eq  p15,p0=r0,r20           // done?
1214 (p15)   br.cond.spnt.few 9f             // bail if done
1215         ;;
1216         add     r21=16,r20              // tag location
1217         ;;
1218         ld8     r21=[r21]               // read tag
1219         ;;
1220         cmp.ne  p15,p0=r21,r19          // compare tags
1221 (p15)   br.cond.sptk.few 2f             // if not, read next in chain
1222         ;;
1223         ld8     r21=[r20]               // read pte
1224         mov     r22=PTE_ACCESSED
1225         ;;
1226         or      r21=r22,r21             // set accessed bit
1227         ;;
1228         st8     [r20]=r21,8             // store back
1229         ;;
1230         ld8     r22=[r20]               // read rest of pte
1231         ;;
1232         dep     r18=0,r18,61,3          // convert vhpt ptr to physical
1233         ;;
1234         add     r20=16,r18              // address of tag
1235         ;;
1236         ld8.acq r23=[r20]               // read old tag
1237         ;;
1238         dep     r23=-1,r23,63,1         // set ti bit
1239         ;;
1240         st8.rel [r20]=r23               // store old tag + ti
1241         ;;
1242         mf                              // make sure everyone sees
1243         ;;
1244         st8     [r18]=r21,8             // store pte
1245         ;;
1246         st8     [r18]=r22,8
1247         ;;
1248         st8.rel [r18]=r19               // store new tag
1249         ;;
1250         itc.d   r21                     // and place in TLB
1251         ssm     psr.dt
1252         ;;
1253         srlz.d
1254         mov     pr=r17,0x1ffff          // restore predicates
1255         rfi                             // walker will retry the access
1256         ;;
1257 2:      add     r20=24,r20              // next in chain
1258         ;;
1259         ld8     r20=[r20]               // read chain
1260         br.cond.sptk.few 1b             // loop
1261         ;;
1262 9:      ssm     psr.dt
1263         mov     pr=r17,0x1ffff          // restore predicates
1264         ;;
1265         srlz.d
1266         ;;
1267         CALL(trap, 10, cr.ifa)
1268 IVT_END(Data_Access_Bit)
1269
1270 IVT_ENTRY(Break_Instruction, 0x2c00)
1271 {       .mib
1272         mov             r17=cr.iim
1273         mov             r16=ip
1274         br.sptk         exception_save
1275         ;;
1276 }
1277 {       .mmi
1278         alloc           r15=ar.pfs,0,0,2,0
1279         ;;
1280 (p11)   ssm             psr.i
1281         mov             out0=11
1282         ;;
1283 }
1284 {       .mmi
1285         flushrs
1286         ;;
1287 (p11)   srlz.d
1288         add             out1=16,sp
1289 }
1290 {       .mib
1291         nop             0
1292         nop             0
1293         br.call.sptk    rp=trap
1294         ;;
1295 }
1296 {       .mib
1297         nop             0
1298         nop             0
1299         br.sptk         exception_restore
1300         ;;
1301 }
1302 IVT_END(Break_Instruction)
1303
1304 IVT_ENTRY(External_Interrupt, 0x3000)
1305 {       .mib
1306         mov             r17=ar.itc      // Put the ITC in the trapframe.
1307         mov             r16=ip
1308         br.sptk         exception_save
1309         ;;
1310 }
1311 {       .mmi
1312         alloc           r15=ar.pfs,0,0,1,0
1313         nop             0
1314         nop             0
1315         ;;
1316 }
1317 {       .mib
1318         add             out0=16,sp
1319         nop             0
1320         br.call.sptk    rp=ia64_handle_intr
1321         ;;
1322 }
1323 {       .mib
1324         nop             0
1325         nop             0
1326         br.sptk         exception_restore
1327         ;;
1328 }
1329 IVT_END(External_Interrupt)
1330
1331 IVT_ENTRY(Reserved_3400, 0x3400)
1332         CALL(trap, 13, cr.ifa)
1333 IVT_END(Reserved_3400)
1334
1335 IVT_ENTRY(Reserved_3800, 0x3800)
1336         CALL(trap, 14, cr.ifa)
1337 IVT_END(Reserved_3800)
1338
1339 IVT_ENTRY(Reserved_3c00, 0x3c00)
1340         CALL(trap, 15, cr.ifa)
1341 IVT_END(Reserved_3c00)
1342
1343 IVT_ENTRY(Reserved_4000, 0x4000)
1344         CALL(trap, 16, cr.ifa)
1345 IVT_END(Reserved_4000)
1346
1347 IVT_ENTRY(Reserved_4400, 0x4400)
1348         CALL(trap, 17, cr.ifa)
1349 IVT_END(Reserved_4400)
1350
1351 IVT_ENTRY(Reserved_4800, 0x4800)
1352         CALL(trap, 18, cr.ifa)
1353 IVT_END(Reserved_4800)
1354
1355 IVT_ENTRY(Reserved_4c00, 0x4c00)
1356         CALL(trap, 19, cr.ifa)
1357 IVT_END(Reserved_4c00)
1358
1359 IVT_ENTRY(Page_Not_Present, 0x5000)
1360         CALL(trap, 20, cr.ifa)
1361 IVT_END(Page_Not_Present)
1362
1363 IVT_ENTRY(Key_Permission, 0x5100)
1364         CALL(trap, 21, cr.ifa)
1365 IVT_END(Key_Permission)
1366
1367 IVT_ENTRY(Instruction_Access_Rights, 0x5200)
1368         CALL(trap, 22, cr.ifa)
1369 IVT_END(Instruction_Access_Rights)
1370
1371 IVT_ENTRY(Data_Access_Rights, 0x5300)
1372         CALL(trap, 23, cr.ifa)
1373 IVT_END(Data_Access_Rights)
1374
1375 IVT_ENTRY(General_Exception, 0x5400)
1376         CALL(trap, 24, cr.ifa)
1377 IVT_END(General_Exception)
1378
1379 IVT_ENTRY(Disabled_FP_Register, 0x5500)
1380         CALL(trap, 25, cr.ifa)
1381 IVT_END(Disabled_FP_Register)
1382
1383 IVT_ENTRY(NaT_Consumption, 0x5600)
1384         CALL(trap, 26, cr.ifa)
1385 IVT_END(NaT_Consumption)
1386
1387 IVT_ENTRY(Speculation, 0x5700)
1388         CALL(trap, 27, cr.iim)
1389 IVT_END(Speculation)
1390
1391 IVT_ENTRY(Reserved_5800, 0x5800)
1392         CALL(trap, 28, cr.ifa)
1393 IVT_END(Reserved_5800)
1394
1395 IVT_ENTRY(Debug, 0x5900)
1396         CALL(trap, 29, cr.ifa)
1397 IVT_END(Debug)
1398
1399 IVT_ENTRY(Unaligned_Reference, 0x5a00)
1400         CALL(trap, 30, cr.ifa)
1401 IVT_END(Unaligned_Reference)
1402
1403 IVT_ENTRY(Unsupported_Data_Reference, 0x5b00)
1404         CALL(trap, 31, cr.ifa)
1405 IVT_END(Unsupported_Data_Reference)
1406
1407 IVT_ENTRY(Floating_Point_Fault, 0x5c00)
1408         CALL(trap, 32, cr.ifa)
1409 IVT_END(Floating_Point_Fault)
1410
1411 IVT_ENTRY(Floating_Point_Trap, 0x5d00)
1412         CALL(trap, 33, cr.ifa)
1413 IVT_END(Floating_Point_Trap)
1414
1415 IVT_ENTRY(Lower_Privilege_Transfer_Trap, 0x5e00)
1416         CALL(trap, 34, cr.ifa)
1417 IVT_END(Lower_Privilege_Transfer_Trap)
1418
1419 IVT_ENTRY(Taken_Branch_Trap, 0x5f00)
1420         CALL(trap, 35, cr.ifa)
1421 IVT_END(Taken_Branch_Trap)
1422
1423 IVT_ENTRY(Single_Step_Trap, 0x6000)
1424         CALL(trap, 36, cr.ifa)
1425 IVT_END(Single_Step_Trap)
1426
1427 IVT_ENTRY(Reserved_6100, 0x6100)
1428         CALL(trap, 37, cr.ifa)
1429 IVT_END(Reserved_6100)
1430
1431 IVT_ENTRY(Reserved_6200, 0x6200)
1432         CALL(trap, 38, cr.ifa)
1433 IVT_END(Reserved_6200)
1434
1435 IVT_ENTRY(Reserved_6300, 0x6300)
1436         CALL(trap, 39, cr.ifa)
1437 IVT_END(Reserved_6300)
1438
1439 IVT_ENTRY(Reserved_6400, 0x6400)
1440         CALL(trap, 40, cr.ifa)
1441 IVT_END(Reserved_6400)
1442
1443 IVT_ENTRY(Reserved_6500, 0x6500)
1444         CALL(trap, 41, cr.ifa)
1445 IVT_END(Reserved_6500)
1446
1447 IVT_ENTRY(Reserved_6600, 0x6600)
1448         CALL(trap, 42, cr.ifa)
1449 IVT_END(Reserved_6600)
1450
1451 IVT_ENTRY(Reserved_6700, 0x6700)
1452         CALL(trap, 43, cr.ifa)
1453 IVT_END(Reserved_6700)
1454
1455 IVT_ENTRY(Reserved_6800, 0x6800)
1456         CALL(trap, 44, cr.ifa)
1457 IVT_END(Reserved_6800)
1458
1459 IVT_ENTRY(IA_32_Exception, 0x6900)
1460         CALL(IA32_TRAP, 45, cr.ifa)
1461 IVT_END(IA_32_Exception)
1462
1463 IVT_ENTRY(IA_32_Intercept, 0x6a00)
1464         CALL(IA32_TRAP, 46, cr.iim)
1465 IVT_END(IA_32_Intercept)
1466
1467 IVT_ENTRY(IA_32_Interrupt, 0x6b00)
1468         CALL(IA32_TRAP, 47, cr.ifa)
1469 IVT_END(IA_32_Interrupt)
1470
1471 IVT_ENTRY(Reserved_6c00, 0x6c00)
1472         CALL(trap, 48, cr.ifa)
1473 IVT_END(Reserved_6c00)
1474
1475 IVT_ENTRY(Reserved_6d00, 0x6d00)
1476         CALL(trap, 49, cr.ifa)
1477 IVT_END(Reserved_6d00)
1478
1479 IVT_ENTRY(Reserved_6e00, 0x6e00)
1480         CALL(trap, 50, cr.ifa)
1481 IVT_END(Reserved_6e00)
1482
1483 IVT_ENTRY(Reserved_6f00, 0x6f00)
1484         CALL(trap, 51, cr.ifa)
1485 IVT_END(Reserved_6f00)
1486
1487 IVT_ENTRY(Reserved_7000, 0x7000)
1488         CALL(trap, 52, cr.ifa)
1489 IVT_END(Reserved_7000)
1490
1491 IVT_ENTRY(Reserved_7100, 0x7100)
1492         CALL(trap, 53, cr.ifa)
1493 IVT_END(Reserved_7100)
1494
1495 IVT_ENTRY(Reserved_7200, 0x7200)
1496         CALL(trap, 54, cr.ifa)
1497 IVT_END(Reserved_7200)
1498
1499 IVT_ENTRY(Reserved_7300, 0x7300)
1500         CALL(trap, 55, cr.ifa)
1501 IVT_END(Reserved_7300)
1502
1503 IVT_ENTRY(Reserved_7400, 0x7400)
1504         CALL(trap, 56, cr.ifa)
1505 IVT_END(Reserved_7400)
1506
1507 IVT_ENTRY(Reserved_7500, 0x7500)
1508         CALL(trap, 57, cr.ifa)
1509 IVT_END(Reserved_7500)
1510
1511 IVT_ENTRY(Reserved_7600, 0x7600)
1512         CALL(trap, 58, cr.ifa)
1513 IVT_END(Reserved_7600)
1514
1515 IVT_ENTRY(Reserved_7700, 0x7700)
1516         CALL(trap, 59, cr.ifa)
1517 IVT_END(Reserved_7700)
1518
1519 IVT_ENTRY(Reserved_7800, 0x7800)
1520         CALL(trap, 60, cr.ifa)
1521 IVT_END(Reserved_7800)
1522
1523 IVT_ENTRY(Reserved_7900, 0x7900)
1524         CALL(trap, 61, cr.ifa)
1525 IVT_END(Reserved_7900)
1526
1527 IVT_ENTRY(Reserved_7a00, 0x7a00)
1528         CALL(trap, 62, cr.ifa)
1529 IVT_END(Reserved_7a00)
1530
1531 IVT_ENTRY(Reserved_7b00, 0x7b00)
1532         CALL(trap, 63, cr.ifa)
1533 IVT_END(Reserved_7b00)
1534
1535 IVT_ENTRY(Reserved_7c00, 0x7c00)
1536         CALL(trap, 64, cr.ifa)
1537 IVT_END(Reserved_7c00)
1538
1539 IVT_ENTRY(Reserved_7d00, 0x7d00)
1540         CALL(trap, 65, cr.ifa)
1541 IVT_END(Reserved_7d00)
1542
1543 IVT_ENTRY(Reserved_7e00, 0x7e00)
1544         CALL(trap, 66, cr.ifa)
1545 IVT_END(Reserved_7e00)
1546
1547 IVT_ENTRY(Reserved_7f00, 0x7f00)
1548         CALL(trap, 67, cr.ifa)
1549 IVT_END(Reserved_7f00)