sys/sparc64/include/tlb.h

   1 /*-
   2  * Copyright (c) 2001 Jake Burkholder.
   3  * Copyright (c) 2008, 2010 Marius Strobl <marius@FreeBSD.org>
   4  * All rights reserved.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions
   8  * are met:
   9  * 1. Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions and the following disclaimer.
  11  * 2. Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the distribution.
  14  *
  15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  16  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  17  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  18  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  19  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  20  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  21  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  22  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  23  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  24  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  25  * SUCH DAMAGE.
  26  *
  27  * $FreeBSD$
  28  */
  29
  30 #ifndef _MACHINE_TLB_H_
  31 #define _MACHINE_TLB_H_
  32
  33 #define TLB_DIRECT_ADDRESS_BITS         (43)
  34 #define TLB_DIRECT_PAGE_BITS            (PAGE_SHIFT_4M)
  35
  36 #define TLB_DIRECT_ADDRESS_MASK         ((1UL << TLB_DIRECT_ADDRESS_BITS) - 1)
  37 #define TLB_DIRECT_PAGE_MASK            ((1UL << TLB_DIRECT_PAGE_BITS) - 1)
  38
  39 #define TLB_PHYS_TO_DIRECT(pa)                                          \
  40         ((pa) | VM_MIN_DIRECT_ADDRESS)
  41 #define TLB_DIRECT_TO_PHYS(va)                                          \
  42         ((va) & TLB_DIRECT_ADDRESS_MASK)
  43 #define TLB_DIRECT_TO_TTE_MASK                                          \
  44         (TD_V | TD_4M | (TLB_DIRECT_ADDRESS_MASK - TLB_DIRECT_PAGE_MASK))
  45
  46 #define TLB_DAR_SLOT_SHIFT              (3)
  47 #define TLB_DAR_SLOT(slot)              ((slot) << TLB_DAR_SLOT_SHIFT)
  48
  49 #define TAR_VPN_SHIFT                   (13)
  50 #define TAR_CTX_MASK                    ((1 << TAR_VPN_SHIFT) - 1)
  51
  52 #define TLB_TAR_VA(va)                  ((va) & ~TAR_CTX_MASK)
  53 #define TLB_TAR_CTX(ctx)                ((ctx) & TAR_CTX_MASK)
  54
  55 #define TLB_CXR_CTX_BITS                (13)
  56 #define TLB_CXR_CTX_MASK                                                \
  57         (((1UL << TLB_CXR_CTX_BITS) - 1) << TLB_CXR_CTX_SHIFT)
  58 #define TLB_CXR_CTX_SHIFT               (0)
  59 #define TLB_CXR_PGSZ_BITS               (3)
  60 #define TLB_CXR_PGSZ_MASK               (~TLB_CXR_CTX_MASK)
  61 #define TLB_PCXR_N_IPGSZ0_SHIFT         (53)    /* SPARC64 VI, VII, VIIIfx */
  62 #define TLB_PCXR_N_IPGSZ1_SHIFT         (50)    /* SPARC64 VI, VII, VIIIfx */
  63 #define TLB_PCXR_N_PGSZ0_SHIFT          (61)
  64 #define TLB_PCXR_N_PGSZ1_SHIFT          (58)
  65 #define TLB_PCXR_N_PGSZ_I_SHIFT         (55)    /* US-IV+ */
  66 #define TLB_PCXR_P_IPGSZ0_SHIFT         (24)    /* SPARC64 VI, VII, VIIIfx */
  67 #define TLB_PCXR_P_IPGSZ1_SHIFT         (27)    /* SPARC64 VI, VII, VIIIfx */
  68 #define TLB_PCXR_P_PGSZ0_SHIFT          (16)
  69 #define TLB_PCXR_P_PGSZ1_SHIFT          (19)
  70 /*
  71  * Note that the US-IV+ documentation appears to have TLB_PCXR_P_PGSZ_I_SHIFT
  72  * and TLB_PCXR_P_PGSZ0_SHIFT erroneously inverted.
  73  */
  74 #define TLB_PCXR_P_PGSZ_I_SHIFT         (22)    /* US-IV+ */
  75 #define TLB_SCXR_S_PGSZ1_SHIFT          (19)
  76 #define TLB_SCXR_S_PGSZ0_SHIFT          (16)
  77
  78 #define TLB_TAE_PGSZ_BITS               (3)
  79 #define TLB_TAE_PGSZ0_MASK                                              \
  80         (((1UL << TLB_TAE_PGSZ_BITS) - 1) << TLB_TAE_PGSZ0_SHIFT)
  81 #define TLB_TAE_PGSZ1_MASK                                              \
  82         (((1UL << TLB_TAE_PGSZ_BITS) - 1) << TLB_TAE_PGSZ1_SHIFT)
  83 #define TLB_TAE_PGSZ0_SHIFT             (16)
  84 #define TLB_TAE_PGSZ1_SHIFT             (19)
  85
  86 #define TLB_DEMAP_ID_SHIFT              (4)
  87 #define TLB_DEMAP_ID_PRIMARY            (0)
  88 #define TLB_DEMAP_ID_SECONDARY          (1)
  89 #define TLB_DEMAP_ID_NUCLEUS            (2)
  90
  91 #define TLB_DEMAP_TYPE_SHIFT            (6)
  92 #define TLB_DEMAP_TYPE_PAGE             (0)
  93 #define TLB_DEMAP_TYPE_CONTEXT          (1)
  94 #define TLB_DEMAP_TYPE_ALL              (2)     /* US-III and beyond only */
  95
  96 #define TLB_DEMAP_VA(va)                ((va) & ~PAGE_MASK)
  97 #define TLB_DEMAP_ID(id)                ((id) << TLB_DEMAP_ID_SHIFT)
  98 #define TLB_DEMAP_TYPE(type)            ((type) << TLB_DEMAP_TYPE_SHIFT)
  99
 100 #define TLB_DEMAP_PAGE                  (TLB_DEMAP_TYPE(TLB_DEMAP_TYPE_PAGE))
 101 #define TLB_DEMAP_CONTEXT               (TLB_DEMAP_TYPE(TLB_DEMAP_TYPE_CONTEXT))
 102 #define TLB_DEMAP_ALL                   (TLB_DEMAP_TYPE(TLB_DEMAP_TYPE_ALL))
 103
 104 #define TLB_DEMAP_PRIMARY               (TLB_DEMAP_ID(TLB_DEMAP_ID_PRIMARY))
 105 #define TLB_DEMAP_SECONDARY             (TLB_DEMAP_ID(TLB_DEMAP_ID_SECONDARY))
 106 #define TLB_DEMAP_NUCLEUS               (TLB_DEMAP_ID(TLB_DEMAP_ID_NUCLEUS))
 107
 108 #define TLB_CTX_KERNEL                  (0)
 109 #define TLB_CTX_USER_MIN                (1)
 110 #define TLB_CTX_USER_MAX                (8192)
 111
 112 #define MMU_SFSR_ASI_SHIFT              (16)
 113 #define MMU_SFSR_FT_SHIFT               (7)
 114 #define MMU_SFSR_E_SHIFT                (6)
 115 #define MMU_SFSR_CT_SHIFT               (4)
 116 #define MMU_SFSR_PR_SHIFT               (3)
 117 #define MMU_SFSR_W_SHIFT                (2)
 118 #define MMU_SFSR_OW_SHIFT               (1)
 119 #define MMU_SFSR_FV_SHIFT               (0)
 120
 121 #define MMU_SFSR_ASI_SIZE               (8)
 122 #define MMU_SFSR_FT_SIZE                (6)
 123 #define MMU_SFSR_CT_SIZE                (2)
 124
 125 #define MMU_SFSR_GET_ASI(sfsr)                                          \
 126         (((sfsr) >> MMU_SFSR_ASI_SHIFT) & ((1UL << MMU_SFSR_ASI_SIZE) - 1))
 127 #define MMU_SFSR_GET_FT(sfsr)                                           \
 128         (((sfsr) >> MMU_SFSR_FT_SHIFT) & ((1UL << MMU_SFSR_FT_SIZE) - 1))
 129 #define MMU_SFSR_GET_CT(sfsr)                                           \
 130         (((sfsr) >> MMU_SFSR_CT_SHIFT) & ((1UL << MMU_SFSR_CT_SIZE) - 1))
 131
 132 #define MMU_SFSR_E                      (1UL << MMU_SFSR_E_SHIFT)
 133 #define MMU_SFSR_PR                     (1UL << MMU_SFSR_PR_SHIFT)
 134 #define MMU_SFSR_W                      (1UL << MMU_SFSR_W_SHIFT)
 135 #define MMU_SFSR_OW                     (1UL << MMU_SFSR_OW_SHIFT)
 136 #define MMU_SFSR_FV                     (1UL << MMU_SFSR_FV_SHIFT)
 137
 138 typedef void tlb_flush_nonlocked_t(void);
 139 typedef void tlb_flush_user_t(void);
 140
 141 struct pmap;
 142 struct tlb_entry;
 143
 144 extern int dtlb_slots;
 145 extern int itlb_slots;
 146 extern int kernel_tlb_slots;
 147 extern struct tlb_entry *kernel_tlbs;
 148
 149 void    tlb_context_demap(struct pmap *pm);
 150 void    tlb_page_demap(struct pmap *pm, vm_offset_t va);
 151 void    tlb_range_demap(struct pmap *pm, vm_offset_t start, vm_offset_t end);
 152
 153 tlb_flush_nonlocked_t cheetah_tlb_flush_nonlocked;
 154 tlb_flush_user_t cheetah_tlb_flush_user;
 155
 156 tlb_flush_nonlocked_t spitfire_tlb_flush_nonlocked;
 157 tlb_flush_user_t spitfire_tlb_flush_user;
 158
 159 extern tlb_flush_nonlocked_t *tlb_flush_nonlocked;
 160 extern tlb_flush_user_t *tlb_flush_user;
 161
 162 #endif /* !_MACHINE_TLB_H_ */