2 * Copyright (c) 1999, 2000 Matthew R. Green
3 * Copyright (c) 2001 - 2003 by Thomas Moestl <tmm@FreeBSD.org>
4 * Copyright (c) 2005 - 2006 Marius Strobl <marius@FreeBSD.org>
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. The name of the author may not be used to endorse or promote products
16 * derived from this software without specific prior written permission.
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
23 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
24 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
25 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
26 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 * from: NetBSD: psycho.c,v 1.39 2001/10/07 20:30:41 eeh Exp
33 #include <sys/cdefs.h>
34 __FBSDID("$FreeBSD$");
37 * Support for `Hummingbird' (UltraSPARC IIe), `Psycho' and `Psycho+'
38 * (UltraSPARC II) and `Sabre' (UltraSPARC IIi) UPA to PCI bridges.
41 #include "opt_ofw_pci.h"
42 #include "opt_psycho.h"
44 #include <sys/param.h>
45 #include <sys/systm.h>
47 #include <sys/endian.h>
49 #include <sys/kernel.h>
51 #include <sys/malloc.h>
52 #include <sys/module.h>
53 #include <sys/mutex.h>
55 #include <sys/reboot.h>
58 #include <dev/ofw/ofw_bus.h>
59 #include <dev/ofw/ofw_pci.h>
60 #include <dev/ofw/openfirm.h>
62 #include <machine/bus.h>
63 #include <machine/bus_common.h>
64 #include <machine/bus_private.h>
65 #include <machine/iommureg.h>
66 #include <machine/iommuvar.h>
67 #include <machine/resource.h>
68 #include <machine/ver.h>
70 #include <dev/pci/pcireg.h>
71 #include <dev/pci/pcivar.h>
73 #include <sparc64/pci/ofw_pci.h>
74 #include <sparc64/pci/psychoreg.h>
75 #include <sparc64/pci/psychovar.h>
79 static const struct psycho_desc *psycho_find_desc(const struct psycho_desc *,
81 static const struct psycho_desc *psycho_get_desc(device_t);
82 static void psycho_set_intr(struct psycho_softc *, u_int, bus_addr_t,
83 driver_filter_t, driver_intr_t);
84 static int psycho_find_intrmap(struct psycho_softc *, u_int, bus_addr_t *,
85 bus_addr_t *, u_long *);
86 static driver_filter_t psycho_dma_sync_stub;
87 static void psycho_intr_enable(void *);
88 static void psycho_intr_disable(void *);
89 static void psycho_intr_assign(void *);
90 static void psycho_intr_clear(void *);
91 static bus_space_tag_t psycho_alloc_bus_tag(struct psycho_softc *, int);
93 /* Interrupt handlers */
94 static driver_filter_t psycho_ue;
95 static driver_filter_t psycho_ce;
96 static driver_filter_t psycho_pci_bus;
97 static driver_filter_t psycho_powerfail;
98 static driver_intr_t psycho_overtemp;
99 #ifdef PSYCHO_MAP_WAKEUP
100 static driver_filter_t psycho_wakeup;
104 static void psycho_iommu_init(struct psycho_softc *, int, uint32_t);
109 static device_probe_t psycho_probe;
110 static device_attach_t psycho_attach;
111 static bus_read_ivar_t psycho_read_ivar;
112 static bus_setup_intr_t psycho_setup_intr;
113 static bus_teardown_intr_t psycho_teardown_intr;
114 static bus_alloc_resource_t psycho_alloc_resource;
115 static bus_activate_resource_t psycho_activate_resource;
116 static bus_deactivate_resource_t psycho_deactivate_resource;
117 static bus_release_resource_t psycho_release_resource;
118 static bus_describe_intr_t psycho_describe_intr;
119 static bus_get_dma_tag_t psycho_get_dma_tag;
120 static pcib_maxslots_t psycho_maxslots;
121 static pcib_read_config_t psycho_read_config;
122 static pcib_write_config_t psycho_write_config;
123 static pcib_route_interrupt_t psycho_route_interrupt;
124 static ofw_bus_get_node_t psycho_get_node;
126 static device_method_t psycho_methods[] = {
127 /* Device interface */
128 DEVMETHOD(device_probe, psycho_probe),
129 DEVMETHOD(device_attach, psycho_attach),
130 DEVMETHOD(device_shutdown, bus_generic_shutdown),
131 DEVMETHOD(device_suspend, bus_generic_suspend),
132 DEVMETHOD(device_resume, bus_generic_resume),
135 DEVMETHOD(bus_print_child, bus_generic_print_child),
136 DEVMETHOD(bus_read_ivar, psycho_read_ivar),
137 DEVMETHOD(bus_setup_intr, psycho_setup_intr),
138 DEVMETHOD(bus_teardown_intr, psycho_teardown_intr),
139 DEVMETHOD(bus_alloc_resource, psycho_alloc_resource),
140 DEVMETHOD(bus_activate_resource, psycho_activate_resource),
141 DEVMETHOD(bus_deactivate_resource, psycho_deactivate_resource),
142 DEVMETHOD(bus_release_resource, psycho_release_resource),
143 DEVMETHOD(bus_describe_intr, psycho_describe_intr),
144 DEVMETHOD(bus_get_dma_tag, psycho_get_dma_tag),
147 DEVMETHOD(pcib_maxslots, psycho_maxslots),
148 DEVMETHOD(pcib_read_config, psycho_read_config),
149 DEVMETHOD(pcib_write_config, psycho_write_config),
150 DEVMETHOD(pcib_route_interrupt, psycho_route_interrupt),
152 /* ofw_bus interface */
153 DEVMETHOD(ofw_bus_get_node, psycho_get_node),
158 static devclass_t psycho_devclass;
160 DEFINE_CLASS_0(pcib, psycho_driver, psycho_methods,
161 sizeof(struct psycho_softc));
162 DRIVER_MODULE(psycho, nexus, psycho_driver, psycho_devclass, 0, 0);
164 static SLIST_HEAD(, psycho_softc) psycho_softcs =
165 SLIST_HEAD_INITIALIZER(psycho_softcs);
167 static const struct intr_controller psycho_ic = {
174 struct psycho_icarg {
175 struct psycho_softc *pica_sc;
180 struct psycho_dma_sync {
181 struct psycho_softc *pds_sc;
182 driver_filter_t *pds_handler; /* handler to call */
183 void *pds_arg; /* argument for the handler */
184 void *pds_cookie; /* parent bus int. cookie */
185 device_t pds_ppb; /* farest PCI-PCI bridge */
186 uint8_t pds_bus; /* bus of farest PCI dev. */
187 uint8_t pds_slot; /* slot of farest PCI dev. */
188 uint8_t pds_func; /* func. of farest PCI dev. */
191 #define PSYCHO_READ8(sc, off) \
192 bus_read_8((sc)->sc_mem_res, (off))
193 #define PSYCHO_WRITE8(sc, off, v) \
194 bus_write_8((sc)->sc_mem_res, (off), (v))
195 #define PCICTL_READ8(sc, off) \
196 PSYCHO_READ8((sc), (sc)->sc_pcictl + (off))
197 #define PCICTL_WRITE8(sc, off, v) \
198 PSYCHO_WRITE8((sc), (sc)->sc_pcictl + (off), (v))
201 * "Sabre" is the UltraSPARC IIi onboard UPA to PCI bridge. It manages a
202 * single PCI bus and does not have a streaming buffer. It often has an APB
203 * (advanced PCI bridge) connected to it, which was designed specifically for
204 * the IIi. The APB let's the IIi handle two independednt PCI buses, and
205 * appears as two "Simba"'s underneath the Sabre.
207 * "Hummingbird" is the UltraSPARC IIe onboard UPA to PCI bridge. It's
208 * basically the same as Sabre but without an APB underneath it.
210 * "Psycho" and "Psycho+" are dual UPA to PCI bridges. They sit on the UPA
211 * bus and manage two PCI buses. "Psycho" has two 64-bit 33MHz buses, while
212 * "Psycho+" controls both a 64-bit 33Mhz and a 64-bit 66Mhz PCI bus. You
213 * will usually find a "Psycho+" since I don't think the original "Psycho"
214 * ever shipped, and if it did it would be in the U30.
216 * Each "Psycho" PCI bus appears as a separate OFW node, but since they are
217 * both part of the same IC, they only have a single register space. As such,
218 * they need to be configured together, even though the autoconfiguration will
219 * attach them separately.
221 * On UltraIIi machines, "Sabre" itself usually takes pci0, with "Simba" often
222 * as pci1 and pci2, although they have been implemented with other PCI bus
223 * numbers on some machines.
225 * On UltraII machines, there can be any number of "Psycho+" ICs, each
226 * providing two PCI buses.
230 const char *pd_string;
235 static const struct psycho_desc const psycho_compats[] = {
236 { "pci108e,8000", PSYCHO_MODE_PSYCHO, "Psycho compatible" },
237 { "pci108e,a000", PSYCHO_MODE_SABRE, "Sabre compatible" },
238 { "pci108e,a001", PSYCHO_MODE_SABRE, "Hummingbird compatible" },
242 static const struct psycho_desc const psycho_models[] = {
243 { "SUNW,psycho", PSYCHO_MODE_PSYCHO, "Psycho" },
244 { "SUNW,sabre", PSYCHO_MODE_SABRE, "Sabre" },
248 static const struct psycho_desc *
249 psycho_find_desc(const struct psycho_desc *table, const char *string)
251 const struct psycho_desc *desc;
255 for (desc = table; desc->pd_string != NULL; desc++)
256 if (strcmp(desc->pd_string, string) == 0)
261 static const struct psycho_desc *
262 psycho_get_desc(device_t dev)
264 const struct psycho_desc *rv;
266 rv = psycho_find_desc(psycho_models, ofw_bus_get_model(dev));
268 rv = psycho_find_desc(psycho_compats,
269 ofw_bus_get_compat(dev));
274 psycho_probe(device_t dev)
278 dtype = ofw_bus_get_type(dev);
279 if (dtype != NULL && strcmp(dtype, OFW_TYPE_PCI) == 0 &&
280 psycho_get_desc(dev) != NULL) {
281 device_set_desc(dev, "U2P UPA-PCI bridge");
288 psycho_attach(device_t dev)
290 char name[sizeof("pci108e,1000")];
291 struct psycho_icarg *pica;
292 struct psycho_softc *asc, *sc, *osc;
293 struct ofw_pci_ranges *range;
294 const struct psycho_desc *desc;
295 bus_addr_t intrclr, intrmap;
297 phandle_t child, node;
298 uint32_t dvmabase, prop, prop_array[2];
303 node = ofw_bus_get_node(dev);
304 sc = device_get_softc(dev);
305 desc = psycho_get_desc(dev);
309 sc->sc_mode = desc->pd_mode;
312 * The Psycho gets three register banks:
313 * (0) per-PBM configuration and status registers
314 * (1) per-PBM PCI configuration space, containing only the
315 * PBM 256-byte PCI header
316 * (2) the shared Psycho configuration registers
318 if (sc->sc_mode == PSYCHO_MODE_PSYCHO) {
321 bus_get_resource_start(dev, SYS_RES_MEMORY, 0) -
322 bus_get_resource_start(dev, SYS_RES_MEMORY, 2);
323 switch (sc->sc_pcictl) {
331 panic("%s: bogus PCI control register location",
337 sc->sc_pcictl = PSR_PCICTL0;
340 sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &i,
341 (sc->sc_mode == PSYCHO_MODE_PSYCHO ? RF_SHAREABLE : 0) |
343 if (sc->sc_mem_res == NULL)
344 panic("%s: could not allocate registers", __func__);
347 * Match other Psychos that are already configured against
348 * the base physical address. This will be the same for a
349 * pair of devices that share register space.
352 SLIST_FOREACH(asc, &psycho_softcs, sc_link) {
353 if (rman_get_start(asc->sc_mem_res) ==
354 rman_get_start(sc->sc_mem_res)) {
361 sc->sc_mtx = malloc(sizeof(*sc->sc_mtx), M_DEVBUF,
363 if (sc->sc_mtx == NULL)
364 panic("%s: could not malloc mutex", __func__);
365 mtx_init(sc->sc_mtx, "pcib_mtx", NULL, MTX_SPIN);
367 if (sc->sc_mode != PSYCHO_MODE_PSYCHO)
368 panic("%s: no partner expected", __func__);
369 if (mtx_initialized(osc->sc_mtx) == 0)
370 panic("%s: mutex not initialized", __func__);
371 sc->sc_mtx = osc->sc_mtx;
374 csr = PSYCHO_READ8(sc, PSR_CS);
375 ver = PSYCHO_GCSR_VERS(csr);
376 sc->sc_ign = 0x1f; /* Hummingbird/Sabre IGN is always 0x1f. */
377 if (sc->sc_mode == PSYCHO_MODE_PSYCHO)
378 sc->sc_ign = PSYCHO_GCSR_IGN(csr);
379 if (OF_getprop(node, "clock-frequency", &prop, sizeof(prop)) == -1)
383 "%s, impl %d, version %d, IGN %#x, bus %c, %dMHz\n",
384 desc->pd_name, (u_int)PSYCHO_GCSR_IMPL(csr), ver, sc->sc_ign,
385 'A' + sc->sc_half, prop / 1000 / 1000);
387 /* Set up the PCI control and PCI diagnostic registers. */
390 * Revision 0 EBus bridges have a bug which prevents them from
391 * working when bus parking is enabled.
394 csr = PCICTL_READ8(sc, PCR_CS);
395 csr &= ~PCICTL_ARB_PARK;
396 for (child = OF_child(node); child != 0; child = OF_peer(child)) {
397 if (OF_getprop(child, "name", name, sizeof(name)) == -1)
399 if ((strcmp(name, "ebus") == 0 ||
400 strcmp(name, "pci108e,1000") == 0) &&
401 OF_getprop(child, "revision-id", &rev, sizeof(rev)) > 0 &&
405 if (rev != 0 && OF_getproplen(node, "no-bus-parking") < 0)
406 csr |= PCICTL_ARB_PARK;
408 /* Workarounds for version specific bugs. */
409 dr = PCICTL_READ8(sc, PCR_DIAG);
413 dr &= ~DIAG_DWSYNC_DIS;
417 csr &= ~PCICTL_ARB_PARK;
418 dr |= DIAG_RTRY_DIS | DIAG_DWSYNC_DIS;
422 dr |= DIAG_DWSYNC_DIS;
423 dr &= ~DIAG_RTRY_DIS;
428 csr |= PCICTL_ERRINTEN | PCICTL_ARB_4;
429 csr &= ~(PCICTL_SBHINTEN | PCICTL_WAKEUPEN);
431 device_printf(dev, "PCI CSR 0x%016llx -> 0x%016llx\n",
432 (unsigned long long)PCICTL_READ8(sc, PCR_CS),
433 (unsigned long long)csr);
435 PCICTL_WRITE8(sc, PCR_CS, csr);
437 dr &= ~DIAG_ISYNC_DIS;
439 device_printf(dev, "PCI DR 0x%016llx -> 0x%016llx\n",
440 (unsigned long long)PCICTL_READ8(sc, PCR_DIAG),
441 (unsigned long long)dr);
443 PCICTL_WRITE8(sc, PCR_DIAG, dr);
445 if (sc->sc_mode == PSYCHO_MODE_SABRE) {
446 /* Use the PROM preset for now. */
447 csr = PCICTL_READ8(sc, PCR_TAS);
449 panic("%s: Hummingbird/Sabre TAS not initialized.",
451 dvmabase = (ffs(csr) - 1) << PCITAS_ADDR_SHIFT;
455 /* Initialize memory and I/O rmans. */
456 sc->sc_pci_io_rman.rm_type = RMAN_ARRAY;
457 sc->sc_pci_io_rman.rm_descr = "Psycho PCI I/O Ports";
458 if (rman_init(&sc->sc_pci_io_rman) != 0 ||
459 rman_manage_region(&sc->sc_pci_io_rman, 0, PSYCHO_IO_SIZE) != 0)
460 panic("%s: failed to set up I/O rman", __func__);
461 sc->sc_pci_mem_rman.rm_type = RMAN_ARRAY;
462 sc->sc_pci_mem_rman.rm_descr = "Psycho PCI Memory";
463 if (rman_init(&sc->sc_pci_mem_rman) != 0 ||
464 rman_manage_region(&sc->sc_pci_mem_rman, 0, PSYCHO_MEM_SIZE) != 0)
465 panic("%s: failed to set up memory rman", __func__);
467 i = OF_getprop_alloc(node, "ranges", sizeof(*range), (void **)&range);
469 * Make sure that the expected ranges are present. The
470 * OFW_PCI_CS_MEM64 one is not currently used though.
472 if (i != PSYCHO_NRANGE)
473 panic("%s: unsupported number of ranges", __func__);
475 * Find the addresses of the various bus spaces.
476 * There should not be multiple ones of one kind.
477 * The physical start addresses of the ranges are the configuration,
478 * memory and I/O handles.
480 for (i = 0; i < PSYCHO_NRANGE; i++) {
481 j = OFW_PCI_RANGE_CS(&range[i]);
482 if (sc->sc_pci_bh[j] != 0)
483 panic("%s: duplicate range for space %d",
485 sc->sc_pci_bh[j] = OFW_PCI_RANGE_PHYS(&range[i]);
487 free(range, M_OFWPROP);
489 /* Register the softc, this is needed for paired Psychos. */
490 SLIST_INSERT_HEAD(&psycho_softcs, sc, sc_link);
493 * If we're a Hummingbird/Sabre or the first of a pair of Psychos
494 * to arrive here, do the interrupt setup and start up the IOMMU.
498 * Hunt through all the interrupt mapping regs and register
499 * our interrupt controller for the corresponding interrupt
500 * vectors. We do this early in order to be able to catch
503 for (i = 0; i <= PSYCHO_MAX_INO; i++) {
504 if (psycho_find_intrmap(sc, i, &intrmap, &intrclr,
507 pica = malloc(sizeof(*pica), M_DEVBUF, M_NOWAIT);
509 panic("%s: could not allocate interrupt "
510 "controller argument", __func__);
512 pica->pica_map = intrmap;
513 pica->pica_clr = intrclr;
516 * Enable all interrupts and clear all interrupt
517 * states. This aids the debugging of interrupt
521 "intr map (INO %d, %s) %#lx: %#lx, clr: %#lx\n",
522 i, intrmap <= PSR_PCIB3_INT_MAP ? "PCI" : "OBIO",
523 (u_long)intrmap, (u_long)PSYCHO_READ8(sc,
524 intrmap), (u_long)intrclr);
525 PSYCHO_WRITE8(sc, intrmap, INTMAP_VEC(sc->sc_ign, i));
526 PSYCHO_WRITE8(sc, intrclr, INTCLR_IDLE);
527 PSYCHO_WRITE8(sc, intrmap,
528 INTMAP_ENABLE(INTMAP_VEC(sc->sc_ign, i),
531 j = intr_controller_register(INTMAP_VEC(sc->sc_ign,
532 i), &psycho_ic, pica);
534 device_printf(dev, "could not register "
535 "interrupt controller for INO %d (%d)\n",
539 if (sc->sc_mode == PSYCHO_MODE_PSYCHO)
540 sparc64_counter_init(device_get_nameunit(dev),
541 rman_get_bustag(sc->sc_mem_res),
542 rman_get_bushandle(sc->sc_mem_res), PSR_TC0);
545 * Set up IOMMU and PCI configuration if we're the first
546 * of a pair of Psychos to arrive here or a Hummingbird
549 * We should calculate a TSB size based on amount of RAM
550 * and number of bus controllers and number and type of
553 * For the moment, 32KB should be more than enough.
555 sc->sc_is = malloc(sizeof(struct iommu_state), M_DEVBUF,
557 if (sc->sc_is == NULL)
558 panic("%s: malloc iommu_state failed", __func__);
559 sc->sc_is->is_flags = IOMMU_PRESERVE_PROM;
560 if (sc->sc_mode == PSYCHO_MODE_SABRE)
561 sc->sc_is->is_pmaxaddr =
562 IOMMU_MAXADDR(SABRE_IOMMU_BITS);
564 sc->sc_is->is_pmaxaddr =
565 IOMMU_MAXADDR(PSYCHO_IOMMU_BITS);
566 sc->sc_is->is_sb[0] = sc->sc_is->is_sb[1] = 0;
567 if (OF_getproplen(node, "no-streaming-cache") < 0)
568 sc->sc_is->is_sb[0] = sc->sc_pcictl + PCR_STRBUF;
569 sc->sc_is->is_flags |= (rerun != 1) ? IOMMU_RERUN_DISABLE : 0;
570 psycho_iommu_init(sc, 3, dvmabase);
572 /* Just copy IOMMU state, config tag and address. */
573 sc->sc_is = osc->sc_is;
574 if (OF_getproplen(node, "no-streaming-cache") < 0)
575 sc->sc_is->is_sb[1] = sc->sc_pcictl + PCR_STRBUF;
576 iommu_reset(sc->sc_is);
579 /* Allocate our tags. */
580 sc->sc_pci_memt = psycho_alloc_bus_tag(sc, PCI_MEMORY_BUS_SPACE);
581 sc->sc_pci_iot = psycho_alloc_bus_tag(sc, PCI_IO_BUS_SPACE);
582 sc->sc_pci_cfgt = psycho_alloc_bus_tag(sc, PCI_CONFIG_BUS_SPACE);
583 if (bus_dma_tag_create(bus_get_dma_tag(dev), 8, 0,
584 sc->sc_is->is_pmaxaddr, ~0, NULL, NULL, sc->sc_is->is_pmaxaddr,
585 0xff, 0xffffffff, 0, NULL, NULL, &sc->sc_pci_dmat) != 0)
586 panic("%s: bus_dma_tag_create failed", __func__);
587 /* Customize the tag. */
588 sc->sc_pci_dmat->dt_cookie = sc->sc_is;
589 sc->sc_pci_dmat->dt_mt = &iommu_dma_methods;
591 i = OF_getprop(node, "bus-range", (void *)prop_array,
594 panic("%s: could not get bus-range", __func__);
595 if (i != sizeof(prop_array))
596 panic("%s: broken bus-range (%d)", __func__, i);
597 sc->sc_pci_secbus = prop_array[0];
598 sc->sc_pci_subbus = prop_array[1];
600 device_printf(dev, "bus range %u to %u; PCI bus %d\n",
601 sc->sc_pci_secbus, sc->sc_pci_subbus, sc->sc_pci_secbus);
603 /* Clear any pending PCI error bits. */
604 PCIB_WRITE_CONFIG(dev, sc->sc_pci_secbus, PCS_DEVICE, PCS_FUNC,
605 PCIR_STATUS, PCIB_READ_CONFIG(dev, sc->sc_pci_secbus,
606 PCS_DEVICE, PCS_FUNC, PCIR_STATUS, 2), 2);
607 PCICTL_WRITE8(sc, PCR_CS, PCICTL_READ8(sc, PCR_CS));
608 PCICTL_WRITE8(sc, PCR_AFS, PCICTL_READ8(sc, PCR_AFS));
612 * Establish handlers for interesting interrupts...
614 * XXX We need to remember these and remove this to support
615 * hotplug on the UPA/FHC bus.
617 * XXX Not all controllers have these, but installing them
618 * is better than trying to sort through this mess.
620 psycho_set_intr(sc, 1, PSR_UE_INT_MAP, psycho_ue, NULL);
621 psycho_set_intr(sc, 2, PSR_CE_INT_MAP, psycho_ce, NULL);
622 #ifdef DEBUGGER_ON_POWERFAIL
623 psycho_set_intr(sc, 3, PSR_POWER_INT_MAP, psycho_powerfail,
626 psycho_set_intr(sc, 3, PSR_POWER_INT_MAP, NULL,
627 (driver_intr_t *)psycho_powerfail);
629 if (sc->sc_mode == PSYCHO_MODE_PSYCHO) {
631 * Hummingbirds/Sabres do not have the following two
636 * The spare hardware interrupt is used for the
637 * over-temperature interrupt.
639 psycho_set_intr(sc, 4, PSR_SPARE_INT_MAP,
640 NULL, psycho_overtemp);
641 #ifdef PSYCHO_MAP_WAKEUP
643 * psycho_wakeup() doesn't do anything useful right
646 psycho_set_intr(sc, 5, PSR_PWRMGT_INT_MAP,
647 psycho_wakeup, NULL);
648 #endif /* PSYCHO_MAP_WAKEUP */
652 * Register a PCI bus error interrupt handler according to which
653 * half this is. Hummingbird/Sabre don't have a PCI bus B error
654 * interrupt but they are also only used for PCI bus A.
656 psycho_set_intr(sc, 0, sc->sc_half == 0 ? PSR_PCIAERR_INT_MAP :
657 PSR_PCIBERR_INT_MAP, psycho_pci_bus, NULL);
660 * Set the latency timer register as this isn't always done by the
663 PCIB_WRITE_CONFIG(dev, sc->sc_pci_secbus, PCS_DEVICE, PCS_FUNC,
664 PCIR_LATTIMER, OFW_PCI_LATENCY, 1);
666 for (i = PCIR_VENDOR; i < PCIR_STATUS; i += sizeof(uint16_t))
667 le16enc(&sc->sc_pci_hpbcfg[i], bus_space_read_2(
668 sc->sc_pci_cfgt, sc->sc_pci_bh[OFW_PCI_CS_CONFIG],
669 PSYCHO_CONF_OFF(sc->sc_pci_secbus, PCS_DEVICE,
671 for (i = PCIR_REVID; i <= PCIR_BIST; i += sizeof(uint8_t))
672 sc->sc_pci_hpbcfg[i] = bus_space_read_1(sc->sc_pci_cfgt,
673 sc->sc_pci_bh[OFW_PCI_CS_CONFIG], PSYCHO_CONF_OFF(
674 sc->sc_pci_secbus, PCS_DEVICE, PCS_FUNC, i));
676 ofw_bus_setup_iinfo(node, &sc->sc_pci_iinfo, sizeof(ofw_pci_intr_t));
678 * On E250 the interrupt map entry for the EBus bridge is wrong,
679 * causing incorrect interrupts to be assigned to some devices on
680 * the EBus. Work around it by changing our copy of the interrupt
681 * map mask to perform a full comparison of the INO. That way
682 * the interrupt map entry for the EBus bridge won't match at all
683 * and the INOs specified in the "interrupts" properties of the
684 * EBus devices will be used directly instead.
686 if (strcmp(sparc64_model, "SUNW,Ultra-250") == 0 &&
687 sc->sc_pci_iinfo.opi_imapmsk != NULL)
688 *(ofw_pci_intr_t *)(&sc->sc_pci_iinfo.opi_imapmsk[
689 sc->sc_pci_iinfo.opi_addrc]) = INTMAP_INO_MASK;
691 device_add_child(dev, "pci", -1);
692 return (bus_generic_attach(dev));
696 psycho_set_intr(struct psycho_softc *sc, u_int index, bus_addr_t intrmap,
697 driver_filter_t filt, driver_intr_t intr)
703 sc->sc_irq_res[index] = bus_alloc_resource_any(sc->sc_dev,
704 SYS_RES_IRQ, &rid, RF_ACTIVE);
705 if (sc->sc_irq_res[index] == NULL && intrmap >= PSR_POWER_INT_MAP) {
707 * These interrupts aren't mandatory and not available
708 * with all controllers (not even Psychos).
712 if (sc->sc_irq_res[index] == NULL ||
713 INTIGN(vec = rman_get_start(sc->sc_irq_res[index])) !=
715 INTVEC(PSYCHO_READ8(sc, intrmap)) != vec ||
716 intr_vectors[vec].iv_ic != &psycho_ic ||
717 bus_setup_intr(sc->sc_dev, sc->sc_irq_res[index],
718 INTR_TYPE_MISC | INTR_FAST, filt, intr, sc,
719 &sc->sc_ihand[index]) != 0)
720 panic("%s: failed to set up interrupt %d", __func__, index);
724 psycho_find_intrmap(struct psycho_softc *sc, u_int ino,
725 bus_addr_t *intrmapptr, bus_addr_t *intrclrptr, bus_addr_t *intrdiagptr)
727 bus_addr_t intrclr, intrmap;
732 * XXX we only compare INOs rather than INRs since the firmware may
733 * not provide the IGN and the IGN is constant for all devices on
734 * that PCI controller.
735 * This could cause problems for the FFB/external interrupt which
736 * has a full vector that can be set arbitrarily.
739 if (ino > PSYCHO_MAX_INO) {
740 device_printf(sc->sc_dev, "out of range INO %d requested\n",
746 /* Hunt through OBIO first. */
747 diag = PSYCHO_READ8(sc, PSR_OBIO_INT_DIAG);
748 for (intrmap = PSR_SCSI_INT_MAP, intrclr = PSR_SCSI_INT_CLR;
749 intrmap <= PSR_PWRMGT_INT_MAP; intrmap += 8, intrclr += 8,
751 if (sc->sc_mode == PSYCHO_MODE_SABRE &&
752 (intrmap == PSR_TIMER0_INT_MAP ||
753 intrmap == PSR_TIMER1_INT_MAP ||
754 intrmap == PSR_PCIBERR_INT_MAP ||
755 intrmap == PSR_PWRMGT_INT_MAP))
757 if (INTINO(PSYCHO_READ8(sc, intrmap)) == ino) {
765 diag = PSYCHO_READ8(sc, PSR_PCI_INT_DIAG);
766 /* Now do PCI interrupts. */
767 for (intrmap = PSR_PCIA0_INT_MAP, intrclr = PSR_PCIA0_INT_CLR;
768 intrmap <= PSR_PCIB3_INT_MAP; intrmap += 8, intrclr += 32,
770 if (sc->sc_mode == PSYCHO_MODE_PSYCHO &&
771 (intrmap == PSR_PCIA2_INT_MAP ||
772 intrmap == PSR_PCIA3_INT_MAP))
774 if (((PSYCHO_READ8(sc, intrmap) ^ ino) & 0x3c) == 0) {
775 intrclr += 8 * (ino & 3);
776 diag = (diag >> ((ino & 3) * 2)) & 2;
782 if (intrmapptr != NULL)
783 *intrmapptr = intrmap;
784 if (intrclrptr != NULL)
785 *intrclrptr = intrclr;
786 if (intrdiagptr != NULL)
797 struct psycho_softc *sc = arg;
800 afar = PSYCHO_READ8(sc, PSR_UE_AFA);
801 afsr = PSYCHO_READ8(sc, PSR_UE_AFS);
803 * On the UltraSPARC-IIi/IIe, IOMMU misses/protection faults cause
804 * the AFAR to be set to the physical address of the TTE entry that
805 * was invalid/write protected. Call into the IOMMU code to have
806 * them decoded to virtual I/O addresses.
808 if ((afsr & UEAFSR_P_DTE) != 0)
809 iommu_decode_fault(sc->sc_is, afar);
810 panic("%s: uncorrectable DMA error AFAR %#lx AFSR %#lx",
811 device_get_nameunit(sc->sc_dev), (u_long)afar, (u_long)afsr);
812 return (FILTER_HANDLED);
818 struct psycho_softc *sc = arg;
821 mtx_lock_spin(sc->sc_mtx);
822 afar = PSYCHO_READ8(sc, PSR_CE_AFA);
823 afsr = PSYCHO_READ8(sc, PSR_CE_AFS);
824 device_printf(sc->sc_dev, "correctable DMA error AFAR %#lx "
825 "AFSR %#lx\n", (u_long)afar, (u_long)afsr);
826 /* Clear the error bits that we caught. */
827 PSYCHO_WRITE8(sc, PSR_CE_AFS, afsr);
828 mtx_unlock_spin(sc->sc_mtx);
829 return (FILTER_HANDLED);
833 psycho_pci_bus(void *arg)
835 struct psycho_softc *sc = arg;
838 afar = PCICTL_READ8(sc, PCR_AFA);
839 afsr = PCICTL_READ8(sc, PCR_AFS);
840 panic("%s: PCI bus %c error AFAR %#lx AFSR %#lx",
841 device_get_nameunit(sc->sc_dev), 'A' + sc->sc_half, (u_long)afar,
843 return (FILTER_HANDLED);
847 psycho_powerfail(void *arg)
849 #ifdef DEBUGGER_ON_POWERFAIL
850 struct psycho_softc *sc = arg;
852 kdb_enter(KDB_WHY_POWERFAIL, "powerfail");
856 /* As the interrupt is cleared we may be called multiple times. */
858 return (FILTER_HANDLED);
860 printf("Power Failure Detected: Shutting down NOW.\n");
863 return (FILTER_HANDLED);
867 psycho_overtemp(void *arg)
871 /* As the interrupt is cleared we may be called multiple times. */
875 printf("DANGER: OVER TEMPERATURE detected.\nShutting down NOW.\n");
876 shutdown_nice(RB_POWEROFF);
879 #ifdef PSYCHO_MAP_WAKEUP
881 psycho_wakeup(void *arg)
883 struct psycho_softc *sc = arg;
885 /* We don't really have a framework to deal with this properly. */
886 device_printf(sc->sc_dev, "power management wakeup\n");
887 return (FILTER_HANDLED);
889 #endif /* PSYCHO_MAP_WAKEUP */
892 psycho_iommu_init(struct psycho_softc *sc, int tsbsize, uint32_t dvmabase)
894 struct iommu_state *is = sc->sc_is;
896 /* Punch in our copies. */
897 is->is_bustag = rman_get_bustag(sc->sc_mem_res);
898 is->is_bushandle = rman_get_bushandle(sc->sc_mem_res);
899 is->is_iommu = PSR_IOMMU;
900 is->is_dtag = PSR_IOMMU_TLB_TAG_DIAG;
901 is->is_ddram = PSR_IOMMU_TLB_DATA_DIAG;
902 is->is_dqueue = PSR_IOMMU_QUEUE_DIAG;
903 is->is_dva = PSR_IOMMU_SVADIAG;
904 is->is_dtcmp = PSR_IOMMU_TLB_CMP_DIAG;
906 iommu_init(device_get_nameunit(sc->sc_dev), is, tsbsize, dvmabase, 0);
910 psycho_maxslots(device_t dev)
913 /* XXX: is this correct? */
914 return (PCI_SLOTMAX);
918 psycho_read_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg,
921 struct psycho_softc *sc;
922 bus_space_handle_t bh;
929 sc = device_get_softc(dev);
930 if (bus < sc->sc_pci_secbus || bus > sc->sc_pci_subbus ||
931 slot > PCI_SLOTMAX || func > PCI_FUNCMAX || reg > PCI_REGMAX)
934 bh = sc->sc_pci_bh[OFW_PCI_CS_CONFIG];
937 * The Hummingbird and Sabre bridges are picky in that they
938 * only allow their config space to be accessed using the
939 * "native" width of the respective register being accessed
940 * and return semi-random other content of their config space
941 * otherwise. Given that the PCI specs don't say anything
942 * about such a (unusual) limitation and lots of stuff expects
943 * to be able to access the contents of the config space at
944 * any width we allow just that. We do this by using a copy
945 * of the header of the bridge (the rest is all zero anyway)
946 * read during attach (expect for PCIR_STATUS) in order to
948 * The Psycho bridges contain a dupe of their header at 0x80
949 * which we nullify that way also.
951 if (bus == sc->sc_pci_secbus && slot == PCS_DEVICE &&
953 if (offset % width != 0)
956 if (reg >= sizeof(sc->sc_pci_hpbcfg))
959 if ((reg < PCIR_STATUS && reg + width > PCIR_STATUS) ||
960 reg == PCIR_STATUS || reg == PCIR_STATUS + 1)
961 le16enc(&sc->sc_pci_hpbcfg[PCIR_STATUS],
962 bus_space_read_2(sc->sc_pci_cfgt, bh,
963 PSYCHO_CONF_OFF(sc->sc_pci_secbus,
964 PCS_DEVICE, PCS_FUNC, PCIR_STATUS)));
968 return (sc->sc_pci_hpbcfg[reg]);
970 return (le16dec(&sc->sc_pci_hpbcfg[reg]));
972 return (le32dec(&sc->sc_pci_hpbcfg[reg]));
976 offset = PSYCHO_CONF_OFF(bus, slot, func, reg);
979 i = bus_space_peek_1(sc->sc_pci_cfgt, bh, offset, &byte);
983 i = bus_space_peek_2(sc->sc_pci_cfgt, bh, offset, &shrt);
987 i = bus_space_peek_4(sc->sc_pci_cfgt, bh, offset, &wrd);
991 panic("%s: bad width", __func__);
997 printf("%s: read data error reading: %d.%d.%d: 0x%x\n",
998 __func__, bus, slot, func, reg);
1006 psycho_write_config(device_t dev, u_int bus, u_int slot, u_int func,
1007 u_int reg, uint32_t val, int width)
1009 struct psycho_softc *sc;
1010 bus_space_handle_t bh;
1013 sc = device_get_softc(dev);
1014 if (bus < sc->sc_pci_secbus || bus > sc->sc_pci_subbus ||
1015 slot > PCI_SLOTMAX || func > PCI_FUNCMAX || reg > PCI_REGMAX)
1018 offset = PSYCHO_CONF_OFF(bus, slot, func, reg);
1019 bh = sc->sc_pci_bh[OFW_PCI_CS_CONFIG];
1022 bus_space_write_1(sc->sc_pci_cfgt, bh, offset, val);
1025 bus_space_write_2(sc->sc_pci_cfgt, bh, offset, val);
1028 bus_space_write_4(sc->sc_pci_cfgt, bh, offset, val);
1031 panic("%s: bad width", __func__);
1037 psycho_route_interrupt(device_t bridge, device_t dev, int pin)
1039 struct psycho_softc *sc;
1040 struct ofw_pci_register reg;
1042 ofw_pci_intr_t pintr, mintr;
1043 uint8_t maskbuf[sizeof(reg) + sizeof(pintr)];
1045 sc = device_get_softc(bridge);
1047 if (ofw_bus_lookup_imap(ofw_bus_get_node(dev), &sc->sc_pci_iinfo,
1048 ®, sizeof(reg), &pintr, sizeof(pintr), &mintr, sizeof(mintr),
1052 * If this is outside of the range for an intpin, it's likely a full
1053 * INO, and no mapping is required at all; this happens on the U30,
1054 * where there's no interrupt map at the Psycho node. Fortunately,
1055 * there seem to be no INOs in the intpin range on this boxen, so
1056 * this easy heuristics will do.
1061 * Guess the INO; we always assume that this is a non-OBIO
1062 * device, and that pin is a "real" intpin number. Determine
1063 * the mapping register to be used by the slot number.
1064 * We only need to do this on E450s, it seems; here, the slot numbers
1065 * for bus A are one-based, while those for bus B seemingly have an
1066 * offset of 2 (hence the factor of 3 below).
1068 intrmap = PSR_PCIA0_INT_MAP +
1069 8 * (pci_get_slot(dev) - 1 + 3 * sc->sc_half);
1070 mintr = INTINO(PSYCHO_READ8(sc, intrmap)) + pin - 1;
1071 device_printf(bridge,
1072 "guessing interrupt %d for device %d.%d pin %d\n",
1073 (int)mintr, pci_get_slot(dev), pci_get_function(dev), pin);
1078 psycho_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
1080 struct psycho_softc *sc;
1082 sc = device_get_softc(dev);
1084 case PCIB_IVAR_DOMAIN:
1085 *result = device_get_unit(dev);
1088 *result = sc->sc_pci_secbus;
1095 psycho_dma_sync_stub(void *arg)
1097 struct psycho_dma_sync *pds = arg;
1099 (void)PCIB_READ_CONFIG(pds->pds_ppb, pds->pds_bus, pds->pds_slot,
1100 pds->pds_func, PCIR_VENDOR, 2);
1101 (void)PSYCHO_READ8(pds->pds_sc, PSR_DMA_WRITE_SYNC);
1102 return (pds->pds_handler(pds->pds_arg));
1106 psycho_intr_enable(void *arg)
1108 struct intr_vector *iv = arg;
1109 struct psycho_icarg *pica = iv->iv_icarg;
1111 PSYCHO_WRITE8(pica->pica_sc, pica->pica_map,
1112 INTMAP_ENABLE(iv->iv_vec, iv->iv_mid));
1116 psycho_intr_disable(void *arg)
1118 struct intr_vector *iv = arg;
1119 struct psycho_icarg *pica = iv->iv_icarg;
1121 PSYCHO_WRITE8(pica->pica_sc, pica->pica_map, iv->iv_vec);
1125 psycho_intr_assign(void *arg)
1127 struct intr_vector *iv = arg;
1128 struct psycho_icarg *pica = iv->iv_icarg;
1130 PSYCHO_WRITE8(pica->pica_sc, pica->pica_map, INTMAP_TID(
1131 PSYCHO_READ8(pica->pica_sc, pica->pica_map), iv->iv_mid));
1135 psycho_intr_clear(void *arg)
1137 struct intr_vector *iv = arg;
1138 struct psycho_icarg *pica = iv->iv_icarg;
1140 PSYCHO_WRITE8(pica->pica_sc, pica->pica_clr, INTCLR_IDLE);
1144 psycho_setup_intr(device_t dev, device_t child, struct resource *ires,
1145 int flags, driver_filter_t *filt, driver_intr_t *intr, void *arg,
1152 devclass_t pci_devclass;
1153 device_t cdev, pdev, pcidev;
1154 struct psycho_softc *sc;
1155 struct psycho_dma_sync *pds;
1159 sc = device_get_softc(dev);
1161 * Make sure the vector is fully specified and we registered
1162 * our interrupt controller for it.
1164 vec = rman_get_start(ires);
1165 if (INTIGN(vec) != sc->sc_ign ||
1166 intr_vectors[vec].iv_ic != &psycho_ic) {
1167 device_printf(dev, "invalid interrupt vector 0x%lx\n", vec);
1172 * The Sabre-APB-combination does not automatically flush DMA
1173 * write data for devices behind additional PCI-PCI bridges
1174 * underneath the APB PCI-PCI bridge. The procedure for a
1175 * manual flush is to do a PIO read on the far side of the
1176 * farthest PCI-PCI bridge followed by a read of the PCI DMA
1177 * write sync register of the Sabre.
1179 if (sc->sc_mode == PSYCHO_MODE_SABRE) {
1180 pds = malloc(sizeof(*pds), M_DEVBUF, M_NOWAIT | M_ZERO);
1184 found.apb = found.ppb = 0;
1185 pci_devclass = devclass_find("pci");
1186 for (cdev = child; cdev != dev; cdev = pdev) {
1187 pdev = device_get_parent(cdev);
1188 if (pcidev == NULL) {
1189 if (device_get_devclass(pdev) != pci_devclass)
1195 * NB: APB would also match as PCI-PCI bridges.
1197 if (pci_get_vendor(cdev) == 0x108e &&
1198 pci_get_device(cdev) == 0x5000) {
1202 if (pci_get_class(cdev) == PCIC_BRIDGE &&
1203 pci_get_subclass(cdev) == PCIS_BRIDGE_PCI)
1206 if (found.apb && found.ppb && pcidev != NULL) {
1210 device_get_parent(device_get_parent(pcidev));
1211 pds->pds_bus = pci_get_bus(pcidev);
1212 pds->pds_slot = pci_get_slot(pcidev);
1213 pds->pds_func = pci_get_function(pcidev);
1215 device_printf(dev, "installed DMA sync "
1216 "wrapper for device %d.%d on bus %d\n",
1217 pds->pds_slot, pds->pds_func,
1220 pds->pds_handler = filt;
1221 error = bus_generic_setup_intr(dev, child,
1222 ires, flags, psycho_dma_sync_stub, intr,
1225 pds->pds_handler = (driver_filter_t *)intr;
1226 error = bus_generic_setup_intr(dev, child,
1228 (driver_intr_t *)psycho_dma_sync_stub,
1232 error = bus_generic_setup_intr(dev, child, ires,
1233 flags, filt, intr, arg, cookiep);
1235 free(pds, M_DEVBUF);
1238 pds->pds_cookie = *cookiep;
1242 return (bus_generic_setup_intr(dev, child, ires, flags, filt, intr,
1247 psycho_teardown_intr(device_t dev, device_t child, struct resource *vec,
1250 struct psycho_softc *sc;
1251 struct psycho_dma_sync *pds;
1254 sc = device_get_softc(dev);
1255 if (sc->sc_mode == PSYCHO_MODE_SABRE) {
1257 error = bus_generic_teardown_intr(dev, child, vec,
1260 free(pds, M_DEVBUF);
1263 return (bus_generic_teardown_intr(dev, child, vec, cookie));
1267 psycho_describe_intr(device_t dev, device_t child, struct resource *vec,
1268 void *cookie, const char *descr)
1270 struct psycho_softc *sc;
1272 sc = device_get_softc(dev);
1273 if (sc->sc_mode == PSYCHO_MODE_SABRE)
1274 cookie = ((struct psycho_dma_sync *)cookie)->pds_cookie;
1275 return (bus_generic_describe_intr(dev, child, vec, cookie, descr));
1278 static struct resource *
1279 psycho_alloc_resource(device_t bus, device_t child, int type, int *rid,
1280 u_long start, u_long end, u_long count, u_int flags)
1282 struct psycho_softc *sc;
1283 struct resource *rv;
1286 bus_space_handle_t bh;
1287 int needactivate = flags & RF_ACTIVE;
1289 flags &= ~RF_ACTIVE;
1291 sc = device_get_softc(bus);
1292 if (type == SYS_RES_IRQ) {
1294 * XXX: Don't accept blank ranges for now, only single
1295 * interrupts. The other case should not happen with
1296 * the MI PCI code...
1297 * XXX: This may return a resource that is out of the
1298 * range that was specified. Is this correct...?
1301 panic("%s: XXX: interrupt range", __func__);
1302 start = end = INTMAP_VEC(sc->sc_ign, end);
1303 return (BUS_ALLOC_RESOURCE(device_get_parent(bus), child,
1304 type, rid, start, end, count, flags));
1307 case SYS_RES_MEMORY:
1308 rm = &sc->sc_pci_mem_rman;
1309 bt = sc->sc_pci_memt;
1310 bh = sc->sc_pci_bh[OFW_PCI_CS_MEM32];
1312 case SYS_RES_IOPORT:
1313 rm = &sc->sc_pci_io_rman;
1314 bt = sc->sc_pci_iot;
1315 bh = sc->sc_pci_bh[OFW_PCI_CS_IO];
1322 rv = rman_reserve_resource(rm, start, end, count, flags, child);
1325 rman_set_rid(rv, *rid);
1326 bh += rman_get_start(rv);
1327 rman_set_bustag(rv, bt);
1328 rman_set_bushandle(rv, bh);
1331 if (bus_activate_resource(child, type, *rid, rv)) {
1332 rman_release_resource(rv);
1340 psycho_activate_resource(device_t bus, device_t child, int type, int rid,
1346 if (type == SYS_RES_IRQ)
1347 return (BUS_ACTIVATE_RESOURCE(device_get_parent(bus), child,
1349 if (type == SYS_RES_MEMORY) {
1351 * Need to memory-map the device space, as some drivers
1352 * depend on the virtual address being set and usable.
1354 error = sparc64_bus_mem_map(rman_get_bustag(r),
1355 rman_get_bushandle(r), rman_get_size(r), 0, 0, &p);
1358 rman_set_virtual(r, p);
1360 return (rman_activate_resource(r));
1364 psycho_deactivate_resource(device_t bus, device_t child, int type, int rid,
1368 if (type == SYS_RES_IRQ)
1369 return (BUS_DEACTIVATE_RESOURCE(device_get_parent(bus), child,
1371 if (type == SYS_RES_MEMORY) {
1372 sparc64_bus_mem_unmap(rman_get_virtual(r), rman_get_size(r));
1373 rman_set_virtual(r, NULL);
1375 return (rman_deactivate_resource(r));
1379 psycho_release_resource(device_t bus, device_t child, int type, int rid,
1384 if (type == SYS_RES_IRQ)
1385 return (BUS_RELEASE_RESOURCE(device_get_parent(bus), child,
1387 if (rman_get_flags(r) & RF_ACTIVE) {
1388 error = bus_deactivate_resource(child, type, rid, r);
1392 return (rman_release_resource(r));
1395 static bus_dma_tag_t
1396 psycho_get_dma_tag(device_t bus, device_t child)
1398 struct psycho_softc *sc;
1400 sc = device_get_softc(bus);
1401 return (sc->sc_pci_dmat);
1405 psycho_get_node(device_t bus, device_t dev)
1407 struct psycho_softc *sc;
1409 sc = device_get_softc(bus);
1410 /* We only have one child, the PCI bus, which needs our own node. */
1411 return (sc->sc_node);
1414 static bus_space_tag_t
1415 psycho_alloc_bus_tag(struct psycho_softc *sc, int type)
1419 bt = malloc(sizeof(struct bus_space_tag), M_DEVBUF,
1422 panic("%s: out of memory", __func__);
1424 bt->bst_cookie = sc;
1425 bt->bst_parent = rman_get_bustag(sc->sc_mem_res);
1426 bt->bst_type = type;