2 * Copyright (c) 1999, 2000 Matthew R. Green
3 * Copyright (c) 2001 - 2003 by Thomas Moestl <tmm@FreeBSD.org>
4 * Copyright (c) 2005, 2007, 2008 by Marius Strobl <marius@FreeBSD.org>
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. The name of the author may not be used to endorse or promote products
16 * derived from this software without specific prior written permission.
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
23 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
24 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
25 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
26 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 * from: NetBSD: psycho.c,v 1.39 2001/10/07 20:30:41 eeh Exp
31 * from: FreeBSD: psycho.c 183152 2008-09-18 19:45:22Z marius
34 #include <sys/cdefs.h>
35 __FBSDID("$FreeBSD$");
38 * Driver for `Schizo' Fireplane/Safari to PCI 2.1 and `Tomatillo' JBus to
42 #include "opt_ofw_pci.h"
43 #include "opt_schizo.h"
45 #include <sys/param.h>
46 #include <sys/systm.h>
48 #include <sys/kernel.h>
50 #include <sys/malloc.h>
51 #include <sys/module.h>
52 #include <sys/mutex.h>
55 #include <sys/sysctl.h>
57 #include <sys/timetc.h>
59 #include <dev/ofw/ofw_bus.h>
60 #include <dev/ofw/ofw_pci.h>
61 #include <dev/ofw/openfirm.h>
63 #include <machine/bus.h>
64 #include <machine/bus_common.h>
65 #include <machine/bus_private.h>
66 #include <machine/fsr.h>
67 #include <machine/iommureg.h>
68 #include <machine/iommuvar.h>
69 #include <machine/resource.h>
71 #include <dev/pci/pcireg.h>
72 #include <dev/pci/pcivar.h>
74 #include <sparc64/pci/ofw_pci.h>
75 #include <sparc64/pci/schizoreg.h>
76 #include <sparc64/pci/schizovar.h>
80 static const struct schizo_desc *schizo_get_desc(device_t);
81 static void schizo_set_intr(struct schizo_softc *, u_int, u_int,
83 static driver_filter_t schizo_dma_sync_stub;
84 static driver_filter_t ichip_dma_sync_stub;
85 static void schizo_intr_enable(void *);
86 static void schizo_intr_disable(void *);
87 static void schizo_intr_assign(void *);
88 static void schizo_intr_clear(void *);
89 static int schizo_intr_register(struct schizo_softc *sc, u_int ino);
90 static int schizo_get_intrmap(struct schizo_softc *, u_int,
91 bus_addr_t *, bus_addr_t *);
92 static bus_space_tag_t schizo_alloc_bus_tag(struct schizo_softc *, int);
93 static timecounter_get_t schizo_get_timecount;
95 /* Interrupt handlers */
96 static driver_filter_t schizo_pci_bus;
97 static driver_filter_t schizo_ue;
98 static driver_filter_t schizo_ce;
99 static driver_filter_t schizo_host_bus;
100 static driver_filter_t schizo_cdma;
103 static void schizo_iommu_init(struct schizo_softc *, int, uint32_t);
108 static device_probe_t schizo_probe;
109 static device_attach_t schizo_attach;
110 static bus_read_ivar_t schizo_read_ivar;
111 static bus_setup_intr_t schizo_setup_intr;
112 static bus_teardown_intr_t schizo_teardown_intr;
113 static bus_alloc_resource_t schizo_alloc_resource;
114 static bus_activate_resource_t schizo_activate_resource;
115 static bus_deactivate_resource_t schizo_deactivate_resource;
116 static bus_release_resource_t schizo_release_resource;
117 static bus_describe_intr_t schizo_describe_intr;
118 static bus_get_dma_tag_t schizo_get_dma_tag;
119 static pcib_maxslots_t schizo_maxslots;
120 static pcib_read_config_t schizo_read_config;
121 static pcib_write_config_t schizo_write_config;
122 static pcib_route_interrupt_t schizo_route_interrupt;
123 static ofw_bus_get_node_t schizo_get_node;
125 static device_method_t schizo_methods[] = {
126 /* Device interface */
127 DEVMETHOD(device_probe, schizo_probe),
128 DEVMETHOD(device_attach, schizo_attach),
129 DEVMETHOD(device_shutdown, bus_generic_shutdown),
130 DEVMETHOD(device_suspend, bus_generic_suspend),
131 DEVMETHOD(device_resume, bus_generic_resume),
134 DEVMETHOD(bus_print_child, bus_generic_print_child),
135 DEVMETHOD(bus_read_ivar, schizo_read_ivar),
136 DEVMETHOD(bus_setup_intr, schizo_setup_intr),
137 DEVMETHOD(bus_teardown_intr, schizo_teardown_intr),
138 DEVMETHOD(bus_alloc_resource, schizo_alloc_resource),
139 DEVMETHOD(bus_activate_resource, schizo_activate_resource),
140 DEVMETHOD(bus_deactivate_resource, schizo_deactivate_resource),
141 DEVMETHOD(bus_release_resource, schizo_release_resource),
142 DEVMETHOD(bus_describe_intr, schizo_describe_intr),
143 DEVMETHOD(bus_get_dma_tag, schizo_get_dma_tag),
146 DEVMETHOD(pcib_maxslots, schizo_maxslots),
147 DEVMETHOD(pcib_read_config, schizo_read_config),
148 DEVMETHOD(pcib_write_config, schizo_write_config),
149 DEVMETHOD(pcib_route_interrupt, schizo_route_interrupt),
151 /* ofw_bus interface */
152 DEVMETHOD(ofw_bus_get_node, schizo_get_node),
157 static devclass_t schizo_devclass;
159 DEFINE_CLASS_0(pcib, schizo_driver, schizo_methods,
160 sizeof(struct schizo_softc));
161 DRIVER_MODULE(schizo, nexus, schizo_driver, schizo_devclass, 0, 0);
163 static SLIST_HEAD(, schizo_softc) schizo_softcs =
164 SLIST_HEAD_INITIALIZER(schizo_softcs);
166 static const struct intr_controller schizo_ic = {
173 struct schizo_icarg {
174 struct schizo_softc *sica_sc;
179 struct schizo_dma_sync {
180 struct schizo_softc *sds_sc;
181 driver_filter_t *sds_handler;
184 uint64_t sds_syncval;
185 device_t sds_ppb; /* farest PCI-PCI bridge */
186 uint8_t sds_bus; /* bus of farest PCI dev. */
187 uint8_t sds_slot; /* slot of farest PCI dev. */
188 uint8_t sds_func; /* func. of farest PCI dev. */
191 #define SCHIZO_PERF_CNT_QLTY 100
193 #define SCHIZO_SPC_READ_8(spc, sc, offs) \
194 bus_read_8((sc)->sc_mem_res[(spc)], (offs))
195 #define SCHIZO_SPC_WRITE_8(spc, sc, offs, v) \
196 bus_write_8((sc)->sc_mem_res[(spc)], (offs), (v))
198 #define SCHIZO_PCI_READ_8(sc, offs) \
199 SCHIZO_SPC_READ_8(STX_PCI, (sc), (offs))
200 #define SCHIZO_PCI_WRITE_8(sc, offs, v) \
201 SCHIZO_SPC_WRITE_8(STX_PCI, (sc), (offs), (v))
202 #define SCHIZO_CTRL_READ_8(sc, offs) \
203 SCHIZO_SPC_READ_8(STX_CTRL, (sc), (offs))
204 #define SCHIZO_CTRL_WRITE_8(sc, offs, v) \
205 SCHIZO_SPC_WRITE_8(STX_CTRL, (sc), (offs), (v))
206 #define SCHIZO_PCICFG_READ_8(sc, offs) \
207 SCHIZO_SPC_READ_8(STX_PCICFG, (sc), (offs))
208 #define SCHIZO_PCICFG_WRITE_8(sc, offs, v) \
209 SCHIZO_SPC_WRITE_8(STX_PCICFG, (sc), (offs), (v))
210 #define SCHIZO_ICON_READ_8(sc, offs) \
211 SCHIZO_SPC_READ_8(STX_ICON, (sc), (offs))
212 #define SCHIZO_ICON_WRITE_8(sc, offs, v) \
213 SCHIZO_SPC_WRITE_8(STX_ICON, (sc), (offs), (v))
216 const char *sd_string;
221 static const struct schizo_desc const schizo_compats[] = {
222 { "pci108e,8001", SCHIZO_MODE_SCZ, "Schizo" },
223 { "pci108e,a801", SCHIZO_MODE_TOM, "Tomatillo" },
227 static const struct schizo_desc *
228 schizo_get_desc(device_t dev)
230 const struct schizo_desc *desc;
233 compat = ofw_bus_get_compat(dev);
236 for (desc = schizo_compats; desc->sd_string != NULL; desc++)
237 if (strcmp(desc->sd_string, compat) == 0)
243 schizo_probe(device_t dev)
247 dtype = ofw_bus_get_type(dev);
248 if (dtype != NULL && strcmp(dtype, OFW_TYPE_PCI) == 0 &&
249 schizo_get_desc(dev) != NULL) {
250 device_set_desc(dev, "Sun Host-PCI bridge");
257 schizo_attach(device_t dev)
259 struct ofw_pci_ranges *range;
260 const struct schizo_desc *desc;
261 struct schizo_softc *asc, *sc, *osc;
262 struct timecounter *tc;
263 uint64_t ino_bitmap, reg;
265 uint32_t prop, prop_array[2];
266 int i, j, mode, rid, tsbsize;
268 sc = device_get_softc(dev);
269 node = ofw_bus_get_node(dev);
270 desc = schizo_get_desc(dev);
271 mode = desc->sd_mode;
279 * The Schizo has three register banks:
280 * (0) per-PBM PCI configuration and status registers, but for bus B
281 * shared with the UPA64s interrupt mapping register banks
282 * (1) shared Schizo controller configuration and status registers
283 * (2) per-PBM PCI configuration space
285 * The Tomatillo has four register banks:
286 * (0) per-PBM PCI configuration and status registers
287 * (1) per-PBM Tomatillo controller configuration registers, but on
288 * machines having the `jbusppm' device shared with its Estar
289 * register bank for bus A
290 * (2) per-PBM PCI configuration space
291 * (3) per-PBM interrupt concentrator registers
293 sc->sc_half = (bus_get_resource_start(dev, SYS_RES_MEMORY, STX_PCI) >>
295 for (i = 0; i < (mode == SCHIZO_MODE_SCZ ? SCZ_NREG : TOM_NREG);
298 sc->sc_mem_res[i] = bus_alloc_resource_any(dev,
299 SYS_RES_MEMORY, &rid,
300 (((mode == SCHIZO_MODE_SCZ && ((sc->sc_half == 1 &&
301 i == STX_PCI) || i == STX_CTRL)) ||
302 (mode == SCHIZO_MODE_TOM && sc->sc_half == 0 &&
303 i == STX_CTRL)) ? RF_SHAREABLE : 0) | RF_ACTIVE);
304 if (sc->sc_mem_res[i] == NULL)
305 panic("%s: could not allocate register bank %d",
310 * Match other Schizos that are already configured against
311 * the controller base physical address. This will be the
312 * same for a pair of devices that share register space.
315 SLIST_FOREACH(asc, &schizo_softcs, sc_link) {
316 if (rman_get_start(asc->sc_mem_res[STX_CTRL]) ==
317 rman_get_start(sc->sc_mem_res[STX_CTRL])) {
324 sc->sc_mtx = malloc(sizeof(*sc->sc_mtx), M_DEVBUF,
326 if (sc->sc_mtx == NULL)
327 panic("%s: could not malloc mutex", __func__);
328 mtx_init(sc->sc_mtx, "pcib_mtx", NULL, MTX_SPIN);
330 if (sc->sc_mode != SCHIZO_MODE_SCZ)
331 panic("%s: no partner expected", __func__);
332 if (mtx_initialized(osc->sc_mtx) == 0)
333 panic("%s: mutex not initialized", __func__);
334 sc->sc_mtx = osc->sc_mtx;
337 if (OF_getprop(node, "portid", &sc->sc_ign, sizeof(sc->sc_ign)) == -1)
338 panic("%s: could not determine IGN", __func__);
339 if (OF_getprop(node, "version#", &sc->sc_ver, sizeof(sc->sc_ver)) ==
341 panic("%s: could not determine version", __func__);
342 if (OF_getprop(node, "clock-frequency", &prop, sizeof(prop)) == -1)
345 device_printf(dev, "%s, version %d, IGN %#x, bus %c, %dMHz\n",
346 desc->sd_name, sc->sc_ver, sc->sc_ign, 'A' + sc->sc_half,
349 /* Set up the PCI interrupt retry timer. */
351 device_printf(dev, "PCI IRT 0x%016llx\n", (unsigned long long)
352 SCHIZO_PCI_READ_8(sc, STX_PCI_INTR_RETRY_TIM));
354 SCHIZO_PCI_WRITE_8(sc, STX_PCI_INTR_RETRY_TIM, 5);
356 /* Set up the PCI control register. */
357 reg = SCHIZO_PCI_READ_8(sc, STX_PCI_CTRL);
358 reg |= STX_PCI_CTRL_MMU_IEN | STX_PCI_CTRL_SBH_IEN |
359 STX_PCI_CTRL_ERR_IEN | STX_PCI_CTRL_ARB_MASK;
360 reg &= ~(TOM_PCI_CTRL_DTO_IEN | STX_PCI_CTRL_ARB_PARK);
361 if (OF_getproplen(node, "no-bus-parking") < 0)
362 reg |= STX_PCI_CTRL_ARB_PARK;
363 if (mode == SCHIZO_MODE_TOM) {
364 reg |= TOM_PCI_CTRL_PRM | TOM_PCI_CTRL_PRO | TOM_PCI_CTRL_PRL;
365 if (sc->sc_ver <= 1) /* revision <= 2.0 */
366 reg |= TOM_PCI_CTRL_DTO_IEN;
368 reg |= STX_PCI_CTRL_PTO;
371 device_printf(dev, "PCI CSR 0x%016llx -> 0x%016llx\n",
372 (unsigned long long)SCHIZO_PCI_READ_8(sc, STX_PCI_CTRL),
373 (unsigned long long)reg);
375 SCHIZO_PCI_WRITE_8(sc, STX_PCI_CTRL, reg);
377 /* Set up the PCI diagnostic register. */
378 reg = SCHIZO_PCI_READ_8(sc, STX_PCI_DIAG);
379 reg &= ~(SCZ_PCI_DIAG_RTRYARB_DIS | STX_PCI_DIAG_RETRY_DIS |
380 STX_PCI_DIAG_INTRSYNC_DIS);
382 device_printf(dev, "PCI DR 0x%016llx -> 0x%016llx\n",
383 (unsigned long long)SCHIZO_PCI_READ_8(sc, STX_PCI_DIAG),
384 (unsigned long long)reg);
386 SCHIZO_PCI_WRITE_8(sc, STX_PCI_DIAG, reg);
389 * Enable DMA write parity error interrupts of version >= 7 (i.e.
390 * revision >= 2.5) Schizo.
392 if (mode == SCHIZO_MODE_SCZ && sc->sc_ver >= 7) {
393 reg = SCHIZO_PCI_READ_8(sc, SX_PCI_CFG_ICD);
394 reg |= SX_PCI_CFG_ICD_DMAW_PERR_IEN;
396 device_printf(dev, "PCI CFG/ICD 0x%016llx -> 0x%016llx\n",
397 (unsigned long long)SCHIZO_PCI_READ_8(sc, SX_PCI_CFG_ICD),
398 (unsigned long long)reg);
400 SCHIZO_PCI_WRITE_8(sc, SX_PCI_CFG_ICD, reg);
404 * On Tomatillo clear the I/O prefetch lengths (workaround for a
407 if (mode == SCHIZO_MODE_TOM)
408 SCHIZO_PCI_WRITE_8(sc, TOM_PCI_IOC_CSR, TOM_PCI_IOC_PW |
409 (1 << TOM_PCI_IOC_PREF_OFF_SHIFT) | TOM_PCI_IOC_CPRM |
410 TOM_PCI_IOC_CPRO | TOM_PCI_IOC_CPRL);
413 * Hunt through all the interrupt mapping regs and register
414 * the interrupt controller for our interrupt vectors. We do
415 * this early in order to be able to catch stray interrupts.
416 * This is complicated by the fact that a pair of Schizo PBMs
419 i = OF_getprop(node, "ino-bitmap", (void *)prop_array,
422 ino_bitmap = ((uint64_t)prop_array[1] << 32) | prop_array[0];
425 * If the ino-bitmap property is missing, just provide the
426 * default set of interrupts for this controller and let
427 * schizo_setup_intr() take care of child interrupts.
429 if (sc->sc_half == 0)
430 ino_bitmap = (1ULL << STX_UE_INO) |
431 (1ULL << STX_CE_INO) |
432 (1ULL << STX_PCIERR_A_INO) |
433 (1ULL << STX_BUS_INO);
435 ino_bitmap = 1ULL << STX_PCIERR_B_INO;
437 for (i = 0; i <= STX_MAX_INO; i++) {
438 if ((ino_bitmap & (1ULL << i)) == 0)
440 if (i == STX_FB0_INO || i == STX_FB1_INO)
441 /* Leave for upa(4). */
443 j = schizo_intr_register(sc, i);
445 device_printf(dev, "could not register interrupt "
446 "controller for INO %d (%d)\n", i, j);
450 * Setup Safari/JBus performance counter 0 in bus cycle counting
451 * mode as timecounter. Unfortunately, this is broken with at
452 * least the version 4 Tomatillos found in Fire V120 and Blade
453 * 1500, which apparently actually count some different event at
454 * ~0.5 and 3MHz respectively instead (also when running in full
455 * power mode). Besides, one counter seems to be shared by a
456 * "pair" of Tomatillos, too.
458 if (sc->sc_half == 0) {
459 SCHIZO_CTRL_WRITE_8(sc, STX_CTRL_PERF,
460 (STX_CTRL_PERF_DIS << STX_CTRL_PERF_CNT1_SHIFT) |
461 (STX_CTRL_PERF_BUSCYC << STX_CTRL_PERF_CNT0_SHIFT));
462 tc = malloc(sizeof(*tc), M_DEVBUF, M_NOWAIT | M_ZERO);
464 panic("%s: could not malloc timecounter", __func__);
465 tc->tc_get_timecount = schizo_get_timecount;
466 tc->tc_poll_pps = NULL;
467 tc->tc_counter_mask = STX_CTRL_PERF_CNT_MASK;
468 if (OF_getprop(OF_peer(0), "clock-frequency", &prop,
470 panic("%s: could not determine clock frequency",
472 tc->tc_frequency = prop;
473 tc->tc_name = strdup(device_get_nameunit(dev), M_DEVBUF);
474 if (mode == SCHIZO_MODE_SCZ)
475 tc->tc_quality = SCHIZO_PERF_CNT_QLTY;
477 tc->tc_quality = -SCHIZO_PERF_CNT_QLTY;
483 * Set up the IOMMU. Schizo, Tomatillo and XMITS all have
484 * one per PBM. Schizo and XMITS additionally have a streaming
485 * buffer, in Schizo version < 5 (i.e. revision < 2.3) it's
486 * affected by several errata and basically unusable though.
488 sc->sc_is.is_flags = IOMMU_PRESERVE_PROM;
489 sc->sc_is.is_pmaxaddr = IOMMU_MAXADDR(STX_IOMMU_BITS);
490 sc->sc_is.is_sb[0] = sc->sc_is.is_sb[1] = 0;
491 if (OF_getproplen(node, "no-streaming-cache") < 0 &&
492 !(sc->sc_mode == SCHIZO_MODE_SCZ && sc->sc_ver < 5))
493 sc->sc_is.is_sb[0] = STX_PCI_STRBUF;
496 case (IOTSB_BASESZ << (x)) << (IO_PAGE_SHIFT - IOTTE_SHIFT): \
500 i = OF_getprop(node, "virtual-dma", (void *)prop_array,
502 if (i == -1 || i != sizeof(prop_array))
503 schizo_iommu_init(sc, 7, -1);
505 switch (prop_array[1]) {
515 panic("%s: unsupported DVMA size 0x%x",
516 __func__, prop_array[1]);
519 schizo_iommu_init(sc, tsbsize, prop_array[0]);
524 /* Initialize memory and I/O rmans. */
525 sc->sc_pci_io_rman.rm_type = RMAN_ARRAY;
526 sc->sc_pci_io_rman.rm_descr = "Schizo PCI I/O Ports";
527 if (rman_init(&sc->sc_pci_io_rman) != 0 ||
528 rman_manage_region(&sc->sc_pci_io_rman, 0, STX_IO_SIZE) != 0)
529 panic("%s: failed to set up I/O rman", __func__);
530 sc->sc_pci_mem_rman.rm_type = RMAN_ARRAY;
531 sc->sc_pci_mem_rman.rm_descr = "Schizo PCI Memory";
532 if (rman_init(&sc->sc_pci_mem_rman) != 0 ||
533 rman_manage_region(&sc->sc_pci_mem_rman, 0, STX_MEM_SIZE) != 0)
534 panic("%s: failed to set up memory rman", __func__);
536 i = OF_getprop_alloc(node, "ranges", sizeof(*range), (void **)&range);
538 * Make sure that the expected ranges are present. The
539 * OFW_PCI_CS_MEM64 one is not currently used though.
542 panic("%s: unsupported number of ranges", __func__);
544 * Find the addresses of the various bus spaces.
545 * There should not be multiple ones of one kind.
546 * The physical start addresses of the ranges are the configuration,
547 * memory and I/O handles.
549 for (i = 0; i < STX_NRANGE; i++) {
550 j = OFW_PCI_RANGE_CS(&range[i]);
551 if (sc->sc_pci_bh[j] != 0)
552 panic("%s: duplicate range for space %d",
554 sc->sc_pci_bh[j] = OFW_PCI_RANGE_PHYS(&range[i]);
556 free(range, M_OFWPROP);
558 /* Register the softc, this is needed for paired Schizos. */
559 SLIST_INSERT_HEAD(&schizo_softcs, sc, sc_link);
561 /* Allocate our tags. */
562 sc->sc_pci_memt = schizo_alloc_bus_tag(sc, PCI_MEMORY_BUS_SPACE);
563 sc->sc_pci_iot = schizo_alloc_bus_tag(sc, PCI_IO_BUS_SPACE);
564 sc->sc_pci_cfgt = schizo_alloc_bus_tag(sc, PCI_CONFIG_BUS_SPACE);
565 if (bus_dma_tag_create(bus_get_dma_tag(dev), 8, 0,
566 sc->sc_is.is_pmaxaddr, ~0, NULL, NULL, sc->sc_is.is_pmaxaddr,
567 0xff, 0xffffffff, 0, NULL, NULL, &sc->sc_pci_dmat) != 0)
568 panic("%s: bus_dma_tag_create failed", __func__);
569 /* Customize the tag. */
570 sc->sc_pci_dmat->dt_cookie = &sc->sc_is;
571 sc->sc_pci_dmat->dt_mt = &iommu_dma_methods;
574 * Get the bus range from the firmware.
575 * NB: Tomatillos don't support PCI bus reenumeration.
577 i = OF_getprop(node, "bus-range", (void *)prop_array,
580 panic("%s: could not get bus-range", __func__);
581 if (i != sizeof(prop_array))
582 panic("%s: broken bus-range (%d)", __func__, i);
583 sc->sc_pci_secbus = prop_array[0];
584 sc->sc_pci_subbus = prop_array[1];
586 device_printf(dev, "bus range %u to %u; PCI bus %d\n",
587 sc->sc_pci_secbus, sc->sc_pci_subbus, sc->sc_pci_secbus);
589 /* Clear any pending PCI error bits. */
590 PCIB_WRITE_CONFIG(dev, sc->sc_pci_secbus, STX_CS_DEVICE, STX_CS_FUNC,
591 PCIR_STATUS, PCIB_READ_CONFIG(dev, sc->sc_pci_secbus,
592 STX_CS_DEVICE, STX_CS_FUNC, PCIR_STATUS, 2), 2);
593 SCHIZO_PCI_WRITE_8(sc, STX_PCI_CTRL,
594 SCHIZO_PCI_READ_8(sc, STX_PCI_CTRL));
595 SCHIZO_PCI_WRITE_8(sc, STX_PCI_AFSR,
596 SCHIZO_PCI_READ_8(sc, STX_PCI_AFSR));
599 * Establish handlers for interesting interrupts...
600 * Someone at Sun clearly was smoking crack; with Schizos PCI
601 * bus error interrupts for one PBM can be routed to the other
602 * PBM though we obviously need to use the softc of the former
603 * as the argument for the interrupt handler and the softc of
604 * the latter as the argument for the interrupt controller.
606 if (sc->sc_half == 0) {
607 if ((ino_bitmap & (1ULL << STX_PCIERR_A_INO)) != 0 ||
608 (osc != NULL && ((struct schizo_icarg *)intr_vectors[
609 INTMAP_VEC(sc->sc_ign, STX_PCIERR_A_INO)].iv_icarg)->
612 * We are the driver for PBM A and either also
613 * registered the interrupt controller for us or
614 * the driver for PBM B has probed first and
615 * registered it for us.
617 schizo_set_intr(sc, 0, STX_PCIERR_A_INO,
619 if ((ino_bitmap & (1ULL << STX_PCIERR_B_INO)) != 0 &&
622 * We are the driver for PBM A but registered
623 * the interrupt controller for PBM B, i.e. the
624 * driver for PBM B attached first but couldn't
625 * set up a handler for PBM B.
627 schizo_set_intr(osc, 0, STX_PCIERR_B_INO,
630 if ((ino_bitmap & (1ULL << STX_PCIERR_B_INO)) != 0 ||
631 (osc != NULL && ((struct schizo_icarg *)intr_vectors[
632 INTMAP_VEC(sc->sc_ign, STX_PCIERR_B_INO)].iv_icarg)->
635 * We are the driver for PBM B and either also
636 * registered the interrupt controller for us or
637 * the driver for PBM A has probed first and
638 * registered it for us.
640 schizo_set_intr(sc, 0, STX_PCIERR_B_INO,
642 if ((ino_bitmap & (1ULL << STX_PCIERR_A_INO)) != 0 &&
645 * We are the driver for PBM B but registered
646 * the interrupt controller for PBM A, i.e. the
647 * driver for PBM A attached first but couldn't
648 * set up a handler for PBM A.
650 schizo_set_intr(osc, 0, STX_PCIERR_A_INO,
653 if ((ino_bitmap & (1ULL << STX_UE_INO)) != 0)
654 schizo_set_intr(sc, 1, STX_UE_INO, schizo_ue);
655 if ((ino_bitmap & (1ULL << STX_CE_INO)) != 0)
656 schizo_set_intr(sc, 2, STX_CE_INO, schizo_ce);
657 if ((ino_bitmap & (1ULL << STX_BUS_INO)) != 0)
658 schizo_set_intr(sc, 3, STX_BUS_INO, schizo_host_bus);
661 * According to the Schizo Errata I-13, consistent DMA flushing/
662 * syncing is FUBAR in version < 5 (i.e. revision < 2.3) bridges,
663 * so we can't use it and need to live with the consequences. With
664 * Schizo version >= 5, CDMA flushing/syncing is usable but requires
665 * the workaround described in Schizo Errata I-23. With Tomatillo
666 * and XMITS, CDMA flushing/syncing works as expected, Tomatillo
667 * version <= 4 (i.e. revision <= 2.3) bridges additionally require
668 * a block store after a write to TOMXMS_PCI_DMA_SYNC_PEND though.
670 if ((sc->sc_mode == SCHIZO_MODE_SCZ && sc->sc_ver >= 5) ||
671 sc->sc_mode == SCHIZO_MODE_TOM ||
672 sc->sc_mode == SCHIZO_MODE_XMS) {
673 sc->sc_flags |= SCHIZO_FLAGS_CDMA;
674 if (sc->sc_mode == SCHIZO_MODE_SCZ) {
675 sc->sc_cdma_state = SCHIZO_CDMA_STATE_DONE;
677 * Some firmware versions include the CDMA interrupt
678 * at RID 4 but most don't. With the latter we add
679 * it ourselves at the spare RID 5.
681 i = INTINO(bus_get_resource_start(dev, SYS_RES_IRQ,
683 if (i == STX_CDMA_A_INO || i == STX_CDMA_B_INO) {
684 (void)schizo_get_intrmap(sc, i, NULL,
686 schizo_set_intr(sc, 4, i, schizo_cdma);
688 i = STX_CDMA_A_INO + sc->sc_half;
689 if (bus_set_resource(dev, SYS_RES_IRQ, 5,
690 INTMAP_VEC(sc->sc_ign, i), 1) != 0)
691 panic("%s: failed to add CDMA "
692 "interrupt", __func__);
693 j = schizo_intr_register(sc, i);
695 panic("%s: could not register "
696 "interrupt controller for CDMA "
697 "(%d)", __func__, j);
698 (void)schizo_get_intrmap(sc, i, NULL,
700 schizo_set_intr(sc, 5, i, schizo_cdma);
703 if (sc->sc_mode == SCHIZO_MODE_TOM && sc->sc_ver <= 4)
704 sc->sc_flags |= SCHIZO_FLAGS_BSWAR;
708 * Set the latency timer register as this isn't always done by the
711 PCIB_WRITE_CONFIG(dev, sc->sc_pci_secbus, STX_CS_DEVICE, STX_CS_FUNC,
712 PCIR_LATTIMER, OFW_PCI_LATENCY, 1);
714 ofw_bus_setup_iinfo(node, &sc->sc_pci_iinfo, sizeof(ofw_pci_intr_t));
716 #define SCHIZO_SYSCTL_ADD_UINT(name, arg, desc) \
717 SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev), \
718 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, \
719 (name), CTLFLAG_RD, (arg), 0, (desc))
721 SCHIZO_SYSCTL_ADD_UINT("dma_ce", &sc->sc_stats_dma_ce,
722 "DMA correctable errors");
723 SCHIZO_SYSCTL_ADD_UINT("pci_non_fatal", &sc->sc_stats_pci_non_fatal,
724 "PCI bus non-fatal errors");
726 #undef SCHIZO_SYSCTL_ADD_UINT
728 device_add_child(dev, "pci", -1);
729 return (bus_generic_attach(dev));
733 schizo_set_intr(struct schizo_softc *sc, u_int index, u_int ino,
734 driver_filter_t handler)
740 sc->sc_irq_res[index] = bus_alloc_resource_any(sc->sc_dev,
741 SYS_RES_IRQ, &rid, RF_ACTIVE);
742 if (sc->sc_irq_res[index] == NULL ||
743 INTINO(vec = rman_get_start(sc->sc_irq_res[index])) != ino ||
744 INTIGN(vec) != sc->sc_ign ||
745 intr_vectors[vec].iv_ic != &schizo_ic ||
746 bus_setup_intr(sc->sc_dev, sc->sc_irq_res[index],
747 INTR_TYPE_MISC | INTR_FAST, handler, NULL, sc,
748 &sc->sc_ihand[index]) != 0)
749 panic("%s: failed to set up interrupt %d", __func__, index);
753 schizo_intr_register(struct schizo_softc *sc, u_int ino)
755 struct schizo_icarg *sica;
756 bus_addr_t intrclr, intrmap;
759 if (schizo_get_intrmap(sc, ino, &intrmap, &intrclr) == 0)
761 sica = malloc(sizeof(*sica), M_DEVBUF, M_NOWAIT);
765 sica->sica_map = intrmap;
766 sica->sica_clr = intrclr;
768 device_printf(sc->sc_dev, "intr map (INO %d) %#lx: %#lx, clr: %#lx\n",
769 ino, (u_long)intrmap, (u_long)SCHIZO_PCI_READ_8(sc, intrmap),
772 error = (intr_controller_register(INTMAP_VEC(sc->sc_ign, ino),
775 free(sica, M_DEVBUF);
780 schizo_get_intrmap(struct schizo_softc *sc, u_int ino,
781 bus_addr_t *intrmapptr, bus_addr_t *intrclrptr)
783 bus_addr_t intrclr, intrmap;
787 * XXX we only look for INOs rather than INRs since the firmware
788 * may not provide the IGN and the IGN is constant for all devices
789 * on that PCI controller.
792 if (ino > STX_MAX_INO) {
793 device_printf(sc->sc_dev, "out of range INO %d requested\n",
798 intrmap = STX_PCI_IMAP_BASE + (ino << 3);
799 intrclr = STX_PCI_ICLR_BASE + (ino << 3);
800 mr = SCHIZO_PCI_READ_8(sc, intrmap);
801 if (INTINO(mr) != ino) {
802 device_printf(sc->sc_dev,
803 "interrupt map entry does not match INO (%d != %d)\n",
804 (int)INTINO(mr), ino);
808 if (intrmapptr != NULL)
809 *intrmapptr = intrmap;
810 if (intrclrptr != NULL)
811 *intrclrptr = intrclr;
819 schizo_pci_bus(void *arg)
821 struct schizo_softc *sc = arg;
822 uint64_t afar, afsr, csr, iommu;
828 mtx_lock_spin(sc->sc_mtx);
830 afar = SCHIZO_PCI_READ_8(sc, STX_PCI_AFAR);
831 afsr = SCHIZO_PCI_READ_8(sc, STX_PCI_AFSR);
832 csr = SCHIZO_PCI_READ_8(sc, STX_PCI_CTRL);
833 iommu = SCHIZO_PCI_READ_8(sc, STX_PCI_IOMMU);
834 status = PCIB_READ_CONFIG(sc->sc_dev, sc->sc_pci_secbus,
835 STX_CS_DEVICE, STX_CS_FUNC, PCIR_STATUS, 2);
838 * IOMMU errors are only fatal on Tomatillo and there also only if
839 * target abort was not signaled.
841 if ((csr & STX_PCI_CTRL_MMU_ERR) != 0 &&
842 (iommu & TOM_PCI_IOMMU_ERR) != 0 &&
843 ((status & PCIM_STATUS_STABORT) == 0 ||
844 ((iommu & TOM_PCI_IOMMU_ERRMASK) != TOM_PCI_IOMMU_INVALID_ERR &&
845 (iommu & TOM_PCI_IOMMU_ERR_ILLTSBTBW) == 0 &&
846 (iommu & TOM_PCI_IOMMU_ERR_BAD_VA) == 0)))
848 else if ((status & PCIM_STATUS_STABORT) != 0)
850 if ((status & (PCIM_STATUS_PERR | PCIM_STATUS_SERR |
851 PCIM_STATUS_RMABORT | PCIM_STATUS_RTABORT |
852 PCIM_STATUS_PERRREPORT)) != 0 ||
853 (csr & (SCZ_PCI_CTRL_BUS_UNUS | TOM_PCI_CTRL_DTO_ERR |
854 STX_PCI_CTRL_TTO_ERR | STX_PCI_CTRL_RTRY_ERR |
855 SCZ_PCI_CTRL_SBH_ERR | STX_PCI_CTRL_SERR)) != 0 ||
856 (afsr & (STX_PCI_AFSR_P_MA | STX_PCI_AFSR_P_TA |
857 STX_PCI_AFSR_P_RTRY | STX_PCI_AFSR_P_PERR | STX_PCI_AFSR_P_TTO |
858 STX_PCI_AFSR_P_UNUS)) != 0)
861 sc->sc_stats_pci_non_fatal++;
863 device_printf(sc->sc_dev, "PCI bus %c error AFAR %#llx AFSR %#llx "
864 "PCI CSR %#llx IOMMU %#llx STATUS %#llx\n", 'A' + sc->sc_half,
865 (unsigned long long)afar, (unsigned long long)afsr,
866 (unsigned long long)csr, (unsigned long long)iommu,
867 (unsigned long long)status);
869 /* Clear the error bits that we caught. */
870 PCIB_WRITE_CONFIG(sc->sc_dev, sc->sc_pci_secbus, STX_CS_DEVICE,
871 STX_CS_FUNC, PCIR_STATUS, status, 2);
872 SCHIZO_PCI_WRITE_8(sc, STX_PCI_CTRL, csr);
873 SCHIZO_PCI_WRITE_8(sc, STX_PCI_AFSR, afsr);
874 SCHIZO_PCI_WRITE_8(sc, STX_PCI_IOMMU, iommu);
876 mtx_unlock_spin(sc->sc_mtx);
879 panic("%s: fatal PCI bus error",
880 device_get_nameunit(sc->sc_dev));
881 return (FILTER_HANDLED);
887 struct schizo_softc *sc = arg;
891 afar = SCHIZO_CTRL_READ_8(sc, STX_CTRL_UE_AFAR);
892 for (i = 0; i < 1000; i++)
893 if (((afsr = SCHIZO_CTRL_READ_8(sc, STX_CTRL_UE_AFSR)) &
894 STX_CTRL_CE_AFSR_ERRPNDG) == 0)
896 panic("%s: uncorrectable DMA error AFAR %#llx AFSR %#llx",
897 device_get_nameunit(sc->sc_dev), (unsigned long long)afar,
898 (unsigned long long)afsr);
899 return (FILTER_HANDLED);
905 struct schizo_softc *sc = arg;
909 mtx_lock_spin(sc->sc_mtx);
911 afar = SCHIZO_CTRL_READ_8(sc, STX_CTRL_CE_AFAR);
912 for (i = 0; i < 1000; i++)
913 if (((afsr = SCHIZO_CTRL_READ_8(sc, STX_CTRL_UE_AFSR)) &
914 STX_CTRL_CE_AFSR_ERRPNDG) == 0)
916 sc->sc_stats_dma_ce++;
917 device_printf(sc->sc_dev,
918 "correctable DMA error AFAR %#llx AFSR %#llx\n",
919 (unsigned long long)afar, (unsigned long long)afsr);
921 /* Clear the error bits that we caught. */
922 SCHIZO_CTRL_WRITE_8(sc, STX_CTRL_UE_AFSR, afsr);
924 mtx_unlock_spin(sc->sc_mtx);
926 return (FILTER_HANDLED);
930 schizo_host_bus(void *arg)
932 struct schizo_softc *sc = arg;
935 errlog = SCHIZO_CTRL_READ_8(sc, STX_CTRL_BUS_ERRLOG);
936 panic("%s: %s error %#llx", device_get_nameunit(sc->sc_dev),
937 sc->sc_mode == SCHIZO_MODE_TOM ? "JBus" : "Safari",
938 (unsigned long long)errlog);
939 return (FILTER_HANDLED);
943 schizo_cdma(void *arg)
945 struct schizo_softc *sc = arg;
947 atomic_store_rel_32(&sc->sc_cdma_state, SCHIZO_CDMA_STATE_DONE);
948 return (FILTER_HANDLED);
952 schizo_iommu_init(struct schizo_softc *sc, int tsbsize, uint32_t dvmabase)
955 /* Punch in our copies. */
956 sc->sc_is.is_bustag = rman_get_bustag(sc->sc_mem_res[STX_PCI]);
957 sc->sc_is.is_bushandle = rman_get_bushandle(sc->sc_mem_res[STX_PCI]);
958 sc->sc_is.is_iommu = STX_PCI_IOMMU;
959 sc->sc_is.is_dtag = STX_PCI_IOMMU_TLB_TAG_DIAG;
960 sc->sc_is.is_ddram = STX_PCI_IOMMU_TLB_DATA_DIAG;
961 sc->sc_is.is_dqueue = STX_PCI_IOMMU_QUEUE_DIAG;
962 sc->sc_is.is_dva = STX_PCI_IOMMU_SVADIAG;
963 sc->sc_is.is_dtcmp = STX_PCI_IOMMU_TLB_CMP_DIAG;
965 iommu_init(device_get_nameunit(sc->sc_dev), &sc->sc_is, tsbsize,
970 schizo_maxslots(device_t dev)
972 struct schizo_softc *sc;
974 sc = device_get_softc(dev);
975 if (sc->sc_mode == SCHIZO_MODE_SCZ)
976 return (sc->sc_half == 0 ? 4 : 6);
978 /* XXX: is this correct? */
979 return (PCI_SLOTMAX);
983 schizo_read_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg,
986 struct schizo_softc *sc;
987 bus_space_handle_t bh;
994 sc = device_get_softc(dev);
995 if (bus < sc->sc_pci_secbus || bus > sc->sc_pci_subbus ||
996 slot > PCI_SLOTMAX || func > PCI_FUNCMAX || reg > PCI_REGMAX)
1000 * The Schizo bridges contain a dupe of their header at 0x80.
1002 if (sc->sc_mode == SCHIZO_MODE_SCZ && bus == sc->sc_pci_secbus &&
1003 slot == STX_CS_DEVICE && func == STX_CS_FUNC &&
1007 offset = STX_CONF_OFF(bus, slot, func, reg);
1008 bh = sc->sc_pci_bh[OFW_PCI_CS_CONFIG];
1011 i = bus_space_peek_1(sc->sc_pci_cfgt, bh, offset, &byte);
1015 i = bus_space_peek_2(sc->sc_pci_cfgt, bh, offset, &shrt);
1019 i = bus_space_peek_4(sc->sc_pci_cfgt, bh, offset, &wrd);
1023 panic("%s: bad width", __func__);
1029 printf("%s: read data error reading: %d.%d.%d: 0x%x\n",
1030 __func__, bus, slot, func, reg);
1038 schizo_write_config(device_t dev, u_int bus, u_int slot, u_int func,
1039 u_int reg, uint32_t val, int width)
1041 struct schizo_softc *sc;
1042 bus_space_handle_t bh;
1045 sc = device_get_softc(dev);
1046 if (bus < sc->sc_pci_secbus || bus > sc->sc_pci_subbus ||
1047 slot > PCI_SLOTMAX || func > PCI_FUNCMAX || reg > PCI_REGMAX)
1050 offset = STX_CONF_OFF(bus, slot, func, reg);
1051 bh = sc->sc_pci_bh[OFW_PCI_CS_CONFIG];
1054 bus_space_write_1(sc->sc_pci_cfgt, bh, offset, val);
1057 bus_space_write_2(sc->sc_pci_cfgt, bh, offset, val);
1060 bus_space_write_4(sc->sc_pci_cfgt, bh, offset, val);
1063 panic("%s: bad width", __func__);
1069 schizo_route_interrupt(device_t bridge, device_t dev, int pin)
1071 struct schizo_softc *sc;
1072 struct ofw_pci_register reg;
1073 ofw_pci_intr_t pintr, mintr;
1074 uint8_t maskbuf[sizeof(reg) + sizeof(pintr)];
1076 sc = device_get_softc(bridge);
1078 if (ofw_bus_lookup_imap(ofw_bus_get_node(dev), &sc->sc_pci_iinfo,
1079 ®, sizeof(reg), &pintr, sizeof(pintr), &mintr, sizeof(mintr),
1083 device_printf(bridge, "could not route pin %d for device %d.%d\n",
1084 pin, pci_get_slot(dev), pci_get_function(dev));
1085 return (PCI_INVALID_IRQ);
1089 schizo_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
1091 struct schizo_softc *sc;
1093 sc = device_get_softc(dev);
1095 case PCIB_IVAR_DOMAIN:
1096 *result = device_get_unit(dev);
1099 *result = sc->sc_pci_secbus;
1106 schizo_dma_sync_stub(void *arg)
1108 struct timeval cur, end;
1109 struct schizo_dma_sync *sds = arg;
1110 struct schizo_softc *sc = sds->sds_sc;
1113 (void)PCIB_READ_CONFIG(sds->sds_ppb, sds->sds_bus, sds->sds_slot,
1114 sds->sds_func, PCIR_VENDOR, 2);
1115 for (; atomic_cmpset_acq_32(&sc->sc_cdma_state,
1116 SCHIZO_CDMA_STATE_DONE, SCHIZO_CDMA_STATE_PENDING) == 0;)
1118 SCHIZO_PCI_WRITE_8(sc, sc->sc_cdma_clr, INTCLR_RECEIVED);
1122 timevaladd(&end, &cur);
1123 for (; (state = atomic_load_32(&sc->sc_cdma_state)) !=
1124 SCHIZO_CDMA_STATE_DONE && timevalcmp(&cur, &end, <=);)
1126 if (state != SCHIZO_CDMA_STATE_DONE)
1127 panic("%s: DMA does not sync", __func__);
1128 return (sds->sds_handler(sds->sds_arg));
1131 #define VIS_BLOCKSIZE 64
1134 ichip_dma_sync_stub(void *arg)
1136 static u_char buf[VIS_BLOCKSIZE] __aligned(VIS_BLOCKSIZE);
1137 struct timeval cur, end;
1138 struct schizo_dma_sync *sds = arg;
1139 struct schizo_softc *sc = sds->sds_sc;
1142 (void)PCIB_READ_CONFIG(sds->sds_ppb, sds->sds_bus, sds->sds_slot,
1143 sds->sds_func, PCIR_VENDOR, 2);
1144 SCHIZO_PCI_WRITE_8(sc, TOMXMS_PCI_DMA_SYNC_PEND, sds->sds_syncval);
1148 timevaladd(&end, &cur);
1149 for (; ((reg = SCHIZO_PCI_READ_8(sc, TOMXMS_PCI_DMA_SYNC_PEND)) &
1150 sds->sds_syncval) != 0 && timevalcmp(&cur, &end, <=);)
1152 if ((reg & sds->sds_syncval) != 0)
1153 panic("%s: DMA does not sync", __func__);
1155 if ((sc->sc_flags & SCHIZO_FLAGS_BSWAR) != 0) {
1158 wr(fprs, reg | FPRS_FEF, 0);
1159 __asm __volatile("stda %%f0, [%0] %1"
1160 : : "r" (buf), "n" (ASI_BLK_COMMIT_S));
1165 return (sds->sds_handler(sds->sds_arg));
1169 schizo_intr_enable(void *arg)
1171 struct intr_vector *iv = arg;
1172 struct schizo_icarg *sica = iv->iv_icarg;
1174 SCHIZO_PCI_WRITE_8(sica->sica_sc, sica->sica_map,
1175 INTMAP_ENABLE(iv->iv_vec, iv->iv_mid));
1179 schizo_intr_disable(void *arg)
1181 struct intr_vector *iv = arg;
1182 struct schizo_icarg *sica = iv->iv_icarg;
1184 SCHIZO_PCI_WRITE_8(sica->sica_sc, sica->sica_map, iv->iv_vec);
1188 schizo_intr_assign(void *arg)
1190 struct intr_vector *iv = arg;
1191 struct schizo_icarg *sica = iv->iv_icarg;
1193 SCHIZO_PCI_WRITE_8(sica->sica_sc, sica->sica_map, INTMAP_TID(
1194 SCHIZO_PCI_READ_8(sica->sica_sc, sica->sica_map), iv->iv_mid));
1198 schizo_intr_clear(void *arg)
1200 struct intr_vector *iv = arg;
1201 struct schizo_icarg *sica = iv->iv_icarg;
1203 SCHIZO_PCI_WRITE_8(sica->sica_sc, sica->sica_clr, INTCLR_IDLE);
1207 schizo_setup_intr(device_t dev, device_t child, struct resource *ires,
1208 int flags, driver_filter_t *filt, driver_intr_t *intr, void *arg,
1211 devclass_t pci_devclass;
1212 device_t cdev, pdev, pcidev;
1213 struct schizo_dma_sync *sds;
1214 struct schizo_softc *sc;
1218 sc = device_get_softc(dev);
1220 * Make sure the vector is fully specified.
1222 vec = rman_get_start(ires);
1223 if (INTIGN(vec) != sc->sc_ign) {
1224 device_printf(dev, "invalid interrupt vector 0x%lx\n", vec);
1228 if (intr_vectors[vec].iv_ic == &schizo_ic) {
1230 * Ensure we use the right softc in case the interrupt
1231 * is routed to our companion PBM for some odd reason.
1233 sc = ((struct schizo_icarg *)intr_vectors[vec].iv_icarg)->
1235 } else if (intr_vectors[vec].iv_ic == NULL) {
1237 * Work around broken firmware which misses entries in
1240 error = schizo_intr_register(sc, INTINO(vec));
1242 device_printf(dev, "could not register interrupt "
1243 "controller for vector 0x%lx (%d)\n", vec, error);
1247 device_printf(dev, "belatedly registered as "
1248 "interrupt controller for vector 0x%lx\n", vec);
1251 "invalid interrupt controller for vector 0x%lx\n", vec);
1256 * Install a a wrapper for CDMA flushing/syncing for devices
1257 * behind PCI-PCI bridges if possible.
1261 pci_devclass = devclass_find("pci");
1262 for (cdev = child; cdev != dev; cdev = pdev) {
1263 pdev = device_get_parent(cdev);
1264 if (pcidev == NULL) {
1265 if (device_get_devclass(pdev) != pci_devclass)
1270 if (pci_get_class(cdev) == PCIC_BRIDGE &&
1271 pci_get_subclass(cdev) == PCIS_BRIDGE_PCI)
1274 if ((sc->sc_flags & SCHIZO_FLAGS_CDMA) != 0) {
1275 sds = malloc(sizeof(*sds), M_DEVBUF, M_NOWAIT | M_ZERO);
1278 if (found != 0 && pcidev != NULL) {
1282 device_get_parent(device_get_parent(pcidev));
1283 sds->sds_bus = pci_get_bus(pcidev);
1284 sds->sds_slot = pci_get_slot(pcidev);
1285 sds->sds_func = pci_get_function(pcidev);
1286 sds->sds_syncval = 1ULL << INTINO(vec);
1288 device_printf(dev, "installed DMA sync "
1289 "wrapper for device %d.%d on bus %d\n",
1290 sds->sds_slot, sds->sds_func,
1293 #define DMA_SYNC_STUB \
1294 (sc->sc_mode == SCHIZO_MODE_SCZ ? schizo_dma_sync_stub : \
1295 ichip_dma_sync_stub)
1298 sds->sds_handler = filt;
1299 error = bus_generic_setup_intr(dev, child,
1300 ires, flags, DMA_SYNC_STUB, intr, sds,
1303 sds->sds_handler = (driver_filter_t *)intr;
1304 error = bus_generic_setup_intr(dev, child,
1305 ires, flags, filt, (driver_intr_t *)
1306 DMA_SYNC_STUB, sds, cookiep);
1309 #undef DMA_SYNC_STUB
1312 error = bus_generic_setup_intr(dev, child, ires,
1313 flags, filt, intr, arg, cookiep);
1315 free(sds, M_DEVBUF);
1318 sds->sds_cookie = *cookiep;
1321 } else if (found != 0)
1322 device_printf(dev, "WARNING: using devices behind PCI-PCI "
1323 "bridges may cause data corruption\n");
1324 return (bus_generic_setup_intr(dev, child, ires, flags, filt, intr,
1329 schizo_teardown_intr(device_t dev, device_t child, struct resource *vec,
1332 struct schizo_dma_sync *sds;
1333 struct schizo_softc *sc;
1336 sc = device_get_softc(dev);
1337 if ((sc->sc_flags & SCHIZO_FLAGS_CDMA) != 0) {
1339 error = bus_generic_teardown_intr(dev, child, vec,
1342 free(sds, M_DEVBUF);
1345 return (bus_generic_teardown_intr(dev, child, vec, cookie));
1349 schizo_describe_intr(device_t dev, device_t child, struct resource *vec,
1350 void *cookie, const char *descr)
1352 struct schizo_softc *sc;
1354 sc = device_get_softc(dev);
1355 if ((sc->sc_flags & SCHIZO_FLAGS_CDMA) != 0)
1356 cookie = ((struct schizo_dma_sync *)cookie)->sds_cookie;
1357 return (bus_generic_describe_intr(dev, child, vec, cookie, descr));
1360 static struct resource *
1361 schizo_alloc_resource(device_t bus, device_t child, int type, int *rid,
1362 u_long start, u_long end, u_long count, u_int flags)
1364 struct schizo_softc *sc;
1365 struct resource *rv;
1368 bus_space_handle_t bh;
1369 int needactivate = flags & RF_ACTIVE;
1371 flags &= ~RF_ACTIVE;
1373 sc = device_get_softc(bus);
1374 if (type == SYS_RES_IRQ) {
1376 * XXX: Don't accept blank ranges for now, only single
1377 * interrupts. The other case should not happen with
1378 * the MI PCI code...
1379 * XXX: This may return a resource that is out of the
1380 * range that was specified. Is this correct...?
1383 panic("%s: XXX: interrupt range", __func__);
1384 start = end = INTMAP_VEC(sc->sc_ign, end);
1385 return (BUS_ALLOC_RESOURCE(device_get_parent(bus), child,
1386 type, rid, start, end, count, flags));
1389 case SYS_RES_MEMORY:
1390 rm = &sc->sc_pci_mem_rman;
1391 bt = sc->sc_pci_memt;
1392 bh = sc->sc_pci_bh[OFW_PCI_CS_MEM32];
1394 case SYS_RES_IOPORT:
1395 rm = &sc->sc_pci_io_rman;
1396 bt = sc->sc_pci_iot;
1397 bh = sc->sc_pci_bh[OFW_PCI_CS_IO];
1404 rv = rman_reserve_resource(rm, start, end, count, flags, child);
1407 rman_set_rid(rv, *rid);
1408 bh += rman_get_start(rv);
1409 rman_set_bustag(rv, bt);
1410 rman_set_bushandle(rv, bh);
1413 if (bus_activate_resource(child, type, *rid, rv)) {
1414 rman_release_resource(rv);
1422 schizo_activate_resource(device_t bus, device_t child, int type, int rid,
1428 if (type == SYS_RES_IRQ)
1429 return (BUS_ACTIVATE_RESOURCE(device_get_parent(bus), child,
1431 if (type == SYS_RES_MEMORY) {
1433 * Need to memory-map the device space, as some drivers
1434 * depend on the virtual address being set and usable.
1436 error = sparc64_bus_mem_map(rman_get_bustag(r),
1437 rman_get_bushandle(r), rman_get_size(r), 0, 0, &p);
1440 rman_set_virtual(r, p);
1442 return (rman_activate_resource(r));
1446 schizo_deactivate_resource(device_t bus, device_t child, int type, int rid,
1450 if (type == SYS_RES_IRQ)
1451 return (BUS_DEACTIVATE_RESOURCE(device_get_parent(bus), child,
1453 if (type == SYS_RES_MEMORY) {
1454 sparc64_bus_mem_unmap(rman_get_virtual(r), rman_get_size(r));
1455 rman_set_virtual(r, NULL);
1457 return (rman_deactivate_resource(r));
1461 schizo_release_resource(device_t bus, device_t child, int type, int rid,
1466 if (type == SYS_RES_IRQ)
1467 return (BUS_RELEASE_RESOURCE(device_get_parent(bus), child,
1469 if (rman_get_flags(r) & RF_ACTIVE) {
1470 error = bus_deactivate_resource(child, type, rid, r);
1474 return (rman_release_resource(r));
1477 static bus_dma_tag_t
1478 schizo_get_dma_tag(device_t bus, device_t child)
1480 struct schizo_softc *sc;
1482 sc = device_get_softc(bus);
1483 return (sc->sc_pci_dmat);
1487 schizo_get_node(device_t bus, device_t dev)
1489 struct schizo_softc *sc;
1491 sc = device_get_softc(bus);
1492 /* We only have one child, the PCI bus, which needs our own node. */
1493 return (sc->sc_node);
1496 static bus_space_tag_t
1497 schizo_alloc_bus_tag(struct schizo_softc *sc, int type)
1501 bt = malloc(sizeof(struct bus_space_tag), M_DEVBUF,
1504 panic("%s: out of memory", __func__);
1506 bt->bst_cookie = sc;
1507 bt->bst_parent = rman_get_bustag(sc->sc_mem_res[STX_PCI]);
1508 bt->bst_type = type;
1513 schizo_get_timecount(struct timecounter *tc)
1515 struct schizo_softc *sc;
1518 return (SCHIZO_CTRL_READ_8(sc, STX_CTRL_PERF_CNT) &
1519 (STX_CTRL_PERF_CNT_MASK << STX_CTRL_PERF_CNT_CNT0_SHIFT));